Merge https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
diff --git a/arch/arm/cpu/arm1136/mx35/generic.c b/arch/arm/cpu/arm1136/mx35/generic.c
index cbc4364..a651b8c 100644
--- a/arch/arm/cpu/arm1136/mx35/generic.c
+++ b/arch/arm/cpu/arm1136/mx35/generic.c
@@ -14,8 +14,8 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
 #endif
 #include <netdev.h>
 #include <spl.h>
@@ -27,7 +27,7 @@
 
 #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
@@ -446,7 +446,7 @@
 	return rc;
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 /*
  * Initializes on-chip MMC controllers.
  * to override, implement board_mmc_init()
@@ -459,7 +459,7 @@
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index 2795a5f..5fcf06a 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -16,8 +16,8 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 #endif
@@ -233,7 +233,7 @@
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #else
@@ -243,7 +243,7 @@
 	return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 /*
  * Initializes on-chip MMC controllers.
  * to override, implement board_mmc_init()
diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c
index f962903..337f4af 100644
--- a/arch/arm/cpu/armv7/vf610/generic.c
+++ b/arch/arm/cpu/armv7/vf610/generic.c
@@ -10,11 +10,11 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/mach-imx/sys_proto.h>
 #include <netdev.h>
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
@@ -345,7 +345,7 @@
 	return rc;
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 int cpu_mmc_init(bd_t *bis)
 {
 	return fsl_esdhc_mmc_init(bis);
@@ -354,7 +354,7 @@
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 #endif
 	return 0;
diff --git a/arch/arm/cpu/armv8/s32v234/generic.c b/arch/arm/cpu/armv8/s32v234/generic.c
index 273b88e..2c4ea36 100644
--- a/arch/arm/cpu/armv8/s32v234/generic.c
+++ b/arch/arm/cpu/armv8/s32v234/generic.c
@@ -342,7 +342,7 @@
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
 #endif
 	return 0;
diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts
index c0708fe..7f0d169 100644
--- a/arch/arm/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/dts/at91-sama5d2_xplained.dts
@@ -79,26 +79,18 @@
 			};
 
 			qspi0: spi@f0020000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_qspi0_sck_cs_default &pinctrl_qspi0_dat_default>;
 				status = "okay";
+				u-boot,dm-pre-reloc;
 
 				flash@0 {
-					compatible = "atmel,sama5d2-qspi-flash";
+					compatible = "jedec,spi-nor";
 					reg = <0>;
-					#address-cells = <1>;
-					#size-cells = <1>;
-					pinctrl-names = "default";
-					pinctrl-0 = <&pinctrl_qspi0_default>;
 					spi-max-frequency = <83000000>;
-
-					partition@00000000 {
-						label = "boot";
-						reg = <0x00000000 0x00c00000>;
-					};
-
-					partition@00c00000 {
-						label = "rootfs";
-						reg = <0x00c00000 0x00000000>;
-					};
+					spi-rx-bus-width = <4>;
+					spi-tx-bus-width = <4>;
+					u-boot,dm-pre-reloc;
 				};
 			};
 
@@ -208,14 +200,20 @@
 						bias-disable;
 					};
 
-					pinctrl_qspi0_default: qspi0_default {
+					pinctrl_qspi0_sck_cs_default: qspi0_sck_cs_default {
 						pinmux = <PIN_PA22__QSPI0_SCK>,
-							 <PIN_PA23__QSPI0_CS>,
-							 <PIN_PA24__QSPI0_IO0>,
+							 <PIN_PA23__QSPI0_CS>;
+						bias-disable;
+						u-boot,dm-pre-reloc;
+					};
+
+					pinctrl_qspi0_dat_default: qspi0_dat_default {
+						pinmux = <PIN_PA24__QSPI0_IO0>,
 							 <PIN_PA25__QSPI0_IO1>,
 							 <PIN_PA26__QSPI0_IO2>,
 							 <PIN_PA27__QSPI0_IO3>;
-						bias-disable;
+						bias-pull-up;
+						u-boot,dm-pre-reloc;
 					};
 
 					pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
diff --git a/arch/arm/include/asm/arch-meson/eth.h b/arch/arm/include/asm/arch-meson/eth.h
index 08acc5c..f765cd7 100644
--- a/arch/arm/include/asm/arch-meson/eth.h
+++ b/arch/arm/include/asm/arch-meson/eth.h
@@ -19,4 +19,7 @@
  */
 void meson_eth_init(phy_interface_t mode, unsigned int flags);
 
+/* Generate an unique MAC address based on the HW serial */
+int meson_generate_serial_ethaddr(void);
+
 #endif /* __MESON_ETH_H__ */
diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h
index 83d6441..60d04ae 100644
--- a/arch/arm/include/asm/arch-meson/sm.h
+++ b/arch/arm/include/asm/arch-meson/sm.h
@@ -8,4 +8,8 @@
 
 ssize_t meson_sm_read_efuse(uintptr_t offset, void *buffer, size_t size);
 
+#define SM_SERIAL_SIZE	12
+
+int meson_sm_get_serial(void *buffer, size_t size);
+
 #endif /* __MESON_SM_H__ */
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index a81b106..1774014 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -9,7 +9,7 @@
 
 /* Architecture-specific global data */
 struct arch_global_data {
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_FSL_ESDHC_IMX)
 	u32 sdhc_clk;
 #endif
 
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index d62ff6e..3a8cf30 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -21,8 +21,8 @@
 #include <thermal.h>
 #include <sata.h>
 
-#ifdef CONFIG_FSL_ESDHC
-#include <fsl_esdhc.h>
+#ifdef CONFIG_FSL_ESDHC_IMX
+#include <fsl_esdhc_imx.h>
 #endif
 
 static u32 reset_cause = -1;
@@ -258,7 +258,7 @@
 	return rc;
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 /*
  * Initializes on-chip MMC controllers.
  * to override, implement board_mmc_init()
diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c
index c332d68..4f4df74 100644
--- a/arch/arm/mach-imx/mx6/litesom.c
+++ b/arch/arm/mach-imx/mx6/litesom.c
@@ -16,7 +16,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/io.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/sizes.h>
 #include <mmc.h>
 
@@ -49,7 +49,7 @@
 	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 static struct fsl_esdhc_cfg emmc_cfg = {USDHC2_BASE_ADDR, 0, 8};
 
 #define EMMC_PWR_GPIO	IMX_GPIO_NR(4, 10)
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index e364b16..4f9724c 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -19,13 +19,13 @@
 					 ANATOP_BASE_ADDR;
 struct mxc_ccm_reg *ccm_reg = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index fac9011..dc317fe 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -14,7 +14,7 @@
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 #elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
index ab134d0..f9e486c 100644
--- a/arch/arm/mach-imx/speed.c
+++ b/arch/arm/mach-imx/speed.c
@@ -11,13 +11,13 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/clock.h>
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 int get_clocks(void)
 {
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 #ifdef CONFIG_FSL_USDHC
 #if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
 	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
diff --git a/arch/arm/mach-meson/board-common.c b/arch/arm/mach-meson/board-common.c
index 8c41301..18383f7 100644
--- a/arch/arm/mach-meson/board-common.c
+++ b/arch/arm/mach-meson/board-common.c
@@ -7,6 +7,7 @@
 #include <asm/arch/boot.h>
 #include <linux/libfdt.h>
 #include <linux/err.h>
+#include <environment.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sm.h>
 #include <asm/armv8/mmu.h>
@@ -67,6 +68,36 @@
 	}
 }
 
+int meson_generate_serial_ethaddr(void)
+{
+	u8 mac_addr[ARP_HLEN];
+	char serial[SM_SERIAL_SIZE];
+	u32 sid;
+	u16 sid16;
+
+	if (!meson_sm_get_serial(serial, SM_SERIAL_SIZE)) {
+		sid = crc32(0, (unsigned char *)serial, SM_SERIAL_SIZE);
+		sid16 = crc16_ccitt(0, (unsigned char *)serial,	SM_SERIAL_SIZE);
+
+		/* Ensure the NIC specific bytes of the mac are not all 0 */
+		if ((sid & 0xffffff) == 0)
+			sid |= 0x800000;
+
+		/* Non OUI / registered MAC address */
+		mac_addr[0] = ((sid16 >> 8) & 0xfc) | 0x02;
+		mac_addr[1] = (sid16 >>  0) & 0xff;
+		mac_addr[2] = (sid >> 24) & 0xff;
+		mac_addr[3] = (sid >> 16) & 0xff;
+		mac_addr[4] = (sid >>  8) & 0xff;
+		mac_addr[5] = (sid >>  0) & 0xff;
+
+		eth_env_set_enetaddr("ethaddr", mac_addr);
+	} else
+		return -EINVAL;
+
+	return 0;
+}
+
 static void meson_set_boot_source(void)
 {
 	const char *source;
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index a07b468..05b7f0b 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -6,12 +6,14 @@
  */
 
 #include <common.h>
+#include <asm/arch/sm.h>
 #include <linux/kernel.h>
 
 #define FN_GET_SHARE_MEM_INPUT_BASE	0x82000020
 #define FN_GET_SHARE_MEM_OUTPUT_BASE	0x82000021
 #define FN_EFUSE_READ			0x82000030
 #define FN_EFUSE_WRITE			0x82000031
+#define FN_CHIP_ID			0x82000044
 
 static void *shmem_input;
 static void *shmem_output;
@@ -53,3 +55,25 @@
 
 	return regs.regs[0];
 }
+
+#define SM_CHIP_ID_LENGTH	119
+#define SM_CHIP_ID_OFFSET	4
+#define SM_CHIP_ID_SIZE		12
+
+int meson_sm_get_serial(void *buffer, size_t size)
+{
+	struct pt_regs regs;
+
+	meson_init_shmem();
+
+	regs.regs[0] = FN_CHIP_ID;
+	regs.regs[1] = 0;
+	regs.regs[2] = 0;
+
+	smc_call(&regs);
+
+	memcpy(buffer, shmem_output + SM_CHIP_ID_OFFSET,
+	       min_t(size_t, size, SM_CHIP_ID_SIZE));
+
+	return 0;
+}
diff --git a/arch/m68k/cpu/mcf5445x/cpu_init.c b/arch/m68k/cpu/mcf5445x/cpu_init.c
index 8f4991c..134510b 100644
--- a/arch/m68k/cpu/mcf5445x/cpu_init.c
+++ b/arch/m68k/cpu/mcf5445x/cpu_init.c
@@ -200,7 +200,7 @@
 	/* Lowest slew rate for UART0,1,2 */
 	out_8(&gpio->srcr_uart, 0x00);
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 	/* eSDHC pin as faster speed */
 	out_8(&gpio->srcr_sdhc, 0x03);
 
diff --git a/board/advantech/dms-ba16/dms-ba16.c b/board/advantech/dms-ba16/dms-ba16.c
index 0962043..2eccc05 100644
--- a/board/advantech/dms-ba16/dms-ba16.c
+++ b/board/advantech/dms-ba16/dms-ba16.c
@@ -16,7 +16,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
@@ -221,7 +221,7 @@
 	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC2_BASE_ADDR},
 	{USDHC3_BASE_ADDR},
diff --git a/board/amlogic/p212/README.khadas-vim b/board/amlogic/p212/README.khadas-vim
index b194236..a2c7606 100644
--- a/board/amlogic/p212/README.khadas-vim
+++ b/board/amlogic/p212/README.khadas-vim
@@ -50,7 +50,7 @@
  > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot
  > cd vim-u-boot
  > make kvim_defconfig
- > make
+ > make CROSS_COMPILE=aarch64-none-elf-
  > export FIPDIR=$PWD/fip
 
 Go back to mainline U-Boot source tree then :
diff --git a/board/amlogic/p212/p212.c b/board/amlogic/p212/p212.c
index 546c4d9..1159cee 100644
--- a/board/amlogic/p212/p212.c
+++ b/board/amlogic/p212/p212.c
@@ -32,6 +32,8 @@
 					  mac_addr, EFUSE_MAC_SIZE);
 		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
 			eth_env_set_enetaddr("ethaddr", mac_addr);
+		else
+			meson_generate_serial_ethaddr();
 	}
 
 	if (!env_get("serial#")) {
diff --git a/board/amlogic/q200/q200.c b/board/amlogic/q200/q200.c
index de97d6a..2ea97c3 100644
--- a/board/amlogic/q200/q200.c
+++ b/board/amlogic/q200/q200.c
@@ -31,6 +31,8 @@
 					  mac_addr, EFUSE_MAC_SIZE);
 		if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr))
 			eth_env_set_enetaddr("ethaddr", mac_addr);
+		else
+			meson_generate_serial_ethaddr();
 	}
 
 	if (!env_get("serial#")) {
diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c
index 5231c2e..de1a018 100644
--- a/board/aristainetos/aristainetos-v1.c
+++ b/board/aristainetos/aristainetos-v1.c
@@ -20,7 +20,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c
index 63b1057..c81c441 100644
--- a/board/aristainetos/aristainetos-v2.c
+++ b/board/aristainetos/aristainetos-v2.c
@@ -20,7 +20,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c
index c88b9fc..9f744b3 100644
--- a/board/aristainetos/aristainetos.c
+++ b/board/aristainetos/aristainetos.c
@@ -20,7 +20,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
@@ -107,7 +107,7 @@
 	return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC1_BASE_ADDR},
 	{USDHC2_BASE_ADDR},
diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS
index 74434e9..f2d2f49 100644
--- a/board/atmel/sama5d27_som1_ek/MAINTAINERS
+++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS
@@ -5,3 +5,4 @@
 F:	include/configs/sama5d27_som1_ek.h
 F:	configs/sama5d27_som1_ek_mmc_defconfig
 F:	configs/sama5d27_som1_ek_mmc1_defconfig
+F:	configs/sama5d27_som1_ek_qspiflash_defconfig
diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS
index 08de5bb..88e327f 100644
--- a/board/atmel/sama5d2_xplained/MAINTAINERS
+++ b/board/atmel/sama5d2_xplained/MAINTAINERS
@@ -6,3 +6,4 @@
 F:	configs/sama5d2_xplained_mmc_defconfig
 F:	configs/sama5d2_xplained_spiflash_defconfig
 F:	configs/sama5d2_xplained_emmc_defconfig
+F:	configs/sama5d2_xplained_qspiflash_defconfig
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index 2d73441..067a970 100644
--- a/board/bachmann/ot1200/ot1200.c
+++ b/board/bachmann/ot1200/ot1200.c
@@ -18,7 +18,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <netdev.h>
 #include <i2c.h>
 #include <pca953x.h>
diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c
index b484ec2..1c6514a 100644
--- a/board/barco/platinum/platinum.c
+++ b/board/barco/platinum/platinum.c
@@ -6,7 +6,7 @@
 
 #include <common.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/io.h>
diff --git a/board/barco/titanium/titanium.c b/board/barco/titanium/titanium.c
index e9955c8..407bfe9 100644
--- a/board/barco/titanium/titanium.c
+++ b/board/barco/titanium/titanium.c
@@ -16,7 +16,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <micrel.h>
 #include <miiphy.h>
 #include <netdev.h>
@@ -215,7 +215,7 @@
 
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 	{ USDHC3_BASE_ADDR },
 };
diff --git a/board/boundary/nitrogen6x/nitrogen6x.c b/board/boundary/nitrogen6x/nitrogen6x.c
index 84d7cee..867eade 100644
--- a/board/boundary/nitrogen6x/nitrogen6x.c
+++ b/board/boundary/nitrogen6x/nitrogen6x.c
@@ -21,7 +21,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <micrel.h>
 #include <miiphy.h>
 #include <netdev.h>
@@ -283,7 +283,7 @@
 
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC3_BASE_ADDR},
 	{USDHC4_BASE_ADDR},
diff --git a/board/ccv/xpress/xpress.c b/board/ccv/xpress/xpress.c
index dcf5e144..35e1c55 100644
--- a/board/ccv/xpress/xpress.c
+++ b/board/ccv/xpress/xpress.c
@@ -16,7 +16,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <mmc.h>
diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c
index 1bc33b0..94e7bf1 100644
--- a/board/compulab/cl-som-imx7/cl-som-imx7.c
+++ b/board/compulab/cl-som-imx7/cl-som-imx7.c
@@ -12,7 +12,7 @@
 #include <mmc.h>
 #include <phy.h>
 #include <netdev.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <power/pmic.h>
 #include <power/pfuze3000_pmic.h>
 #include <asm/mach-imx/mxc_i2c.h>
@@ -68,7 +68,7 @@
 	return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 
 #define CL_SOM_IMX7_GPIO_USDHC3_PWR	IMX_GPIO_NR(6, 11)
 
@@ -116,7 +116,7 @@
 
 	return 0;
 }
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
 
 #ifdef CONFIG_FEC_MXC
 
diff --git a/board/compulab/cl-som-imx7/common.c b/board/compulab/cl-som-imx7/common.c
index e0f90fd..40ba0f7 100644
--- a/board/compulab/cl-som-imx7/common.c
+++ b/board/compulab/cl-som-imx7/common.c
@@ -8,7 +8,7 @@
  */
 
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm-generic/gpio.h>
 #include "common.h"
 
@@ -23,7 +23,7 @@
 
 #endif /* CONFIG_SPI */
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 
 int board_mmc_getcd(struct mmc *mmc)
 {
@@ -42,4 +42,4 @@
 	return ret;
 }
 
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
diff --git a/board/compulab/cl-som-imx7/common.h b/board/compulab/cl-som-imx7/common.h
index 8b15a59..bc19867 100644
--- a/board/compulab/cl-som-imx7/common.h
+++ b/board/compulab/cl-som-imx7/common.h
@@ -9,19 +9,19 @@
 
 #define PADS_SET_PROT(pads_array) void cl_som_imx7_##pads_array##_set(void)
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 #define CL_SOM_IMX7_GPIO_USDHC1_CD	IMX_GPIO_NR(5, 0)
 PADS_SET_PROT(usdhc1_pads);
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
 PADS_SET_PROT(uart1_pads);
 #ifdef CONFIG_SPI
 PADS_SET_PROT(espi1_pads);
 #endif /* CONFIG_SPI */
 
 #ifndef CONFIG_SPL_BUILD
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 PADS_SET_PROT(usdhc3_emmc_pads);
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
 #ifdef CONFIG_FEC_MXC
 PADS_SET_PROT(phy1_rst_pads);
 PADS_SET_PROT(fec1_pads);
diff --git a/board/compulab/cl-som-imx7/mux.c b/board/compulab/cl-som-imx7/mux.c
index e29d2de..18f16a4 100644
--- a/board/compulab/cl-som-imx7/mux.c
+++ b/board/compulab/cl-som-imx7/mux.c
@@ -17,7 +17,7 @@
 	imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array));  \
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 
 #define USDHC_PAD_CTRL		(PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
 				PAD_CTL_HYS | PAD_CTL_PUE | \
@@ -36,7 +36,7 @@
 
 PADS_SET(usdhc1_pads)
 
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
 
 #define UART_PAD_CTRL		(PAD_CTL_DSE_3P3V_49OHM | \
 				PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
@@ -69,7 +69,7 @@
 
 #ifndef CONFIG_SPL_BUILD
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 
 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
 	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
@@ -89,7 +89,7 @@
 
 PADS_SET(usdhc3_emmc_pads)
 
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
 
 #ifdef CONFIG_FEC_MXC
 
diff --git a/board/compulab/cl-som-imx7/spl.c b/board/compulab/cl-som-imx7/spl.c
index 76a4c8b..f9a19f0 100644
--- a/board/compulab/cl-som-imx7/spl.c
+++ b/board/compulab/cl-som-imx7/spl.c
@@ -9,14 +9,14 @@
 
 #include <common.h>
 #include <spl.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/arch-mx7/mx7-pins.h>
 #include <asm/arch-mx7/clock.h>
 #include <asm/arch-mx7/mx7-ddr.h>
 #include "common.h"
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 
 static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = {
 	USDHC1_BASE_ADDR, 0, 4};
@@ -27,7 +27,7 @@
 	cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 	return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg);
 }
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
 
 static iomux_v3_cfg_t const led_pads[] = {
 	MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |
diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c
index d42f57d..e9262c6 100644
--- a/board/compulab/cm_fx6/cm_fx6.c
+++ b/board/compulab/cm_fx6/cm_fx6.c
@@ -12,7 +12,7 @@
 #include <dm.h>
 #include <dwc_ahsata.h>
 #include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <mtd_node.h>
 #include <netdev.h>
@@ -608,7 +608,7 @@
 	cm_fx6_setup_display();
 
 	/* This should be done in the MMC driver when MX6 has a clock driver */
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 	if (IS_ENABLED(CONFIG_BLK)) {
 		int i;
 
diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c
index e1e4a67..ed8c7a3 100644
--- a/board/compulab/cm_fx6/common.c
+++ b/board/compulab/cm_fx6/common.c
@@ -11,10 +11,10 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/spi.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include "common.h"
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c
index acbb2ad..66186ec 100644
--- a/board/compulab/cm_fx6/spl.c
+++ b/board/compulab/cm_fx6/spl.c
@@ -16,7 +16,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/mach-imx/iomux-v3.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include "common.h"
 
 enum ddr_config {
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index 50124f8..7c767fb 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -21,7 +21,7 @@
 #include <asm/arch/mxc_hdmi.h>
 #include <asm/arch/crm_regs.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <input.h>
 #include <power/pmic.h>
@@ -411,7 +411,7 @@
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 static struct fsl_esdhc_cfg usdhc_cfg[] = {
 	{USDHC2_BASE_ADDR},
 	{USDHC3_BASE_ADDR},
diff --git a/board/dhelectronics/dh_imx6/dh_imx6.c b/board/dhelectronics/dh_imx6/dh_imx6.c
index 50e3cb5..1d41690 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6.c
@@ -24,7 +24,7 @@
 #include <dwc_ahsata.h>
 #include <environment.h>
 #include <errno.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <fuse.h>
 #include <i2c.h>
 #include <miiphy.h>
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
index 2939389..b492961 100644
--- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c
+++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c
@@ -20,7 +20,7 @@
 #include <asm/io.h>
 #include <errno.h>
 #include <fuse.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <spl.h>
diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c
index dd0c112..55db26a 100644
--- a/board/el/el6x/el6x.c
+++ b/board/el/el6x/el6x.c
@@ -16,7 +16,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
@@ -255,7 +255,7 @@
 	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC2_BASE_ADDR},
 	{USDHC4_BASE_ADDR},
diff --git a/board/embest/mx6boards/mx6boards.c b/board/embest/mx6boards/mx6boards.c
index fed92aa..bcfe125 100644
--- a/board/embest/mx6boards/mx6boards.c
+++ b/board/embest/mx6boards/mx6boards.c
@@ -27,7 +27,7 @@
 #include <i2c.h>
 #include <input.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
@@ -181,7 +181,7 @@
 	MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC2_BASE_ADDR},
 	{USDHC3_BASE_ADDR},
diff --git a/board/freescale/imx8mq_evk/imx8mq_evk.c b/board/freescale/imx8mq_evk/imx8mq_evk.c
index 54e0c38..322713c 100644
--- a/board/freescale/imx8mq_evk/imx8mq_evk.c
+++ b/board/freescale/imx8mq_evk/imx8mq_evk.c
@@ -11,7 +11,7 @@
 #include <netdev.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm-generic/gpio.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <mmc.h>
 #include <asm/arch/imx8mq_pins.h>
 #include <asm/arch/sys_proto.h>
diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c
index 3c0ff0b..9164cfb 100644
--- a/board/freescale/imx8mq_evk/spl.c
+++ b/board/freescale/imx8mq_evk/spl.c
@@ -16,7 +16,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/gpio.h>
 #include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <mmc.h>
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
index 63cd605..1207314 100644
--- a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -7,7 +7,7 @@
 #include <errno.h>
 #include <linux/libfdt.h>
 #include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <asm/arch/clock.h>
diff --git a/board/freescale/m54418twr/m54418twr.c b/board/freescale/m54418twr/m54418twr.c
index aa6f0e6..a4943e7 100644
--- a/board/freescale/m54418twr/m54418twr.c
+++ b/board/freescale/m54418twr/m54418twr.c
@@ -9,7 +9,7 @@
 #include <asm/io.h>
 #include <asm/immap.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c
index 18922d8..c59f0fb 100644
--- a/board/freescale/mx25pdk/mx25pdk.c
+++ b/board/freescale/mx25pdk/mx25pdk.c
@@ -12,7 +12,7 @@
 #include <asm/arch/iomux-mx25.h>
 #include <asm/arch/clock.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <power/pmic.h>
 #include <fsl_pmic.h>
@@ -24,7 +24,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{IMX_MMC_SDHC1_BASE},
 };
@@ -151,7 +151,7 @@
 	return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 int board_mmc_getcd(struct mmc *mmc)
 {
 	/* Set up the Card Detect pin. */
diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c
index fa67230..aba17a6 100644
--- a/board/freescale/mx35pdk/mx35pdk.c
+++ b/board/freescale/mx35pdk/mx35pdk.c
@@ -16,7 +16,7 @@
 #include <power/pmic.h>
 #include <fsl_pmic.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <mc9sdz60.h>
 #include <mc13892.h>
 #include <linux/types.h>
@@ -261,7 +261,7 @@
 	return cpu_eth_init(bis);
 }
 
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC_IMX)
 
 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
 
diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c
index 68a9c77..d1bb852 100644
--- a/board/freescale/mx51evk/mx51evk.c
+++ b/board/freescale/mx51evk/mx51evk.c
@@ -16,7 +16,7 @@
 #include <i2c.h>
 #include <input.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <power/pmic.h>
 #include <fsl_pmic.h>
 #include <mc13892.h>
@@ -24,7 +24,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 	{MMC_SDHC1_BASE_ADDR},
 	{MMC_SDHC2_BASE_ADDR},
@@ -262,7 +262,7 @@
 	gpio_set_value(IMX_GPIO_NR(2, 14), 1);
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c
index 9ed4668..e8fcccc 100644
--- a/board/freescale/mx53ard/mx53ard.c
+++ b/board/freescale/mx53ard/mx53ard.c
@@ -13,7 +13,7 @@
 #include <linux/errno.h>
 #include <netdev.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/gpio.h>
 
 #define ETHERNET_INT		IMX_GPIO_NR(2, 31)
@@ -112,7 +112,7 @@
 	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 	{MMC_SDHC1_BASE_ADDR},
 	{MMC_SDHC2_BASE_ADDR},
diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c
index 5603658..56985c6 100644
--- a/board/freescale/mx53evk/mx53evk.c
+++ b/board/freescale/mx53evk/mx53evk.c
@@ -15,7 +15,7 @@
 #include <netdev.h>
 #include <i2c.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <power/pmic.h>
 #include <fsl_pmic.h>
 #include <asm/gpio.h>
@@ -137,7 +137,7 @@
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 	{MMC_SDHC1_BASE_ADDR},
 	{MMC_SDHC3_BASE_ADDR},
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c
index b66cdcd..d023ce6 100644
--- a/board/freescale/mx53loco/mx53loco.c
+++ b/board/freescale/mx53loco/mx53loco.c
@@ -18,7 +18,7 @@
 #include <i2c.h>
 #include <input.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/gpio.h>
 #include <power/pmic.h>
 #include <dialog_pmic.h>
@@ -92,7 +92,7 @@
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 	{MMC_SDHC1_BASE_ADDR},
 	{MMC_SDHC3_BASE_ADDR},
diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c
index 1a1a039..cab0e79 100644
--- a/board/freescale/mx53smd/mx53smd.c
+++ b/board/freescale/mx53smd/mx53smd.c
@@ -13,7 +13,7 @@
 #include <linux/errno.h>
 #include <netdev.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -77,7 +77,7 @@
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{MMC_SDHC1_BASE_ADDR},
 };
diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index f445f4b..3957c09 100644
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -12,7 +12,7 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <usb.h>
@@ -103,7 +103,7 @@
 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC3_BASE_ADDR},
 	{USDHC4_BASE_ADDR},
diff --git a/board/freescale/mx6sabreauto/mx6sabreauto.c b/board/freescale/mx6sabreauto/mx6sabreauto.c
index dd72de9..e1a3b47 100644
--- a/board/freescale/mx6sabreauto/mx6sabreauto.c
+++ b/board/freescale/mx6sabreauto/mx6sabreauto.c
@@ -18,7 +18,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/spi.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/sys_proto.h>
@@ -282,7 +282,7 @@
 	SETUP_IOMUX_PADS(uart4_pads);
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
 	{USDHC3_BASE_ADDR},
 };
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index cdfc5ff..63e1dd0 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -17,7 +17,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
@@ -250,7 +250,7 @@
 	SETUP_IOMUX_PADS(uart1_pads);
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC2_BASE_ADDR},
 	{USDHC3_BASE_ADDR},
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c
index e05aea6..4c48679 100644
--- a/board/freescale/mx6slevk/mx6slevk.c
+++ b/board/freescale/mx6slevk/mx6slevk.c
@@ -19,7 +19,7 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <netdev.h>
diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
index 6e606da..15e921a 100644
--- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
+++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c
@@ -17,7 +17,7 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <power/pmic.h>
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
index 3e10c7f..8ee85cc 100644
--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -17,7 +17,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 #include <linux/sizes.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <mmc.h>
 #include <i2c.h>
 #include <miiphy.h>
diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
index 636c008..785247f 100644
--- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
+++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c
@@ -16,7 +16,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/io.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <miiphy.h>
 #include <linux/sizes.h>
@@ -189,7 +189,7 @@
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC1_BASE_ADDR, 0, 4},
 #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
diff --git a/board/freescale/mx6ullevk/mx6ullevk.c b/board/freescale/mx6ullevk/mx6ullevk.c
index ad83f36..1f0f70e 100644
--- a/board/freescale/mx6ullevk/mx6ullevk.c
+++ b/board/freescale/mx6ullevk/mx6ullevk.c
@@ -14,7 +14,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/io.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/sizes.h>
 #include <mmc.h>
 
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 191b59a..86bf030 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -12,7 +12,7 @@
 #include <asm/io.h>
 #include <linux/sizes.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <mmc.h>
 #include <miiphy.h>
 #include <netdev.h>
diff --git a/board/freescale/s32v234evb/s32v234evb.c b/board/freescale/s32v234evb/s32v234evb.c
index 464be2b..9bc9ddf 100644
--- a/board/freescale/s32v234evb/s32v234evb.c
+++ b/board/freescale/s32v234evb/s32v234evb.c
@@ -10,7 +10,7 @@
 #include <asm/arch/lpddr2.h>
 #include <asm/arch/clock.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <i2c.h>
@@ -74,7 +74,7 @@
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{USDHC_BASE_ADDR},
 };
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index 63be3bd..f6cd7a4 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -11,7 +11,7 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <i2c.h>
@@ -234,7 +234,7 @@
 	imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 	{ESDHC1_BASE_ADDR},
 };
diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c
index 8786a12..a543916 100644
--- a/board/gateworks/gw_ventana/common.c
+++ b/board/gateworks/gw_ventana/common.c
@@ -10,7 +10,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <hwconfig.h>
 #include <power/pmic.h>
 #include <power/ltc3676_pmic.h>
@@ -1656,7 +1656,7 @@
 	}
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 static struct fsl_esdhc_cfg usdhc_cfg[2];
 
 int board_mmc_init(bd_t *bis)
@@ -1753,4 +1753,4 @@
 	return -1;
 }
 
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c
index c63fb41..92edc10 100644
--- a/board/gateworks/gw_ventana/gw_ventana.c
+++ b/board/gateworks/gw_ventana/gw_ventana.c
@@ -25,7 +25,7 @@
 #include <hwconfig.h>
 #include <i2c.h>
 #include <fdt_support.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <jffs2/load_kernel.h>
 #include <linux/ctype.h>
 #include <miiphy.h>
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index f42d2ce..8065252 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -17,7 +17,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <net.h>
 #include <netdev.h>
diff --git a/board/ge/mx53ppd/mx53ppd.c b/board/ge/mx53ppd/mx53ppd.c
index 5411e42..bf75bd2 100644
--- a/board/ge/mx53ppd/mx53ppd.c
+++ b/board/ge/mx53ppd/mx53ppd.c
@@ -24,7 +24,7 @@
 #include <netdev.h>
 #include <i2c.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/gpio.h>
 #include <power/pmic.h>
 #include <dialog_pmic.h>
diff --git a/board/grinn/liteboard/board.c b/board/grinn/liteboard/board.c
index 80910e4..1491b8c 100644
--- a/board/grinn/liteboard/board.c
+++ b/board/grinn/liteboard/board.c
@@ -17,7 +17,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/io.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/sizes.h>
 #include <linux/fb.h>
 #include <miiphy.h>
@@ -66,7 +66,7 @@
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
 
 #define SD_CD_GPIO	IMX_GPIO_NR(1, 19)
diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c
index a490aa8..de4ad83 100644
--- a/board/inversepath/usbarmory/usbarmory.c
+++ b/board/inversepath/usbarmory/usbarmory.c
@@ -17,7 +17,7 @@
 #include <linux/errno.h>
 #include <i2c.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
index ace986f..7bdc64b 100644
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
@@ -18,7 +18,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <errno.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <fuse.h>
 #include <i2c.h>
 #include <miiphy.h>
@@ -166,7 +166,7 @@
 }
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 
 #define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
 static struct fsl_esdhc_cfg usdhc_cfg[] = {
diff --git a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
index d89e112..e284d5e 100644
--- a/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
+++ b/board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
@@ -20,7 +20,7 @@
 #include <asm/io.h>
 #include <errno.h>
 #include <fuse.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <spl.h>
diff --git a/board/kosagi/novena/novena.c b/board/kosagi/novena/novena.c
index 78294b8..dcf3d7f 100644
--- a/board/kosagi/novena/novena.c
+++ b/board/kosagi/novena/novena.c
@@ -25,7 +25,7 @@
 #include <asm/mach-imx/video.h>
 #include <dwc_ahsata.h>
 #include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <input.h>
 #include <ipu_pixfmt.h>
diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c
index b2d670e..00210ab 100644
--- a/board/kosagi/novena/novena_spl.c
+++ b/board/kosagi/novena/novena_spl.c
@@ -19,7 +19,7 @@
 #include <asm/arch/crm_regs.h>
 #include <i2c.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <spl.h>
 
 #include <asm/arch/mx6-ddr.h>
@@ -404,7 +404,7 @@
 /*
  * SPL boots from uSDHC card
  */
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 static struct fsl_esdhc_cfg usdhc_cfg = {
 	USDHC3_BASE_ADDR, 0, 4
 };
@@ -566,7 +566,7 @@
 #ifdef CONFIG_BOARD_POSTCLK_INIT
 	board_postclk_init();
 #endif
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 	get_clocks();
 #endif
 
diff --git a/board/liebherr/display5/common.c b/board/liebherr/display5/common.c
index 4eb86d8..7b89d16 100644
--- a/board/liebherr/display5/common.c
+++ b/board/liebherr/display5/common.c
@@ -89,7 +89,7 @@
 void displ5_set_iomux_ecspi(void) {}
 #endif
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 iomux_v3_cfg_t const usdhc4_pads[] = {
 	MX6_PAD_SD4_CLK__SD4_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_CMD__SD4_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
diff --git a/board/liebherr/display5/display5.c b/board/liebherr/display5/display5.c
index d838317..6b7ff0a 100644
--- a/board/liebherr/display5/display5.c
+++ b/board/liebherr/display5/display5.c
@@ -21,7 +21,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/spi.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <i2c.h>
@@ -186,7 +186,7 @@
 	MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg usdhc_cfg[1] = {
 	{ USDHC4_BASE_ADDR, 0, 8, },
 };
@@ -204,7 +204,7 @@
 
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
 
 static void displ5_setup_ecspi(void)
 {
diff --git a/board/liebherr/display5/spl.c b/board/liebherr/display5/spl.c
index 0c0172e..27f843e 100644
--- a/board/liebherr/display5/spl.c
+++ b/board/liebherr/display5/spl.c
@@ -18,7 +18,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/gpio.h>
 #include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <netdev.h>
 #include <bootcount.h>
 #include <watchdog.h>
diff --git a/board/liebherr/mccmon6/mccmon6.c b/board/liebherr/mccmon6/mccmon6.c
index 946b91f..0e069a7 100644
--- a/board/liebherr/mccmon6/mccmon6.c
+++ b/board/liebherr/mccmon6/mccmon6.c
@@ -16,7 +16,7 @@
 #include <asm/mach-imx/spi.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/io.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <mmc.h>
 #include <netdev.h>
 #include <micrel.h>
diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c
index acfc490..f0ed78c 100644
--- a/board/liebherr/mccmon6/spl.c
+++ b/board/liebherr/mccmon6/spl.c
@@ -14,7 +14,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
diff --git a/board/logicpd/imx6/imx6logic.c b/board/logicpd/imx6/imx6logic.c
index 53e609e..e48b3be 100644
--- a/board/logicpd/imx6/imx6logic.c
+++ b/board/logicpd/imx6/imx6logic.c
@@ -12,7 +12,7 @@
 #include <miiphy.h>
 #include <input.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/io.h>
 #include <asm/gpio.h>
 #include <linux/sizes.h>
@@ -200,7 +200,7 @@
 	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg usdhc_cfg[] = {
 	{USDHC1_BASE_ADDR}, /* SOM */
 	{USDHC2_BASE_ADDR}  /* Baseboard */
diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c
index 31ba44e..f2227f6 100644
--- a/board/menlo/m53menlo/m53menlo.c
+++ b/board/menlo/m53menlo/m53menlo.c
@@ -19,7 +19,7 @@
 #include <asm/gpio.h>
 #include <asm/spl.h>
 #include <fdt_support.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <ipu_pixfmt.h>
 #include <linux/errno.h>
@@ -125,6 +125,43 @@
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
+#ifdef CONFIG_FSL_ESDHC_IMX
+struct fsl_esdhc_cfg esdhc_cfg = {
+	MMC_SDHC1_BASE_ADDR,
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
+	gpio_direction_input(IMX_GPIO_NR(1, 1));
+
+	return !gpio_get_value(IMX_GPIO_NR(1, 1));
+}
+
+#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
+				 PAD_CTL_PUS_100K_UP)
+#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
+				 PAD_CTL_DSE_HIGH)
+
+int board_mmc_init(bd_t *bis)
+{
+	static const iomux_v3_cfg_t sd1_pads[] = {
+		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
+		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
+	};
+
+	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
+
+	return fsl_esdhc_initialize(bis, &esdhc_cfg);
+}
+#endif
+
 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
 {
 	static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
diff --git a/board/phytec/pcl063/pcl063.c b/board/phytec/pcl063/pcl063.c
index 17012df..f8cbd1c 100644
--- a/board/phytec/pcl063/pcl063.c
+++ b/board/phytec/pcl063/pcl063.c
@@ -12,7 +12,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/bitops.h>
 #include <miiphy.h>
 #include <netdev.h>
diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c
index 73a7746..6d4c827 100644
--- a/board/phytec/pcl063/spl.c
+++ b/board/phytec/pcl063/spl.c
@@ -14,7 +14,7 @@
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 
 /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
 
@@ -101,7 +101,7 @@
 	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 
 #define USDHC_PAD_CTRL (PAD_CTL_PKE         | PAD_CTL_PUE       | \
 			PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW | \
@@ -205,7 +205,7 @@
 
 	spl_boot_list[0] = boot_dev;
 }
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
 
 void board_init_f(ulong dummy)
 {
diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c
index 5ecaf00..ac5e3a2 100644
--- a/board/phytec/pcm058/pcm058.c
+++ b/board/phytec/pcm058/pcm058.c
@@ -25,7 +25,7 @@
 #include <asm/gpio.h>
 #include <mmc.h>
 #include <i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <nand.h>
 #include <miiphy.h>
 #include <netdev.h>
diff --git a/board/phytec/pfla02/pfla02.c b/board/phytec/pfla02/pfla02.c
index aae23a3..753cf2b 100644
--- a/board/phytec/pfla02/pfla02.c
+++ b/board/phytec/pfla02/pfla02.c
@@ -19,7 +19,7 @@
 #include <asm/gpio.h>
 #include <mmc.h>
 #include <i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <nand.h>
 #include <miiphy.h>
 #include <netdev.h>
diff --git a/board/seco/common/mx6.c b/board/seco/common/mx6.c
index fd7008a..51832b9 100644
--- a/board/seco/common/mx6.c
+++ b/board/seco/common/mx6.c
@@ -16,7 +16,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/boot_mode.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
diff --git a/board/seco/mx6quq7/mx6quq7.c b/board/seco/mx6quq7/mx6quq7.c
index 094a210..c1e36b6 100644
--- a/board/seco/mx6quq7/mx6quq7.c
+++ b/board/seco/mx6quq7/mx6quq7.c
@@ -17,7 +17,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <malloc.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
diff --git a/board/sks-kinkel/sksimx6/sksimx6.c b/board/sks-kinkel/sksimx6/sksimx6.c
index f6e3d4d..59a07a9 100644
--- a/board/sks-kinkel/sksimx6/sksimx6.c
+++ b/board/sks-kinkel/sksimx6/sksimx6.c
@@ -12,7 +12,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index 19b9b37..5332801 100644
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -19,7 +19,7 @@
 #include <linux/sizes.h>
 #include <common.h>
 #include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <mmc.h>
 #include <i2c.h>
 #include <miiphy.h>
diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c
index cf63427..d333ccc 100644
--- a/board/solidrun/mx6cuboxi/mx6cuboxi.c
+++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c
@@ -24,7 +24,7 @@
 #include <asm/mach-imx/sata.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <malloc.h>
 #include <miiphy.h>
 #include <netdev.h>
diff --git a/board/tbs/tbs2910/tbs2910.c b/board/tbs/tbs2910/tbs2910.c
index fb0e773..d8db7a8 100644
--- a/board/tbs/tbs2910/tbs2910.c
+++ b/board/tbs/tbs2910/tbs2910.c
@@ -13,7 +13,7 @@
 #include <asm/mach-imx/boot_mode.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <asm/arch/mxc_hdmi.h>
@@ -98,7 +98,7 @@
 	imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 /* set environment device to boot device when booting from SD */
 int board_mmc_get_env_dev(int devno)
 {
@@ -109,7 +109,7 @@
 {
 	return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
 }
-#endif /* CONFIG_FSL_ESDHC */
+#endif /* CONFIG_FSL_ESDHC_IMX */
 
 #ifdef CONFIG_VIDEO_IPUV3
 static void do_enable_hdmi(struct display_info_t const *dev)
diff --git a/board/technexion/pico-imx6ul/spl.c b/board/technexion/pico-imx6ul/spl.c
index f972cc9..284aa40 100644
--- a/board/technexion/pico-imx6ul/spl.c
+++ b/board/technexion/pico-imx6ul/spl.c
@@ -10,7 +10,7 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/libfdt.h>
 #include <spl.h>
 
diff --git a/board/technexion/pico-imx7d/spl.c b/board/technexion/pico-imx7d/spl.c
index 92a4646..c55a35d 100644
--- a/board/technexion/pico-imx7d/spl.c
+++ b/board/technexion/pico-imx7d/spl.c
@@ -13,7 +13,7 @@
 #include <asm/arch-mx7/mx7-ddr.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/gpio.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <spl.h>
 
 #if defined(CONFIG_SPL_BUILD)
diff --git a/board/technologic/ts4800/ts4800.c b/board/technologic/ts4800/ts4800.c
index a0e021e..927a19d 100644
--- a/board/technologic/ts4800/ts4800.c
+++ b/board/technologic/ts4800/ts4800.c
@@ -19,7 +19,7 @@
 #include <environment.h>
 #include <mmc.h>
 #include <input.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <mc13892.h>
 
 #include <malloc.h>
@@ -29,7 +29,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 	{MMC_SDHC1_BASE_ADDR},
 	{MMC_SDHC2_BASE_ADDR},
@@ -96,7 +96,7 @@
 	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifdef CONFIG_FSL_ESDHC_IMX
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c
index b502d4e..3417351 100644
--- a/board/toradex/apalis_imx6/apalis_imx6.c
+++ b/board/toradex/apalis_imx6/apalis_imx6.c
@@ -27,7 +27,7 @@
 #include <dm/platform_data/serial_mxc.h>
 #include <dwc_ahsata.h>
 #include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <imx_thermal.h>
 #include <micrel.h>
 #include <miiphy.h>
@@ -131,7 +131,7 @@
 	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 	MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(WEAK_PULLUP) | MUX_MODE_SION,
 };
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 
 int mx6_rgmii_rework(struct phy_device *phydev)
 {
@@ -355,7 +355,7 @@
 
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 
 int board_phy_config(struct phy_device *phydev)
 {
diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c
index c634e32..6417ba4 100644
--- a/board/toradex/colibri_imx6/colibri_imx6.c
+++ b/board/toradex/colibri_imx6/colibri_imx6.c
@@ -25,7 +25,7 @@
 #include <cpu.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <environment.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <imx_thermal.h>
 #include <micrel.h>
 #include <miiphy.h>
@@ -110,7 +110,7 @@
 	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_EMMC_PAD_CTRL),
 	MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -361,7 +361,7 @@
 
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
-#endif /* CONFIG_FSL_ESDHC & CONFIG_SPL_BUILD */
+#endif /* CONFIG_FSL_ESDHC_IMX & CONFIG_SPL_BUILD */
 
 int board_phy_config(struct phy_device *phydev)
 {
diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c
index 61bf8bf..0eb8347 100644
--- a/board/toradex/colibri_imx7/colibri_imx7.c
+++ b/board/toradex/colibri_imx7/colibri_imx7.c
@@ -15,7 +15,7 @@
 #include <dm.h>
 #include <dm/platform_data/serial_mxc.h>
 #include <fdt_support.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <jffs2/load_kernel.h>
 #include <linux/sizes.h>
 #include <mmc.h>
diff --git a/board/tqc/tqma6/tqma6.c b/board/tqc/tqma6/tqma6.c
index 372a17c..5f0c7aa 100644
--- a/board/tqc/tqma6/tqma6.c
+++ b/board/tqc/tqma6/tqma6.c
@@ -18,7 +18,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/spi.h>
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/libfdt.h>
 #include <i2c.h>
 #include <mmc.h>
diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
index f7072b8..8a2431e 100644
--- a/board/tqc/tqma6/tqma6_mba6.c
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -18,7 +18,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/libfdt.h>
 #include <malloc.h>
 #include <i2c.h>
diff --git a/board/tqc/tqma6/tqma6_wru4.c b/board/tqc/tqma6/tqma6_wru4.c
index aaee9bf..99196ad 100644
--- a/board/tqc/tqma6/tqma6_wru4.c
+++ b/board/tqc/tqma6/tqma6_wru4.c
@@ -21,7 +21,7 @@
 #include <asm/mach-imx/mxc_i2c.h>
 
 #include <common.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/libfdt.h>
 #include <malloc.h>
 #include <i2c.h>
diff --git a/board/udoo/neo/neo.c b/board/udoo/neo/neo.c
index 8281613..d51f648 100644
--- a/board/udoo/neo/neo.c
+++ b/board/udoo/neo/neo.c
@@ -16,7 +16,7 @@
 #include <asm/gpio.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/mach-imx/mxc_i2c.h>
diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c
index 491e9be..c34a5a6 100644
--- a/board/udoo/udoo.c
+++ b/board/udoo/udoo.c
@@ -15,7 +15,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/sata.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c
index 30663e2..b287fbf 100644
--- a/board/udoo/udoo_spl.c
+++ b/board/udoo/udoo_spl.c
@@ -15,7 +15,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
diff --git a/board/variscite/dart_6ul/dart_6ul.c b/board/variscite/dart_6ul/dart_6ul.c
index 4765595..2d0b760 100644
--- a/board/variscite/dart_6ul/dart_6ul.c
+++ b/board/variscite/dart_6ul/dart_6ul.c
@@ -10,7 +10,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/bitops.h>
 #include <miiphy.h>
 #include <netdev.h>
diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c
index f7e6ab6..798523d 100644
--- a/board/variscite/dart_6ul/spl.c
+++ b/board/variscite/dart_6ul/spl.c
@@ -11,7 +11,7 @@
 #include <asm/arch/mx6-ddr.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/arch/crm_regs.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 
 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c
index 7b0f15a..dbd9d02 100644
--- a/board/wandboard/spl.c
+++ b/board/wandboard/spl.c
@@ -14,7 +14,7 @@
 #include <asm/mach-imx/iomux-v3.h>
 #include <asm/mach-imx/video.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
diff --git a/board/warp/warp.c b/board/warp/warp.c
index f346b92..a44a578 100644
--- a/board/warp/warp.c
+++ b/board/warp/warp.c
@@ -19,7 +19,7 @@
 #include <linux/sizes.h>
 #include <common.h>
 #include <watchdog.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <i2c.h>
 #include <mmc.h>
 #include <usb.h>
diff --git a/board/woodburn/woodburn.c b/board/woodburn/woodburn.c
index 42633ed..5cab3f4 100644
--- a/board/woodburn/woodburn.c
+++ b/board/woodburn/woodburn.c
@@ -17,7 +17,7 @@
 #include <fsl_pmic.h>
 #include <mc13892.h>
 #include <mmc.h>
-#include <fsl_esdhc.h>
+#include <fsl_esdhc_imx.h>
 #include <linux/types.h>
 #include <asm/gpio.h>
 #include <asm/arch/sys_proto.h>
@@ -206,7 +206,7 @@
 	return 0;
 }
 
-#if defined(CONFIG_FSL_ESDHC)
+#if defined(CONFIG_FSL_ESDHC_IMX)
 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
 
 int board_mmc_init(bd_t *bis)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 142753f..8021661 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -613,6 +613,104 @@
 	  This enables the drivers in drivers/mtd/nand/raw as part of an SPL
 	  build.
 
+config SPL_UBI
+	bool "Support UBI"
+	help
+	  Enable support for loading payloads from UBI. See
+	  README.ubispl for more info.
+
+if SPL_UBI
+config SPL_UBI_LOAD_BY_VOLNAME
+	bool "Support loading volumes by name"
+	help
+	  This enables support for loading UBI volumes by name. When this
+	  is set, CONFIG_SPL_UBI_LOAD_MONITOR_VOLNAME can be used to
+	  configure the volume name from which to load U-Boot.
+
+config SPL_UBI_MAX_VOL_LEBS
+	int "Maximum number of LEBs per volume"
+	depends on SPL_UBI
+	help
+	  The maximum number of logical eraseblocks which a static volume
+	  to load can contain. Used for sizing the scan data structure.
+
+config SPL_UBI_MAX_PEB_SIZE
+	int "Maximum PEB size"
+	depends on SPL_UBI
+	help
+	  The maximum physical erase block size.
+
+config SPL_UBI_MAX_PEBS
+	int "Maximum number of PEBs"
+	depends on SPL_UBI
+	help
+	  The maximum physical erase block size. If not overridden by
+	  board code, this value will be used as the actual number of PEBs.
+
+config SPL_UBI_PEB_OFFSET
+	int "Offset to first UBI PEB"
+	depends on SPL_UBI
+	help
+	  The offset in number of PEBs from the start of flash to the first
+	  PEB part of the UBI image.
+
+config SPL_UBI_VID_OFFSET
+	int "Offset to VID header"
+	depends on SPL_UBI
+
+config SPL_UBI_LEB_START
+	int "Offset to LEB in PEB"
+	depends on SPL_UBI
+	help
+	  The offset in bytes to the LEB within a PEB.
+
+config SPL_UBI_INFO_ADDR
+	hex "Address to place UBI scan info"
+	depends on SPL_UBI
+	help
+	  Address for ubispl to place the scan info. Read README.ubispl to
+	  determine the required size
+
+config SPL_UBI_VOL_IDS
+	int "Maximum volume id"
+	depends on SPL_UBI
+	help
+	  The maximum volume id which can be loaded. Used for sizing the
+	  scan data structure.
+
+config SPL_UBI_LOAD_MONITOR_ID
+	int "id of U-Boot volume"
+	depends on SPL_UBI
+	help
+	  The UBI volume id from which to load U-Boot
+
+config SPL_UBI_LOAD_MONITOR_VOLNAME
+	string "volume name of U-Boot volume"
+	depends on SPL_UBI_LOAD_BY_VOLNAME
+	help
+	  The UBI volume name from which to load U-Boot
+
+config SPL_UBI_LOAD_KERNEL_ID
+	int "id of kernel volume"
+	depends on SPL_OS_BOOT && SPL_UBI
+	help
+	  The UBI volume id from which to load the kernel
+
+config SPL_UBI_LOAD_ARGS_ID
+	int "id of kernel args volume"
+	depends on SPL_OS_BOOT && SPL_UBI
+	help
+	  The UBI volume id from which to load the device tree
+
+config UBI_SPL_SILENCE_MSG
+	bool "silence UBI SPL messages"
+	default n
+	help
+	  Disable messages from UBI SPL. This leaves warnings
+	  and errors enabled.
+
+endif   # if SPL_UBI
+
 config SPL_NET_SUPPORT
 	bool "Support networking"
 	help
diff --git a/common/spl/spl_ubi.c b/common/spl/spl_ubi.c
index 67e5fad..0cb5080 100644
--- a/common/spl/spl_ubi.c
+++ b/common/spl/spl_ubi.c
@@ -62,7 +62,14 @@
 	}
 #endif
 	header = spl_get_load_buffer(-sizeof(*header), sizeof(header));
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+	volumes[0].vol_id = -1;
+	strncpy(volumes[0].name,
+		CONFIG_SPL_UBI_LOAD_MONITOR_VOLNAME,
+		UBI_VOL_NAME_MAX + 1);
+#else
 	volumes[0].vol_id = CONFIG_SPL_UBI_LOAD_MONITOR_ID;
+#endif
 	volumes[0].load_addr = (void *)header;
 
 	ret = ubispl_load_volumes(&info, volumes, 1);
diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig
index 3a57946..df91615 100644
--- a/configs/am335x_guardian_defconfig
+++ b/configs/am335x_guardian_defconfig
@@ -8,6 +8,8 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x040000
+CONFIG_ENV_OFFSET=0x300000
 CONFIG_SPL=y
 CONFIG_BOOTSTAGE_STASH_ADDR=0x0
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index ea2a68f..5874831 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -8,6 +8,7 @@
 CONFIG_TARGET_AM335X_IGEP003X=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x18000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -20,6 +21,18 @@
 CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C_SUPPORT=y
 CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_UBI=y
+CONFIG_SPL_UBI_MAX_VOL_LEBS=256
+CONFIG_SPL_UBI_MAX_PEB_SIZE=262144
+CONFIG_SPL_UBI_MAX_PEBS=4096
+CONFIG_SPL_UBI_PEB_OFFSET=4
+CONFIG_SPL_UBI_VID_OFFSET=512
+CONFIG_SPL_UBI_LEB_START=2048
+CONFIG_SPL_UBI_INFO_ADDR=0x88080000
+CONFIG_SPL_UBI_VOL_IDS=8
+CONFIG_SPL_UBI_LOAD_MONITOR_ID=0
+CONFIG_SPL_UBI_LOAD_KERNEL_ID=3
+CONFIG_SPL_UBI_LOAD_ARGS_ID=4
 CONFIG_SPL_OS_BOOT=y
 CONFIG_SPL_POWER_SUPPORT=y
 CONFIG_SPL_WATCHDOG_SUPPORT=y
@@ -42,6 +55,9 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="am335x-base0033"
 CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="config"
+CONFIG_ENV_UBI_VOLUME_REDUND="config_r"
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index a0a4aba..4fa08e1 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -6,6 +6,7 @@
 CONFIG_TARGET_PDU001=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index 98efb6f..aa4caf6 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -7,6 +7,8 @@
 CONFIG_TARGET_AM335X_SHC=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x7000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 94672f6..2083857 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -7,6 +7,8 @@
 CONFIG_TARGET_AM335X_SHC=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x7000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index ab7afdd..fdb22af 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -7,6 +7,8 @@
 CONFIG_TARGET_AM335X_SHC=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x7000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index ea77f4e..1bbd85f 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -7,6 +7,8 @@
 CONFIG_TARGET_AM335X_SHC=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x7000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 678ead9..b10d045 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -7,6 +7,7 @@
 CONFIG_TARGET_AM335X_SL50=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_OFFSET=0x0
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 526dda2..4bb5dfe 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_AM43XX=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index b644273..56881f2 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -3,6 +3,8 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x30000000
 CONFIG_AM43XX=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x110000
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,QSPI,QSPI_BOOT"
 CONFIG_QSPI_BOOT=y
@@ -29,6 +31,7 @@
 CONFIG_DTB_RESELECT=y
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 # CONFIG_BLK is not set
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index c855705..1af908a 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -4,6 +4,7 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_AM43XX=y
 CONFIG_SPL_RTC_DDR_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 6a47c66..fc474aa 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -3,6 +3,7 @@
 CONFIG_ISW_ENTRY_ADDR=0x40300350
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_AM43XX=y
+CONFIG_ENV_SIZE=0x10000
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_SPL_LOAD_FIT=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index ff7f815..fad564d 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -8,6 +8,7 @@
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
 CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+CONFIG_ENV_SIZE=0x10000
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT_IMAGE_POST_PROCESS=y
diff --git a/configs/apalis-imx8qm_defconfig b/configs/apalis-imx8qm_defconfig
index 7f6ccc9..46a0a2a 100644
--- a/configs/apalis-imx8qm_defconfig
+++ b/configs/apalis-imx8qm_defconfig
@@ -35,6 +35,7 @@
 CONFIG_SYS_I2C_IMX_LPI2C=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 248922c..cad3f1a 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -61,7 +61,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 87a8678..49dd9bb 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -35,7 +35,7 @@
 CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index 256d722..06c05f7 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -35,7 +35,7 @@
 CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index 44b30e3..e645055 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -35,7 +35,7 @@
 CONFIG_CMD_MTDPARTS=y
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/at91rm9200ek_defconfig b/configs/at91rm9200ek_defconfig
index 7ebbdac..5eb6da0 100644
--- a/configs/at91rm9200ek_defconfig
+++ b/configs/at91rm9200ek_defconfig
@@ -2,6 +2,8 @@
 CONFIG_ARCH_AT91=y
 CONFIG_SYS_TEXT_BASE=0x10000000
 CONFIG_TARGET_AT91RM9200EK=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_BOOTDELAY=3
 # CONFIG_DISPLAY_CPUINFO is not set
@@ -18,6 +20,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/at91rm9200ek_ram_defconfig b/configs/at91rm9200ek_ram_defconfig
index 87fd7a3..f99b17b 100644
--- a/configs/at91rm9200ek_ram_defconfig
+++ b/configs/at91rm9200ek_ram_defconfig
@@ -2,6 +2,8 @@
 CONFIG_ARCH_AT91=y
 CONFIG_SYS_TEXT_BASE=0x20100000
 CONFIG_TARGET_AT91RM9200EK=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT"
 CONFIG_BOOTDELAY=3
@@ -19,6 +21,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
 # CONFIG_MMC is not set
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/at91sam9260ek_dataflash_cs0_defconfig b/configs/at91sam9260ek_dataflash_cs0_defconfig
index 137ecd9..633b0a3 100644
--- a/configs/at91sam9260ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs0_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -31,6 +33,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9260ek_dataflash_cs1_defconfig b/configs/at91sam9260ek_dataflash_cs1_defconfig
index 2547f2d..2e47f43 100644
--- a/configs/at91sam9260ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9260ek_dataflash_cs1_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -31,6 +33,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9261ek_dataflash_cs0_defconfig b/configs/at91sam9261ek_dataflash_cs0_defconfig
index 8eab764..82bf9ee 100644
--- a/configs/at91sam9261ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs0_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -32,6 +34,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9261ek_dataflash_cs3_defconfig b/configs/at91sam9261ek_dataflash_cs3_defconfig
index dfafdfa..7e4e493 100644
--- a/configs/at91sam9261ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9261ek_dataflash_cs3_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -32,6 +34,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index b768a32..c26a128 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21F00000
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
@@ -35,6 +37,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index b768a32..c26a128 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21F00000
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
@@ -35,6 +37,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 270d2e6..a40e072 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x0000000
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x7e0000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
@@ -31,6 +33,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index ad86956..b7d4491 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21F00000
 CONFIG_TARGET_AT91SAM9263EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x7e0000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
@@ -31,6 +33,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9g10ek_dataflash_cs0_defconfig b/configs/at91sam9g10ek_dataflash_cs0_defconfig
index a20f461..87796dd 100644
--- a/configs/at91sam9g10ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs0_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -32,6 +34,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9g10ek_dataflash_cs3_defconfig b/configs/at91sam9g10ek_dataflash_cs3_defconfig
index 5ea03c5..9ee0cbb 100644
--- a/configs/at91sam9g10ek_dataflash_cs3_defconfig
+++ b/configs/at91sam9g10ek_dataflash_cs3_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9261EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -32,6 +34,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index abc7661..dde8343 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x2000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
diff --git a/configs/at91sam9g20ek_dataflash_cs0_defconfig b/configs/at91sam9g20ek_dataflash_cs0_defconfig
index 73146fd..bd2d548 100644
--- a/configs/at91sam9g20ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs0_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -31,6 +33,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9g20ek_dataflash_cs1_defconfig b/configs/at91sam9g20ek_dataflash_cs1_defconfig
index 127e3ad..88bffdb 100644
--- a/configs/at91sam9g20ek_dataflash_cs1_defconfig
+++ b/configs/at91sam9g20ek_dataflash_cs1_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -31,6 +33,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 039f4c1..dc1dedd 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x73f00000
 CONFIG_TARGET_AT91SAM9M10G45EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index a20f575..ce3603b 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x26f00000
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index a1caaeb..7470c78 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x26f00000
 CONFIG_TARGET_AT91SAM9N12EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0x5000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -32,6 +34,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9n12ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index 4f2818f..4d2926e 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21F00000
 CONFIG_TARGET_AT91SAM9RLEK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -32,6 +34,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 # CONFIG_NET is not set
 CONFIG_DM=y
 CONFIG_CLK=y
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index 807a47b..80a5b8d 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x21F00000
 CONFIG_TARGET_AT91SAM9RLEK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index c45970b..d8b5712 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x26f00000
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -34,6 +36,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 63ddf75..3fd4a81 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x26f00000
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 65f3175..f328257 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x26f00000
 CONFIG_TARGET_AT91SAM9X5EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x3000
+CONFIG_ENV_OFFSET=0x5000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -34,6 +36,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g35ek"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9xeek_dataflash_cs0_defconfig b/configs/at91sam9xeek_dataflash_cs0_defconfig
index 80cbb9e..f550ad4 100644
--- a/configs/at91sam9xeek_dataflash_cs0_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs0_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -31,6 +33,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/at91sam9xeek_dataflash_cs1_defconfig b/configs/at91sam9xeek_dataflash_cs1_defconfig
index 4f19edc..5d69ac5 100644
--- a/configs/at91sam9xeek_dataflash_cs1_defconfig
+++ b/configs/at91sam9xeek_dataflash_cs1_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_AT91SAM9260EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xfffff200
@@ -31,6 +33,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/axm_defconfig b/configs/axm_defconfig
index 73febdf..bb27b72 100644
--- a/configs/axm_defconfig
+++ b/configs/axm_defconfig
@@ -11,6 +11,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 7c455d2..d9e337a 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -52,7 +52,7 @@
 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_NAND_VF610_NFC_DT=y
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index b5d7b7c..5487e55 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -8,6 +8,8 @@
 CONFIG_TARGET_BRPPT1=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
diff --git a/configs/brppt1_nand_defconfig b/configs/brppt1_nand_defconfig
index 2d93c89..5ab3f92 100644
--- a/configs/brppt1_nand_defconfig
+++ b/configs/brppt1_nand_defconfig
@@ -7,6 +7,8 @@
 CONFIG_AM33XX=y
 CONFIG_TARGET_BRPPT1=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x60000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 28856ab..ce7c852 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -7,6 +7,8 @@
 CONFIG_AM33XX=y
 CONFIG_TARGET_BRPPT1=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x20000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -68,6 +70,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="am335x-brppt1-spi"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent interrupt-controller interrupt-cells dma-names dmas "
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index c35c73f..f2f10ba 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -9,6 +9,8 @@
 CONFIG_TARGET_BRXRE1=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
 CONFIG_SPL=y
 CONFIG_TPL_SYS_MALLOC_F_LEN=0x0
diff --git a/configs/cgtqmx6eval_defconfig b/configs/cgtqmx6eval_defconfig
index 0a6ff20..ec042d7 100644
--- a/configs/cgtqmx6eval_defconfig
+++ b/configs/cgtqmx6eval_defconfig
@@ -55,7 +55,7 @@
 CONFIG_DFU_SF=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index 944dd0d..e208a21 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -6,6 +6,8 @@
 CONFIG_TARGET_CHILIBOARD=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x20000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index 73c78e2..cad8f4b 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -51,7 +51,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index ce3f9de..002db24 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -55,7 +55,7 @@
 # CONFIG_DWC_AHSATA_AHCI is not set
 CONFIG_DM_KEYBOARD=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_SPI_FLASH=y
diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig
index 3df94d2..550ee2b 100644
--- a/configs/cm_t335_defconfig
+++ b/configs/cm_t335_defconfig
@@ -7,6 +7,8 @@
 CONFIG_TARGET_CM_T335=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x300000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig
index f363914..44b66a4 100644
--- a/configs/cm_t35_defconfig
+++ b/configs/cm_t35_defconfig
@@ -3,6 +3,7 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x80008000
 CONFIG_TARGET_CM_T35=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_BOOTDELAY=3
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 72b7d36..be94b84 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -6,6 +6,8 @@
 CONFIG_TARGET_CM_T43=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0xc0000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
@@ -44,6 +46,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_MTDPARTS=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
diff --git a/configs/cm_t54_defconfig b/configs/cm_t54_defconfig
index dedc8b5..8b04f33 100644
--- a/configs/cm_t54_defconfig
+++ b/configs/cm_t54_defconfig
@@ -3,6 +3,8 @@
 CONFIG_OMAP54XX=y
 CONFIG_TARGET_CM_T54=y
 CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0xc0000
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 1c02729..c28a167 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -53,7 +53,7 @@
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
diff --git a/configs/colibri-imx8qxp_defconfig b/configs/colibri-imx8qxp_defconfig
index 8d6c078..b35ec58 100644
--- a/configs/colibri-imx8qxp_defconfig
+++ b/configs/colibri-imx8qxp_defconfig
@@ -34,6 +34,7 @@
 CONFIG_SYS_I2C_IMX_LPI2C=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_MICREL=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 56e512d..b343178 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -60,7 +60,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index e5e4168..c303c06 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -52,7 +52,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS_DT=y
diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig
index 06902b6..aaab4c8 100644
--- a/configs/colibri_imx7_emmc_defconfig
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -54,7 +54,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index 75498fd..1d48fc9 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -58,7 +58,7 @@
 CONFIG_VYBRID_GPIO=y
 CONFIG_DM_MMC=y
 # CONFIG_MMC_HW_PARTITIONING is not set
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_NAND_VF610_NFC_DT=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 68c7bec..3894d19 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -10,6 +10,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x800
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_OFFSET=0x100000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,MACH_TYPE=2066,SYS_USE_NANDFLASH"
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index d71bbce..3b24dd3 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -46,7 +46,7 @@
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/display5_defconfig b/configs/display5_defconfig
index 3b793f4..938414c 100644
--- a/configs/display5_defconfig
+++ b/configs/display5_defconfig
@@ -64,7 +64,7 @@
 CONFIG_BOOTCOUNT_LIMIT=y
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD_DEVICE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig
index 0d9eed3..40df91a 100644
--- a/configs/display5_factory_defconfig
+++ b/configs/display5_factory_defconfig
@@ -65,7 +65,7 @@
 CONFIG_DFU_MMC=y
 CONFIG_DFU_SF=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD_DEVICE=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/dms-ba16-1g_defconfig b/configs/dms-ba16-1g_defconfig
index 980f7b4..4231adb 100644
--- a/configs/dms-ba16-1g_defconfig
+++ b/configs/dms-ba16-1g_defconfig
@@ -33,7 +33,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DWC_AHSATA=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/dms-ba16_defconfig b/configs/dms-ba16_defconfig
index bea75b5..f98088d 100644
--- a/configs/dms-ba16_defconfig
+++ b/configs/dms-ba16_defconfig
@@ -32,7 +32,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DWC_AHSATA=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index 5f9e84a..d23ca8a 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_DRACO=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index 8996858..aded18f 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -10,6 +10,8 @@
 CONFIG_TARGET_ETAMIN=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x980000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 2ec3aae..99cccdb 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x27000000
 CONFIG_TARGET_ETHERNUT5=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x21000
+CONFIG_ENV_OFFSET=0x3DE000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9XE"
 CONFIG_BOOTDELAY=3
@@ -47,6 +49,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x21000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig
index a25d378..e0df5f4 100644
--- a/configs/gardena-smart-gateway-at91sam_defconfig
+++ b/configs/gardena-smart-gateway-at91sam_defconfig
@@ -8,6 +8,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x10000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
@@ -52,6 +53,9 @@
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9g25-gardena-smart-gateway"
 CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupts interrupt-parent interrupts-extended dmas dma-names"
 CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="ubi"
+CONFIG_ENV_UBI_VOLUME="env"
+CONFIG_ENV_UBI_VOLUME_REDUND="env_r"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 8be881b..60bdcd6 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -43,7 +43,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
index d19f485..5001385 100644
--- a/configs/gurnard_defconfig
+++ b/configs/gurnard_defconfig
@@ -2,6 +2,8 @@
 CONFIG_ARCH_AT91=y
 CONFIG_SYS_TEXT_BASE=0x73f00000
 CONFIG_TARGET_GURNARD=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x80000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G45"
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index f9857d1..19aa73f 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -63,7 +63,7 @@
 CONFIG_DWC_AHSATA=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD_DEVICE=y
 CONFIG_PHYLIB=y
 CONFIG_E1000=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 27ef264..1461cb1 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -63,7 +63,7 @@
 CONFIG_DWC_AHSATA=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD_DEVICE=y
 CONFIG_PHYLIB=y
 CONFIG_MV88E61XX_SWITCH=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 25af087..f440363 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -65,7 +65,7 @@
 CONFIG_DWC_AHSATA=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index bc77069..ab11935 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_ENV_SIZE=0x8000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
@@ -16,6 +17,18 @@
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 # CONFIG_SPL_FS_EXT4 is not set
 CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_UBI=y
+CONFIG_SPL_UBI_MAX_VOL_LEBS=256
+CONFIG_SPL_UBI_MAX_PEB_SIZE=262144
+CONFIG_SPL_UBI_MAX_PEBS=4096
+CONFIG_SPL_UBI_PEB_OFFSET=4
+CONFIG_SPL_UBI_VID_OFFSET=512
+CONFIG_SPL_UBI_LEB_START=2048
+CONFIG_SPL_UBI_INFO_ADDR=0x88080000
+CONFIG_SPL_UBI_VOL_IDS=8
+CONFIG_SPL_UBI_LOAD_MONITOR_ID=0
+CONFIG_SPL_UBI_LOAD_KERNEL_ID=3
+CONFIG_SPL_UBI_LOAD_ARGS_ID=4
 CONFIG_SPL_ONENAND_SUPPORT=y
 CONFIG_SPL_OS_BOOT=y
 CONFIG_CMD_SPL=y
@@ -29,6 +42,10 @@
 # CONFIG_CMD_UBIFS is not set
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="omap3-igep0020"
+CONFIG_ENV_IS_IN_UBI=y
+CONFIG_ENV_UBI_PART="UBI"
+CONFIG_ENV_UBI_VOLUME="config"
+CONFIG_ENV_UBI_VOLUME_REDUND="config_r"
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM_MMC=y
 CONFIG_MMC_OMAP_HS=y
diff --git a/configs/imx6dl_icore_nand_defconfig b/configs/imx6dl_icore_nand_defconfig
index 3db7082..6801ff0 100644
--- a/configs/imx6dl_icore_nand_defconfig
+++ b/configs/imx6dl_icore_nand_defconfig
@@ -39,7 +39,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig
index c27c5cc..dbf230c 100644
--- a/configs/imx6dl_mamoj_defconfig
+++ b/configs/imx6dl_mamoj_defconfig
@@ -32,7 +32,7 @@
 CONFIG_FASTBOOT_FLASH_MMC_DEV=2
 CONFIG_SYS_I2C_MXC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/imx6q_icore_nand_defconfig b/configs/imx6q_icore_nand_defconfig
index ad4b930..1657298 100644
--- a/configs/imx6q_icore_nand_defconfig
+++ b/configs/imx6q_icore_nand_defconfig
@@ -40,7 +40,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 0bb2fc6..cf6964b 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -63,7 +63,7 @@
 CONFIG_PCF8575_GPIO=y
 CONFIG_LED=y
 CONFIG_LED_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig
index f6fc59f..d52b18c 100644
--- a/configs/imx6qdl_icore_mipi_defconfig
+++ b/configs/imx6qdl_icore_mipi_defconfig
@@ -44,7 +44,7 @@
 CONFIG_OF_LIST="imx6q-icore-mipi imx6dl-icore-mipi"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
 CONFIG_FEC_MXC=y
diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index 5ab932d..68e371d 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -54,7 +54,7 @@
 CONFIG_BOOTCOUNT_BOOTLIMIT=3
 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
index ad4b930..1657298 100644
--- a/configs/imx6qdl_icore_nand_defconfig
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -40,7 +40,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6q-icore"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig
index 4b89981..3d164c0 100644
--- a/configs/imx6qdl_icore_rqs_defconfig
+++ b/configs/imx6qdl_icore_rqs_defconfig
@@ -41,7 +41,7 @@
 CONFIG_OF_LIST="imx6q-icore-rqs imx6dl-icore-rqs"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig
index d5fdc43..4d3bef8 100644
--- a/configs/imx6ul_geam_mmc_defconfig
+++ b/configs/imx6ul_geam_mmc_defconfig
@@ -38,7 +38,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
 CONFIG_FEC_MXC=y
diff --git a/configs/imx6ul_geam_nand_defconfig b/configs/imx6ul_geam_nand_defconfig
index ea4d7ad..68e16bb 100644
--- a/configs/imx6ul_geam_nand_defconfig
+++ b/configs/imx6ul_geam_nand_defconfig
@@ -41,7 +41,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-geam"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig
index 88b9b49..92f5bd0 100644
--- a/configs/imx6ul_isiot_emmc_defconfig
+++ b/configs/imx6ul_isiot_emmc_defconfig
@@ -38,7 +38,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-emmc"
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
 CONFIG_FEC_MXC=y
diff --git a/configs/imx6ul_isiot_nand_defconfig b/configs/imx6ul_isiot_nand_defconfig
index c60bde7..8ed5ea4 100644
--- a/configs/imx6ul_isiot_nand_defconfig
+++ b/configs/imx6ul_isiot_nand_defconfig
@@ -41,7 +41,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-isiot-nand"
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index f02b5e2..8417c3b 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -30,6 +30,7 @@
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_DM_ETH=y
 CONFIG_PINCTRL=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 6db0669..aa23b9c 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -51,6 +51,7 @@
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
 CONFIG_PHY_ATHEROS=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index d735d34..39e5f5e 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -55,6 +55,7 @@
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_MISC=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/kp_imx53_defconfig b/configs/kp_imx53_defconfig
index a6a727b..86d6727 100644
--- a/configs/kp_imx53_defconfig
+++ b/configs/kp_imx53_defconfig
@@ -31,7 +31,7 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
 CONFIG_FEC_MXC=y
diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig
index 0ca83cb..87b25e6 100644
--- a/configs/kp_imx6q_tpc_defconfig
+++ b/configs/kp_imx6q_tpc_defconfig
@@ -34,6 +34,7 @@
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_EFI_PARTITION is not set
 CONFIG_ENV_IS_IN_MMC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_ATHEROS=y
 CONFIG_FEC_MXC=y
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index a439631..456f1e3 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -39,7 +39,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_DM_ETH=y
 CONFIG_MII=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index a4ae87b..3b1568f 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -31,6 +31,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index aa3256f..08eedec 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -32,6 +32,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_WINBOND=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index 827d4ec..64c59d9 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -31,6 +31,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index cbeb9ca..7af253c 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -32,6 +32,7 @@
 CONFIG_DM=y
 CONFIG_SATA_CEVA=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 # CONFIG_SPI_FLASH_BAR is not set
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index 7cd2f59..ef78f0d 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -32,6 +32,7 @@
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index 7982ce4..93d22a2 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -35,6 +35,7 @@
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 3432f90..a2a2181 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -32,6 +32,7 @@
 CONFIG_SCSI_AHCI=y
 CONFIG_SATA_CEVA=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index c65e37d..2d0c2b1 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -35,6 +35,7 @@
 CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DM_MMC=y
+CONFIG_FSL_ESDHC=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index 5a1fbf5..3a5fa26 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -60,7 +60,7 @@
 CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXC=y
 CONFIG_PHYLIB=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 8607760..f6e351f 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -21,7 +21,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index af2a106..7816200 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -29,7 +29,7 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index aac433c..522207a 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -30,7 +30,7 @@
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_MTD_DEVICE=y
diff --git a/configs/meesc_dataflash_defconfig b/configs/meesc_dataflash_defconfig
index 476700c..0bef67e 100644
--- a/configs/meesc_dataflash_defconfig
+++ b/configs/meesc_dataflash_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x21F00000
 CONFIG_TARGET_MEESC=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4200
+CONFIG_ENV_OFFSET=0x4200
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
@@ -22,6 +24,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x210
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/meesc_defconfig b/configs/meesc_defconfig
index 0e49d82..970e8b8 100644
--- a/configs/meesc_defconfig
+++ b/configs/meesc_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x21F00000
 CONFIG_TARGET_MEESC=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0xC0000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_NANDFLASH"
diff --git a/configs/mx25pdk_defconfig b/configs/mx25pdk_defconfig
index c024d79..a6ee105 100644
--- a/configs/mx25pdk_defconfig
+++ b/configs/mx25pdk_defconfig
@@ -19,7 +19,7 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_DOS_PARTITION=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT=y
diff --git a/configs/mx35pdk_defconfig b/configs/mx35pdk_defconfig
index 7fec4b6..3d36045 100644
--- a/configs/mx35pdk_defconfig
+++ b/configs/mx35pdk_defconfig
@@ -26,7 +26,7 @@
 # CONFIG_PARTITION_UUIDS is not set
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index ffb821e..42b37af 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -21,7 +21,7 @@
 CONFIG_CMD_DATE=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_SPI=y
 CONFIG_MXC_SPI=y
diff --git a/configs/mx53ard_defconfig b/configs/mx53ard_defconfig
index ea1d3f6..cf85c42 100644
--- a/configs/mx53ard_defconfig
+++ b/configs/mx53ard_defconfig
@@ -15,7 +15,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXC=y
 CONFIG_MII=y
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index bf48966..e57d0df 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig
@@ -26,7 +26,7 @@
 CONFIG_FPGA_CYCLON2=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_FEC_MXC=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
diff --git a/configs/mx53evk_defconfig b/configs/mx53evk_defconfig
index 67582b5..ab9e485 100644
--- a/configs/mx53evk_defconfig
+++ b/configs/mx53evk_defconfig
@@ -14,6 +14,6 @@
 CONFIG_CMD_DATE=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index a7adeff..2c76b83 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -23,7 +23,7 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_MX5=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index 19ebab7..a88af15 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -39,7 +39,7 @@
 CONFIG_BOOTCOUNT_BOOTLIMIT=10
 CONFIG_SYS_BOOTCOUNT_EXT_DEVPART="0:5"
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX5=y
diff --git a/configs/mx53smd_defconfig b/configs/mx53smd_defconfig
index 8c3e40f..2454956 100644
--- a/configs/mx53smd_defconfig
+++ b/configs/mx53smd_defconfig
@@ -14,6 +14,6 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index f13e688..cc2ed9a 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -33,7 +33,7 @@
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_DM_THERMAL=y
diff --git a/configs/mx6dlarm2_defconfig b/configs/mx6dlarm2_defconfig
index 35f8183..866e0b5 100644
--- a/configs/mx6dlarm2_defconfig
+++ b/configs/mx6dlarm2_defconfig
@@ -26,7 +26,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx6dlarm2_lpddr2_defconfig b/configs/mx6dlarm2_lpddr2_defconfig
index 0e68df0..98ae70e 100644
--- a/configs/mx6dlarm2_lpddr2_defconfig
+++ b/configs/mx6dlarm2_lpddr2_defconfig
@@ -26,7 +26,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx6qarm2_defconfig b/configs/mx6qarm2_defconfig
index 304d1dc..8056e53 100644
--- a/configs/mx6qarm2_defconfig
+++ b/configs/mx6qarm2_defconfig
@@ -26,7 +26,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx6qarm2_lpddr2_defconfig b/configs/mx6qarm2_lpddr2_defconfig
index bbdc771..27c215f 100644
--- a/configs/mx6qarm2_lpddr2_defconfig
+++ b/configs/mx6qarm2_lpddr2_defconfig
@@ -26,7 +26,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MII=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index 03bddda..0d402f2 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -34,7 +34,7 @@
 CONFIG_DWC_AHSATA=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 558b1cd..02f972a 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -62,7 +62,7 @@
 CONFIG_DFU_SF=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index 0739c58..9400805 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -74,7 +74,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 50cc225..643cad4 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -34,7 +34,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index d2be52f..3dada99 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -34,7 +34,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 4841dc6..63a7a74 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -43,7 +43,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
index 4dcac21..81f5fa5 100644
--- a/configs/mx6sllevk_defconfig
+++ b/configs/mx6sllevk_defconfig
@@ -30,7 +30,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
index 090ab06..565dc89 100644
--- a/configs/mx6sllevk_plugin_defconfig
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -31,7 +31,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX6=y
 CONFIG_DM_PMIC=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index f7ae29e..11c2a82 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -34,7 +34,7 @@
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index 4e516c5..135961a 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -38,7 +38,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig
index 159f079..21c9366 100644
--- a/configs/mx6sxsabresd_spl_defconfig
+++ b/configs/mx6sxsabresd_spl_defconfig
@@ -47,7 +47,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PCI=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index 2fc7119..1d777b5 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -44,7 +44,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 8816f6a..1014bd8 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -44,7 +44,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 7902465..f4681a6 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -30,7 +30,7 @@
 CONFIG_DM_74X164=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index c52de80..6fb30ce 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -31,7 +31,7 @@
 CONFIG_DM_74X164=y
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index b2ca4f9..45901f0 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -48,7 +48,7 @@
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_EON=y
 CONFIG_PHYLIB=y
diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig
index 27a8387..2f56698 100644
--- a/configs/mx7dsabresd_qspi_defconfig
+++ b/configs/mx7dsabresd_qspi_defconfig
@@ -48,7 +48,7 @@
 CONFIG_MMC_IO_VOLTAGE=y
 CONFIG_MMC_UHS_SUPPORT=y
 CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index d125ccc..d4eba65 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -22,7 +22,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7ULP=y
 CONFIG_DM_REGULATOR=y
diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index fcead94..ae8d4b4 100644
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -21,7 +21,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7ULP=y
 CONFIG_DM_REGULATOR=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index dff3770..015675b 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -36,7 +36,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index 95fdb4a..ee353f2 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -36,7 +36,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 05f0a21..ebd9bf8 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -38,7 +38,7 @@
 CONFIG_DWC_AHSATA=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 5ac4a33..d324282 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -38,7 +38,7 @@
 CONFIG_DWC_AHSATA=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index 69cd12d..b26bce4 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -36,7 +36,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 2e3d62f..a2fb07f 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -36,7 +36,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=25000000
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 2a7807d..9337428 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -49,7 +49,7 @@
 CONFIG_DWC_AHSATA=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/omap3_overo_defconfig b/configs/omap3_overo_defconfig
index ff968b3..5986791 100644
--- a/configs/omap3_overo_defconfig
+++ b/configs/omap3_overo_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_TARGET_OMAP3_OVERO=y
+CONFIG_ENV_OFFSET=0x240000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index 1d7f21a..7f251ac 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -5,6 +5,7 @@
 CONFIG_OMAP44XX=y
 CONFIG_TARGET_OMAP4_SDP4430=y
 CONFIG_CMD_BAT=y
+CONFIG_ENV_OFFSET=0xE0000
 CONFIG_SPL=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig
index b0ec120..4f8bc28 100644
--- a/configs/opos6uldev_defconfig
+++ b/configs/opos6uldev_defconfig
@@ -68,7 +68,7 @@
 CONFIG_SYS_I2C_MXC=y
 CONFIG_PWRSEQ=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/ot1200_defconfig b/configs/ot1200_defconfig
index f0fe375..02c6d71 100644
--- a/configs/ot1200_defconfig
+++ b/configs/ot1200_defconfig
@@ -31,7 +31,7 @@
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
 CONFIG_CMD_PCA953X=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/ot1200_spl_defconfig b/configs/ot1200_spl_defconfig
index 9bc22fe..dd74591 100644
--- a/configs/ot1200_spl_defconfig
+++ b/configs/ot1200_spl_defconfig
@@ -41,7 +41,7 @@
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
 CONFIG_CMD_PCA953X=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=2
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 171341b..b7e3d04 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -39,7 +39,7 @@
 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_NAND_VF610_NFC_DT=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index c461459..f7e5faa 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -43,7 +43,7 @@
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig
index b0c0520..c4539e9 100644
--- a/configs/pengwyn_defconfig
+++ b/configs/pengwyn_defconfig
@@ -7,6 +7,7 @@
 CONFIG_TARGET_PENGWYN=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/pfla02_defconfig b/configs/pfla02_defconfig
index aeab883..f710d0d 100644
--- a/configs/pfla02_defconfig
+++ b/configs/pfla02_defconfig
@@ -42,7 +42,7 @@
 CONFIG_CMD_UBI=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig
index a051a8d..cf43b43 100644
--- a/configs/phycore_pcl063_defconfig
+++ b/configs/phycore_pcl063_defconfig
@@ -35,7 +35,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6ul-phycore-segin"
 CONFIG_DM_I2C_GPIO=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig
index 5c07b95..ff0cd6c 100644
--- a/configs/phycore_pcl063_ull_defconfig
+++ b/configs/phycore_pcl063_ull_defconfig
@@ -30,7 +30,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-phycore-segin"
 CONFIG_DM_I2C_GPIO=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_FEC_MXC=y
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index bb6a9e4..55f25d5 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -46,7 +46,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index 9545d6b..bc34e99 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -52,7 +52,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 3284680..0345263 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -48,7 +48,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index 932ed4c..b609b6d 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -43,7 +43,7 @@
 CONFIG_DFU_MMC=y
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index 92ab9c5..f23bbf7 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -52,7 +52,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index d52c09e..2e23c7b 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -46,7 +46,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index 042affe..14c0817 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -52,7 +52,7 @@
 CONFIG_DM_GPIO=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
diff --git a/configs/picosam9g45_defconfig b/configs/picosam9g45_defconfig
index 6a087b4..abae023 100644
--- a/configs/picosam9g45_defconfig
+++ b/configs/picosam9g45_defconfig
@@ -8,6 +8,7 @@
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
diff --git a/configs/platinum_picon_defconfig b/configs/platinum_picon_defconfig
index 786f6a4..130d8ac 100644
--- a/configs/platinum_picon_defconfig
+++ b/configs/platinum_picon_defconfig
@@ -47,7 +47,7 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),495M(ubi0),14M(res0),2M(res1),512k(res2),512k(res3),-(ubi1)"
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/platinum_titanium_defconfig b/configs/platinum_titanium_defconfig
index c45abb0..71914ad 100644
--- a/configs/platinum_titanium_defconfig
+++ b/configs/platinum_titanium_defconfig
@@ -47,7 +47,7 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:14M(spl),2M(uboot),512k(env1),512k(env2),-(ubi)"
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/pm9261_defconfig b/configs/pm9261_defconfig
index d2c4c25..4a74932 100644
--- a/configs/pm9261_defconfig
+++ b/configs/pm9261_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0
 CONFIG_TARGET_PM9261=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9261"
 CONFIG_BOOTDELAY=3
@@ -29,6 +31,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9261ek"
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/pm9263_defconfig b/configs/pm9263_defconfig
index ceb7efe..1c948b2 100644
--- a/configs/pm9263_defconfig
+++ b/configs/pm9263_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0
 CONFIG_TARGET_PM9263=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x40000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263"
 CONFIG_BOOTDELAY=3
@@ -29,6 +31,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91sam9263ek"
 CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x10000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index 1a5955a..31f5888 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_PXM2=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index e5052bb..efd6e49 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_RASTABAN=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index 6b0d7e5..0b6304e 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -22,7 +22,7 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/riotboard_spl_defconfig b/configs/riotboard_spl_defconfig
index 1b61232..427bd9d 100644
--- a/configs/riotboard_spl_defconfig
+++ b/configs/riotboard_spl_defconfig
@@ -32,7 +32,7 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=20000000
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 50387d5..330f7e2 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_RUT=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
diff --git a/configs/s32v234evb_defconfig b/configs/s32v234evb_defconfig
index deb8c04..9eaa894 100644
--- a/configs/s32v234evb_defconfig
+++ b/configs/s32v234evb_defconfig
@@ -11,7 +11,7 @@
 CONFIG_CMD_MEMTEST=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LINFLEXUART=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index 205a439..85a8fe5 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xf8020000
@@ -67,6 +68,7 @@
 CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
@@ -80,6 +82,7 @@
 CONFIG_ATMEL_USART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 0a07800..ae2a4e6 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -67,6 +68,7 @@
 CONFIG_SF_DEFAULT_SPEED=66000000
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
@@ -80,6 +82,7 @@
 CONFIG_ATMEL_USART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
new file mode 100644
index 0000000..3226e0e
--- /dev/null
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x23f00000
+CONFIG_TARGET_SAMA5D27_SOM1_EK=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=66000000
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index e047108..dce4809 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xf801c000
diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig
index 25b3aaf..266c6d2 100644
--- a/configs/sama5d2_ptc_ek_mmc_defconfig
+++ b/configs/sama5d2_ptc_ek_mmc_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x26f00000
 CONFIG_TARGET_SAMA5D2_PTC_EK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xf801c000
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index f643b5a..b6b3730 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xf8020000
@@ -65,6 +66,10 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
@@ -76,6 +81,7 @@
 CONFIG_ATMEL_USART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index c25d67b..2e80ab4 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -67,6 +68,10 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
@@ -78,6 +83,7 @@
 CONFIG_ATMEL_USART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
new file mode 100644
index 0000000..6832283
--- /dev/null
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_ARCH_AT91=y
+CONFIG_SYS_TEXT_BASE=0x26f00000
+CONFIG_TARGET_SAMA5D2_XPLAINED=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BOARD_INIT=y
+CONFIG_DEBUG_UART_BASE=0xf8020000
+CONFIG_DEBUG_UART_CLOCK=83000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEBUG_UART=y
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC"
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait"
+CONFIG_MISC_INIT_R=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL_TEXT_BASE=0x200000
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_AT91=y
+CONFIG_AT91_UTMI=y
+CONFIG_AT91_H32MX=y
+CONFIG_AT91_GENERIC_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_ATMEL_PIO4=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_AT91=y
+CONFIG_I2C_EEPROM=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ATMEL=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_DM_ETH=y
+CONFIG_MACB=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_AT91PIO4=y
+CONFIG_DM_SERIAL=y
+CONFIG_DEBUG_UART_ATMEL=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ATMEL_USART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_ATMEL_PIT_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_ATMEL_USBA=y
+CONFIG_DM_VIDEO=y
+CONFIG_ATMEL_HLCD=y
+CONFIG_W1=y
+CONFIG_W1_GPIO=y
+CONFIG_W1_EEPROM=y
+CONFIG_W1_EEPROM_DS24XXX=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index ac5ae51..78df9b6 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -8,6 +8,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -43,6 +45,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained"
 CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
@@ -64,6 +67,10 @@
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=30000000
 CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
 CONFIG_DM_ETH=y
 CONFIG_MACB=y
 CONFIG_PINCTRL=y
@@ -75,6 +82,7 @@
 CONFIG_ATMEL_USART=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
+CONFIG_ATMEL_QSPI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_ATMEL_PIT_TIMER=y
diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig
index e61f897..bc20f17 100644
--- a/configs/sama5d36ek_cmp_mmc_defconfig
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -3,6 +3,7 @@
 CONFIG_SYS_TEXT_BASE=0x26f00000
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index 4a876e3..eddeead 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x26f00000
 CONFIG_TARGET_SAMA5D3XEK=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEBUG_UART_BOARD_INIT=y
 CONFIG_DEBUG_UART_BASE=0xffffee00
@@ -32,6 +34,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek_cmp"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_CLK=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index d5021eb..6e9d65c 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index b770ac4..ea565ec 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 84bbf9c..9bf9e4f 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -8,6 +8,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -44,6 +46,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="sama5d36ek"
 CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index 0504b4e..755ff0b 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index f108689..b12c476 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -8,6 +8,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -42,6 +44,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4_xplained"
 CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index d7e1701..2dd75c3 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -9,6 +9,7 @@
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index 8db517d..1b6c19f 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -8,6 +8,8 @@
 CONFIG_SYS_MALLOC_F_LEN=0x2000
 CONFIG_SPL_SERIAL_SUPPORT=y
 CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x6000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_DEBUG_UART_BOARD_INIT=y
@@ -42,6 +44,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d4ek"
 CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dma-names dmas"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
diff --git a/configs/secomx6quq7_defconfig b/configs/secomx6quq7_defconfig
index 8526f05..40ca954 100644
--- a/configs/secomx6quq7_defconfig
+++ b/configs/secomx6quq7_defconfig
@@ -26,7 +26,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/sksimx6_defconfig b/configs/sksimx6_defconfig
index 164614d..748b13e 100644
--- a/configs/sksimx6_defconfig
+++ b/configs/sksimx6_defconfig
@@ -33,7 +33,7 @@
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 656188f..e8d846f 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -11,6 +11,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index 7ce29bf..be71dc8 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -2,6 +2,8 @@
 CONFIG_ARCH_AT91=y
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_SNAPPER9260=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x80000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260"
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index 2773c6b..aca456e 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -2,6 +2,8 @@
 CONFIG_ARCH_AT91=y
 CONFIG_SYS_TEXT_BASE=0x21f00000
 CONFIG_TARGET_SNAPPER9260=y
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_OFFSET=0x80000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_FIT=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20"
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index 4aa184f..79687d3 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -52,6 +52,7 @@
 CONFIG_ENV_EXT4_FILE="/uboot.env"
 CONFIG_ENV_UBI_PART="UBI"
 CONFIG_ENV_UBI_VOLUME="uboot_config"
+CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
 CONFIG_STM32_ADC=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 5fe9477..e1ab2ab 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -44,6 +44,7 @@
 CONFIG_ENV_EXT4_FILE="/uboot.env"
 CONFIG_ENV_UBI_PART="UBI"
 CONFIG_ENV_UBI_VOLUME="uboot_config"
+CONFIG_ENV_UBI_VOLUME_REDUND="uboot_config_r"
 CONFIG_STM32_ADC=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0xC0000000
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index ee21811..403c0b6 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -13,6 +13,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_OFFSET=0x100000
 CONFIG_SPL_SYS_MALLOC_F_LEN=0x1000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index ba42603..17c90a7 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -48,7 +48,7 @@
 CONFIG_SYS_I2C_MXC=y
 CONFIG_DM_KEYBOARD=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PCI=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index 67012f8..68ce230 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -10,6 +10,7 @@
 CONFIG_TARGET_THUBAN=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index bf877f5..19519f8 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -7,6 +7,8 @@
 CONFIG_TARGET_TI816X_EVM=y
 CONFIG_SPL_MMC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x001c0000
 CONFIG_SPL=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
diff --git a/configs/titanium_defconfig b/configs/titanium_defconfig
index 1e19240..2816f66 100644
--- a/configs/titanium_defconfig
+++ b/configs/titanium_defconfig
@@ -34,7 +34,7 @@
 CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:16M(uboot),512k(env1),512k(env2),-(ubi)"
 CONFIG_CMD_UBI=y
 CONFIG_ENV_IS_IN_NAND=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND=y
 CONFIG_NAND_MXS=y
 CONFIG_PHYLIB=y
diff --git a/configs/tqma6dl_mba6_mmc_defconfig b/configs/tqma6dl_mba6_mmc_defconfig
index bc54005..887f938 100644
--- a/configs/tqma6dl_mba6_mmc_defconfig
+++ b/configs/tqma6dl_mba6_mmc_defconfig
@@ -32,7 +32,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6dl_mba6_spi_defconfig b/configs/tqma6dl_mba6_spi_defconfig
index 58d08bf..6abefa3 100644
--- a/configs/tqma6dl_mba6_spi_defconfig
+++ b/configs/tqma6dl_mba6_spi_defconfig
@@ -33,7 +33,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6q_mba6_mmc_defconfig b/configs/tqma6q_mba6_mmc_defconfig
index b57cb81..67aae05 100644
--- a/configs/tqma6q_mba6_mmc_defconfig
+++ b/configs/tqma6q_mba6_mmc_defconfig
@@ -31,7 +31,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6q_mba6_spi_defconfig b/configs/tqma6q_mba6_spi_defconfig
index c713fac..6ecba56 100644
--- a/configs/tqma6q_mba6_spi_defconfig
+++ b/configs/tqma6q_mba6_spi_defconfig
@@ -32,7 +32,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6s_mba6_mmc_defconfig b/configs/tqma6s_mba6_mmc_defconfig
index d9d3ce9..d291d0f 100644
--- a/configs/tqma6s_mba6_mmc_defconfig
+++ b/configs/tqma6s_mba6_mmc_defconfig
@@ -32,7 +32,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6s_mba6_spi_defconfig b/configs/tqma6s_mba6_spi_defconfig
index f793658..b5acd0e 100644
--- a/configs/tqma6s_mba6_spi_defconfig
+++ b/configs/tqma6s_mba6_spi_defconfig
@@ -33,7 +33,7 @@
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
 CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/tqma6s_wru4_mmc_defconfig b/configs/tqma6s_wru4_mmc_defconfig
index 57f2221..f2a8376 100644
--- a/configs/tqma6s_wru4_mmc_defconfig
+++ b/configs/tqma6s_wru4_mmc_defconfig
@@ -59,7 +59,7 @@
 CONFIG_LED_STATUS_STATE5=2
 CONFIG_LED_STATUS_CMD=y
 CONFIG_PCA9551_LED=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_USB=y
diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig
index 973c5ac..53e8256 100644
--- a/configs/tricorder_defconfig
+++ b/configs/tricorder_defconfig
@@ -2,6 +2,8 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x80100000
 CONFIG_TARGET_TRICORDER=y
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x120000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_BOOTDELAY=0
diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig
index 1dc2992..85ff2bf 100644
--- a/configs/tricorder_flash_defconfig
+++ b/configs/tricorder_flash_defconfig
@@ -2,6 +2,7 @@
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_SYS_TEXT_BASE=0x80100000
 CONFIG_TARGET_TRICORDER=y
+CONFIG_ENV_SIZE=0x4000
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD"
diff --git a/configs/ts4800_defconfig b/configs/ts4800_defconfig
index 68404e3..208366e 100644
--- a/configs/ts4800_defconfig
+++ b/configs/ts4800_defconfig
@@ -15,7 +15,7 @@
 CONFIG_CMD_PING=y
 CONFIG_CMD_FAT=y
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_SPI=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 317592b..259ffee 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -29,7 +29,7 @@
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_DM=y
 CONFIG_DWC_AHSATA=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index e8df11d..4f00e48 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -28,7 +28,7 @@
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_PHY_MICREL_KSZ8XXX=y
diff --git a/configs/usb_a9263_dataflash_defconfig b/configs/usb_a9263_dataflash_defconfig
index 3b9e4a5..5d19809 100644
--- a/configs/usb_a9263_dataflash_defconfig
+++ b/configs/usb_a9263_dataflash_defconfig
@@ -3,6 +3,8 @@
 CONFIG_SYS_TEXT_BASE=0x23f00000
 CONFIG_TARGET_USB_A9263=y
 CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0x2000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9263,SYS_USE_DATAFLASH"
 CONFIG_BOOTDELAY=3
@@ -27,6 +29,7 @@
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_USE_ENV_SPI_MAX_HZ=y
 CONFIG_ENV_SPI_MAX_HZ=15000000
+CONFIG_ENV_SECT_SIZE=0x2000
 CONFIG_DM=y
 CONFIG_CLK=y
 CONFIG_CLK_AT91=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 3c1eaf6..77a3a23 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -13,7 +13,7 @@
 CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_ENV_IS_IN_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_MX5=y
 CONFIG_OF_LIBFDT=y
diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig
index f55c386..55f4ff5 100644
--- a/configs/variscite_dart6ul_defconfig
+++ b/configs/variscite_dart6ul_defconfig
@@ -30,7 +30,7 @@
 CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
 CONFIG_DM_I2C_GPIO=y
 CONFIG_SYS_I2C_MXC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_MICREL=y
 CONFIG_FEC_MXC=y
diff --git a/configs/vf610twr_defconfig b/configs/vf610twr_defconfig
index dc67ddc..3ad60e6 100644
--- a/configs/vf610twr_defconfig
+++ b/configs/vf610twr_defconfig
@@ -32,7 +32,7 @@
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_PHYLIB=y
diff --git a/configs/vf610twr_nand_defconfig b/configs/vf610twr_nand_defconfig
index 7fcb630..d7598c4 100644
--- a/configs/vf610twr_nand_defconfig
+++ b/configs/vf610twr_nand_defconfig
@@ -32,7 +32,7 @@
 CONFIG_DM=y
 CONFIG_DM_GPIO=y
 CONFIG_VYBRID_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_NAND_VF610_NFC=y
 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
 CONFIG_PHYLIB=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index 745aa85..92fdc93 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -2,6 +2,8 @@
 CONFIG_ARCH_AT91=y
 CONFIG_SYS_TEXT_BASE=0x20f00000
 CONFIG_TARGET_VINCO=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x10000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_VARS_UBOOT_CONFIG=y
 CONFIG_SPI_BOOT=y
@@ -27,6 +29,7 @@
 CONFIG_OF_CONTROL=y
 CONFIG_DEFAULT_DEVICE_TREE="at91-vinco"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_SECT_SIZE=0x1000
 CONFIG_SUPPORT_EMMC_BOOT=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 9e8326e..7364c67 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -42,7 +42,7 @@
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_RPMB=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PCI=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index f1d6cc5..c4a9624 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -54,7 +54,7 @@
 CONFIG_SYS_I2C_MXC_I2C2=y
 CONFIG_SYS_I2C_MXC_I2C3=y
 CONFIG_DM_MMC=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_PINCTRL=y
diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
index a79f670..8a4e294 100644
--- a/configs/warp7_bl33_defconfig
+++ b/configs/warp7_bl33_defconfig
@@ -30,7 +30,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_DM_PMIC=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 5b35113..11f16cf 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -39,7 +39,7 @@
 CONFIG_DM_I2C=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_IMX7=y
 CONFIG_DM_PMIC=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index a37d769..0f911a9 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -30,7 +30,7 @@
 # CONFIG_NET is not set
 CONFIG_DFU_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_USB=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_GADGET=y
diff --git a/configs/wb45n_defconfig b/configs/wb45n_defconfig
index 8da284a..16fb444 100644
--- a/configs/wb45n_defconfig
+++ b/configs/wb45n_defconfig
@@ -7,6 +7,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_OFFSET=0xa0000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/wb50n_defconfig b/configs/wb50n_defconfig
index 71a95b3..417eda3 100644
--- a/configs/wb50n_defconfig
+++ b/configs/wb50n_defconfig
@@ -6,6 +6,7 @@
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_ENV_OFFSET=0xA0000
 CONFIG_NR_DRAM_BANKS=1
 CONFIG_SPL=y
 CONFIG_FIT=y
diff --git a/configs/woodburn_defconfig b/configs/woodburn_defconfig
index ebc12ab..73b76aa 100644
--- a/configs/woodburn_defconfig
+++ b/configs/woodburn_defconfig
@@ -28,7 +28,7 @@
 # CONFIG_PARTITION_UUIDS is not set
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/woodburn_sd_defconfig b/configs/woodburn_sd_defconfig
index 7182aff..72e6ab4 100644
--- a/configs/woodburn_sd_defconfig
+++ b/configs/woodburn_sd_defconfig
@@ -40,7 +40,7 @@
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_MXC_GPIO=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_FLASH_CFI_DRIVER=y
 CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/xpress_defconfig b/configs/xpress_defconfig
index 709a7ef..64fed1d 100644
--- a/configs/xpress_defconfig
+++ b/configs/xpress_defconfig
@@ -26,7 +26,7 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_USB=y
diff --git a/configs/xpress_spl_defconfig b/configs/xpress_spl_defconfig
index e79a038..c203353 100644
--- a/configs/xpress_spl_defconfig
+++ b/configs/xpress_spl_defconfig
@@ -37,7 +37,7 @@
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_PHYLIB=y
 CONFIG_MII=y
 CONFIG_USB=y
diff --git a/configs/zc5202_defconfig b/configs/zc5202_defconfig
index ae3a6b3..1aee743 100644
--- a/configs/zc5202_defconfig
+++ b/configs/zc5202_defconfig
@@ -35,7 +35,7 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=3
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/zc5601_defconfig b/configs/zc5601_defconfig
index 65a1915..f361ad9 100644
--- a/configs/zc5601_defconfig
+++ b/configs/zc5601_defconfig
@@ -34,7 +34,7 @@
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
 CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_FSL_ESDHC=y
+CONFIG_FSL_ESDHC_IMX=y
 CONFIG_SPI_FLASH=y
 CONFIG_SF_DEFAULT_BUS=3
 CONFIG_SF_DEFAULT_MODE=0
diff --git a/disk/part_efi.c b/disk/part_efi.c
index c0fa753..3e02669 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -313,8 +313,8 @@
 		     - info->start;
 	info->blksz = dev_desc->blksz;
 
-	sprintf((char *)info->name, "%s",
-			print_efiname(&gpt_pte[part - 1]));
+	snprintf((char *)info->name, sizeof(info->name), "%s",
+		 print_efiname(&gpt_pte[part - 1]));
 	strcpy((char *)info->type, "U-Boot");
 	info->bootable = is_bootable(&gpt_pte[part - 1]);
 #if CONFIG_IS_ENABLED(PARTITION_UUIDS)
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index c23299e..9358872 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -668,8 +668,14 @@
 config FSL_ESDHC
 	bool "Freescale/NXP eSDHC controller support"
 	help
-	  This selects support for the eSDHC (enhanced secure digital host
-	  controller) found on numerous Freescale/NXP SoCs.
+	  This selects support for the eSDHC (Enhanced Secure Digital Host
+	  Controller) found on numerous Freescale/NXP SoCs.
+
+config FSL_ESDHC_IMX
+	bool "Freescale/NXP i.MX eSDHC controller support"
+	help
+	  This selects support for the i.MX eSDHC (Enhanced Secure Digital Host
+	  Controller) found on numerous Freescale/NXP SoCs.
 
 endmenu
 
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 0076fc3..3c8c53a 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -26,6 +26,7 @@
 obj-$(CONFIG_MMC_DW_SOCFPGA)		+= socfpga_dw_mmc.o
 obj-$(CONFIG_MMC_DW_SNPS)		+= snps_dw_mmc.o
 obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+obj-$(CONFIG_FSL_ESDHC_IMX) += fsl_esdhc_imx.o
 obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o
 obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o
 obj-$(CONFIG_MMC_MESON_GX) += meson_gx_mmc.o
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 6a191a1..0731847 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -17,14 +17,11 @@
 #include <hwconfig.h>
 #include <mmc.h>
 #include <part.h>
-#include <power/regulator.h>
 #include <malloc.h>
 #include <fsl_esdhc.h>
 #include <fdt_support.h>
 #include <asm/io.h>
 #include <dm.h>
-#include <asm-generic/gpio.h>
-#include <dm/pinctrl.h>
 
 #if !CONFIG_IS_ENABLED(BLK)
 #include "mmc_private.h"
@@ -38,7 +35,6 @@
 				IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
 				IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
 				IRQSTATEN_DINT)
-#define MAX_TUNING_LOOP 40
 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
 
 struct fsl_esdhc {
@@ -60,37 +56,20 @@
 	uint    autoc12err;	/* Auto CMD error status register */
 	uint    hostcapblt;	/* Host controller capabilities register */
 	uint    wml;		/* Watermark level register */
-	uint    mixctrl;	/* For USDHC */
-	char    reserved1[4];	/* reserved */
+	char    reserved1[8];	/* reserved */
 	uint    fevt;		/* Force event register */
 	uint    admaes;		/* ADMA error status register */
 	uint    adsaddr;	/* ADMA system address register */
-	char    reserved2[4];
-	uint    dllctrl;
-	uint    dllstat;
-	uint    clktunectrlstatus;
-	char    reserved3[4];
-	uint	strobe_dllctrl;
-	uint	strobe_dllstat;
-	char    reserved4[72];
-	uint    vendorspec;
-	uint    mmcboot;
-	uint    vendorspec2;
-	uint    tuning_ctrl;	/* on i.MX6/7/8 */
-	char	reserved5[44];
+	char    reserved2[160];
 	uint    hostver;	/* Host controller version register */
-	char    reserved6[4];	/* reserved */
+	char    reserved3[4];	/* reserved */
 	uint    dmaerraddr;	/* DMA error address register */
-	char    reserved7[4];	/* reserved */
+	char    reserved4[4];	/* reserved */
 	uint    dmaerrattr;	/* DMA error attribute register */
-	char    reserved8[4];	/* reserved */
+	char    reserved5[4];	/* reserved */
 	uint    hostcapblt2;	/* Host controller capabilities register 2 */
-	char    reserved9[8];	/* reserved */
-	uint    tcr;		/* Tuning control register */
-	char    reserved10[28];	/* reserved */
-	uint    sddirctl;	/* SD direction control register */
-	char    reserved11[712];/* reserved */
-	uint    scr;		/* eSDHC control register */
+	char    reserved6[756];	/* reserved */
+	uint    esdhcctl;	/* eSDHC control register */
 };
 
 struct fsl_esdhc_plat {
@@ -98,11 +77,6 @@
 	struct mmc mmc;
 };
 
-struct esdhc_soc_data {
-	u32 flags;
-	u32 caps;
-};
-
 /**
  * struct fsl_esdhc_priv
  *
@@ -115,13 +89,6 @@
  * @dev: pointer for the device
  * @non_removable: 0: removable; 1: non-removable
  * @wp_enable: 1: enable checking wp; 0: no check
- * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
- * @flags: ESDHC_FLAG_xx in include/fsl_esdhc.h
- * @caps: controller capabilities
- * @tuning_step: tuning step setting in tuning_ctrl register
- * @start_tuning_tap: the start point for tuning in tuning_ctrl register
- * @strobe_dll_delay_target: settings in strobe_dllctrl
- * @signal_voltage: indicating the current voltage
  * @cd_gpio: gpio for card detection
  * @wp_gpio: gpio for write protection
  */
@@ -130,7 +97,6 @@
 	unsigned int sdhc_clk;
 	struct clk per_clk;
 	unsigned int clock;
-	unsigned int mode;
 	unsigned int bus_width;
 #if !CONFIG_IS_ENABLED(BLK)
 	struct mmc *mmc;
@@ -138,21 +104,6 @@
 	struct udevice *dev;
 	int non_removable;
 	int wp_enable;
-	int vs18_enable;
-	u32 flags;
-	u32 caps;
-	u32 tuning_step;
-	u32 tuning_start_tap;
-	u32 strobe_dll_delay_target;
-	u32 signal_voltage;
-#if IS_ENABLED(CONFIG_DM_REGULATOR)
-	struct udevice *vqmmc_dev;
-	struct udevice *vmmc_dev;
-#endif
-#ifdef CONFIG_DM_GPIO
-	struct gpio_desc cd_gpio;
-	struct gpio_desc wp_gpio;
-#endif
 };
 
 /* Return the XFERTYP flags for a given command and data packet */
@@ -264,8 +215,7 @@
 {
 	int timeout;
 	struct fsl_esdhc *regs = priv->esdhc_regs;
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
 	dma_addr_t addr;
 #endif
 	uint wml_value;
@@ -278,8 +228,7 @@
 
 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
 		addr = virt_to_phys((void *)(data->dest));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -303,20 +252,12 @@
 				printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
 				return -ETIMEDOUT;
 			}
-		} else {
-#ifdef CONFIG_DM_GPIO
-			if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
-				printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
-				return -ETIMEDOUT;
-			}
-#endif
 		}
 
 		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
 					wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
 		addr = virt_to_phys((void *)(data->src));
 		if (upper_32_bits(addr))
 			printf("Error found for upper 32 bits\n");
@@ -381,8 +322,7 @@
 	unsigned end = 0;
 	unsigned size = roundup(ARCH_DMA_MINALIGN,
 				data->blocks*data->blocksize);
-#if defined(CONFIG_FSL_LAYERSCAPE) || defined(CONFIG_S32V234) || \
-	defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+#if defined(CONFIG_FSL_LAYERSCAPE)
 	dma_addr_t addr;
 
 	addr = virt_to_phys((void *)(data->dest));
@@ -396,25 +336,6 @@
 	end = start + size;
 	invalidate_dcache_range(start, end);
 }
-
-#ifdef CONFIG_MCF5441x
-/*
- * Swaps 32-bit words to little-endian byte order.
- */
-static inline void sd_swap_dma_buff(struct mmc_data *data)
-{
-	int i, size = data->blocksize >> 2;
-	u32 *buffer = (u32 *)data->dest;
-	u32 sw;
-
-	while (data->blocks--) {
-		for (i = 0; i < size; i++) {
-			sw = __sw32(*buffer);
-			*buffer++ = sw;
-		}
-	}
-}
-#endif
 
 /*
  * Sends a command out on the bus.  Takes the mmc pointer,
@@ -472,14 +393,7 @@
 
 	/* Send the command */
 	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
-#if defined(CONFIG_FSL_USDHC)
-	esdhc_write32(&regs->mixctrl,
-	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
-			| (mmc->ddr_mode ? XFERTYP_DDREN : 0));
-	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
-#else
 	esdhc_write32(&regs->xfertyp, xfertyp);
-#endif
 
 	if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
 	    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
@@ -506,15 +420,6 @@
 		goto out;
 	}
 
-	/* Switch voltage to 1.8V if CMD11 succeeded */
-	if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
-		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-
-		printf("Run CMD11 1.8V switch\n");
-		/* Sleep for 5 ms - max time for card to switch to 1.8V */
-		udelay(5000);
-	}
-
 	/* Workaround for ESDHC errata ENGcm03648 */
 	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
 		int timeout = 6000;
@@ -580,9 +485,6 @@
 		 */
 		if (data->flags & MMC_DATA_READ) {
 			check_and_invalidate_dcache_range(cmd, data);
-#ifdef CONFIG_MCF5441x
-			sd_swap_dma_buff(data);
-#endif
 		}
 #endif
 	}
@@ -602,10 +504,6 @@
 			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
 				;
 		}
-
-		/* If this was CMD11, then notify that power cycle is needed */
-		if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
-			printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
 	}
 
 	esdhc_write32(&regs->irqstat, -1);
@@ -617,16 +515,7 @@
 {
 	struct fsl_esdhc *regs = priv->esdhc_regs;
 	int div = 1;
-#ifdef ARCH_MXC
-#ifdef CONFIG_MX53
-	/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
-	int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
-#else
-	int pre_div = 1;
-#endif
-#else
 	int pre_div = 2;
-#endif
 	int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
 	int sdhc_clk = priv->sdhc_clk;
 	uint clk;
@@ -645,21 +534,13 @@
 
 	clk = (pre_div << 8) | (div << 4);
 
-#ifdef CONFIG_FSL_USDHC
-	esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
-#else
 	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
-#endif
 
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
 
 	udelay(10000);
 
-#ifdef CONFIG_FSL_USDHC
-	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
-#else
 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
-#endif
 
 	priv->clock = clock;
 }
@@ -690,320 +571,23 @@
 		time_out--;
 		mdelay(1);
 	}
-}
-#endif
-
-#ifdef MMC_SUPPORTS_TUNING
-static int esdhc_change_pinstate(struct udevice *dev)
-{
-	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
-	int ret;
-
-	switch (priv->mode) {
-	case UHS_SDR50:
-	case UHS_DDR50:
-		ret = pinctrl_select_state(dev, "state_100mhz");
-		break;
-	case UHS_SDR104:
-	case MMC_HS_200:
-	case MMC_HS_400:
-		ret = pinctrl_select_state(dev, "state_200mhz");
-		break;
-	default:
-		ret = pinctrl_select_state(dev, "default");
-		break;
-	}
-
-	if (ret)
-		printf("%s %d error\n", __func__, priv->mode);
-
-	return ret;
-}
-
-static void esdhc_reset_tuning(struct mmc *mmc)
-{
-	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
-	struct fsl_esdhc *regs = priv->esdhc_regs;
-
-	if (priv->flags & ESDHC_FLAG_USDHC) {
-		if (priv->flags & ESDHC_FLAG_STD_TUNING) {
-			esdhc_clrbits32(&regs->autoc12err,
-					MIX_CTRL_SMPCLK_SEL |
-					MIX_CTRL_EXE_TUNE);
-		}
-	}
-}
-
-static void esdhc_set_strobe_dll(struct mmc *mmc)
-{
-	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
-	struct fsl_esdhc *regs = priv->esdhc_regs;
-	u32 val;
-
-	if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
-		writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);
-
-		/*
-		 * enable strobe dll ctrl and adjust the delay target
-		 * for the uSDHC loopback read clock
-		 */
-		val = ESDHC_STROBE_DLL_CTRL_ENABLE |
-			(priv->strobe_dll_delay_target <<
-			 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
-		writel(val, &regs->strobe_dllctrl);
-		/* wait 1us to make sure strobe dll status register stable */
-		mdelay(1);
-		val = readl(&regs->strobe_dllstat);
-		if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
-			pr_warn("HS400 strobe DLL status REF not lock!\n");
-		if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
-			pr_warn("HS400 strobe DLL status SLV not lock!\n");
-	}
-}
-
-static int esdhc_set_timing(struct mmc *mmc)
-{
-	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
-	struct fsl_esdhc *regs = priv->esdhc_regs;
-	u32 mixctrl;
-
-	mixctrl = readl(&regs->mixctrl);
-	mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
-
-	switch (mmc->selected_mode) {
-	case MMC_LEGACY:
-	case SD_LEGACY:
-		esdhc_reset_tuning(mmc);
-		writel(mixctrl, &regs->mixctrl);
-		break;
-	case MMC_HS_400:
-		mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
-		writel(mixctrl, &regs->mixctrl);
-		esdhc_set_strobe_dll(mmc);
-		break;
-	case MMC_HS:
-	case MMC_HS_52:
-	case MMC_HS_200:
-	case SD_HS:
-	case UHS_SDR12:
-	case UHS_SDR25:
-	case UHS_SDR50:
-	case UHS_SDR104:
-		writel(mixctrl, &regs->mixctrl);
-		break;
-	case UHS_DDR50:
-	case MMC_DDR_52:
-		mixctrl |= MIX_CTRL_DDREN;
-		writel(mixctrl, &regs->mixctrl);
-		break;
-	default:
-		printf("Not supported %d\n", mmc->selected_mode);
-		return -EINVAL;
-	}
-
-	priv->mode = mmc->selected_mode;
-
-	return esdhc_change_pinstate(mmc->dev);
-}
-
-static int esdhc_set_voltage(struct mmc *mmc)
-{
-	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
-	struct fsl_esdhc *regs = priv->esdhc_regs;
-	int ret;
-
-	priv->signal_voltage = mmc->signal_voltage;
-	switch (mmc->signal_voltage) {
-	case MMC_SIGNAL_VOLTAGE_330:
-		if (priv->vs18_enable)
-			return -EIO;
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
-		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
-			ret = regulator_set_value(priv->vqmmc_dev, 3300000);
-			if (ret) {
-				printf("Setting to 3.3V error");
-				return -EIO;
-			}
-			/* Wait for 5ms */
-			mdelay(5);
-		}
-#endif
-
-		esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-		if (!(esdhc_read32(&regs->vendorspec) &
-		    ESDHC_VENDORSPEC_VSELECT))
-			return 0;
-
-		return -EAGAIN;
-	case MMC_SIGNAL_VOLTAGE_180:
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
-		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
-			ret = regulator_set_value(priv->vqmmc_dev, 1800000);
-			if (ret) {
-				printf("Setting to 1.8V error");
-				return -EIO;
-			}
-		}
-#endif
-		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
-		if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
-			return 0;
-
-		return -EAGAIN;
-	case MMC_SIGNAL_VOLTAGE_120:
-		return -ENOTSUPP;
-	default:
-		return 0;
-	}
-}
-
-static void esdhc_stop_tuning(struct mmc *mmc)
-{
-	struct mmc_cmd cmd;
-
-	cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
-	cmd.cmdarg = 0;
-	cmd.resp_type = MMC_RSP_R1b;
-
-	dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
-}
-
-static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
-{
-	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
-	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
-	struct fsl_esdhc *regs = priv->esdhc_regs;
-	struct mmc *mmc = &plat->mmc;
-	u32 irqstaten = readl(&regs->irqstaten);
-	u32 irqsigen = readl(&regs->irqsigen);
-	int i, ret = -ETIMEDOUT;
-	u32 val, mixctrl;
-
-	/* clock tuning is not needed for upto 52MHz */
-	if (mmc->clock <= 52000000)
-		return 0;
-
-	/* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
-	if (priv->flags & ESDHC_FLAG_STD_TUNING) {
-		val = readl(&regs->autoc12err);
-		mixctrl = readl(&regs->mixctrl);
-		val &= ~MIX_CTRL_SMPCLK_SEL;
-		mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
-
-		val |= MIX_CTRL_EXE_TUNE;
-		mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
-
-		writel(val, &regs->autoc12err);
-		writel(mixctrl, &regs->mixctrl);
-	}
-
-	/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
-	mixctrl = readl(&regs->mixctrl);
-	mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
-	writel(mixctrl, &regs->mixctrl);
-
-	writel(IRQSTATEN_BRR, &regs->irqstaten);
-	writel(IRQSTATEN_BRR, &regs->irqsigen);
-
-	/*
-	 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
-	 * of loops reaches 40 times.
-	 */
-	for (i = 0; i < MAX_TUNING_LOOP; i++) {
-		u32 ctrl;
-
-		if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
-			if (mmc->bus_width == 8)
-				writel(0x7080, &regs->blkattr);
-			else if (mmc->bus_width == 4)
-				writel(0x7040, &regs->blkattr);
-		} else {
-			writel(0x7040, &regs->blkattr);
-		}
-
-		/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
-		val = readl(&regs->mixctrl);
-		val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
-		writel(val, &regs->mixctrl);
-
-		/* We are using STD tuning, no need to check return value */
-		mmc_send_tuning(mmc, opcode, NULL);
-
-		ctrl = readl(&regs->autoc12err);
-		if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
-		    (ctrl & MIX_CTRL_SMPCLK_SEL)) {
-			/*
-			 * need to wait some time, make sure sd/mmc fininsh
-			 * send out tuning data, otherwise, the sd/mmc can't
-			 * response to any command when the card still out
-			 * put the tuning data.
-			 */
-			mdelay(1);
-			ret = 0;
-			break;
-		}
-
-		/* Add 1ms delay for SD and eMMC */
-		mdelay(1);
-	}
-
-	writel(irqstaten, &regs->irqstaten);
-	writel(irqsigen, &regs->irqsigen);
-
-	esdhc_stop_tuning(mmc);
-
-	return ret;
 }
 #endif
 
 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
 {
 	struct fsl_esdhc *regs = priv->esdhc_regs;
-	int ret __maybe_unused;
 
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 	/* Select to use peripheral clock */
 	esdhc_clock_control(priv, false);
-	esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
+	esdhc_setbits32(&regs->esdhcctl, ESDHCCTL_PCS);
 	esdhc_clock_control(priv, true);
 #endif
 	/* Set the clock speed */
 	if (priv->clock != mmc->clock)
 		set_sysctl(priv, mmc, mmc->clock);
 
-#ifdef MMC_SUPPORTS_TUNING
-	if (mmc->clk_disable) {
-#ifdef CONFIG_FSL_USDHC
-		esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
-#else
-		esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
-#endif
-	} else {
-#ifdef CONFIG_FSL_USDHC
-		esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
-				VENDORSPEC_CKEN);
-#else
-		esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
-#endif
-	}
-
-	if (priv->mode != mmc->selected_mode) {
-		ret = esdhc_set_timing(mmc);
-		if (ret) {
-			printf("esdhc_set_timing error %d\n", ret);
-			return ret;
-		}
-	}
-
-	if (priv->signal_voltage != mmc->signal_voltage) {
-		ret = esdhc_set_voltage(mmc);
-		if (ret) {
-			printf("esdhc_set_voltage error %d\n", ret);
-			return ret;
-		}
-	}
-#endif
-
 	/* Set the bus width */
 	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
 
@@ -1030,34 +614,10 @@
 			return -ETIMEDOUT;
 	}
 
-#if defined(CONFIG_FSL_USDHC)
-	/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
-	esdhc_write32(&regs->mmcboot, 0x0);
-	/* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
-	esdhc_write32(&regs->mixctrl, 0x0);
-	esdhc_write32(&regs->clktunectrlstatus, 0x0);
-
-	/* Put VEND_SPEC to default value */
-	if (priv->vs18_enable)
-		esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
-			      ESDHC_VENDORSPEC_VSELECT));
-	else
-		esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
-
-	/* Disable DLL_CTRL delay line */
-	esdhc_write32(&regs->dllctrl, 0x0);
-#endif
-
-#ifndef ARCH_MXC
 	/* Enable cache snooping */
-	esdhc_write32(&regs->scr, 0x00000040);
-#endif
+	esdhc_write32(&regs->esdhcctl, 0x00000040);
 
-#ifndef CONFIG_FSL_USDHC
 	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
-#else
-	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
-#endif
 
 	/* Set the initial clock speed */
 	mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
@@ -1065,12 +625,8 @@
 	/* Disable the BRR and BWR bits in IRQSTAT */
 	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
 
-#ifdef CONFIG_MCF5441x
-	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
-#else
 	/* Put the PROCTL reg back to the default */
 	esdhc_write32(&regs->proctl, PROCTL_INIT);
-#endif
 
 	/* Set timout to the maximum value */
 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
@@ -1091,10 +647,6 @@
 #if CONFIG_IS_ENABLED(DM_MMC)
 	if (priv->non_removable)
 		return 1;
-#ifdef CONFIG_DM_GPIO
-	if (dm_gpio_is_valid(&priv->cd_gpio))
-		return dm_gpio_get_value(&priv->cd_gpio);
-#endif
 #endif
 
 	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
@@ -1178,25 +730,8 @@
 	if (ret)
 		return ret;
 
-#ifdef CONFIG_MCF5441x
-	/* ColdFire, using SDHC_DATA[3] for card detection */
-	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
-#endif
-
-#ifndef CONFIG_FSL_USDHC
-	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
-				| SYSCTL_IPGEN | SYSCTL_CKEN);
-	/* Clearing tuning bits in case ROM has set it already */
-	esdhc_write32(&regs->mixctrl, 0);
-	esdhc_write32(&regs->autoc12err, 0);
-	esdhc_write32(&regs->clktunectrlstatus, 0);
-#else
-	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
-			VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
-#endif
-
-	if (priv->vs18_enable)
-		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN |
+				       SYSCTL_IPGEN | SYSCTL_CKEN);
 
 	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 	cfg = &plat->cfg;
@@ -1207,15 +742,6 @@
 	voltage_caps = 0;
 	caps = esdhc_read32(&regs->hostcapblt);
 
-#ifdef CONFIG_MCF5441x
-	/*
-	 * MCF5441x RM declares in more points that sdhc clock speed must
-	 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
-	 * from host capabilities.
-	 */
-	caps &= ~ESDHC_HOSTCAPBLT_HSS;
-#endif
-
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
 	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
 			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
@@ -1272,27 +798,11 @@
 		cfg->host_caps &= ~MMC_MODE_8BIT;
 #endif
 
-	cfg->host_caps |= priv->caps;
-
 	cfg->f_min = 400000;
 	cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
 
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
-	writel(0, &regs->dllctrl);
-	if (priv->flags & ESDHC_FLAG_USDHC) {
-		if (priv->flags & ESDHC_FLAG_STD_TUNING) {
-			u32 val = readl(&regs->tuning_ctrl);
-
-			val |= ESDHC_STD_TUNING_EN;
-			val &= ~ESDHC_TUNING_START_TAP_MASK;
-			val |= priv->tuning_start_tap;
-			val &= ~ESDHC_TUNING_STEP_MASK;
-			val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
-			writel(val, &regs->tuning_ctrl);
-		}
-	}
-
 	return 0;
 }
 
@@ -1307,7 +817,6 @@
 	priv->bus_width = cfg->max_bus_width;
 	priv->sdhc_clk = cfg->sdhc_clk;
 	priv->wp_enable  = cfg->wp_enable;
-	priv->vs18_enable  = cfg->vs18_enable;
 
 	return 0;
 };
@@ -1444,22 +953,11 @@
 #ifndef CONFIG_PPC
 #include <asm/arch/clock.h>
 #endif
-__weak void init_clk_usdhc(u32 index)
-{
-}
-
 static int fsl_esdhc_probe(struct udevice *dev)
 {
 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
 	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
-	const void *fdt = gd->fdt_blob;
-	int node = dev_of_offset(dev);
-	struct esdhc_soc_data *data =
-		(struct esdhc_soc_data *)dev_get_driver_data(dev);
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
-	struct udevice *vqmmc_dev;
-#endif
 	fdt_addr_t addr;
 	unsigned int val;
 	struct mmc *mmc;
@@ -1477,11 +975,6 @@
 	priv->esdhc_regs = (struct fsl_esdhc *)addr;
 #endif
 	priv->dev = dev;
-	priv->mode = -1;
-	if (data) {
-		priv->flags = data->flags;
-		priv->caps = data->caps;
-	}
 
 	val = dev_read_u32_default(dev, "bus-width", -1);
 	if (val == 8)
@@ -1491,81 +984,13 @@
 	else
 		priv->bus_width = 1;
 
-	val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
-	priv->tuning_step = val;
-	val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
-			     ESDHC_TUNING_START_TAP_DEFAULT);
-	priv->tuning_start_tap = val;
-	val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
-			     ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
-	priv->strobe_dll_delay_target = val;
-
 	if (dev_read_bool(dev, "non-removable")) {
 		priv->non_removable = 1;
 	 } else {
 		priv->non_removable = 0;
-#ifdef CONFIG_DM_GPIO
-		gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
-				     GPIOD_IS_IN);
-#endif
-	}
-
-	if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
-		priv->wp_enable = 1;
-	} else {
-		priv->wp_enable = 0;
-#ifdef CONFIG_DM_GPIO
-		gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
-				   GPIOD_IS_IN);
-#endif
-	}
-
-	priv->vs18_enable = 0;
-
-#if CONFIG_IS_ENABLED(DM_REGULATOR)
-	/*
-	 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
-	 * otherwise, emmc will work abnormally.
-	 */
-	ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
-	if (ret) {
-		dev_dbg(dev, "no vqmmc-supply\n");
-	} else {
-		ret = regulator_set_enable(vqmmc_dev, true);
-		if (ret) {
-			dev_err(dev, "fail to enable vqmmc-supply\n");
-			return ret;
-		}
-
-		if (regulator_get_value(vqmmc_dev) == 1800000)
-			priv->vs18_enable = 1;
 	}
-#endif
 
-	if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
-		priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
-
-	/*
-	 * TODO:
-	 * Because lack of clk driver, if SDHC clk is not enabled,
-	 * need to enable it first before this driver is invoked.
-	 *
-	 * we use MXC_ESDHC_CLK to get clk freq.
-	 * If one would like to make this function work,
-	 * the aliases should be provided in dts as this:
-	 *
-	 *  aliases {
-	 *	mmc0 = &usdhc1;
-	 *	mmc1 = &usdhc2;
-	 *	mmc2 = &usdhc3;
-	 *	mmc3 = &usdhc4;
-	 *	};
-	 * Then if your board only supports mmc2 and mmc3, but we can
-	 * correctly get the seq as 2 and 3, then let mxc_get_clock
-	 * work as expected.
-	 */
-
-	init_clk_usdhc(dev->seq);
+	priv->wp_enable = 1;
 
 	if (IS_ENABLED(CONFIG_CLK)) {
 		/* Assigned clock already set clock */
@@ -1656,28 +1081,10 @@
 	.get_cd		= fsl_esdhc_get_cd,
 	.send_cmd	= fsl_esdhc_send_cmd,
 	.set_ios	= fsl_esdhc_set_ios,
-#ifdef MMC_SUPPORTS_TUNING
-	.execute_tuning	= fsl_esdhc_execute_tuning,
-#endif
 };
 #endif
 
-static struct esdhc_soc_data usdhc_imx7d_data = {
-	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
-			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
-			| ESDHC_FLAG_HS400,
-	.caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
-		MMC_MODE_HS_52MHz | MMC_MODE_HS,
-};
-
 static const struct udevice_id fsl_esdhc_ids[] = {
-	{ .compatible = "fsl,imx53-esdhc", },
-	{ .compatible = "fsl,imx6ul-usdhc", },
-	{ .compatible = "fsl,imx6sx-usdhc", },
-	{ .compatible = "fsl,imx6sl-usdhc", },
-	{ .compatible = "fsl,imx6q-usdhc", },
-	{ .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
-	{ .compatible = "fsl,imx7ulp-usdhc", },
 	{ .compatible = "fsl,esdhc", },
 	{ /* sentinel */ }
 };
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
new file mode 100644
index 0000000..c0d47ba
--- /dev/null
+++ b/drivers/mmc/fsl_esdhc_imx.c
@@ -0,0 +1,1650 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
+ * Copyright 2019 NXP Semiconductors
+ * Andy Fleming
+ * Yangbo Lu <yangbo.lu@nxp.com>
+ *
+ * Based vaguely on the pxa mmc code:
+ * (C) Copyright 2003
+ * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <clk.h>
+#include <errno.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <part.h>
+#include <power/regulator.h>
+#include <malloc.h>
+#include <fsl_esdhc_imx.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <asm-generic/gpio.h>
+#include <dm/pinctrl.h>
+
+#if !CONFIG_IS_ENABLED(BLK)
+#include "mmc_private.h"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SDHCI_IRQ_EN_BITS		(IRQSTATEN_CC | IRQSTATEN_TC | \
+				IRQSTATEN_CINT | \
+				IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
+				IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
+				IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
+				IRQSTATEN_DINT)
+#define MAX_TUNING_LOOP 40
+#define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
+
+struct fsl_esdhc {
+	uint    dsaddr;		/* SDMA system address register */
+	uint    blkattr;	/* Block attributes register */
+	uint    cmdarg;		/* Command argument register */
+	uint    xfertyp;	/* Transfer type register */
+	uint    cmdrsp0;	/* Command response 0 register */
+	uint    cmdrsp1;	/* Command response 1 register */
+	uint    cmdrsp2;	/* Command response 2 register */
+	uint    cmdrsp3;	/* Command response 3 register */
+	uint    datport;	/* Buffer data port register */
+	uint    prsstat;	/* Present state register */
+	uint    proctl;		/* Protocol control register */
+	uint    sysctl;		/* System Control Register */
+	uint    irqstat;	/* Interrupt status register */
+	uint    irqstaten;	/* Interrupt status enable register */
+	uint    irqsigen;	/* Interrupt signal enable register */
+	uint    autoc12err;	/* Auto CMD error status register */
+	uint    hostcapblt;	/* Host controller capabilities register */
+	uint    wml;		/* Watermark level register */
+	uint    mixctrl;	/* For USDHC */
+	char    reserved1[4];	/* reserved */
+	uint    fevt;		/* Force event register */
+	uint    admaes;		/* ADMA error status register */
+	uint    adsaddr;	/* ADMA system address register */
+	char    reserved2[4];
+	uint    dllctrl;
+	uint    dllstat;
+	uint    clktunectrlstatus;
+	char    reserved3[4];
+	uint	strobe_dllctrl;
+	uint	strobe_dllstat;
+	char    reserved4[72];
+	uint    vendorspec;
+	uint    mmcboot;
+	uint    vendorspec2;
+	uint    tuning_ctrl;	/* on i.MX6/7/8 */
+	char	reserved5[44];
+	uint    hostver;	/* Host controller version register */
+	char    reserved6[4];	/* reserved */
+	uint    dmaerraddr;	/* DMA error address register */
+	char    reserved7[4];	/* reserved */
+	uint    dmaerrattr;	/* DMA error attribute register */
+	char    reserved8[4];	/* reserved */
+	uint    hostcapblt2;	/* Host controller capabilities register 2 */
+	char    reserved9[8];	/* reserved */
+	uint    tcr;		/* Tuning control register */
+	char    reserved10[28];	/* reserved */
+	uint    sddirctl;	/* SD direction control register */
+	char    reserved11[712];/* reserved */
+	uint    scr;		/* eSDHC control register */
+};
+
+struct fsl_esdhc_plat {
+	struct mmc_config cfg;
+	struct mmc mmc;
+};
+
+struct esdhc_soc_data {
+	u32 flags;
+	u32 caps;
+};
+
+/**
+ * struct fsl_esdhc_priv
+ *
+ * @esdhc_regs: registers of the sdhc controller
+ * @sdhc_clk: Current clk of the sdhc controller
+ * @bus_width: bus width, 1bit, 4bit or 8bit
+ * @cfg: mmc config
+ * @mmc: mmc
+ * Following is used when Driver Model is enabled for MMC
+ * @dev: pointer for the device
+ * @non_removable: 0: removable; 1: non-removable
+ * @wp_enable: 1: enable checking wp; 0: no check
+ * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
+ * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
+ * @caps: controller capabilities
+ * @tuning_step: tuning step setting in tuning_ctrl register
+ * @start_tuning_tap: the start point for tuning in tuning_ctrl register
+ * @strobe_dll_delay_target: settings in strobe_dllctrl
+ * @signal_voltage: indicating the current voltage
+ * @cd_gpio: gpio for card detection
+ * @wp_gpio: gpio for write protection
+ */
+struct fsl_esdhc_priv {
+	struct fsl_esdhc *esdhc_regs;
+	unsigned int sdhc_clk;
+	struct clk per_clk;
+	unsigned int clock;
+	unsigned int mode;
+	unsigned int bus_width;
+#if !CONFIG_IS_ENABLED(BLK)
+	struct mmc *mmc;
+#endif
+	struct udevice *dev;
+	int non_removable;
+	int wp_enable;
+	int vs18_enable;
+	u32 flags;
+	u32 caps;
+	u32 tuning_step;
+	u32 tuning_start_tap;
+	u32 strobe_dll_delay_target;
+	u32 signal_voltage;
+#if IS_ENABLED(CONFIG_DM_REGULATOR)
+	struct udevice *vqmmc_dev;
+	struct udevice *vmmc_dev;
+#endif
+#ifdef CONFIG_DM_GPIO
+	struct gpio_desc cd_gpio;
+	struct gpio_desc wp_gpio;
+#endif
+};
+
+/* Return the XFERTYP flags for a given command and data packet */
+static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
+{
+	uint xfertyp = 0;
+
+	if (data) {
+		xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+		xfertyp |= XFERTYP_DMAEN;
+#endif
+		if (data->blocks > 1) {
+			xfertyp |= XFERTYP_MSBSEL;
+			xfertyp |= XFERTYP_BCEN;
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+			xfertyp |= XFERTYP_AC12EN;
+#endif
+		}
+
+		if (data->flags & MMC_DATA_READ)
+			xfertyp |= XFERTYP_DTDSEL;
+	}
+
+	if (cmd->resp_type & MMC_RSP_CRC)
+		xfertyp |= XFERTYP_CCCEN;
+	if (cmd->resp_type & MMC_RSP_OPCODE)
+		xfertyp |= XFERTYP_CICEN;
+	if (cmd->resp_type & MMC_RSP_136)
+		xfertyp |= XFERTYP_RSPTYP_136;
+	else if (cmd->resp_type & MMC_RSP_BUSY)
+		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
+	else if (cmd->resp_type & MMC_RSP_PRESENT)
+		xfertyp |= XFERTYP_RSPTYP_48;
+
+	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+		xfertyp |= XFERTYP_CMDTYP_ABORT;
+
+	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
+}
+
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
+				 struct mmc_data *data)
+{
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	uint blocks;
+	char *buffer;
+	uint databuf;
+	uint size;
+	uint irqstat;
+	ulong start;
+
+	if (data->flags & MMC_DATA_READ) {
+		blocks = data->blocks;
+		buffer = data->dest;
+		while (blocks) {
+			start = get_timer(0);
+			size = data->blocksize;
+			irqstat = esdhc_read32(&regs->irqstat);
+			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
+				if (get_timer(start) > PIO_TIMEOUT) {
+					printf("\nData Read Failed in PIO Mode.");
+					return;
+				}
+			}
+			while (size && (!(irqstat & IRQSTAT_TC))) {
+				udelay(100); /* Wait before last byte transfer complete */
+				irqstat = esdhc_read32(&regs->irqstat);
+				databuf = in_le32(&regs->datport);
+				*((uint *)buffer) = databuf;
+				buffer += 4;
+				size -= 4;
+			}
+			blocks--;
+		}
+	} else {
+		blocks = data->blocks;
+		buffer = (char *)data->src;
+		while (blocks) {
+			start = get_timer(0);
+			size = data->blocksize;
+			irqstat = esdhc_read32(&regs->irqstat);
+			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
+				if (get_timer(start) > PIO_TIMEOUT) {
+					printf("\nData Write Failed in PIO Mode.");
+					return;
+				}
+			}
+			while (size && (!(irqstat & IRQSTAT_TC))) {
+				udelay(100); /* Wait before last byte transfer complete */
+				databuf = *((uint *)buffer);
+				buffer += 4;
+				size -= 4;
+				irqstat = esdhc_read32(&regs->irqstat);
+				out_le32(&regs->datport, databuf);
+			}
+			blocks--;
+		}
+	}
+}
+#endif
+
+static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+			    struct mmc_data *data)
+{
+	int timeout;
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+	dma_addr_t addr;
+#endif
+	uint wml_value;
+
+	wml_value = data->blocksize/4;
+
+	if (data->flags & MMC_DATA_READ) {
+		if (wml_value > WML_RD_WML_MAX)
+			wml_value = WML_RD_WML_MAX_VAL;
+
+		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+		addr = virt_to_phys((void *)(data->dest));
+		if (upper_32_bits(addr))
+			printf("Error found for upper 32 bits\n");
+		else
+			esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+#else
+		esdhc_write32(&regs->dsaddr, (u32)data->dest);
+#endif
+#endif
+	} else {
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+		flush_dcache_range((ulong)data->src,
+				   (ulong)data->src+data->blocks
+					 *data->blocksize);
+#endif
+		if (wml_value > WML_WR_WML_MAX)
+			wml_value = WML_WR_WML_MAX_VAL;
+		if (priv->wp_enable) {
+			if ((esdhc_read32(&regs->prsstat) &
+			    PRSSTAT_WPSPL) == 0) {
+				printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+				return -ETIMEDOUT;
+			}
+		} else {
+#ifdef CONFIG_DM_GPIO
+			if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
+				printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
+				return -ETIMEDOUT;
+			}
+#endif
+		}
+
+		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
+					wml_value << 16);
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+		addr = virt_to_phys((void *)(data->src));
+		if (upper_32_bits(addr))
+			printf("Error found for upper 32 bits\n");
+		else
+			esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+#else
+		esdhc_write32(&regs->dsaddr, (u32)data->src);
+#endif
+#endif
+	}
+
+	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
+
+	/* Calculate the timeout period for data transactions */
+	/*
+	 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
+	 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
+	 *  So, Number of SD Clock cycles for 0.25sec should be minimum
+	 *		(SD Clock/sec * 0.25 sec) SD Clock cycles
+	 *		= (mmc->clock * 1/4) SD Clock cycles
+	 * As 1) >=  2)
+	 * => (2^(timeout+13)) >= mmc->clock * 1/4
+	 * Taking log2 both the sides
+	 * => timeout + 13 >= log2(mmc->clock/4)
+	 * Rounding up to next power of 2
+	 * => timeout + 13 = log2(mmc->clock/4) + 1
+	 * => timeout + 13 = fls(mmc->clock/4)
+	 *
+	 * However, the MMC spec "It is strongly recommended for hosts to
+	 * implement more than 500ms timeout value even if the card
+	 * indicates the 250ms maximum busy length."  Even the previous
+	 * value of 300ms is known to be insufficient for some cards.
+	 * So, we use
+	 * => timeout + 13 = fls(mmc->clock/2)
+	 */
+	timeout = fls(mmc->clock/2);
+	timeout -= 13;
+
+	if (timeout > 14)
+		timeout = 14;
+
+	if (timeout < 0)
+		timeout = 0;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+	if ((timeout == 4) || (timeout == 8) || (timeout == 12))
+		timeout++;
+#endif
+
+#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+	timeout = 0xE;
+#endif
+	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
+
+	return 0;
+}
+
+static void check_and_invalidate_dcache_range
+	(struct mmc_cmd *cmd,
+	 struct mmc_data *data) {
+	unsigned start = 0;
+	unsigned end = 0;
+	unsigned size = roundup(ARCH_DMA_MINALIGN,
+				data->blocks*data->blocksize);
+#if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
+	dma_addr_t addr;
+
+	addr = virt_to_phys((void *)(data->dest));
+	if (upper_32_bits(addr))
+		printf("Error found for upper 32 bits\n");
+	else
+		start = lower_32_bits(addr);
+#else
+	start = (unsigned)data->dest;
+#endif
+	end = start + size;
+	invalidate_dcache_range(start, end);
+}
+
+#ifdef CONFIG_MCF5441x
+/*
+ * Swaps 32-bit words to little-endian byte order.
+ */
+static inline void sd_swap_dma_buff(struct mmc_data *data)
+{
+	int i, size = data->blocksize >> 2;
+	u32 *buffer = (u32 *)data->dest;
+	u32 sw;
+
+	while (data->blocks--) {
+		for (i = 0; i < size; i++) {
+			sw = __sw32(*buffer);
+			*buffer++ = sw;
+		}
+	}
+}
+#endif
+
+/*
+ * Sends a command out on the bus.  Takes the mmc pointer,
+ * a command pointer, and an optional data pointer.
+ */
+static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
+				 struct mmc_cmd *cmd, struct mmc_data *data)
+{
+	int	err = 0;
+	uint	xfertyp;
+	uint	irqstat;
+	u32	flags = IRQSTAT_CC | IRQSTAT_CTOE;
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	unsigned long start;
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
+	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
+		return 0;
+#endif
+
+	esdhc_write32(&regs->irqstat, -1);
+
+	sync();
+
+	/* Wait for the bus to be idle */
+	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
+			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
+		;
+
+	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
+		;
+
+	/* Wait at least 8 SD clock cycles before the next command */
+	/*
+	 * Note: This is way more than 8 cycles, but 1ms seems to
+	 * resolve timing issues with some cards
+	 */
+	udelay(1000);
+
+	/* Set up for a data transfer if we have one */
+	if (data) {
+		err = esdhc_setup_data(priv, mmc, data);
+		if(err)
+			return err;
+
+		if (data->flags & MMC_DATA_READ)
+			check_and_invalidate_dcache_range(cmd, data);
+	}
+
+	/* Figure out the transfer arguments */
+	xfertyp = esdhc_xfertyp(cmd, data);
+
+	/* Mask all irqs */
+	esdhc_write32(&regs->irqsigen, 0);
+
+	/* Send the command */
+	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
+#if defined(CONFIG_FSL_USDHC)
+	esdhc_write32(&regs->mixctrl,
+	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
+			| (mmc->ddr_mode ? XFERTYP_DDREN : 0));
+	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
+#else
+	esdhc_write32(&regs->xfertyp, xfertyp);
+#endif
+
+	if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
+	    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
+		flags = IRQSTAT_BRR;
+
+	/* Wait for the command to complete */
+	start = get_timer(0);
+	while (!(esdhc_read32(&regs->irqstat) & flags)) {
+		if (get_timer(start) > 1000) {
+			err = -ETIMEDOUT;
+			goto out;
+		}
+	}
+
+	irqstat = esdhc_read32(&regs->irqstat);
+
+	if (irqstat & CMD_ERR) {
+		err = -ECOMM;
+		goto out;
+	}
+
+	if (irqstat & IRQSTAT_CTOE) {
+		err = -ETIMEDOUT;
+		goto out;
+	}
+
+	/* Switch voltage to 1.8V if CMD11 succeeded */
+	if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
+		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
+		printf("Run CMD11 1.8V switch\n");
+		/* Sleep for 5 ms - max time for card to switch to 1.8V */
+		udelay(5000);
+	}
+
+	/* Workaround for ESDHC errata ENGcm03648 */
+	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
+		int timeout = 6000;
+
+		/* Poll on DATA0 line for cmd with busy signal for 600 ms */
+		while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
+					PRSSTAT_DAT0)) {
+			udelay(100);
+			timeout--;
+		}
+
+		if (timeout <= 0) {
+			printf("Timeout waiting for DAT0 to go high!\n");
+			err = -ETIMEDOUT;
+			goto out;
+		}
+	}
+
+	/* Copy the response to the response buffer */
+	if (cmd->resp_type & MMC_RSP_136) {
+		u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
+
+		cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
+		cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
+		cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
+		cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
+		cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
+		cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
+		cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
+		cmd->response[3] = (cmdrsp0 << 8);
+	} else
+		cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
+
+	/* Wait until all of the blocks are transferred */
+	if (data) {
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+		esdhc_pio_read_write(priv, data);
+#else
+		flags = DATA_COMPLETE;
+		if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
+		    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
+			flags = IRQSTAT_BRR;
+		}
+
+		do {
+			irqstat = esdhc_read32(&regs->irqstat);
+
+			if (irqstat & IRQSTAT_DTOE) {
+				err = -ETIMEDOUT;
+				goto out;
+			}
+
+			if (irqstat & DATA_ERR) {
+				err = -ECOMM;
+				goto out;
+			}
+		} while ((irqstat & flags) != flags);
+
+		/*
+		 * Need invalidate the dcache here again to avoid any
+		 * cache-fill during the DMA operations such as the
+		 * speculative pre-fetching etc.
+		 */
+		if (data->flags & MMC_DATA_READ) {
+			check_and_invalidate_dcache_range(cmd, data);
+#ifdef CONFIG_MCF5441x
+			sd_swap_dma_buff(data);
+#endif
+		}
+#endif
+	}
+
+out:
+	/* Reset CMD and DATA portions on error */
+	if (err) {
+		esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
+			      SYSCTL_RSTC);
+		while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
+			;
+
+		if (data) {
+			esdhc_write32(&regs->sysctl,
+				      esdhc_read32(&regs->sysctl) |
+				      SYSCTL_RSTD);
+			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
+				;
+		}
+
+		/* If this was CMD11, then notify that power cycle is needed */
+		if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
+			printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
+	}
+
+	esdhc_write32(&regs->irqstat, -1);
+
+	return err;
+}
+
+static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
+{
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	int div = 1;
+#ifdef ARCH_MXC
+#ifdef CONFIG_MX53
+	/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
+	int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
+#else
+	int pre_div = 1;
+#endif
+#else
+	int pre_div = 2;
+#endif
+	int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
+	int sdhc_clk = priv->sdhc_clk;
+	uint clk;
+
+	if (clock < mmc->cfg->f_min)
+		clock = mmc->cfg->f_min;
+
+	while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
+		pre_div *= 2;
+
+	while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
+		div++;
+
+	pre_div >>= 1;
+	div -= 1;
+
+	clk = (pre_div << 8) | (div << 4);
+
+#ifdef CONFIG_FSL_USDHC
+	esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
+#else
+	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
+#endif
+
+	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
+
+	udelay(10000);
+
+#ifdef CONFIG_FSL_USDHC
+	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
+#else
+	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
+
+	priv->clock = clock;
+}
+
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
+{
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	u32 value;
+	u32 time_out;
+
+	value = esdhc_read32(&regs->sysctl);
+
+	if (enable)
+		value |= SYSCTL_CKEN;
+	else
+		value &= ~SYSCTL_CKEN;
+
+	esdhc_write32(&regs->sysctl, value);
+
+	time_out = 20;
+	value = PRSSTAT_SDSTB;
+	while (!(esdhc_read32(&regs->prsstat) & value)) {
+		if (time_out == 0) {
+			printf("fsl_esdhc: Internal clock never stabilised.\n");
+			break;
+		}
+		time_out--;
+		mdelay(1);
+	}
+}
+#endif
+
+#ifdef MMC_SUPPORTS_TUNING
+static int esdhc_change_pinstate(struct udevice *dev)
+{
+	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	switch (priv->mode) {
+	case UHS_SDR50:
+	case UHS_DDR50:
+		ret = pinctrl_select_state(dev, "state_100mhz");
+		break;
+	case UHS_SDR104:
+	case MMC_HS_200:
+	case MMC_HS_400:
+		ret = pinctrl_select_state(dev, "state_200mhz");
+		break;
+	default:
+		ret = pinctrl_select_state(dev, "default");
+		break;
+	}
+
+	if (ret)
+		printf("%s %d error\n", __func__, priv->mode);
+
+	return ret;
+}
+
+static void esdhc_reset_tuning(struct mmc *mmc)
+{
+	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+
+	if (priv->flags & ESDHC_FLAG_USDHC) {
+		if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+			esdhc_clrbits32(&regs->autoc12err,
+					MIX_CTRL_SMPCLK_SEL |
+					MIX_CTRL_EXE_TUNE);
+		}
+	}
+}
+
+static void esdhc_set_strobe_dll(struct mmc *mmc)
+{
+	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	u32 val;
+
+	if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
+		writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);
+
+		/*
+		 * enable strobe dll ctrl and adjust the delay target
+		 * for the uSDHC loopback read clock
+		 */
+		val = ESDHC_STROBE_DLL_CTRL_ENABLE |
+			(priv->strobe_dll_delay_target <<
+			 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
+		writel(val, &regs->strobe_dllctrl);
+		/* wait 1us to make sure strobe dll status register stable */
+		mdelay(1);
+		val = readl(&regs->strobe_dllstat);
+		if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
+			pr_warn("HS400 strobe DLL status REF not lock!\n");
+		if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
+			pr_warn("HS400 strobe DLL status SLV not lock!\n");
+	}
+}
+
+static int esdhc_set_timing(struct mmc *mmc)
+{
+	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	u32 mixctrl;
+
+	mixctrl = readl(&regs->mixctrl);
+	mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
+
+	switch (mmc->selected_mode) {
+	case MMC_LEGACY:
+	case SD_LEGACY:
+		esdhc_reset_tuning(mmc);
+		writel(mixctrl, &regs->mixctrl);
+		break;
+	case MMC_HS_400:
+		mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
+		writel(mixctrl, &regs->mixctrl);
+		esdhc_set_strobe_dll(mmc);
+		break;
+	case MMC_HS:
+	case MMC_HS_52:
+	case MMC_HS_200:
+	case SD_HS:
+	case UHS_SDR12:
+	case UHS_SDR25:
+	case UHS_SDR50:
+	case UHS_SDR104:
+		writel(mixctrl, &regs->mixctrl);
+		break;
+	case UHS_DDR50:
+	case MMC_DDR_52:
+		mixctrl |= MIX_CTRL_DDREN;
+		writel(mixctrl, &regs->mixctrl);
+		break;
+	default:
+		printf("Not supported %d\n", mmc->selected_mode);
+		return -EINVAL;
+	}
+
+	priv->mode = mmc->selected_mode;
+
+	return esdhc_change_pinstate(mmc->dev);
+}
+
+static int esdhc_set_voltage(struct mmc *mmc)
+{
+	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	int ret;
+
+	priv->signal_voltage = mmc->signal_voltage;
+	switch (mmc->signal_voltage) {
+	case MMC_SIGNAL_VOLTAGE_330:
+		if (priv->vs18_enable)
+			return -EIO;
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+			ret = regulator_set_value(priv->vqmmc_dev, 3300000);
+			if (ret) {
+				printf("Setting to 3.3V error");
+				return -EIO;
+			}
+			/* Wait for 5ms */
+			mdelay(5);
+		}
+#endif
+
+		esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+		if (!(esdhc_read32(&regs->vendorspec) &
+		    ESDHC_VENDORSPEC_VSELECT))
+			return 0;
+
+		return -EAGAIN;
+	case MMC_SIGNAL_VOLTAGE_180:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
+			ret = regulator_set_value(priv->vqmmc_dev, 1800000);
+			if (ret) {
+				printf("Setting to 1.8V error");
+				return -EIO;
+			}
+		}
+#endif
+		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+		if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
+			return 0;
+
+		return -EAGAIN;
+	case MMC_SIGNAL_VOLTAGE_120:
+		return -ENOTSUPP;
+	default:
+		return 0;
+	}
+}
+
+static void esdhc_stop_tuning(struct mmc *mmc)
+{
+	struct mmc_cmd cmd;
+
+	cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
+	cmd.cmdarg = 0;
+	cmd.resp_type = MMC_RSP_R1b;
+
+	dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
+}
+
+static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
+{
+	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	struct mmc *mmc = &plat->mmc;
+	u32 irqstaten = readl(&regs->irqstaten);
+	u32 irqsigen = readl(&regs->irqsigen);
+	int i, ret = -ETIMEDOUT;
+	u32 val, mixctrl;
+
+	/* clock tuning is not needed for upto 52MHz */
+	if (mmc->clock <= 52000000)
+		return 0;
+
+	/* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
+	if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+		val = readl(&regs->autoc12err);
+		mixctrl = readl(&regs->mixctrl);
+		val &= ~MIX_CTRL_SMPCLK_SEL;
+		mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
+
+		val |= MIX_CTRL_EXE_TUNE;
+		mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
+
+		writel(val, &regs->autoc12err);
+		writel(mixctrl, &regs->mixctrl);
+	}
+
+	/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
+	mixctrl = readl(&regs->mixctrl);
+	mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
+	writel(mixctrl, &regs->mixctrl);
+
+	writel(IRQSTATEN_BRR, &regs->irqstaten);
+	writel(IRQSTATEN_BRR, &regs->irqsigen);
+
+	/*
+	 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
+	 * of loops reaches 40 times.
+	 */
+	for (i = 0; i < MAX_TUNING_LOOP; i++) {
+		u32 ctrl;
+
+		if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
+			if (mmc->bus_width == 8)
+				writel(0x7080, &regs->blkattr);
+			else if (mmc->bus_width == 4)
+				writel(0x7040, &regs->blkattr);
+		} else {
+			writel(0x7040, &regs->blkattr);
+		}
+
+		/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
+		val = readl(&regs->mixctrl);
+		val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
+		writel(val, &regs->mixctrl);
+
+		/* We are using STD tuning, no need to check return value */
+		mmc_send_tuning(mmc, opcode, NULL);
+
+		ctrl = readl(&regs->autoc12err);
+		if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
+		    (ctrl & MIX_CTRL_SMPCLK_SEL)) {
+			/*
+			 * need to wait some time, make sure sd/mmc fininsh
+			 * send out tuning data, otherwise, the sd/mmc can't
+			 * response to any command when the card still out
+			 * put the tuning data.
+			 */
+			mdelay(1);
+			ret = 0;
+			break;
+		}
+
+		/* Add 1ms delay for SD and eMMC */
+		mdelay(1);
+	}
+
+	writel(irqstaten, &regs->irqstaten);
+	writel(irqsigen, &regs->irqsigen);
+
+	esdhc_stop_tuning(mmc);
+
+	return ret;
+}
+#endif
+
+static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
+{
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	int ret __maybe_unused;
+
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+	/* Select to use peripheral clock */
+	esdhc_clock_control(priv, false);
+	esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
+	esdhc_clock_control(priv, true);
+#endif
+	/* Set the clock speed */
+	if (priv->clock != mmc->clock)
+		set_sysctl(priv, mmc, mmc->clock);
+
+#ifdef MMC_SUPPORTS_TUNING
+	if (mmc->clk_disable) {
+#ifdef CONFIG_FSL_USDHC
+		esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
+#else
+		esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
+#endif
+	} else {
+#ifdef CONFIG_FSL_USDHC
+		esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
+				VENDORSPEC_CKEN);
+#else
+		esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
+#endif
+	}
+
+	if (priv->mode != mmc->selected_mode) {
+		ret = esdhc_set_timing(mmc);
+		if (ret) {
+			printf("esdhc_set_timing error %d\n", ret);
+			return ret;
+		}
+	}
+
+	if (priv->signal_voltage != mmc->signal_voltage) {
+		ret = esdhc_set_voltage(mmc);
+		if (ret) {
+			printf("esdhc_set_voltage error %d\n", ret);
+			return ret;
+		}
+	}
+#endif
+
+	/* Set the bus width */
+	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
+
+	if (mmc->bus_width == 4)
+		esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
+	else if (mmc->bus_width == 8)
+		esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
+
+	return 0;
+}
+
+static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
+{
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	ulong start;
+
+	/* Reset the entire host controller */
+	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+
+	/* Wait until the controller is available */
+	start = get_timer(0);
+	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
+		if (get_timer(start) > 1000)
+			return -ETIMEDOUT;
+	}
+
+#if defined(CONFIG_FSL_USDHC)
+	/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
+	esdhc_write32(&regs->mmcboot, 0x0);
+	/* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
+	esdhc_write32(&regs->mixctrl, 0x0);
+	esdhc_write32(&regs->clktunectrlstatus, 0x0);
+
+	/* Put VEND_SPEC to default value */
+	if (priv->vs18_enable)
+		esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
+			      ESDHC_VENDORSPEC_VSELECT));
+	else
+		esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
+
+	/* Disable DLL_CTRL delay line */
+	esdhc_write32(&regs->dllctrl, 0x0);
+#endif
+
+#ifndef ARCH_MXC
+	/* Enable cache snooping */
+	esdhc_write32(&regs->scr, 0x00000040);
+#endif
+
+#ifndef CONFIG_FSL_USDHC
+	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#else
+	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
+#endif
+
+	/* Set the initial clock speed */
+	mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
+
+	/* Disable the BRR and BWR bits in IRQSTAT */
+	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
+
+#ifdef CONFIG_MCF5441x
+	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
+#else
+	/* Put the PROCTL reg back to the default */
+	esdhc_write32(&regs->proctl, PROCTL_INIT);
+#endif
+
+	/* Set timout to the maximum value */
+	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
+
+	return 0;
+}
+
+static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
+{
+	struct fsl_esdhc *regs = priv->esdhc_regs;
+	int timeout = 1000;
+
+#ifdef CONFIG_ESDHC_DETECT_QUIRK
+	if (CONFIG_ESDHC_DETECT_QUIRK)
+		return 1;
+#endif
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+	if (priv->non_removable)
+		return 1;
+#ifdef CONFIG_DM_GPIO
+	if (dm_gpio_is_valid(&priv->cd_gpio))
+		return dm_gpio_get_value(&priv->cd_gpio);
+#endif
+#endif
+
+	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
+		udelay(1000);
+
+	return timeout > 0;
+}
+
+static int esdhc_reset(struct fsl_esdhc *regs)
+{
+	ulong start;
+
+	/* reset the controller */
+	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
+
+	/* hardware clears the bit when it is done */
+	start = get_timer(0);
+	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
+		if (get_timer(start) > 100) {
+			printf("MMC/SD: Reset never completed.\n");
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int esdhc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_priv *priv = mmc->priv;
+
+	return esdhc_getcd_common(priv);
+}
+
+static int esdhc_init(struct mmc *mmc)
+{
+	struct fsl_esdhc_priv *priv = mmc->priv;
+
+	return esdhc_init_common(priv, mmc);
+}
+
+static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
+			  struct mmc_data *data)
+{
+	struct fsl_esdhc_priv *priv = mmc->priv;
+
+	return esdhc_send_cmd_common(priv, mmc, cmd, data);
+}
+
+static int esdhc_set_ios(struct mmc *mmc)
+{
+	struct fsl_esdhc_priv *priv = mmc->priv;
+
+	return esdhc_set_ios_common(priv, mmc);
+}
+
+static const struct mmc_ops esdhc_ops = {
+	.getcd		= esdhc_getcd,
+	.init		= esdhc_init,
+	.send_cmd	= esdhc_send_cmd,
+	.set_ios	= esdhc_set_ios,
+};
+#endif
+
+static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
+			  struct fsl_esdhc_plat *plat)
+{
+	struct mmc_config *cfg;
+	struct fsl_esdhc *regs;
+	u32 caps, voltage_caps;
+	int ret;
+
+	if (!priv)
+		return -EINVAL;
+
+	regs = priv->esdhc_regs;
+
+	/* First reset the eSDHC controller */
+	ret = esdhc_reset(regs);
+	if (ret)
+		return ret;
+
+#ifdef CONFIG_MCF5441x
+	/* ColdFire, using SDHC_DATA[3] for card detection */
+	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
+#endif
+
+#ifndef CONFIG_FSL_USDHC
+	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
+				| SYSCTL_IPGEN | SYSCTL_CKEN);
+	/* Clearing tuning bits in case ROM has set it already */
+	esdhc_write32(&regs->mixctrl, 0);
+	esdhc_write32(&regs->autoc12err, 0);
+	esdhc_write32(&regs->clktunectrlstatus, 0);
+#else
+	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
+			VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
+#endif
+
+	if (priv->vs18_enable)
+		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
+
+	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
+	cfg = &plat->cfg;
+#ifndef CONFIG_DM_MMC
+	memset(cfg, '\0', sizeof(*cfg));
+#endif
+
+	voltage_caps = 0;
+	caps = esdhc_read32(&regs->hostcapblt);
+
+#ifdef CONFIG_MCF5441x
+	/*
+	 * MCF5441x RM declares in more points that sdhc clock speed must
+	 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
+	 * from host capabilities.
+	 */
+	caps &= ~ESDHC_HOSTCAPBLT_HSS;
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
+	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
+			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
+#endif
+
+/* T4240 host controller capabilities register should have VS33 bit */
+#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+	caps = caps | ESDHC_HOSTCAPBLT_VS33;
+#endif
+
+	if (caps & ESDHC_HOSTCAPBLT_VS18)
+		voltage_caps |= MMC_VDD_165_195;
+	if (caps & ESDHC_HOSTCAPBLT_VS30)
+		voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
+	if (caps & ESDHC_HOSTCAPBLT_VS33)
+		voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
+
+	cfg->name = "FSL_SDHC";
+#if !CONFIG_IS_ENABLED(DM_MMC)
+	cfg->ops = &esdhc_ops;
+#endif
+#ifdef CONFIG_SYS_SD_VOLTAGE
+	cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
+#else
+	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
+#endif
+	if ((cfg->voltages & voltage_caps) == 0) {
+		printf("voltage not supported by controller\n");
+		return -1;
+	}
+
+	if (priv->bus_width == 8)
+		cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+	else if (priv->bus_width == 4)
+		cfg->host_caps = MMC_MODE_4BIT;
+
+	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
+#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
+	cfg->host_caps |= MMC_MODE_DDR_52MHz;
+#endif
+
+	if (priv->bus_width > 0) {
+		if (priv->bus_width < 8)
+			cfg->host_caps &= ~MMC_MODE_8BIT;
+		if (priv->bus_width < 4)
+			cfg->host_caps &= ~MMC_MODE_4BIT;
+	}
+
+	if (caps & ESDHC_HOSTCAPBLT_HSS)
+		cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+	if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+		cfg->host_caps &= ~MMC_MODE_8BIT;
+#endif
+
+	cfg->host_caps |= priv->caps;
+
+	cfg->f_min = 400000;
+	cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
+
+	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
+
+	writel(0, &regs->dllctrl);
+	if (priv->flags & ESDHC_FLAG_USDHC) {
+		if (priv->flags & ESDHC_FLAG_STD_TUNING) {
+			u32 val = readl(&regs->tuning_ctrl);
+
+			val |= ESDHC_STD_TUNING_EN;
+			val &= ~ESDHC_TUNING_START_TAP_MASK;
+			val |= priv->tuning_start_tap;
+			val &= ~ESDHC_TUNING_STEP_MASK;
+			val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
+			writel(val, &regs->tuning_ctrl);
+		}
+	}
+
+	return 0;
+}
+
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
+				 struct fsl_esdhc_priv *priv)
+{
+	if (!cfg || !priv)
+		return -EINVAL;
+
+	priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
+	priv->bus_width = cfg->max_bus_width;
+	priv->sdhc_clk = cfg->sdhc_clk;
+	priv->wp_enable  = cfg->wp_enable;
+	priv->vs18_enable  = cfg->vs18_enable;
+
+	return 0;
+};
+
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
+{
+	struct fsl_esdhc_plat *plat;
+	struct fsl_esdhc_priv *priv;
+	struct mmc *mmc;
+	int ret;
+
+	if (!cfg)
+		return -EINVAL;
+
+	priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
+	if (!priv)
+		return -ENOMEM;
+	plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
+	if (!plat) {
+		free(priv);
+		return -ENOMEM;
+	}
+
+	ret = fsl_esdhc_cfg_to_priv(cfg, priv);
+	if (ret) {
+		debug("%s xlate failure\n", __func__);
+		free(plat);
+		free(priv);
+		return ret;
+	}
+
+	ret = fsl_esdhc_init(priv, plat);
+	if (ret) {
+		debug("%s init failure\n", __func__);
+		free(plat);
+		free(priv);
+		return ret;
+	}
+
+	mmc = mmc_create(&plat->cfg, priv);
+	if (!mmc)
+		return -EIO;
+
+	priv->mmc = mmc;
+
+	return 0;
+}
+
+int fsl_esdhc_mmc_init(bd_t *bis)
+{
+	struct fsl_esdhc_cfg *cfg;
+
+	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
+	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
+	cfg->sdhc_clk = gd->arch.sdhc_clk;
+	return fsl_esdhc_initialize(bis, cfg);
+}
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+__weak int esdhc_status_fixup(void *blob, const char *compat)
+{
+#ifdef CONFIG_FSL_ESDHC_PIN_MUX
+	if (!hwconfig("esdhc")) {
+		do_fixup_by_compat(blob, compat, "status", "disabled",
+				sizeof("disabled"), 1);
+		return 1;
+	}
+#endif
+	return 0;
+}
+
+void fdt_fixup_esdhc(void *blob, bd_t *bd)
+{
+	const char *compat = "fsl,esdhc";
+
+	if (esdhc_status_fixup(blob, compat))
+		return;
+
+#ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
+	do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
+			       gd->arch.sdhc_clk, 1);
+#else
+	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
+			       gd->arch.sdhc_clk, 1);
+#endif
+}
+#endif
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+#include <asm/arch/clock.h>
+__weak void init_clk_usdhc(u32 index)
+{
+}
+
+static int fsl_esdhc_probe(struct udevice *dev)
+{
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+	const void *fdt = gd->fdt_blob;
+	int node = dev_of_offset(dev);
+	struct esdhc_soc_data *data =
+		(struct esdhc_soc_data *)dev_get_driver_data(dev);
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	struct udevice *vqmmc_dev;
+#endif
+	fdt_addr_t addr;
+	unsigned int val;
+	struct mmc *mmc;
+#if !CONFIG_IS_ENABLED(BLK)
+	struct blk_desc *bdesc;
+#endif
+	int ret;
+
+	addr = dev_read_addr(dev);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+	priv->esdhc_regs = (struct fsl_esdhc *)addr;
+	priv->dev = dev;
+	priv->mode = -1;
+	if (data) {
+		priv->flags = data->flags;
+		priv->caps = data->caps;
+	}
+
+	val = dev_read_u32_default(dev, "bus-width", -1);
+	if (val == 8)
+		priv->bus_width = 8;
+	else if (val == 4)
+		priv->bus_width = 4;
+	else
+		priv->bus_width = 1;
+
+	val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
+	priv->tuning_step = val;
+	val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
+			     ESDHC_TUNING_START_TAP_DEFAULT);
+	priv->tuning_start_tap = val;
+	val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
+			     ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
+	priv->strobe_dll_delay_target = val;
+
+	if (dev_read_bool(dev, "non-removable")) {
+		priv->non_removable = 1;
+	 } else {
+		priv->non_removable = 0;
+#ifdef CONFIG_DM_GPIO
+		gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
+				     GPIOD_IS_IN);
+#endif
+	}
+
+	if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
+		priv->wp_enable = 1;
+	} else {
+		priv->wp_enable = 0;
+#ifdef CONFIG_DM_GPIO
+		gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
+				   GPIOD_IS_IN);
+#endif
+	}
+
+	priv->vs18_enable = 0;
+
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+	/*
+	 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
+	 * otherwise, emmc will work abnormally.
+	 */
+	ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
+	if (ret) {
+		dev_dbg(dev, "no vqmmc-supply\n");
+	} else {
+		ret = regulator_set_enable(vqmmc_dev, true);
+		if (ret) {
+			dev_err(dev, "fail to enable vqmmc-supply\n");
+			return ret;
+		}
+
+		if (regulator_get_value(vqmmc_dev) == 1800000)
+			priv->vs18_enable = 1;
+	}
+#endif
+
+	if (fdt_get_property(fdt, node, "no-1-8-v", NULL))
+		priv->caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400);
+
+	/*
+	 * TODO:
+	 * Because lack of clk driver, if SDHC clk is not enabled,
+	 * need to enable it first before this driver is invoked.
+	 *
+	 * we use MXC_ESDHC_CLK to get clk freq.
+	 * If one would like to make this function work,
+	 * the aliases should be provided in dts as this:
+	 *
+	 *  aliases {
+	 *	mmc0 = &usdhc1;
+	 *	mmc1 = &usdhc2;
+	 *	mmc2 = &usdhc3;
+	 *	mmc3 = &usdhc4;
+	 *	};
+	 * Then if your board only supports mmc2 and mmc3, but we can
+	 * correctly get the seq as 2 and 3, then let mxc_get_clock
+	 * work as expected.
+	 */
+
+	init_clk_usdhc(dev->seq);
+
+	if (IS_ENABLED(CONFIG_CLK)) {
+		/* Assigned clock already set clock */
+		ret = clk_get_by_name(dev, "per", &priv->per_clk);
+		if (ret) {
+			printf("Failed to get per_clk\n");
+			return ret;
+		}
+		ret = clk_enable(&priv->per_clk);
+		if (ret) {
+			printf("Failed to enable per_clk\n");
+			return ret;
+		}
+
+		priv->sdhc_clk = clk_get_rate(&priv->per_clk);
+	} else {
+		priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
+		if (priv->sdhc_clk <= 0) {
+			dev_err(dev, "Unable to get clk for %s\n", dev->name);
+			return -EINVAL;
+		}
+	}
+
+	ret = fsl_esdhc_init(priv, plat);
+	if (ret) {
+		dev_err(dev, "fsl_esdhc_init failure\n");
+		return ret;
+	}
+
+	mmc = &plat->mmc;
+	mmc->cfg = &plat->cfg;
+	mmc->dev = dev;
+#if !CONFIG_IS_ENABLED(BLK)
+	mmc->priv = priv;
+
+	/* Setup dsr related values */
+	mmc->dsr_imp = 0;
+	mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
+	/* Setup the universal parts of the block interface just once */
+	bdesc = mmc_get_blk_desc(mmc);
+	bdesc->if_type = IF_TYPE_MMC;
+	bdesc->removable = 1;
+	bdesc->devnum = mmc_get_next_devnum();
+	bdesc->block_read = mmc_bread;
+	bdesc->block_write = mmc_bwrite;
+	bdesc->block_erase = mmc_berase;
+
+	/* setup initial part type */
+	bdesc->part_type = mmc->cfg->part_type;
+	mmc_list_add(mmc);
+#endif
+
+	upriv->mmc = mmc;
+
+	return esdhc_init_common(priv, mmc);
+}
+
+#if CONFIG_IS_ENABLED(DM_MMC)
+static int fsl_esdhc_get_cd(struct udevice *dev)
+{
+	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+	return esdhc_getcd_common(priv);
+}
+
+static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
+			      struct mmc_data *data)
+{
+	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+	return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
+}
+
+static int fsl_esdhc_set_ios(struct udevice *dev)
+{
+	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
+
+	return esdhc_set_ios_common(priv, &plat->mmc);
+}
+
+static const struct dm_mmc_ops fsl_esdhc_ops = {
+	.get_cd		= fsl_esdhc_get_cd,
+	.send_cmd	= fsl_esdhc_send_cmd,
+	.set_ios	= fsl_esdhc_set_ios,
+#ifdef MMC_SUPPORTS_TUNING
+	.execute_tuning	= fsl_esdhc_execute_tuning,
+#endif
+};
+#endif
+
+static struct esdhc_soc_data usdhc_imx7d_data = {
+	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
+			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
+			| ESDHC_FLAG_HS400,
+	.caps = UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_DDR_52MHz |
+		MMC_MODE_HS_52MHz | MMC_MODE_HS,
+};
+
+static const struct udevice_id fsl_esdhc_ids[] = {
+	{ .compatible = "fsl,imx53-esdhc", },
+	{ .compatible = "fsl,imx6ul-usdhc", },
+	{ .compatible = "fsl,imx6sx-usdhc", },
+	{ .compatible = "fsl,imx6sl-usdhc", },
+	{ .compatible = "fsl,imx6q-usdhc", },
+	{ .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
+	{ .compatible = "fsl,imx7ulp-usdhc", },
+	{ .compatible = "fsl,esdhc", },
+	{ /* sentinel */ }
+};
+
+#if CONFIG_IS_ENABLED(BLK)
+static int fsl_esdhc_bind(struct udevice *dev)
+{
+	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
+
+	return mmc_bind(dev, &plat->mmc, &plat->cfg);
+}
+#endif
+
+U_BOOT_DRIVER(fsl_esdhc) = {
+	.name	= "fsl-esdhc-mmc",
+	.id	= UCLASS_MMC,
+	.of_match = fsl_esdhc_ids,
+	.ops	= &fsl_esdhc_ops,
+#if CONFIG_IS_ENABLED(BLK)
+	.bind	= fsl_esdhc_bind,
+#endif
+	.probe	= fsl_esdhc_probe,
+	.platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
+	.priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
+};
+#endif
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 2b17eae..a78fd51 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -1,6 +1,6 @@
 menu "UBI support"
 
-config CONFIG_UBI_SILENCE_MSG
+config UBI_SILENCE_MSG
 	bool "UBI silence verbose messages"
 	default ENV_IS_IN_UBI
 	help
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index 8ef7823..688fb50 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -1351,6 +1351,7 @@
 
 		ubi_err(ubi, "self-check failed for PEB %d:%d, len %d",
 			pnum, offset, len);
+#if !defined(CONFIG_UBI_SILENCE_MSG)
 		ubi_msg(ubi, "data differ at position %d", i);
 		ubi_msg(ubi, "hex dump of the original buffer from %d to %d",
 			i, i + dump_len);
@@ -1360,6 +1361,7 @@
 			i, i + dump_len);
 		print_hex_dump("", DUMP_PREFIX_OFFSET, 32, 1,
 			       buf1 + i, dump_len, 1);
+#endif
 		dump_stack();
 		err = -EINVAL;
 		goto out_free;
diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c
index eeb1cbe..3f3b9b4 100644
--- a/drivers/mtd/ubispl/ubispl.c
+++ b/drivers/mtd/ubispl/ubispl.c
@@ -45,6 +45,187 @@
 	return peb >= ubi->peb_count || peb < 0;
 }
 
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+
+/**
+ * ubi_dump_vtbl_record - dump a &struct ubi_vtbl_record object.
+ * @r: the object to dump
+ * @idx: volume table index
+ */
+void ubi_dump_vtbl_record(const struct ubi_vtbl_record *r, int idx)
+{
+	int name_len = be16_to_cpu(r->name_len);
+
+	ubi_dbg("Volume table record %d dump: size: %d",
+		idx, sizeof(struct ubi_vtbl_record));
+	ubi_dbg("\treserved_pebs   %d", be32_to_cpu(r->reserved_pebs));
+	ubi_dbg("\talignment       %d", be32_to_cpu(r->alignment));
+	ubi_dbg("\tdata_pad        %d", be32_to_cpu(r->data_pad));
+	ubi_dbg("\tvol_type        %d", (int)r->vol_type);
+	ubi_dbg("\tupd_marker      %d", (int)r->upd_marker);
+	ubi_dbg("\tname_len        %d", name_len);
+
+	if (r->name[0] == '\0') {
+		ubi_dbg("\tname            NULL");
+		return;
+	}
+
+	if (name_len <= UBI_VOL_NAME_MAX &&
+	    strnlen(&r->name[0], name_len + 1) == name_len) {
+		ubi_dbg("\tname            %s", &r->name[0]);
+	} else {
+		ubi_dbg("\t1st 5 characters of name: %c%c%c%c%c",
+			r->name[0], r->name[1], r->name[2], r->name[3],
+			r->name[4]);
+	}
+	ubi_dbg("\tcrc             %#08x", be32_to_cpu(r->crc));
+}
+
+/* Empty volume table record */
+static struct ubi_vtbl_record empty_vtbl_record;
+
+/**
+ * vtbl_check - check if volume table is not corrupted and sensible.
+ * @ubi: UBI device description object
+ * @vtbl: volume table
+ *
+ * This function returns zero if @vtbl is all right, %1 if CRC is incorrect,
+ * and %-EINVAL if it contains inconsistent data.
+ */
+static int vtbl_check(struct ubi_scan_info *ubi,
+		      struct ubi_vtbl_record *vtbl)
+{
+	int i, n, reserved_pebs, alignment, data_pad, vol_type, name_len;
+	int upd_marker, err;
+	uint32_t crc;
+	const char *name;
+
+	for (i = 0; i < UBI_SPL_VOL_IDS; i++) {
+		reserved_pebs = be32_to_cpu(vtbl[i].reserved_pebs);
+		alignment = be32_to_cpu(vtbl[i].alignment);
+		data_pad = be32_to_cpu(vtbl[i].data_pad);
+		upd_marker = vtbl[i].upd_marker;
+		vol_type = vtbl[i].vol_type;
+		name_len = be16_to_cpu(vtbl[i].name_len);
+		name = &vtbl[i].name[0];
+
+		crc = crc32(UBI_CRC32_INIT, &vtbl[i], UBI_VTBL_RECORD_SIZE_CRC);
+		if (be32_to_cpu(vtbl[i].crc) != crc) {
+			ubi_err("bad CRC at record %u: %#08x, not %#08x",
+				i, crc, be32_to_cpu(vtbl[i].crc));
+			ubi_dump_vtbl_record(&vtbl[i], i);
+			return 1;
+		}
+
+		if (reserved_pebs == 0) {
+			if (memcmp(&vtbl[i], &empty_vtbl_record,
+				   UBI_VTBL_RECORD_SIZE)) {
+				err = 2;
+				goto bad;
+			}
+			continue;
+		}
+
+		if (reserved_pebs < 0 || alignment < 0 || data_pad < 0 ||
+		    name_len < 0) {
+			err = 3;
+			goto bad;
+		}
+
+		if (alignment > ubi->leb_size || alignment == 0) {
+			err = 4;
+			goto bad;
+		}
+
+		n = alignment & (CONFIG_SPL_UBI_VID_OFFSET - 1);
+		if (alignment != 1 && n) {
+			err = 5;
+			goto bad;
+		}
+
+		n = ubi->leb_size % alignment;
+		if (data_pad != n) {
+			ubi_err("bad data_pad, has to be %d", n);
+			err = 6;
+			goto bad;
+		}
+
+		if (vol_type != UBI_VID_DYNAMIC && vol_type != UBI_VID_STATIC) {
+			err = 7;
+			goto bad;
+		}
+
+		if (upd_marker != 0 && upd_marker != 1) {
+			err = 8;
+			goto bad;
+		}
+
+		if (name_len > UBI_VOL_NAME_MAX) {
+			err = 10;
+			goto bad;
+		}
+
+		if (name[0] == '\0') {
+			err = 11;
+			goto bad;
+		}
+
+		if (name_len != strnlen(name, name_len + 1)) {
+			err = 12;
+			goto bad;
+		}
+
+		ubi_dump_vtbl_record(&vtbl[i], i);
+	}
+
+	/* Checks that all names are unique */
+	for (i = 0; i < UBI_SPL_VOL_IDS - 1; i++) {
+		for (n = i + 1; n < UBI_SPL_VOL_IDS; n++) {
+			int len1 = be16_to_cpu(vtbl[i].name_len);
+			int len2 = be16_to_cpu(vtbl[n].name_len);
+
+			if (len1 > 0 && len1 == len2 &&
+			    !strncmp(vtbl[i].name, vtbl[n].name, len1)) {
+				ubi_err("volumes %d and %d have the same name \"%s\"",
+					i, n, vtbl[i].name);
+				ubi_dump_vtbl_record(&vtbl[i], i);
+				ubi_dump_vtbl_record(&vtbl[n], n);
+				return -EINVAL;
+			}
+		}
+	}
+
+	return 0;
+
+bad:
+	ubi_err("volume table check failed: record %d, error %d", i, err);
+	ubi_dump_vtbl_record(&vtbl[i], i);
+	return -EINVAL;
+}
+
+static int ubi_read_volume_table(struct ubi_scan_info *ubi, u32 pnum)
+{
+	int err = -EINVAL;
+
+	empty_vtbl_record.crc = cpu_to_be32(0xf116c36b);
+
+	err = ubi_io_read(ubi, &ubi->vtbl, pnum, ubi->leb_start,
+			  sizeof(struct ubi_vtbl_record) * UBI_SPL_VOL_IDS);
+	if (err && err != UBI_IO_BITFLIPS) {
+		ubi_err("unable to read volume table");
+		goto out;
+	}
+
+	if (!vtbl_check(ubi, ubi->vtbl)) {
+		ubi->vtbl_valid = 1;
+		err = 0;
+	}
+out:
+	return err;
+}
+
+#endif /* CONFIG_SPL_UBI_LOAD_BY_VOLNAME */
+
 static int ubi_io_read_vid_hdr(struct ubi_scan_info *ubi, int pnum,
 			       struct ubi_vid_hdr *vh, int unused)
 {
@@ -210,14 +391,23 @@
 	if (vol_id == UBI_FM_SB_VOLUME_ID)
 		return ubi->fm_enabled ? UBI_FASTMAP_ANCHOR : 0;
 
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+	/* If this is a UBI volume table, read it and return */
+	if (vol_id == UBI_LAYOUT_VOLUME_ID && !ubi->vtbl_valid) {
+		res = ubi_read_volume_table(ubi, pnum);
+		return res;
+	}
+#endif
+
 	/* We only care about static volumes with an id < UBI_SPL_VOL_IDS */
 	if (vol_id >= UBI_SPL_VOL_IDS || vh->vol_type != UBI_VID_STATIC)
 		return 0;
 
+#ifndef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
 	/* We are only interested in the volumes to load */
 	if (!test_bit(vol_id, ubi->toload))
 		return 0;
-
+#endif
 	lnum = be32_to_cpu(vh->lnum);
 	return ubi_add_peb_to_vol(ubi, vh, vol_id, pnum, lnum);
 }
@@ -232,13 +422,14 @@
 
 	ubi->fastmap_pebs++;
 
+#ifndef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
 	if (vol_id >= UBI_SPL_VOL_IDS || vol_type != UBI_STATIC_VOLUME)
 		return 0;
 
 	/* We are only interested in the volumes to load */
 	if (!test_bit(vol_id, ubi->toload))
 		return 0;
-
+#endif
 	vh = ubi->blockinfo + pnum;
 
 	return ubi_scan_vid_hdr(ubi, vh, pnum);
@@ -892,6 +1083,10 @@
 	ubi->peb_count = info->peb_count;
 	ubi->peb_offset = info->peb_offset;
 
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+	ubi->vtbl_valid = 0;
+#endif
+
 	fsize = info->peb_size * info->peb_count;
 	ubi->fsize_mb = fsize >> 20;
 
@@ -910,7 +1105,23 @@
 	for (i = 0; i < nrvols; i++) {
 		struct ubispl_load *lv = lvols + i;
 
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+		if (lv->vol_id == -1) {
+			for (int j = 0; j < UBI_SPL_VOL_IDS; j++) {
+				int len = be16_to_cpu(ubi->vtbl[j].name_len);
+
+				if (strncmp(lv->name,
+					    ubi->vtbl[j].name,
+					    len) == 0) {
+					lv->vol_id = j;
+					break;
+				}
+			}
+		}
+		ubi_msg("Loading VolName %s (VolId #%d)", lv->name, lv->vol_id);
+#else
 		ubi_msg("Loading VolId #%d", lv->vol_id);
+#endif
 		res = ipl_load(ubi, lv->vol_id, lv->load_addr);
 		if (res < 0) {
 			if (fastmap) {
diff --git a/drivers/mtd/ubispl/ubispl.h b/drivers/mtd/ubispl/ubispl.h
index 9e40b46..b7cb7fc 100644
--- a/drivers/mtd/ubispl/ubispl.h
+++ b/drivers/mtd/ubispl/ubispl.h
@@ -77,6 +77,8 @@
  * @blockinfo:		The vid headers of the scanned blocks
  * @volinfo:		The volume information of the interesting (toload)
  *			volumes
+ * @vtbl_corrupted:	Flag to indicate status of volume table
+ * @vtbl:		Volume table
  *
  * @fm_buf:		The large fastmap attach buffer
  */
@@ -112,6 +114,11 @@
 	struct ubi_vol_info		volinfo[UBI_SPL_VOL_IDS];
 	struct ubi_vid_hdr		blockinfo[CONFIG_SPL_UBI_MAX_PEBS];
 
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+	/* Volume table */
+	int                             vtbl_valid;
+	struct ubi_vtbl_record          vtbl[UBI_SPL_VOL_IDS];
+#endif
 	/* The large buffer for the fastmap */
 	uint8_t				fm_buf[UBI_FM_BUF_SIZE];
 };
@@ -122,7 +129,7 @@
 #define ubi_dbg(fmt, ...)
 #endif
 
-#ifdef CONFIG_UBI_SILENCE_MSG
+#ifdef CONFIG_UBI_SPL_SILENCE_MSG
 #define ubi_msg(fmt, ...)
 #else
 #define ubi_msg(fmt, ...) printf("UBI: " fmt "\n", ##__VA_ARGS__)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 9469147..f9b2823 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -49,6 +49,14 @@
 	  uses driver model and requires a device tree binding to operate.
 	  please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
 
+config ATMEL_QSPI
+	bool "Atmel Quad SPI Controller"
+	depends on ARCH_AT91
+	help
+	  Enable the Atmel Quad SPI controller in master mode. This driver
+	  does not support generic SPI. The implementation supports only the
+	  spi-mem interface.
+
 config ATMEL_SPI
 	bool "Atmel SPI driver"
 	default y if ARCH_AT91
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 3f9f2fa..64c407e 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -18,6 +18,7 @@
 
 obj-$(CONFIG_ALTERA_SPI) += altera_spi.o
 obj-$(CONFIG_ATH79_SPI) += ath79_spi.o
+obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o
 obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o
 obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o
 obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
new file mode 100644
index 0000000..7d9a540
--- /dev/null
+++ b/drivers/spi/atmel-quadspi.c
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Atmel QSPI Controller
+ *
+ * Copyright (C) 2015 Atmel Corporation
+ * Copyright (C) 2018 Cryptera A/S
+ *
+ * Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
+ * Author: Piotr Bugalski <bugalski.piotr@gmail.com>
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/ioport.h>
+#include <mach/clk.h>
+#include <spi.h>
+#include <spi-mem.h>
+
+/* QSPI register offsets */
+#define QSPI_CR      0x0000  /* Control Register */
+#define QSPI_MR      0x0004  /* Mode Register */
+#define QSPI_RD      0x0008  /* Receive Data Register */
+#define QSPI_TD      0x000c  /* Transmit Data Register */
+#define QSPI_SR      0x0010  /* Status Register */
+#define QSPI_IER     0x0014  /* Interrupt Enable Register */
+#define QSPI_IDR     0x0018  /* Interrupt Disable Register */
+#define QSPI_IMR     0x001c  /* Interrupt Mask Register */
+#define QSPI_SCR     0x0020  /* Serial Clock Register */
+
+#define QSPI_IAR     0x0030  /* Instruction Address Register */
+#define QSPI_ICR     0x0034  /* Instruction Code Register */
+#define QSPI_WICR    0x0034  /* Write Instruction Code Register */
+#define QSPI_IFR     0x0038  /* Instruction Frame Register */
+#define QSPI_RICR    0x003C  /* Read Instruction Code Register */
+
+#define QSPI_SMR     0x0040  /* Scrambling Mode Register */
+#define QSPI_SKR     0x0044  /* Scrambling Key Register */
+
+#define QSPI_WPMR    0x00E4  /* Write Protection Mode Register */
+#define QSPI_WPSR    0x00E8  /* Write Protection Status Register */
+
+#define QSPI_VERSION 0x00FC  /* Version Register */
+
+/* Bitfields in QSPI_CR (Control Register) */
+#define QSPI_CR_QSPIEN                  BIT(0)
+#define QSPI_CR_QSPIDIS                 BIT(1)
+#define QSPI_CR_SWRST                   BIT(7)
+#define QSPI_CR_LASTXFER                BIT(24)
+
+/* Bitfields in QSPI_MR (Mode Register) */
+#define QSPI_MR_SMM                     BIT(0)
+#define QSPI_MR_LLB                     BIT(1)
+#define QSPI_MR_WDRBT                   BIT(2)
+#define QSPI_MR_SMRM                    BIT(3)
+#define QSPI_MR_CSMODE_MASK             GENMASK(5, 4)
+#define QSPI_MR_CSMODE_NOT_RELOADED     (0 << 4)
+#define QSPI_MR_CSMODE_LASTXFER         (1 << 4)
+#define QSPI_MR_CSMODE_SYSTEMATICALLY   (2 << 4)
+#define QSPI_MR_NBBITS_MASK             GENMASK(11, 8)
+#define QSPI_MR_NBBITS(n)               ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
+#define QSPI_MR_DLYBCT_MASK             GENMASK(23, 16)
+#define QSPI_MR_DLYBCT(n)               (((n) << 16) & QSPI_MR_DLYBCT_MASK)
+#define QSPI_MR_DLYCS_MASK              GENMASK(31, 24)
+#define QSPI_MR_DLYCS(n)                (((n) << 24) & QSPI_MR_DLYCS_MASK)
+
+/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR  */
+#define QSPI_SR_RDRF                    BIT(0)
+#define QSPI_SR_TDRE                    BIT(1)
+#define QSPI_SR_TXEMPTY                 BIT(2)
+#define QSPI_SR_OVRES                   BIT(3)
+#define QSPI_SR_CSR                     BIT(8)
+#define QSPI_SR_CSS                     BIT(9)
+#define QSPI_SR_INSTRE                  BIT(10)
+#define QSPI_SR_QSPIENS                 BIT(24)
+
+#define QSPI_SR_CMD_COMPLETED	(QSPI_SR_INSTRE | QSPI_SR_CSR)
+
+/* Bitfields in QSPI_SCR (Serial Clock Register) */
+#define QSPI_SCR_CPOL                   BIT(0)
+#define QSPI_SCR_CPHA                   BIT(1)
+#define QSPI_SCR_SCBR_MASK              GENMASK(15, 8)
+#define QSPI_SCR_SCBR(n)                (((n) << 8) & QSPI_SCR_SCBR_MASK)
+#define QSPI_SCR_DLYBS_MASK             GENMASK(23, 16)
+#define QSPI_SCR_DLYBS(n)               (((n) << 16) & QSPI_SCR_DLYBS_MASK)
+
+/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
+#define QSPI_ICR_INST_MASK              GENMASK(7, 0)
+#define QSPI_ICR_INST(inst)             (((inst) << 0) & QSPI_ICR_INST_MASK)
+#define QSPI_ICR_OPT_MASK               GENMASK(23, 16)
+#define QSPI_ICR_OPT(opt)               (((opt) << 16) & QSPI_ICR_OPT_MASK)
+
+/* Bitfields in QSPI_IFR (Instruction Frame Register) */
+#define QSPI_IFR_WIDTH_MASK             GENMASK(2, 0)
+#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI   (0 << 0)
+#define QSPI_IFR_WIDTH_DUAL_OUTPUT      (1 << 0)
+#define QSPI_IFR_WIDTH_QUAD_OUTPUT      (2 << 0)
+#define QSPI_IFR_WIDTH_DUAL_IO          (3 << 0)
+#define QSPI_IFR_WIDTH_QUAD_IO          (4 << 0)
+#define QSPI_IFR_WIDTH_DUAL_CMD         (5 << 0)
+#define QSPI_IFR_WIDTH_QUAD_CMD         (6 << 0)
+#define QSPI_IFR_INSTEN                 BIT(4)
+#define QSPI_IFR_ADDREN                 BIT(5)
+#define QSPI_IFR_OPTEN                  BIT(6)
+#define QSPI_IFR_DATAEN                 BIT(7)
+#define QSPI_IFR_OPTL_MASK              GENMASK(9, 8)
+#define QSPI_IFR_OPTL_1BIT              (0 << 8)
+#define QSPI_IFR_OPTL_2BIT              (1 << 8)
+#define QSPI_IFR_OPTL_4BIT              (2 << 8)
+#define QSPI_IFR_OPTL_8BIT              (3 << 8)
+#define QSPI_IFR_ADDRL                  BIT(10)
+#define QSPI_IFR_TFRTYP_MEM		BIT(12)
+#define QSPI_IFR_SAMA5D2_WRITE_TRSFR	BIT(13)
+#define QSPI_IFR_CRM                    BIT(14)
+#define QSPI_IFR_NBDUM_MASK             GENMASK(20, 16)
+#define QSPI_IFR_NBDUM(n)               (((n) << 16) & QSPI_IFR_NBDUM_MASK)
+#define QSPI_IFR_APBTFRTYP_READ		BIT(24)	/* Defined in SAM9X60 */
+
+/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
+#define QSPI_SMR_SCREN                  BIT(0)
+#define QSPI_SMR_RVDIS                  BIT(1)
+
+/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
+#define QSPI_WPMR_WPEN                  BIT(0)
+#define QSPI_WPMR_WPKEY_MASK            GENMASK(31, 8)
+#define QSPI_WPMR_WPKEY(wpkey)          (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
+
+/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
+#define QSPI_WPSR_WPVS                  BIT(0)
+#define QSPI_WPSR_WPVSRC_MASK           GENMASK(15, 8)
+#define QSPI_WPSR_WPVSRC(src)           (((src) << 8) & QSPI_WPSR_WPVSRC)
+
+struct atmel_qspi_caps {
+	bool has_qspick;
+	bool has_ricr;
+};
+
+struct atmel_qspi {
+	void __iomem *regs;
+	void __iomem *mem;
+	const struct atmel_qspi_caps *caps;
+	ulong bus_clk_rate;
+	u32 mr;
+};
+
+struct atmel_qspi_mode {
+	u8 cmd_buswidth;
+	u8 addr_buswidth;
+	u8 data_buswidth;
+	u32 config;
+};
+
+static const struct atmel_qspi_mode atmel_qspi_modes[] = {
+	{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
+	{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
+	{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
+	{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
+	{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
+	{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
+	{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
+};
+
+static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
+					    const struct atmel_qspi_mode *mode)
+{
+	if (op->cmd.buswidth != mode->cmd_buswidth)
+		return false;
+
+	if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
+		return false;
+
+	if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
+		return false;
+
+	return true;
+}
+
+static int atmel_qspi_find_mode(const struct spi_mem_op *op)
+{
+	u32 i;
+
+	for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
+		if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
+			return i;
+
+	return -ENOTSUPP;
+}
+
+static bool atmel_qspi_supports_op(struct spi_slave *slave,
+				   const struct spi_mem_op *op)
+{
+	if (atmel_qspi_find_mode(op) < 0)
+		return false;
+
+	/* special case not supported by hardware */
+	if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
+	    op->dummy.nbytes == 0)
+		return false;
+
+	return true;
+}
+
+static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
+			      const struct spi_mem_op *op, u32 *offset)
+{
+	u32 iar, icr, ifr;
+	u32 dummy_cycles = 0;
+	int mode;
+
+	iar = 0;
+	icr = QSPI_ICR_INST(op->cmd.opcode);
+	ifr = QSPI_IFR_INSTEN;
+
+	mode = atmel_qspi_find_mode(op);
+	if (mode < 0)
+		return mode;
+	ifr |= atmel_qspi_modes[mode].config;
+
+	if (op->dummy.buswidth && op->dummy.nbytes)
+		dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
+
+	/*
+	 * The controller allows 24 and 32-bit addressing while NAND-flash
+	 * requires 16-bit long. Handling 8-bit long addresses is done using
+	 * the option field. For the 16-bit addresses, the workaround depends
+	 * of the number of requested dummy bits. If there are 8 or more dummy
+	 * cycles, the address is shifted and sent with the first dummy byte.
+	 * Otherwise opcode is disabled and the first byte of the address
+	 * contains the command opcode (works only if the opcode and address
+	 * use the same buswidth). The limitation is when the 16-bit address is
+	 * used without enough dummy cycles and the opcode is using a different
+	 * buswidth than the address.
+	 */
+	if (op->addr.buswidth) {
+		switch (op->addr.nbytes) {
+		case 0:
+			break;
+		case 1:
+			ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
+			icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
+			break;
+		case 2:
+			if (dummy_cycles < 8 / op->addr.buswidth) {
+				ifr &= ~QSPI_IFR_INSTEN;
+				ifr |= QSPI_IFR_ADDREN;
+				iar = (op->cmd.opcode << 16) |
+					(op->addr.val & 0xffff);
+			} else {
+				ifr |= QSPI_IFR_ADDREN;
+				iar = (op->addr.val << 8) & 0xffffff;
+				dummy_cycles -= 8 / op->addr.buswidth;
+			}
+			break;
+		case 3:
+			ifr |= QSPI_IFR_ADDREN;
+			iar = op->addr.val & 0xffffff;
+			break;
+		case 4:
+			ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
+			iar = op->addr.val & 0x7ffffff;
+			break;
+		default:
+			return -ENOTSUPP;
+		}
+	}
+
+	/* offset of the data access in the QSPI memory space */
+	*offset = iar;
+
+	/* Set number of dummy cycles */
+	if (dummy_cycles)
+		ifr |= QSPI_IFR_NBDUM(dummy_cycles);
+
+	/* Set data enable */
+	if (op->data.nbytes)
+		ifr |= QSPI_IFR_DATAEN;
+
+	/*
+	 * If the QSPI controller is set in regular SPI mode, set it in
+	 * Serial Memory Mode (SMM).
+	 */
+	if (aq->mr != QSPI_MR_SMM) {
+		writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+		aq->mr = QSPI_MR_SMM;
+	}
+
+	/* Clear pending interrupts */
+	(void)readl(aq->regs + QSPI_SR);
+
+	if (aq->caps->has_ricr) {
+		if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
+			ifr |= QSPI_IFR_APBTFRTYP_READ;
+
+		/* Set QSPI Instruction Frame registers */
+		writel(iar, aq->regs + QSPI_IAR);
+		if (op->data.dir == SPI_MEM_DATA_IN)
+			writel(icr, aq->regs + QSPI_RICR);
+		else
+			writel(icr, aq->regs + QSPI_WICR);
+		writel(ifr, aq->regs + QSPI_IFR);
+	} else {
+		if (op->data.dir == SPI_MEM_DATA_OUT)
+			ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
+
+		/* Set QSPI Instruction Frame registers */
+		writel(iar, aq->regs + QSPI_IAR);
+		writel(icr, aq->regs + QSPI_ICR);
+		writel(ifr, aq->regs + QSPI_IFR);
+	}
+
+	return 0;
+}
+
+static int atmel_qspi_exec_op(struct spi_slave *slave,
+			      const struct spi_mem_op *op)
+{
+	struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
+	u32 sr, imr, offset;
+	int err;
+
+	err = atmel_qspi_set_cfg(aq, op, &offset);
+	if (err)
+		return err;
+
+	/* Skip to the final steps if there is no data */
+	if (op->data.nbytes) {
+		/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
+		(void)readl(aq->regs + QSPI_IFR);
+
+		/* Send/Receive data */
+		if (op->data.dir == SPI_MEM_DATA_IN)
+			memcpy_fromio(op->data.buf.in, aq->mem + offset,
+				      op->data.nbytes);
+		else
+			memcpy_toio(aq->mem + offset, op->data.buf.out,
+				    op->data.nbytes);
+
+		/* Release the chip-select */
+		writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
+	}
+
+	/* Poll INSTruction End and Chip Select Rise flags. */
+	imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
+	return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
+				  1000000);
+}
+
+static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
+{
+	struct atmel_qspi *aq = dev_get_priv(bus);
+	u32 scr, scbr, mask, new_value;
+
+	/* Compute the QSPI baudrate */
+	scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
+	if (scbr > 0)
+		scbr--;
+
+	new_value = QSPI_SCR_SCBR(scbr);
+	mask = QSPI_SCR_SCBR_MASK;
+
+	scr = readl(aq->regs + QSPI_SCR);
+	if ((scr & mask) == new_value)
+		return 0;
+
+	scr = (scr & ~mask) | new_value;
+	writel(scr, aq->regs + QSPI_SCR);
+
+	return 0;
+}
+
+static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
+{
+	struct atmel_qspi *aq = dev_get_priv(bus);
+	u32 scr, mask, new_value = 0;
+
+	if (mode & SPI_CPOL)
+		new_value = QSPI_SCR_CPOL;
+	if (mode & SPI_CPHA)
+		new_value = QSPI_SCR_CPHA;
+
+	mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
+
+	scr = readl(aq->regs + QSPI_SCR);
+	if ((scr & mask) == new_value)
+		return 0;
+
+	scr = (scr & ~mask) | new_value;
+	writel(scr, aq->regs + QSPI_SCR);
+
+	return 0;
+}
+
+static int atmel_qspi_enable_clk(struct udevice *dev)
+{
+	struct atmel_qspi *aq = dev_get_priv(dev);
+	struct clk pclk, qspick;
+	int ret;
+
+	ret = clk_get_by_name(dev, "pclk", &pclk);
+	if (ret)
+		ret = clk_get_by_index(dev, 0, &pclk);
+
+	if (ret) {
+		dev_err(dev, "Missing QSPI peripheral clock\n");
+		return ret;
+	}
+
+	ret = clk_enable(&pclk);
+	if (ret) {
+		dev_err(dev, "Failed to enable QSPI peripheral clock\n");
+		goto free_pclk;
+	}
+
+	if (aq->caps->has_qspick) {
+		/* Get the QSPI system clock */
+		ret = clk_get_by_name(dev, "qspick", &qspick);
+		if (ret) {
+			dev_err(dev, "Missing QSPI peripheral clock\n");
+			goto free_pclk;
+		}
+
+		ret = clk_enable(&qspick);
+		if (ret)
+			dev_err(dev, "Failed to enable QSPI system clock\n");
+		clk_free(&qspick);
+	}
+
+	aq->bus_clk_rate = clk_get_rate(&pclk);
+	if (!aq->bus_clk_rate)
+		ret = -EINVAL;
+
+free_pclk:
+	clk_free(&pclk);
+
+	return ret;
+}
+
+static void atmel_qspi_init(struct atmel_qspi *aq)
+{
+	/* Reset the QSPI controller */
+	writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
+
+	/* Set the QSPI controller by default in Serial Memory Mode */
+	writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+	aq->mr = QSPI_MR_SMM;
+
+	/* Enable the QSPI controller */
+	writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
+}
+
+static int atmel_qspi_probe(struct udevice *dev)
+{
+	struct atmel_qspi *aq = dev_get_priv(dev);
+	struct resource res;
+	int ret;
+
+	aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
+	if (!aq->caps) {
+		dev_err(dev, "Could not retrieve QSPI caps\n");
+		return -EINVAL;
+	};
+
+	/* Map the registers */
+	ret = dev_read_resource_byname(dev, "qspi_base", &res);
+	if (ret) {
+		dev_err(dev, "missing registers\n");
+		return ret;
+	}
+
+	aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
+	if (IS_ERR(aq->regs))
+		return PTR_ERR(aq->regs);
+
+	/* Map the AHB memory */
+	ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
+	if (ret) {
+		dev_err(dev, "missing AHB memory\n");
+		return ret;
+	}
+
+	aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
+	if (IS_ERR(aq->mem))
+		return PTR_ERR(aq->mem);
+
+	ret = atmel_qspi_enable_clk(dev);
+	if (ret)
+		return ret;
+
+	atmel_qspi_init(aq);
+
+	return 0;
+}
+
+static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
+	.supports_op = atmel_qspi_supports_op,
+	.exec_op = atmel_qspi_exec_op,
+};
+
+static const struct dm_spi_ops atmel_qspi_ops = {
+	.set_speed = atmel_qspi_set_speed,
+	.set_mode = atmel_qspi_set_mode,
+	.mem_ops = &atmel_qspi_mem_ops,
+};
+
+static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
+
+static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
+	.has_qspick = true,
+	.has_ricr = true,
+};
+
+static const struct udevice_id atmel_qspi_ids[] = {
+	{
+		.compatible = "atmel,sama5d2-qspi",
+		.data = (ulong)&atmel_sama5d2_qspi_caps,
+	},
+	{
+		.compatible = "microchip,sam9x60-qspi",
+		.data = (ulong)&atmel_sam9x60_qspi_caps,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(atmel_qspi) = {
+	.name           = "atmel_qspi",
+	.id             = UCLASS_SPI,
+	.of_match       = atmel_qspi_ids,
+	.ops            = &atmel_qspi_ops,
+	.priv_auto_alloc_size = sizeof(struct atmel_qspi),
+	.probe          = atmel_qspi_probe,
+};
diff --git a/env/Kconfig b/env/Kconfig
index b943917..d86a9bf 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -464,7 +464,7 @@
 	  It's a string of the EXT4 file name. This file use to store the
 	  environment (explicit path to the file)
 
-if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARC || ARCH_STM32MP
+if ARCH_ROCKCHIP || ARCH_SUNXI || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL || ARC || ARCH_STM32MP || ARCH_OMAP2PLUS || ARCH_AT91
 
 config ENV_OFFSET
 	hex "Environment Offset"
@@ -475,23 +475,26 @@
 	default 0xE0000 if ARCH_ZYNQ
 	default 0x1E00000 if ARCH_ZYNQMP
 	default 0 if ARC
+	default 0x140000 if ARCH_AT91
+	default 0x260000 if ARCH_OMAP2PLUS
 	help
 	  Offset from the start of the device (or partition)
 
 config ENV_SIZE
 	hex "Environment Size"
 	default 0x40000 if ENV_IS_IN_SPI_FLASH && ARCH_ZYNQMP
-	default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ
+	default 0x20000 if ARCH_SUNXI || ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
 	default 0x8000 if ARCH_ROCKCHIP || ARCH_ZYNQMP || ARCH_VERSAL
 	default 0x4000 if ARC
+	default 0x1f000
 	help
 	  Size of the environment storage area
 
 config ENV_SECT_SIZE
 	hex "Environment Sector-Size"
-	depends on !ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP)
+	depends on !ENV_IS_NOWHERE && (ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_OMAP2PLUS || ARCH_AT91)
 	default 0x40000 if ARCH_ZYNQMP
-	default 0x20000 if ARCH_ZYNQ
+	default 0x20000 if ARCH_ZYNQ || ARCH_OMAP2PLUS || ARCH_AT91
 	help
 	  Size of the sector containing the environment.
 
@@ -507,6 +510,19 @@
 	help
 	  Name of the volume that you want to store the environment in.
 
+config ENV_UBI_VOLUME_REDUND
+	string "UBI redundant volume name"
+	depends on ENV_IS_IN_UBI
+	help
+	  Name of the redundant volume that you want to store the environment in.
+
+config ENV_UBI_VID_OFFSET
+	int "ubi environment VID offset"
+	depends on ENV_IS_IN_UBI
+	default 0
+	help
+	  UBI VID offset for environment. If 0, no custom VID offset is used.
+
 endif
 
 config USE_DEFAULT_ENV_FILE
diff --git a/env/ubi.c b/env/ubi.c
index 1dfdf0a..e4b8516 100644
--- a/env/ubi.c
+++ b/env/ubi.c
@@ -15,6 +15,15 @@
 #include <ubi_uboot.h>
 #undef crc32
 
+#define _QUOTE(x) #x
+#define QUOTE(x) _QUOTE(x)
+
+#if (CONFIG_ENV_UBI_VID_OFFSET == 0)
+ #define UBI_VID_OFFSET NULL
+#else
+ #define UBI_VID_OFFSET QUOTE(CONFIG_ENV_UBI_VID_OFFSET)
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_CMD_SAVEENV
@@ -28,7 +37,7 @@
 	if (ret)
 		return ret;
 
-	if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) {
+	if (ubi_part(CONFIG_ENV_UBI_PART, UBI_VID_OFFSET)) {
 		printf("\n** Cannot find mtd partition \"%s\"\n",
 		       CONFIG_ENV_UBI_PART);
 		return 1;
@@ -70,7 +79,7 @@
 	if (ret)
 		return ret;
 
-	if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) {
+	if (ubi_part(CONFIG_ENV_UBI_PART, UBI_VID_OFFSET)) {
 		printf("\n** Cannot find mtd partition \"%s\"\n",
 		       CONFIG_ENV_UBI_PART);
 		return 1;
@@ -111,7 +120,7 @@
 	tmp_env1 = (env_t *)env1_buf;
 	tmp_env2 = (env_t *)env2_buf;
 
-	if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) {
+	if (ubi_part(CONFIG_ENV_UBI_PART, UBI_VID_OFFSET)) {
 		printf("\n** Cannot find mtd partition \"%s\"\n",
 		       CONFIG_ENV_UBI_PART);
 		set_default_env(NULL, 0);
@@ -148,7 +157,7 @@
 	 */
 	memset(buf, 0x0, CONFIG_ENV_SIZE);
 
-	if (ubi_part(CONFIG_ENV_UBI_PART, NULL)) {
+	if (ubi_part(CONFIG_ENV_UBI_PART, UBI_VID_OFFSET)) {
 		printf("\n** Cannot find mtd partition \"%s\"\n",
 		       CONFIG_ENV_UBI_PART);
 		set_default_env(NULL, 0);
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index b5fba0a..1885ac8 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -31,9 +31,6 @@
 #define V_OSCK				24000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
 
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE			SZ_128K
-
 #ifdef CONFIG_NAND
 #define NANDARGS \
 	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h
index 5fe7565..5b5e160 100644
--- a/include/configs/am335x_igep003x.h
+++ b/include/configs/am335x_igep003x.h
@@ -20,8 +20,6 @@
 #define V_OSCK				24000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
 
-#define CONFIG_ENV_SIZE			(96 << 10)	/*  96 KiB */
-
 #ifndef CONFIG_SPL_BUILD
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
@@ -108,27 +106,6 @@
 /* NAND support */
 #define CONFIG_SYS_NAND_ONFI_DETECTION	1
 
-/* SPL */
-
-/* UBI configuration */
-#define CONFIG_SPL_UBI			1
-#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
-#define CONFIG_SPL_UBI_MAX_PEB_SIZE	(256*1024)
-#define CONFIG_SPL_UBI_MAX_PEBS		4096
-#define CONFIG_SPL_UBI_VOL_IDS		8
-#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
-#define CONFIG_SPL_UBI_LOAD_KERNEL_ID	3
-#define CONFIG_SPL_UBI_LOAD_ARGS_ID	4
-#define CONFIG_SPL_UBI_PEB_OFFSET	4
-#define CONFIG_SPL_UBI_VID_OFFSET	512
-#define CONFIG_SPL_UBI_LEB_START	2048
-#define CONFIG_SPL_UBI_INFO_ADDR	0x88080000
-
-/* environment organization */
-#define CONFIG_ENV_UBI_PART		"UBI"
-#define CONFIG_ENV_UBI_VOLUME		"config"
-#define CONFIG_ENV_UBI_VOLUME_REDUND	"config_r"
-
 /* NAND config */
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h
index 381c75e..a08e6bf 100644
--- a/include/configs/am335x_sl50.h
+++ b/include/configs/am335x_sl50.h
@@ -22,9 +22,6 @@
 #define V_OSCK				24000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
 
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE			(128 << 10)
-
 #ifndef CONFIG_SPL_BUILD
 
 #define MEM_LAYOUT_ENV_SETTINGS \
diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h
index 2c51026..cacd799 100644
--- a/include/configs/am3517_crane.h
+++ b/include/configs/am3517_crane.h
@@ -31,7 +31,6 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 						/* initial data */
 /*
@@ -192,7 +191,6 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB sector */
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_ADDR			0x260000
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index 9475e99..e0521ab 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -184,8 +184,6 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_SIZE			CONFIG_SYS_ENV_SECT_SIZE
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_ADDR			0x260000
 
 /* Defines for SPL */
diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h
index ef85cd2..b0d95599 100644
--- a/include/configs/am43xx_evm.h
+++ b/include/configs/am43xx_evm.h
@@ -59,9 +59,6 @@
 /* Now bring in the rest of the common code. */
 #include <configs/ti_armv7_omap.h>
 
-/* Always 64 KiB env size */
-#define CONFIG_ENV_SIZE			(64 << 10)
-
 /* Clock Defines */
 #define V_OSCK				24000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
@@ -114,8 +111,6 @@
 
 #ifdef CONFIG_QSPI_BOOT
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SECT_SIZE           (64 << 10) /* 64 KB sectors */
-#define CONFIG_ENV_OFFSET              0x110000
 #define CONFIG_ENV_OFFSET_REDUND       0x120000
 #endif
 
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 2c651aa..e69e800 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -19,8 +19,6 @@
 /* MMC ENV related defines */
 #define CONFIG_SYS_MMC_ENV_DEV		1		/* eMMC */
 #define CONFIG_SYS_MMC_ENV_PART		0
-#define CONFIG_ENV_SIZE			SZ_128K
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index 780ae61..32623c2 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -15,7 +15,6 @@
 
 #undef CONFIG_BOOTM_NETBSD
 
-#define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define USDHC1_BASE_ADDR		0x5b010000
diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h
index 30c6cd4..1b8373f 100644
--- a/include/configs/at91-sama5_common.h
+++ b/include/configs/at91-sama5_common.h
@@ -57,21 +57,23 @@
 
 #ifdef CONFIG_NAND_BOOT
 /* u-boot env in nand flash */
-#define CONFIG_ENV_OFFSET		0x140000
 #define CONFIG_ENV_OFFSET_REDUND	0x100000
-#define CONFIG_ENV_SIZE			0x20000
 #define CONFIG_BOOTCOMMAND		"nand read 0x21000000 0x180000 0x80000;"	\
 					"nand read 0x22000000 0x200000 0x600000;"	\
 					"bootz 0x22000000 - 0x21000000"
 #elif CONFIG_SPI_BOOT
 /* u-boot env in serial flash, by default is bus 0 and cs 0 */
-#define CONFIG_ENV_OFFSET		0x6000
-#define CONFIG_ENV_SIZE			0x2000
-#define CONFIG_ENV_SECT_SIZE		0x1000
 #define CONFIG_BOOTCOMMAND		"sf probe 0; "				\
 					"sf read 0x21000000 0x60000 0xc000; "	\
 					"sf read 0x22000000 0x6c000 0x394000; "	\
 					"bootz 0x22000000 - 0x21000000"
+#elif CONFIG_QSPI_BOOT
+#define CONFIG_ENV_OFFSET		0x140000
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_BOOTCOMMAND		"sf probe 0; "					\
+					"sf read 0x21000000 0x180000 0x80000; "		\
+					"sf read 0x22000000 0x200000 0x600000; "	\
+					"bootz 0x22000000 - 0x21000000"
 #endif
 
 #endif
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index e2a2f3b..8bfba35 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -145,7 +145,7 @@
  */
 #define CONFIG_ENV_ADDR			\
 		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE			SZ_64K /* sectors are 64K here */
+
 /* The following #defines are needed to get flash environment right */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_MONITOR_LEN		SZ_256K
diff --git a/include/configs/baltos.h b/include/configs/baltos.h
index fbf657f..a9b14c5 100644
--- a/include/configs/baltos.h
+++ b/include/configs/baltos.h
@@ -25,9 +25,6 @@
 #define V_OSCK				24000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
 
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE			(128 << 10)
-
 /* FIT support */
 #define CONFIG_SYS_BOOTM_LEN         SZ_64M
 
diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h
index 0525efa..bfa9fc9 100644
--- a/include/configs/bav335x.h
+++ b/include/configs/bav335x.h
@@ -31,9 +31,6 @@
 #define V_OSCK				24000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
 
-/* Always 128 KiB env size */
-#define CONFIG_ENV_SIZE			(128 << 10)
-
 #ifdef CONFIG_NAND
 #define NANDARGS \
 	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h
index 82f3f1a..5a40f3a 100644
--- a/include/configs/brppt1.h
+++ b/include/configs/brppt1.h
@@ -59,9 +59,6 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
 #endif /* CONFIG_NAND */
 
-/* Always 64 KiB env size */
-#define CONFIG_ENV_SIZE			(64 << 10)
-
 #ifdef CONFIG_NAND
 #define NANDTGTS \
 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
@@ -187,8 +184,6 @@
 #define CONFIG_SYS_SPI_U_BOOT_OFFS		0x40000
 /* Environment */
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SECT_SIZE			CONFIG_ENV_SIZE
-#define CONFIG_ENV_OFFSET			0x20000
 #define CONFIG_ENV_OFFSET_REDUND		(CONFIG_ENV_OFFSET + \
 						 CONFIG_ENV_SECT_SIZE)
 #elif defined(CONFIG_ENV_IS_IN_MMC)
diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h
index db990fc..13c15bd 100644
--- a/include/configs/chiliboard.h
+++ b/include/configs/chiliboard.h
@@ -161,15 +161,11 @@
 #endif
 
 #if defined(CONFIG_ENV_IS_IN_NAND)
-#define CONFIG_ENV_OFFSET		0x001c0000
 #define CONFIG_ENV_OFFSET_REDUND	0x001e0000
-#define CONFIG_ENV_SIZE			SZ_128K
 #define CONFIG_SYS_ENV_SECT_SIZE	CONFIG_SYS_NAND_BLOCK_SIZE
 #else
 #define CONFIG_SYS_MMC_ENV_DEV		0
-#define CONFIG_ENV_OFFSET		SZ_128K
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE			SZ_8K
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #endif
 
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
index 740bbd4..54f2cea 100644
--- a/include/configs/cm_t335.h
+++ b/include/configs/cm_t335.h
@@ -23,8 +23,6 @@
 #define V_OSCK				25000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
 
-#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */
-
 #ifndef CONFIG_SPL_BUILD
 #define MMCARGS \
 	"mmcdev=0\0" \
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index fd693cf..f9a6444 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -39,7 +39,6 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KiB */
 					/* Sector */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 10))
 
@@ -179,7 +178,6 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */
 
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_ADDR			0x260000
 
 /* additions for new relocation code, must be added to all boards */
diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h
index bd40989..b2c1300 100644
--- a/include/configs/cm_t43.h
+++ b/include/configs/cm_t43.h
@@ -75,14 +75,9 @@
 #include <configs/ti_armv7_omap.h>
 #undef CONFIG_SYS_MONITOR_LEN
 
-#define CONFIG_ENV_SIZE			(16 * 1024)
-
 #define V_OSCK				24000000  /* Clock output from T2 */
 #define V_SCLK				(V_OSCK)
 
-#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
-#define CONFIG_ENV_OFFSET		(768 * 1024)
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x80200000\0" \
 	"fdtaddr=0x81200000\0" \
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
index e15bab2..2469066 100644
--- a/include/configs/colibri-imx8x.h
+++ b/include/configs/colibri-imx8x.h
@@ -15,7 +15,6 @@
 
 #undef CONFIG_BOOTM_NETBSD
 
-#define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define USDHC1_BASE_ADDR		0x5b010000
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index f1b0374..f2df66e 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -88,9 +88,7 @@
 #define CONFIG_SYS_LOAD_ADDR	ATMEL_BASE_CS6
 
 /* bootstrap + u-boot + env in nandflash */
-#define CONFIG_ENV_OFFSET		0x100000
 #define CONFIG_ENV_OFFSET_REDUND	0x180000
-#define CONFIG_ENV_SIZE			SZ_128K
 
 #define CONFIG_BOOTCOMMAND						\
 	"nand read 0x70000000 0x200000 0x300000;"			\
diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h
index 2eb658d..baf1a73b 100644
--- a/include/configs/devkit8000.h
+++ b/include/configs/devkit8000.h
@@ -37,8 +37,6 @@
 #define CONFIG_REVISION_TAG		1
 
 /* Size of malloc() pool */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-						/* Sector */
 #undef CONFIG_SYS_MALLOC_LEN
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
 
@@ -144,10 +142,6 @@
 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
 					0x01000000) /* 16MB */
 
-/* NAND and environment organization  */
-
-#define CONFIG_ENV_OFFSET		0x260000
-
 /* SRAM config */
 #define CONFIG_SYS_SRAM_START              0x40200000
 #define CONFIG_SYS_SRAM_SIZE               0x10000
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index aec70ee..9c8141d 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -21,8 +21,6 @@
 #ifndef CONFIG_QSPI_BOOT
 /* MMC ENV related defines */
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
-#define CONFIG_ENV_SIZE			(128 << 10)
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 #endif
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index b86b542..24aaae5 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -52,8 +52,6 @@
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
 #define CONFIG_ENV_OFFSET	0x3DE000
-#define CONFIG_ENV_SIZE		(132 << 10)
-#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h
index 02bf4d1..482e471 100644
--- a/include/configs/gardena-smart-gateway-at91sam.h
+++ b/include/configs/gardena-smart-gateway-at91sam.h
@@ -43,12 +43,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
 
-/* environment organization */
-#define CONFIG_ENV_UBI_PART		"ubi"
-#define CONFIG_ENV_UBI_VOLUME		"env"
-#define CONFIG_ENV_UBI_VOLUME_REDUND	"env_r"
-#define CONFIG_ENV_SIZE			(64 << 10)
-
 /* SPL */
 #define CONFIG_SPL_MAX_SIZE		0x7000
 #define CONFIG_SPL_STACK		0x308000
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h
index e4fa2df..16e4136 100644
--- a/include/configs/imx8mq_evk.h
+++ b/include/configs/imx8mq_evk.h
@@ -216,7 +216,6 @@
 #define CONFIG_IMX_BOOTAUX
 
 #define CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 
 #define CONFIG_SYS_FSL_USDHC_NUM	2
diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h
index d06ed61..8fdf677 100644
--- a/include/configs/imx8qm_mek.h
+++ b/include/configs/imx8qm_mek.h
@@ -47,7 +47,6 @@
 #undef CONFIG_CMD_CRC32
 #undef CONFIG_BOOTM_NETBSD
 
-#define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 #define USDHC1_BASE_ADDR                0x5B010000
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
index a8591c9..c1f1934 100644
--- a/include/configs/imx8qxp_mek.h
+++ b/include/configs/imx8qxp_mek.h
@@ -46,7 +46,6 @@
 #undef CONFIG_CMD_CRC32
 #undef CONFIG_BOOTM_NETBSD
 
-#define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 #define USDHC1_BASE_ADDR                0x5B010000
diff --git a/include/configs/kc1.h b/include/configs/kc1.h
index 59814b5..e3a219c 100644
--- a/include/configs/kc1.h
+++ b/include/configs/kc1.h
@@ -103,8 +103,6 @@
  * Environment
  */
 
-#define CONFIG_ENV_SIZE		(128 * 1024)
-
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h
index d2ebf92..dbae276 100644
--- a/include/configs/kp_imx6q_tpc.h
+++ b/include/configs/kp_imx6q_tpc.h
@@ -39,7 +39,6 @@
 #define CONFIG_SYS_I2C_SPEED		100000
 
 /* MMC Configs */
-#define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR	0
 #define CONFIG_SYS_FSL_USDHC_NUM	2
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h
index 12e6437..77aa22b 100644
--- a/include/configs/ls1012afrwy.h
+++ b/include/configs/ls1012afrwy.h
@@ -41,7 +41,6 @@
 
 /*  MMC  */
 #ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h
index d3d787f..896d7a3 100644
--- a/include/configs/ls1028a_common.h
+++ b/include/configs/ls1028a_common.h
@@ -164,7 +164,6 @@
 
 /*  MMC  */
 #ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 
@@ -178,12 +177,6 @@
 
 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 
-/*  MMC  */
-#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
-#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#endif
-
 /* I2C bus multiplexer */
 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 #define I2C_MUX_CH_DEFAULT              0x8
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 453dd32..d9f4bdc 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -50,7 +50,6 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE			(128 << 10)
 #define CONFIG_UBI_SIZE			(512 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \
 					(128 << 10))
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index f0c8c99..a2a6be7 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -40,7 +40,6 @@
 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 #define CONFIG_SYS_ENV_SECT_SIZE        SZ_128K
-#define CONFIG_ENV_OFFSET               0x260000
 #define CONFIG_ENV_ADDR                 0x260000
 #define CONFIG_ENV_OVERWRITE
 /* NAND: SPL falcon mode configs */
@@ -59,9 +58,6 @@
 
 /* TWL4030 LED Support */
 
-/* Environment */
-#define CONFIG_ENV_SIZE                 SZ_128K
-
 #define CONFIG_PREBOOT                  "usb start"
 
 #define MEM_LAYOUT_ENV_SETTINGS \
diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h
index ef69b24..9e2b752 100644
--- a/include/configs/omap3_cairo.h
+++ b/include/configs/omap3_cairo.h
@@ -160,11 +160,7 @@
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
 
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
-
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_ADDR			0x260000
 
 /* Defines for SPL */
diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 5b9d8a5..4ab172c 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -44,7 +44,6 @@
 #define CONFIG_SYS_NAND_ECCBYTES        3
 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 #define CONFIG_SYS_ENV_SECT_SIZE        SZ_128K
-#define CONFIG_ENV_OFFSET               0x260000
 #define CONFIG_ENV_ADDR                 0x260000
 #define CONFIG_ENV_OVERWRITE
 /* NAND: SPL falcon mode configs */
@@ -54,8 +53,6 @@
 #endif /* CONFIG_NAND */
 
 /* Environment */
-#define CONFIG_ENV_SIZE                 SZ_128K
-
 #define CONFIG_PREBOOT                  "usb start"
 
 #define MEM_LAYOUT_ENV_SETTINGS \
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 23d12c6..4ad7dc1 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -96,24 +96,4 @@
 #define CONFIG_SYS_NAND_ECCBYTES	14
 #define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
 
-/* UBI configuration */
-#define CONFIG_SPL_UBI			1
-#define CONFIG_SPL_UBI_MAX_VOL_LEBS	256
-#define CONFIG_SPL_UBI_MAX_PEB_SIZE	(256*1024)
-#define CONFIG_SPL_UBI_MAX_PEBS		4096
-#define CONFIG_SPL_UBI_VOL_IDS		8
-#define CONFIG_SPL_UBI_LOAD_MONITOR_ID	0
-#define CONFIG_SPL_UBI_LOAD_KERNEL_ID	3
-#define CONFIG_SPL_UBI_LOAD_ARGS_ID	4
-#define CONFIG_SPL_UBI_PEB_OFFSET	4
-#define CONFIG_SPL_UBI_VID_OFFSET	512
-#define CONFIG_SPL_UBI_LEB_START	2048
-#define CONFIG_SPL_UBI_INFO_ADDR	0x88080000
-
-/* environment organization */
-#define CONFIG_ENV_UBI_PART		"UBI"
-#define CONFIG_ENV_UBI_VOLUME		"config"
-#define CONFIG_ENV_UBI_VOLUME_REDUND	"config_r"
-#define CONFIG_ENV_SIZE			(32*1024)
-
 #endif /* __IGEP00X0_H */
diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index e318a9f..6b7104d 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -194,10 +194,7 @@
 /* Monitor at start of flash */
 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
 
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_ADDR			0x260000
 
 /* Defines for SPL */
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index ea941db..38a10e2 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -19,7 +19,6 @@
 
 /* override size of malloc() pool */
 #undef CONFIG_SYS_MALLOC_LEN
-#define CONFIG_ENV_SIZE		(128 << 10)	/* 128 KiB sector */
 /* Shift 128 << 15 provides 4 MiB heap to support UBI commands.
  * Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */
 #define CONFIG_SYS_MALLOC_LEN	(CONFIG_ENV_SIZE + (128 << 15))
diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h
index 82c66c4..98f243f 100644
--- a/include/configs/omap3_pandora.h
+++ b/include/configs/omap3_pandora.h
@@ -15,8 +15,6 @@
 
 #define CONFIG_REVISION_TAG		1
 
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-
 #define CONFIG_SYS_DEVICE_NULLDEV	1
 
 /*
@@ -63,7 +61,6 @@
 
 
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_ADDR			0x260000
 
 #endif				/* __CONFIG_H */
diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 0a02ecd..4dc22a7 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -23,8 +23,6 @@
 
 #define CONFIG_REVISION_TAG		1
 
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-
 /*
  * Hardware drivers
  */
@@ -132,7 +130,6 @@
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_ADDR			0x260000
 
 #endif				/* __CONFIG_H */
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 0d8f945..27e4732 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -32,8 +32,6 @@
 
 /* MMC ENV related defines */
 #define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
-#define CONFIG_ENV_SIZE			(128 << 10)
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
 
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 8cde12e..153e567 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -21,7 +21,6 @@
 
 #include <configs/ti_am335x_common.h>
 
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 #define CONFIG_MACH_TYPE		MACH_TYPE_PCM051
 
 /* set to negative value for no autoboot */
diff --git a/include/configs/pepper.h b/include/configs/pepper.h
index ef662d7..662fce3 100644
--- a/include/configs/pepper.h
+++ b/include/configs/pepper.h
@@ -17,8 +17,6 @@
 /* Mach type */
 #define CONFIG_MACH_TYPE		MACH_TYPE_PEPPER
 
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
-
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	DEFAULT_LINUX_BOOT_ENV \
 	"bootdir=/boot\0" \
diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h
index 5f6979c..90846c4 100644
--- a/include/configs/sama5d27_som1_ek.h
+++ b/include/configs/sama5d27_som1_ek.h
@@ -43,13 +43,6 @@
 #endif
 
 #ifdef CONFIG_QSPI_BOOT
-#define CONFIG_ENV_OFFSET		0xb0000
-#define CONFIG_ENV_SIZE			0x10000
-#define CONFIG_ENV_SECT_SIZE		0x10000
-#define CONFIG_BOOTCOMMAND		"sf probe 0; "				\
-					"sf read 0x21000000 0xc0000 0x20000; "	\
-					"sf read 0x22000000 0xe0000 0x400000; "	\
-					"bootz 0x22000000 - 0x21000000"
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTARGS \
 	"console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h
index e522740..3dea359 100644
--- a/include/configs/sama5d2_xplained.h
+++ b/include/configs/sama5d2_xplained.h
@@ -46,6 +46,17 @@
 
 #endif
 
+#ifdef CONFIG_QSPI_BOOT
+#undef CONFIG_ENV_SPI_BUS
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_ENV_SPI_BUS	1
+#define CONFIG_BOOTCOMMAND	"sf probe 1:0; "			\
+				"sf read 0x21000000 0x180000 0x80000; "	\
+				"sf read 0x22000000 0x200000 0x600000; "\
+				"bootz 0x22000000 - 0x21000000"
+
+#endif
+
 /* SPL */
 #define CONFIG_SPL_MAX_SIZE		0x10000
 #define CONFIG_SPL_BSS_START_ADDR	0x20000000
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index 1281955..c07814f 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -18,7 +18,6 @@
 #define CONFIG_DMA_COHERENT
 #define CONFIG_DMA_COHERENT_SIZE	(1 << 20)
 
-#define CONFIG_ENV_SIZE			(0x2000)
 #define CONFIG_SYS_MALLOC_LEN		(16 * 1024 * 1024)
 #ifdef CONFIG_SIEMENS_MACH_TYPE
 #define CONFIG_MACH_TYPE		CONFIG_SIEMENS_MACH_TYPE
@@ -461,7 +460,6 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND
 							   devices */
 #if !defined(CONFIG_SPI_BOOT)
-#define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
 #endif
 #endif
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 776d7d7..c1a43a5 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -144,10 +144,8 @@
 /*
  * The NAND Flash partitions:
  */
-#define CONFIG_ENV_OFFSET		(0x100000)
 #define CONFIG_ENV_OFFSET_REDUND	(0x180000)
 #define CONFIG_ENV_RANGE		(SZ_512K)
-#define CONFIG_ENV_SIZE			(SZ_128K)
 
 /*
  * Predefined environment variables.
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index f212d15..7c2c5fb 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -111,8 +111,6 @@
 #define CONFIG_BOOTP_BOOTFILESIZE
 
 /* Environment settings */
-#define CONFIG_ENV_OFFSET		(512 << 10)
-#define CONFIG_ENV_SIZE			(256 << 10)
 #define CONFIG_ENV_OVERWRITE
 
 /* Console settings */
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index dac2e65..ffcfdca 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -74,8 +74,6 @@
 #define CONFIG_BOOTP_BOOTFILESIZE
 
 /* Environment settings */
-#define CONFIG_ENV_OFFSET		(512 << 10)
-#define CONFIG_ENV_SIZE			(256 << 10)
 #define CONFIG_ENV_OVERWRITE
 
 #define	CONFIG_EXTRA_ENV_SETTINGS	\
diff --git a/include/configs/sniper.h b/include/configs/sniper.h
index 540ea77..0e2fcc3 100644
--- a/include/configs/sniper.h
+++ b/include/configs/sniper.h
@@ -96,8 +96,6 @@
  * Environment
  */
 
-#define CONFIG_ENV_SIZE		(128 * 1024)
-
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h
index 1d385e0..0ce2fcb 100644
--- a/include/configs/stm32mp1.h
+++ b/include/configs/stm32mp1.h
@@ -38,10 +38,6 @@
  */
 #define CONFIG_SYS_LOAD_ADDR			STM32_DDR_BASE
 
-#if defined(CONFIG_ENV_IS_IN_UBI)
-#define CONFIG_ENV_UBI_VOLUME_REDUND		"uboot_config_r"
-#endif
-
 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
 #define	CONFIG_ENV_SECT_SIZE			SZ_256K
 #define	CONFIG_ENV_OFFSET			0x00280000
diff --git a/include/configs/tam3517-common.h b/include/configs/tam3517-common.h
index e7bab72..121de2b 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -28,7 +28,6 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10) + \
 					2 * 1024 * 1024)
 /*
diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h
index a95cbed..c34e785 100644
--- a/include/configs/tao3530.h
+++ b/include/configs/tao3530.h
@@ -32,7 +32,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(4 << 20)
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
 
 /*
  * Hardware drivers
@@ -170,7 +169,6 @@
 #define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
 
 #define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)
-#define CONFIG_ENV_OFFSET		0x260000
 #define CONFIG_ENV_ADDR			CONFIG_ENV_OFFSET
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index dbb01af..36a41ff 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -110,9 +110,7 @@
 #define CONFIG_SYS_LOAD_ADDR			0x22000000
 
 /* bootstrap in spi flash , u-boot + env + linux in nandflash */
-#define CONFIG_ENV_OFFSET		0x100000
 #define CONFIG_ENV_OFFSET_REDUND	0x180000
-#define CONFIG_ENV_SIZE		(SZ_128K)	/* 1 sector = 128 kB */
 
 #ifndef CONFIG_SPL_BUILD
 #if defined(CONFIG_BOARD_AXM)
diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h
index 512386e..90b424f 100644
--- a/include/configs/ti814x_evm.h
+++ b/include/configs/ti814x_evm.h
@@ -18,7 +18,6 @@
 
 #include <asm/arch/omap.h>
 
-#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */
 #define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
 #define CONFIG_MACH_TYPE		MACH_TYPE_TI8148EVM
 
diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h
index fc59aba..1e31622 100644
--- a/include/configs/ti_omap4_common.h
+++ b/include/configs/ti_omap4_common.h
@@ -24,11 +24,6 @@
 #define CONFIG_SYS_TIMERBASE		GPT2_BASE
 
 /*
- * Total Size Environment - 128k
- */
-#define CONFIG_ENV_SIZE			(128 << 10)
-
-/*
  * For the DDR timing information we can either dynamically determine
  * the timings to use or use pre-determined timings (based on using the
  * dynamic method.  Default to the static timing infomation.
diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h
index 683375a..2106f4e 100644
--- a/include/configs/tricorder.h
+++ b/include/configs/tricorder.h
@@ -78,9 +78,7 @@
 
 /* environment placement (for NAND), is different for FLASHCARD but does not
  * harm there */
-#define CONFIG_ENV_OFFSET		0x120000    /* env start */
 #define CONFIG_ENV_OFFSET_REDUND	0x2A0000    /* redundant env start */
-#define CONFIG_ENV_SIZE			(16 << 10)  /* use 16KiB for env */
 #define CONFIG_ENV_RANGE		(384 << 10) /* allow badblocks in env */
 
 /* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
index fa38274..ee72354 100644
--- a/include/configs/usb_a9263.h
+++ b/include/configs/usb_a9263.h
@@ -79,9 +79,6 @@
 #define CONFIG_SYS_MEMTEST_END			0x23e00000
 
 /* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_OFFSET	0x2000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
 #define CONFIG_BOOTCOMMAND	"nboot 21000000 0"
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h
index e3973d0..81d30a6 100644
--- a/include/configs/wb50n.h
+++ b/include/configs/wb50n.h
@@ -74,9 +74,7 @@
     "autostart=no\0"
 
 /* bootstrap + u-boot + env in nandflash */
-#define CONFIG_ENV_OFFSET           0xA0000
 #define CONFIG_ENV_OFFSET_REDUND    0xC0000
-#define CONFIG_ENV_SIZE             0x20000
 #define CONFIG_BOOTCOMMAND \
     "nand read 0x22000000 0x000e0000 0x500000; " \
     "bootm"
diff --git a/include/efi_api.h b/include/efi_api.h
index a36ecec..d4f32db 100644
--- a/include/efi_api.h
+++ b/include/efi_api.h
@@ -23,8 +23,8 @@
 #include <asm/setjmp.h>
 #endif
 
-/* UEFI spec version 2.7 */
-#define EFI_SPECIFICATION_VERSION (2 << 16 | 70)
+/* UEFI spec version 2.8 */
+#define EFI_SPECIFICATION_VERSION (2 << 16 | 80)
 
 /* Types and defines for EFI CreateEvent */
 enum efi_timer_delay {
diff --git a/include/efi_loader.h b/include/efi_loader.h
index b07155c..db4763f 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -325,10 +325,16 @@
 
 /* Initialize efi execution environment */
 efi_status_t efi_init_obj_list(void);
+/* Initialize variable services */
+efi_status_t efi_init_variables(void);
+/* Notify ExitBootServices() is called */
+void efi_variables_boot_exit_notify(void);
 /* Called by bootefi to initialize root node */
 efi_status_t efi_root_node_register(void);
 /* Called by bootefi to initialize runtime */
 efi_status_t efi_initialize_system_table(void);
+/* efi_runtime_detach() - detach unimplemented runtime functions */
+void efi_runtime_detach(void);
 /* Called by bootefi to make console interface available */
 efi_status_t efi_console_register(void);
 /* Called by bootefi to make all disk storage accessible as EFI objects */
@@ -618,6 +624,11 @@
 				     const efi_guid_t *vendor, u32 attributes,
 				     efi_uintn_t data_size, const void *data);
 
+efi_status_t EFIAPI efi_query_variable_info(
+			u32 attributes, u64 *maximum_variable_storage_size,
+			u64 *remaining_variable_storage_size,
+			u64 *maximum_variable_size);
+
 /*
  * See section 3.1.3 in the v2.7 UEFI spec for more details on
  * the layout of EFI_LOAD_OPTION.  In short it is:
diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
index 8dbd524..7d7e946 100644
--- a/include/fsl_esdhc.h
+++ b/include/fsl_esdhc.h
@@ -9,7 +9,6 @@
 #ifndef  __FSL_ESDHC_H__
 #define	__FSL_ESDHC_H__
 
-#include <linux/bitops.h>
 #include <linux/errno.h>
 #include <asm/byteorder.h>
 
@@ -25,22 +24,14 @@
 #define SYSCTL_INITA		0x08000000
 #define SYSCTL_TIMEOUT_MASK	0x000f0000
 #define SYSCTL_CLOCK_MASK	0x0000fff0
-#if !defined(CONFIG_FSL_USDHC)
 #define SYSCTL_CKEN		0x00000008
 #define SYSCTL_PEREN		0x00000004
 #define SYSCTL_HCKEN		0x00000002
 #define SYSCTL_IPGEN		0x00000001
-#endif
 #define SYSCTL_RSTA		0x01000000
 #define SYSCTL_RSTC		0x02000000
 #define SYSCTL_RSTD		0x04000000
 
-#define VENDORSPEC_CKEN		0x00004000
-#define VENDORSPEC_PEREN	0x00002000
-#define VENDORSPEC_HCKEN	0x00001000
-#define VENDORSPEC_IPGEN	0x00000800
-#define VENDORSPEC_INIT		0x20007809
-
 #define IRQSTAT			0x0002e030
 #define IRQSTAT_DMAE		(0x10000000)
 #define IRQSTAT_AC12E		(0x01000000)
@@ -172,54 +163,6 @@
 #define ESDHC_HOSTCAPBLT_DMAS	0x00400000
 #define ESDHC_HOSTCAPBLT_HSS	0x00200000
 
-#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
-
-/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
-#define	MIX_CTRL_DDREN		BIT(3)
-#define MIX_CTRL_DTDSEL_READ	BIT(4)
-#define	MIX_CTRL_AC23EN		BIT(7)
-#define	MIX_CTRL_EXE_TUNE	BIT(22)
-#define	MIX_CTRL_SMPCLK_SEL	BIT(23)
-#define	MIX_CTRL_AUTO_TUNE_EN	BIT(24)
-#define	MIX_CTRL_FBCLK_SEL	BIT(25)
-#define	MIX_CTRL_HS400_EN	BIT(26)
-#define	MIX_CTRL_HS400_ES	BIT(27)
-/* Bits 3 and 6 are not SDHCI standard definitions */
-#define	MIX_CTRL_SDHCI_MASK	0xb7
-/* Tuning bits */
-#define	MIX_CTRL_TUNING_MASK	0x03c00000
-
-/* strobe dll register */
-#define ESDHC_STROBE_DLL_CTRL		0x70
-#define ESDHC_STROBE_DLL_CTRL_ENABLE	BIT(0)
-#define ESDHC_STROBE_DLL_CTRL_RESET	BIT(1)
-#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT	0x7
-#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3
-
-#define ESDHC_STROBE_DLL_STATUS		0x74
-#define ESDHC_STROBE_DLL_STS_REF_LOCK	BIT(1)
-#define ESDHC_STROBE_DLL_STS_SLV_LOCK	0x1
-#define ESDHC_STROBE_DLL_CLK_FREQ	100000000
-
-#define ESDHC_STD_TUNING_EN             BIT(24)
-/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
-#define ESDHC_TUNING_START_TAP_DEFAULT	0x1
-#define ESDHC_TUNING_START_TAP_MASK	0xff
-#define ESDHC_TUNING_STEP_MASK		0x00070000
-#define ESDHC_TUNING_STEP_SHIFT		16
-
-#define	ESDHC_FLAG_MULTIBLK_NO_INT	BIT(1)
-#define	ESDHC_FLAG_ENGCM07207		BIT(2)
-#define	ESDHC_FLAG_USDHC		BIT(3)
-#define	ESDHC_FLAG_MAN_TUNING		BIT(4)
-#define	ESDHC_FLAG_STD_TUNING		BIT(5)
-#define	ESDHC_FLAG_HAVE_CAP1		BIT(6)
-#define	ESDHC_FLAG_ERR004536		BIT(7)
-#define	ESDHC_FLAG_HS200		BIT(8)
-#define	ESDHC_FLAG_HS400		BIT(9)
-#define	ESDHC_FLAG_ERR010450		BIT(10)
-#define	ESDHC_FLAG_HS400_ES		BIT(11)
-
 struct fsl_esdhc_cfg {
 	phys_addr_t esdhc_base;
 	u32	sdhc_clk;
diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h
new file mode 100644
index 0000000..33c6d52
--- /dev/null
+++ b/include/fsl_esdhc_imx.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * FSL SD/MMC Defines
+ *-------------------------------------------------------------------
+ *
+ * Copyright 2019 NXP
+ * Yangbo Lu <yangbo.lu@nxp.com>
+ *
+ * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
+ */
+
+#ifndef __FSL_ESDHC_IMX_H__
+#define __FSL_ESDHC_IMX_H__
+
+#include <linux/bitops.h>
+#include <linux/errno.h>
+#include <asm/byteorder.h>
+
+/* needed for the mmc_cfg definition */
+#include <mmc.h>
+
+/* FSL eSDHC-specific constants */
+#define SYSCTL			0x0002e02c
+#define SYSCTL_INITA		0x08000000
+#define SYSCTL_TIMEOUT_MASK	0x000f0000
+#define SYSCTL_CLOCK_MASK	0x0000fff0
+#if !defined(CONFIG_FSL_USDHC)
+#define SYSCTL_CKEN		0x00000008
+#define SYSCTL_PEREN		0x00000004
+#define SYSCTL_HCKEN		0x00000002
+#define SYSCTL_IPGEN		0x00000001
+#endif
+#define SYSCTL_RSTA		0x01000000
+#define SYSCTL_RSTC		0x02000000
+#define SYSCTL_RSTD		0x04000000
+
+#define VENDORSPEC_CKEN		0x00004000
+#define VENDORSPEC_PEREN	0x00002000
+#define VENDORSPEC_HCKEN	0x00001000
+#define VENDORSPEC_IPGEN	0x00000800
+#define VENDORSPEC_INIT		0x20007809
+
+#define IRQSTAT			0x0002e030
+#define IRQSTAT_DMAE		(0x10000000)
+#define IRQSTAT_AC12E		(0x01000000)
+#define IRQSTAT_DEBE		(0x00400000)
+#define IRQSTAT_DCE		(0x00200000)
+#define IRQSTAT_DTOE		(0x00100000)
+#define IRQSTAT_CIE		(0x00080000)
+#define IRQSTAT_CEBE		(0x00040000)
+#define IRQSTAT_CCE		(0x00020000)
+#define IRQSTAT_CTOE		(0x00010000)
+#define IRQSTAT_CINT		(0x00000100)
+#define IRQSTAT_CRM		(0x00000080)
+#define IRQSTAT_CINS		(0x00000040)
+#define IRQSTAT_BRR		(0x00000020)
+#define IRQSTAT_BWR		(0x00000010)
+#define IRQSTAT_DINT		(0x00000008)
+#define IRQSTAT_BGE		(0x00000004)
+#define IRQSTAT_TC		(0x00000002)
+#define IRQSTAT_CC		(0x00000001)
+
+#define CMD_ERR		(IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
+#define DATA_ERR	(IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
+				IRQSTAT_DMAE)
+#define DATA_COMPLETE	(IRQSTAT_TC | IRQSTAT_DINT)
+
+#define IRQSTATEN		0x0002e034
+#define IRQSTATEN_DMAE		(0x10000000)
+#define IRQSTATEN_AC12E		(0x01000000)
+#define IRQSTATEN_DEBE		(0x00400000)
+#define IRQSTATEN_DCE		(0x00200000)
+#define IRQSTATEN_DTOE		(0x00100000)
+#define IRQSTATEN_CIE		(0x00080000)
+#define IRQSTATEN_CEBE		(0x00040000)
+#define IRQSTATEN_CCE		(0x00020000)
+#define IRQSTATEN_CTOE		(0x00010000)
+#define IRQSTATEN_CINT		(0x00000100)
+#define IRQSTATEN_CRM		(0x00000080)
+#define IRQSTATEN_CINS		(0x00000040)
+#define IRQSTATEN_BRR		(0x00000020)
+#define IRQSTATEN_BWR		(0x00000010)
+#define IRQSTATEN_DINT		(0x00000008)
+#define IRQSTATEN_BGE		(0x00000004)
+#define IRQSTATEN_TC		(0x00000002)
+#define IRQSTATEN_CC		(0x00000001)
+
+#define ESDHCCTL		0x0002e40c
+#define ESDHCCTL_PCS		(0x00080000)
+
+#define PRSSTAT			0x0002e024
+#define PRSSTAT_DAT0		(0x01000000)
+#define PRSSTAT_CLSL		(0x00800000)
+#define PRSSTAT_WPSPL		(0x00080000)
+#define PRSSTAT_CDPL		(0x00040000)
+#define PRSSTAT_CINS		(0x00010000)
+#define PRSSTAT_BREN		(0x00000800)
+#define PRSSTAT_BWEN		(0x00000400)
+#define PRSSTAT_SDSTB		(0X00000008)
+#define PRSSTAT_DLA		(0x00000004)
+#define PRSSTAT_CICHB		(0x00000002)
+#define PRSSTAT_CIDHB		(0x00000001)
+
+#define PROCTL			0x0002e028
+#define PROCTL_INIT		0x00000020
+#define PROCTL_DTW_4		0x00000002
+#define PROCTL_DTW_8		0x00000004
+#define PROCTL_D3CD		0x00000008
+
+#define CMDARG			0x0002e008
+
+#define XFERTYP			0x0002e00c
+#define XFERTYP_CMD(x)		((x & 0x3f) << 24)
+#define XFERTYP_CMDTYP_NORMAL	0x0
+#define XFERTYP_CMDTYP_SUSPEND	0x00400000
+#define XFERTYP_CMDTYP_RESUME	0x00800000
+#define XFERTYP_CMDTYP_ABORT	0x00c00000
+#define XFERTYP_DPSEL		0x00200000
+#define XFERTYP_CICEN		0x00100000
+#define XFERTYP_CCCEN		0x00080000
+#define XFERTYP_RSPTYP_NONE	0
+#define XFERTYP_RSPTYP_136	0x00010000
+#define XFERTYP_RSPTYP_48	0x00020000
+#define XFERTYP_RSPTYP_48_BUSY	0x00030000
+#define XFERTYP_MSBSEL		0x00000020
+#define XFERTYP_DTDSEL		0x00000010
+#define XFERTYP_DDREN		0x00000008
+#define XFERTYP_AC12EN		0x00000004
+#define XFERTYP_BCEN		0x00000002
+#define XFERTYP_DMAEN		0x00000001
+
+#define CINS_TIMEOUT		1000
+#define PIO_TIMEOUT		500
+
+#define DSADDR		0x2e004
+
+#define CMDRSP0		0x2e010
+#define CMDRSP1		0x2e014
+#define CMDRSP2		0x2e018
+#define CMDRSP3		0x2e01c
+
+#define DATPORT		0x2e020
+
+#define WML		0x2e044
+#define WML_WRITE	0x00010000
+#ifdef CONFIG_FSL_SDHC_V2_3
+#define WML_RD_WML_MAX		0x80
+#define WML_WR_WML_MAX		0x80
+#define WML_RD_WML_MAX_VAL	0x0
+#define WML_WR_WML_MAX_VAL	0x0
+#define WML_RD_WML_MASK		0x7f
+#define WML_WR_WML_MASK		0x7f0000
+#else
+#define WML_RD_WML_MAX		0x10
+#define WML_WR_WML_MAX		0x80
+#define WML_RD_WML_MAX_VAL	0x10
+#define WML_WR_WML_MAX_VAL	0x80
+#define WML_RD_WML_MASK	0xff
+#define WML_WR_WML_MASK	0xff0000
+#endif
+
+#define BLKATTR		0x2e004
+#define BLKATTR_CNT(x)	((x & 0xffff) << 16)
+#define BLKATTR_SIZE(x)	(x & 0x1fff)
+#define MAX_BLK_CNT	0x7fff	/* so malloc will have enough room with 32M */
+
+#define ESDHC_HOSTCAPBLT_VS18	0x04000000
+#define ESDHC_HOSTCAPBLT_VS30	0x02000000
+#define ESDHC_HOSTCAPBLT_VS33	0x01000000
+#define ESDHC_HOSTCAPBLT_SRS	0x00800000
+#define ESDHC_HOSTCAPBLT_DMAS	0x00400000
+#define ESDHC_HOSTCAPBLT_HSS	0x00200000
+
+#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
+
+/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
+#define	MIX_CTRL_DDREN		BIT(3)
+#define MIX_CTRL_DTDSEL_READ	BIT(4)
+#define	MIX_CTRL_AC23EN		BIT(7)
+#define	MIX_CTRL_EXE_TUNE	BIT(22)
+#define	MIX_CTRL_SMPCLK_SEL	BIT(23)
+#define	MIX_CTRL_AUTO_TUNE_EN	BIT(24)
+#define	MIX_CTRL_FBCLK_SEL	BIT(25)
+#define	MIX_CTRL_HS400_EN	BIT(26)
+#define	MIX_CTRL_HS400_ES	BIT(27)
+/* Bits 3 and 6 are not SDHCI standard definitions */
+#define	MIX_CTRL_SDHCI_MASK	0xb7
+/* Tuning bits */
+#define	MIX_CTRL_TUNING_MASK	0x03c00000
+
+/* strobe dll register */
+#define ESDHC_STROBE_DLL_CTRL		0x70
+#define ESDHC_STROBE_DLL_CTRL_ENABLE	BIT(0)
+#define ESDHC_STROBE_DLL_CTRL_RESET	BIT(1)
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT	0x7
+#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT	3
+
+#define ESDHC_STROBE_DLL_STATUS		0x74
+#define ESDHC_STROBE_DLL_STS_REF_LOCK	BIT(1)
+#define ESDHC_STROBE_DLL_STS_SLV_LOCK	0x1
+#define ESDHC_STROBE_DLL_CLK_FREQ	100000000
+
+#define ESDHC_STD_TUNING_EN             BIT(24)
+/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
+#define ESDHC_TUNING_START_TAP_DEFAULT	0x1
+#define ESDHC_TUNING_START_TAP_MASK	0xff
+#define ESDHC_TUNING_STEP_MASK		0x00070000
+#define ESDHC_TUNING_STEP_SHIFT		16
+
+#define	ESDHC_FLAG_MULTIBLK_NO_INT	BIT(1)
+#define	ESDHC_FLAG_ENGCM07207		BIT(2)
+#define	ESDHC_FLAG_USDHC		BIT(3)
+#define	ESDHC_FLAG_MAN_TUNING		BIT(4)
+#define	ESDHC_FLAG_STD_TUNING		BIT(5)
+#define	ESDHC_FLAG_HAVE_CAP1		BIT(6)
+#define	ESDHC_FLAG_ERR004536		BIT(7)
+#define	ESDHC_FLAG_HS200		BIT(8)
+#define	ESDHC_FLAG_HS400		BIT(9)
+#define	ESDHC_FLAG_ERR010450		BIT(10)
+#define	ESDHC_FLAG_HS400_ES		BIT(11)
+
+struct fsl_esdhc_cfg {
+	phys_addr_t esdhc_base;
+	u32	sdhc_clk;
+	u8	max_bus_width;
+	int	wp_enable;
+	int	vs18_enable; /* Use 1.8V if set to 1 */
+	struct mmc_config cfg;
+};
+
+/* Select the correct accessors depending on endianess */
+#if defined CONFIG_SYS_FSL_ESDHC_LE
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
+#define esdhc_read32            in_be32
+#define esdhc_write32           out_be32
+#define esdhc_clrsetbits32      clrsetbits_be32
+#define esdhc_clrbits32         clrbits_be32
+#define esdhc_setbits32         setbits_be32
+#elif __BYTE_ORDER == __LITTLE_ENDIAN
+#define esdhc_read32		in_le32
+#define esdhc_write32		out_le32
+#define esdhc_clrsetbits32	clrsetbits_le32
+#define esdhc_clrbits32		clrbits_le32
+#define esdhc_setbits32		setbits_le32
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#define esdhc_read32		in_be32
+#define esdhc_write32		out_be32
+#define esdhc_clrsetbits32	clrsetbits_be32
+#define esdhc_clrbits32		clrbits_be32
+#define esdhc_setbits32		setbits_be32
+#else
+#error "Endianess is not defined: please fix to continue"
+#endif
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+int fsl_esdhc_mmc_init(bd_t *bis);
+int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
+void fdt_fixup_esdhc(void *blob, bd_t *bd);
+#else
+static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
+static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
+#endif /* CONFIG_FSL_ESDHC_IMX */
+void __noreturn mmc_boot(void);
+void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
+
+#endif  /* __FSL_ESDHC_IMX_H__ */
diff --git a/include/ubispl.h b/include/ubispl.h
index 1e5da94..ecfe0c9 100644
--- a/include/ubispl.h
+++ b/include/ubispl.h
@@ -5,6 +5,8 @@
 #ifndef __UBOOT_UBISPL_H
 #define __UBOOT_UBISPL_H
 
+#define UBI_VOL_NAME_MAX	127
+
 /*
  * The following CONFIG options are relevant for UBISPL
  *
@@ -74,6 +76,10 @@
  */
 struct ubispl_load {
 	int		vol_id;
+#ifdef CONFIG_SPL_UBI_LOAD_BY_VOLNAME
+	u32		name_len;
+	char		name[UBI_VOL_NAME_MAX + 1];
+#endif
 	void		*load_addr;
 };
 
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index cd5436c..a7f2c68 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -101,4 +101,10 @@
 	  RFC 4646 format, e.g. "en-US;de-DE". The first language code is used
 	  to initialize the PlatformLang variable.
 
+config EFI_HAVE_RUNTIME_RESET
+	# bool "Reset runtime service is available"
+	bool
+	default y
+	depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || SYSRESET_X86
+
 endif
diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c
index d104cc6..c2f8980 100644
--- a/lib/efi_loader/efi_boottime.c
+++ b/lib/efi_loader/efi_boottime.c
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- *  EFI application boot time services
+ * EFI application boot time services
  *
- *  Copyright (c) 2016 Alexander Graf
+ * Copyright (c) 2016 Alexander Graf
  */
 
 #include <common.h>
@@ -1968,10 +1968,14 @@
 	/* Make sure that notification functions are not called anymore */
 	efi_tpl = TPL_HIGH_LEVEL;
 
-	/* TODO: Should persist EFI variables here */
+	/* Notify variable services */
+	efi_variables_boot_exit_notify();
 
 	board_quiesce_devices();
 
+	/* Patch out unsupported runtime function */
+	efi_runtime_detach();
+
 	/* Fix up caches for EFI payloads if necessary */
 	efi_exit_caches();
 
@@ -3234,7 +3238,7 @@
 	if (r != EFI_SUCCESS)
 		return r;
 
-	/*  Context Override */
+	/* Context Override */
 	if (driver_image_handle) {
 		for (; *driver_image_handle; ++driver_image_handle) {
 			for (i = 0; i < count; ++i) {
@@ -3341,7 +3345,7 @@
 			}
 		}
 	}
-	/*  Check for child controller specified by end node */
+	/* Check for child controller specified by end node */
 	if (ret != EFI_SUCCESS && remain_device_path &&
 	    remain_device_path->type == DEVICE_PATH_TYPE_END)
 		ret = EFI_SUCCESS;
@@ -3620,11 +3624,7 @@
 	},
 	.fw_vendor = firmware_vendor,
 	.fw_revision = FW_VERSION << 16 | FW_PATCHLEVEL << 8,
-	.con_in = &efi_con_in,
-	.con_out = &efi_con_out,
-	.std_err = &efi_con_out,
 	.runtime = &efi_runtime_services,
-	.boottime = &efi_boot_services,
 	.nr_tables = 0,
 	.tables = NULL,
 };
@@ -3644,6 +3644,15 @@
 				sizeof(struct efi_configuration_table),
 				(void **)&systab.tables);
 
+	/*
+	 * These entries will be set to NULL in ExitBootServices(). To avoid
+	 * relocation in SetVirtualAddressMap(), set them dynamically.
+	 */
+	systab.con_in = &efi_con_in;
+	systab.con_out = &efi_con_out;
+	systab.std_err = &efi_con_out;
+	systab.boottime = &efi_boot_services;
+
 	/* Set CRC32 field in table headers */
 	efi_update_table_header_crc32(&systab.hdr);
 	efi_update_table_header_crc32(&efi_runtime_services.hdr);
diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c
index 40fdc0e..7a64dd4 100644
--- a/lib/efi_loader/efi_runtime.c
+++ b/lib/efi_loader/efi_runtime.c
@@ -26,8 +26,6 @@
 LIST_HEAD(efi_runtime_mmio);
 
 static efi_status_t __efi_runtime EFIAPI efi_unimplemented(void);
-static efi_status_t __efi_runtime EFIAPI efi_device_error(void);
-static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void);
 
 /*
  * TODO(sjg@chromium.org): These defines and structures should come from the ELF
@@ -97,10 +95,7 @@
 	 * This value must be synced with efi_runtime_detach_list
 	 * as well as efi_runtime_services.
 	 */
-#if CONFIG_IS_ENABLED(ARCH_BCM283X) || \
-    CONFIG_IS_ENABLED(FSL_LAYERSCAPE) || \
-    CONFIG_IS_ENABLED(SYSRESET_X86) || \
-    CONFIG_IS_ENABLED(PSCI_RESET)
+#ifdef CONFIG_EFI_HAVE_RUNTIME_RESET
 	efi_runtime_services_supported |= EFI_RT_SUPPORTED_RESET_SYSTEM;
 #endif
 	efi_runtime_services_supported |=
@@ -387,80 +382,102 @@
 	return EFI_UNSUPPORTED;
 }
 
-struct efi_runtime_detach_list_struct {
-	void *ptr;
-	void *patchto;
-};
-
-static const struct efi_runtime_detach_list_struct efi_runtime_detach_list[] = {
-	{
-		/* do_reset is gone */
-		.ptr = &efi_runtime_services.reset_system,
-		.patchto = efi_reset_system,
-	}, {
-		/* invalidate_*cache_all are gone */
-		.ptr = &efi_runtime_services.set_virtual_address_map,
-		.patchto = &efi_unimplemented,
-	}, {
-		/* RTC accessors are gone */
-		.ptr = &efi_runtime_services.get_time,
-		.patchto = &efi_get_time,
-	}, {
-		.ptr = &efi_runtime_services.set_time,
-		.patchto = &efi_set_time,
-	}, {
-		/* Clean up system table */
-		.ptr = &systab.con_in,
-		.patchto = NULL,
-	}, {
-		/* Clean up system table */
-		.ptr = &systab.con_out,
-		.patchto = NULL,
-	}, {
-		/* Clean up system table */
-		.ptr = &systab.std_err,
-		.patchto = NULL,
-	}, {
-		/* Clean up system table */
-		.ptr = &systab.boottime,
-		.patchto = NULL,
-	}, {
-		.ptr = &efi_runtime_services.get_variable,
-		.patchto = &efi_device_error,
-	}, {
-		.ptr = &efi_runtime_services.get_next_variable_name,
-		.patchto = &efi_device_error,
-	}, {
-		.ptr = &efi_runtime_services.set_variable,
-		.patchto = &efi_device_error,
-	}
-};
+/**
+ * efi_is_runtime_service_pointer() - check if pointer points to runtime table
+ *
+ * @p:		pointer to check
+ * Return:	true if the pointer points to a service function pointer in the
+ *		runtime table
+ */
+static bool efi_is_runtime_service_pointer(void *p)
+{
+	return p >= (void *)&efi_runtime_services.get_time &&
+	       p <= (void *)&efi_runtime_services.query_variable_info;
+}
 
-static bool efi_runtime_tobedetached(void *p)
+/**
+ * efi_runtime_detach() - detach unimplemented runtime functions
+ */
+void efi_runtime_detach(void)
 {
-	int i;
+	efi_runtime_services.reset_system = efi_reset_system;
+	efi_runtime_services.get_time = efi_get_time;
+	efi_runtime_services.set_time = efi_set_time;
 
-	for (i = 0; i < ARRAY_SIZE(efi_runtime_detach_list); i++)
-		if (efi_runtime_detach_list[i].ptr == p)
-			return true;
+	/* Update CRC32 */
+	efi_update_table_header_crc32(&efi_runtime_services.hdr);
+}
 
-	return false;
+/**
+ * efi_set_virtual_address_map_runtime() - change from physical to virtual
+ *					   mapping
+ *
+ * This function implements the SetVirtualAddressMap() runtime service after
+ * it is first called.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @memory_map_size:	size of the virtual map
+ * @descriptor_size:	size of an entry in the map
+ * @descriptor_version:	version of the map entries
+ * @virtmap:		virtual address mapping information
+ * Return:		status code EFI_UNSUPPORTED
+ */
+static efi_status_t EFIAPI efi_set_virtual_address_map_runtime(
+			unsigned long memory_map_size,
+			unsigned long descriptor_size,
+			uint32_t descriptor_version,
+			struct efi_mem_desc *virtmap)
+{
+	return EFI_UNSUPPORTED;
 }
 
-static void efi_runtime_detach(ulong offset)
+/**
+ * efi_convert_pointer_runtime() - convert from physical to virtual pointer
+ *
+ * This function implements the ConvertPointer() runtime service after
+ * the first call to SetVirtualAddressMap().
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @debug_disposition:	indicates if pointer may be converted to NULL
+ * @address:		pointer to be converted
+ * Return:		status code EFI_UNSUPPORTED
+ */
+static __efi_runtime efi_status_t EFIAPI efi_convert_pointer_runtime(
+			efi_uintn_t debug_disposition, void **address)
 {
-	int i;
-	ulong patchoff = offset - (ulong)gd->relocaddr;
+	return EFI_UNSUPPORTED;
+}
 
-	for (i = 0; i < ARRAY_SIZE(efi_runtime_detach_list); i++) {
-		ulong patchto = (ulong)efi_runtime_detach_list[i].patchto;
-		ulong *p = efi_runtime_detach_list[i].ptr;
-		ulong newaddr = patchto ? (patchto + patchoff) : 0;
+static __efi_runtime void efi_relocate_runtime_table(ulong offset)
+{
+	ulong patchoff;
+	void **pos;
 
-		debug("%s: Setting %p to %lx\n", __func__, p, newaddr);
-		*p = newaddr;
+	/* Relocate the runtime services pointers */
+	patchoff = offset - gd->relocaddr;
+	for (pos = (void **)&efi_runtime_services.get_time;
+	     pos <= (void **)&efi_runtime_services.query_variable_info; ++pos) {
+		if (*pos)
+			*pos += patchoff;
 	}
 
+	/*
+	 * The entry for SetVirtualAddress() must point to a physical address.
+	 * After the first execution the service must return EFI_UNSUPPORTED.
+	 */
+	efi_runtime_services.set_virtual_address_map =
+			&efi_set_virtual_address_map_runtime;
+
+	/*
+	 * The entry for ConvertPointer() must point to a physical address.
+	 * The service is not usable after SetVirtualAddress().
+	 */
+	efi_runtime_services.convert_pointer = &efi_convert_pointer_runtime;
+
 	/* Update CRC32 */
 	efi_update_table_header_crc32(&efi_runtime_services.hdr);
 }
@@ -483,6 +500,10 @@
 
 		p = (void*)((ulong)rel->offset - base) + gd->relocaddr;
 
+		/* The runtime services are updated in efi_runtime_detach() */
+		if (map && efi_is_runtime_service_pointer(p))
+			continue;
+
 		debug("%s: rel->info=%#lx *p=%#lx rel->offset=%p\n", __func__,
 		      rel->info, *p, rel->offset);
 
@@ -506,9 +527,8 @@
 		}
 #endif
 		default:
-			if (!efi_runtime_tobedetached(p))
-				printf("%s: Unknown relocation type %llx\n",
-				       __func__, rel->info & R_MASK);
+			printf("%s: Unknown relocation type %llx\n",
+			       __func__, rel->info & R_MASK);
 			continue;
 		}
 
@@ -516,9 +536,8 @@
 		if (map && ((newaddr < map->virtual_start) ||
 		    newaddr > (map->virtual_start +
 			      (map->num_pages << EFI_PAGE_SHIFT)))) {
-			if (!efi_runtime_tobedetached(p))
-				printf("%s: Relocation at %p is out of "
-				       "range (%lx)\n", __func__, p, newaddr);
+			printf("%s: Relocation at %p is out of range (%lx)\n",
+			       __func__, p, newaddr);
 			continue;
 		}
 
@@ -623,7 +642,15 @@
 		}
 	}
 
+	/*
+	 * Some runtime services are implemented in a way that we can only offer
+	 * them at boottime. Replace those function pointers.
+	 *
+	 * TODO: move this call to ExitBootServices().
+	 */
+	efi_runtime_detach();
+
-	/* Move the actual runtime code over */
+	/* Relocate the runtime. See TODO above */
 	for (i = 0; i < n; i++) {
 		struct efi_mem_desc *map;
 
@@ -632,10 +659,8 @@
 			ulong new_offset = map->virtual_start -
 					   map->physical_start + gd->relocaddr;
 
+			efi_relocate_runtime_table(new_offset);
 			efi_runtime_relocate(new_offset, map);
-			/* Once we're virtual, we can no longer handle
-			   complex callbacks */
-			efi_runtime_detach(new_offset);
 			return EFI_EXIT(EFI_SUCCESS);
 		}
 	}
@@ -711,34 +736,6 @@
 }
 
 /**
- * efi_device_error() - replacement function, returns EFI_DEVICE_ERROR
- *
- * This function is used after SetVirtualAddressMap() is called as replacement
- * for services that are not available anymore due to constraints of the U-Boot
- * implementation.
- *
- * Return:	EFI_DEVICE_ERROR
- */
-static efi_status_t __efi_runtime EFIAPI efi_device_error(void)
-{
-	return EFI_DEVICE_ERROR;
-}
-
-/**
- * efi_invalid_parameter() - replacement function, returns EFI_INVALID_PARAMETER
- *
- * This function is used after SetVirtualAddressMap() is called as replacement
- * for services that are not available anymore due to constraints of the U-Boot
- * implementation.
- *
- * Return:	EFI_INVALID_PARAMETER
- */
-static efi_status_t __efi_runtime EFIAPI efi_invalid_parameter(void)
-{
-	return EFI_INVALID_PARAMETER;
-}
-
-/**
  * efi_update_capsule() - process information from operating system
  *
  * This function implements the UpdateCapsule() runtime service.
@@ -782,33 +779,6 @@
 	return EFI_UNSUPPORTED;
 }
 
-/**
- * efi_query_variable_info() - get information about EFI variables
- *
- * This function implements the QueryVariableInfo() runtime service.
- *
- * See the Unified Extensible Firmware Interface (UEFI) specification for
- * details.
- *
- * @attributes:				bitmask to select variables to be
- *					queried
- * @maximum_variable_storage_size:	maximum size of storage area for the
- *					selected variable types
- * @remaining_variable_storage_size:	remaining size of storage are for the
- *					selected variable types
- * @maximum_variable_size:		maximum size of a variable of the
- *					selected type
- * Returns:				status code
- */
-efi_status_t __efi_runtime EFIAPI efi_query_variable_info(
-			u32 attributes,
-			u64 *maximum_variable_storage_size,
-			u64 *remaining_variable_storage_size,
-			u64 *maximum_variable_size)
-{
-	return EFI_UNSUPPORTED;
-}
-
 struct efi_runtime_services __efi_runtime_data efi_runtime_services = {
 	.hdr = {
 		.signature = EFI_RUNTIME_SERVICES_SIGNATURE,
@@ -820,11 +790,11 @@
 	.get_wakeup_time = (void *)&efi_unimplemented,
 	.set_wakeup_time = (void *)&efi_unimplemented,
 	.set_virtual_address_map = &efi_set_virtual_address_map,
-	.convert_pointer = (void *)&efi_invalid_parameter,
+	.convert_pointer = (void *)&efi_unimplemented,
 	.get_variable = efi_get_variable,
 	.get_next_variable_name = efi_get_next_variable_name,
 	.set_variable = efi_set_variable,
-	.get_next_high_mono_count = (void *)&efi_device_error,
+	.get_next_high_mono_count = (void *)&efi_unimplemented,
 	.reset_system = &efi_reset_system_boottime,
 	.update_capsule = efi_update_capsule,
 	.query_capsule_caps = efi_query_capsule_caps,
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index bfb5783..de7b616 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -102,6 +102,11 @@
 	/* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */
 	switch_to_non_secure_mode();
 
+	/* Initialize variable services */
+	ret = efi_init_variables();
+	if (ret != EFI_SUCCESS)
+		goto out;
+
 	/* Define supported languages */
 	ret = efi_init_platform_lang();
 	if (ret != EFI_SUCCESS)
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index d6b75ca..bc8ed67 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -520,3 +520,84 @@
 
 	return EFI_EXIT(ret);
 }
+
+/**
+ * efi_query_variable_info() - get information about EFI variables
+ *
+ * This function implements the QueryVariableInfo() runtime service.
+ *
+ * See the Unified Extensible Firmware Interface (UEFI) specification for
+ * details.
+ *
+ * @attributes:				bitmask to select variables to be
+ *					queried
+ * @maximum_variable_storage_size:	maximum size of storage area for the
+ *					selected variable types
+ * @remaining_variable_storage_size:	remaining size of storage are for the
+ *					selected variable types
+ * @maximum_variable_size:		maximum size of a variable of the
+ *					selected type
+ * Returns:				status code
+ */
+efi_status_t __efi_runtime EFIAPI efi_query_variable_info(
+			u32 attributes,
+			u64 *maximum_variable_storage_size,
+			u64 *remaining_variable_storage_size,
+			u64 *maximum_variable_size)
+{
+	return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_get_variable_runtime() - runtime implementation of GetVariable()
+ */
+static efi_status_t __efi_runtime EFIAPI
+efi_get_variable_runtime(u16 *variable_name, const efi_guid_t *vendor,
+			 u32 *attributes, efi_uintn_t *data_size, void *data)
+{
+	return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_get_next_variable_name_runtime() - runtime implementation of
+ *					  GetNextVariable()
+ */
+static efi_status_t __efi_runtime EFIAPI
+efi_get_next_variable_name_runtime(efi_uintn_t *variable_name_size,
+				   u16 *variable_name, const efi_guid_t *vendor)
+{
+	return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_set_variable_runtime() - runtime implementation of SetVariable()
+ */
+static efi_status_t __efi_runtime EFIAPI
+efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *vendor,
+			 u32 attributes, efi_uintn_t data_size,
+			 const void *data)
+{
+	return EFI_UNSUPPORTED;
+}
+
+/**
+ * efi_variables_boot_exit_notify() - notify ExitBootServices() is called
+ */
+void efi_variables_boot_exit_notify(void)
+{
+	efi_runtime_services.get_variable = efi_get_variable_runtime;
+	efi_runtime_services.get_next_variable_name =
+				efi_get_next_variable_name_runtime;
+	efi_runtime_services.set_variable = efi_set_variable_runtime;
+	efi_update_table_header_crc32(&efi_runtime_services.hdr);
+}
+
+/**
+ * efi_init_variables() - initialize variable services
+ *
+ * Return:	status code
+ */
+efi_status_t efi_init_variables(void)
+{
+	return EFI_SUCCESS;
+}
diff --git a/lib/efi_selftest/Kconfig b/lib/efi_selftest/Kconfig
index 59f9f36..d20f589 100644
--- a/lib/efi_selftest/Kconfig
+++ b/lib/efi_selftest/Kconfig
@@ -1,9 +1,9 @@
 config CMD_BOOTEFI_SELFTEST
-	bool "Allow booting an EFI efi_selftest"
+	bool "UEFI unit tests"
 	depends on CMD_BOOTEFI
 	imply FAT
 	imply FAT_WRITE
 	help
-	  This adds an EFI test application to U-Boot that can be executed
-	  with the 'bootefi selftest' command. It provides extended tests of
-	  the EFI API implementation.
+	  This adds a UEFI test application to U-Boot that can be executed
+	  via the 'bootefi selftest' command. It provides extended tests of
+	  the UEFI API implementation.
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index 3bebd0f..8867875 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -35,6 +35,7 @@
 efi_selftest_tpl.o \
 efi_selftest_util.o \
 efi_selftest_variables.o \
+efi_selftest_variables_runtime.o \
 efi_selftest_watchdog.o
 
 obj-$(CONFIG_EFI_DEVICE_PATH_TO_TEXT) += efi_selftest_devicepath.o
diff --git a/lib/efi_selftest/efi_selftest_variables_runtime.c b/lib/efi_selftest/efi_selftest_variables_runtime.c
new file mode 100644
index 0000000..b3b40ad
--- /dev/null
+++ b/lib/efi_selftest/efi_selftest_variables_runtime.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * efi_selftest_variables_runtime
+ *
+ * Copyright (c) 2019 Heinrich Schuchardt <xypron.glpk@gmx.de>
+ *
+ * This unit test checks the runtime services for variables after
+ * ExitBootServices():
+ * GetVariable, GetNextVariableName, SetVariable, QueryVariableInfo.
+ */
+
+#include <efi_selftest.h>
+
+#define EFI_ST_MAX_DATA_SIZE 16
+#define EFI_ST_MAX_VARNAME_SIZE 40
+
+static struct efi_boot_services *boottime;
+static struct efi_runtime_services *runtime;
+static const efi_guid_t guid_vendor0 =
+	EFI_GUID(0x67029eb5, 0x0af2, 0xf6b1,
+		 0xda, 0x53, 0xfc, 0xb5, 0x66, 0xdd, 0x1c, 0xe6);
+
+/*
+ * Setup unit test.
+ *
+ * @handle	handle of the loaded image
+ * @systable	system table
+ */
+static int setup(const efi_handle_t img_handle,
+		 const struct efi_system_table *systable)
+{
+	boottime = systable->boottime;
+	runtime = systable->runtime;
+
+	return EFI_ST_SUCCESS;
+}
+
+/**
+ * execute() - execute unit test
+ *
+ * As runtime support is not implmented expect EFI_UNSUPPORTED to be returned.
+ */
+static int execute(void)
+{
+	efi_status_t ret;
+	efi_uintn_t len;
+	u32 attr;
+	u8 v[16] = {0x5d, 0xd1, 0x5e, 0x51, 0x5a, 0x05, 0xc7, 0x0c,
+		    0x35, 0x4a, 0xae, 0x87, 0xa5, 0xdf, 0x0f, 0x65,};
+	u8 data[EFI_ST_MAX_DATA_SIZE];
+	u16 varname[EFI_ST_MAX_VARNAME_SIZE];
+	efi_guid_t guid;
+	u64 max_storage, rem_storage, max_size;
+
+	ret = runtime->query_variable_info(EFI_VARIABLE_BOOTSERVICE_ACCESS,
+					   &max_storage, &rem_storage,
+					   &max_size);
+	if (ret != EFI_UNSUPPORTED) {
+		efi_st_error("QueryVariableInfo failed\n");
+		return EFI_ST_FAILURE;
+	}
+
+	ret = runtime->set_variable(L"efi_st_var0", &guid_vendor0,
+				    EFI_VARIABLE_BOOTSERVICE_ACCESS |
+				    EFI_VARIABLE_RUNTIME_ACCESS,
+				    3, v + 4);
+	if (ret != EFI_UNSUPPORTED) {
+		efi_st_error("SetVariable failed\n");
+		return EFI_ST_FAILURE;
+	}
+	len = 3;
+	ret = runtime->get_variable(L"efi_st_var0", &guid_vendor0,
+				    &attr, &len, data);
+	if (ret != EFI_UNSUPPORTED) {
+		efi_st_error("GetVariable failed\n");
+		return EFI_ST_FAILURE;
+	}
+	memset(&guid, 0, 16);
+	*varname = 0;
+	ret = runtime->get_next_variable_name(&len, varname, &guid);
+	if (ret != EFI_UNSUPPORTED) {
+		efi_st_error("GetNextVariableName failed\n");
+		return EFI_ST_FAILURE;
+	}
+
+	return EFI_ST_SUCCESS;
+}
+
+EFI_UNIT_TEST(variables_run) = {
+	.name = "variables at runtime",
+	.phase = EFI_SETUP_BEFORE_BOOTTIME_EXIT,
+	.setup = setup,
+	.execute = execute,
+};
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index d252045..2fc77b7 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -473,7 +473,6 @@
 CONFIG_ENV_TOTAL_SIZE
 CONFIG_ENV_UBIFS_OPTION
 CONFIG_ENV_UBI_MTD
-CONFIG_ENV_UBI_VOLUME_REDUND
 CONFIG_ENV_VERSION
 CONFIG_EP9302
 CONFIG_EP9307
@@ -1795,18 +1794,6 @@
 CONFIG_SPL_STACK_SIZE
 CONFIG_SPL_START_S_PATH
 CONFIG_SPL_TARGET
-CONFIG_SPL_UBI
-CONFIG_SPL_UBI_INFO_ADDR
-CONFIG_SPL_UBI_LEB_START
-CONFIG_SPL_UBI_LOAD_ARGS_ID
-CONFIG_SPL_UBI_LOAD_KERNEL_ID
-CONFIG_SPL_UBI_LOAD_MONITOR_ID
-CONFIG_SPL_UBI_MAX_PEBS
-CONFIG_SPL_UBI_MAX_PEB_SIZE
-CONFIG_SPL_UBI_MAX_VOL_LEBS
-CONFIG_SPL_UBI_PEB_OFFSET
-CONFIG_SPL_UBI_VID_OFFSET
-CONFIG_SPL_UBI_VOL_IDS
 CONFIG_SPL_UBOOT_KEY_HASH
 CONFIG_SRAM_BASE
 CONFIG_SRAM_SIZE
diff --git a/test/py/tests/test_efi_selftest.py b/test/py/tests/test_efi_selftest.py
index 07e4db0..d5430f9 100644
--- a/test/py/tests/test_efi_selftest.py
+++ b/test/py/tests/test_efi_selftest.py
@@ -19,10 +19,6 @@
 	m = u_boot_console.p.expect(['Summary: 0 failures', 'Press any key'])
 	if m != 0:
 		raise Exception('Failures occurred during the EFI selftest')
-	u_boot_console.run_command(cmd='', wait_for_echo=False, wait_for_prompt=False);
-	m = u_boot_console.p.expect(['resetting', 'U-Boot'])
-	if m != 0:
-		raise Exception('Reset failed during the EFI selftest')
 	u_boot_console.restart_uboot();
 
 @pytest.mark.buildconfigspec('cmd_bootefi_selftest')
@@ -37,7 +33,7 @@
 	u_boot_console.run_command(cmd='bootefi selftest ${fdtcontroladdr}', wait_for_prompt=False)
 	m = u_boot_console.p.expect(['serial-number: Testing DT', 'U-Boot'])
 	if m != 0:
-		raise Exception('Reset failed in \'device tree\' test')
+		raise Exception('serial-number missing in device tree')
 	u_boot_console.restart_uboot();
 
 @pytest.mark.buildconfigspec('cmd_bootefi_selftest')
diff --git a/tools/moveconfig.py b/tools/moveconfig.py
index 1a214c5..0bbc7c1 100755
--- a/tools/moveconfig.py
+++ b/tools/moveconfig.py
@@ -354,6 +354,26 @@
 
 CONFIG_LEN = len('CONFIG_')
 
+SIZES = {
+    "SZ_1":    0x00000001, "SZ_2":    0x00000002,
+    "SZ_4":    0x00000004, "SZ_8":    0x00000008,
+    "SZ_16":   0x00000010, "SZ_32":   0x00000020,
+    "SZ_64":   0x00000040, "SZ_128":  0x00000080,
+    "SZ_256":  0x00000100, "SZ_512":  0x00000200,
+    "SZ_1K":   0x00000400, "SZ_2K":   0x00000800,
+    "SZ_4K":   0x00001000, "SZ_8K":   0x00002000,
+    "SZ_16K":  0x00004000, "SZ_32K":  0x00008000,
+    "SZ_64K":  0x00010000, "SZ_128K": 0x00020000,
+    "SZ_256K": 0x00040000, "SZ_512K": 0x00080000,
+    "SZ_1M":   0x00100000, "SZ_2M":   0x00200000,
+    "SZ_4M":   0x00400000, "SZ_8M":   0x00800000,
+    "SZ_16M":  0x01000000, "SZ_32M":  0x02000000,
+    "SZ_64M":  0x04000000, "SZ_128M": 0x08000000,
+    "SZ_256M": 0x10000000, "SZ_512M": 0x20000000,
+    "SZ_1G":   0x40000000, "SZ_2G":   0x80000000,
+    "SZ_4G":  0x100000000
+}
+
 ### helper functions ###
 def get_devnull():
     """Get the file object of '/dev/null' device."""
@@ -777,6 +797,25 @@
     with open('README', 'w') as f:
         f.write(''.join(newlines))
 
+def try_expand(line):
+    """If value looks like an expression, try expanding it
+    Otherwise just return the existing value
+    """
+    if line.find('=') == -1:
+        return line
+
+    try:
+        cfg, val = re.split("=", line)
+        val= val.strip('\"')
+        if re.search("[*+-/]|<<|SZ_+|\(([^\)]+)\)", val):
+            newval = hex(eval(val, SIZES))
+            print "\tExpanded expression %s to %s" % (val, newval)
+            return cfg+'='+newval
+    except:
+        print "\tFailed to expand expression in %s" % line
+
+    return line
+
 
 ### classes ###
 class Progress:
@@ -891,6 +930,8 @@
         else:
             new_val = not_set
 
+        new_val = try_expand(new_val)
+
         for line in dotconfig_lines:
             line = line.rstrip()
             if line.startswith(config + '=') or line == not_set: