diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index 20135f5..f6d326b 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -11,8 +11,8 @@
 #define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMEROFF		0xbff8
 #define RISCV_MMODE_TIMER_FREQ		1000000
-
 #define RISCV_SMODE_TIMER_FREQ		1000000
 
 /* Environment options */
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index de3a0dc..f208f5e 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -14,8 +14,8 @@
 #define CFG_SYS_SDRAM_BASE		0x80000000
 
 #define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMEROFF		0xbff8
 #define RISCV_MMODE_TIMER_FREQ		1000000
-
 #define RISCV_SMODE_TIMER_FREQ		1000000
 
 /* Environment options */
diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h
index 93dcc22..4ee02b8 100644
--- a/include/configs/starfive-visionfive2.h
+++ b/include/configs/starfive-visionfive2.h
@@ -9,6 +9,7 @@
 #define _STARFIVE_VISIONFIVE2_H
 
 #define RISCV_MMODE_TIMERBASE		0x2000000
+#define RISCV_MMODE_TIMEROFF		0xbff8
 #define RISCV_MMODE_TIMER_FREQ		4000000
 #define RISCV_SMODE_TIMER_FREQ		4000000