commit 5190decd54d3f01827600f8611a2a28d1d70020e
author Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Tue Dec 01 00:34:47 2020 -0700
committer Michal Simek <michal.simek@xilinx.com> Mon Jan 04 10:51:26 2021 +0100
tree 409b92d16db048cbd3dd2d7fb24eac4891014770
parent cfd8a6e3aac66564e2c8a6a4813b4658bb786dc3

serial: uartlite: Fix uninitialized ret in debug uartlite

Endianness detection is checked against uninitialized ret variable.
Assign ret with read value from status register to fix this.

Fixes: 31a359f87eaa ("serial: uartlite: Add support to work with any endianness")
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

drivers/serial/serial_xuartlite.c

diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index 236ab86..1453fb4 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -148,7 +148,7 @@
 
 	uart_out32(&regs->control, 0);
 	uart_out32(&regs->control, ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
-	uart_in32(&regs->status);
+	ret = uart_in32(&regs->status);
 	/* Endianness detection */
 	if ((ret & SR_TX_FIFO_EMPTY) != SR_TX_FIFO_EMPTY) {
 		little_endian = true;