Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23051
- risc-v: Add Zicbom support
- board: Support RVVM board
- DTS: device tree fixes
- configs: Enable some configs
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index fa37102..043d963 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -21,7 +21,7 @@
bool "Support RISC-V cores on OpenPiton SoC"
config TARGET_QEMU_VIRT
- bool "Support QEMU Virt Board"
+ bool "Support QEMU Virt & RVVM Boards"
select BOARD_LATE_INIT
config TARGET_SIFIVE_UNLEASHED
@@ -319,6 +319,10 @@
help
Adds "A" to the ISA string passed to the compiler.
+config RISCV_ISA_ZICBOM
+ bool "Zicbom support"
+ depends on !SYS_DISABLE_DCACHE_OPS
+
config DMA_ADDR_T_64BIT
bool
default y if 64BIT
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h
new file mode 100644
index 0000000..19a10ca
--- /dev/null
+++ b/arch/riscv/include/asm/insn-def.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Ventana Micro Systems Ltd.
+ *
+ * Ported from linux insn-def.h.
+ */
+
+#ifndef _ASM_RISCV_BARRIER_H
+#define _ASM_RISCV_BARRIER_H
+
+#define INSN_I_SIMM12_SHIFT 20
+#define INSN_I_RS1_SHIFT 15
+#define INSN_I_FUNC3_SHIFT 12
+#define INSN_I_RD_SHIFT 7
+#define INSN_I_OPCODE_SHIFT 0
+
+#define RV_OPCODE(v) __ASM_STR(v)
+#define RV_FUNC3(v) __ASM_STR(v)
+#define RV_FUNC7(v) __ASM_STR(v)
+#define RV_SIMM12(v) __ASM_STR(v)
+#define RV_RD(v) __ASM_STR(v)
+#define RV_RS1(v) __ASM_STR(v)
+#define RV_RS2(v) __ASM_STR(v)
+#define __RV_REG(v) __ASM_STR(x ## v)
+#define RV___RD(v) __RV_REG(v)
+#define RV___RS1(v) __RV_REG(v)
+#define RV___RS2(v) __RV_REG(v)
+
+#define RV_OPCODE_MISC_MEM RV_OPCODE(15)
+#define RV_OPCODE_SYSTEM RV_OPCODE(115)
+
+#define __INSN_I(opcode, func3, rd, rs1, simm12) \
+ ".insn i " opcode ", " func3 ", " rd ", " rs1 ", " simm12 "\n"
+
+#define INSN_I(opcode, func3, rd, rs1, simm12) \
+ __INSN_I(RV_##opcode, RV_##func3, RV_##rd, \
+ RV_##rs1, RV_##simm12)
+
+#endif /* _ASM_RISCV_BARRIER_H */
diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
index ad32ded..47124db 100644
--- a/arch/riscv/include/asm/sbi.h
+++ b/arch/riscv/include/asm/sbi.h
@@ -33,8 +33,10 @@
SBI_EXT_CPPC = 0x43505043,
SBI_EXT_NACL = 0x4E41434C,
SBI_EXT_STA = 0x535441,
- SBI_EXT_DBTR = 0x44425452,
SBI_EXT_SSE = 0x535345,
+ SBI_EXT_FWFT = 0x46574654,
+ SBI_EXT_DBTR = 0x44425452,
+ SBI_EXT_MPXY = 0x4D505859,
};
enum sbi_ext_base_fid {
diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
index afad7e1..e184d5e 100644
--- a/arch/riscv/lib/cache.c
+++ b/arch/riscv/lib/cache.c
@@ -5,6 +5,98 @@
*/
#include <cpu_func.h>
+#include <dm.h>
+#include <asm/insn-def.h>
+#include <linux/const.h>
+
+#define CBO_INVAL(base) \
+ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
+ RS1(base), SIMM12(0))
+#define CBO_CLEAN(base) \
+ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
+ RS1(base), SIMM12(1))
+#define CBO_FLUSH(base) \
+ INSN_I(OPCODE_MISC_MEM, FUNC3(2), __RD(0), \
+ RS1(base), SIMM12(2))
+enum {
+ CBO_CLEAN,
+ CBO_FLUSH,
+ CBO_INVAL
+} riscv_cbo_ops;
+static int zicbom_block_size;
+
+static inline void do_cbo_clean(unsigned long base)
+{
+ asm volatile ("add a0, %0, zero\n" CBO_CLEAN(%0) ::
+ "r"(base) : "memory");
+}
+
+static inline void do_cbo_flush(unsigned long base)
+{
+ asm volatile ("add a0, %0, zero\n" CBO_FLUSH(%0) ::
+ "r"(base) : "memory");
+}
+
+static inline void do_cbo_inval(unsigned long base)
+{
+ asm volatile ("add a0, %0, zero\n" CBO_INVAL(%0) ::
+ "r"(base) : "memory");
+}
+
+static void cbo_op(int op_type, unsigned long start,
+ unsigned long end)
+{
+ unsigned long op_size = end - start, size = 0;
+ void (*fn)(unsigned long base);
+
+ switch (op_type) {
+ case CBO_CLEAN:
+ fn = do_cbo_clean;
+ break;
+ case CBO_FLUSH:
+ fn = do_cbo_flush;
+ break;
+ case CBO_INVAL:
+ fn = do_cbo_inval;
+ break;
+ }
+ start &= ~(UL(zicbom_block_size - 1));
+ while (size < op_size) {
+ fn(start + size);
+ size += zicbom_block_size;
+ }
+}
+
+void cbo_flush(unsigned long start, unsigned long end)
+{
+ if (zicbom_block_size)
+ cbo_op(CBO_FLUSH, start, end);
+}
+
+void cbo_inval(unsigned long start, unsigned long end)
+{
+ if (zicbom_block_size)
+ cbo_op(CBO_INVAL, start, end);
+}
+
+static int riscv_zicbom_init(void)
+{
+ struct udevice *dev;
+
+ if (!CONFIG_IS_ENABLED(RISCV_ISA_ZICBOM) || zicbom_block_size)
+ return 1;
+
+ uclass_first_device(UCLASS_CPU, &dev);
+ if (!dev) {
+ log_debug("Failed to get cpu device!\n");
+ return 0;
+ }
+
+ if (dev_read_u32(dev, "riscv,cbom-block-size", &zicbom_block_size))
+ log_debug("riscv,cbom-block-size DT property not present\n");
+
+ return zicbom_block_size;
+}
void invalidate_icache_all(void)
{
@@ -17,6 +109,7 @@
__weak void flush_dcache_range(unsigned long start, unsigned long end)
{
+ cbo_flush(start, end);
}
__weak void invalidate_icache_range(unsigned long start, unsigned long end)
@@ -30,6 +123,7 @@
__weak void invalidate_dcache_range(unsigned long start, unsigned long end)
{
+ cbo_inval(start, end);
}
void cache_flush(void)
@@ -72,4 +166,6 @@
__weak void enable_caches(void)
{
+ if (!riscv_zicbom_init())
+ log_info("Zicbom not initialized.\n");
}
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index c658e72..6dfd1a2 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -142,7 +142,7 @@
size = fdt_totalsize(blob);
err = fdt_open_into(blob, blob, size + 32);
if (err < 0) {
- log_err("Device Tree can't be expanded to accommodate new node");
+ log_err("Device-tree can't be expanded to accommodate new node\n");
return err;
}
chosen_offset = fdt_path_offset(blob, "/chosen");
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 9538c66..012ac14 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -58,6 +58,8 @@
imply E1000
imply PCI
imply NVME_PCI
+ imply VIDEO
+ imply VIDEO_SIMPLE
imply PCIE_ECAM_GENERIC
imply DM_RNG
imply DM_RTC
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index f55c6b5..3fd535e 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -41,7 +41,7 @@
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
- "rx-internal-delay-ps", "1900"},
+ "rx-internal-delay-ps", "1500"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"tx-internal-delay-ps", "1500"},
};
@@ -68,9 +68,7 @@
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
"motorcomm,rx-data-drv-microamp", "2910"},
{"/soc/ethernet@16030000/mdio/ethernet-phy@0",
- "rx-internal-delay-ps", "1900"},
- {"/soc/ethernet@16030000/mdio/ethernet-phy@0",
- "tx-internal-delay-ps", "1500"},
+ "rx-internal-delay-ps", "1500"},
{"/soc/ethernet@16040000/mdio/ethernet-phy@1",
"motorcomm,tx-clk-adj-enabled", NULL},
diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c
index a231604..5ecf567 100644
--- a/cmd/riscv/sbi.c
+++ b/cmd/riscv/sbi.c
@@ -54,8 +54,10 @@
{ SBI_EXT_CPPC, "Collaborative Processor Performance Control Extension" },
{ SBI_EXT_NACL, "Nested Acceleration Extension" },
{ SBI_EXT_STA, "Steal-time Accounting Extension" },
- { SBI_EXT_DBTR, "Debug Trigger Extension" },
{ SBI_EXT_SSE, "Supervisor Software Events" },
+ { SBI_EXT_FWFT, "Firmware Features Extension" },
+ { SBI_EXT_DBTR, "Debug Triggers Extension" },
+ { SBI_EXT_MPXY, "Message Proxy Extension" },
};
static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc,
diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig
index 511645c..c350892 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -62,6 +62,7 @@
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_PROMPT="StarFive # "
+CONFIG_CMD_ERASEENV=y
CONFIG_CMD_EEPROM=y
CONFIG_SYS_EEPROM_SIZE=512
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=4
diff --git a/configs/th1520_lpi4a_defconfig b/configs/th1520_lpi4a_defconfig
index a57cedb..3b6ff62 100644
--- a/configs/th1520_lpi4a_defconfig
+++ b/configs/th1520_lpi4a_defconfig
@@ -4,6 +4,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000
+CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a"
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_SYS_LOAD_ADDR=0x80200000
@@ -50,6 +51,7 @@
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_GPIO=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_ITEST is not set
@@ -61,7 +63,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_NO_NET=y
# CONFIG_BLOCK_CACHE is not set
-# CONFIG_GPIO is not set
+CONFIG_DWAPB_GPIO=y
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
# CONFIG_DM_MMC is not set
diff --git a/drivers/gpio/dwapb_gpio.c b/drivers/gpio/dwapb_gpio.c
index 7a6eae9..04639a4 100644
--- a/drivers/gpio/dwapb_gpio.c
+++ b/drivers/gpio/dwapb_gpio.c
@@ -177,7 +177,9 @@
plat->base = (void *)base;
plat->bank = bank;
- plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
+
+ if (ofnode_read_u32(node, "ngpios", &plat->pins))
+ plat->pins = ofnode_read_u32_default(node, "snps,nr-gpios", 0);
if (ofnode_read_string_index(node, "bank-name", 0,
&plat->name)) {
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index 2f594bf..cf4fcb9 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -22,6 +22,7 @@
"stderr=serial,vidconsole\0"
#define BOOT_TARGET_DEVICES(func) \
+ func(NVME, nvme, 0) \
func(VIRTIO, virtio, 0) \
func(VIRTIO, virtio, 1) \
func(SCSI, scsi, 0) \