tree ccefe89314acbc2b9a0e1d7a450eeb1cb83b584c
parent b1c4269991839c571de04b2d0b11a581cdfa5705
author Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> 1554836526 +0200
committer Marek Vasut <marex@denx.de> 1556143249 +0200

arm: socfpga: gen5: reduce SPL pre-reloc malloc

By enabling debug prints in malloc_simple, we can see that SPL for socfpga
gen5 does by far not need the 8 KiB malloc pool currently allocated for
SPL in pre-reloc phase.

On socfpga_socrates, 1304 bytes are currently used (and this increases by
~200 bytes only for the sdram/reset fixes in socfpga-next).

To prevent wasting precious SRAM space, let's reduce the initial heap used
for SPL to 2 KiB. This is still some hundred bytes more than currently
used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
early. Only the initial uclass/dm parsing, serial console and DDR
initialization is done in the initial heap, so these 2 KiB should be
enough for all boards.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>