ppc: xilinx-ppc4xx: Port to DM serial
xilinx_uartlite has been ported to DM, this patch makes the
xilinx-ppc405-generic and the xilinx-ppc440-generic boards use the new
DM driver.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
index 8b10dba..32105a8 100644
--- a/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
+++ b/board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
@@ -46,3 +46,7 @@
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
+
+int get_serial_clock(void){
+ return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+}
diff --git a/board/xilinx/ppc405-generic/xparameters.h b/board/xilinx/ppc405-generic/xparameters.h
index 90fe969..c3df9e5 100644
--- a/board/xilinx/ppc405-generic/xparameters.h
+++ b/board/xilinx/ppc405-generic/xparameters.h
@@ -19,7 +19,6 @@
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
-#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif
diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
index 3718a76..f92a303 100644
--- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
+++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
@@ -39,3 +39,7 @@
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
+
+int get_serial_clock(void){
+ return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
+}
diff --git a/board/xilinx/ppc440-generic/xparameters.h b/board/xilinx/ppc440-generic/xparameters.h
index e307de9..9685560 100644
--- a/board/xilinx/ppc440-generic/xparameters.h
+++ b/board/xilinx/ppc440-generic/xparameters.h
@@ -17,7 +17,6 @@
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
-#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif