mmc: fsl_esdhc: drop i.MX DDR support code
A previous patch below adding DDR mode support was actually for i.MX
platforms. Now i.MX eSDHC driver is fsl_esdhc_imx.c. For QorIQ eSDHC,
it uses different process for DDR mode, and hasn't been supported.
Let's drop DDR support code for i.MX in fsl_esdhc driver.
0e1bf61 mmc: fsl_esdhc: Add support for DDR mode
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 03c54c3..cd357ea 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -501,7 +501,6 @@
struct fsl_esdhc *regs = priv->esdhc_regs;
int div = 1;
int pre_div = 2;
- int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
unsigned int sdhc_clk = priv->sdhc_clk;
u32 time_out;
u32 value;
@@ -510,10 +509,10 @@
if (clock < mmc->cfg->f_min)
clock = mmc->cfg->f_min;
- while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
+ while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
pre_div *= 2;
- while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
+ while (sdhc_clk / (div * pre_div) > clock && div < 16)
div++;
pre_div >>= 1;
@@ -773,9 +772,6 @@
cfg->host_caps = MMC_MODE_4BIT;
cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
-#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
- cfg->host_caps |= MMC_MODE_DDR_52MHz;
-#endif
if (priv->bus_width > 0) {
if (priv->bus_width < 8)