commit 4e2f4dffcf406be2143f24949a707093b21206ea
author Michal Simek <michal.simek@xilinx.com> Thu Sep 13 08:44:02 2018 +0200
committer Michal Simek <michal.simek@xilinx.com> Tue Oct 16 14:58:45 2018 +0200
tree b8b9281ae1e35f3ada1e0694e34ae9b3c517a661
parent b20b19eabcb719fada497d20fbec78b9ed1ebec4

arm: zynq: Add support for DLC20 board

Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).

Boards have mix of Winbond/ST QSPIs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

arch/arm/dts/Makefile

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dfe9335..8e6f8e9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -135,6 +135,7 @@
 	zynq-cse-nand.dtb \
 	zynq-cse-nor.dtb \
 	zynq-cse-qspi-single.dtb \
+	zynq-dlc20-rev1.0.dtb \
 	zynq-microzed.dtb \
 	zynq-minized.dtb \
 	zynq-picozed.dtb \