arm: zynqmp: Enable non-invasive CCI-400 PMU debug
Set NIDEN, enabling non-invasive debug for the CCI-400 PMU. Otherwise,
the PMU is effectively disabled.
Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240905171833.325548-3-sean.anderson@linux.dev
Signed-off-by: Michal Simek <michal.simek@amd.com>
diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h
index eb8fffa..49e449e 100644
--- a/arch/arm/mach-zynqmp/include/mach/hardware.h
+++ b/arch/arm/mach-zynqmp/include/mach/hardware.h
@@ -132,6 +132,9 @@
#define crfapb_base ((struct crfapb_regs *)ZYNQMP_CRF_APB_BASEADDR)
+#define ZYNQMP_CCI_REG_CCI_MISC_CTRL 0xFD5E0040
+#define ZYNQMP_CCI_REG_CCI_MISC_CTRL_NIDEN BIT(1)
+
#define ZYNQMP_APU_BASEADDR 0xFD5C0000
struct apu_regs {
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 56e3b36..20a675c 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -76,6 +76,10 @@
writel(0x04920492, ZYNQMP_IOU_SECURE_SLCR);
writel(0x00920492, ZYNQMP_IOU_SECURE_SLCR + 4);
+ /* Enable CCI PMU events */
+ writel(ZYNQMP_CCI_REG_CCI_MISC_CTRL_NIDEN,
+ ZYNQMP_CCI_REG_CCI_MISC_CTRL);
+
/* Delay is required for clocks to be propagated */
udelay(1000000);