| commit | 654c50b266b0f4fc0365b1d4881904ccc041d977 | [log] [tgz] |
|---|---|---|
| author | Duy Nguyen <duy.nguyen.rh@renesas.com> | Sun Jan 28 16:51:59 2024 +0100 |
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | Sat Feb 10 17:08:06 2024 +0100 |
| tree | 8de8bba8dbef100b55301752d80c9cd4ecaf7523 | |
| parent | f70dc3650f970c012b35f5476eefe779e82e33ba [diff] |
dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4M (R8A779H0) SoC. The current version is imported from: https://lore.kernel.org/linux-renesas-soc/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be/ Signed-off-by: Duy Nguyen <duy.nguyen.rh@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>