tree ad1f6527943f089fa6e7f90a7d35fcd78675cbf6
parent 635638ff9a8dcb0bd2867b560aebe941f53adfef
author Chin Liang See <clsee@altera.com> 1402381612 -0500
committer Pantelis Antoniou <panto@antoniou-consulting.com> 1406911532 +0300

mmc/dw_mmc: Fix clock divider calculation error for bypass mode

To fix the clock divider calculation error when the controller
clock same as the operating frequency. This is known as bypass
mode. In this mode, the divider should be 0.

Signed-off-by: Chin Liang See <clsee@altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Mischa Jonker <mjonker@synopsys.com>