imx: imx8ulp: add ND/LD clock
Add a new ddr script, defconfig for ND
Configure the clock for ND mode
changing A35 to 960MHz for OD mode
Update NIC CLK for the various modes
Introduce clock_init_early/late, late is used after pmic voltage
setting, early is used in the very early stage for upower mu, lpuart and
etc.
Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with
cpuidle enabled now.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index a2b3ce7..4697157 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -102,7 +102,7 @@
/* enable pll4 and ddrclk*/
cgc2_pll4_init();
- cgc2_ddrclk_config(1, 1);
+ cgc2_ddrclk_config(4, 1);
/* enable ddr pcc */
writel(0xd0000000, PCC5_LPDDR4_ADDR);
@@ -153,30 +153,66 @@
return 0;
}
-void clock_init(void)
+void clock_init_early(void)
{
cgc1_soscdiv_init();
- cgc1_init_core_clk();
init_clk_lpuart();
- pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
- pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
- pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
- pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+ /* Enable upower mu1 clk */
+ pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
+}
- pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
- pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
- pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
- pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+/* This will be invoked after pmic voltage setting */
+void clock_init_late(void)
+{
- pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
- pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
- pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
- pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+ if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE))
+ cgc1_init_core_clk(MHZ(500));
+ else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE))
+ cgc1_init_core_clk(MHZ(750));
+ else
+ cgc1_init_core_clk(MHZ(960));
- /* Enable upower mu1 clk */
- pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
+ /*
+ * Audio use this frequency in kernel dts,
+ * however nic use pll3 pfd0, we have to
+ * make the freqency same as kernel to make nic
+ * not being disabled
+ */
+ cgc1_pll3_init(540672000);
+
+ if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
+ pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2);
+ pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+
+ pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2);
+ pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+
+ pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2);
+ pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+ } else {
+ pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
+ pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
+
+ pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
+ pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
+
+ pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
+ pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
+ pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
+ pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
+ }
/*
* Enable clock division