imx: imx8ulp: add ND/LD clock
Add a new ddr script, defconfig for ND
Configure the clock for ND mode
changing A35 to 960MHz for OD mode
Update NIC CLK for the various modes
Introduce clock_init_early/late, late is used after pmic voltage
setting, early is used in the very early stage for upower mu, lpuart and
etc.
Note: NIC runs at 324MHz, 442MHz has some random kernel hang issue with
cpuidle enabled now.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/include/asm/arch-imx8ulp/cgc.h b/arch/arm/include/asm/arch-imx8ulp/cgc.h
index ad3edc8..e45f046 100644
--- a/arch/arm/include/asm/arch-imx8ulp/cgc.h
+++ b/arch/arm/include/asm/arch-imx8ulp/cgc.h
@@ -146,10 +146,10 @@
};
u32 cgc_clk_get_rate(enum cgc_clk clk);
-void cgc1_pll3_init(void);
-void cgc1_pll2_init(void);
+void cgc1_pll3_init(ulong freq);
+void cgc1_pll2_init(ulong freq);
void cgc1_soscdiv_init(void);
-void cgc1_init_core_clk(void);
+void cgc1_init_core_clk(ulong freq);
void cgc2_pll4_init(void);
void cgc2_ddrclk_config(u32 src, u32 div);
void cgc2_ddrclk_wait_unlock(void);