diff --git a/include/dt-bindings/clock/imx8ulp-clock.h b/include/dt-bindings/clock/imx8ulp-clock.h
index 49166a1..953ecfe 100644
--- a/include/dt-bindings/clock/imx8ulp-clock.h
+++ b/include/dt-bindings/clock/imx8ulp-clock.h
@@ -1,16 +1,14 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
 /*
- * Copyright 2020 NXP
+ * Copyright 2021 NXP
  */
 
 #ifndef __DT_BINDINGS_CLOCK_IMX8ULP_H
 #define __DT_BINDINGS_CLOCK_IMX8ULP_H
 
 #define IMX8ULP_CLK_DUMMY			0
-#define IMX8ULP_CLK_ROSC			1
-#define IMX8ULP_CLK_FROSC			2
-#define IMX8ULP_CLK_LPOSC			3
-#define IMX8ULP_CLK_SOSC			4
+
+/* CGC1 */
 #define IMX8ULP_CLK_SPLL2			5
 #define IMX8ULP_CLK_SPLL3			6
 #define IMX8ULP_CLK_A35_SEL			7
@@ -57,14 +55,15 @@
 #define IMX8ULP_CLK_FROSC_DIV1_GATE		48
 #define IMX8ULP_CLK_FROSC_DIV2_GATE		49
 #define IMX8ULP_CLK_FROSC_DIV3_GATE		50
-#define IMX8ULP_CLK_ENETSTAMP_SEL		51
-#define IMX8ULP_CLK_SAI4_SEL			52
-#define IMX8ULP_CLK_SAI5_SEL			53
-#define IMX8ULP_CLK_AUD_CLK1			54
-#define IMX8ULP_CLK_ARM				55
+#define IMX8ULP_CLK_SAI4_SEL			51
+#define IMX8ULP_CLK_SAI5_SEL			52
+#define IMX8ULP_CLK_AUD_CLK1			53
+#define IMX8ULP_CLK_ARM				54
+#define IMX8ULP_CLK_ENET_TS_SEL			55
 
 #define IMX8ULP_CLK_CGC1_END			56
 
+/* CGC2 */
 #define IMX8ULP_CLK_PLL4_PRE_SEL	0
 #define IMX8ULP_CLK_PLL4		1
 #define IMX8ULP_CLK_PLL4_VCODIV		2
@@ -110,8 +109,12 @@
 #define IMX8ULP_CLK_SAI6_SEL		42
 #define IMX8ULP_CLK_SAI7_SEL		43
 #define IMX8ULP_CLK_SPDIF_SEL		44
+#define IMX8ULP_CLK_HIFI_SEL		45
+#define IMX8ULP_CLK_HIFI_DIVCORE	46
+#define IMX8ULP_CLK_HIFI_DIVPLAT	47
+#define IMX8ULP_CLK_DSI_PHY_REF		48
 
-#define IMX8ULP_CLK_CGC2_END		45
+#define IMX8ULP_CLK_CGC2_END		49
 
 /* PCC3 */
 #define IMX8ULP_CLK_WDOG3		0
@@ -160,9 +163,12 @@
 #define IMX8ULP_CLK_DMA1_CH29		43
 #define IMX8ULP_CLK_DMA1_CH30		44
 #define IMX8ULP_CLK_DMA1_CH31		45
+#define IMX8ULP_CLK_MU3_A		46
+#define IMX8ULP_CLK_MU0_B		47
 
-#define IMX8ULP_CLK_PCC3_END		46
+#define IMX8ULP_CLK_PCC3_END		48
 
+/* PCC4 */
 #define IMX8ULP_CLK_FLEXSPI2		0
 #define IMX8ULP_CLK_TPM6		1
 #define IMX8ULP_CLK_TPM7		2
@@ -189,24 +195,25 @@
 
 #define IMX8ULP_CLK_PCC4_END		23
 
+/* PCC5 */
 #define IMX8ULP_CLK_TPM8		0
 #define IMX8ULP_CLK_SAI6		1
 #define IMX8ULP_CLK_SAI7		2
 #define IMX8ULP_CLK_SPDIF		3
-#define IMX8ULP_CLK_ISI		4
-#define IMX8ULP_CLK_CSI_REGS		5
+#define IMX8ULP_CLK_ISI			4
+#define IMX8ULP_CLK_CSI_REGS 		5
 #define IMX8ULP_CLK_PCTLD		6
-#define IMX8ULP_CLK_CSI		7
-#define IMX8ULP_CLK_DSI		8
+#define IMX8ULP_CLK_CSI			7
+#define IMX8ULP_CLK_DSI			8
 #define IMX8ULP_CLK_WDOG5		9
 #define IMX8ULP_CLK_EPDC		10
-#define IMX8ULP_CLK_PXP		11
+#define IMX8ULP_CLK_PXP			11
 #define IMX8ULP_CLK_SFA2		12
 #define IMX8ULP_CLK_GPU2D		13
 #define IMX8ULP_CLK_GPU3D		14
 #define IMX8ULP_CLK_DC_NANO		15
-#define IMX8ULP_CLK_CSI_CLK_UI		16
-#define IMX8ULP_CLK_CSI_CLK_ESC	17
+#define IMX8ULP_CLK_CSI_CLK_UI 		16
+#define IMX8ULP_CLK_CSI_CLK_ESC		17
 #define IMX8ULP_CLK_RGPIOD		18
 #define IMX8ULP_CLK_DMA2_MP		19
 #define IMX8ULP_CLK_DMA2_CH0		20
@@ -241,7 +248,11 @@
 #define IMX8ULP_CLK_DMA2_CH29		49
 #define IMX8ULP_CLK_DMA2_CH30		50
 #define IMX8ULP_CLK_DMA2_CH31		51
+#define IMX8ULP_CLK_MU2_B		52
+#define IMX8ULP_CLK_MU3_B		53
+#define IMX8ULP_CLK_AVD_SIM		54
+#define IMX8ULP_CLK_DSI_TX_ESC		55
 
-#define IMX8ULP_CLK_PCC5_END		52
+#define IMX8ULP_CLK_PCC5_END		56
 
 #endif