diff --git a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
index 7c1dab2..ad264f2 100644
--- a/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8ulp-evk-u-boot.dtsi
@@ -3,7 +3,16 @@
  * Copyright 2021 NXP
  */
 
-&{/soc@0} {
+/ {
+	mu@27020000 {
+		compatible = "fsl,imx8ulp-mu";
+		reg = <0 0x27020000 0 0x10000>;
+		status = "okay";
+		u-boot,dm-spl;
+	};
+};
+
+&soc {
 	u-boot,dm-spl;
 };
 
@@ -23,10 +32,6 @@
 	u-boot,dm-spl;
 };
 
-&s400_mu {
-	u-boot,dm-spl;
-};
-
 &lpuart5 {
 	u-boot,dm-spl;
 };
diff --git a/arch/arm/dts/imx8ulp-evk.dts b/arch/arm/dts/imx8ulp-evk.dts
index da09ff4..f1c6d93 100644
--- a/arch/arm/dts/imx8ulp-evk.dts
+++ b/arch/arm/dts/imx8ulp-evk.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright 2021 NXP
  */
@@ -8,17 +8,31 @@
 #include "imx8ulp.dtsi"
 
 / {
-	model = "FSL i.MX8ULP EVK";
+	model = "NXP i.MX8ULP EVK";
 	compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
 
 	chosen {
 		stdout-path = &lpuart5;
-		bootargs = "console=ttyLP1,115200 earlycon";
 	};
 
-	usdhc2_pwrseq: usdhc2_pwrseq {
-		compatible = "mmc-pwrseq-simple";
-		reset-gpios = <&pcal6408 2 GPIO_ACTIVE_LOW>;
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0 0x80000000>;
+	};
+
+	clock_ext_rmii: clock-ext-rmii {
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+		clock-output-names = "ext_rmii_clk";
+		#clock-cells = <0>;
+	};
+
+	clock_ext_ts: clock-ext-ts {
+		compatible = "fixed-clock";
+		/* External ts clock is 50MHZ from PHY on EVK board. */
+		clock-frequency = <50000000>;
+		clock-output-names = "ext_ts_clk";
+		#clock-cells = <0>;
 	};
 };
 
@@ -30,161 +44,30 @@
 	status = "okay";
 };
 
-&iomuxc1 {
-	pinctrl_lpuart5: lpuart5grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTF14__LPUART5_TX	0x03
-			MX8ULP_PAD_PTF15__LPUART5_RX	0x03
-		>;
-	};
-
-	pinctrl_lpi2c7: lpi2c7grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTE12__LPI2C7_SCL	0x27
-			MX8ULP_PAD_PTE13__LPI2C7_SDA	0x27
-		>;
-	};
-
-	pinctrl_usdhc0: usdhc0grp {
-		fsl,pins = <
-			MX8ULP_PAD_PTD0__SDHC0_RESET_B  0x43
-			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
-			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
-			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
-			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
-			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
-			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
-			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
-			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
-			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
-			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
-			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
-		>;
-	};
-
-	pinctrl_usdhc2_pte: usdhc2ptegrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTE1__SDHC2_D0	0x43
-			MX8ULP_PAD_PTE0__SDHC2_D1	0x43
-			MX8ULP_PAD_PTE5__SDHC2_D2	0x43
-			MX8ULP_PAD_PTE4__SDHC2_D3	0x43
-			MX8ULP_PAD_PTE2__SDHC2_CLK	0x10042
-			MX8ULP_PAD_PTE3__SDHC2_CMD	0x43
-			MX8ULP_PAD_PTE7__PTE7		0x10003
-		>;
-	};
-
-	pinctrl_fec: fecgrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTE14__ENET0_MDIO		0x43
-			MX8ULP_PAD_PTE15__ENET0_MDC	0x43
-			MX8ULP_PAD_PTE18__ENET0_CRS_DV	0x43
-			MX8ULP_PAD_PTE17__ENET0_RXER	0x43
-			MX8ULP_PAD_PTF1__ENET0_RXD0	0x43
-			MX8ULP_PAD_PTE20__ENET0_RXD1	0x43
-			MX8ULP_PAD_PTE16__ENET0_TXEN	0x43
-			MX8ULP_PAD_PTE23__ENET0_TXD0	0x43
-			MX8ULP_PAD_PTE22__ENET0_TXD1	0x43
-			MX8ULP_PAD_PTE19__ENET0_REFCLK	0x10043
-			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x10043
-		>;
-	};
-
-	pinctrl_usbotg0_id: otg0idgrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTF2__USB0_ID	0x10003
-		>;
-	};
-
-	pinctrl_usbotg1_id: otg1idgrp {
-		fsl,pins = <
-			MX8ULP_PAD_PTD23__USB1_ID	0x10003
-		>;
-	};
-};
-
 &usdhc0 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-names = "default", "sleep";
 	pinctrl-0 = <&pinctrl_usdhc0>;
 	pinctrl-1 = <&pinctrl_usdhc0>;
-	pinctrl-2 = <&pinctrl_usdhc0>;
-	bus-width = <8>;
-	non-removable;
-	status = "okay";
-};
-
-&usdhc2 {
-	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
-	pinctrl-0 = <&pinctrl_usdhc2_pte>;
-	pinctrl-1 = <&pinctrl_usdhc2_pte>;
-	pinctrl-2 = <&pinctrl_usdhc2_pte>;
-	pinctrl-3 = <&pinctrl_usdhc2_pte>;
-	mmc-pwrseq = <&usdhc2_pwrseq>;
-	max-frequency = <100000000>;
-	bus-width = <4>;
-	keep-power-in-suspend;
 	non-removable;
-	wakeup-source;
-	status = "okay";
-
-	wifi_wake_host {
-		compatible = "nxp,wifi-wake-host";
-		interrupt-parent = <&gpioe>;
-		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
-		interrupt-names = "host-wake";
-	};
-};
-
-&lpi2c7 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	clock-frequency = <100000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_lpi2c7>;
-	status = "okay";
-
-	pcal6408: gpio@21 {
-		compatible = "ti,tca6408";
-		reg = <0x21>;
-		gpio-controller;
-		#gpio-cells = <2>;
-	};
-};
-
-&flexspi0 {
-	status = "okay";
-
-	flash0: atxp032@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <66000000>;
-	};
-};
-
-&flexspi2 {
+	bus-width = <8>;
 	status = "okay";
-
-	flash1: mt35xu512aba@0 {
-		reg = <0>;
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "jedec,spi-nor";
-		spi-max-frequency = <29000000>;
-		spi-nor,ddr-quad-read-dummy = <8>;
-	};
 };
 
 &fec {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_fec>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_enet>;
+	pinctrl-1 = <&pinctrl_enet>;
+	clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+		 <&pcc4 IMX8ULP_CLK_ENET>,
+		 <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>,
+		 <&clock_ext_rmii>;
+	clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+	assigned-clocks = <&cgc1 IMX8ULP_CLK_ENET_TS_SEL>;
+	assigned-clock-parents = <&clock_ext_ts>;
 	phy-mode = "rmii";
 	phy-handle = <&ethphy>;
 	status = "okay";
 
-	phy-reset-gpios = <&pcal6408 4 GPIO_ACTIVE_LOW>;
-
 	mdio {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -196,28 +79,43 @@
 	};
 };
 
-&usbotg0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg0_id>;
-	srp-disable;
-	hnp-disable;
-	adp-disable;
-	status = "okay";
-};
-
-&usbphy0 {
-	fsl,tx-d-cal = <88>;
-};
+&iomuxc1 {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX8ULP_PAD_PTE15__ENET0_MDC     0x43
+			MX8ULP_PAD_PTE14__ENET0_MDIO    0x43
+			MX8ULP_PAD_PTE17__ENET0_RXER    0x43
+			MX8ULP_PAD_PTE18__ENET0_CRS_DV  0x43
+			MX8ULP_PAD_PTF1__ENET0_RXD0     0x43
+			MX8ULP_PAD_PTE20__ENET0_RXD1    0x43
+			MX8ULP_PAD_PTE16__ENET0_TXEN    0x43
+			MX8ULP_PAD_PTE23__ENET0_TXD0    0x43
+			MX8ULP_PAD_PTE22__ENET0_TXD1    0x43
+			MX8ULP_PAD_PTE19__ENET0_REFCLK  0x43
+			MX8ULP_PAD_PTF10__ENET0_1588_CLKIN 0x43
+		>;
+	};
 
-&usbotg1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_usbotg1_id>;
-	srp-disable;
-	hnp-disable;
-	adp-disable;
-	status = "okay";
-};
+	pinctrl_lpuart5: lpuart5grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTF14__LPUART5_TX	0x3
+			MX8ULP_PAD_PTF15__LPUART5_RX	0x3
+		>;
+	};
 
-&usbphy1 {
-	fsl,tx-d-cal = <88>;
+	pinctrl_usdhc0: usdhc0grp {
+		fsl,pins = <
+			MX8ULP_PAD_PTD1__SDHC0_CMD	0x43
+			MX8ULP_PAD_PTD2__SDHC0_CLK	0x10042
+			MX8ULP_PAD_PTD10__SDHC0_D0	0x43
+			MX8ULP_PAD_PTD9__SDHC0_D1	0x43
+			MX8ULP_PAD_PTD8__SDHC0_D2	0x43
+			MX8ULP_PAD_PTD7__SDHC0_D3	0x43
+			MX8ULP_PAD_PTD6__SDHC0_D4	0x43
+			MX8ULP_PAD_PTD5__SDHC0_D5	0x43
+			MX8ULP_PAD_PTD4__SDHC0_D6	0x43
+			MX8ULP_PAD_PTD3__SDHC0_D7	0x43
+			MX8ULP_PAD_PTD11__SDHC0_DQS	0x10042
+		>;
+	};
 };
diff --git a/arch/arm/dts/imx8ulp-pinfunc.h b/arch/arm/dts/imx8ulp-pinfunc.h
index c21c3b6..b204ac7 100644
--- a/arch/arm/dts/imx8ulp-pinfunc.h
+++ b/arch/arm/dts/imx8ulp-pinfunc.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: GPL-2.0+ OR MIT */
 /*
- * Copyright 2020 NXP
+ * Copyright 2021 NXP
  */
 
 #ifndef __DTS_IMX8ULP_PINFUNC_H
diff --git a/arch/arm/dts/imx8ulp.dtsi b/arch/arm/dts/imx8ulp.dtsi
index d3b16bd..06ce5f1 100644
--- a/arch/arm/dts/imx8ulp.dtsi
+++ b/arch/arm/dts/imx8ulp.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
  * Copyright 2021 NXP
  */
@@ -6,6 +6,8 @@
 #include <dt-bindings/clock/imx8ulp-clock.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/imx8ulp-power.h>
+
 #include "imx8ulp-pinfunc.h"
 
 / {
@@ -14,49 +16,29 @@
 	#size-cells = <2>;
 
 	aliases {
+		ethernet0 = &fec;
 		gpio0 = &gpiod;
 		gpio1 = &gpioe;
 		gpio2 = &gpiof;
-		serial0 = &lpuart5;
 		mmc0 = &usdhc0;
 		mmc1 = &usdhc1;
 		mmc2 = &usdhc2;
-		spi0 = &flexspi0;
-		spi2 = &flexspi2;
-		ethernet0 = &fec;
-		i2c7 = &lpi2c7;
-		usbphy0 = &usbphy0;
-		usb0 = &usbotg0;
-		usbphy1 = &usbphy1;
-		usb1 = &usbotg1;
+		serial0 = &lpuart4;
+		serial1 = &lpuart5;
+		serial2 = &lpuart6;
+		serial3 = &lpuart7;
 	};
 
-	cpus: cpus {
+	cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
 
-		idle-states {
-			entry-method = "psci";
-
-			CPU_SLEEP: cpu-sleep {
-				compatible = "arm,idle-state";
-				arm,psci-suspend-param = <0x0010033>;
-				local-timer-stop;
-				entry-latency-us = <1000>;
-				exit-latency-us = <700>;
-				min-residency-us = <2700>;
-				wakeup-latency-us = <1500>;
-			};
-		};
-
-		/* We have 1 clusters with 4 Cortex-A35 cores */
 		A35_0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a35";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
 			next-level-cache = <&A35_L2>;
-			clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
 		};
 
 		A35_1: cpu@1 {
@@ -65,43 +47,11 @@
 			reg = <0x0 0x1>;
 			enable-method = "psci";
 			next-level-cache = <&A35_L2>;
-			clocks = <&cgc1 IMX8ULP_CLK_A35_DIV>;
 		};
 
 		A35_L2: l2-cache0 {
 			compatible = "cache";
 		};
-	};
-
-	a35_opp_table: opp-table {
-		compatible = "operating-points-v2";
-		opp-shared;
-
-		opp-504000000 {
-			opp-hz = /bits/ 64 <504000000>;
-			opp-microvolt = <800000>;
-			clock-latency-ns = <150000>;
-		};
-
-		opp-744000000 {
-			opp-hz = /bits/ 64 <744000000>;
-			opp-microvolt = <900000>;
-			clock-latency-ns = <150000>;
-		};
-
-		opp-1008000000 {
-			opp-hz = /bits/ 64 <1008000000>;
-			opp-microvolt = <1000000>;
-			clock-latency-ns = <150000>;
-			opp-suspend;
-		};
-	};
-
-	s400_mu: mu@27020000 {
-		u-boot,dm-spl;
-		compatible = "fsl,imx8ulp-mu";
-		reg = <0 0x27020000 0 0x10000>;
-		status = "okay";
 	};
 
 	gic: interrupt-controller@2d400000 {
@@ -113,6 +63,14 @@
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	pmu {
+		compatible = "arm,cortex-a35-pmu";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 7
+			     (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+		interrupt-affinity = <&A35_0>, <&A35_1>;
+	};
+
 	psci {
 		compatible = "arm,psci-1.0";
 		method = "smc";
@@ -154,7 +112,7 @@
 		#clock-cells = <0>;
 	};
 
-	sram@0x2201f000 {
+	sram@2201f000 {
 		compatible = "mmio-sram";
 		reg = <0x0 0x2201f000 0x0 0x1000>;
 
@@ -162,10 +120,9 @@
 		#size-cells = <1>;
 		ranges = <0 0x0 0x2201f000 0x1000>;
 
-		/* TODO: split or unify */
-		scmi_pd: scmi_pd@0 {
+		scmi_buf: scmi-sram-section@0 {
 			compatible = "arm,scmi-shmem";
-			reg = <0x0 0x200>;
+			reg = <0x0 0x400>;
 		};
 	};
 
@@ -175,41 +132,31 @@
 			arm,smc-id = <0xc20000fe>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			shmem = <&scmi_pd>;
+			shmem = <&scmi_buf>;
 
 			scmi_devpd: protocol@11 {
 				reg = <0x11>;
 				#power-domain-cells = <1>;
 			};
 
-			scmi_perf: protocol@13 {
-				reg = <0x13>;
+			scmi_sensor: protocol@15 {
+				reg = <0x15>;
+				#thermal-sensor-cells = <1>;
 			};
 		};
 	};
 
-	soc@0 {
+	soc: soc@0 {
 		compatible = "simple-bus";
 		#address-cells = <1>;
 		#size-cells = <1>;
-		ranges = <0x0 0x0 0x0 0x80000000>;
+		ranges = <0x0 0x0 0x0 0x40000000>;
 
-		per_bridge0: bus@28000000 {
-			compatible = "simple-bus";
-			reg = <0x28000000 0x800000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			flexspi0: flexspi@28039000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "nxp,imx8ulp-fspi";
-				reg = <0x28039000 0x10000>,
-					<0x04000000 0x7ffffff>;
-				reg-names = "fspi_base", "fspi_mmap";
-				status = "disabled";
-			};
+		s4muap: mailbox@27020000 {
+			compatible = "fsl,imx8ulp-mu-s4";
+			reg = <0x27020000 0x10000>;
+			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+			#mbox-cells = <2>;
 		};
 
 		per_bridge3: bus@29000000 {
@@ -219,127 +166,36 @@
 			#size-cells = <1>;
 			ranges;
 
-			edma1: dma-controller@29010000 {
-				compatible = "fsl,imx8ulp-edma";
-				reg = <0x29010000 0x10000>,
-				      <0x29020000 0x10000>, <0x29030000 0x10000>,
-				      <0x29040000 0x10000>, <0x29050000 0x10000>,
-				      <0x29060000 0x10000>, <0x29070000 0x10000>,
-				      <0x29080000 0x10000>, <0x29090000 0x10000>,
-				      <0x290a0000 0x10000>, <0x290b0000 0x10000>,
-				      <0x290c0000 0x10000>, <0x290d0000 0x10000>,
-				      <0x290e0000 0x10000>, <0x290f0000 0x10000>,
-				      <0x29100000 0x10000>, <0x29110000 0x10000>,
-				      <0x29120000 0x10000>, <0x29130000 0x10000>,
-				      <0x29140000 0x10000>, <0x29150000 0x10000>,
-				      <0x29160000 0x10000>, <0x29170000 0x10000>,
-				      <0x29180000 0x10000>, <0x29190000 0x10000>,
-				      <0x291a0000 0x10000>, <0x291b0000 0x10000>,
-				      <0x291c0000 0x10000>, <0x291d0000 0x10000>,
-				      <0x291e0000 0x10000>, <0x291f0000 0x10000>,
-				      <0x29200000 0x10000>, <0x29210000 0x10000>;
-				#dma-cells = <3>;
-				dma-channels = <32>;
-				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "edma1-chan0-tx", "edma1-chan1-tx",
-						  "edma1-chan2-tx", "edma1-chan3-tx",
-						  "edma1-chan4-tx", "edma1-chan5-tx",
-						  "edma1-chan6-tx", "edma1-chan7-tx",
-						  "edma1-chan8-tx", "edma1-chan9-tx",
-						  "edma1-chan10-tx", "edma1-chan11-tx",
-						  "edma1-chan12-tx", "edma1-chan13-tx",
-						  "edma1-chan14-tx", "edma1-chan15-tx",
-						  "edma1-chan16-tx", "edma1-chan17-tx",
-						  "edma1-chan18-tx", "edma1-chan19-tx",
-						  "edma1-chan20-tx", "edma1-chan21-tx",
-						  "edma1-chan22-tx", "edma1-chan23-tx",
-						  "edma1-chan24-tx", "edma1-chan25-tx",
-						  "edma1-chan26-tx", "edma1-chan27-tx",
-						  "edma1-chan28-tx", "edma1-chan29-tx",
-						  "edma1-chan30-tx", "edma1-chan31-tx";
-				clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>,
-					<&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>;
-				clock-names = "edma-mp-clk",
-						"edma1-chan0-clk", "edma1-chan1-clk",
-						"edma1-chan2-clk", "edma1-chan3-clk",
-						"edma1-chan4-clk", "edma1-chan5-clk",
-						"edma1-chan6-clk", "edma1-chan7-clk",
-						"edma1-chan8-clk", "edma1-chan9-clk",
-						"edma1-chan10-clk", "edma1-chan11-clk",
-						"edma1-chan12-clk", "edma1-chan13-clk",
-						"edma1-chan14-clk", "edma1-chan15-clk",
-						"edma1-chan16-clk", "edma1-chan17-clk",
-						"edma1-chan18-clk", "edma1-chan19-clk",
-						"edma1-chan20-clk", "edma1-chan21-clk",
-						"edma1-chan22-clk", "edma1-chan23-clk",
-						"edma1-chan24-clk", "edma1-chan25-clk",
-						"edma1-chan26-clk", "edma1-chan27-clk",
-						"edma1-chan28-clk", "edma1-chan29-clk",
-						"edma1-chan30-clk", "edma1-chan31-clk";
-				status = "okay";
+			mu: mailbox@29220000 {
+				compatible = "fsl,imx8ulp-mu";
+				reg = <0x29220000 0x10000>;
+				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+				#mbox-cells = <2>;
+				status = "disabled";
 			};
 
+			mu3: mailbox@29230000 {
+				compatible = "fsl,imx8ulp-mu";
+				reg = <0x29230000 0x10000>;
+				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_MU3_A>;
+				#mbox-cells = <2>;
+				status = "disabled";
+			};
+
 			wdog3: watchdog@292a0000 {
 				compatible = "fsl,imx8ulp-wdt", "fsl,imx7ulp-wdt";
 				reg = <0x292a0000 0x10000>;
 				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
 				assigned-clocks = <&pcc3 IMX8ULP_CLK_WDOG3>;
-				assigned-clocks-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SOSC_DIV2>;
 				timeout-sec = <40>;
 			};
 
 			cgc1: clock-controller@292c0000 {
 				compatible = "fsl,imx8ulp-cgc1";
 				reg = <0x292c0000 0x10000>;
-				clocks = <&rosc>, <&sosc>, <&frosc>, <&lposc>;
-				clock-names = "rosc", "sosc", "frosc", "lposc";
 				#clock-cells = <1>;
 			};
 
@@ -347,6 +203,7 @@
 				compatible = "fsl,imx8ulp-pcc3";
 				reg = <0x292d0000 0x10000>;
 				#clock-cells = <1>;
+				#reset-cells = <1>;
 			};
 
 			tpm5: tpm@29340000 {
@@ -356,8 +213,35 @@
 				clocks = <&pcc3 IMX8ULP_CLK_TPM5>,
 					 <&pcc3 IMX8ULP_CLK_TPM5>;
 				clock-names = "ipg", "per";
+				status = "disabled";
 			};
 
+			lpi2c4: i2c@29370000 {
+				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x29370000 0x10000>;
+				interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>,
+					 <&pcc3 IMX8ULP_CLK_LPI2C4>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C4>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
+				status = "disabled";
+			};
+
+			lpi2c5: i2c@29380000 {
+				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
+				reg = <0x29380000 0x10000>;
+				interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>,
+					 <&pcc3 IMX8ULP_CLK_LPI2C5>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPI2C5>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
+				status = "disabled";
+			};
+
 			lpuart4: serial@29390000 {
 				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x29390000 0x1000>;
@@ -370,10 +254,41 @@
 			lpuart5: serial@293a0000 {
 				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
 				reg = <0x293a0000 0x1000>;
+				interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc3 IMX8ULP_CLK_LPUART5>;
 				clock-names = "ipg";
 				status = "disabled";
 			};
+
+			lpspi4: spi@293b0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
+				reg = <0x293b0000 0x10000>;
+				interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>,
+					 <&pcc3 IMX8ULP_CLK_LPSPI4>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI4>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
+				status = "disabled";
+			};
+
+			lpspi5: spi@293c0000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8ulp-spi", "fsl,imx7ulp-spi";
+				reg = <0x293c0000 0x10000>;
+				interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>,
+					 <&pcc3 IMX8ULP_CLK_LPSPI5>;
+				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc3 IMX8ULP_CLK_LPSPI5>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
+				status = "disabled";
+			};
 		};
 
 		per_bridge4: bus@29800000 {
@@ -387,77 +302,84 @@
 				compatible = "fsl,imx8ulp-pcc4";
 				reg = <0x29800000 0x10000>;
 				#clock-cells = <1>;
+				#reset-cells = <1>;
 			};
 
-			lpi2c6: lpi2c6@29840000 {
+			lpi2c6: i2c@29840000 {
 				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x29840000 0x10000>;
 				interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>,
 					 <&pcc4 IMX8ULP_CLK_LPI2C6>;
 				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C6>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
 				status = "disabled";
 			};
 
-			lpi2c7: lpi2c7@29850000 {
+			lpi2c7: i2c@29850000 {
 				compatible = "fsl,imx8ulp-lpi2c", "fsl,imx7ulp-lpi2c";
 				reg = <0x29850000 0x10000>;
 				interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>,
 					 <&pcc4 IMX8ULP_CLK_LPI2C7>;
 				clock-names = "per", "ipg";
+				assigned-clocks = <&pcc4 IMX8ULP_CLK_LPI2C7>;
+				assigned-clock-parents = <&cgc1 IMX8ULP_CLK_FROSC_DIV2>;
+				assigned-clock-rates = <48000000>;
 				status = "disabled";
 			};
 
-			flexspi2: flexspi@29810000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "nxp,imx8ulp-fspi";
-				reg = <0x29810000 0x10000>,
-					<0x60000000 0xfffffff>;
-				reg-names = "fspi_base", "fspi_mmap";
+			lpuart6: serial@29860000 {
+				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x29860000 0x1000>;
+				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc4 IMX8ULP_CLK_LPUART6>;
+				clock-names = "ipg";
 				status = "disabled";
 			};
 
-			flexspi2_nand: flexspi2_nand@29810000 {
-				#address-cells = <1>;
-				#size-cells = <0>;
-				compatible = "fsl,imx8-fspi-nand";
-				reg = <0x29810000 0x10000>, <0x60000000 0x10000000>;
-				reg-names = "FlexSPI", "FlexSPI-memory";
+			lpuart7: serial@29870000 {
+				compatible = "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
+				reg = <0x29870000 0x1000>;
+				interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&pcc4 IMX8ULP_CLK_LPUART7>;
+				clock-names = "ipg";
 				status = "disabled";
 			};
 
 			iomuxc1: pinctrl@298c0000 {
 				compatible = "fsl,imx8ulp-iomuxc1";
 				reg = <0x298c0000 0x10000>;
-				fsl,mux_mask = <0xf00>;
 			};
 
 			usdhc0: mmc@298d0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
+				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 				reg = <0x298d0000 0x10000>;
 				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
-					 <&cgc1 IMX8ULP_CLK_DUMMY>,
+				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+					 <&cgc1 IMX8ULP_CLK_XBAR_AD_DIVPLAT>,
 					 <&pcc4 IMX8ULP_CLK_USDHC0>;
 				clock-names = "ipg", "ahb", "per";
+				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC0>;
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
 
 			usdhc1: mmc@298e0000 {
-				compatible = "fsl,imx8ulp-usdhc", "fsl,imx7ulp-usdhc";
+				compatible = "fsl,imx8ulp-usdhc", "fsl,imx8mm-usdhc";
 				reg = <0x298e0000 0x10000>;
 				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&cgc1 IMX8ULP_CLK_DUMMY>,
-					 <&cgc1 IMX8ULP_CLK_DUMMY>,
+				clocks = <&cgc1 IMX8ULP_CLK_XBAR_DIVBUS>,
+					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
 					 <&pcc4 IMX8ULP_CLK_USDHC1>;
 				clock-names = "ipg", "ahb", "per";
+				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC1>;
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
@@ -470,117 +392,50 @@
 					 <&cgc1 IMX8ULP_CLK_NIC_PER_DIVPLAT>,
 					 <&pcc4 IMX8ULP_CLK_USDHC2>;
 				clock-names = "ipg", "ahb", "per";
-				assigned-clocks = <&cgc1 IMX8ULP_CLK_SPLL3_PFD2>, <&pcc4 IMX8ULP_CLK_USDHC2>;
-				assigned-clock-parents = <0>, <&cgc1 IMX8ULP_CLK_SPLL3_PFD2_DIV1>;
-				assigned-clock-rates = <396000000>, <396000000>;
+				power-domains = <&scmi_devpd IMX8ULP_PD_USDHC2_USB1>;
 				fsl,tuning-start-tap = <20>;
-				fsl,tuning-step= <2>;
+				fsl,tuning-step = <2>;
 				bus-width = <4>;
 				status = "disabled";
 			};
 
-			usbotg0: usb@29900000 {
-				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
-					"fsl,imx27-usb";
-				reg = <0x29900000 0x200>;
-				interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_USB0>;
-				fsl,usbphy = <&usbphy0>;
-				fsl,usbmisc = <&usbmisc0 0>;
-				ahb-burst-config = <0x0>;
-				tx-burst-size-dword = <0x8>;
-				rx-burst-size-dword = <0x8>;
-				status = "disabled";
-			};
-
-			usbmisc0: usbmisc@29900200 {
-				#index-cells = <1>;
-				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
-					"fsl,imx6q-usbmisc";
-				reg = <0x29900200 0x200>;
-			};
-
-			usbphy0: usbphy@29910000 {
-				compatible = "fsl,imx8ulp-usbphy",
-					"fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
-				reg = <0x29910000 0x1000>;
-				interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_USB0_PHY>;
-			};
-
-			usbotg1: usb@29920000 {
-				compatible = "fsl,imx8ulp-usb", "fsl,imx7ulp-usb",
-					"fsl,imx27-usb";
-				reg = <0x29920000 0x200>;
-				interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_USB1>;
-				fsl,usbphy = <&usbphy1>;
-				fsl,usbmisc = <&usbmisc1 0>;
-				ahb-burst-config = <0x0>;
-				tx-burst-size-dword = <0x8>;
-				rx-burst-size-dword = <0x8>;
-				status = "disabled";
-			};
-
-			usbmisc1: usbmisc@29920200 {
-				#index-cells = <1>;
-				compatible = "fsl,imx8ulp-usbmisc", "fsl,imx7ulp-usbmisc",
-					"fsl,imx6q-usbmisc";
-				reg = <0x29920200 0x200>;
-			};
-
-			usbphy1: usbphy@29930000 {
-				compatible = "fsl,imx8ulp-usbphy",
-					"fsl,imx7ulp-usbphy", "fsl,imx23-usbphy";
-				reg = <0x29930000 0x1000>;
-				interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_USB1_PHY>;
-			};
-
 			fec: ethernet@29950000 {
-				compatible = "fsl,imx8ulp-fec", "fsl,imx6sx-fec";
+				compatible = "fsl,imx8ulp-fec", "fsl,imx6ul-fec", "fsl,imx6q-fec";
 				reg = <0x29950000 0x10000>;
 				interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&pcc4 IMX8ULP_CLK_ENET>,
-					 <&pcc4 IMX8ULP_CLK_ENET>,
-					 <&cgc1 IMX8ULP_CLK_ENETSTAMP_SEL>,
-					 <&pcc4 IMX8ULP_CLK_ENET>,
-					 <&pcc4 IMX8ULP_CLK_ENET>;
-				clock-names = "ipg", "ahb", "ptp",
-					      "enet_clk_ref", "enet_out";
-				fsl,num-tx-queues = <3>;
-				fsl,num-rx-queues = <3>;
+				interrupt-names = "int0";
+				fsl,num-tx-queues = <1>;
+				fsl,num-rx-queues = <1>;
 				status = "disabled";
 			};
-
 		};
 
-		gpioe: gpio@2d000000 {
-			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
-			reg = <0x2d000080 0x1000 0x2d000040 0x40>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
-				 <&pcc4 IMX8ULP_CLK_PCTLE>;
-			clock-names = "gpio", "port";
-			gpio-ranges = <&iomuxc1 0 32 24>;
+		gpioe: gpio@2d000080 {
+				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+				reg = <0x2d000080 0x1000>, <0x2d000040 0x40>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>,
+					 <&pcc4 IMX8ULP_CLK_PCTLE>;
+				clock-names = "gpio", "port";
+				gpio-ranges = <&iomuxc1 0 32 24>;
 		};
 
-		gpiof: gpio@2d010000 {
-			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
-			reg = <0x2d010080 0x1000 0x2d010040 0x40>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
-			interrupt-controller;
-			#interrupt-cells = <2>;
-			clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
-				 <&pcc4 IMX8ULP_CLK_PCTLF>;
-			clock-names = "gpio", "port";
-			gpio-ranges = <&iomuxc1 0 64 24>;
+		gpiof: gpio@2d010080 {
+				compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+				reg = <0x2d010080 0x1000>, <0x2d010040 0x40>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>,
+					 <&pcc4 IMX8ULP_CLK_PCTLF>;
+				clock-names = "gpio", "port";
+				gpio-ranges = <&iomuxc1 0 64 32>;
 		};
 
 		per_bridge5: bus@2d800000 {
@@ -590,117 +445,9 @@
 			#size-cells = <1>;
 			ranges;
 
-			edma2: dma-controller@2d800000 {
-				compatible = "fsl,imx8ulp-edma";
-				reg = <0x2d800000 0x10000>,
-				      <0x2d810000 0x10000>, <0x2d820000 0x10000>,
-				      <0x2d830000 0x10000>, <0x2d840000 0x10000>,
-				      <0x2d850000 0x10000>, <0x2d860000 0x10000>,
-				      <0x2d870000 0x10000>, <0x2d880000 0x10000>,
-				      <0x2d890000 0x10000>, <0x2d8a0000 0x10000>,
-				      <0x2d8b0000 0x10000>, <0x2d8c0000 0x10000>,
-				      <0x2d8d0000 0x10000>, <0x2d8e0000 0x10000>,
-				      <0x2d8f0000 0x10000>, <0x2d900000 0x10000>,
-				      <0x2d910000 0x10000>, <0x2d920000 0x10000>,
-				      <0x2d930000 0x10000>, <0x2d940000 0x10000>,
-				      <0x2d950000 0x10000>, <0x2d960000 0x10000>,
-				      <0x2d970000 0x10000>, <0x2d980000 0x10000>,
-				      <0x2d990000 0x10000>, <0x2d9a0000 0x10000>,
-				      <0x2d9b0000 0x10000>, <0x2d9c0000 0x10000>,
-				      <0x2d9d0000 0x10000>, <0x2d9e0000 0x10000>,
-				      <0x2d9f0000 0x10000>, <0x2da00000 0x10000>;
-				#dma-cells = <3>;
-				dma-channels = <32>;
-				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "edma2-chan0-tx", "edma2-chan1-tx",
-						  "edma2-chan2-tx", "edma2-chan3-tx",
-						  "edma2-chan4-tx", "edma2-chan5-tx",
-						  "edma2-chan6-tx", "edma2-chan7-tx",
-						  "edma2-chan8-tx", "edma2-chan9-tx",
-						  "edma2-chan10-tx", "edma2-chan11-tx",
-						  "edma2-chan12-tx", "edma2-chan13-tx",
-						  "edma2-chan14-tx", "edma2-chan15-tx",
-						  "edma2-chan16-tx", "edma2-chan17-tx",
-						  "edma2-chan18-tx", "edma2-chan19-tx",
-						  "edma2-chan20-tx", "edma2-chan21-tx",
-						  "edma2-chan22-tx", "edma2-chan23-tx",
-						  "edma2-chan24-tx", "edma2-chan25-tx",
-						  "edma2-chan26-tx", "edma2-chan27-tx",
-						  "edma2-chan28-tx", "edma2-chan29-tx",
-						  "edma2-chan30-tx", "edma2-chan31-tx";
-				clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>,
-					<&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>;
-				clock-names = "edma-mp-clk",
-						"edma2-chan0-clk", "edma2-chan1-clk",
-						"edma2-chan2-clk", "edma2-chan3-clk",
-						"edma2-chan4-clk", "edma2-chan5-clk",
-						"edma2-chan6-clk", "edma2-chan7-clk",
-						"edma2-chan8-clk", "edma2-chan9-clk",
-						"edma2-chan10-clk", "edma2-chan11-clk",
-						"edma2-chan12-clk", "edma2-chan13-clk",
-						"edma2-chan14-clk", "edma2-chan15-clk",
-						"edma2-chan16-clk", "edma2-chan17-clk",
-						"edma2-chan18-clk", "edma2-chan19-clk",
-						"edma2-chan20-clk", "edma2-chan21-clk",
-						"edma2-chan22-clk", "edma2-chan23-clk",
-						"edma2-chan24-clk", "edma2-chan25-clk",
-						"edma2-chan26-clk", "edma2-chan27-clk",
-						"edma2-chan28-clk", "edma2-chan29-clk",
-						"edma2-chan30-clk", "edma2-chan31-clk";
-				status = "okay";
-			};
-
 			cgc2: clock-controller@2da60000 {
 				compatible = "fsl,imx8ulp-cgc2";
 				reg = <0x2da60000 0x10000>;
-				clocks = <&sosc>, <&frosc>;
-				clock-names = "sosc", "frosc";
 				#clock-cells = <1>;
 			};
 
@@ -708,12 +455,13 @@
 				compatible = "fsl,imx8ulp-pcc5";
 				reg = <0x2da70000 0x10000>;
 				#clock-cells = <1>;
+				#reset-cells = <1>;
 			};
 		};
 
-		gpiod: gpio@2e200000 {
-			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
-			reg = <0x2e200080 0x1000 0x2e200040 0x40>;
+		gpiod: gpio@2e200080 {
+			compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio";
+			reg = <0x2e200080 0x1000>, <0x2e200040 0x40>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;