| commit | 4b159041e3269e6e447b2bb131b86c6e961541fb | [log] [tgz] |
|---|---|---|
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | Fri Feb 26 14:21:41 2016 +0900 |
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | Mon Feb 29 03:50:16 2016 +0900 |
| tree | 9c06698652d1ee3e40044d62cdd60f59437d0c9e | |
| parent | a5731889565fcef673b0aaae88b7720582b677a3 [diff] |
ARM: uniphier: merge DDR PHY init code for 3 SoCs Now these three are almost the same. The only difference is the DTPR1 register dependency on the DRAM size, but it can be ignored. (It has already been ignored in PH1-sLD8 and PH1-Pro4.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>