if TARGET_MICROBLAZE_GENERIC

config SYS_BOARD
	default "microblaze-generic"

config SYS_VENDOR
	default "xilinx"

config XILINX_MICROBLAZE0_USE_MSR_INSTR
	int "USE_MSR_INSTR range (0:1)"
	default 0

config XILINX_MICROBLAZE0_USE_PCMP_INSTR
	int "USE_PCMP_INSTR range (0:1)"
	default 0

config XILINX_MICROBLAZE0_USE_BARREL
	int "USE_BARREL range (0:1)"
	default 0

config XILINX_MICROBLAZE0_USE_DIV
	int "USE_DIV range (0:1)"
	default 0

config XILINX_MICROBLAZE0_USE_HW_MUL
	int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
	default 0

config XILINX_MICROBLAZE0_HW_VER
	string "Core version number"
	default "7.10.d"

config XILINX_MICROBLAZE0_FPGA_FAMILY
	string "Targeted FPGA family"
	default "virtex5"
	help
	  This option contains info about the target FPGA architecture
	  (Zynq-7000, UltraScale+ Kintex, etc) that the MicroBlaze soft core is
	  implemented on. It corresponds to the C_FAMILY hdl parameter.

config XILINX_MICROBLAZE0_USR_EXCEP
	bool "MicroBlaze user exception support"
	default y
	help
	  Enable this option in order to install the user exception handler
	  (_exception_handler routine from arch/microblaze/cpu/exception.c) in
	  the exception vector table. The user exception vector is located at
	  C_BASE_VECTORS + 0x8 address.

config XILINX_MICROBLAZE0_DELAY_SLOT_EXCEP
	bool "MicroBlaze delay slot exception support"
	default y
	help
	  Enable this option if the MicroBlaze processor supports exceptions
	  caused by delay slot instructions (processor version >= v5.00). When
	  enabled, the hw exception handler will print a message indicating
	  whether the exception was triggered by a delay slot instruction.

config XILINX_MICROBLAZE0_VECTOR_BASE_ADDR
	hex "Location of MicroBlaze vectors"
	default 0x0
	help
	  Memory address location of the exception vector table. It is
	  configurable via the C_BASE_VECTORS hdl parameter.

config XILINX_MICROBLAZE0_USE_WDC
	bool "MicroBlaze wdc instruction support"
	default y
	help
	  Enable this option if the MicroBlaze processor is configured with
	  support for the "wdc" (Write to Data Cache) instruction.

config SPL_XILINX_MICROBLAZE0_USE_WDC
	bool
	default XILINX_MICROBLAZE0_USE_WDC

config XILINX_MICROBLAZE0_USE_WIC
	bool "MicroBlaze wic instruction support"
	default y
	help
	  Enable this option if the MicroBlaze processor is configured with
	  support for the "wic" (Write to Instruction Cache) instruction.

config SPL_XILINX_MICROBLAZE0_USE_WIC
	bool
	default XILINX_MICROBLAZE0_USE_WIC

config XILINX_MICROBLAZE0_DCACHE_SIZE
	int "Default data cache size"
	default 32768
	help
	  This fallback size will be used when no dcache info can be found in
	  the device tree, or when the data cache is flushed very early in the
	  boot process, before device tree is available.

config XILINX_MICROBLAZE0_ICACHE_SIZE
	int "Default instruction cache size"
	default 32768
	help
	  This fallback size will be used when no icache info can be found in
	  the device tree, or when the instruction cache is flushed very early
	  in the boot process, before device tree is available.

config XILINX_MICROBLAZE0_PVR
	bool "MicroBlaze PVR support"
	help
	  Enables helper functions and macros needed to manipulate PVR
	  (Processor Version Register) data. Currently, only the microblaze
	  UCLASS_CPU driver makes use of this feature to retrieve CPU info at
	  runtime.

endif