Merge patch series "Enable OSPI boot for j721s2"
Manorit Chawdhry <m-chawdhry@ti.com> says:
The series enables ospi boot for j721s2.
Test logs: https://gist.github.com/manorit2001/6bb91885c608e3a8cb0267ab2c614781
diff --git a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
index 91a82b3..54eb9b4 100644
--- a/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721s2-common-proc-board-u-boot.dtsi
@@ -102,7 +102,9 @@
};
&ospi0 {
- status = "disabled";
+ flash@0 {
+ bootph-all;
+ };
};
&ospi1 {
diff --git a/arch/arm/dts/k3-j721s2-r5.dtsi b/arch/arm/dts/k3-j721s2-r5.dtsi
index eb0df42..dbea6b9 100644
--- a/arch/arm/dts/k3-j721s2-r5.dtsi
+++ b/arch/arm/dts/k3-j721s2-r5.dtsi
@@ -79,3 +79,16 @@
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
+
+&ospi0 {
+ reg = <0x0 0x47040000 0x0 0x100>,
+ <0x0 0x50000000 0x0 0x8000000>;
+};
+
+&fss {
+ /* fss node has 64 bit address regions mapped to it and since the ospi
+ * nodes is being override, override the fss node ranges as well
+ */
+ ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x00068400>,
+ <0x0 0x50000000 0x0 0x50000000 0x0 0x08000000>;
+};
diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig
index 5ed8d00..5c3b52ba 100644
--- a/configs/j721s2_evm_a72_defconfig
+++ b/configs/j721s2_evm_a72_defconfig
@@ -10,6 +10,7 @@
CONFIG_TARGET_J721S2_A72_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
+CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig
index 3c958ca..7413ddd 100644
--- a/configs/j721s2_evm_r5_defconfig
+++ b/configs/j721s2_evm_r5_defconfig
@@ -10,6 +10,7 @@
CONFIG_TARGET_J721S2_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41c76000
+CONFIG_SF_DEFAULT_SPEED=25000000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 982dd25..aea611f 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1804,11 +1804,62 @@
if (ret < 0)
return ret;
#endif
+
write_enable(nor);
- ret = nor->write(nor, addr, page_remain, buf + i);
- if (ret < 0)
- goto write_err;
- written = ret;
+
+ /*
+ * On DTR capable flashes like Micron Xcella the writes cannot
+ * start or end at an odd address in DTR mode. So we need to
+ * append or prepend extra 0xff bytes to make sure the start
+ * address and end address are even.
+ */
+ if (spi_nor_protocol_is_dtr(nor->write_proto) &&
+ ((addr | page_remain) & 1)) {
+ u_char *tmp;
+ size_t extra_bytes = 0;
+
+ tmp = kmalloc(nor->page_size, 0);
+ if (!tmp) {
+ ret = -ENOMEM;
+ goto write_err;
+ }
+
+ /* Prepend a 0xff byte if the start address is odd. */
+ if (addr & 1) {
+ tmp[0] = 0xff;
+ memcpy(tmp + 1, buf + i, page_remain);
+ addr--;
+ page_remain++;
+ extra_bytes++;
+ } else {
+ memcpy(tmp, buf + i, page_remain);
+ }
+
+ /* Append a 0xff byte if the end address is odd. */
+ if ((addr + page_remain) & 1) {
+ tmp[page_remain + extra_bytes] = 0xff;
+ extra_bytes++;
+ page_remain++;
+ }
+
+ ret = nor->write(nor, addr, page_remain, tmp);
+
+ kfree(tmp);
+
+ if (ret < 0)
+ goto write_err;
+
+ /*
+ * We write extra bytes but they are not part of the
+ * original write.
+ */
+ written = ret - extra_bytes;
+ } else {
+ ret = nor->write(nor, addr, page_remain, buf + i);
+ if (ret < 0)
+ goto write_err;
+ written = ret;
+ }
ret = spi_nor_wait_till_ready(nor);
if (ret)