diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c
new file mode 100644
index 0000000..73881ee
--- /dev/null
+++ b/cpu/mpc8260/cpu.c
@@ -0,0 +1,243 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CPU specific code for the MPC8260
+ *
+ * written or collected and sometimes rewritten by
+ * Magnus Damm <damm@bitsmart.com>
+ *
+ * minor modifications by
+ * Wolfgang Denk <wd@denx.de>
+ *
+ * modified for 8260 by
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * added 8260 masks by
+ * Marius Groeger <mag@sysgo.de>
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <mpc8260.h>
+#include <asm/processor.h>
+#include <asm/cpm_8260.h>
+
+int checkcpu (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	ulong clock = gd->cpu_clk;
+	uint pvr = get_pvr ();
+	uint immr, rev, m, k;
+	char buf[32];
+
+	puts ("CPU:   ");
+
+	if (((pvr >> 16) & 0xff) != 0x81)
+		return -1;	/* whoops! not an MPC8260 */
+	rev = pvr & 0xff;
+
+	immr = immap->im_memctl.memc_immr;
+	if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
+		return -1;	/* whoops! someone moved the IMMR */
+
+	printf ("MPC8260 (Rev %02x, Mask ", rev);
+
+	/*
+	 * the bottom 16 bits of the immr are the Part Number and Mask Number
+	 * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
+	 * RISC Microcode Revision Number (13-10).
+	 * For the 8260, Motorola doesn't include the Microcode Revision
+	 * in the mask.
+	 */
+	m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
+	k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
+
+	switch (m) {
+	case 0x0000:
+		printf ("0.2 2J24M");
+		break;
+	case 0x0010:
+		printf ("A.0 K22A");
+		break;
+	case 0x0011:
+		printf ("A.1 1K22A-XC");
+		break;
+	case 0x0001:
+		printf ("B.1 1K23A");
+		break;
+	case 0x0021:
+		printf ("B.2 2K23A-XC");
+		break;
+	case 0x0023:
+		printf ("B.3 3K23A");
+		break;
+	case 0x0024:
+		printf ("C.2 6K23A");
+		break;
+	case 0x0060:
+		printf ("A.0(A) 2K25A");
+		break;
+	default:
+		printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
+		break;
+	}
+
+	printf (") at %s MHz\n", strmhz (buf, clock));
+
+	return 0;
+}
+
+/* ------------------------------------------------------------------------- */
+/* configures a UPM by writing into the UPM RAM array			     */
+/* uses bank 11 and a dummy physical address (=BRx_BA_MSK)		     */
+/* NOTE: the physical address chosen must not overlap into any other area    */
+/* mapped by the memory controller because bank 11 has the lowest priority   */
+
+void upmconfig (uint upm, uint * table, uint size)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8260_t *memctl = &immap->im_memctl;
+	volatile uchar *dummy = (uchar *) BRx_BA_MSK;	/* set all BA bits */
+	uint i;
+
+	/* first set up bank 11 to reference the correct UPM at a dummy address */
+
+	memctl->memc_or11 = ORxU_AM_MSK;	/* set all AM bits */
+
+	switch (upm) {
+
+	case UPMA:
+		memctl->memc_br11 =
+			((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
+			BRx_V;
+		memctl->memc_mamr = MxMR_OP_WARR;
+		break;
+
+	case UPMB:
+		memctl->memc_br11 =
+			((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
+			BRx_V;
+		memctl->memc_mbmr = MxMR_OP_WARR;
+		break;
+
+	case UPMC:
+		memctl->memc_br11 =
+			((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
+			BRx_V;
+		memctl->memc_mcmr = MxMR_OP_WARR;
+		break;
+
+	default:
+		panic ("upmconfig passed invalid UPM number (%u)\n", upm);
+		break;
+
+	}
+
+	/*
+	 * at this point, the dummy address is set up to access the selected UPM,
+	 * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
+	 *
+	 * now we simply load the mdr with each word and poke the dummy address.
+	 * the MAD is incremented on each access.
+	 */
+
+	for (i = 0; i < size; i++) {
+		memctl->memc_mdr = table[i];
+		*dummy = 0;
+	}
+
+	/* now kill bank 11 */
+	memctl->memc_br11 = 0;
+}
+
+/* ------------------------------------------------------------------------- */
+
+int
+do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+	ulong msr, addr;
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+
+	immap->im_clkrst.car_rmr = RMR_CSRE;	/* Checkstop Reset enable */
+
+	/* Interrupts and MMU off */
+	__asm__ __volatile__ ("mfmsr    %0":"=r" (msr):);
+
+	msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
+	__asm__ __volatile__ ("mtmsr    %0"::"r" (msr));
+
+	/*
+	 * Trying to execute the next instruction at a non-existing address
+	 * should cause a machine check, resulting in reset
+	 */
+#ifdef CFG_RESET_ADDRESS
+	addr = CFG_RESET_ADDRESS;
+#else
+	/*
+	 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
+	 * - sizeof (ulong) is usually a valid address. Better pick an address
+	 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
+	 */
+	addr = CFG_MONITOR_BASE - sizeof (ulong);
+#endif
+	((void (*)(void)) addr) ();
+	return 1;
+
+}
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Get timebase clock frequency (like cpu_clk in Hz)
+ *
+ */
+unsigned long get_tbclk (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	ulong tbclk;
+
+	tbclk = (gd->bus_clk + 3L) / 4L;
+
+	return (tbclk);
+}
+
+/* ------------------------------------------------------------------------- */
+
+#if defined(CONFIG_WATCHDOG)
+void watchdog_reset (void)
+{
+	int re_enable = disable_interrupts ();
+
+	reset_8260_watchdog ((immap_t *) CFG_IMMR);
+	if (re_enable)
+		enable_interrupts ();
+}
+#endif /* CONFIG_WATCHDOG */
+
+/* ------------------------------------------------------------------------- */
diff --git a/cpu/mpc8260/interrupts.c b/cpu/mpc8260/interrupts.c
new file mode 100644
index 0000000..d804408
--- /dev/null
+++ b/cpu/mpc8260/interrupts.c
@@ -0,0 +1,383 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 22-Oct-00
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <command.h>
+#include <mpc8260.h>
+#include <mpc8260_irq.h>
+#include <asm/processor.h>
+
+/****************************************************************************/
+
+unsigned decrementer_count;		/* count val for 1e6/HZ microseconds */
+
+struct irq_action {
+	interrupt_handler_t *handler;
+	void *arg;
+	ulong count;
+};
+
+static struct irq_action irq_handlers[NR_IRQS];
+
+static ulong ppc_cached_irq_mask[NR_MASK_WORDS];
+
+/****************************************************************************/
+/* this section was ripped out of arch/ppc/kernel/ppc8260_pic.c in the	    */
+/* Linux/PPC 2.4.x source. There was no copyright notice in that file.	    */
+
+/* The 8260 internal interrupt controller.  It is usually
+ * the only interrupt controller.
+ * There are two 32-bit registers (high/low) for up to 64
+ * possible interrupts.
+ *
+ * Now, the fun starts.....Interrupt Numbers DO NOT MAP
+ * in a simple arithmetic fashion to mask or pending registers.
+ * That is, interrupt 4 does not map to bit position 4.
+ * We create two tables, indexed by vector number, to indicate
+ * which register to use and which bit in the register to use.
+ */
+static u_char irq_to_siureg[] = {
+	1, 1, 1, 1, 1, 1, 1, 1,
+	1, 1, 1, 1, 1, 1, 1, 1,
+	0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0,
+	1, 1, 1, 1, 1, 1, 1, 1,
+	1, 1, 1, 1, 1, 1, 1, 1,
+	0, 0, 0, 0, 0, 0, 0, 0,
+	0, 0, 0, 0, 0, 0, 0, 0
+};
+
+static u_char irq_to_siubit[] = {
+	31, 16, 17, 18, 19, 20, 21, 22,
+	23, 24, 25, 26, 27, 28, 29, 30,
+	29, 30, 16, 17, 18, 19, 20, 21,
+	22, 23, 24, 25, 26, 27, 28, 31,
+	0, 1, 2, 3, 4, 5, 6, 7,
+	8, 9, 10, 11, 12, 13, 14, 15,
+	15, 14, 13, 12, 11, 10, 9, 8,
+	7, 6, 5, 4, 3, 2, 1, 0
+};
+
+static void m8260_mask_irq (unsigned int irq_nr)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	int bit, word;
+	volatile uint *simr;
+
+	bit = irq_to_siubit[irq_nr];
+	word = irq_to_siureg[irq_nr];
+
+	simr = &(immr->im_intctl.ic_simrh);
+	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
+	simr[word] = ppc_cached_irq_mask[word];
+}
+
+static void m8260_unmask_irq (unsigned int irq_nr)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	int bit, word;
+	volatile uint *simr;
+
+	bit = irq_to_siubit[irq_nr];
+	word = irq_to_siureg[irq_nr];
+
+	simr = &(immr->im_intctl.ic_simrh);
+	ppc_cached_irq_mask[word] |= (1 << (31 - bit));
+	simr[word] = ppc_cached_irq_mask[word];
+}
+
+static void m8260_mask_and_ack (unsigned int irq_nr)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	int bit, word;
+	volatile uint *simr, *sipnr;
+
+	bit = irq_to_siubit[irq_nr];
+	word = irq_to_siureg[irq_nr];
+
+	simr = &(immr->im_intctl.ic_simrh);
+	sipnr = &(immr->im_intctl.ic_sipnrh);
+	ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
+	simr[word] = ppc_cached_irq_mask[word];
+	sipnr[word] = 1 << (31 - bit);
+}
+
+static int m8260_get_irq (struct pt_regs *regs)
+{
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	int irq;
+	unsigned long bits;
+
+	/* For MPC8260, read the SIVEC register and shift the bits down
+	 * to get the irq number.         */
+	bits = immr->im_intctl.ic_sivec;
+	irq = bits >> 26;
+	return irq;
+}
+
+/* end of code ripped out of arch/ppc/kernel/ppc8260_pic.c		    */
+/****************************************************************************/
+
+static __inline__ unsigned long get_msr (void)
+{
+	unsigned long msr;
+
+	__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
+
+	return msr;
+}
+
+static __inline__ void set_msr (unsigned long msr)
+{
+	__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
+}
+
+static __inline__ unsigned long get_dec (void)
+{
+	unsigned long val;
+
+	__asm__ __volatile__ ("mfdec %0":"=r" (val):);
+
+	return val;
+}
+
+static __inline__ void set_dec (unsigned long val)
+{
+	__asm__ __volatile__ ("mtdec %0"::"r" (val));
+}
+
+void enable_interrupts (void)
+{
+	set_msr (get_msr () | MSR_EE);
+}
+
+/* returns flag if MSR_EE was set before */
+int disable_interrupts (void)
+{
+	ulong msr = get_msr ();
+
+	set_msr (msr & ~MSR_EE);
+	return ((msr & MSR_EE) != 0);
+}
+
+/****************************************************************************/
+
+int interrupt_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+
+	decrementer_count = (gd->bus_clk / 4) / CFG_HZ;
+
+	/* Initialize the default interrupt mapping priorities */
+	immr->im_intctl.ic_sicr = 0;
+	immr->im_intctl.ic_siprr = 0x05309770;
+	immr->im_intctl.ic_scprrh = 0x05309770;
+	immr->im_intctl.ic_scprrl = 0x05309770;
+
+	/* disable all interrupts and clear all pending bits */
+	immr->im_intctl.ic_simrh = ppc_cached_irq_mask[0] = 0;
+	immr->im_intctl.ic_simrl = ppc_cached_irq_mask[1] = 0;
+	immr->im_intctl.ic_sipnrh = 0xffffffff;
+	immr->im_intctl.ic_sipnrl = 0xffffffff;
+
+	set_dec (decrementer_count);
+
+	set_msr (get_msr () | MSR_EE);
+
+	return (0);
+}
+
+/****************************************************************************/
+
+/*
+ * Handle external interrupts
+ */
+void external_interrupt (struct pt_regs *regs)
+{
+	int irq, unmask = 1;
+
+	irq = m8260_get_irq (regs);
+
+	m8260_mask_and_ack (irq);
+
+	set_msr (get_msr () | MSR_EE);
+
+	if (irq_handlers[irq].handler != NULL)
+		(*irq_handlers[irq].handler) (irq_handlers[irq].arg);
+	else {
+		printf ("\nBogus External Interrupt IRQ %d\n", irq);
+		/*
+		 * turn off the bogus interrupt, otherwise it
+		 * might repeat forever
+		 */
+		unmask = 0;
+	}
+
+	if (unmask)
+		m8260_unmask_irq (irq);
+}
+
+/****************************************************************************/
+
+/*
+ * Install and free an interrupt handler.
+ */
+
+void
+irq_install_handler (int irq, interrupt_handler_t * handler, void *arg)
+{
+	if (irq < 0 || irq >= NR_IRQS) {
+		printf ("irq_install_handler: bad irq number %d\n", irq);
+		return;
+	}
+
+	if (irq_handlers[irq].handler != NULL)
+		printf ("irq_install_handler: 0x%08lx replacing 0x%08lx\n",
+				(ulong) handler, (ulong) irq_handlers[irq].handler);
+
+	irq_handlers[irq].handler = handler;
+	irq_handlers[irq].arg = arg;
+
+	m8260_unmask_irq (irq);
+}
+
+void irq_free_handler (int irq)
+{
+	if (irq < 0 || irq >= NR_IRQS) {
+		printf ("irq_free_handler: bad irq number %d\n", irq);
+		return;
+	}
+
+	m8260_mask_irq (irq);
+
+	irq_handlers[irq].handler = NULL;
+	irq_handlers[irq].arg = NULL;
+}
+
+/****************************************************************************/
+
+volatile ulong timestamp = 0;
+
+/*
+ * timer_interrupt - gets called when the decrementer overflows,
+ * with interrupts disabled.
+ * Trivial implementation - no need to be really accurate.
+ */
+void timer_interrupt (struct pt_regs *regs)
+{
+#if defined(CONFIG_WATCHDOG) || defined(CFG_HYMOD_DBLEDS)
+	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+#endif							/* CONFIG_WATCHDOG */
+
+	/* Restore Decrementer Count */
+	set_dec (decrementer_count);
+
+	timestamp++;
+
+#if defined(CONFIG_WATCHDOG) || \
+    defined(CFG_CMA_LCD_HEARTBEAT) || \
+    defined(CFG_HYMOD_DBLEDS)
+
+	if ((timestamp % CFG_HZ) == 0) {
+#if defined(CFG_CMA_LCD_HEARTBEAT)
+		extern void lcd_heartbeat (void);
+#endif							/* CFG_CMA_LCD_HEARTBEAT */
+#if defined(CFG_HYMOD_DBLEDS)
+		volatile iop8260_t *iop = &immr->im_ioport;
+		static int shift = 0;
+#endif							/* CFG_HYMOD_DBLEDS */
+
+#if defined(CFG_CMA_LCD_HEARTBEAT)
+		lcd_heartbeat ();
+#endif							/* CFG_CMA_LCD_HEARTBEAT */
+
+#if defined(CONFIG_WATCHDOG)
+		reset_8260_watchdog (immr);
+#endif							/* CONFIG_WATCHDOG */
+
+#if defined(CFG_HYMOD_DBLEDS)
+		/* hymod daughter board LEDs */
+		if (++shift > 3)
+			shift = 0;
+		iop->iop_pdatd =
+				(iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
+#endif							/* CFG_HYMOD_DBLEDS */
+	}
+#endif							/* CONFIG_WATCHDOG || CFG_CMA_LCD_HEARTBEAT */
+}
+
+/****************************************************************************/
+
+void reset_timer (void)
+{
+	timestamp = 0;
+}
+
+ulong get_timer (ulong base)
+{
+	return (timestamp - base);
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+/****************************************************************************/
+
+#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
+
+/* ripped this out of ppc4xx/interrupts.c */
+
+/*******************************************************************************
+*
+* irqinfo - print information about PCI devices
+*
+*/
+void
+do_irqinfo (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
+{
+	int irq, re_enable;
+
+	re_enable = disable_interrupts ();
+
+	printf ("\nInterrupt-Information:\n");
+	printf ("Nr  Routine   Arg       Count\n");
+
+	for (irq = 0; irq < 32; irq++)
+		if (irq_handlers[irq].handler != NULL)
+			printf ("%02d  %08lx  %08lx  %ld\n", irq,
+					(ulong) irq_handlers[irq].handler,
+					(ulong) irq_handlers[irq].arg,
+					irq_handlers[irq].count);
+
+	if (re_enable)
+		enable_interrupts ();
+}
+
+#endif							/* CONFIG_COMMANDS & CFG_CMD_IRQ */
diff --git a/cpu/mpc8260/serial_scc.c b/cpu/mpc8260/serial_scc.c
new file mode 100644
index 0000000..ca76302
--- /dev/null
+++ b/cpu/mpc8260/serial_scc.c
@@ -0,0 +1,498 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00.
+ */
+
+/*
+ * Minimal serial functions needed to use one of the SCC ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <asm/cpm_8260.h>
+
+#if defined(CONFIG_CONS_ON_SCC)
+
+#if CONFIG_CONS_INDEX == 1	/* Console on SCC1 */
+
+#define SCC_INDEX		0
+#define PROFF_SCC		PROFF_SCC1
+#define CMXSCR_MASK		(CMXSCR_GR1|CMXSCR_SC1|\
+					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
+#define CMXSCR_VALUE		(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
+#define CPM_CR_SCC_PAGE		CPM_CR_SCC1_PAGE
+#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK
+
+#elif CONFIG_CONS_INDEX == 2	/* Console on SCC2 */
+
+#define SCC_INDEX		1
+#define PROFF_SCC		PROFF_SCC2
+#define CMXSCR_MASK		(CMXSCR_GR2|CMXSCR_SC2|\
+					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
+#define CMXSCR_VALUE		(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
+#define CPM_CR_SCC_PAGE		CPM_CR_SCC2_PAGE
+#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK
+
+#elif CONFIG_CONS_INDEX == 3	/* Console on SCC3 */
+
+#define SCC_INDEX		2
+#define PROFF_SCC		PROFF_SCC3
+#define CMXSCR_MASK		(CMXSCR_GR3|CMXSCR_SC3|\
+					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
+#define CMXSCR_VALUE		(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
+#define CPM_CR_SCC_PAGE		CPM_CR_SCC3_PAGE
+#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK
+
+#elif CONFIG_CONS_INDEX == 4	/* Console on SCC4 */
+
+#define SCC_INDEX		3
+#define PROFF_SCC		PROFF_SCC4
+#define CMXSCR_MASK		(CMXSCR_GR4|CMXSCR_SC4|\
+					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
+#define CMXSCR_VALUE		(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
+#define CPM_CR_SCC_PAGE		CPM_CR_SCC4_PAGE
+#define CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK
+
+#else
+
+#error "console not correctly defined"
+
+#endif
+
+int serial_init (void)
+{
+        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile scc_t *sp;
+	volatile scc_uart_t *up;
+	volatile cbd_t *tbdf, *rbdf;
+	volatile cpm8260_t *cp = &(im->im_cpm);
+	uint	dpaddr;
+
+	/* initialize pointers to SCC */
+
+	sp = (scc_t *) &(im->im_scc[SCC_INDEX]);
+	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
+
+	/* Disable transmitter/receiver.
+	*/
+	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+	/* put the SCC channel into NMSI (non multiplexd serial interface)
+	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
+	 */
+	im->im_cpmux.cmx_scr = (im->im_cpmux.cmx_scr&~CMXSCR_MASK)|CMXSCR_VALUE;
+
+	/* Set up the baud rate generator.
+	*/
+	serial_setbrg ();
+
+	/* Allocate space for two buffer descriptors in the DP ram.
+	 * damm: allocating space after the two buffers for rx/tx data
+	 */
+
+	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
+
+	/* Set the physical address of the host memory buffers in
+	 * the buffer descriptors.
+	 */
+	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
+	rbdf->cbd_bufaddr = (uint) (rbdf+2);
+	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
+	tbdf = rbdf + 1;
+	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
+	tbdf->cbd_sc = BD_SC_WRAP;
+
+	/* Set up the uart parameters in the parameter ram.
+	*/
+	up->scc_genscc.scc_rbase = dpaddr;
+	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
+	up->scc_genscc.scc_rfcr = CPMFCR_EB;
+	up->scc_genscc.scc_tfcr = CPMFCR_EB;
+	up->scc_genscc.scc_mrblr = 1;
+	up->scc_maxidl = 0;
+	up->scc_brkcr = 1;
+	up->scc_parec = 0;
+	up->scc_frmec = 0;
+	up->scc_nosec = 0;
+	up->scc_brkec = 0;
+	up->scc_uaddr1 = 0;
+	up->scc_uaddr2 = 0;
+	up->scc_toseq = 0;
+	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
+	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
+	up->scc_rccm = 0xc0ff;
+
+	/* Mask all interrupts and remove anything pending.
+	*/
+	sp->scc_sccm = 0;
+	sp->scc_scce = 0xffff;
+
+	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
+	*/
+	sp->scc_gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
+	sp->scc_gsmrl = \
+		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
+
+	/* Set CTS flow control, 1 stop bit, 8 bit character length,
+	 * normal async UART mode, no parity
+	 */
+	sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;
+
+	/* execute the "Init Rx and Tx params" CP command.
+	*/
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	cp->cp_cpcr = mk_cr_cmd(CPM_CR_SCC_PAGE, CPM_CR_SCC_SBLOCK,
+					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	/* Enable transmitter/receiver.
+	*/
+	sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
+
+	return (0);
+}
+
+void
+serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CONS_USE_EXTC)
+	m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
+		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
+#else
+	m8260_cpm_setbrg(SCC_INDEX, gd->baudrate);
+#endif
+}
+
+void
+serial_putc(const char c)
+{
+	volatile scc_uart_t	*up;
+	volatile cbd_t		*tbdf;
+        volatile immap_t	*im;
+
+	if (c == '\n')
+		serial_putc ('\r');
+
+        im = (immap_t *)CFG_IMMR;
+	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
+	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
+
+	/* Wait for last character to go.
+	 */
+	while (tbdf->cbd_sc & BD_SC_READY)
+		;
+
+	/* Load the character into the transmit buffer.
+	 */
+	*(volatile char *)tbdf->cbd_bufaddr = c;
+	tbdf->cbd_datlen = 1;
+	tbdf->cbd_sc |= BD_SC_READY;
+}
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int
+serial_getc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile scc_uart_t	*up;
+        volatile immap_t	*im;
+	unsigned char		c;
+
+        im = (immap_t *)CFG_IMMR;
+	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
+	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
+
+	/* Wait for character to show up.
+	 */
+	while (rbdf->cbd_sc & BD_SC_EMPTY)
+		;
+
+	/* Grab the char and clear the buffer again.
+	 */
+	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
+	rbdf->cbd_sc |= BD_SC_EMPTY;
+
+	return (c);
+}
+
+int
+serial_tstc()
+{
+	volatile cbd_t		*rbdf;
+	volatile scc_uart_t	*up;
+        volatile immap_t	*im;
+
+        im = (immap_t *)CFG_IMMR;
+	up = (scc_uart_t *)&im->im_dprambase[PROFF_SCC];
+	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
+
+	return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
+}
+
+#endif	/* CONFIG_CONS_ON_SCC */
+
+#if defined(CONFIG_KGDB_ON_SCC)
+
+#if defined(CONFIG_CONS_ON_SCC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
+#error Whoops! serial console and kgdb are on the same scc serial port
+#endif
+
+#if CONFIG_KGDB_INDEX == 1	/* KGDB Port on SCC1 */
+
+#define KGDB_SCC_INDEX		0
+#define KGDB_PROFF_SCC		PROFF_SCC1
+#define KGDB_CMXSCR_MASK	(CMXSCR_GR1|CMXSCR_SC1|\
+					CMXSCR_RS1CS_MSK|CMXSCR_TS1CS_MSK)
+#define KGDB_CMXSCR_VALUE	(CMXSCR_RS1CS_BRG1|CMXSCR_TS1CS_BRG1)
+#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC1_PAGE
+#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC1_SBLOCK
+
+#elif CONFIG_KGDB_INDEX == 2	/* KGDB Port on SCC2 */
+
+#define KGDB_SCC_INDEX		1
+#define KGDB_PROFF_SCC		PROFF_SCC2
+#define KGDB_CMXSCR_MASK	(CMXSCR_GR2|CMXSCR_SC2|\
+					CMXSCR_RS2CS_MSK|CMXSCR_TS2CS_MSK)
+#define KGDB_CMXSCR_VALUE	(CMXSCR_RS2CS_BRG2|CMXSCR_TS2CS_BRG2)
+#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC2_PAGE
+#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC2_SBLOCK
+
+#elif CONFIG_KGDB_INDEX == 3	/* KGDB Port on SCC3 */
+
+#define KGDB_SCC_INDEX		2
+#define KGDB_PROFF_SCC		PROFF_SCC3
+#define KGDB_CMXSCR_MASK	(CMXSCR_GR3|CMXSCR_SC3|\
+					CMXSCR_RS3CS_MSK|CMXSCR_TS3CS_MSK)
+#define KGDB_CMXSCR_VALUE	(CMXSCR_RS3CS_BRG3|CMXSCR_TS3CS_BRG3)
+#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC3_PAGE
+#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC3_SBLOCK
+
+#elif CONFIG_KGDB_INDEX == 4	/* KGDB Port on SCC4 */
+
+#define KGDB_SCC_INDEX		3
+#define KGDB_PROFF_SCC		PROFF_SCC4
+#define KGDB_CMXSCR_MASK	(CMXSCR_GR4|CMXSCR_SC4|\
+					CMXSCR_RS4CS_MSK|CMXSCR_TS4CS_MSK)
+#define KGDB_CMXSCR_VALUE	(CMXSCR_RS4CS_BRG4|CMXSCR_TS4CS_BRG4)
+#define KGDB_CPM_CR_SCC_PAGE	CPM_CR_SCC4_PAGE
+#define KGDB_CPM_CR_SCC_SBLOCK	CPM_CR_SCC4_SBLOCK
+
+#else
+
+#error "kgdb serial port not correctly defined"
+
+#endif
+
+void
+kgdb_serial_init (void)
+{
+        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile scc_t *sp;
+	volatile scc_uart_t *up;
+	volatile cbd_t *tbdf, *rbdf;
+	volatile cpm8260_t *cp = &(im->im_cpm);
+	uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
+	char *s, *e;
+
+	if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
+		ulong rate = simple_strtoul(s, &e, 10);
+		if (e > s && *e == '\0')
+			speed = rate;
+	}
+
+	/* initialize pointers to SCC */
+
+	sp = (scc_t *) &(im->im_scc[KGDB_SCC_INDEX]);
+	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
+
+	/* Disable transmitter/receiver.
+	*/
+	sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+	/* put the SCC channel into NMSI (non multiplexd serial interface)
+	 * mode and wire the selected SCC Tx and Rx clocks to BRGx (15-15).
+	 */
+	im->im_cpmux.cmx_scr = \
+		(im->im_cpmux.cmx_scr & ~KGDB_CMXSCR_MASK) | KGDB_CMXSCR_VALUE;
+
+	/* Set up the baud rate generator.
+	*/
+#if defined(CONFIG_KGDB_USE_EXTC)
+	m8260_cpm_extcbrg(KGDB_SCC_INDEX, speed,
+		CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
+#else
+	m8260_cpm_setbrg(KGDB_SCC_INDEX, speed);
+#endif
+
+	/* Allocate space for two buffer descriptors in the DP ram.
+	 * damm: allocating space after the two buffers for rx/tx data
+	 */
+
+	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
+
+	/* Set the physical address of the host memory buffers in
+	 * the buffer descriptors.
+	 */
+	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
+	rbdf->cbd_bufaddr = (uint) (rbdf+2);
+	rbdf->cbd_sc = BD_SC_EMPTY | BD_SC_WRAP;
+	tbdf = rbdf + 1;
+	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
+	tbdf->cbd_sc = BD_SC_WRAP;
+
+	/* Set up the uart parameters in the parameter ram.
+	*/
+	up->scc_genscc.scc_rbase = dpaddr;
+	up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
+	up->scc_genscc.scc_rfcr = CPMFCR_EB;
+	up->scc_genscc.scc_tfcr = CPMFCR_EB;
+	up->scc_genscc.scc_mrblr = 1;
+	up->scc_maxidl = 0;
+	up->scc_brkcr = 1;
+	up->scc_parec = 0;
+	up->scc_frmec = 0;
+	up->scc_nosec = 0;
+	up->scc_brkec = 0;
+	up->scc_uaddr1 = 0;
+	up->scc_uaddr2 = 0;
+	up->scc_toseq = 0;
+	up->scc_char1 = up->scc_char2 = up->scc_char3 = up->scc_char4 = 0x8000;
+	up->scc_char5 = up->scc_char6 = up->scc_char7 = up->scc_char8 = 0x8000;
+	up->scc_rccm = 0xc0ff;
+
+	/* Mask all interrupts and remove anything pending.
+	*/
+	sp->scc_sccm = 0;
+	sp->scc_scce = 0xffff;
+
+	/* Set 8 bit FIFO, 16 bit oversampling and UART mode.
+	*/
+	sp->scc_gsmrh = SCC_GSMRH_RFW;	/* 8 bit FIFO */
+	sp->scc_gsmrl = \
+		SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16 | SCC_GSMRL_MODE_UART;
+
+	/* Set CTS flow control, 1 stop bit, 8 bit character length,
+	 * normal async UART mode, no parity
+	 */
+	sp->scc_psmr = SCU_PSMR_FLC | SCU_PSMR_CL;
+
+	/* execute the "Init Rx and Tx params" CP command.
+	*/
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SCC_PAGE, KGDB_CPM_CR_SCC_SBLOCK,
+					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	/* Enable transmitter/receiver.
+	*/
+	sp->scc_gsmrl |= SCC_GSMRL_ENR | SCC_GSMRL_ENT;
+
+	printf("SCC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
+}
+
+void
+putDebugChar(const char c)
+{
+	volatile scc_uart_t	*up;
+	volatile cbd_t		*tbdf;
+        volatile immap_t	*im;
+
+	if (c == '\n')
+		putDebugChar ('\r');
+
+        im = (immap_t *)CFG_IMMR;
+	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
+	tbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_tbase];
+
+	/* Wait for last character to go.
+	 */
+	while (tbdf->cbd_sc & BD_SC_READY)
+		;
+
+	/* Load the character into the transmit buffer.
+	 */
+	*(volatile char *)tbdf->cbd_bufaddr = c;
+	tbdf->cbd_datlen = 1;
+	tbdf->cbd_sc |= BD_SC_READY;
+}
+
+void
+putDebugStr (const char *s)
+{
+	while (*s) {
+		putDebugChar (*s++);
+	}
+}
+
+int
+getDebugChar(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile scc_uart_t	*up;
+        volatile immap_t	*im;
+	unsigned char		c;
+
+        im = (immap_t *)CFG_IMMR;
+	up = (scc_uart_t *)&im->im_dprambase[KGDB_PROFF_SCC];
+	rbdf = (cbd_t *)&im->im_dprambase[up->scc_genscc.scc_rbase];
+
+	/* Wait for character to show up.
+	 */
+	while (rbdf->cbd_sc & BD_SC_EMPTY)
+		;
+
+	/* Grab the char and clear the buffer again.
+	 */
+	c = *(volatile unsigned char *)rbdf->cbd_bufaddr;
+	rbdf->cbd_sc |= BD_SC_EMPTY;
+
+	return (c);
+}
+
+void
+kgdb_interruptible(int yes)
+{
+	return;
+}
+
+#endif	/* CONFIG_KGDB_ON_SCC */
diff --git a/cpu/mpc8260/serial_smc.c b/cpu/mpc8260/serial_smc.c
new file mode 100644
index 0000000..b0e1ce4
--- /dev/null
+++ b/cpu/mpc8260/serial_smc.c
@@ -0,0 +1,462 @@
+/*
+ * (C) Copyright 2000, 2001, 2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Hacked for MPC8260 by Murray.Jensen@cmst.csiro.au, 19-Oct-00, with
+ * changes based on the file arch/ppc/mbxboot/m8260_tty.c from the
+ * Linux/PPC sources (m8260_tty.c had no copyright info in it).
+ */
+
+/*
+ * Minimal serial functions needed to use one of the SMC ports
+ * as serial console interface.
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <asm/cpm_8260.h>
+
+#if defined(CONFIG_CONS_ON_SMC)
+
+#if CONFIG_CONS_INDEX == 1	/* Console on SMC1 */
+
+#define SMC_INDEX		0
+#define PROFF_SMC_BASE		PROFF_SMC1_BASE
+#define PROFF_SMC		PROFF_SMC1
+#define CPM_CR_SMC_PAGE		CPM_CR_SMC1_PAGE
+#define CPM_CR_SMC_SBLOCK	CPM_CR_SMC1_SBLOCK
+#define CMXSMR_MASK		(CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
+#define CMXSMR_VALUE		CMXSMR_SMC1CS_BRG7
+
+#elif CONFIG_CONS_INDEX == 2	/* Console on SMC2 */
+
+#define SMC_INDEX		1
+#define PROFF_SMC_BASE		PROFF_SMC2_BASE
+#define PROFF_SMC		PROFF_SMC2
+#define CPM_CR_SMC_PAGE		CPM_CR_SMC2_PAGE
+#define CPM_CR_SMC_SBLOCK	CPM_CR_SMC2_SBLOCK
+#define CMXSMR_MASK		(CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
+#define CMXSMR_VALUE		CMXSMR_SMC2CS_BRG8
+
+#else
+
+#error "console not correctly defined"
+
+#endif
+
+/* map rs_table index to baud rate generator index */
+static unsigned char brg_map[] = {
+	6,	/* BRG7 for SMC1 */
+	7,	/* BRG8 for SMC2 */
+	0,	/* BRG1 for SCC1 */
+	1,	/* BRG1 for SCC2 */
+	2,	/* BRG1 for SCC3 */
+	3,	/* BRG1 for SCC4 */
+};
+
+int serial_init (void)
+{
+        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile smc_t *sp;
+	volatile smc_uart_t *up;
+	volatile cbd_t *tbdf, *rbdf;
+	volatile cpm8260_t *cp = &(im->im_cpm);
+	uint	dpaddr;
+
+	/* initialize pointers to SMC */
+
+	sp = (smc_t *) &(im->im_smc[SMC_INDEX]);
+	*(ushort *)(&im->im_dprambase[PROFF_SMC_BASE]) = PROFF_SMC;
+	up = (smc_uart_t *)&im->im_dprambase[PROFF_SMC];
+
+	/* Disable transmitter/receiver.
+	*/
+	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+
+	/* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
+
+	/* Allocate space for two buffer descriptors in the DP ram.
+	 * damm: allocating space after the two buffers for rx/tx data
+	 */
+
+	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
+
+	/* Set the physical address of the host memory buffers in
+	 * the buffer descriptors.
+	 */
+	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
+	rbdf->cbd_bufaddr = (uint) (rbdf+2);
+	rbdf->cbd_sc = 0;
+	tbdf = rbdf + 1;
+	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
+	tbdf->cbd_sc = 0;
+
+	/* Set up the uart parameters in the parameter ram.
+	*/
+	up->smc_rbase = dpaddr;
+	up->smc_tbase = dpaddr+sizeof(cbd_t);
+	up->smc_rfcr = CPMFCR_EB;
+	up->smc_tfcr = CPMFCR_EB;
+	up->smc_brklen = 0;
+	up->smc_brkec = 0;
+	up->smc_brkcr = 0;
+
+	/* Set UART mode, 8 bit, no parity, one stop.
+	 * Enable receive and transmit.
+	 */
+	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
+
+	/* Mask all interrupts and remove anything pending.
+	*/
+	sp->smc_smcm = 0;
+	sp->smc_smce = 0xff;
+
+	/* put the SMC channel into NMSI (non multiplexd serial interface)
+	 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
+	 */
+	im->im_cpmux.cmx_smr = (im->im_cpmux.cmx_smr&~CMXSMR_MASK)|CMXSMR_VALUE;
+
+	/* Set up the baud rate generator.
+	*/
+	serial_setbrg ();
+
+	/* Make the first buffer the only buffer.
+	*/
+	tbdf->cbd_sc |= BD_SC_WRAP;
+	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+
+	/* Single character receive.
+	*/
+	up->smc_mrblr = 1;
+	up->smc_maxidl = 0;
+
+	/* Initialize Tx/Rx parameters.
+	*/
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	cp->cp_cpcr = mk_cr_cmd(CPM_CR_SMC_PAGE, CPM_CR_SMC_SBLOCK,
+					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	/* Enable transmitter/receiver.
+	*/
+	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+
+	return (0);
+}
+
+void
+serial_setbrg (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CONS_USE_EXTC)
+	m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
+		CONFIG_CONS_EXTC_RATE, CONFIG_CONS_EXTC_PINSEL);
+#else
+	m8260_cpm_setbrg(brg_map[SMC_INDEX], gd->baudrate);
+#endif
+}
+
+void
+serial_putc(const char c)
+{
+	volatile cbd_t		*tbdf;
+	volatile char		*buf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+
+	if (c == '\n')
+		serial_putc ('\r');
+
+	up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
+
+	tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
+
+	/* Wait for last character to go.
+	*/
+	buf = (char *)tbdf->cbd_bufaddr;
+	while (tbdf->cbd_sc & BD_SC_READY)
+		;
+
+	*buf = c;
+	tbdf->cbd_datlen = 1;
+	tbdf->cbd_sc |= BD_SC_READY;
+}
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
+
+int
+serial_getc(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile unsigned char	*buf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	unsigned char		c;
+
+	up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
+
+	rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
+
+	/* Wait for character to show up.
+	*/
+	buf = (unsigned char *)rbdf->cbd_bufaddr;
+	while (rbdf->cbd_sc & BD_SC_EMPTY)
+		;
+	c = *buf;
+	rbdf->cbd_sc |= BD_SC_EMPTY;
+
+	return(c);
+}
+
+int
+serial_tstc()
+{
+	volatile cbd_t		*rbdf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+
+	up = (smc_uart_t *)&(im->im_dprambase[PROFF_SMC]);
+
+	rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
+
+	return(!(rbdf->cbd_sc & BD_SC_EMPTY));
+}
+
+#endif	/* CONFIG_CONS_ON_SMC */
+
+#if defined(CONFIG_KGDB_ON_SMC)
+
+#if defined(CONFIG_CONS_ON_SMC) && CONFIG_KGDB_INDEX == CONFIG_CONS_INDEX
+#error Whoops! serial console and kgdb are on the same smc serial port
+#endif
+
+#if CONFIG_KGDB_INDEX == 1	/* KGDB Port on SMC1 */
+
+#define KGDB_SMC_INDEX		0
+#define KGDB_PROFF_SMC_BASE	PROFF_SMC1_BASE
+#define KGDB_PROFF_SMC		PROFF_SMC1
+#define KGDB_CPM_CR_SMC_PAGE	CPM_CR_SMC1_PAGE
+#define KGDB_CPM_CR_SMC_SBLOCK	CPM_CR_SMC1_SBLOCK
+#define KGDB_CMXSMR_MASK	(CMXSMR_SMC1|CMXSMR_SMC1CS_MSK)
+#define KGDB_CMXSMR_VALUE	CMXSMR_SMC1CS_BRG7
+
+#elif CONFIG_KGDB_INDEX == 2	/* KGDB Port on SMC2 */
+
+#define KGDB_SMC_INDEX		1
+#define KGDB_PROFF_SMC_BASE	PROFF_SMC2_BASE
+#define KGDB_PROFF_SMC		PROFF_SMC2
+#define KGDB_CPM_CR_SMC_PAGE	CPM_CR_SMC2_PAGE
+#define KGDB_CPM_CR_SMC_SBLOCK	CPM_CR_SMC2_SBLOCK
+#define KGDB_CMXSMR_MASK	(CMXSMR_SMC2|CMXSMR_SMC2CS_MSK)
+#define KGDB_CMXSMR_VALUE	CMXSMR_SMC2CS_BRG8
+
+#else
+
+#error "console not correctly defined"
+
+#endif
+
+void
+kgdb_serial_init (void)
+{
+        volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile smc_t *sp;
+	volatile smc_uart_t *up;
+	volatile cbd_t *tbdf, *rbdf;
+	volatile cpm8260_t *cp = &(im->im_cpm);
+	uint dpaddr, speed = CONFIG_KGDB_BAUDRATE;
+	char *s, *e;
+
+	if ((s = getenv("kgdbrate")) != NULL && *s != '\0') {
+		ulong rate = simple_strtoul(s, &e, 10);
+		if (e > s && *e == '\0')
+			speed = rate;
+	}
+
+	/* initialize pointers to SMC */
+
+	sp = (smc_t *) &(im->im_smc[KGDB_SMC_INDEX]);
+	*(ushort *)(&im->im_dprambase[KGDB_PROFF_SMC_BASE]) = KGDB_PROFF_SMC;
+	up = (smc_uart_t *)&im->im_dprambase[KGDB_PROFF_SMC];
+
+	/* Disable transmitter/receiver.
+	*/
+	sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+
+	/* NOTE: I/O port pins are set up via the iop_conf_tab[] table */
+
+	/* Allocate space for two buffer descriptors in the DP ram.
+	 * damm: allocating space after the two buffers for rx/tx data
+	 */
+
+	dpaddr = m8260_cpm_dpalloc((2 * sizeof (cbd_t)) + 2, 16);
+
+	/* Set the physical address of the host memory buffers in
+	 * the buffer descriptors.
+	 */
+	rbdf = (cbd_t *)&im->im_dprambase[dpaddr];
+	rbdf->cbd_bufaddr = (uint) (rbdf+2);
+	rbdf->cbd_sc = 0;
+	tbdf = rbdf + 1;
+	tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
+	tbdf->cbd_sc = 0;
+
+	/* Set up the uart parameters in the parameter ram.
+	*/
+	up->smc_rbase = dpaddr;
+	up->smc_tbase = dpaddr+sizeof(cbd_t);
+	up->smc_rfcr = CPMFCR_EB;
+	up->smc_tfcr = CPMFCR_EB;
+	up->smc_brklen = 0;
+	up->smc_brkec = 0;
+	up->smc_brkcr = 0;
+
+	/* Set UART mode, 8 bit, no parity, one stop.
+	 * Enable receive and transmit.
+	 */
+	sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
+
+	/* Mask all interrupts and remove anything pending.
+	*/
+	sp->smc_smcm = 0;
+	sp->smc_smce = 0xff;
+
+	/* put the SMC channel into NMSI (non multiplexd serial interface)
+	 * mode and wire either BRG7 to SMC1 or BRG8 to SMC2 (15-17).
+	 */
+	im->im_cpmux.cmx_smr =
+		(im->im_cpmux.cmx_smr & ~KGDB_CMXSMR_MASK) | KGDB_CMXSMR_VALUE;
+
+	/* Set up the baud rate generator.
+	*/
+#if defined(CONFIG_KGDB_USE_EXTC)
+	m8260_cpm_extcbrg(KGDB_SMC_INDEX, speed,
+		CONFIG_KGDB_EXTC_RATE, CONFIG_KGDB_EXTC_PINSEL);
+#else
+	m8260_cpm_setbrg(KGDB_SMC_INDEX, speed);
+#endif
+
+	/* Make the first buffer the only buffer.
+	*/
+	tbdf->cbd_sc |= BD_SC_WRAP;
+	rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
+
+	/* Single character receive.
+	*/
+	up->smc_mrblr = 1;
+	up->smc_maxidl = 0;
+
+	/* Initialize Tx/Rx parameters.
+	*/
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	cp->cp_cpcr = mk_cr_cmd(KGDB_CPM_CR_SMC_PAGE, KGDB_CPM_CR_SMC_SBLOCK,
+					0, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+
+	while (cp->cp_cpcr & CPM_CR_FLG)  /* wait if cp is busy */
+	  ;
+
+	/* Enable transmitter/receiver.
+	*/
+	sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+
+	printf("SMC%d at %dbps ", CONFIG_KGDB_INDEX, speed);
+}
+
+void
+putDebugChar(const char c)
+{
+	volatile cbd_t		*tbdf;
+	volatile char		*buf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+
+	if (c == '\n')
+		putDebugChar ('\r');
+
+	up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
+
+	tbdf = (cbd_t *)&im->im_dprambase[up->smc_tbase];
+
+	/* Wait for last character to go.
+	*/
+	buf = (char *)tbdf->cbd_bufaddr;
+	while (tbdf->cbd_sc & BD_SC_READY)
+		;
+
+	*buf = c;
+	tbdf->cbd_datlen = 1;
+	tbdf->cbd_sc |= BD_SC_READY;
+}
+
+void
+putDebugStr (const char *s)
+{
+	while (*s) {
+		putDebugChar (*s++);
+	}
+}
+
+int
+getDebugChar(void)
+{
+	volatile cbd_t		*rbdf;
+	volatile unsigned char	*buf;
+	volatile smc_uart_t	*up;
+        volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	unsigned char		c;
+
+	up = (smc_uart_t *)&(im->im_dprambase[KGDB_PROFF_SMC]);
+
+	rbdf = (cbd_t *)&im->im_dprambase[up->smc_rbase];
+
+	/* Wait for character to show up.
+	*/
+	buf = (unsigned char *)rbdf->cbd_bufaddr;
+	while (rbdf->cbd_sc & BD_SC_EMPTY)
+		;
+	c = *buf;
+	rbdf->cbd_sc |= BD_SC_EMPTY;
+
+	return(c);
+}
+
+void
+kgdb_interruptible(int yes)
+{
+	return;
+}
+
+#endif	/* CONFIG_KGDB_ON_SMC */
diff --git a/cpu/mpc8260/speed.c b/cpu/mpc8260/speed.c
new file mode 100644
index 0000000..2bf2c4a
--- /dev/null
+++ b/cpu/mpc8260/speed.c
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2000-2002
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8260.h>
+#include <asm/processor.h>
+
+/* ------------------------------------------------------------------------- */
+
+/* Bus-to-Core Multiplier */
+#define _1x	2
+#define _1_5x	3
+#define _2x	4
+#define _2_5x	5
+#define _3x	6
+#define _3_5x	7
+#define _4x	8
+#define _4_5x	9
+#define _5x	10
+#define _5_5x	11
+#define _6x	12
+#define _6_5x	13
+#define _7x	14
+#define _7_5x	15
+#define _8x	16
+#define _byp	-1
+#define _off	-2
+#define _unk	-3
+
+typedef struct {
+	int b2c_mult;
+	int vco_div;
+	char *freq_60x;
+	char *freq_core;
+} corecnf_t;
+
+/*
+ * this table based on "Errata to MPC8260 PowerQUICC II User's Manual",
+ * Rev. 1, 8/2000, page 10.
+ */
+corecnf_t corecnf_tab[] = {
+	{ _1_5x,  4, " 33-100", " 33-100" },	/* 0x00 */
+	{   _1x,  4, " 50-150", " 50-150" },	/* 0x01 */
+	{   _1x,  8, " 25-75 ", " 25-75 " },	/* 0x02 */
+	{  _byp, -1, "  ?-?  ", "  ?-?  " },	/* 0x03 */
+	{   _2x,  2, " 50-150", "100-300" },	/* 0x04 */
+	{   _2x,  4, " 25-75 ", " 50-150" },	/* 0x05 */
+	{ _2_5x,  2, " 40-120", "100-240" },	/* 0x06 */
+	{ _4_5x,  2, " 22-65 ", "100-300" },	/* 0x07 */
+	{   _3x,  2, " 33-100", "100-300" },	/* 0x08 */
+	{ _5_5x,  2, " 18-55 ", "100-300" },	/* 0x09 */
+	{   _4x,  2, " 25-75 ", "100-300" },	/* 0x0A */
+	{   _5x,  2, " 20-60 ", "100-300" },	/* 0x0B */
+	{ _1_5x,  8, " 16-50 ", " 16-50 " },	/* 0x0C */
+	{   _6x,  2, " 16-50 ", "100-300" },	/* 0x0D */
+	{ _3_5x,  2, " 30-85 ", "100-300" },	/* 0x0E */
+	{  _off, -1, "  ?-?  ", "  ?-?  " },	/* 0x0F */
+	{   _3x,  4, " 16-50 ", " 50-150" },	/* 0x10 */
+	{ _2_5x,  4, " 20-60 ", " 50-120" },	/* 0x11 */
+	{ _6_5x,  2, " 15-46 ", "100-300" },	/* 0x12 */
+	{  _byp, -1, "  ?-?  ", "  ?-?  " },	/* 0x13 */
+	{   _7x,  2, " 14-43 ", "100-300" },	/* 0x14 */
+	{   _2x,  4, " 25-75 ", " 50-150" },	/* 0x15 */
+	{ _7_5x,  2, " 13-40 ", "100-300" },	/* 0x16 */
+	{ _4_5x,  2, " 22-65 ", "100-300" },	/* 0x17 */
+	{  _unk, -1, "  ?-?  ", "  ?-?  " },	/* 0x18 */
+	{ _5_5x,  2, " 18-55 ", "100-300" },	/* 0x19 */
+	{   _4x,  2, " 25-75 ", "100-300" },	/* 0x1A */
+	{   _5x,  2, " 20-60 ", "100-300" },	/* 0x1B */
+	{   _8x,  2, " 12-38 ", "100-300" },	/* 0x1C */
+	{   _6x,  2, " 16-50 ", "100-300" },	/* 0x1D */
+	{ _3_5x,  2, " 30-85 ", "100-300" },	/* 0x1E */
+	{  _off, -1, "  ?-?  ", "  ?-?  " },	/* 0x1F */
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ *
+ */
+
+int get_clocks (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	ulong clkin;
+	ulong sccr, dfbrg;
+	ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
+	corecnf_t *cp;
+
+#if !defined(CONFIG_8260_CLKIN)
+#error clock measuring not implemented yet - define CONFIG_8260_CLKIN
+#else
+	clkin = CONFIG_8260_CLKIN;
+#endif
+
+	sccr = immap->im_clkrst.car_sccr;
+	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
+
+	scmr = immap->im_clkrst.car_scmr;
+	corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
+	busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
+	cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
+	plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
+	pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
+
+	cp = &corecnf_tab[corecnf];
+
+	gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
+
+#if 0
+	if (gd->vco_out / (busdf + 1) != clkin) {
+		/* aaarrrggghhh!!! */
+		return (1);
+	}
+#endif
+
+	gd->cpm_clk = gd->vco_out / 2;
+	gd->bus_clk = clkin;
+	gd->scc_clk = gd->vco_out / 4;
+	gd->brg_clk = gd->vco_out / (1 << (2 * (dfbrg + 1)));
+
+	if (cp->b2c_mult > 0) {
+		gd->cpu_clk = (clkin * cp->b2c_mult) / 2;
+	} else {
+		gd->cpu_clk = clkin;
+	}
+
+	return (0);
+}
+
+int prt_8260_clks (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	ulong sccr, dfbrg;
+	ulong scmr, corecnf, busdf, cpmdf, plldf, pllmf;
+	corecnf_t *cp;
+
+	sccr = immap->im_clkrst.car_sccr;
+	dfbrg = (sccr & SCCR_DFBRG_MSK) >> SCCR_DFBRG_SHIFT;
+
+	scmr = immap->im_clkrst.car_scmr;
+	corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
+	busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
+	cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
+	plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
+	pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
+
+	cp = &corecnf_tab[corecnf];
+
+	printf ("MPC8260 Clock Configuration\n - Bus-to-Core Mult ");
+
+	switch (cp->b2c_mult) {
+	case _byp:
+		printf ("BYPASS");
+		break;
+
+	case _off:
+		printf ("OFF");
+		break;
+
+	case _unk:
+		printf ("UNKNOWN");
+		break;
+
+	default:
+		printf ("%d%sx",
+			cp->b2c_mult / 2,
+			(cp->b2c_mult % 2) ? ".5" : "");
+		break;
+	}
+
+	printf (", VCO Div %d, 60x Bus Freq %s, Core Freq %s\n",
+			cp->vco_div, cp->freq_60x, cp->freq_core);
+
+	printf (" - dfbrg %ld, corecnf 0x%02lx, busdf %ld, cpmdf %ld, "
+			"plldf %ld, pllmf %ld\n", dfbrg, corecnf, busdf, cpmdf, plldf,
+			pllmf);
+
+	printf (" - vco_out %10ld, scc_clk %10ld, brg_clk %10ld\n",
+			gd->vco_out, gd->scc_clk, gd->brg_clk);
+
+	printf (" - cpu_clk %10ld, cpm_clk %10ld, bus_clk %10ld\n\n",
+			gd->cpu_clk, gd->cpm_clk, gd->bus_clk);
+	return (0);
+}
+
+/* ------------------------------------------------------------------------- */