| // SPDX-License-Identifier: GPL-2.0+ |
| /* |
| * Xilinx MicroZED board DTS |
| * |
| * Copyright (C) 2013 - 2016 Xilinx, Inc. |
| */ |
| /dts-v1/; |
| #include "zynq-7000.dtsi" |
| |
| / { |
| model = "Zynq MicroZED Board"; |
| compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; |
| |
| aliases { |
| serial0 = &uart1; |
| spi0 = &qspi; |
| mmc0 = &sdhci0; |
| }; |
| |
| memory@0 { |
| device_type = "memory"; |
| reg = <0 0x40000000>; |
| }; |
| |
| chosen { |
| bootargs = "earlyprintk"; |
| stdout-path = "serial0:115200n8"; |
| }; |
| |
| usb_phy0: phy0 { |
| compatible = "usb-nop-xceiv"; |
| #phy-cells = <0>; |
| }; |
| }; |
| |
| &clkc { |
| ps-clk-frequency = <33333333>; |
| }; |
| |
| &qspi { |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| &gem0 { |
| status = "okay"; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðernet_phy>; |
| |
| ethernet_phy: ethernet-phy@0 { |
| reg = <0>; |
| }; |
| }; |
| |
| &sdhci0 { |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| &usb0 { |
| status = "okay"; |
| dr_mode = "host"; |
| usb-phy = <&usb_phy0>; |
| }; |