commit 49d0eeeb9aad2929a9137b8a36e7f9be015eb668
author Marian Balakowicz <m8@semihalf.com> Fri Jun 30 16:30:46 2006 +0200
committer Marian Balakowicz <m8@semihalf.com> Fri Jun 30 16:30:46 2006 +0200
tree 32b48cff57dafc910c7b0dfdd6c5b99109c21e46
parent b55b60ebe5ba47d65741af9ffa2e1cdd61b7135a

Add support for AMCC 440SPe CPU based eval board (Yucca).

cpu/ppc4xx/cpu.c

diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index a26533c..3e85a88 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -78,7 +78,9 @@
 	return (mfdcr(cpc0_strp1) & CPC0_STRP1_PAE_MASK);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+     defined(CONFIG_440SPE)
 	unsigned long val;
 
 	mfsdr(sdr_sdstp1, val);
@@ -87,8 +89,8 @@
 }
 #endif
 
-#if defined(CONFIG_405EP)|| defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
-	defined(CONFIG_440GX) || defined(CONFIG_440SP)
+#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) ||  \
+     defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
 
 #define I2C_BOOTROM
 
@@ -98,7 +100,9 @@
 	return (mfdcr(cpc0_boot) & CPC0_BOOT_SEP);
 #endif
 
-#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) || defined(CONFIG_440SP)
+#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || \
+     defined(CONFIG_440GR) || defined(CONFIG_440SP) || \
+	defined(CONFIG_440SPE)
 	unsigned long val;
 
 	mfsdr(sdr_sdcs, val);
@@ -237,6 +241,12 @@
 		puts("SP Rev. B");
 		break;
 
+	case PVR_440SPe_RA:
+		puts("SPe 3GA533C");
+		break;
+	case PVR_440SPe_RB:
+		puts("SPe 3GB533C");
+		break;
 	default:
 		printf (" UNKNOWN (PVR=%08x)", pvr);
 		break;