| commit | f53bd8126b7ba5a4e881f4799a4ff12585370eba | [log] [tgz] |
|---|---|---|
| author | Vignesh Raghavendra <vigneshr@ti.com> | Fri Oct 11 13:28:19 2019 +0530 |
| committer | Jagan Teki <jagan@amarulasolutions.com> | Fri Oct 25 00:48:32 2019 +0530 |
| tree | 44f33fa7505061b547d8ee317dd673b9ec691509 | |
| parent | 84acf7320f7e1cfef70a68c89006790c66c52126 [diff] |
spi-nor: spi-nor-ids: Add entries for mt25q variants mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>