Merge tag 'u-boot-atmel-2021.10-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel into next
First set of u-boot-atmel features for the 2021.10 cycle:
This feature set converts the boards pm9261 and pm9263 Ethernet support
to DM; enables hash command for all SAM boards; fixes the NAND pmecc
bit-flips correction; adds Falcon boot for sama5d3_xplained board; and
other minor adjustments.
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index d176e04..35ab7f3 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -144,7 +144,7 @@
export USER=azure
virtualenv -p /usr/bin/python3 /tmp/venv
. /tmp/venv/bin/activate
- pip install pyelftools pytest pygit2
+ pip install -r test/py/requirements.txt
export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl
export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt
export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}
@@ -205,18 +205,6 @@
qemu_arm64:
TEST_PY_BD: "qemu_arm64"
TEST_PY_TEST_SPEC: "not sleep"
- qemu_mips:
- TEST_PY_BD: "qemu_mips"
- TEST_PY_TEST_SPEC: "not sleep"
- qemu_mipsel:
- TEST_PY_BD: "qemu_mipsel"
- TEST_PY_TEST_SPEC: "not sleep"
- qemu_mips64:
- TEST_PY_BD: "qemu_mips64"
- TEST_PY_TEST_SPEC: "not sleep"
- qemu_mips64el:
- TEST_PY_BD: "qemu_mips64el"
- TEST_PY_TEST_SPEC: "not sleep"
qemu_malta:
TEST_PY_BD: "malta"
TEST_PY_ID: "--id qemu"
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 51bd643..d072e83 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -151,7 +151,7 @@
export USER=gitlab;
virtualenv -p /usr/bin/python3 /tmp/venv;
. /tmp/venv/bin/activate;
- pip install pyelftools pytest pygit2;
+ pip install -r test/py/requirements.txt;
export UBOOT_TRAVIS_BUILD_DIR=/tmp/sandbox_spl;
export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt";
export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}";
@@ -189,7 +189,6 @@
<<: *buildman_and_testpy_dfn
sandbox_noinst_test.py:
- tags: [ 'all' ]
variables:
TEST_PY_BD: "sandbox_noinst"
TEST_PY_TEST_SPEC: "test_ofplatdata or test_handoff or test_spl"
@@ -225,30 +224,6 @@
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
-qemu_mips test.py:
- variables:
- TEST_PY_BD: "qemu_mips"
- TEST_PY_TEST_SPEC: "not sleep"
- <<: *buildman_and_testpy_dfn
-
-qemu_mipsel test.py:
- variables:
- TEST_PY_BD: "qemu_mipsel"
- TEST_PY_TEST_SPEC: "not sleep"
- <<: *buildman_and_testpy_dfn
-
-qemu_mips64 test.py:
- variables:
- TEST_PY_BD: "qemu_mips64"
- TEST_PY_TEST_SPEC: "not sleep"
- <<: *buildman_and_testpy_dfn
-
-qemu_mips64el test.py:
- variables:
- TEST_PY_BD: "qemu_mips64el"
- TEST_PY_TEST_SPEC: "not sleep"
- <<: *buildman_and_testpy_dfn
-
qemu_malta test.py:
variables:
TEST_PY_BD: "malta"
diff --git a/Kbuild b/Kbuild
index 1eac091..bf52e54 100644
--- a/Kbuild
+++ b/Kbuild
@@ -10,6 +10,8 @@
always := $(generic-offsets-file)
targets := lib/asm-offsets.s
+CFLAGS_REMOVE_asm-offsets.o := $(LTO_CFLAGS)
+
$(obj)/$(generic-offsets-file): $(obj)/lib/asm-offsets.s FORCE
$(call filechk,offsets,__GENERIC_ASM_OFFSETS_H__)
diff --git a/Kconfig b/Kconfig
index 86f0a39..f8c1a77 100644
--- a/Kconfig
+++ b/Kconfig
@@ -85,6 +85,30 @@
do what it thinks is best, which is desirable in some cases for size
reasons.
+config ARCH_SUPPORTS_LTO
+ bool
+
+config LTO
+ bool "Enable Link Time Optimizations"
+ depends on ARCH_SUPPORTS_LTO
+ default n
+ help
+ This option enables Link Time Optimization (LTO), a mechanism which
+ allows the compiler to optimize between different compilation units.
+
+ This can optimize away dead code paths, resulting in smaller binary
+ size (if CC_OPTIMIZE_FOR_SIZE is enabled).
+
+ This option is not available for every architecture and may
+ introduce bugs.
+
+ Currently, when compiling with GCC, due to a weird bug regarding
+ jobserver, the final linking will not respect make's --jobs argument.
+ Instead all available processors will be used (as reported by the
+ nproc command).
+
+ If unsure, say n.
+
config TPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in TPL"
depends on TPL
diff --git a/MAINTAINERS b/MAINTAINERS
index 2d267ae..effcf54 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -118,7 +118,7 @@
ARM ALTERA SOCFPGA
M: Marek Vasut <marex@denx.de>
M: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
-M: Ley Foon Tan <ley.foon.tan@intel.com>
+M: Ley Foon Tan <lftan.linux@gmail.com>
S: Maintainted
T: git https://source.denx.de/u-boot/custodians/u-boot-socfpga.git
F: arch/arm/mach-socfpga/
@@ -352,7 +352,7 @@
ARM ROCKCHIP
M: Simon Glass <sjg@chromium.org>
-M: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+M: Philipp Tomsich <philipp.tomsich@vrull.eu>
M: Kever Yang <kever.yang@rock-chips.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git
@@ -478,6 +478,9 @@
F: arch/arm/include/asm/arch-sunxi/
F: arch/arm/mach-sunxi/
F: board/sunxi/
+F: drivers/clk/sunxi/
+F: drivers/phy/allwinner/
+F: drivers/video/sunxi/
ARM TEGRA
M: Tom Warren <twarren@nvidia.com>
@@ -981,6 +984,7 @@
RISC-V
M: Rick Chen <rick@andestech.com>
+M: Leo <ycliang@andestech.com>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-riscv.git
F: arch/riscv/
@@ -995,8 +999,8 @@
S: Maintained
F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
F: doc/device-tree-bindings/pinctrl/kendryte,k210-fpioa.txt
-F: drivers/clk/kendryte/
-F: drivers/pinctrl/kendryte/
+F: drivers/clk/clk_kendryte.c
+F: drivers/pinctrl/pinctrl-kendryte.c
F: include/kendryte/
RNG
@@ -1171,6 +1175,18 @@
F: include/lcd*.h
F: include/video*.h
+VirtIO
+M: Bin Meng <bmeng.cn@gmail.com>
+S: Maintained
+F: drivers/virtio/
+F: cmd/virtio.c
+F: include/config/virtio/
+F: include/config/virtio.h
+F: include/config/cmd/virtio.h
+F: include/virtio*.h
+F: test/dm/virtio.c
+F: doc/develop/driver-model/virtio.rst
+
X86
M: Simon Glass <sjg@chromium.org>
M: Bin Meng <bmeng.cn@gmail.com>
diff --git a/Makefile b/Makefile
index a0ab464..a73481d 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@
VERSION = 2021
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc4
NAME =
# *DOCUMENTATION*
@@ -408,7 +408,7 @@
PERL = perl
PYTHON ?= python
PYTHON2 = python2
-PYTHON3 = python3
+PYTHON3 ?= python3
DTC ?= $(objtree)/scripts/dtc/dtc
CHECK = sparse
@@ -676,6 +676,31 @@
KBUILD_CFLAGS += -O2
endif
+LTO_CFLAGS :=
+LTO_FINAL_LDFLAGS :=
+export LTO_CFLAGS LTO_FINAL_LDFLAGS
+ifdef CONFIG_LTO
+ ifeq ($(cc-name),clang)
+ LTO_CFLAGS += -flto
+ LTO_FINAL_LDFLAGS += -flto
+
+ AR = $(shell $(CC) -print-prog-name=llvm-ar)
+ NM = $(shell $(CC) -print-prog-name=llvm-nm)
+ else
+ NPROC := $(shell nproc 2>/dev/null || echo 1)
+ LTO_CFLAGS += -flto=$(NPROC)
+ LTO_FINAL_LDFLAGS += -fuse-linker-plugin -flto=$(NPROC)
+
+ # use plugin aware tools
+ AR = $(CROSS_COMPILE)gcc-ar
+ NM = $(CROSS_COMPILE)gcc-nm
+ endif
+
+ CFLAGS_NON_EFI += $(LTO_CFLAGS)
+
+ KBUILD_CFLAGS += $(LTO_CFLAGS)
+endif
+
ifeq ($(CONFIG_STACKPROTECTOR),y)
KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong)
CFLAGS_EFI += $(call cc-option,-fno-stack-protector)
@@ -918,6 +943,7 @@
endif
INPUTS-$(CONFIG_TPL) += tpl/u-boot-tpl.bin
INPUTS-$(CONFIG_OF_SEPARATE) += u-boot.dtb
+INPUTS-$(CONFIG_BINMAN_STANDALONE_FDT) += u-boot.dtb
ifeq ($(CONFIG_SPL_FRAMEWORK),y)
INPUTS-$(CONFIG_OF_SEPARATE) += u-boot-dtb.img
endif
@@ -971,6 +997,8 @@
# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
LDFLAGS_u-boot += $(call ld-option, --no-dynamic-linker)
+LDFLAGS_u-boot += --build-id=none
+
ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),)
LDFLAGS_u-boot += -Ttext $(CONFIG_SYS_TEXT_BASE)
endif
@@ -1086,10 +1114,8 @@
@echo >&2 "See doc/driver-model/migration.rst for more info."
@echo >&2 "===================================================="
endif
- $(call deprecated,CONFIG_DM_MMC CONFIG_BLK,MMC,v2019.04,$(CONFIG_MMC))
$(call deprecated,CONFIG_DM_USB CONFIG_OF_CONTROL CONFIG_BLK,\
USB,v2019.07,$(CONFIG_USB))
- $(call deprecated,CONFIG_AHCI,AHCI,v2019.07, $(CONFIG_LIBATA))
$(call deprecated,CONFIG_DM_PCI,PCI,v2019.07,$(CONFIG_PCI))
$(call deprecated,CONFIG_DM_VIDEO,video,v2019.07,\
$(CONFIG_LCD)$(CONFIG_VIDEO))
@@ -1287,6 +1313,7 @@
-I . -I $(srctree) -I $(srctree)/board/$(BOARDDIR) \
-I arch/$(ARCH)/dts -a of-list=$(CONFIG_OF_LIST) \
-a atf-bl31-path=${BL31} \
+ -a opensbi-path=${OPENSBI} \
-a default-dt=$(default_dt) \
-a scp-path=$(SCP) \
-a spl-bss-pad=$(if $(CONFIG_SPL_SEPARATE_BSS),,1) \
@@ -1391,7 +1418,7 @@
u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
- $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
+ $(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE)$(CONFIG_BINMAN_STANDALONE_FDT),dts/dt.dtb) \
,$(UBOOT_BIN)) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
@@ -1493,10 +1520,16 @@
flash.bin: spl/u-boot-spl.bin u-boot.cnt FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
else
+ifeq ($(CONFIG_BINMAN),y)
+flash.bin: spl/u-boot-spl.bin $(INPUTS-y) FORCE
+ $(call if_changed,binman)
+ $(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
+else
flash.bin: spl/u-boot-spl.bin u-boot.itb FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
endif
endif
+endif
u-boot.uim: u-boot.bin FORCE
$(Q)$(MAKE) $(build)=arch/arm/mach-imx $@
@@ -1702,14 +1735,54 @@
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
+# Generate linker list symbols references to force compiler to not optimize
+# them away when compiling with LTO
+ifdef CONFIG_LTO
+u-boot-keep-syms-lto := keep-syms-lto.o
+u-boot-keep-syms-lto_c := $(patsubst %.o,%.c,$(u-boot-keep-syms-lto))
+
+quiet_cmd_keep_syms_lto = KSL $@
+ cmd_keep_syms_lto = \
+ NM=$(NM) $(srctree)/scripts/gen_ll_addressable_symbols.sh $^ >$@
+
+quiet_cmd_keep_syms_lto_cc = KSLCC $@
+ cmd_keep_syms_lto_cc = \
+ $(CC) $(filter-out $(LTO_CFLAGS),$(c_flags)) -c -o $@ $<
+
+$(u-boot-keep-syms-lto_c): $(u-boot-main)
+ $(call if_changed,keep_syms_lto)
+$(u-boot-keep-syms-lto): $(u-boot-keep-syms-lto_c)
+ $(call if_changed,keep_syms_lto_cc)
+else
+u-boot-keep-syms-lto :=
+endif
+
# Rule to link u-boot
# May be overridden by arch/$(ARCH)/config.mk
+ifdef CONFIG_LTO
+quiet_cmd_u-boot__ ?= LTO $@
+ cmd_u-boot__ ?= \
+ $(CC) -nostdlib -nostartfiles \
+ $(LTO_FINAL_LDFLAGS) $(c_flags) \
+ $(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@ \
+ -T u-boot.lds $(u-boot-init) \
+ -Wl,--whole-archive \
+ $(u-boot-main) \
+ $(u-boot-keep-syms-lto) \
+ $(PLATFORM_LIBS) \
+ -Wl,--no-whole-archive \
+ -Wl,-Map,u-boot.map; \
+ $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
+else
quiet_cmd_u-boot__ ?= LD $@
- cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
- -T u-boot.lds $(u-boot-init) \
- --start-group $(u-boot-main) --end-group \
- $(PLATFORM_LIBS) -Map u-boot.map; \
- $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
+ cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@ \
+ -T u-boot.lds $(u-boot-init) \
+ --whole-archive \
+ $(u-boot-main) \
+ --no-whole-archive \
+ $(PLATFORM_LIBS) -Map u-boot.map; \
+ $(if $(ARCH_POSTLINK), $(MAKE) -f $(ARCH_POSTLINK) $@, true)
+endif
quiet_cmd_smap = GEN common/system_map.o
cmd_smap = \
@@ -1718,7 +1791,7 @@
$(CC) $(c_flags) -DSYSTEM_MAP="\"$${smap}\"" \
-c $(srctree)/common/system_map.c -o common/system_map.o
-u-boot: $(u-boot-init) $(u-boot-main) u-boot.lds FORCE
+u-boot: $(u-boot-init) $(u-boot-main) $(u-boot-keep-syms-lto) u-boot.lds FORCE
+$(call if_changed,u-boot__)
ifeq ($(CONFIG_KALLSYMS),y)
$(call cmd,smap)
@@ -1854,11 +1927,10 @@
endef
define filechk_defaultenv.h
- (grep -v '^#' | \
- grep -v '^$$' | \
+ ( { grep -v '^#' | grep -v '^$$' || true ; echo '' ; } | \
tr '\n' '\0' | \
sed -e 's/\\\x0\s*//g' | \
- xxd -i ; echo ", 0x00" ; )
+ xxd -i ; )
endef
define filechk_dt.h
@@ -2002,14 +2074,16 @@
boot* u-boot* MLO* SPL System.map fit-dtb.blob* \
u-boot-ivt.img.log u-boot-dtb.imx.log SPL.log u-boot.imx.log \
lpc32xx-* bl31.c bl31.elf bl31_*.bin image.map tispl.bin* \
- idbloader.img flash.bin flash.log defconfig
+ idbloader.img flash.bin flash.log defconfig keep-syms-lto.c
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
.tmp_objdiff doc/output
+
+# Remove include/asm symlink created by U-Boot before v2014.01
MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
- drivers/video/fonts/*.S
+ drivers/video/fonts/*.S include/asm
# clean - Delete most, but leave enough to build external modules
#
diff --git a/README b/README
index a565748..ad13092 100644
--- a/README
+++ b/README
@@ -747,6 +747,15 @@
SoC, then define this variable and provide board
specific code for the "hw_watchdog_reset" function.
+ CONFIG_SYS_WATCHDOG_FREQ
+ Some platforms automatically call WATCHDOG_RESET()
+ from the timer interrupt handler every
+ CONFIG_SYS_WATCHDOG_FREQ interrupts. If not set by the
+ board configuration file, a default of CONFIG_SYS_HZ/2
+ (i.e. 500) is used. Setting CONFIG_SYS_WATCHDOG_FREQ
+ to 0 disables calling WATCHDOG_RESET() from the timer
+ interrupt.
+
- Real-Time Clock:
When CONFIG_CMD_DATE is selected, the type of the RTC
diff --git a/arch/Kconfig b/arch/Kconfig
index e61a752..49813a4 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -33,6 +33,7 @@
config ARM
bool "ARM architecture"
+ select ARCH_SUPPORTS_LTO
select CREATE_ARCH_SYMLINK
select HAVE_PRIVATE_LIBGCC if !ARM64
select SUPPORT_OF_CONTROL
@@ -101,6 +102,7 @@
config SANDBOX
bool "Sandbox"
+ select ARCH_SUPPORTS_LTO
select BOARD_LATE_INIT
select BZIP2
select CMD_POWEROFF
@@ -121,8 +123,10 @@
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF
select IRQ
+ select SUPPORT_EXTENSION_SCAN
imply BITREVERSE
select BLOBLIST
+ imply LTO
imply CMD_DM
imply CMD_EXCEPTION
imply CMD_GETTIME
@@ -165,6 +169,7 @@
imply BOOTARGS_SUBST
imply PHY_FIXED
imply DM_DSA
+ imply CMD_EXTENSION
config SH
bool "SuperH architecture"
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index e79f010..16c63e1 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -15,9 +15,15 @@
-fstack-protector-strong
CFLAGS_EFI := -fpic -fshort-wchar
+ifneq ($(CONFIG_LTO)$(CONFIG_USE_PRIVATE_LIBGCC),yy)
LDFLAGS_FINAL += --gc-sections
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections \
- -fno-common -ffixed-r9
+endif
+
+ifndef CONFIG_LTO
+PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
+endif
+
+PLATFORM_RELFLAGS += -fno-common -ffixed-r9
PLATFORM_RELFLAGS += $(call cc-option, -msoft-float) \
$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index af63d5c..98aafe8 100644
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -25,6 +25,8 @@
CFLAGS_cpu.o := -marm
CFLAGS_cache.o := -marm
+CFLAGS_REMOVE_cpu.o := $(LTO_CFLAGS)
+CFLAGS_REMOVE_cache.o := $(LTO_CFLAGS)
endif
endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 344b9b4..4d21e3d 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -25,6 +25,7 @@
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
+#include <asm/sections.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -98,7 +99,6 @@
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
- extern uint32_t _start;
mx28_fixup_vt((uint32_t)&_start);
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index a16a15e..0a8985b 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -16,6 +16,7 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
+#include <asm/sections.h>
#include <linux/compiler.h>
#include "mxs_init.h"
@@ -100,7 +101,6 @@
* thus this fixup. Our vectoring table is PIC, so copying is
* fine.
*/
- extern uint32_t _start;
/* cppcheck-suppress nullPointer */
memcpy(0x0, &_start, 0x60);
@@ -122,7 +122,7 @@
{
struct mxs_spl_data *data = MXS_SPL_DATA;
uint8_t bootmode = mxs_get_bootmode_index();
- gd = &gdata;
+ set_gd(&gdata);
mxs_spl_fixup_vectors();
diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c
index 08b98a2..b5b9945 100644
--- a/arch/arm/cpu/arm926ejs/spear/spl.c
+++ b/arch/arm/cpu/arm926ejs/spear/spl.c
@@ -22,7 +22,7 @@
* The BSS cannot be used for this purpose because it will be zeroed after
* having stored the pointer, so force the location to the data section.
*/
-u32 bootrom_stash_sp __attribute__((section(".data")));
+u32 bootrom_stash_sp __section(".data");
static void ddr_clock_init(void)
{
diff --git a/arch/arm/cpu/armv7/kona-common/clk-stubs.c b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
index 2dfa3f7..4eddaca 100644
--- a/arch/arm/cpu/armv7/kona-common/clk-stubs.c
+++ b/arch/arm/cpu/armv7/kona-common/clk-stubs.c
@@ -14,7 +14,7 @@
return 0;
}
-int __weak clk_bsc_enable(void *base, u32 rate, u32 *actual_ratep)
+int __weak clk_bsc_enable(void *base)
{
return 0;
}
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 4a4b3c6..28a7945 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -13,7 +13,7 @@
#include <fsl_immap.h>
#include "fsl_epu.h"
-#define __secure __attribute__((section("._secure.text")))
+#define __secure __section("._secure.text")
#define CCSR_GICD_CTLR 0x1000
#define CCSR_GICC_CTLR 0x2000
diff --git a/arch/arm/cpu/armv8/spl_data.c b/arch/arm/cpu/armv8/spl_data.c
index 8fd986a..8f1231c 100644
--- a/arch/arm/cpu/armv8/spl_data.c
+++ b/arch/arm/cpu/armv8/spl_data.c
@@ -6,8 +6,8 @@
#include <common.h>
#include <spl.h>
-char __data_save_start[0] __section(.__data_save_start);
-char __data_save_end[0] __section(.__data_save_end);
+char __data_save_start[0] __section(".__data_save_start");
+char __data_save_end[0] __section(".__data_save_end");
u32 cold_reboot_flag = 1;
diff --git a/arch/arm/cpu/armv8/u-boot-spl.lds b/arch/arm/cpu/armv8/u-boot-spl.lds
index 0e67ab0..9edb662 100644
--- a/arch/arm/cpu/armv8/u-boot-spl.lds
+++ b/arch/arm/cpu/armv8/u-boot-spl.lds
@@ -77,6 +77,7 @@
KEEP(*(.__bss_end));
} >.sdram
+ /DISCARD/ : { *(.rela*) }
/DISCARD/ : { *(.dynsym) }
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aec5020..0960682 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -236,7 +236,15 @@
armada-xp-gp.dtb \
armada-xp-maxbcm.dtb \
armada-xp-synology-ds414.dtb \
- armada-xp-theadorable.dtb
+ armada-xp-theadorable.dtb \
+ cn9130-db-A.dtb \
+ cn9130-db-B.dtb \
+ cn9131-db-A.dtb \
+ cn9131-db-B.dtb \
+ cn9132-db-A.dtb \
+ cn9132-db-B.dtb \
+ cn9130-crb-A.dtb \
+ cn9130-crb-B.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
@@ -303,6 +311,10 @@
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
+ zynqmp-sm-k26-revA.dtb \
+ zynqmp-smk-k26-revA.dtb \
+ zynqmp-sck-kv-g-revA.dtbo \
+ zynqmp-sck-kv-g-revB.dtbo \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
@@ -809,6 +821,7 @@
dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
+ imx7-cm.dtb \
imx7-colibri-emmc.dtb \
imx7-colibri-rawnand.dtb \
imx7s-warp.dtb \
@@ -833,6 +846,8 @@
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
+ imx8mm-icore-mx8mm-ctouch2.dtb \
+ imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
@@ -840,6 +855,7 @@
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
imx8mn-ddr4-evk.dtb \
+ imx8mq-cm.dtb \
imx8mn-evk.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
@@ -1054,6 +1070,10 @@
k3-j721e-r5-common-proc-board.dtb \
k3-j7200-common-proc-board.dtb \
k3-j7200-r5-common-proc-board.dtb
+dtb-$(CONFIG_SOC_K3_AM642) += k3-am642-evm.dtb \
+ k3-am642-r5-evm.dtb \
+ k3-am642-sk.dtb \
+ k3-am642-r5-sk.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7622-rfb.dtb \
@@ -1081,6 +1101,8 @@
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
+dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
+
targets += $(dtb-y)
# Add any required device tree compiler flags here
diff --git a/arch/arm/dts/am335x-bone-common.dtsi b/arch/arm/dts/am335x-bone-common.dtsi
index 5b8230e..8dcfac3 100644
--- a/arch/arm/dts/am335x-bone-common.dtsi
+++ b/arch/arm/dts/am335x-bone-common.dtsi
@@ -398,3 +398,8 @@
&sham {
status = "okay";
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
+ clock-names = "ext-clk", "int-clk";
+};
diff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts
index 07288fb..2a2972f 100644
--- a/arch/arm/dts/am335x-evm.dts
+++ b/arch/arm/dts/am335x-evm.dts
@@ -762,3 +762,8 @@
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins_default>;
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
+ clock-names = "ext-clk", "int-clk";
+};
diff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts
index c94c33b..b14bf2f 100644
--- a/arch/arm/dts/am335x-evmsk.dts
+++ b/arch/arm/dts/am335x-evmsk.dts
@@ -724,3 +724,8 @@
&lcdc {
status = "okay";
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
+ clock-names = "ext-clk", "int-clk";
+};
diff --git a/arch/arm/dts/am335x-osd335x-common.dtsi b/arch/arm/dts/am335x-osd335x-common.dtsi
index f8ff473..2b55b7d 100644
--- a/arch/arm/dts/am335x-osd335x-common.dtsi
+++ b/arch/arm/dts/am335x-osd335x-common.dtsi
@@ -122,3 +122,9 @@
&sham {
status = "okay";
};
+
+&rtc {
+ clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
+ clock-names = "ext-clk", "int-clk";
+ system-power-controller;
+};
diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts
index 1b1b66b..42e7ddd 100644
--- a/arch/arm/dts/armada-3720-db.dts
+++ b/arch/arm/dts/armada-3720-db.dts
@@ -70,13 +70,13 @@
&comphy {
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_2_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_2_5G>;
};
};
diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts
index 96a4b3d..d86d8f0 100644
--- a/arch/arm/dts/armada-3720-espressobin.dts
+++ b/arch/arm/dts/armada-3720-espressobin.dts
@@ -83,18 +83,18 @@
&comphy {
max-lanes = <3>;
phy0 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_2_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_2_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_SATA0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_SATA0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts
index 974270c..8e0ebf5 100644
--- a/arch/arm/dts/armada-3720-turris-mox.dts
+++ b/arch/arm/dts/armada-3720-turris-mox.dts
@@ -73,18 +73,18 @@
&comphy {
max-lanes = <3>;
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts
index 7f4b822..4bf6d2e 100644
--- a/arch/arm/dts/armada-3720-uDPU.dts
+++ b/arch/arm/dts/armada-3720-uDPU.dts
@@ -108,31 +108,32 @@
&comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
- phy1 {
- phy-type = <PHY_TYPE_SGMII0>;
- phy-speed = <PHY_SPEED_3_125G>;
- };
- phy2 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- phy-speed = <PHY_SPEED_5G>;
- };
+ phy1 {
+ phy-type = <COMPHY_TYPE_SGMII0>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ phy-speed = <COMPHY_SPEED_5G>;
+ };
};
ð0 {
pinctrl-0 = <&pcie_pins>;
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
managed = "in-band-status";
phy = <ðphy0>;
};
ð1 {
status = "okay";
- phy-mode = "sgmii-2500";
+ phy-mode = "2500base-x";
managed = "in-band-status";
phy = <ðphy1>;
};
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi
index a1052ad..2615b8c 100644
--- a/arch/arm/dts/armada-37xx.dtsi
+++ b/arch/arm/dts/armada-37xx.dtsi
@@ -323,7 +323,7 @@
};
pcie0: pcie@d0070000 {
- compatible = "marvell,armada-37xx-pcie";
+ compatible = "marvell,armada-3700-pcie";
reg = <0 0xd0070000 0 0x20000>;
#address-cells = <3>;
#size-cells = <2>;
@@ -332,10 +332,17 @@
status = "disabled";
bus-range = <0 0xff>;
+ /*
+ * The 128 MiB address range [0xe8000000-0xf0000000] is
+ * dedicated for PCIe and can be assigned to 8 windows
+ * with size a power of two. Use one 64 KiB window for
+ * IO at the end and the remaining seven windows
+ * (totaling 127 MiB) for MEM.
+ */
ranges = <0x82000000 0 0xe8000000
- 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
- 0x81000000 0 0xe9000000
- 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
+ 0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
+ 0x81000000 0 0xefff0000
+ 0 0xefff0000 0 0x10000>; /* Port 0 IO*/
};
};
};
diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts
index 3a9df21..ccf470b 100644
--- a/arch/arm/dts/armada-7040-db-nand.dts
+++ b/arch/arm/dts/armada-7040-db-nand.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2017 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
*/
/*
@@ -58,8 +21,8 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- spi0 = &cpm_spi1;
+ i2c0 = &cp0_i2c0;
+ spi0 = &cp0_spi1;
};
memory@00000000 {
@@ -83,18 +46,18 @@
};
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_pinctl {
+&cp0_pinctl {
/* MPP Bus:
* AUDIO [0-5]
* GBE [6-11]
@@ -122,9 +85,9 @@
0xe 0xe 0x0>;
};
-&cpm_spi1 {
+&cp0_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_spi0_pins>;
+ pinctrl-0 = <&cp0_spi0_pins>;
status = "disabled";
spi-flash@0 {
@@ -152,59 +115,59 @@
};
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_usb3_0 {
+&cp0_usb3_0 {
status = "okay";
};
-&cpm_usb3_1 {
+&cp0_usb3_1 {
status = "okay";
};
-&cpm_comphy {
+&cp0_comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_SGMII0>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII0>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_SATA1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX2>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
-&cpm_nand {
+&cp0_nand {
status = "okay";
};
-&cpm_utmi0 {
+&cp0_utmi0 {
status = "okay";
};
-&cpm_utmi1 {
+&cp0_utmi1 {
status = "okay";
};
@@ -215,7 +178,7 @@
non-removable;
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts
index cfd2b4b..b158f92 100644
--- a/arch/arm/dts/armada-7040-db.dts
+++ b/arch/arm/dts/armada-7040-db.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
*/
/*
@@ -57,8 +20,8 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- spi0 = &cpm_spi1;
+ i2c0 = &cp0_i2c0;
+ spi0 = &cp0_spi1;
};
memory@00000000 {
@@ -82,18 +45,18 @@
};
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_pinctl {
+&cp0_pinctl {
/* MPP Bus:
* TDM [0-11]
* SPI [13-16]
@@ -115,9 +78,9 @@
0xE 0xE 0xE >;
};
-&cpm_spi1 {
+&cp0_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_spi0_pins>;
+ pinctrl-0 = <&cp0_spi0_pins>;
status = "okay";
spi-flash@0 {
@@ -145,54 +108,55 @@
};
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_usb3_0 {
+&cp0_usb3_0 {
status = "okay";
};
-&cpm_usb3_1 {
+&cp0_usb3_1 {
status = "okay";
};
-&cpm_comphy {
+&cp0_comphy {
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy1 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_SATA1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
- phy-speed = <PHY_SPEED_5G>;
+ phy-type = <COMPHY_TYPE_PEX2>;
+ phy-speed = <COMPHY_SPEED_5G>;
};
};
-&cpm_utmi0 {
+&cp0_utmi0 {
status = "okay";
};
-&cpm_utmi1 {
+&cp0_utmi1 {
status = "okay";
};
@@ -203,14 +167,14 @@
non-removable;
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
non-removable;
};
-&cpm_mdio {
+&cp0_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
@@ -219,22 +183,22 @@
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
phy-mode = "sfi"; /* lane-2 */
};
-&cpm_eth1 {
+&cp0_eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
diff --git a/arch/arm/dts/armada-7040.dtsi b/arch/arm/dts/armada-7040.dtsi
index b5be0c4..039d30c 100644
--- a/arch/arm/dts/armada-7040.dtsi
+++ b/arch/arm/dts/armada-7040.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
*/
/*
@@ -46,11 +9,57 @@
*/
#include <dt-bindings/gpio/gpio.h>
-#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
+#include "armada-common.dtsi"
+#include "armada-8k.dtsi"
+#include "armada-ap806.dtsi"
+#include "armada-ap80x-quad.dtsi"
+
+/* CP110-0 Settings */
+#define CP110_NAME cp0
+#define CP110_NUM 0
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_NUM
/ {
model = "Marvell Armada 7040";
compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
};
+
+&cp0_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,7k-pinctrl";
+ bank-name ="cp0-110";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
+ marvell,function = <3>;
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = < 44 45 46 47 48 49 50 51
+ 52 53 54 55 >;
+ marvell,function = <1>;
+ };
+ cp0_pca0_pins: cp0-pca0_pins {
+ marvell,pins = <62>;
+ marvell,function = <0>;
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+};
diff --git a/arch/arm/dts/armada-8020.dtsi b/arch/arm/dts/armada-8020.dtsi
deleted file mode 100644
index 048e5cf..0000000
--- a/arch/arm/dts/armada-8020.dtsi
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and
- * two CP110.
- */
-
-#include "armada-ap806-dual.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
-
-/ {
- model = "Marvell Armada 8020";
- compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
- "marvell,armada-ap806";
-};
diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
index 720c950..6a586db 100644
--- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
+++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts
@@ -15,9 +15,9 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- i2c1 = &cpm_i2c1;
- spi0 = &cps_spi1;
+ i2c0 = &cp0_i2c0;
+ i2c1 = &cp0_i2c1;
+ spi0 = &cp1_spi1;
};
memory@00000000 {
@@ -31,14 +31,14 @@
reg_usb3h0_vbus: usb3-vbus0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "reg-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
startup-delay-us = <300000>;
shutdown-delay-us = <500000>;
regulator-force-boot-off;
- gpio = <&cpm_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
+ gpio = <&cp0_gpio1 15 GPIO_ACTIVE_LOW>; /* GPIO[47] */
};
};
};
@@ -66,7 +66,7 @@
status = "okay";
};
-&cpm_pinctl {
+&cp0_pinctl {
/*
* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
@@ -99,111 +99,111 @@
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
- cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+ cp0_pcie_reset_pins: cp0-pcie-reset-pins {
marvell,pins = < 32 >;
marvell,function = <0>;
};
- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+ cp0_xhci_vbus_pins: cp0-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
};
- cps_1g_phy_reset: cps-1g-phy-reset {
+ cp1_1g_phy_reset: cp1-1g-phy-reset {
marvell,pins = < 43 >;
marvell,function = <0>;
};
};
/* uSD slot */
-&cpm_sdhci0 {
+&cp0_sdhci0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
bus-width = <4>;
status = "okay";
};
-&cpm_pcie0 {
+&cp0_pcie0 {
num-lanes = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_pcie_reset_pins>;
- marvell,reset-gpio = <&cpm_gpio1 0 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&cp0_pcie_reset_pins>;
+ marvell,reset-gpio = <&cp0_gpio1 0 GPIO_ACTIVE_LOW>;
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_i2c1 {
+&cp0_i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c1_pins>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_comphy {
+&cp0_comphy {
/*
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: Not connected
- * Lane 2: SFI (10G)
+ * Lane 2: SFI0 (10G)
* Lane 3: Not connected
* Lane 4: USB 3.0 host port1 (can be PCIe)
* Lane 5: Not connected
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
};
phy5 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
};
-&cpm_ethernet {
+&cp0_ethernet {
pinctrl-names = "default";
status = "okay";
};
/* 10G SFI SFP */
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
phy-mode = "sfi";
};
-&cps_sata0 {
+&cp1_sata0 {
status = "okay";
};
-&cps_usb3_0 {
+&cp1_usb3_0 {
vbus-supply = <®_usb3h0_vbus>;
status = "okay";
};
-&cps_utmi0 {
+&cp1_utmi0 {
status = "okay";
};
-&cps_pinctl {
+&cp1_pinctl {
/*
* MPP Bus:
* [0-5] TDM
@@ -234,9 +234,9 @@
0xff 0xff 0xff>;
};
-&cps_spi1 {
+&cp1_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cps_spi1_pins>;
+ pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
@@ -261,7 +261,7 @@
};
};
-&cps_comphy {
+&cp1_comphy {
/*
* CP1 Serdes Configuration:
* Lane 0: SATA 1 (RX swapped). Can be PCIe0
@@ -272,52 +272,52 @@
* Lane 5: SGMII2 - Connected to Topaz switch
*/
phy0 {
- phy-type = <PHY_TYPE_SATA1>;
- phy-invert = <PHY_POLARITY_RXD_INVERT>;
+ phy-type = <COMPHY_TYPE_SATA1>;
+ phy-invert = <COMPHY_POLARITY_RXD_INVERT>;
};
phy1 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <PHY_TYPE_UNCONNECTED>;
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_3_125G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
};
-&cps_mdio {
+&cp1_mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
};
-&cps_ethernet {
+&cp1_ethernet {
pinctrl-names = "default";
- pinctrl-0 = <&cps_1g_phy_reset>;
+ pinctrl-0 = <&cp1_1g_phy_reset>;
status = "okay";
};
/* 1G SGMII */
-&cps_eth1 {
+&cp1_eth1 {
status = "okay";
phy-mode = "sgmii";
phy = <&phy0>;
- phy-reset-gpios = <&cpm_gpio1 11 GPIO_ACTIVE_LOW>;
+ phy-reset-gpios = <&cp0_gpio1 11 GPIO_ACTIVE_LOW>;
};
/* 2.5G to Topaz switch */
-&cps_eth2 {
+&cp1_eth2 {
status = "okay";
phy-mode = "sgmii";
phy-speed = <2500>;
- phy-reset-gpios = <&cps_gpio0 24 GPIO_ACTIVE_LOW>;
+ phy-reset-gpios = <&cp1_gpio0 24 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts
index 65b30bb..51c2f23 100644
--- a/arch/arm/dts/armada-8040-db.dts
+++ b/arch/arm/dts/armada-8040-db.dts
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016 - 2021 Marvell International Ltd.
*/
/*
@@ -56,8 +19,8 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- spi0 = &cps_spi1;
+ i2c0 = &cp0_i2c0;
+ spi0 = &cp1_spi1;
};
memory@00000000 {
@@ -88,7 +51,7 @@
status = "okay";
};
-&cpm_pinctl {
+&cp0_pinctl {
/* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins
* [11] CLKOUT_MPP_11 (out)
@@ -116,7 +79,7 @@
0xe 0xe 0xe>;
};
-&cpm_comphy {
+&cp0_comphy {
/* Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: SATA0
@@ -126,77 +89,77 @@
* Lane 5: PCIe2 (x1)
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_USB3_HOST1>;
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
+ phy-type = <COMPHY_TYPE_PEX2>;
};
};
/* CON6 on CP0 expansion */
-&cpm_pcie0 {
+&cp0_pcie0 {
status = "okay";
};
-&cpm_pcie1 {
+&cp0_pcie1 {
status = "disabled";
};
/* CON5 on CP0 expansion */
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
/* CON4 on CP0 expansion */
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
/* CON9 on CP0 expansion */
-&cpm_usb3_0 {
+&cp0_usb3_0 {
status = "okay";
};
/* CON10 on CP0 expansion */
-&cpm_usb3_1 {
+&cp0_usb3_1 {
status = "okay";
};
-&cpm_utmi0 {
+&cp0_utmi0 {
status = "okay";
};
-&cpm_utmi1 {
+&cp0_utmi1 {
status = "okay";
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
bus-width = <4>;
status = "okay";
};
-&cps_pinctl {
+&cp1_pinctl {
/* MPP Bus:
* [0-11] RGMII0
* [13-16] SPI1
@@ -215,7 +178,7 @@
0xff 0xff 0xff>;
};
-&cps_comphy {
+&cp1_comphy {
/* Serdes Configuration:
* Lane 0: PCIe0 (x1)
* Lane 1: SATA0
@@ -225,42 +188,42 @@
* Lane 5: PCIe2 (x1)
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_PEX1>;
+ phy-type = <COMPHY_TYPE_PEX1>;
};
phy5 {
- phy-type = <PHY_TYPE_PEX2>;
+ phy-type = <COMPHY_TYPE_PEX2>;
};
};
/* CON6 on CP1 expansion */
-&cps_pcie0 {
+&cp1_pcie0 {
status = "okay";
};
-&cps_pcie1 {
+&cp1_pcie1 {
status = "okay";
};
/* CON5 on CP1 expansion */
-&cps_pcie2 {
+&cp1_pcie2 {
status = "okay";
};
-&cps_spi1 {
+&cp1_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cps_spi1_pins>;
+ pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
@@ -288,35 +251,35 @@
};
/* CON4 on CP1 expansion */
-&cps_sata0 {
+&cp1_sata0 {
status = "okay";
};
/* CON9 on CP1 expansion */
-&cps_usb3_0 {
+&cp1_usb3_0 {
status = "okay";
};
/* CON10 on CP1 expansion */
-&cps_usb3_1 {
+&cp1_usb3_1 {
status = "okay";
};
-&cps_utmi0 {
+&cp1_utmi0 {
status = "okay";
};
-&cpm_mdio {
+&cp0_mdio {
phy1: ethernet-phy@1 {
reg = <1>;
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index 5a046d9..2184648 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016 Marvell International Ltd.
+ * Copyright (C) 2016 - 2021 Marvell International Ltd.
*/
#include "armada-8040.dtsi" /* include SoC device tree */
@@ -15,12 +15,12 @@
};
aliases {
- i2c0 = &cpm_i2c0;
- i2c1 = &cpm_i2c1;
- spi0 = &cps_spi1;
+ i2c0 = &cp0_i2c0;
+ i2c1 = &cp0_i2c1;
+ spi0 = &cp1_spi1;
gpio0 = &ap_gpio0;
- gpio1 = &cpm_gpio0;
- gpio2 = &cpm_gpio1;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
};
memory@00000000 {
@@ -36,7 +36,7 @@
reg_usb3h0_vbus: usb3-vbus0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "reg-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -44,7 +44,7 @@
enable-active-high;
regulator-always-on;
regulator-boot-on;
- gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
+ gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
};
};
};
@@ -73,7 +73,7 @@
status = "okay";
};
-&cpm_pinctl {
+&cp0_pinctl {
/*
* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
@@ -108,59 +108,59 @@
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+ cp0_xhci_vbus_pins: cp0-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
};
- cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+ cp0_pcie_reset_pins: cp0-pcie-reset-pins {
marvell,pins = < 52 >;
marvell,function = <0>;
};
};
/* uSD slot */
-&cpm_sdhci0 {
+&cp0_sdhci0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
bus-width= <4>;
status = "okay";
};
/* PCIe x4 */
-&cpm_pcie0 {
+&cp0_pcie0 {
num-lanes = <4>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_pcie_reset_pins>;
- marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
+ pinctrl-0 = <&cp0_pcie_reset_pins>;
+ marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_i2c1 {
+&cp0_i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c1_pins>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
clock-frequency = <100000>;
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_mdio {
+&cp0_mdio {
ge_phy: ethernet-phy@0 {
reg = <0>;
};
};
-&cpm_comphy {
+&cp0_comphy {
/*
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x4)
@@ -171,49 +171,49 @@
* Lane 5: SATA1
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy3 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
};
-&cps_sata0 {
+&cp1_sata0 {
status = "okay";
};
-&cps_usb3_0 {
+&cp1_usb3_0 {
vbus-supply = <®_usb3h0_vbus>;
status = "okay";
};
-&cps_utmi0 {
+&cp1_utmi0 {
status = "okay";
};
-&cps_ethernet {
+&cp1_ethernet {
status = "okay";
};
-&cps_eth1 {
+&cp1_eth1 {
status = "okay";
phy = <&ge_phy>;
phy-mode = "sgmii";
};
-&cps_pinctl {
+&cp1_pinctl {
/*
* MPP Bus:
* [0-5] TDM
@@ -246,9 +246,9 @@
0xff 0xff 0xff>;
};
-&cps_spi1 {
+&cp1_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cps_spi1_pins>;
+ pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash@0 {
@@ -275,7 +275,7 @@
};
};
-&cps_comphy {
+&cp1_comphy {
/*
* CP1 Serdes Configuration:
* Lane 0: SGMII1
@@ -286,22 +286,23 @@
* Lane 5: SGMII3
*/
phy0 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy1 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII3>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
};
};
diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts
index 58edb5b..510fb84 100644
--- a/arch/arm/dts/armada-8040-puzzle-m801.dts
+++ b/arch/arm/dts/armada-8040-puzzle-m801.dts
@@ -16,14 +16,14 @@
};
aliases {
- i2c0 = &i2c0;
- i2c1 = &cpm_i2c0;
- i2c2 = &cpm_i2c1;
+ i2c0 = &ap_i2c0;
+ i2c1 = &cp0_i2c0;
+ i2c2 = &cp0_i2c1;
i2c3 = &i2c_switch;
- spi0 = &spi0;
+ spi0 = &ap_spi0;
gpio0 = &ap_gpio0;
- gpio1 = &cpm_gpio0;
- gpio2 = &cpm_gpio1;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
gpio3 = &sfpplus_gpio;
};
@@ -40,7 +40,7 @@
reg_usb3h0_vbus: usb3-vbus0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
- pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "reg-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -48,12 +48,12 @@
enable-active-high;
regulator-always-on;
regulator-boot-on;
- gpio = <&cpm_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
+ gpio = <&cp0_gpio1 15 GPIO_ACTIVE_HIGH>; /* GPIO[47] */
};
};
};
-&i2c0 {
+&ap_i2c0 {
status = "okay";
clock-frequency = <100000>;
@@ -83,7 +83,7 @@
0 3 0 0 0 0 0 0 0 3 >;
};
-&cpm_pinctl {
+&cp0_pinctl {
/*
* MPP Bus:
* [0-31] = 0xff: Keep default CP0_shared_pins:
@@ -118,35 +118,35 @@
0 0 0 0 0 0 0xe 0xe 0xe 0xe
0xe 0xe 0 >;
- cpm_xhci_vbus_pins: cpm-xhci-vbus-pins {
+ cp0_xhci_vbus_pins: cpm-xhci-vbus-pins {
marvell,pins = < 47 >;
marvell,function = <0>;
};
- cpm_pcie_reset_pins: cpm-pcie-reset-pins {
+ cp0_pcie_reset_pins: cpm-pcie-reset-pins {
marvell,pins = < 52 >;
marvell,function = <0>;
};
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
bus-width= <4>;
status = "okay";
};
-&cpm_pcie0 {
+&cp0_pcie0 {
num-lanes = <1>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_pcie_reset_pins>;
- marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
+ pinctrl-0 = <&cp0_pcie_reset_pins>;
+ marvell,reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
clock-frequency = <100000>;
@@ -158,9 +158,9 @@
};
};
-&cpm_i2c1 {
+&cp0_i2c1 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c1_pins>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
clock-frequency = <100000>;
@@ -172,44 +172,44 @@
};
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_ethernet {
+&cp0_ethernet {
pinctrl-names = "default";
status = "okay";
};
-&cpm_mdio {
+&cp0_mdio {
status = "okay";
- cpm_ge_phy0: ethernet-phy@1 {
+ cp0_ge_phy0: ethernet-phy@1 {
reg = <0>;
};
- cpm_ge_phy1: ethernet-phy@2 {
+ cp0_ge_phy1: ethernet-phy@2 {
reg = <1>;
};
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
phy-mode = "sfi";
};
-&cpm_eth1 {
+&cp0_eth1 {
status = "okay";
phy-mode = "sgmii";
- phy = <&cpm_ge_phy0>;
+ phy = <&cp0_ge_phy0>;
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy-mode = "sgmii";
- phy = <&cpm_ge_phy1>;
+ phy = <&cp0_ge_phy1>;
};
-&cpm_comphy {
+&cp0_comphy {
/*
* CP0 Serdes Configuration:
* Lane 0: PCIe0 (x1)
@@ -220,75 +220,75 @@
* Lane 5: SATA1
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy2 {
- phy-type = <PHY_TYPE_SATA0>;
+ phy-type = <COMPHY_TYPE_SATA0>;
};
phy3 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
- phy-type = <PHY_TYPE_SATA1>;
+ phy-type = <COMPHY_TYPE_SATA1>;
};
};
-&cps_mdio {
+&cp1_mdio {
status = "okay";
- cps_ge_phy0: ethernet-phy@3 {
+ cp1_ge_phy0: ethernet-phy@3 {
reg = <1>;
};
- cps_ge_phy1: ethernet-phy@4 {
+ cp1_ge_phy1: ethernet-phy@4 {
reg = <0>;
};
};
-&cps_pcie0 {
+&cp1_pcie0 {
num-lanes = <2>;
pinctrl-names = "default";
status = "okay";
};
-&cps_usb3_0 {
+&cp1_usb3_0 {
vbus-supply = <®_usb3h0_vbus>;
status = "okay";
};
-&cps_utmi0 {
+&cp1_utmi0 {
status = "okay";
};
-&cps_ethernet {
+&cp1_ethernet {
status = "okay";
};
-&cps_eth0 {
+&cp1_eth0 {
status = "okay";
phy-mode = "sfi";
};
-&cps_eth1 {
+&cp1_eth1 {
status = "okay";
- phy = <&cps_ge_phy0>;
+ phy = <&cp1_ge_phy0>;
phy-mode = "sgmii";
};
-&cps_eth2 {
+&cp1_eth2 {
status = "okay";
- phy = <&cps_ge_phy1>;
+ phy = <&cp1_ge_phy1>;
phy-mode = "sgmii";
};
-&cps_pinctl {
+&cp1_pinctl {
/*
* MPP Bus:
* [0-5] TDM
@@ -321,7 +321,7 @@
0xff 0xff 0xff>;
};
-&spi0 {
+&ap_spi0 {
status = "okay";
spi-flash@0 {
@@ -356,7 +356,7 @@
};
};
-&cps_comphy {
+&cp1_comphy {
/*
* CP1 Serdes Configuration:
* Lane 0: PCIe0 (x2)
@@ -367,23 +367,23 @@
* Lane 5: SGMII2
*/
phy0 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
- phy-type = <PHY_TYPE_PEX0>;
+ phy-type = <COMPHY_TYPE_PEX0>;
};
phy2 {
- phy-type = <PHY_TYPE_USB3_HOST0>;
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy3 {
- phy-type = <PHY_TYPE_SGMII1>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
phy4 {
- phy-type = <PHY_TYPE_SFI>;
+ phy-type = <COMPHY_TYPE_SFI0>;
};
phy5 {
- phy-type = <PHY_TYPE_SGMII2>;
- phy-speed = <PHY_SPEED_1_25G>;
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
};
};
diff --git a/arch/arm/dts/armada-8040.dtsi b/arch/arm/dts/armada-8040.dtsi
index 96cc112..5123742 100644
--- a/arch/arm/dts/armada-8040.dtsi
+++ b/arch/arm/dts/armada-8040.dtsi
@@ -1,43 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
*/
/*
@@ -46,12 +9,81 @@
*/
#include <dt-bindings/gpio/gpio.h>
-#include "armada-ap806-quad.dtsi"
-#include "armada-cp110-master.dtsi"
-#include "armada-cp110-slave.dtsi"
+#include "armada-common.dtsi"
+#include "armada-8k.dtsi"
+#include "armada-ap806.dtsi"
+#include "armada-ap80x-quad.dtsi"
+
+/* CP110-0 Settings */
+#define CP110_NAME cp0
+#define CP110_NUM 0
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_NUM
+
+/* CP110-1 Settings */
+#define CP110_NAME cp1
+#define CP110_NUM 1
+
+#include "armada-cp110.dtsi"
+
+#undef CP110_NAME
+#undef CP110_NUM
+
/ {
model = "Marvell Armada 8040";
compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
"marvell,armada-ap806";
};
+
+&cp0_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,8k-cpm-pinctrl";
+ bank-name ="cp0-110";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
+ marvell,function = <3>;
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = < 44 45 46 47 48 49 50 51
+ 52 53 54 55 >;
+ marvell,function = <1>;
+ };
+ cp0_pca0_pins: cp0-pca0_pins {
+ marvell,pins = <62>;
+ marvell,function = <0>;
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+};
+
+&cp1_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,8k-cps-pinctrl";
+ bank-name ="cp1-110";
+
+ cp1_ge1_rgmii_pins: cp1-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11 >;
+ marvell,function = <3>;
+ };
+ cp1_spi1_pins: cp1-spi-pins-1 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+};
diff --git a/arch/arm/dts/armada-8k.dtsi b/arch/arm/dts/armada-8k.dtsi
new file mode 100644
index 0000000..c6af9ce
--- /dev/null
+++ b/arch/arm/dts/armada-8k.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 - 2021 Marvell International Ltd.
+ */
+/* Common definitions used by Armada 8K DTs */
+
+/* This defines used to calculate the base address of each CP */
+#define CP110_BASE_OFFSET (0xf2000000)
+#define CP110_SPACE_SIZE (0x02000000)
+#define CP110_BASE (CP110_BASE_OFFSET + \
+ ((CP110_NUM % 2) * CP110_SPACE_SIZE))
+
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) \
+ (0xf6000000 + (CP110_NUM % 2) * 0x4000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) \
+ (CP110_PCIEx_CPU_MEM_BASE(iface))
+#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
diff --git a/arch/arm/dts/armada-ap806-quad.dtsi b/arch/arm/dts/armada-ap806-quad.dtsi
deleted file mode 100644
index ba43a43..0000000
--- a/arch/arm/dts/armada-ap806-quad.dtsi
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada AP806.
- */
-
-#include "armada-ap806.dtsi"
-
-/ {
- model = "Marvell Armada AP806 Quad";
- compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@000 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x000>;
- enable-method = "psci";
- };
- cpu@001 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x001>;
- enable-method = "psci";
- };
- cpu@100 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x100>;
- enable-method = "psci";
- };
- cpu@101 {
- device_type = "cpu";
- compatible = "arm,cortex-a72", "arm,armv8";
- reg = <0x101>;
- enable-method = "psci";
- };
- };
-};
diff --git a/arch/arm/dts/armada-ap806.dtsi b/arch/arm/dts/armada-ap806.dtsi
index 713c2db..f432089 100644
--- a/arch/arm/dts/armada-ap806.dtsi
+++ b/arch/arm/dts/armada-ap806.dtsi
@@ -1,274 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * Copyright (C) 2020 Marvell International Ltd.
*/
/*
* Device Tree file for Marvell Armada AP806.
*/
-#include <dt-bindings/interrupt-controller/arm-gic.h>
+/* AP806 Settings */
+#define AP_NAME ap806
-/dts-v1/;
+#include "armada-ap80x.dtsi"
/ {
model = "Marvell Armada AP806";
- compatible = "marvell,armada-ap806";
- #address-cells = <2>;
- #size-cells = <2>;
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- psci-area@4000000 {
- reg = <0x0 0x4000000 0x0 0x200000>;
- no-map;
- };
- };
-
- ap806 {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
+ AP_NAME {
config-space {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x0 0xf0000000 0x1000000>;
-
- gic: interrupt-controller@210000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- reg = <0x210000 0x10000>,
- <0x220000 0x20000>,
- <0x240000 0x20000>,
- <0x260000 0x20000>;
-
- gic_v2m0: v2m@280000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x280000 0x1000>;
- arm,msi-base-spi = <160>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m1: v2m@290000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x290000 0x1000>;
- arm,msi-base-spi = <192>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m2: v2m@2a0000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x2a0000 0x1000>;
- arm,msi-base-spi = <224>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m3: v2m@2b0000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x2b0000 0x1000>;
- arm,msi-base-spi = <256>;
- arm,msi-num-spis = <32>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
- };
-
- odmi: odmi@300000 {
- compatible = "marvell,odmi-controller";
- interrupt-controller;
- msi-controller;
- marvell,odmi-frames = <4>;
- reg = <0x300000 0x4000>,
- <0x304000 0x4000>,
- <0x308000 0x4000>,
- <0x30C000 0x4000>;
- marvell,spi-base = <128>, <136>, <144>, <152>;
- };
-
- ap_pinctl: ap-pinctl@6F4000 {
- compatible = "marvell,ap806-pinctrl";
- bank-name ="apn-806";
- reg = <0x6F4000 0x10>;
- pin-count = <20>;
- max-func = <3>;
-
- ap_i2c0_pins: i2c-pins-0 {
- marvell,pins = < 4 5 >;
- marvell,function = <3>;
- };
- ap_emmc_pins: emmc-pins-0 {
- marvell,pins = < 0 1 2 3 4 5 6 7
- 8 9 10 >;
- marvell,function = <1>;
- };
- };
-
- ap_gpio0: gpio@6F5040 {
- compatible = "marvell,orion-gpio";
- reg = <0x6F5040 0x40>;
- ngpios = <20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- xor@400000 {
- compatible = "marvell,mv-xor-v2";
- reg = <0x400000 0x1000>,
- <0x410000 0x1000>;
- msi-parent = <&gic_v2m0>;
- dma-coherent;
+ sar-reg {
+ compatible = "marvell,sample-at-reset-common",
+ "marvell,sample-at-reset-ap806";
+ reg = <0x6F8200 0x8>;
+ sar-driver = "ap806_sar";
+ sar-name = "ap806_sar";
+ status = "okay";
};
- xor@420000 {
- compatible = "marvell,mv-xor-v2";
- reg = <0x420000 0x1000>,
- <0x430000 0x1000>;
- msi-parent = <&gic_v2m0>;
- dma-coherent;
- };
-
- xor@440000 {
- compatible = "marvell,mv-xor-v2";
- reg = <0x440000 0x1000>,
- <0x450000 0x1000>;
- msi-parent = <&gic_v2m0>;
- dma-coherent;
- };
-
- xor@460000 {
- compatible = "marvell,mv-xor-v2";
- reg = <0x460000 0x1000>,
- <0x470000 0x1000>;
- msi-parent = <&gic_v2m0>;
- dma-coherent;
- };
-
- spi0: spi@510600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x510600 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <0>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ap_syscon 3>;
- status = "disabled";
- };
-
- i2c0: i2c@511000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x511000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
- clocks = <&ap_syscon 3>;
- status = "disabled";
- };
-
- uart0: serial@512000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x512000 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&ap_syscon 3>;
- status = "disabled";
- clock-frequency = <200000000>;
- };
-
- uart1: serial@512100 {
- compatible = "snps,dw-apb-uart";
- reg = <0x512100 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&ap_syscon 3>;
- status = "disabled";
-
- };
-
- ap_sdhci0: sdhci@6e0000 {
- compatible = "marvell,armada-8k-sdhci";
- reg = <0x6e0000 0x300>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- status = "disabled";
- };
-
- ap_syscon: system-controller@6f4000 {
- compatible = "marvell,ap806-system-controller",
- "syscon";
- #clock-cells = <1>;
- clock-output-names = "ap-cpu-cluster-0",
- "ap-cpu-cluster-1",
- "ap-fixed", "ap-mss";
- reg = <0x6f4000 0x1000>;
+ thermal: thermal@6f8084 {
+ compatible = "marvell,mvebu-thermal",
+ "marvell,thermal-ext-sensor";
+ reg = <0x6f8084 0x12>;
+ gain = <425>;
+ offset = <153400>;
+ divisor = <1000>;
+ status = "okay";
};
};
};
diff --git a/arch/arm/dts/armada-ap807.dtsi b/arch/arm/dts/armada-ap807.dtsi
new file mode 100644
index 0000000..a5309f3
--- /dev/null
+++ b/arch/arm/dts/armada-ap807.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP807.
+ */
+
+/* AP807 Settings */
+#define AP_NAME ap807
+
+#include "armada-ap80x.dtsi"
+
+/ {
+ model = "Marvell Armada AP807";
+
+ AP_NAME {
+ config-space {
+ sar-reg {
+ compatible = "marvell,sample-at-reset-common",
+ "marvell,sample-at-reset-ap807";
+ reg = <0x6F8200 0x8>;
+ sar-driver = "ap807_sar";
+ sar-name = "ap807_sar";
+ status = "okay";
+ };
+
+ thermal: thermal@6f8084 {
+ compatible = "marvell,mvebu-thermal",
+ "marvell,thermal-ext-sensor";
+ reg = <0x6f8084 0x12>;
+ gain = <394>;
+ offset = <128900>;
+ divisor = <1000>;
+ status = "okay";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-ap80x-quad.dtsi b/arch/arm/dts/armada-ap80x-quad.dtsi
new file mode 100644
index 0000000..1220e98
--- /dev/null
+++ b/arch/arm/dts/armada-ap80x-quad.dtsi
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP806/AP807.
+ */
+
+/ {
+ model = "Marvell Armada AP80X Quad";
+ compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@000 {
+ clocks;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ };
+ cpu@001 {
+ clocks;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x001>;
+ enable-method = "psci";
+ };
+ cpu@100 {
+ clocks;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ };
+ cpu@101 {
+ clocks;
+ u-boot,dm-pre-reloc;
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-ap80x.dtsi b/arch/arm/dts/armada-ap80x.dtsi
new file mode 100644
index 0000000..8787a87
--- /dev/null
+++ b/arch/arm/dts/armada-ap80x.dtsi
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Marvell International Ltd.
+ *
+ */
+
+/*
+ * Device Tree file for Marvell Armada AP806/AP807.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ compatible = "marvell,armada-ap806";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ psci-area@4000000 {
+ reg = <0x0 0x4000000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ AP_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+ gic: interrupt-controller@210000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x210000 0x10000>,
+ <0x220000 0x20000>,
+ <0x240000 0x20000>,
+ <0x260000 0x20000>;
+
+ gic_v2m0: v2m@280000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x280000 0x1000>;
+ arm,msi-base-spi = <160>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m1: v2m@290000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x290000 0x1000>;
+ arm,msi-base-spi = <192>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m2: v2m@2a0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2a0000 0x1000>;
+ arm,msi-base-spi = <224>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m3: v2m@2b0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2b0000 0x1000>;
+ arm,msi-base-spi = <256>;
+ arm,msi-num-spis = <32>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
+ };
+
+ odmi: odmi@300000 {
+ compatible = "marvell,odmi-controller";
+ interrupt-controller;
+ msi-controller;
+ marvell,odmi-frames = <4>;
+ reg = <0x300000 0x4000>,
+ <0x304000 0x4000>,
+ <0x308000 0x4000>,
+ <0x30C000 0x4000>;
+ marvell,spi-base = <128>, <136>, <144>, <152>;
+ };
+
+ ap_pinctl: ap-pinctl@6F4000 {
+ compatible = "marvell,ap806-pinctrl";
+ bank-name ="apn-806";
+ reg = <0x6F4000 0x10>;
+ pin-count = <20>;
+ max-func = <3>;
+
+ ap_i2c0_pins: i2c-pins-0 {
+ marvell,pins = < 4 5 >;
+ marvell,function = <3>;
+ };
+ ap_emmc_pins: emmc-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7
+ 8 9 10 12 >;
+ marvell,function = <1>;
+ };
+ };
+
+ ap_gpio0: gpio@6F5040 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x6F5040 0x40>;
+ ngpios = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ ap_spi0: spi@510600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x510600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+ };
+
+ ap_i2c0: i2c@511000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x511000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-ms = <1000>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+ };
+
+ uart0: serial@512000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512000 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+ clock-frequency = <200000000>;
+ };
+
+ uart1: serial@512100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512100 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_syscon 3>;
+ status = "disabled";
+
+ };
+
+ watchdog: watchdog@610000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x610000 0x1000>, <0x600000 0x1000>;
+ };
+
+ ap_sdhci0: sdhci@6e0000 {
+ compatible = "marvell,armada-8k-sdhci";
+ reg = <0x6e0000 0x300>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ ap_syscon: system-controller@6f4000 {
+ compatible = "marvell,ap806-system-controller",
+ "syscon";
+ #clock-cells = <1>;
+ clock-output-names = "ap-cpu-cluster-0",
+ "ap-cpu-cluster-1",
+ "ap-fixed", "ap-mss";
+ reg = <0x6f4000 0x1000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/armada-common.dtsi b/arch/arm/dts/armada-common.dtsi
new file mode 100644
index 0000000..b7dfbda
--- /dev/null
+++ b/arch/arm/dts/armada-common.dtsi
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Marvell International Ltd.
+ */
+
+/* Common definitions used by Armada 7K/8K DTs */
+#define PASTER(x, y) x ## _ ## y
+#define EVALUATOR(x, y) PASTER(x, y)
+
+/* This define used to create die label:
+ * For example:
+ * CP110 master:
+ * CP110_LABEL(spi0) -> cp0_spi0
+ * CP110 slave:
+ * CP110_LABEL(usb0) -> cp1_usb0
+ */
+#define CP110_LABEL(name) EVALUATOR(CP110_NAME, name)
+
+#define APPEND_NX(A, B) A ##-## B
+#define APPEND(A, B) APPEND_NX(A, B)
+
+#define STRINGIZE_NX(x) #x
+#define STRINGIZE(x) STRINGIZE_NX(x)
+
+/* Same idea here, but this define convert the name to string:
+ * For example:
+ * master: CP110_STRING_LABEL(ppv2) -> "cp0-ppv2"
+ * slave: CP110_STRING_LABEL(ppv2) -> "cp1-ppv2"
+ */
+#define CP110_STRING_LABEL(name) STRINGIZE(APPEND(CP110_NAME, name))
diff --git a/arch/arm/dts/armada-cp110-master.dtsi b/arch/arm/dts/armada-cp110-master.dtsi
deleted file mode 100644
index 7d0d31d..0000000
--- a/arch/arm/dts/armada-cp110-master.dtsi
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada CP110 Master.
- */
-
-#include <dt-bindings/comphy/comphy_data.h>
-
-/ {
- cp110-master {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- config-space {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges = <0x0 0x0 0xf2000000 0x2000000>;
-
- cpm_ethernet: ethernet@0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&cpm_syscon0 1 3>, <&cpm_syscon0 1 9>, <&cpm_syscon0 1 5>;
- clock-names = "pp_clk", "gop_clk", "mg_clk";
- status = "disabled";
- dma-coherent;
-
- cpm_eth0: eth0 {
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <0>;
- gop-port-id = <0>;
- status = "disabled";
- };
-
- cpm_eth1: eth1 {
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <1>;
- gop-port-id = <2>;
- status = "disabled";
- };
-
- cpm_eth2: eth2 {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <2>;
- gop-port-id = <3>;
- status = "disabled";
- };
- };
-
- cpm_mdio: mdio@12a200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x12a200 0x10>;
- device-name = "cpm-mdio";
- };
-
- cpm_xmdio: mdio@12a600 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,xmdio";
- reg = <0x12a600 0x16>;
- status = "disabled";
- device-name = "cpm-xmdio";
- };
-
- cpm_syscon0: system-controller@440000 {
- compatible = "marvell,cp110-system-controller0",
- "syscon";
- reg = <0x440000 0x1000>;
- #clock-cells = <2>;
- core-clock-output-names =
- "cpm-apll", "cpm-ppv2-core", "cpm-eip",
- "cpm-core", "cpm-nand-core";
- gate-clock-output-names =
- "cpm-audio", "cpm-communit", "cpm-nand",
- "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
- "cpm-mg-core", "cpm-xor1", "cpm-xor0",
- "cpm-gop-dp", "none", "cpm-pcie_x10",
- "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
- "cpm-sata", "cpm-sata-usb", "cpm-main",
- "cpm-sd-mmc", "none", "none",
- "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
- "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
- };
-
- cpm_pinctl: cpm-pinctl@440000 {
- compatible = "marvell,mvebu-pinctrl",
- "marvell,armada-7k-pinctrl",
- "marvell,armada-8k-cpm-pinctrl";
- bank-name ="cp0-110";
- reg = <0x440000 0x20>;
- pin-count = <63>;
- max-func = <0xf>;
-
- cpm_i2c0_pins: cpm-i2c-pins-0 {
- marvell,pins = < 37 38 >;
- marvell,function = <2>;
- };
- cpm_i2c1_pins: cpm-i2c-pins-1 {
- marvell,pins = < 35 36 >;
- marvell,function = <2>;
- };
- cpm_ge2_rgmii_pins: cpm-ge-rgmii-pins-0 {
- marvell,pins = < 44 45 46 47 48 49 50 51
- 52 53 54 55 >;
- marvell,function = <1>;
- };
- pca0_pins: cpm-pca0_pins {
- marvell,pins = <62>;
- marvell,function = <0>;
- };
- cpm_sdhci_pins: cpm-sdhi-pins-0 {
- marvell,pins = < 56 57 58 59 60 61 >;
- marvell,function = <14>;
- };
- cpm_spi0_pins: cpm-spi-pins-0 {
- marvell,pins = < 13 14 15 16 >;
- marvell,function = <3>;
- };
- };
-
- cpm_gpio0: gpio@440100 {
- compatible = "marvell,orion-gpio";
- reg = <0x440100 0x40>;
- ngpios = <32>;
- gpiobase = <20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- cpm_gpio1: gpio@440140 {
- compatible = "marvell,orion-gpio";
- reg = <0x440140 0x40>;
- ngpios = <31>;
- gpiobase = <52>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- cpm_sata0: sata@540000 {
- compatible = "marvell,armada-8k-ahci";
- reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 15>;
- status = "disabled";
- };
-
- cpm_usb3_0: usb3@500000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x500000 0x4000>;
- dma-coherent;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 22>;
- status = "disabled";
- };
-
- cpm_usb3_1: usb3@510000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x510000 0x4000>;
- dma-coherent;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 23>;
- status = "disabled";
- };
-
- cpm_spi0: spi@700600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700600 0x50>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- cell-index = <1>;
- clocks = <&cpm_syscon0 0 3>;
- status = "disabled";
- };
-
- cpm_spi1: spi@700680 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <2>;
- clocks = <&cpm_syscon0 1 21>;
- status = "disabled";
- };
-
- cpm_i2c0: i2c@701000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 21>;
- status = "disabled";
- };
-
- cpm_i2c1: i2c@701100 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpm_syscon0 1 21>;
- status = "disabled";
- };
-
- cpm_comphy: comphy@441000 {
- compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
- reg = <0x441000 0x8>,
- <0x120000 0x8>;
- mux-bitcount = <4>;
- max-lanes = <6>;
- };
-
- cpm_utmi0: utmi@580000 {
- compatible = "marvell,mvebu-utmi-2.6.0";
- reg = <0x580000 0x1000>, /* utmi-unit */
- <0x440420 0x4>, /* usb-cfg */
- <0x440440 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
- status = "disabled";
- };
-
- cpm_utmi1: utmi@581000 {
- compatible = "marvell,mvebu-utmi-2.6.0";
- reg = <0x581000 0x1000>, /* utmi-unit */
- <0x440420 0x4>, /* usb-cfg */
- <0x440444 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
- status = "disabled";
- };
-
- cpm_sdhci0: sdhci@780000 {
- compatible = "marvell,armada-8k-sdhci";
- reg = <0x780000 0x300>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
- dma-coherent;
- status = "disabled";
- };
-
- cpm_nand: nand@720000 {
- compatible = "marvell,armada-8k-nand-controller",
- "marvell,armada370-nand-controller";
- reg = <0x720000 0x54>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&cpm_syscon0 1 2>,
- <&cpm_syscon0 1 17>;
- marvell,system-controller = <&cpm_syscon0>;
- nand-enable-arbiter;
- num-cs = <1>;
- status = "disabled";
- };
-
- };
-
- cpm_pcie0: pcie@f2600000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf2600000 0 0x10000>,
- <0 0xf6f00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xf9000000 0 0xf9000000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <1>;
- clocks = <&cpm_syscon0 1 13>;
- status = "disabled";
- };
-
- cpm_pcie1: pcie@f2620000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf2620000 0 0x10000>,
- <0 0xf7f00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xf9010000 0 0xf9010000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cpm_syscon0 1 11>;
- status = "disabled";
- };
-
- cpm_pcie2: pcie@f2640000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf2640000 0 0x10000>,
- <0 0xf8f00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xf9020000 0 0xf9020000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cpm_syscon0 1 12>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/armada-cp110-slave.dtsi b/arch/arm/dts/armada-cp110-slave.dtsi
deleted file mode 100644
index 6cf2177..0000000
--- a/arch/arm/dts/armada-cp110-slave.dtsi
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPLv2 or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Device Tree file for Marvell Armada CP110 Slave.
- */
-
-#include <dt-bindings/comphy/comphy_data.h>
-
-/ {
- cp110-slave {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- config-space {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges = <0x0 0x0 0xf4000000 0x2000000>;
-
- cps_ethernet: ethernet@0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&cps_syscon0 1 3>, <&cps_syscon0 1 9>, <&cps_syscon0 1 5>;
- clock-names = "pp_clk", "gop_clk", "mg_clk";
- status = "disabled";
- dma-coherent;
-
- cps_eth0: eth0 {
- interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <0>;
- gop-port-id = <0>;
- status = "disabled";
- };
-
- cps_eth1: eth1 {
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <1>;
- gop-port-id = <2>;
- status = "disabled";
- };
-
- cps_eth2: eth2 {
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
- port-id = <2>;
- gop-port-id = <3>;
- status = "disabled";
- };
- };
-
- cps_mdio: mdio@12a200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x12a200 0x10>;
- device-name = "cps-mdio";
- };
-
- cps_xmdio: mdio@12a600 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,xmdio";
- reg = <0x12a600 0x16>;
- status = "disabled";
- device-name = "cps-xmdio";
- };
-
- cps_syscon0: system-controller@440000 {
- compatible = "marvell,cp110-system-controller0",
- "syscon";
- reg = <0x440000 0x1000>;
- #clock-cells = <2>;
- core-clock-output-names =
- "cps-apll", "cps-ppv2-core", "cps-eip",
- "cps-core", "cps-nand-core";
- gate-clock-output-names =
- "cps-audio", "cps-communit", "cps-nand",
- "cps-ppv2", "cps-sdio", "cps-mg-domain",
- "cps-mg-core", "cps-xor1", "cps-xor0",
- "cps-gop-dp", "none", "cps-pcie_x10",
- "cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
- "cps-sata", "cps-sata-usb", "cps-main",
- "cps-sd-mmc", "none", "none",
- "cps-slow-io", "cps-usb3h0", "cps-usb3h1",
- "cps-usb3dev", "cps-eip150", "cps-eip197";
- };
-
- cps_pinctl: cps-pinctl@440000 {
- compatible = "marvell,mvebu-pinctrl",
- "marvell,armada-8k-cps-pinctrl";
- bank-name ="cp1-110";
- reg = <0x440000 0x20>;
- pin-count = <63>;
- max-func = <0xf>;
-
- cps_ge1_rgmii_pins: cps-ge-rgmii-pins-0 {
- marvell,pins = < 0 1 2 3 4 5 6 7
- 8 9 10 11 >;
- marvell,function = <3>;
- };
- cps_spi1_pins: cps-spi-pins-1 {
- marvell,pins = < 13 14 15 16 >;
- marvell,function = <3>;
- };
- };
-
- cps_gpio0: gpio@440100 {
- compatible = "marvell,orion-gpio";
- reg = <0x440100 0x40>;
- ngpios = <32>;
- gpiobase = <20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- cps_gpio1: gpio@440140 {
- compatible = "marvell,orion-gpio";
- reg = <0x440140 0x40>;
- ngpios = <31>;
- gpiobase = <52>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- cps_sata0: sata@540000 {
- compatible = "marvell,armada-8k-ahci";
- reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 15>;
- status = "disabled";
- };
-
- cps_usb3_0: usb3@500000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x500000 0x4000>;
- dma-coherent;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 22>;
- status = "disabled";
- };
-
- cps_usb3_1: usb3@510000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x510000 0x4000>;
- dma-coherent;
- interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 23>;
- status = "disabled";
- };
-
- cps_xor0: xor@6a0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6a0000 0x1000>,
- <0x6b0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clocks = <&cps_syscon0 1 8>;
- };
-
- cps_xor1: xor@6c0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6c0000 0x1000>,
- <0x6d0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clocks = <&cps_syscon0 1 7>;
- };
-
- cps_spi0: spi@700600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700600 0x50>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- cell-index = <1>;
- clocks = <&cps_syscon0 0 3>;
- status = "disabled";
- };
-
- cps_spi1: spi@700680 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <2>;
- clocks = <&cps_syscon0 1 21>;
- status = "disabled";
- };
-
- cps_i2c0: i2c@701000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 21>;
- status = "disabled";
- };
-
- cps_i2c1: i2c@701100 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cps_syscon0 1 21>;
- status = "disabled";
- };
-
- cps_comphy: comphy@441000 {
- compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
- reg = <0x441000 0x8>,
- <0x120000 0x8>;
- mux-bitcount = <4>;
- max-lanes = <6>;
- };
-
- cps_utmi0: utmi@580000 {
- compatible = "marvell,mvebu-utmi-2.6.0";
- reg = <0x580000 0x1000>, /* utmi-unit */
- <0x440420 0x4>, /* usb-cfg */
- <0x440440 0x4>; /* utmi-cfg */
- utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
- status = "disabled";
- };
-
- cps_nand: nand@720000 {
- compatible = "marvell,armada-8k-nand-controller",
- "marvell,armada370-nand-controller";
- reg = <0x720000 0x54>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&cps_syscon0 1 2>,
- <&cps_syscon0 1 17>;
- marvell,system-controller = <&cps_syscon0>;
- nand-enable-arbiter;
- num-cs = <1>;
- status = "disabled";
- };
- };
-
- cps_pcie0: pcie@f4600000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf4600000 0 0x10000>,
- <0 0xfaf00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xfd000000 0 0xfd000000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <1>;
- clocks = <&cps_syscon0 1 13>;
- status = "disabled";
- };
-
- cps_pcie1: pcie@f4620000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf4620000 0 0x10000>,
- <0 0xfbf00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xfd010000 0 0xfd010000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cps_syscon0 1 11>;
- status = "disabled";
- };
-
- cps_pcie2: pcie@f4640000 {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 0xf4640000 0 0x10000>,
- <0 0xfcf00000 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 0xfd020000 0 0xfd020000 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clocks = <&cps_syscon0 1 12>;
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/armada-cp110.dtsi b/arch/arm/dts/armada-cp110.dtsi
new file mode 100644
index 0000000..abf1e4e
--- /dev/null
+++ b/arch/arm/dts/armada-cp110.dtsi
@@ -0,0 +1,359 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016- 2021 Marvell International Ltd.
+ */
+
+/*
+ * Generic Device Tree describing Marvell Armada CP-110 device
+ */
+
+#include <dt-bindings/comphy/comphy_data.h>
+
+#define U64_TO_U32_H(addr) (((addr) >> 32) & 0xffffffff)
+#define U64_TO_U32_L(addr) ((addr) & 0xffffffff)
+
+#define CP110_PCIEx_REG0_BASE(iface) \
+ (CP110_BASE + 0x600000 + (iface) * 0x20000)
+#define CP110_PCIEx_REG1_BASE(iface) \
+ (CP110_PCIEx_CPU_MEM_BASE(iface) + CP110_PCIE_MEM_SIZE(iface))
+#define CP110_PCIE_EP_REG_BASE(iface) (CP110_BASE + 0x600000 + \
+ (iface) * 0x4000)
+
+/ {
+ CP110_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 U64_TO_U32_H(CP110_BASE) U64_TO_U32_L(CP110_BASE) 0x2000000>;
+
+ CP110_LABEL(mdio): mdio@12a200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x12a200 0x10>;
+ device-name = CP110_STRING_LABEL(mdio);
+ status = "disabled";
+ };
+
+ CP110_LABEL(xmdio): mdio@12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x200>;
+ device-name = CP110_STRING_LABEL(xmdio);
+ status = "disabled";
+ };
+
+ CP110_LABEL(sar-reg) {
+ compatible = "marvell,sample-at-reset-common",
+ "marvell,sample-at-reset-cp110";
+ reg = <0x400200 0x8>;
+ sar-driver = "cp110_sar";
+ sar-name = CP110_STRING_LABEL(sar);
+ status = "okay";
+ };
+
+ CP110_LABEL(syscon0): system-controller@440000 {
+ compatible = "marvell,cp110-system-controller0",
+ "syscon";
+ reg = <0x440000 0x1000>;
+ #clock-cells = <2>;
+ core-clock-output-names =
+ "cpm-apll", "cpm-ppv2-core", "cpm-eip",
+ "cpm-core", "cpm-nand-core";
+ gate-clock-output-names =
+ "cpm-audio", "cpm-communit", "cpm-nand",
+ "cpm-ppv2", "cpm-sdio", "cpm-mg-domain",
+ "cpm-mg-core", "cpm-xor1", "cpm-xor0",
+ "cpm-gop-dp", "none", "cpm-pcie_x10",
+ "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
+ "cpm-sata", "cpm-sata-usb", "cpm-main",
+ "cpm-sd-mmc", "none", "none",
+ "cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
+ "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
+ };
+
+ CP110_LABEL(pinctl): pinctl@440000 {
+ compatible = "marvell,mvebu-pinctrl";
+ reg = <0x440000 0x20>;
+ pin-count = <63>;
+ max-func = <0xf>;
+ };
+
+ CP110_LABEL(gpio0): gpio@440100 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x440100 0x40>;
+ ngpios = <32>;
+ gpiobase = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ CP110_LABEL(gpio1): gpio@440140 {
+ compatible = "marvell,orion-gpio";
+ reg = <0x440140 0x40>;
+ ngpios = <31>;
+ gpiobase = <52>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ CP110_LABEL(sata0): sata@540000 {
+ compatible = "marvell,armada-8k-ahci";
+ reg = <0x540000 0x30000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 15>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(usb3_0): usb3@500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 22>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(usb3_1): usb3@510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 23>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(spi0): spi@700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ cell-index = <1>;
+ spi-max-frequency = <50000000>;
+ clocks = <&CP110_LABEL(syscon0) 0 3>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(spi1): spi@700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <2>;
+ spi-max-frequency = <50000000>;
+ clocks = <&CP110_LABEL(syscon0) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c0): i2c@701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(i2c1): i2c@701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP110_LABEL(syscon0) 1 21>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(mss_i2c0): i2c@211000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x211000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(comphy): comphy@441000 {
+ compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
+ reg = <0x441000 0x8>,
+ <0x120000 0x8>;
+ mux-bitcount = <4>;
+ max-lanes = <6>;
+ };
+
+ CP110_LABEL(utmi): utmi@580000 {
+ compatible = "marvell,mvebu-utmi";
+ reg = <0x580000 0xc>; /* utmi-common-pll */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ CP110_LABEL(utmi0): utmi@58000c {
+ compatible = "marvell,mvebu-utmi-2.6.0";
+ reg = <0x58000c 0x100>,/* utmi-unit */
+ <0x440420 0x4>, /* usb-cfg */
+ <0x440440 0x4>; /* utmi-cfg */
+ utmi-port = <UTMI_PHY_TO_USB3_HOST0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(utmi1): utmi@58100c {
+ compatible = "marvell,mvebu-utmi-2.6.0";
+ reg = <0x58100c 0x100>,/* utmi-unit */
+ <0x440420 0x4>, /* usb-cfg */
+ <0x440444 0x4>; /* utmi-cfg */
+ utmi-port = <UTMI_PHY_TO_USB3_HOST1>;
+ status = "disabled";
+ };
+ };
+
+ CP110_LABEL(sdhci0): sdhci@780000 {
+ compatible = "marvell,armada-8k-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ CP110_LABEL(nand): nand@720000 {
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&CP110_LABEL(syscon0) 1 2>;
+ nand-enable-arbiter;
+ num-cs = <1>;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+ marvell,system-controller = <&CP110_LABEL(syscon0)>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(ethernet): ethernet@0 {
+ compatible = "marvell,armada-7k-pp22";
+ reg = <0x0 0x100000>, <0x129000 0xb000>;
+ clocks = <&CP110_LABEL(syscon0) 1 3>, <&CP110_LABEL(syscon0) 1 9>, <&CP110_LABEL(syscon0) 1 5>;
+ clock-names = "pp_clk", "gop_clk", "mg_clk";
+ status = "disabled";
+ dma-coherent;
+
+ CP110_LABEL(eth0): eth0 {
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <0>;
+ gop-port-id = <0>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth1): eth1 {
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <1>;
+ gop-port-id = <2>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(eth2): eth2 {
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ port-id = <2>;
+ gop-port-id = <3>;
+ status = "disabled";
+ };
+ };
+ };
+
+ CP110_LABEL(pcie0): pcie0@600000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg =
+ <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(0)) 0 0x10000>,
+ /* Last 512KB of mem space */
+ <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(0)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(0)) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(0))
+ U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(0)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(0))
+ U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(0))
+ U64_TO_U32_H(CP110_PCIE_MEM_SIZE(0)) U64_TO_U32_L(CP110_PCIE_MEM_SIZE(0))>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clocks = <&CP110_LABEL(syscon0) 1 13>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie1): pcie1@620000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg =
+ <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(1)) 0 0x10000>,
+ /* Last 512KB of mem space */
+ <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(1)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(1)) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(1))
+ U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(1))
+ U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(1)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(1))
+ U64_TO_U32_L(CP110_PCIE_MEM_SIZE(1))>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&CP110_LABEL(syscon0) 1 11>;
+ status = "disabled";
+ };
+
+ CP110_LABEL(pcie2): pcie2@640000 {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg =
+ <U64_TO_U32_H(CP110_PCIEx_REG0_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG0_BASE(2)) 0 0x10000>,
+ /* Last 64KB of mem space */
+ <U64_TO_U32_H(CP110_PCIEx_REG1_BASE(2)) U64_TO_U32_L(CP110_PCIEx_REG1_BASE(2)) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* non-prefetchable memory */
+ <CP110_PCIE_BUS_MEM_CFG U64_TO_U32_H(CP110_PCIEx_BUS_MEM_BASE(2))
+ U64_TO_U32_L(CP110_PCIEx_BUS_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIEx_CPU_MEM_BASE(2))
+ U64_TO_U32_L(CP110_PCIEx_CPU_MEM_BASE(2)) U64_TO_U32_H(CP110_PCIE_MEM_SIZE(2))
+ U64_TO_U32_L(CP110_PCIE_MEM_SIZE(2))>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clocks = <&CP110_LABEL(syscon0) 1 12>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts
new file mode 100644
index 0000000..fcfcd15
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb-A.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "CN9130-CRB-A";
+ compatible = "marvell,cn9130-crb-A",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy3 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+
+ phy5 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
+ };
+};
+
+&cp0_pcie0 {
+ num-lanes = <4>;
+ /* non-prefetchable memory */
+ ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
+ status = "disabled";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts
new file mode 100644
index 0000000..b681b60
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb-B.dts
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "CN9130-CRB-B";
+ compatible = "marvell,cn9130-crb-B",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_SATA0>;
+ };
+
+ phy3 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ };
+
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+
+ phy5 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ phy-speed = <COMPHY_SPEED_3_125G>;
+ };
+};
+
+&cp0_sata0 {
+ status = "okay";
+};
+
+&cp0_pcie0 {
+ num-lanes = <1>;
+ /* non-prefetchable memory */
+ ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
+ status = "disabled";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/cn9130-crb.dtsi b/arch/arm/dts/cn9130-crb.dtsi
new file mode 100644
index 0000000..b229725
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb.dtsi
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130.dtsi" /* include SoC device tree */
+
+/ {
+ model = "CN9130-CRB";
+ compatible = "marvell,cn9130-crb",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ spi0 = &cp0_spi1;
+ gpio0 = &ap_gpio0;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ cp0 {
+ config-space {
+ sdhci@780000 {
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ };
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp0_gpio1 18 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&cp0_gpio1 22 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/*
+ * AP related configuration
+ */
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-10, 12]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 3 1 0 0 0 0 0 0 3 >;
+};
+
+/* on-board eMMC - U6 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>;
+ bus-width = <8>;
+ status = "okay";
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_pinctl {
+ /* MPP Bus:
+ * [0-11] RGMII1
+ * [12] GPIO
+ * [13-16] SPI1
+ * [17-32] GPIO
+ * [33] SD_PWR_OFF
+ * [34] CP_PCIE0_CLKREQn
+ * [35-38] I2C1 I2C0
+ * [39] GPIO
+ * [40-43] SMI/XSMI
+ * [44-46] GPIO
+ * [47] UART1_TX
+ * [48] GPIO
+ * [49] SD_HST_18_EN
+ * [50] GPIO
+ * [51] SD_PWR_0
+ * [52] PCIE_RSTn
+ * [53] UART1_RX
+ * [54] GPIO
+ * [55] SD_DT
+ * [56-61] SDIO
+ *
+ * Note that CRB board revisions have different MPP configurations.
+ * r1p2 has SPI flash on MPP[30:27] and r1p3.1, which is the latest
+ * board revision, has it mapped to MPP[16:13].
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 3 3 3 3 3 3 3 3 3 3
+ 3 3 0 3 3 3 3 0 0 0
+ 0 0 0 0 0 0 0 0 0 0
+ 0 0 0 6 9 2 2 2 2 0
+ 8 8 8 8 0 0 0 7 0 0xa
+ 0 0xa 9 7 0 0xb 0xe 0xe 0xe 0xe
+ 0xe 0xe 0xe>;
+
+ cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
+ marvell,pins = < 55 >;
+ marvell,function = <0>;
+ };
+
+ cp0_spi1_pins_crb: cp0-spi-pins-crb {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+
+ cp0_smi_pins_crb: cp0-smi-pins-crb {
+ marvell,pins = < 40 41 >;
+ marvell,function = <8>;
+ };
+
+ cp0_xsmi_pins_crb: cp0-xsmi-pins-crb {
+ marvell,pins = < 42 43 >;
+ marvell,function = <8>;
+ };
+
+};
+
+/*
+ * CP0
+ */
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp0_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c1_pins>;
+ status = "okay";
+};
+
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins_crb>;
+ bus-width = <4>;
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ status = "okay";
+};
+
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi1_pins_crb>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>, /* CS0 */
+ <0 0xffffffff>, /* CS1 */
+ <0 0xffffffff>, /* CS2 */
+ <0 0xffffffff>; /* CS3 */
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor", "spi-flash";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cp0_utmi0 {
+ status = "okay";
+};
+
+&cp0_utmi1 {
+ status = "okay";
+};
+
+&cp0_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_smi_pins_crb>;
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ switch6: ethernet-switch@6 {
+ reg = <6>;
+ };
+};
+
+&cp0_xmdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_xsmi_pins_crb>;
+ status = "okay";
+ nbaset_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "sfi";
+};
+
+&cp0_eth1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_ge1_rgmii_pins>;
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_eth2 {
+ /* Disable it for now, as mainline does not support this IF yet */
+ status = "disabled";
+ phy = <&nbaset_phy0>;
+};
diff --git a/arch/arm/dts/cn9130-db-A.dts b/arch/arm/dts/cn9130-db-A.dts
new file mode 100644
index 0000000..90d6e4a
--- /dev/null
+++ b/arch/arm/dts/cn9130-db-A.dts
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell CN9130 development board (CP NOR) setup(A)";
+
+ aliases {
+ spi0 = &cp0_spi1;
+ };
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_pinctl {
+ /* MPP Bus:
+ * [0-11] RGMII1
+ * [12] GPIO GE-IN
+ * [13-16] SPI1
+ * [17-27] NAND
+ * [28] MSS_GPIO[5] XXX:(mode nr from a3900)
+ * [29-30] SATA
+ * [31] MSS_GPIO[4] XXX:(mode nr from a3900)
+ * [32,34] SMI
+ * [33] SDIO
+ * [35-36] I2C1
+ * [37-38] I2C0
+ * [39-43] SDIOctrl
+ * [44-55] RGMII2
+ * [56-62] SDIO
+ */
+
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 3 3 3 3 3 3 3 3 3 3
+ 3 3 0 3 3 3 3 1 1 1
+ 1 1 1 1 1 1 1 1 3 9
+ 9 3 7 6 7 2 2 2 2 1
+ 1 1 1 1 1 1 1 1 1 1
+ 1 1 1 1 1 1 0xe 0xe 0xe 0xe
+ 0xe 0xe 0xe>;
+};
+
+/* U54 */
+&cp0_nand {
+ status = "disabled";
+};
+
+/* U55 */
+&cp0_spi1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/cn9130-db-B.dts b/arch/arm/dts/cn9130-db-B.dts
new file mode 100644
index 0000000..fb52aa8
--- /dev/null
+++ b/arch/arm/dts/cn9130-db-B.dts
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#include "cn9130-db.dtsi"
+
+/ {
+ model = "Marvell CN9130 development board (CP NAND) setup(B)";
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_pinctl {
+ /* MPP Bus:
+ * [0-11] RGMII1
+ * [12] GPIO GE-IN
+ * [13-14] SPI1
+ * [15-27] NAND
+ * [28] MSS_GPIO[5] XXX:(mode nr from a3900)
+ * [29-30] SATA
+ * [31] MSS_GPIO[4] XXX:(mode nr from a3900)
+ * [32,34] SMI
+ * [33] SDIO
+ * [35-36] I2C1
+ * [37-38] I2C0
+ * [39-43] SDIOctrl
+ * [44-55] RGMII2
+ * [56-62] SDIO
+ */
+
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 3 3 3 3 3 3 3 3 3 3
+ 3 3 0 2 3 1 1 1 1 1
+ 1 1 1 1 1 1 1 1 3 9
+ 9 3 7 6 7 2 2 2 2 1
+ 1 1 1 1 1 1 1 1 1 1
+ 1 1 1 1 1 1 0xe 0xe 0xe 0xe
+ 0xe 0xe 0xe>;
+};
+
+/* U54 */
+&cp0_nand {
+ status = "okay";
+};
+
+/* U55 */
+&cp0_spi1 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/cn9130-db-dev-info.dtsi b/arch/arm/dts/cn9130-db-dev-info.dtsi
new file mode 100644
index 0000000..68e9c0b
--- /dev/null
+++ b/arch/arm/dts/cn9130-db-dev-info.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+/ {
+ /* This should go only into devel boards */
+ compatible = "marvell,cp110";
+ sar {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sar_fields {
+ compatible = "marvell,sample-at-reset";
+ reg = <0x4c 0x4e>;
+ chip_count = <2>;
+ bit_width = <5>;
+ freq {
+ key = "freq";
+ description = "CPU/DDR and PIDI frequencies";
+ start-bit = <0>;
+ bit-length = <4>;
+ option-cnt = <3>;
+ options = "0x0", "CPU/DDR = 0x0: 2000/1200 Mhz, PIDI = 0: 1Ghz",
+ "0x2", "CPU/DDR = 0x6: 2200/1200 Mhz, PIDI = 0: 1Ghz",
+ "0x4", "CPU/DDR = 0xD: 1600/1200 Mhz, PIDI = 0: 1Ghz";
+ default = <0x2>;
+ status = "okay";
+ };
+ boot_mode {
+ key = "boot_mode";
+ description = "Boot mode options";
+ start-bit = <4>;
+ bit-length = <6>;
+ option-cnt = <4>;
+ options = "0xE", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-4bit\t(supported configuration: B)",
+ "0xF", "CP0_NAND PIDI BW-8bit, PS-4KB, ECC-8bit\t(supported configuration: B)",
+ "0x2A", "AP_EMMC",
+ "0x32", "CP1_SPI_1 24bits";
+ default = <0x32>;
+ status = "okay";
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/cn9130-db.dtsi b/arch/arm/dts/cn9130-db.dtsi
new file mode 100644
index 0000000..1b28732
--- /dev/null
+++ b/arch/arm/dts/cn9130-db.dtsi
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#include "cn9130.dtsi" /* include SoC device tree */
+#include "cn9130-db-dev-info.dtsi"
+
+/ {
+ model = "DB-CN-9130";
+ compatible = "marvell,cn9130-db", "marvell,cn91xx", "marvell,cn9030-vd",
+ "marvell,cn9030", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ i2c0 = &cp0_i2c0;
+ gpio0 = &ap_gpio0;
+ gpio1 = &cp0_gpio0;
+ gpio2 = &cp0_gpio1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ cp0 {
+ config-space {
+ i2c@701000 {
+ /* U36 */
+ expander0: pca953x@21 {
+ compatible = "nxp,pca9555";
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ status = "okay";
+ };
+ };
+ sdhci@780000 {
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+ };
+
+ ap_reg_mmc_vccq: ap_mmc_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap_mmc_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+ cp0_reg_usb3_current_lim0:cp0_usb3_current_limiter@0 {
+ compatible = "regulator-fixed";
+ regulator-min-microamp = <900000>;
+ regulator-max-microamp = <900000>;
+ regulator-force-boot-off;
+ gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_reg_usb3_current_lim1: cp0_usb3_current_limiter@1 {
+ compatible = "regulator-fixed";
+ regulator-min-microamp = <900000>;
+ regulator-max-microamp = <900000>;
+ regulator-force-boot-off;
+ gpio = <&expander0 5 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/*
+ * AP related configuration
+ */
+&ap_pinctl {
+ /* MPP Bus:
+ * SDIO [0-10, 12]
+ * UART0 [11,19]
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 1 1 1 1 1 1 1 1 1 1
+ 1 3 1 0 0 0 0 0 0 3 >;
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ap_emmc_pins>;
+ vqmmc-supply = <&ap_reg_mmc_vccq>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ mmc-hs400-1_8v;
+ status = "okay";
+};
+
+/*
+ * CP related configuration
+ */
+&cp0_pinctl {
+ cp0_nand_pins: cp0-nand-pins {
+ marvell,pins = <15 16 17 18 19 20 21 22 23 24 25 26 27 >;
+ marvell,function = <1>;
+ };
+ cp0_nand_rb: cp0-nand-rb {
+ marvell,pins = < 13 >;
+ marvell,function = <2>;
+ };
+};
+
+/*
+ * CP0
+ */
+&cp0_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp0_i2c1 {
+ status = "okay";
+};
+
+/* CON 28 */
+&cp0_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+/* U54 */
+&cp0_nand {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_nand_pins &cp0_nand_rb>;
+ status = "disabled";
+};
+
+/* U55 */
+&cp0_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>, /* CS0 */
+ <0 0xffffffff>, /* CS1 */
+ <0 0xffffffff>, /* CS2 */
+ <0 0xffffffff>; /* CS3 */
+ status = "disabled";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor", "spi-flash";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy3 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+
+ phy5 {
+ phy-type = <COMPHY_TYPE_SATA1>;
+ };
+};
+
+/* SLM-1521-V2, CON6 */
+&cp0_pcie0 {
+ num-lanes = <4>;
+ status = "disabled";
+};
+
+&cp0_mdio {
+ status = "okay";
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+ status = "okay";
+ phy-mode = "sfi";
+};
+
+/* CON56 */
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+/* CON57 */
+&cp0_eth2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
+
+/* SLM-1521-V2, CON2 */
+&cp0_sata0 {
+ status = "okay";
+};
+
+&cp0_utmi0 {
+ status = "okay";
+};
+
+&cp0_utmi1 {
+ status = "okay";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ vbus-supply = <&cp0_reg_usb3_vbus0>;
+ current-limiter = <&cp0_reg_usb3_current_lim0>;
+ vbus-disable-delay = <500>;
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ vbus-supply = <&cp0_reg_usb3_vbus1>;
+ current-limiter = <&cp0_reg_usb3_current_lim1>;
+ vbus-disable-delay = <500>;
+};
+
+&cp0_pcie0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/cn9130.dtsi b/arch/arm/dts/cn9130.dtsi
new file mode 100644
index 0000000..68b767a
--- /dev/null
+++ b/arch/arm/dts/cn9130.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+/*
+ * Device Tree file for the CN 9030 SoC, made of an AP806 Quad and
+ * one CP110.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-common.dtsi"
+#include "armada-ap807.dtsi"
+#include "armada-ap80x-quad.dtsi"
+
+/* This defines used to calculate the base address of each CP */
+#define CP110_BASE_OFFSET (0xf2000000)
+#define CP110_SPACE_SIZE (0x02000000)
+#define CP110_BASE (CP110_BASE_OFFSET + \
+ (CP110_NUM * CP110_SPACE_SIZE))
+
+#define CP110_PCIE_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
+
+/* CP110-0 Settings */
+#define CP110_NAME cp0
+#define CP110_NUM 0
+#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+ (0xe0000000 + (iface - 1) * 0x1000000))
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "Marvell CN 9030";
+ compatible = "marvell,armada70x0", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_pinctl {
+ compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
+ bank-name ="cp0-110";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = < 35 36 >;
+ marvell,function = <2>;
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
+ marvell,function = <3>;
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = < 44 45 46 47 48 49 50 51
+ 52 53 54 55 >;
+ marvell,function = <1>;
+ };
+ cp0_pca0_pins: cp0-pca0_pins {
+ marvell,pins = <62>;
+ marvell,function = <0>;
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+};
diff --git a/arch/arm/dts/cn9131-db-A.dts b/arch/arm/dts/cn9131-db-A.dts
new file mode 100644
index 0000000..81aff17
--- /dev/null
+++ b/arch/arm/dts/cn9131-db-A.dts
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#include "cn9130-db-A.dts"
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell CN9131 development board (CP NOR) setup(A)";
+ compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp1_comphy {
+ /* Serdes Configuration:
+ * Lane 0: PCIe0 (x2)
+ * Lane 1: PCIe0 (x2)
+ * Lane 2: unconnected
+ * Lane 3: USB1
+ * Lane 4: SFP (port 0)
+ * Lane 5: SATA1
+ */
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+ phy1 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+ phy2 {
+ phy-type = <COMPHY_TYPE_UNCONNECTED>;
+ };
+ phy3 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ };
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+ phy5 {
+ phy-type = <COMPHY_TYPE_SATA1>;
+ };
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
+ status = "okay";
+ phy-mode = "sfi"; /* lane-4 */
+ marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>;
+};
diff --git a/arch/arm/dts/cn9131-db-B.dts b/arch/arm/dts/cn9131-db-B.dts
new file mode 100644
index 0000000..0269183
--- /dev/null
+++ b/arch/arm/dts/cn9131-db-B.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#include "cn9130-db-B.dts"
+#include "cn9131-db.dtsi"
+
+/ {
+ model = "Marvell CN9131 development board (CP NAND) setup(B)";
+ compatible = "marvell,cn9131-db", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp1_comphy {
+ /* Serdes Configuration:
+ * Lane 0: PCIe0 (x2)
+ * Lane 1: PCIe0 (x2)
+ * Lane 2: SFI (port 0)
+ * Lane 3: USB1
+ * Lane 4: SGMII (port 1)
+ * Lane 5: SATA1
+ */
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+ phy1 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+ phy2 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+ phy3 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ };
+ phy4 {
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+ phy5 {
+ phy-type = <COMPHY_TYPE_SATA1>;
+ };
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* 3310 RJ45 CON55 */
+&cp1_eth0 {
+ status = "okay";
+ phy-mode = "sfi"; /* lane-2 */
+ phy = <&sfi_phy8>; /* required by 3310 fw download */
+};
+
+/* CON50 */
+&cp1_eth1 {
+ status = "okay";
+ phy-mode = "sgmii"; /* lane-4 */
+ marvell,sfp-tx-disable-gpio = <&cp1_gpio0 9 GPIO_ACTIVE_HIGH>;
+};
+
+&cp1_xmdio {
+ status = "okay";
+ sfi_phy8: ethernet-phy@8 {
+ reg = <8>;
+ };
+};
diff --git a/arch/arm/dts/cn9131-db.dtsi b/arch/arm/dts/cn9131-db.dtsi
new file mode 100644
index 0000000..5057605
--- /dev/null
+++ b/arch/arm/dts/cn9131-db.dtsi
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#undef CP110_NAME
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-1 Settings */
+#define CP110_NAME cp1
+#define CP110_NUM 1
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe2000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "Marvell CN9131 development board";
+ compatible = "marvell,cn9131-db";
+
+ aliases {
+ gpio3 = &cp1_gpio0;
+ gpio4 = &cp1_gpio1;
+ };
+
+ cp1 {
+ config-space {
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ gpio = <&cp1_gpio0 3 GPIO_ACTIVE_HIGH>;
+ };
+ cp1_reg_usb3_current_lim0: cp1_usb3_current_limiter@0 {
+ compatible = "regulator-fixed";
+ regulator-min-microamp = <900000>;
+ regulator-max-microamp = <900000>;
+ regulator-force-boot-off;
+ gpio = <&cp1_gpio0 2 GPIO_ACTIVE_HIGH>;
+ };
+ cp1_pcie_reset_pins: cp1-pcie-reset-pins {
+ marvell,pins = <0>;
+ marvell,function = <0>;
+ };
+ };
+ };
+};
+
+&cp1_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+/* CON40 */
+&cp1_pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_pcie_reset_pins>;
+ marvell,reset-gpio = <&cp1_gpio0 0 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ num-lanes = <2>;
+ /* non-prefetchable memory */
+ ranges = <0x82000000 0 0xe2000000 0 0xe2000000 0 0xf00000>;
+};
+
+&cp1_pinctl {
+ compatible = "marvell,mvebu-pinctrl",
+ "marvell,cp115-standalone-pinctrl";
+ bank-name ="cp1-110";
+
+ /* MPP Bus:
+ * [0-12] GPIO
+ * [13-16] SPI1
+ * [17-27] GPIO (Default)
+ * [28] SATA1_PRESENT_ACTIVEn
+ * [29-34] GPIO (Default)
+ * [35-36] xSMI
+ * [37-38] I2C0
+ * [39-62] GPIO
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x3 0x3 0x3 0x3 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x7 0x7 0x2 0x2 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 >;
+
+ cp1_i2c0_pins: cp1-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+ cp1_spi0_pins: cp1-spi-pins-0 {
+ marvell,pins = < 13 14 15 16 >;
+ marvell,function = <3>;
+ };
+ cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+ marvell,pins = <3>;
+ marvell,function = <0>;
+ };
+};
+
+/* CON32 */
+&cp1_sata0 {
+ status = "okay";
+};
+
+/* U24 */
+&cp1_spi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_spi0_pins>;
+ reg = <0x700680 0x50>, /* control */
+ <0x2000000 0x1000000>, /* CS0 */
+ <0 0xffffffff>, /* CS1 */
+ <0 0xffffffff>, /* CS2 */
+ <0 0xffffffff>; /* CS3 */
+ status = "okay";
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor", "spi-flash";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+/* CON58 */
+&cp1_usb3_1 {
+ vbus-supply = <&cp1_reg_usb3_vbus0>;
+ current-limiter = <&cp1_reg_usb3_current_lim0>;
+ vbus-disable-delay = <500>;
+ status = "okay";
+};
+
+&cp1_utmi1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/cn9132-db-A.dts b/arch/arm/dts/cn9132-db-A.dts
new file mode 100644
index 0000000..ba9b8a2
--- /dev/null
+++ b/arch/arm/dts/cn9132-db-A.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#include "cn9131-db-A.dts"
+#include "cn9132-db.dtsi"
+
+/ {
+ model = "Marvell CN9132 development board (CP NOR) setup(A)";
+ compatible = "marvell,cn9132-db", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
diff --git a/arch/arm/dts/cn9132-db-B.dts b/arch/arm/dts/cn9132-db-B.dts
new file mode 100644
index 0000000..e126e23
--- /dev/null
+++ b/arch/arm/dts/cn9132-db-B.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#include "cn9131-db-B.dts"
+#include "cn9132-db.dtsi"
+
+/ {
+ model = "Marvell CN9132 development board (CP NAND) setup(B)";
+ compatible = "marvell,cn9132-db-B", "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
diff --git a/arch/arm/dts/cn9132-db.dtsi b/arch/arm/dts/cn9132-db.dtsi
new file mode 100644
index 0000000..d51a4d0
--- /dev/null
+++ b/arch/arm/dts/cn9132-db.dtsi
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018-2021 Marvell International Ltd.
+ */
+
+#undef CP110_NAME
+#undef CP110_NUM
+#undef CP110_PCIE_MEM_SIZE
+#undef CP110_PCIEx_CPU_MEM_BASE
+#undef CP110_PCIEx_BUS_MEM_BASE
+
+/* CP110-2 Settings */
+#define CP110_NAME cp2
+#define CP110_NUM 2
+#define CP110_PCIE_MEM_SIZE(iface) (0xf00000)
+#define CP110_PCIEx_CPU_MEM_BASE(iface) (0xe5000000 + (iface) * 0x1000000)
+#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
+
+#include "armada-cp110.dtsi"
+
+/ {
+ model = "Marvell CN9132 development board";
+ compatible = "marvell,cn9132-db";
+
+ aliases {
+ gpio5 = &cp2_gpio0;
+ gpio6 = &cp2_gpio1;
+ };
+
+ cp2 {
+ config-space {
+ sdhci@780000 {
+ vqmmc-supply = <&cp2_reg_sd_vccq>;
+ };
+
+ cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ gpio = <&cp2_gpio0 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ regulator-force-boot-off;
+ gpio = <&cp2_gpio0 3 GPIO_ACTIVE_HIGH>;
+ };
+ cp2_reg_sd_vccq: cp2_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp2_sd_vcc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ /* cp2_mpp49 */
+ gpios = <&cp2_gpio1 17 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+ cp2_reg_usb3_current_lim0: cp2_usb3_current_limiter@0 {
+ compatible = "regulator-fixed";
+ regulator-min-microamp = <900000>;
+ regulator-max-microamp = <900000>;
+ regulator-force-boot-off;
+ gpio = <&cp2_gpio0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_reg_usb3_current_lim1: cp2_usb3_current_limiter@1 {
+ compatible = "regulator-fixed";
+ regulator-min-microamp = <900000>;
+ regulator-max-microamp = <900000>;
+ regulator-force-boot-off;
+ gpio = <&cp2_gpio0 1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+};
+
+&cp2_i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&cp2_pinctl {
+ compatible = "marvell,mvebu-pinctrl",
+ "marvell,cp115-standalone-pinctrl";
+ bank-name ="cp2-110";
+
+ /* MPP Bus:
+ * [0-26] GPIO
+ * [27] SATA0_PRESENT_ACTIVEn
+ * [28] SATA1_PRESENT_ACTIVEn
+ * [29-31, 33] GPIO (Default)
+ * [32,34] SMI
+ * [37-38] I2C0
+ * [39-53] GPIO
+ * [54] SD_CRD_RSTn (out)
+ * [55] SD_CRD_DT (in)
+ * [56-62] SDIO
+ */
+ /* 0 1 2 3 4 5 6 7 8 9 */
+ pin-func = < 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x9 0x9 0x0
+ 0x0 0x0 0x8 0x0 0x8 0x0 0x0 0x2 0x2 0x0
+ 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
+ 0x0 0x0 0x0 0x0 0xa 0xb 0xe 0xe 0xe 0xe
+ 0xe 0xe 0xe >;
+
+ cp2_i2c0_pins: cp2-i2c-pins-0 {
+ marvell,pins = < 37 38 >;
+ marvell,function = <2>;
+ };
+
+ cp2_sdhci_pins: cp2-sdhi-pins-0 {
+ marvell,pins = < 56 57 58 59 60 61 >;
+ marvell,function = <14>;
+ };
+};
+
+&cp2_usb3_0 {
+ status = "okay";
+ vbus-supply = <&cp2_reg_usb3_vbus0>;
+ current-limiter = <&cp2_reg_usb3_current_lim0>;
+ vbus-disable-delay = <500>;
+};
+
+/* SLM-1521-V2, CON11 */
+&cp2_usb3_1 {
+ status = "okay";
+ vbus-supply = <&cp2_reg_usb3_vbus1>;
+ current-limiter = <&cp2_reg_usb3_current_lim1>;
+ vbus-disable-delay = <500>;
+ status = "okay";
+};
+
+&cp2_utmi0 {
+ status = "okay";
+};
+
+&cp2_utmi1 {
+ status = "okay";
+};
+
+&cp2_comphy {
+ phy0 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <COMPHY_TYPE_PEX0>;
+ };
+
+ phy2 {
+ phy-type = <COMPHY_TYPE_SATA0>;
+ };
+
+ phy3 {
+ phy-type = <COMPHY_TYPE_USB3_HOST1>;
+ };
+
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI0>;
+ phy-speed = <COMPHY_SPEED_10_3125G>;
+ };
+
+ phy5 {
+ phy-type = <COMPHY_TYPE_PEX2>;
+ };
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp2_eth0 {
+ status = "okay";
+ phy-mode = "sfi";
+};
+
+/* SLM-1521-V2, CON6 */
+&cp2_pcie0 {
+ /* non-prefetchable memory */
+ ranges =<0x82000000 0 0xe5000000 0 0xe5000000 0 0x1000000>;
+ num-lanes = <2>;
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON8 */
+&cp2_pcie2 {
+ num-lanes = <1>;
+ status = "okay";
+};
+
+&cp2_pinctl {
+};
+
+/* SLM-1521-V2, CON4 */
+&cp2_sata0 {
+ status = "okay";
+};
+
+/* CON 2 on SLM-1683 - microSD */
+&cp2_sdhci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_sdhci_pins>;
+ bus-width = <4>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
index 2de3b85..b54e8e6 100644
--- a/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
+++ b/arch/arm/dts/imx6q-bx50v3-uboot.dtsi
@@ -35,3 +35,15 @@
};
};
};
+
+/*
+ * This is not done in imx6q-ba16.dtsi, since that file is shared
+ * with the kernel and the kernel should not reset the PHY, since
+ * it lacks support for configuring the reserved registeres to
+ * avoid a board specific voltage peak issue.
+ */
+&fec {
+ phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <0>;
+};
diff --git a/arch/arm/dts/imx6qdl-gw552x.dtsi b/arch/arm/dts/imx6qdl-gw552x.dtsi
index 5462907..7935b10 100644
--- a/arch/arm/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/dts/imx6qdl-gw552x.dtsi
@@ -120,7 +120,6 @@
regulator-name = "5P0V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
- regulator-always-on;
};
};
diff --git a/arch/arm/dts/imx7-cm-u-boot.dtsi b/arch/arm/dts/imx7-cm-u-boot.dtsi
new file mode 100644
index 0000000..c6970c5
--- /dev/null
+++ b/arch/arm/dts/imx7-cm-u-boot.dtsi
@@ -0,0 +1,17 @@
+/{
+ aliases {
+ mmc0 = &usdhc1;
+ };
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx7-cm.dts b/arch/arm/dts/imx7-cm.dts
new file mode 100644
index 0000000..da20a63
--- /dev/null
+++ b/arch/arm/dts/imx7-cm.dts
@@ -0,0 +1,432 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+//
+// Copyright 2021 Ronetix GmbH
+
+/dts-v1/;
+
+#include "imx7d.dtsi"
+
+/ {
+ model = "Ronetix iMX7-CM Board";
+ compatible = "ronetix,imx7-cm", "fsl,imx7d";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ /* DRAM size runtime extracted from the DDRC registers */
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led {
+ label = "gpio-led";
+ gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_sd1_vmmc: regulator-sd1-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_SD1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <200000>;
+ off-on-delay-us = <20000>;
+ enable-active-high;
+ };
+
+ reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_pwr>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg2_pwr>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&clks {
+ assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
+ <&clks IMX7D_CLKO2_ROOT_DIV>;
+ assigned-clock-parents = <&clks IMX7D_CKIL>;
+ assigned-clock-rates = <0>, <32768>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ };
+ };
+};
+
+&qspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_1>;
+ status = "okay";
+ ddrsmp=<0>;
+
+ flash0: mx25l25645g@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ reg = <0>;
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@8 {
+ compatible = "fsl,pfuze3000";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1a {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+ /* use sw1c_reg to align with pfuze100/pfuze200 */
+ sw1c_reg: sw1b {
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1475000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1850000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3 {
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1650000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vldo2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ };
+
+ vgen3_reg: vccsd {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: v33 {
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&uart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usbotg1 {
+ vbus-supply = <®_usb_otg1_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usb_otg2_vbus>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+/* SD card */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+ bus-width = <4>;
+ tuning-step = <2>;
+ vmmc-supply = <®_sd1_vmmc>;
+ wakeup-source;
+ no-1-8-v;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ no-1-8-v;
+ fsl,tuning-step = <2>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
+ MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
+ MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3
+ MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3
+ MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
+ MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
+ MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
+ MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
+ MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
+ MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
+ MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
+ MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
+ MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
+ MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
+ MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
+ MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
+ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 /* ETH_RESET */
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioledsgrp {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x59
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x59
+ >;
+ };
+
+ pinctrl_usbotg1_pwr: usbotg_pwr {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14
+ >;
+ };
+
+ pinctrl_usbotg2_pwr: usbotg_pwr {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x14
+ >;
+ };
+
+ pinctrl_usdhc1_gpio: usdhc1_gpiogrp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15 /* CD */
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* Vmmc */
+ MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 /* VSELECT */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x59
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x19
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
+ >;
+ };
+
+ pinctrl_qspi1_1: qspi1grp_1 {
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x51
+ MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x51
+ MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x51
+ MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x51
+ MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x51
+ MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x51
+ >;
+ };
+};
+
+&iomuxc_lpsr {
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
index 6d80a52..73ddfda 100644
--- a/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-beacon-kit-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright 2020 Compass Electronics Group, LLC
*/
+#include "imx8mm-u-boot.dtsi"
+
/ {
wdt-reboot {
compatible = "wdt-reboot";
@@ -11,32 +13,6 @@
};
};
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
@@ -63,15 +39,6 @@
&gpio5 {
u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
};
&pca6416_0 {
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
new file mode 100644
index 0000000..3226a24
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
@@ -0,0 +1,255 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&fec1 {
+ phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+};
+
+&wdog1 {
+ u-boot,dm-spl;
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ flash {
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x920000>;
+ entry = <0x920000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fip {
+ description = "Trusted Firmware FIP";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x40310000>;
+
+ fip_blob: blob-ext{
+ filename = "fip.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf", "fip";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mm-cl-iot-gate.dts b/arch/arm/dts/imx8mm-cl-iot-gate.dts
new file mode 100644
index 0000000..62e8d03
--- /dev/null
+++ b/arch/arm/dts/imx8mm-cl-iot-gate.dts
@@ -0,0 +1,553 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx8mm.dtsi"
+
+/ {
+ model = "CompuLab IOT-GATE-iMX8";
+ compatible = "sb-iotgimx8", "cpl,ucm-imx8m-mini", "fsl,imx8mm-evk", "fsl,imx8mm";
+
+ chosen {
+ bootargs = "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200";
+ stdout-path = &uart3;
+ };
+
+ reg_vusb_5v: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VUSB_5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ regulator-boot-on;
+ enable-active-high;
+ };
+
+ reg_usdhc2_vqmmc: regulator-usdhc2_1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "usdhc2_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ startup-delay-us = <100>;
+ off-on-delay-us = <12000>;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ at803x,led-act-blind-workaround;
+ at803x,eee-okay;
+ at803x,vddio-1p8v;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ eeprom@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ pagesize = <16>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ rtc@69 {
+ compatible = "abracon,ab1805";
+ reg = <0x69>;
+ pagesize = <16>;
+ status = "okay";
+ };
+
+ pmic@4b {
+ compatible = "rohm,bd71837";
+ reg = <0x4b>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+
+ gpo {
+ rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */
+ };
+
+ regulators {
+ bd71837,pmic-buck2-uses-i2c-dvs;
+ bd71837,pmic-buck2-dvs-voltage = <1000000>,
+ <900000>,
+ <0>; /* VDD_ARM: Run-Idle */
+ buck1_reg: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck3_reg: BUCK3 {
+ regulator-name = "BUCK3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ buck4_reg: BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "BUCK7";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "BUCK8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ regulator-name = "LDO5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo7_reg: LDO7 {
+ regulator-name = "LDO7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ };
+ };
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec1>;
+ reg = <0x50>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <11 8>;
+ status = "okay";
+
+ port {
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ op-sink-microwatt = <15000000>;
+ self-powered;
+ };
+ };
+};
+
+&i2c3 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ status = "disabled";
+};
+
+&i2c4 {/* Expansion connector I2C */
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ pca9555: gpio@22 {
+ compatible = "nxp,pca9555";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart3 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ hnp-disable;
+ srp-disable;
+ adp-disable;
+ usb-role-switch;
+ vbus-supply = <®_vusb_5v>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ fsl,wp-controller;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ no-1-8-v;
+ mmc-ddr-1_8v;
+ non-removable;
+ vqmmc-supply = <®_usdhc2_vqmmc>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ /* USB VBUS enable GPIO */
+ MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x00
+ >;
+ };
+
+ pinctrl_hog_1: hoggrp-1 {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
+ MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x140
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
+ >;
+ };
+
+ pinctrl_flexspi0: flexspi0grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c4
+ MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84
+ MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84
+ MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84
+ MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84
+ MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_typec1: typec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
+ >;
+ };
+
+ pinctrl_uart3: uart1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
+ MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
+ MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
+ MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
+ MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
+ MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
+ MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
+ MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
+ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
+ MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
+ MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 3701557..f200afa 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright 2019 NXP
*/
+#include "imx8mm-u-boot.dtsi"
+
/ {
binman: binman {
multiple-images;
@@ -22,41 +24,6 @@
};
};
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
-
®_usdhc2_vmmc {
u-boot,off-on-delay-us = <20000>;
};
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi
new file mode 100644
index 0000000..8b67bcf
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include "imx8mm-icore-mx8mm-u-boot.dtsi"
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts
new file mode 100644
index 0000000..5389d6f
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "imx8mm.dtsi"
+#include "imx8mm-icore-mx8mm.dtsi"
+
+/ {
+ model = "Engicam i.Core MX8M Mini C.TOUCH 2.0";
+ compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm",
+ "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* SD */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ no-1-8-v;
+ pm-ignore-notify;
+ keep-power-in-suspend;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi
new file mode 100644
index 0000000..8b67bcf
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include "imx8mm-icore-mx8mm-u-boot.dtsi"
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts
new file mode 100644
index 0000000..a4a2ada
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "imx8mm.dtsi"
+#include "imx8mm-icore-mx8mm.dtsi"
+
+/ {
+ model = "Engicam i.Core MX8M Mini EDIMM2.2 Starter Kit";
+ compatible = "engicam,icore-mx8mm-edimm2.2", "engicam,icore-mx8mm",
+ "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* SD */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ no-1-8-v;
+ pm-ignore-notify;
+ keep-power-in-suspend;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm-u-boot.dtsi
new file mode 100644
index 0000000..e7d179d
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm-u-boot.dtsi
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include "imx8mm-u-boot.dtsi"
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_100mhz {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3_200mhz {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi
new file mode 100644
index 0000000..b40148d
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm.dtsi
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutons(India)
+ */
+
+/ {
+ compatible = "engicam,icore-mx8mm", "fsl,imx8mm";
+};
+
+&A53_0 {
+ cpu-supply = <®_buck4>;
+};
+
+&A53_1 {
+ cpu-supply = <®_buck4>;
+};
+
+&A53_2 {
+ cpu-supply = <®_buck4>;
+};
+
+&A53_3 {
+ cpu-supply = <®_buck4>;
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <3>;
+ reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic@8 {
+ compatible = "nxp,pf8121a";
+ reg = <0x08>;
+
+ regulators {
+ reg_ldo1: ldo1 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_ldo2: ldo2 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_ldo3: ldo3 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_ldo4: ldo4 {
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_buck1: buck1 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_buck2: buck2 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_buck3: buck3 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_buck4: buck4 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_buck5: buck5 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_buck6: buck6 {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_buck7: buck7 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_vsnvs: vsnvs {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
+ MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
+ MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
+ MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
+ MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
+ MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
+ MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
+ MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
+ MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
+ MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
+ MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
+ >;
+ };
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi
new file mode 100644
index 0000000..f833d9d
--- /dev/null
+++ b/arch/arm/dts/imx8mm-u-boot.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+&{/soc@0} {
+ u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
+};
+
+&aips1 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
+
+&aips2 {
+ u-boot,dm-spl;
+};
+
+&aips3 {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&osc_24m {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
index a4487e2..1a15d6a 100644
--- a/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
@@ -3,40 +3,7 @@
* Copyright 2021 Gateworks Corporation
*/
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
+#include "imx8mm-u-boot.dtsi"
&gpio1 {
u-boot,dm-spl;
diff --git a/arch/arm/dts/imx8mm-venice-u-boot.dtsi b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
index 5b06d87..42b2903 100644
--- a/arch/arm/dts/imx8mm-venice-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-venice-u-boot.dtsi
@@ -3,6 +3,8 @@
* Copyright 2021 Gateworks Corporation
*/
+#include "imx8mm-u-boot.dtsi"
+
/ {
wdt-reboot {
compatible = "wdt-reboot";
@@ -11,41 +13,6 @@
};
};
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
-
&gpio1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
index 249b0f8..67c31c4 100644
--- a/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-verdin-u-boot.dtsi
@@ -2,6 +2,9 @@
/*
* Copyright 2020 Toradex
*/
+
+#include "imx8mm-u-boot.dtsi"
+
/ {
wdt-reboot {
compatible = "wdt-reboot";
@@ -10,27 +13,6 @@
};
};
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
&gpio1 {
u-boot,dm-spl;
};
@@ -55,15 +37,6 @@
u-boot,dm-spl;
};
-&iomuxc {
- u-boot,dm-spl;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
&pinctrl_i2c1 {
u-boot,dm-spl;
};
@@ -84,11 +57,6 @@
u-boot,dm-spl;
};
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
&{/soc@0/bus@30800000/i2c@30a20000/pmic} {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq-cm-u-boot.dtsi b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
new file mode 100644
index 0000000..476a8e3
--- /dev/null
+++ b/arch/arm/dts/imx8mq-cm-u-boot.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ flash {
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+ };
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x910000>;
+ entry = <0x910000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "NAME";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mq-cm.dts b/arch/arm/dts/imx8mq-cm.dts
new file mode 100644
index 0000000..cacbe47
--- /dev/null
+++ b/arch/arm/dts/imx8mq-cm.dts
@@ -0,0 +1,535 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright 2017 NXP
+ * Copyright (C) 2021 Ronetix, Ilko Iliev <iliev@ronetix.at>
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+ model = "Ronetix iMX8M-CM SoM";
+ compatible = "ronetix,imx8mq-cm", "fsl,imx8mq";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000 0 0x40000000>;
+ };
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ pmic_osc: clock-pmic {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic_osc";
+ };
+
+ osc_32k: clock-osc-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "osc_32k";
+ };
+
+ reg_usdhc2_vmmc: regulator-vsd-3v3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reg_usdhc2>;
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_1 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_2 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&A53_3 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&ddrc {
+ operating-points-v2 = <&ddrc_opp_table>;
+
+ ddrc_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-25M {
+ opp-hz = /bits/ 64 <25000000>;
+ };
+
+ opp-100M {
+ opp-hz = /bits/ 64 <100000000>;
+ };
+
+ /*
+ * On imx8mq B0 PLL can't be bypassed so low bus is 166M
+ */
+ opp-166M {
+ opp-hz = /bits/ 64 <166935483>;
+ };
+
+ opp-800M {
+ opp-hz = /bits/ 64 <800000000>;
+ };
+ };
+};
+
+&dphy {
+ status = "okay";
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <10000>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71837";
+ reg = <0x4b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ rohm,reset-snvs-powered;
+
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3_reg: BUCK3 {
+ // BUCK5 in datasheet
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck4_reg: BUCK4 {
+ // BUCK6 in datasheet
+ regulator-name = "buck4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // BUCK7 in datasheet
+ regulator-name = "buck5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // BUCK8 in datasheet
+ regulator-name = "buck6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck7_reg: BUCK7 {
+ regulator-name = "buck7";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ };
+
+ buck8_reg: BUCK8 {
+ regulator-name = "buck8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <1600000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ i2c_eeprom: i2c_eeprom@50 {
+ compatible = "microchip,24lc512";
+ reg = <0x50>;
+ pagesize = <128>;
+ };
+};
+
+&lcdif {
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ status = "okay";
+};
+
+&pgc_gpu {
+ power-supply = <&buck3_reg>;
+};
+
+&qspi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ mx25l51245g: flash@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <29000000>;
+ };
+};
+
+&snvs_pwrkey {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usdhc1 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
+ assigned-clock-rates = <400000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ vqmmc-supply = <&buck7_reg>;
+ bus-width = <8>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ status = "okay";
+};
+
+&usdhc2 {
+ assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
+ assigned-clock-rates = <200000000>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_buck2: vddarmgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
+ >;
+
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
+ MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
+ >;
+ };
+
+ pinctrl_pmic: pmicgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x80 /* PMIC intr */
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
+ MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
+ MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
+ MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
+ MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
+ MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
+
+ >;
+ };
+
+ pinctrl_reg_usdhc2: regusdhc2gpiogrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_wdog: wdog1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
diff --git a/arch/arm/dts/k3-am64-ddr.dtsi b/arch/arm/dts/k3-am64-ddr.dtsi
new file mode 100644
index 0000000..026a547
--- /dev/null
+++ b/arch/arm/dts/k3-am64-ddr.dtsi
@@ -0,0 +1,2205 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ memorycontroller: memorycontroller@f300000 {
+ compatible = "ti,am64-ddrss";
+ reg = <0x00 0x0f308000 0x00 0x4000>,
+ <0x00 0x43014000 0x00 0x100>;
+ reg-names = "cfg", "ctrl_mmr_lp4";
+ power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
+ <&k3_pds 55 TI_SCI_PD_SHARED>;
+ clocks = <&k3_clks 138 0>, <&k3_clks 16 4>;
+ ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>;
+ ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>;
+ ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>;
+
+ u-boot,dm-spl;
+
+ ti,ctl-data = <
+ DDRSS_CTL_0_DATA
+ DDRSS_CTL_1_DATA
+ DDRSS_CTL_2_DATA
+ DDRSS_CTL_3_DATA
+ DDRSS_CTL_4_DATA
+ DDRSS_CTL_5_DATA
+ DDRSS_CTL_6_DATA
+ DDRSS_CTL_7_DATA
+ DDRSS_CTL_8_DATA
+ DDRSS_CTL_9_DATA
+ DDRSS_CTL_10_DATA
+ DDRSS_CTL_11_DATA
+ DDRSS_CTL_12_DATA
+ DDRSS_CTL_13_DATA
+ DDRSS_CTL_14_DATA
+ DDRSS_CTL_15_DATA
+ DDRSS_CTL_16_DATA
+ DDRSS_CTL_17_DATA
+ DDRSS_CTL_18_DATA
+ DDRSS_CTL_19_DATA
+ DDRSS_CTL_20_DATA
+ DDRSS_CTL_21_DATA
+ DDRSS_CTL_22_DATA
+ DDRSS_CTL_23_DATA
+ DDRSS_CTL_24_DATA
+ DDRSS_CTL_25_DATA
+ DDRSS_CTL_26_DATA
+ DDRSS_CTL_27_DATA
+ DDRSS_CTL_28_DATA
+ DDRSS_CTL_29_DATA
+ DDRSS_CTL_30_DATA
+ DDRSS_CTL_31_DATA
+ DDRSS_CTL_32_DATA
+ DDRSS_CTL_33_DATA
+ DDRSS_CTL_34_DATA
+ DDRSS_CTL_35_DATA
+ DDRSS_CTL_36_DATA
+ DDRSS_CTL_37_DATA
+ DDRSS_CTL_38_DATA
+ DDRSS_CTL_39_DATA
+ DDRSS_CTL_40_DATA
+ DDRSS_CTL_41_DATA
+ DDRSS_CTL_42_DATA
+ DDRSS_CTL_43_DATA
+ DDRSS_CTL_44_DATA
+ DDRSS_CTL_45_DATA
+ DDRSS_CTL_46_DATA
+ DDRSS_CTL_47_DATA
+ DDRSS_CTL_48_DATA
+ DDRSS_CTL_49_DATA
+ DDRSS_CTL_50_DATA
+ DDRSS_CTL_51_DATA
+ DDRSS_CTL_52_DATA
+ DDRSS_CTL_53_DATA
+ DDRSS_CTL_54_DATA
+ DDRSS_CTL_55_DATA
+ DDRSS_CTL_56_DATA
+ DDRSS_CTL_57_DATA
+ DDRSS_CTL_58_DATA
+ DDRSS_CTL_59_DATA
+ DDRSS_CTL_60_DATA
+ DDRSS_CTL_61_DATA
+ DDRSS_CTL_62_DATA
+ DDRSS_CTL_63_DATA
+ DDRSS_CTL_64_DATA
+ DDRSS_CTL_65_DATA
+ DDRSS_CTL_66_DATA
+ DDRSS_CTL_67_DATA
+ DDRSS_CTL_68_DATA
+ DDRSS_CTL_69_DATA
+ DDRSS_CTL_70_DATA
+ DDRSS_CTL_71_DATA
+ DDRSS_CTL_72_DATA
+ DDRSS_CTL_73_DATA
+ DDRSS_CTL_74_DATA
+ DDRSS_CTL_75_DATA
+ DDRSS_CTL_76_DATA
+ DDRSS_CTL_77_DATA
+ DDRSS_CTL_78_DATA
+ DDRSS_CTL_79_DATA
+ DDRSS_CTL_80_DATA
+ DDRSS_CTL_81_DATA
+ DDRSS_CTL_82_DATA
+ DDRSS_CTL_83_DATA
+ DDRSS_CTL_84_DATA
+ DDRSS_CTL_85_DATA
+ DDRSS_CTL_86_DATA
+ DDRSS_CTL_87_DATA
+ DDRSS_CTL_88_DATA
+ DDRSS_CTL_89_DATA
+ DDRSS_CTL_90_DATA
+ DDRSS_CTL_91_DATA
+ DDRSS_CTL_92_DATA
+ DDRSS_CTL_93_DATA
+ DDRSS_CTL_94_DATA
+ DDRSS_CTL_95_DATA
+ DDRSS_CTL_96_DATA
+ DDRSS_CTL_97_DATA
+ DDRSS_CTL_98_DATA
+ DDRSS_CTL_99_DATA
+ DDRSS_CTL_100_DATA
+ DDRSS_CTL_101_DATA
+ DDRSS_CTL_102_DATA
+ DDRSS_CTL_103_DATA
+ DDRSS_CTL_104_DATA
+ DDRSS_CTL_105_DATA
+ DDRSS_CTL_106_DATA
+ DDRSS_CTL_107_DATA
+ DDRSS_CTL_108_DATA
+ DDRSS_CTL_109_DATA
+ DDRSS_CTL_110_DATA
+ DDRSS_CTL_111_DATA
+ DDRSS_CTL_112_DATA
+ DDRSS_CTL_113_DATA
+ DDRSS_CTL_114_DATA
+ DDRSS_CTL_115_DATA
+ DDRSS_CTL_116_DATA
+ DDRSS_CTL_117_DATA
+ DDRSS_CTL_118_DATA
+ DDRSS_CTL_119_DATA
+ DDRSS_CTL_120_DATA
+ DDRSS_CTL_121_DATA
+ DDRSS_CTL_122_DATA
+ DDRSS_CTL_123_DATA
+ DDRSS_CTL_124_DATA
+ DDRSS_CTL_125_DATA
+ DDRSS_CTL_126_DATA
+ DDRSS_CTL_127_DATA
+ DDRSS_CTL_128_DATA
+ DDRSS_CTL_129_DATA
+ DDRSS_CTL_130_DATA
+ DDRSS_CTL_131_DATA
+ DDRSS_CTL_132_DATA
+ DDRSS_CTL_133_DATA
+ DDRSS_CTL_134_DATA
+ DDRSS_CTL_135_DATA
+ DDRSS_CTL_136_DATA
+ DDRSS_CTL_137_DATA
+ DDRSS_CTL_138_DATA
+ DDRSS_CTL_139_DATA
+ DDRSS_CTL_140_DATA
+ DDRSS_CTL_141_DATA
+ DDRSS_CTL_142_DATA
+ DDRSS_CTL_143_DATA
+ DDRSS_CTL_144_DATA
+ DDRSS_CTL_145_DATA
+ DDRSS_CTL_146_DATA
+ DDRSS_CTL_147_DATA
+ DDRSS_CTL_148_DATA
+ DDRSS_CTL_149_DATA
+ DDRSS_CTL_150_DATA
+ DDRSS_CTL_151_DATA
+ DDRSS_CTL_152_DATA
+ DDRSS_CTL_153_DATA
+ DDRSS_CTL_154_DATA
+ DDRSS_CTL_155_DATA
+ DDRSS_CTL_156_DATA
+ DDRSS_CTL_157_DATA
+ DDRSS_CTL_158_DATA
+ DDRSS_CTL_159_DATA
+ DDRSS_CTL_160_DATA
+ DDRSS_CTL_161_DATA
+ DDRSS_CTL_162_DATA
+ DDRSS_CTL_163_DATA
+ DDRSS_CTL_164_DATA
+ DDRSS_CTL_165_DATA
+ DDRSS_CTL_166_DATA
+ DDRSS_CTL_167_DATA
+ DDRSS_CTL_168_DATA
+ DDRSS_CTL_169_DATA
+ DDRSS_CTL_170_DATA
+ DDRSS_CTL_171_DATA
+ DDRSS_CTL_172_DATA
+ DDRSS_CTL_173_DATA
+ DDRSS_CTL_174_DATA
+ DDRSS_CTL_175_DATA
+ DDRSS_CTL_176_DATA
+ DDRSS_CTL_177_DATA
+ DDRSS_CTL_178_DATA
+ DDRSS_CTL_179_DATA
+ DDRSS_CTL_180_DATA
+ DDRSS_CTL_181_DATA
+ DDRSS_CTL_182_DATA
+ DDRSS_CTL_183_DATA
+ DDRSS_CTL_184_DATA
+ DDRSS_CTL_185_DATA
+ DDRSS_CTL_186_DATA
+ DDRSS_CTL_187_DATA
+ DDRSS_CTL_188_DATA
+ DDRSS_CTL_189_DATA
+ DDRSS_CTL_190_DATA
+ DDRSS_CTL_191_DATA
+ DDRSS_CTL_192_DATA
+ DDRSS_CTL_193_DATA
+ DDRSS_CTL_194_DATA
+ DDRSS_CTL_195_DATA
+ DDRSS_CTL_196_DATA
+ DDRSS_CTL_197_DATA
+ DDRSS_CTL_198_DATA
+ DDRSS_CTL_199_DATA
+ DDRSS_CTL_200_DATA
+ DDRSS_CTL_201_DATA
+ DDRSS_CTL_202_DATA
+ DDRSS_CTL_203_DATA
+ DDRSS_CTL_204_DATA
+ DDRSS_CTL_205_DATA
+ DDRSS_CTL_206_DATA
+ DDRSS_CTL_207_DATA
+ DDRSS_CTL_208_DATA
+ DDRSS_CTL_209_DATA
+ DDRSS_CTL_210_DATA
+ DDRSS_CTL_211_DATA
+ DDRSS_CTL_212_DATA
+ DDRSS_CTL_213_DATA
+ DDRSS_CTL_214_DATA
+ DDRSS_CTL_215_DATA
+ DDRSS_CTL_216_DATA
+ DDRSS_CTL_217_DATA
+ DDRSS_CTL_218_DATA
+ DDRSS_CTL_219_DATA
+ DDRSS_CTL_220_DATA
+ DDRSS_CTL_221_DATA
+ DDRSS_CTL_222_DATA
+ DDRSS_CTL_223_DATA
+ DDRSS_CTL_224_DATA
+ DDRSS_CTL_225_DATA
+ DDRSS_CTL_226_DATA
+ DDRSS_CTL_227_DATA
+ DDRSS_CTL_228_DATA
+ DDRSS_CTL_229_DATA
+ DDRSS_CTL_230_DATA
+ DDRSS_CTL_231_DATA
+ DDRSS_CTL_232_DATA
+ DDRSS_CTL_233_DATA
+ DDRSS_CTL_234_DATA
+ DDRSS_CTL_235_DATA
+ DDRSS_CTL_236_DATA
+ DDRSS_CTL_237_DATA
+ DDRSS_CTL_238_DATA
+ DDRSS_CTL_239_DATA
+ DDRSS_CTL_240_DATA
+ DDRSS_CTL_241_DATA
+ DDRSS_CTL_242_DATA
+ DDRSS_CTL_243_DATA
+ DDRSS_CTL_244_DATA
+ DDRSS_CTL_245_DATA
+ DDRSS_CTL_246_DATA
+ DDRSS_CTL_247_DATA
+ DDRSS_CTL_248_DATA
+ DDRSS_CTL_249_DATA
+ DDRSS_CTL_250_DATA
+ DDRSS_CTL_251_DATA
+ DDRSS_CTL_252_DATA
+ DDRSS_CTL_253_DATA
+ DDRSS_CTL_254_DATA
+ DDRSS_CTL_255_DATA
+ DDRSS_CTL_256_DATA
+ DDRSS_CTL_257_DATA
+ DDRSS_CTL_258_DATA
+ DDRSS_CTL_259_DATA
+ DDRSS_CTL_260_DATA
+ DDRSS_CTL_261_DATA
+ DDRSS_CTL_262_DATA
+ DDRSS_CTL_263_DATA
+ DDRSS_CTL_264_DATA
+ DDRSS_CTL_265_DATA
+ DDRSS_CTL_266_DATA
+ DDRSS_CTL_267_DATA
+ DDRSS_CTL_268_DATA
+ DDRSS_CTL_269_DATA
+ DDRSS_CTL_270_DATA
+ DDRSS_CTL_271_DATA
+ DDRSS_CTL_272_DATA
+ DDRSS_CTL_273_DATA
+ DDRSS_CTL_274_DATA
+ DDRSS_CTL_275_DATA
+ DDRSS_CTL_276_DATA
+ DDRSS_CTL_277_DATA
+ DDRSS_CTL_278_DATA
+ DDRSS_CTL_279_DATA
+ DDRSS_CTL_280_DATA
+ DDRSS_CTL_281_DATA
+ DDRSS_CTL_282_DATA
+ DDRSS_CTL_283_DATA
+ DDRSS_CTL_284_DATA
+ DDRSS_CTL_285_DATA
+ DDRSS_CTL_286_DATA
+ DDRSS_CTL_287_DATA
+ DDRSS_CTL_288_DATA
+ DDRSS_CTL_289_DATA
+ DDRSS_CTL_290_DATA
+ DDRSS_CTL_291_DATA
+ DDRSS_CTL_292_DATA
+ DDRSS_CTL_293_DATA
+ DDRSS_CTL_294_DATA
+ DDRSS_CTL_295_DATA
+ DDRSS_CTL_296_DATA
+ DDRSS_CTL_297_DATA
+ DDRSS_CTL_298_DATA
+ DDRSS_CTL_299_DATA
+ DDRSS_CTL_300_DATA
+ DDRSS_CTL_301_DATA
+ DDRSS_CTL_302_DATA
+ DDRSS_CTL_303_DATA
+ DDRSS_CTL_304_DATA
+ DDRSS_CTL_305_DATA
+ DDRSS_CTL_306_DATA
+ DDRSS_CTL_307_DATA
+ DDRSS_CTL_308_DATA
+ DDRSS_CTL_309_DATA
+ DDRSS_CTL_310_DATA
+ DDRSS_CTL_311_DATA
+ DDRSS_CTL_312_DATA
+ DDRSS_CTL_313_DATA
+ DDRSS_CTL_314_DATA
+ DDRSS_CTL_315_DATA
+ DDRSS_CTL_316_DATA
+ DDRSS_CTL_317_DATA
+ DDRSS_CTL_318_DATA
+ DDRSS_CTL_319_DATA
+ DDRSS_CTL_320_DATA
+ DDRSS_CTL_321_DATA
+ DDRSS_CTL_322_DATA
+ DDRSS_CTL_323_DATA
+ DDRSS_CTL_324_DATA
+ DDRSS_CTL_325_DATA
+ DDRSS_CTL_326_DATA
+ DDRSS_CTL_327_DATA
+ DDRSS_CTL_328_DATA
+ DDRSS_CTL_329_DATA
+ DDRSS_CTL_330_DATA
+ DDRSS_CTL_331_DATA
+ DDRSS_CTL_332_DATA
+ DDRSS_CTL_333_DATA
+ DDRSS_CTL_334_DATA
+ DDRSS_CTL_335_DATA
+ DDRSS_CTL_336_DATA
+ DDRSS_CTL_337_DATA
+ DDRSS_CTL_338_DATA
+ DDRSS_CTL_339_DATA
+ DDRSS_CTL_340_DATA
+ DDRSS_CTL_341_DATA
+ DDRSS_CTL_342_DATA
+ DDRSS_CTL_343_DATA
+ DDRSS_CTL_344_DATA
+ DDRSS_CTL_345_DATA
+ DDRSS_CTL_346_DATA
+ DDRSS_CTL_347_DATA
+ DDRSS_CTL_348_DATA
+ DDRSS_CTL_349_DATA
+ DDRSS_CTL_350_DATA
+ DDRSS_CTL_351_DATA
+ DDRSS_CTL_352_DATA
+ DDRSS_CTL_353_DATA
+ DDRSS_CTL_354_DATA
+ DDRSS_CTL_355_DATA
+ DDRSS_CTL_356_DATA
+ DDRSS_CTL_357_DATA
+ DDRSS_CTL_358_DATA
+ DDRSS_CTL_359_DATA
+ DDRSS_CTL_360_DATA
+ DDRSS_CTL_361_DATA
+ DDRSS_CTL_362_DATA
+ DDRSS_CTL_363_DATA
+ DDRSS_CTL_364_DATA
+ DDRSS_CTL_365_DATA
+ DDRSS_CTL_366_DATA
+ DDRSS_CTL_367_DATA
+ DDRSS_CTL_368_DATA
+ DDRSS_CTL_369_DATA
+ DDRSS_CTL_370_DATA
+ DDRSS_CTL_371_DATA
+ DDRSS_CTL_372_DATA
+ DDRSS_CTL_373_DATA
+ DDRSS_CTL_374_DATA
+ DDRSS_CTL_375_DATA
+ DDRSS_CTL_376_DATA
+ DDRSS_CTL_377_DATA
+ DDRSS_CTL_378_DATA
+ DDRSS_CTL_379_DATA
+ DDRSS_CTL_380_DATA
+ DDRSS_CTL_381_DATA
+ DDRSS_CTL_382_DATA
+ DDRSS_CTL_383_DATA
+ DDRSS_CTL_384_DATA
+ DDRSS_CTL_385_DATA
+ DDRSS_CTL_386_DATA
+ DDRSS_CTL_387_DATA
+ DDRSS_CTL_388_DATA
+ DDRSS_CTL_389_DATA
+ DDRSS_CTL_390_DATA
+ DDRSS_CTL_391_DATA
+ DDRSS_CTL_392_DATA
+ DDRSS_CTL_393_DATA
+ DDRSS_CTL_394_DATA
+ DDRSS_CTL_395_DATA
+ DDRSS_CTL_396_DATA
+ DDRSS_CTL_397_DATA
+ DDRSS_CTL_398_DATA
+ DDRSS_CTL_399_DATA
+ DDRSS_CTL_400_DATA
+ DDRSS_CTL_401_DATA
+ DDRSS_CTL_402_DATA
+ DDRSS_CTL_403_DATA
+ DDRSS_CTL_404_DATA
+ DDRSS_CTL_405_DATA
+ DDRSS_CTL_406_DATA
+ DDRSS_CTL_407_DATA
+ DDRSS_CTL_408_DATA
+ DDRSS_CTL_409_DATA
+ DDRSS_CTL_410_DATA
+ DDRSS_CTL_411_DATA
+ DDRSS_CTL_412_DATA
+ DDRSS_CTL_413_DATA
+ DDRSS_CTL_414_DATA
+ DDRSS_CTL_415_DATA
+ DDRSS_CTL_416_DATA
+ DDRSS_CTL_417_DATA
+ DDRSS_CTL_418_DATA
+ DDRSS_CTL_419_DATA
+ DDRSS_CTL_420_DATA
+ DDRSS_CTL_421_DATA
+ DDRSS_CTL_422_DATA
+ >;
+
+ ti,pi-data = <
+ DDRSS_PI_0_DATA
+ DDRSS_PI_1_DATA
+ DDRSS_PI_2_DATA
+ DDRSS_PI_3_DATA
+ DDRSS_PI_4_DATA
+ DDRSS_PI_5_DATA
+ DDRSS_PI_6_DATA
+ DDRSS_PI_7_DATA
+ DDRSS_PI_8_DATA
+ DDRSS_PI_9_DATA
+ DDRSS_PI_10_DATA
+ DDRSS_PI_11_DATA
+ DDRSS_PI_12_DATA
+ DDRSS_PI_13_DATA
+ DDRSS_PI_14_DATA
+ DDRSS_PI_15_DATA
+ DDRSS_PI_16_DATA
+ DDRSS_PI_17_DATA
+ DDRSS_PI_18_DATA
+ DDRSS_PI_19_DATA
+ DDRSS_PI_20_DATA
+ DDRSS_PI_21_DATA
+ DDRSS_PI_22_DATA
+ DDRSS_PI_23_DATA
+ DDRSS_PI_24_DATA
+ DDRSS_PI_25_DATA
+ DDRSS_PI_26_DATA
+ DDRSS_PI_27_DATA
+ DDRSS_PI_28_DATA
+ DDRSS_PI_29_DATA
+ DDRSS_PI_30_DATA
+ DDRSS_PI_31_DATA
+ DDRSS_PI_32_DATA
+ DDRSS_PI_33_DATA
+ DDRSS_PI_34_DATA
+ DDRSS_PI_35_DATA
+ DDRSS_PI_36_DATA
+ DDRSS_PI_37_DATA
+ DDRSS_PI_38_DATA
+ DDRSS_PI_39_DATA
+ DDRSS_PI_40_DATA
+ DDRSS_PI_41_DATA
+ DDRSS_PI_42_DATA
+ DDRSS_PI_43_DATA
+ DDRSS_PI_44_DATA
+ DDRSS_PI_45_DATA
+ DDRSS_PI_46_DATA
+ DDRSS_PI_47_DATA
+ DDRSS_PI_48_DATA
+ DDRSS_PI_49_DATA
+ DDRSS_PI_50_DATA
+ DDRSS_PI_51_DATA
+ DDRSS_PI_52_DATA
+ DDRSS_PI_53_DATA
+ DDRSS_PI_54_DATA
+ DDRSS_PI_55_DATA
+ DDRSS_PI_56_DATA
+ DDRSS_PI_57_DATA
+ DDRSS_PI_58_DATA
+ DDRSS_PI_59_DATA
+ DDRSS_PI_60_DATA
+ DDRSS_PI_61_DATA
+ DDRSS_PI_62_DATA
+ DDRSS_PI_63_DATA
+ DDRSS_PI_64_DATA
+ DDRSS_PI_65_DATA
+ DDRSS_PI_66_DATA
+ DDRSS_PI_67_DATA
+ DDRSS_PI_68_DATA
+ DDRSS_PI_69_DATA
+ DDRSS_PI_70_DATA
+ DDRSS_PI_71_DATA
+ DDRSS_PI_72_DATA
+ DDRSS_PI_73_DATA
+ DDRSS_PI_74_DATA
+ DDRSS_PI_75_DATA
+ DDRSS_PI_76_DATA
+ DDRSS_PI_77_DATA
+ DDRSS_PI_78_DATA
+ DDRSS_PI_79_DATA
+ DDRSS_PI_80_DATA
+ DDRSS_PI_81_DATA
+ DDRSS_PI_82_DATA
+ DDRSS_PI_83_DATA
+ DDRSS_PI_84_DATA
+ DDRSS_PI_85_DATA
+ DDRSS_PI_86_DATA
+ DDRSS_PI_87_DATA
+ DDRSS_PI_88_DATA
+ DDRSS_PI_89_DATA
+ DDRSS_PI_90_DATA
+ DDRSS_PI_91_DATA
+ DDRSS_PI_92_DATA
+ DDRSS_PI_93_DATA
+ DDRSS_PI_94_DATA
+ DDRSS_PI_95_DATA
+ DDRSS_PI_96_DATA
+ DDRSS_PI_97_DATA
+ DDRSS_PI_98_DATA
+ DDRSS_PI_99_DATA
+ DDRSS_PI_100_DATA
+ DDRSS_PI_101_DATA
+ DDRSS_PI_102_DATA
+ DDRSS_PI_103_DATA
+ DDRSS_PI_104_DATA
+ DDRSS_PI_105_DATA
+ DDRSS_PI_106_DATA
+ DDRSS_PI_107_DATA
+ DDRSS_PI_108_DATA
+ DDRSS_PI_109_DATA
+ DDRSS_PI_110_DATA
+ DDRSS_PI_111_DATA
+ DDRSS_PI_112_DATA
+ DDRSS_PI_113_DATA
+ DDRSS_PI_114_DATA
+ DDRSS_PI_115_DATA
+ DDRSS_PI_116_DATA
+ DDRSS_PI_117_DATA
+ DDRSS_PI_118_DATA
+ DDRSS_PI_119_DATA
+ DDRSS_PI_120_DATA
+ DDRSS_PI_121_DATA
+ DDRSS_PI_122_DATA
+ DDRSS_PI_123_DATA
+ DDRSS_PI_124_DATA
+ DDRSS_PI_125_DATA
+ DDRSS_PI_126_DATA
+ DDRSS_PI_127_DATA
+ DDRSS_PI_128_DATA
+ DDRSS_PI_129_DATA
+ DDRSS_PI_130_DATA
+ DDRSS_PI_131_DATA
+ DDRSS_PI_132_DATA
+ DDRSS_PI_133_DATA
+ DDRSS_PI_134_DATA
+ DDRSS_PI_135_DATA
+ DDRSS_PI_136_DATA
+ DDRSS_PI_137_DATA
+ DDRSS_PI_138_DATA
+ DDRSS_PI_139_DATA
+ DDRSS_PI_140_DATA
+ DDRSS_PI_141_DATA
+ DDRSS_PI_142_DATA
+ DDRSS_PI_143_DATA
+ DDRSS_PI_144_DATA
+ DDRSS_PI_145_DATA
+ DDRSS_PI_146_DATA
+ DDRSS_PI_147_DATA
+ DDRSS_PI_148_DATA
+ DDRSS_PI_149_DATA
+ DDRSS_PI_150_DATA
+ DDRSS_PI_151_DATA
+ DDRSS_PI_152_DATA
+ DDRSS_PI_153_DATA
+ DDRSS_PI_154_DATA
+ DDRSS_PI_155_DATA
+ DDRSS_PI_156_DATA
+ DDRSS_PI_157_DATA
+ DDRSS_PI_158_DATA
+ DDRSS_PI_159_DATA
+ DDRSS_PI_160_DATA
+ DDRSS_PI_161_DATA
+ DDRSS_PI_162_DATA
+ DDRSS_PI_163_DATA
+ DDRSS_PI_164_DATA
+ DDRSS_PI_165_DATA
+ DDRSS_PI_166_DATA
+ DDRSS_PI_167_DATA
+ DDRSS_PI_168_DATA
+ DDRSS_PI_169_DATA
+ DDRSS_PI_170_DATA
+ DDRSS_PI_171_DATA
+ DDRSS_PI_172_DATA
+ DDRSS_PI_173_DATA
+ DDRSS_PI_174_DATA
+ DDRSS_PI_175_DATA
+ DDRSS_PI_176_DATA
+ DDRSS_PI_177_DATA
+ DDRSS_PI_178_DATA
+ DDRSS_PI_179_DATA
+ DDRSS_PI_180_DATA
+ DDRSS_PI_181_DATA
+ DDRSS_PI_182_DATA
+ DDRSS_PI_183_DATA
+ DDRSS_PI_184_DATA
+ DDRSS_PI_185_DATA
+ DDRSS_PI_186_DATA
+ DDRSS_PI_187_DATA
+ DDRSS_PI_188_DATA
+ DDRSS_PI_189_DATA
+ DDRSS_PI_190_DATA
+ DDRSS_PI_191_DATA
+ DDRSS_PI_192_DATA
+ DDRSS_PI_193_DATA
+ DDRSS_PI_194_DATA
+ DDRSS_PI_195_DATA
+ DDRSS_PI_196_DATA
+ DDRSS_PI_197_DATA
+ DDRSS_PI_198_DATA
+ DDRSS_PI_199_DATA
+ DDRSS_PI_200_DATA
+ DDRSS_PI_201_DATA
+ DDRSS_PI_202_DATA
+ DDRSS_PI_203_DATA
+ DDRSS_PI_204_DATA
+ DDRSS_PI_205_DATA
+ DDRSS_PI_206_DATA
+ DDRSS_PI_207_DATA
+ DDRSS_PI_208_DATA
+ DDRSS_PI_209_DATA
+ DDRSS_PI_210_DATA
+ DDRSS_PI_211_DATA
+ DDRSS_PI_212_DATA
+ DDRSS_PI_213_DATA
+ DDRSS_PI_214_DATA
+ DDRSS_PI_215_DATA
+ DDRSS_PI_216_DATA
+ DDRSS_PI_217_DATA
+ DDRSS_PI_218_DATA
+ DDRSS_PI_219_DATA
+ DDRSS_PI_220_DATA
+ DDRSS_PI_221_DATA
+ DDRSS_PI_222_DATA
+ DDRSS_PI_223_DATA
+ DDRSS_PI_224_DATA
+ DDRSS_PI_225_DATA
+ DDRSS_PI_226_DATA
+ DDRSS_PI_227_DATA
+ DDRSS_PI_228_DATA
+ DDRSS_PI_229_DATA
+ DDRSS_PI_230_DATA
+ DDRSS_PI_231_DATA
+ DDRSS_PI_232_DATA
+ DDRSS_PI_233_DATA
+ DDRSS_PI_234_DATA
+ DDRSS_PI_235_DATA
+ DDRSS_PI_236_DATA
+ DDRSS_PI_237_DATA
+ DDRSS_PI_238_DATA
+ DDRSS_PI_239_DATA
+ DDRSS_PI_240_DATA
+ DDRSS_PI_241_DATA
+ DDRSS_PI_242_DATA
+ DDRSS_PI_243_DATA
+ DDRSS_PI_244_DATA
+ DDRSS_PI_245_DATA
+ DDRSS_PI_246_DATA
+ DDRSS_PI_247_DATA
+ DDRSS_PI_248_DATA
+ DDRSS_PI_249_DATA
+ DDRSS_PI_250_DATA
+ DDRSS_PI_251_DATA
+ DDRSS_PI_252_DATA
+ DDRSS_PI_253_DATA
+ DDRSS_PI_254_DATA
+ DDRSS_PI_255_DATA
+ DDRSS_PI_256_DATA
+ DDRSS_PI_257_DATA
+ DDRSS_PI_258_DATA
+ DDRSS_PI_259_DATA
+ DDRSS_PI_260_DATA
+ DDRSS_PI_261_DATA
+ DDRSS_PI_262_DATA
+ DDRSS_PI_263_DATA
+ DDRSS_PI_264_DATA
+ DDRSS_PI_265_DATA
+ DDRSS_PI_266_DATA
+ DDRSS_PI_267_DATA
+ DDRSS_PI_268_DATA
+ DDRSS_PI_269_DATA
+ DDRSS_PI_270_DATA
+ DDRSS_PI_271_DATA
+ DDRSS_PI_272_DATA
+ DDRSS_PI_273_DATA
+ DDRSS_PI_274_DATA
+ DDRSS_PI_275_DATA
+ DDRSS_PI_276_DATA
+ DDRSS_PI_277_DATA
+ DDRSS_PI_278_DATA
+ DDRSS_PI_279_DATA
+ DDRSS_PI_280_DATA
+ DDRSS_PI_281_DATA
+ DDRSS_PI_282_DATA
+ DDRSS_PI_283_DATA
+ DDRSS_PI_284_DATA
+ DDRSS_PI_285_DATA
+ DDRSS_PI_286_DATA
+ DDRSS_PI_287_DATA
+ DDRSS_PI_288_DATA
+ DDRSS_PI_289_DATA
+ DDRSS_PI_290_DATA
+ DDRSS_PI_291_DATA
+ DDRSS_PI_292_DATA
+ DDRSS_PI_293_DATA
+ DDRSS_PI_294_DATA
+ DDRSS_PI_295_DATA
+ DDRSS_PI_296_DATA
+ DDRSS_PI_297_DATA
+ DDRSS_PI_298_DATA
+ DDRSS_PI_299_DATA
+ DDRSS_PI_300_DATA
+ DDRSS_PI_301_DATA
+ DDRSS_PI_302_DATA
+ DDRSS_PI_303_DATA
+ DDRSS_PI_304_DATA
+ DDRSS_PI_305_DATA
+ DDRSS_PI_306_DATA
+ DDRSS_PI_307_DATA
+ DDRSS_PI_308_DATA
+ DDRSS_PI_309_DATA
+ DDRSS_PI_310_DATA
+ DDRSS_PI_311_DATA
+ DDRSS_PI_312_DATA
+ DDRSS_PI_313_DATA
+ DDRSS_PI_314_DATA
+ DDRSS_PI_315_DATA
+ DDRSS_PI_316_DATA
+ DDRSS_PI_317_DATA
+ DDRSS_PI_318_DATA
+ DDRSS_PI_319_DATA
+ DDRSS_PI_320_DATA
+ DDRSS_PI_321_DATA
+ DDRSS_PI_321_DATA
+ DDRSS_PI_322_DATA
+ DDRSS_PI_323_DATA
+ DDRSS_PI_324_DATA
+ DDRSS_PI_325_DATA
+ DDRSS_PI_326_DATA
+ DDRSS_PI_327_DATA
+ DDRSS_PI_328_DATA
+ DDRSS_PI_329_DATA
+ DDRSS_PI_330_DATA
+ DDRSS_PI_331_DATA
+ DDRSS_PI_332_DATA
+ DDRSS_PI_333_DATA
+ DDRSS_PI_334_DATA
+ DDRSS_PI_335_DATA
+ DDRSS_PI_336_DATA
+ DDRSS_PI_337_DATA
+ DDRSS_PI_338_DATA
+ DDRSS_PI_339_DATA
+ DDRSS_PI_340_DATA
+ DDRSS_PI_341_DATA
+ DDRSS_PI_342_DATA
+ DDRSS_PI_343_DATA
+ DDRSS_PI_344_DATA
+ >;
+
+ ti,phy-data = <
+ DDRSS_PHY_0_DATA
+ DDRSS_PHY_1_DATA
+ DDRSS_PHY_2_DATA
+ DDRSS_PHY_3_DATA
+ DDRSS_PHY_4_DATA
+ DDRSS_PHY_5_DATA
+ DDRSS_PHY_6_DATA
+ DDRSS_PHY_7_DATA
+ DDRSS_PHY_8_DATA
+ DDRSS_PHY_9_DATA
+ DDRSS_PHY_10_DATA
+ DDRSS_PHY_11_DATA
+ DDRSS_PHY_12_DATA
+ DDRSS_PHY_13_DATA
+ DDRSS_PHY_14_DATA
+ DDRSS_PHY_15_DATA
+ DDRSS_PHY_16_DATA
+ DDRSS_PHY_17_DATA
+ DDRSS_PHY_18_DATA
+ DDRSS_PHY_19_DATA
+ DDRSS_PHY_20_DATA
+ DDRSS_PHY_21_DATA
+ DDRSS_PHY_22_DATA
+ DDRSS_PHY_23_DATA
+ DDRSS_PHY_24_DATA
+ DDRSS_PHY_25_DATA
+ DDRSS_PHY_26_DATA
+ DDRSS_PHY_27_DATA
+ DDRSS_PHY_28_DATA
+ DDRSS_PHY_29_DATA
+ DDRSS_PHY_30_DATA
+ DDRSS_PHY_31_DATA
+ DDRSS_PHY_32_DATA
+ DDRSS_PHY_33_DATA
+ DDRSS_PHY_34_DATA
+ DDRSS_PHY_35_DATA
+ DDRSS_PHY_36_DATA
+ DDRSS_PHY_37_DATA
+ DDRSS_PHY_38_DATA
+ DDRSS_PHY_39_DATA
+ DDRSS_PHY_40_DATA
+ DDRSS_PHY_41_DATA
+ DDRSS_PHY_42_DATA
+ DDRSS_PHY_43_DATA
+ DDRSS_PHY_44_DATA
+ DDRSS_PHY_45_DATA
+ DDRSS_PHY_46_DATA
+ DDRSS_PHY_47_DATA
+ DDRSS_PHY_48_DATA
+ DDRSS_PHY_49_DATA
+ DDRSS_PHY_50_DATA
+ DDRSS_PHY_51_DATA
+ DDRSS_PHY_52_DATA
+ DDRSS_PHY_53_DATA
+ DDRSS_PHY_54_DATA
+ DDRSS_PHY_55_DATA
+ DDRSS_PHY_56_DATA
+ DDRSS_PHY_57_DATA
+ DDRSS_PHY_58_DATA
+ DDRSS_PHY_59_DATA
+ DDRSS_PHY_60_DATA
+ DDRSS_PHY_61_DATA
+ DDRSS_PHY_62_DATA
+ DDRSS_PHY_63_DATA
+ DDRSS_PHY_64_DATA
+ DDRSS_PHY_65_DATA
+ DDRSS_PHY_66_DATA
+ DDRSS_PHY_67_DATA
+ DDRSS_PHY_68_DATA
+ DDRSS_PHY_69_DATA
+ DDRSS_PHY_70_DATA
+ DDRSS_PHY_71_DATA
+ DDRSS_PHY_72_DATA
+ DDRSS_PHY_73_DATA
+ DDRSS_PHY_74_DATA
+ DDRSS_PHY_75_DATA
+ DDRSS_PHY_76_DATA
+ DDRSS_PHY_77_DATA
+ DDRSS_PHY_78_DATA
+ DDRSS_PHY_79_DATA
+ DDRSS_PHY_80_DATA
+ DDRSS_PHY_81_DATA
+ DDRSS_PHY_82_DATA
+ DDRSS_PHY_83_DATA
+ DDRSS_PHY_84_DATA
+ DDRSS_PHY_85_DATA
+ DDRSS_PHY_86_DATA
+ DDRSS_PHY_87_DATA
+ DDRSS_PHY_88_DATA
+ DDRSS_PHY_89_DATA
+ DDRSS_PHY_90_DATA
+ DDRSS_PHY_91_DATA
+ DDRSS_PHY_92_DATA
+ DDRSS_PHY_93_DATA
+ DDRSS_PHY_94_DATA
+ DDRSS_PHY_95_DATA
+ DDRSS_PHY_96_DATA
+ DDRSS_PHY_97_DATA
+ DDRSS_PHY_98_DATA
+ DDRSS_PHY_99_DATA
+ DDRSS_PHY_100_DATA
+ DDRSS_PHY_101_DATA
+ DDRSS_PHY_102_DATA
+ DDRSS_PHY_103_DATA
+ DDRSS_PHY_104_DATA
+ DDRSS_PHY_105_DATA
+ DDRSS_PHY_106_DATA
+ DDRSS_PHY_107_DATA
+ DDRSS_PHY_108_DATA
+ DDRSS_PHY_109_DATA
+ DDRSS_PHY_110_DATA
+ DDRSS_PHY_111_DATA
+ DDRSS_PHY_112_DATA
+ DDRSS_PHY_113_DATA
+ DDRSS_PHY_114_DATA
+ DDRSS_PHY_115_DATA
+ DDRSS_PHY_116_DATA
+ DDRSS_PHY_117_DATA
+ DDRSS_PHY_118_DATA
+ DDRSS_PHY_119_DATA
+ DDRSS_PHY_120_DATA
+ DDRSS_PHY_121_DATA
+ DDRSS_PHY_122_DATA
+ DDRSS_PHY_123_DATA
+ DDRSS_PHY_124_DATA
+ DDRSS_PHY_125_DATA
+ DDRSS_PHY_126_DATA
+ DDRSS_PHY_127_DATA
+ DDRSS_PHY_128_DATA
+ DDRSS_PHY_129_DATA
+ DDRSS_PHY_130_DATA
+ DDRSS_PHY_131_DATA
+ DDRSS_PHY_132_DATA
+ DDRSS_PHY_133_DATA
+ DDRSS_PHY_134_DATA
+ DDRSS_PHY_135_DATA
+ DDRSS_PHY_136_DATA
+ DDRSS_PHY_137_DATA
+ DDRSS_PHY_138_DATA
+ DDRSS_PHY_139_DATA
+ DDRSS_PHY_140_DATA
+ DDRSS_PHY_141_DATA
+ DDRSS_PHY_142_DATA
+ DDRSS_PHY_143_DATA
+ DDRSS_PHY_144_DATA
+ DDRSS_PHY_145_DATA
+ DDRSS_PHY_146_DATA
+ DDRSS_PHY_147_DATA
+ DDRSS_PHY_148_DATA
+ DDRSS_PHY_149_DATA
+ DDRSS_PHY_150_DATA
+ DDRSS_PHY_151_DATA
+ DDRSS_PHY_152_DATA
+ DDRSS_PHY_153_DATA
+ DDRSS_PHY_154_DATA
+ DDRSS_PHY_155_DATA
+ DDRSS_PHY_156_DATA
+ DDRSS_PHY_157_DATA
+ DDRSS_PHY_158_DATA
+ DDRSS_PHY_159_DATA
+ DDRSS_PHY_160_DATA
+ DDRSS_PHY_161_DATA
+ DDRSS_PHY_162_DATA
+ DDRSS_PHY_163_DATA
+ DDRSS_PHY_164_DATA
+ DDRSS_PHY_165_DATA
+ DDRSS_PHY_166_DATA
+ DDRSS_PHY_167_DATA
+ DDRSS_PHY_168_DATA
+ DDRSS_PHY_169_DATA
+ DDRSS_PHY_170_DATA
+ DDRSS_PHY_171_DATA
+ DDRSS_PHY_172_DATA
+ DDRSS_PHY_173_DATA
+ DDRSS_PHY_174_DATA
+ DDRSS_PHY_175_DATA
+ DDRSS_PHY_176_DATA
+ DDRSS_PHY_177_DATA
+ DDRSS_PHY_178_DATA
+ DDRSS_PHY_179_DATA
+ DDRSS_PHY_180_DATA
+ DDRSS_PHY_181_DATA
+ DDRSS_PHY_182_DATA
+ DDRSS_PHY_183_DATA
+ DDRSS_PHY_184_DATA
+ DDRSS_PHY_185_DATA
+ DDRSS_PHY_186_DATA
+ DDRSS_PHY_187_DATA
+ DDRSS_PHY_188_DATA
+ DDRSS_PHY_189_DATA
+ DDRSS_PHY_190_DATA
+ DDRSS_PHY_191_DATA
+ DDRSS_PHY_192_DATA
+ DDRSS_PHY_193_DATA
+ DDRSS_PHY_194_DATA
+ DDRSS_PHY_195_DATA
+ DDRSS_PHY_196_DATA
+ DDRSS_PHY_197_DATA
+ DDRSS_PHY_198_DATA
+ DDRSS_PHY_199_DATA
+ DDRSS_PHY_200_DATA
+ DDRSS_PHY_201_DATA
+ DDRSS_PHY_202_DATA
+ DDRSS_PHY_203_DATA
+ DDRSS_PHY_204_DATA
+ DDRSS_PHY_205_DATA
+ DDRSS_PHY_206_DATA
+ DDRSS_PHY_207_DATA
+ DDRSS_PHY_208_DATA
+ DDRSS_PHY_209_DATA
+ DDRSS_PHY_210_DATA
+ DDRSS_PHY_211_DATA
+ DDRSS_PHY_212_DATA
+ DDRSS_PHY_213_DATA
+ DDRSS_PHY_214_DATA
+ DDRSS_PHY_215_DATA
+ DDRSS_PHY_216_DATA
+ DDRSS_PHY_217_DATA
+ DDRSS_PHY_218_DATA
+ DDRSS_PHY_219_DATA
+ DDRSS_PHY_220_DATA
+ DDRSS_PHY_221_DATA
+ DDRSS_PHY_222_DATA
+ DDRSS_PHY_223_DATA
+ DDRSS_PHY_224_DATA
+ DDRSS_PHY_225_DATA
+ DDRSS_PHY_226_DATA
+ DDRSS_PHY_227_DATA
+ DDRSS_PHY_228_DATA
+ DDRSS_PHY_229_DATA
+ DDRSS_PHY_230_DATA
+ DDRSS_PHY_231_DATA
+ DDRSS_PHY_232_DATA
+ DDRSS_PHY_233_DATA
+ DDRSS_PHY_234_DATA
+ DDRSS_PHY_235_DATA
+ DDRSS_PHY_236_DATA
+ DDRSS_PHY_237_DATA
+ DDRSS_PHY_238_DATA
+ DDRSS_PHY_239_DATA
+ DDRSS_PHY_240_DATA
+ DDRSS_PHY_241_DATA
+ DDRSS_PHY_242_DATA
+ DDRSS_PHY_243_DATA
+ DDRSS_PHY_244_DATA
+ DDRSS_PHY_245_DATA
+ DDRSS_PHY_246_DATA
+ DDRSS_PHY_247_DATA
+ DDRSS_PHY_248_DATA
+ DDRSS_PHY_249_DATA
+ DDRSS_PHY_250_DATA
+ DDRSS_PHY_251_DATA
+ DDRSS_PHY_252_DATA
+ DDRSS_PHY_253_DATA
+ DDRSS_PHY_254_DATA
+ DDRSS_PHY_255_DATA
+ DDRSS_PHY_256_DATA
+ DDRSS_PHY_257_DATA
+ DDRSS_PHY_258_DATA
+ DDRSS_PHY_259_DATA
+ DDRSS_PHY_260_DATA
+ DDRSS_PHY_261_DATA
+ DDRSS_PHY_262_DATA
+ DDRSS_PHY_263_DATA
+ DDRSS_PHY_264_DATA
+ DDRSS_PHY_265_DATA
+ DDRSS_PHY_266_DATA
+ DDRSS_PHY_267_DATA
+ DDRSS_PHY_268_DATA
+ DDRSS_PHY_269_DATA
+ DDRSS_PHY_270_DATA
+ DDRSS_PHY_271_DATA
+ DDRSS_PHY_272_DATA
+ DDRSS_PHY_273_DATA
+ DDRSS_PHY_274_DATA
+ DDRSS_PHY_275_DATA
+ DDRSS_PHY_276_DATA
+ DDRSS_PHY_277_DATA
+ DDRSS_PHY_278_DATA
+ DDRSS_PHY_279_DATA
+ DDRSS_PHY_280_DATA
+ DDRSS_PHY_281_DATA
+ DDRSS_PHY_282_DATA
+ DDRSS_PHY_283_DATA
+ DDRSS_PHY_284_DATA
+ DDRSS_PHY_285_DATA
+ DDRSS_PHY_286_DATA
+ DDRSS_PHY_287_DATA
+ DDRSS_PHY_288_DATA
+ DDRSS_PHY_289_DATA
+ DDRSS_PHY_290_DATA
+ DDRSS_PHY_291_DATA
+ DDRSS_PHY_292_DATA
+ DDRSS_PHY_293_DATA
+ DDRSS_PHY_294_DATA
+ DDRSS_PHY_295_DATA
+ DDRSS_PHY_296_DATA
+ DDRSS_PHY_297_DATA
+ DDRSS_PHY_298_DATA
+ DDRSS_PHY_299_DATA
+ DDRSS_PHY_300_DATA
+ DDRSS_PHY_301_DATA
+ DDRSS_PHY_302_DATA
+ DDRSS_PHY_303_DATA
+ DDRSS_PHY_304_DATA
+ DDRSS_PHY_305_DATA
+ DDRSS_PHY_306_DATA
+ DDRSS_PHY_307_DATA
+ DDRSS_PHY_308_DATA
+ DDRSS_PHY_309_DATA
+ DDRSS_PHY_310_DATA
+ DDRSS_PHY_311_DATA
+ DDRSS_PHY_312_DATA
+ DDRSS_PHY_313_DATA
+ DDRSS_PHY_314_DATA
+ DDRSS_PHY_315_DATA
+ DDRSS_PHY_316_DATA
+ DDRSS_PHY_317_DATA
+ DDRSS_PHY_318_DATA
+ DDRSS_PHY_319_DATA
+ DDRSS_PHY_320_DATA
+ DDRSS_PHY_321_DATA
+ DDRSS_PHY_322_DATA
+ DDRSS_PHY_323_DATA
+ DDRSS_PHY_324_DATA
+ DDRSS_PHY_325_DATA
+ DDRSS_PHY_326_DATA
+ DDRSS_PHY_327_DATA
+ DDRSS_PHY_328_DATA
+ DDRSS_PHY_329_DATA
+ DDRSS_PHY_330_DATA
+ DDRSS_PHY_331_DATA
+ DDRSS_PHY_332_DATA
+ DDRSS_PHY_333_DATA
+ DDRSS_PHY_334_DATA
+ DDRSS_PHY_335_DATA
+ DDRSS_PHY_336_DATA
+ DDRSS_PHY_337_DATA
+ DDRSS_PHY_338_DATA
+ DDRSS_PHY_339_DATA
+ DDRSS_PHY_340_DATA
+ DDRSS_PHY_341_DATA
+ DDRSS_PHY_342_DATA
+ DDRSS_PHY_343_DATA
+ DDRSS_PHY_344_DATA
+ DDRSS_PHY_345_DATA
+ DDRSS_PHY_346_DATA
+ DDRSS_PHY_347_DATA
+ DDRSS_PHY_348_DATA
+ DDRSS_PHY_349_DATA
+ DDRSS_PHY_350_DATA
+ DDRSS_PHY_351_DATA
+ DDRSS_PHY_352_DATA
+ DDRSS_PHY_353_DATA
+ DDRSS_PHY_354_DATA
+ DDRSS_PHY_355_DATA
+ DDRSS_PHY_356_DATA
+ DDRSS_PHY_357_DATA
+ DDRSS_PHY_358_DATA
+ DDRSS_PHY_359_DATA
+ DDRSS_PHY_360_DATA
+ DDRSS_PHY_361_DATA
+ DDRSS_PHY_362_DATA
+ DDRSS_PHY_363_DATA
+ DDRSS_PHY_364_DATA
+ DDRSS_PHY_365_DATA
+ DDRSS_PHY_366_DATA
+ DDRSS_PHY_367_DATA
+ DDRSS_PHY_368_DATA
+ DDRSS_PHY_369_DATA
+ DDRSS_PHY_370_DATA
+ DDRSS_PHY_371_DATA
+ DDRSS_PHY_372_DATA
+ DDRSS_PHY_373_DATA
+ DDRSS_PHY_374_DATA
+ DDRSS_PHY_375_DATA
+ DDRSS_PHY_376_DATA
+ DDRSS_PHY_377_DATA
+ DDRSS_PHY_378_DATA
+ DDRSS_PHY_379_DATA
+ DDRSS_PHY_380_DATA
+ DDRSS_PHY_381_DATA
+ DDRSS_PHY_382_DATA
+ DDRSS_PHY_383_DATA
+ DDRSS_PHY_384_DATA
+ DDRSS_PHY_385_DATA
+ DDRSS_PHY_386_DATA
+ DDRSS_PHY_387_DATA
+ DDRSS_PHY_388_DATA
+ DDRSS_PHY_389_DATA
+ DDRSS_PHY_390_DATA
+ DDRSS_PHY_391_DATA
+ DDRSS_PHY_392_DATA
+ DDRSS_PHY_393_DATA
+ DDRSS_PHY_394_DATA
+ DDRSS_PHY_395_DATA
+ DDRSS_PHY_396_DATA
+ DDRSS_PHY_397_DATA
+ DDRSS_PHY_398_DATA
+ DDRSS_PHY_399_DATA
+ DDRSS_PHY_400_DATA
+ DDRSS_PHY_401_DATA
+ DDRSS_PHY_402_DATA
+ DDRSS_PHY_403_DATA
+ DDRSS_PHY_404_DATA
+ DDRSS_PHY_405_DATA
+ DDRSS_PHY_406_DATA
+ DDRSS_PHY_407_DATA
+ DDRSS_PHY_408_DATA
+ DDRSS_PHY_409_DATA
+ DDRSS_PHY_410_DATA
+ DDRSS_PHY_411_DATA
+ DDRSS_PHY_412_DATA
+ DDRSS_PHY_413_DATA
+ DDRSS_PHY_414_DATA
+ DDRSS_PHY_415_DATA
+ DDRSS_PHY_416_DATA
+ DDRSS_PHY_417_DATA
+ DDRSS_PHY_418_DATA
+ DDRSS_PHY_419_DATA
+ DDRSS_PHY_420_DATA
+ DDRSS_PHY_421_DATA
+ DDRSS_PHY_422_DATA
+ DDRSS_PHY_423_DATA
+ DDRSS_PHY_424_DATA
+ DDRSS_PHY_425_DATA
+ DDRSS_PHY_426_DATA
+ DDRSS_PHY_427_DATA
+ DDRSS_PHY_428_DATA
+ DDRSS_PHY_429_DATA
+ DDRSS_PHY_430_DATA
+ DDRSS_PHY_431_DATA
+ DDRSS_PHY_432_DATA
+ DDRSS_PHY_433_DATA
+ DDRSS_PHY_434_DATA
+ DDRSS_PHY_435_DATA
+ DDRSS_PHY_436_DATA
+ DDRSS_PHY_437_DATA
+ DDRSS_PHY_438_DATA
+ DDRSS_PHY_439_DATA
+ DDRSS_PHY_440_DATA
+ DDRSS_PHY_441_DATA
+ DDRSS_PHY_442_DATA
+ DDRSS_PHY_443_DATA
+ DDRSS_PHY_444_DATA
+ DDRSS_PHY_445_DATA
+ DDRSS_PHY_446_DATA
+ DDRSS_PHY_447_DATA
+ DDRSS_PHY_448_DATA
+ DDRSS_PHY_449_DATA
+ DDRSS_PHY_450_DATA
+ DDRSS_PHY_451_DATA
+ DDRSS_PHY_452_DATA
+ DDRSS_PHY_453_DATA
+ DDRSS_PHY_454_DATA
+ DDRSS_PHY_455_DATA
+ DDRSS_PHY_456_DATA
+ DDRSS_PHY_457_DATA
+ DDRSS_PHY_458_DATA
+ DDRSS_PHY_459_DATA
+ DDRSS_PHY_460_DATA
+ DDRSS_PHY_461_DATA
+ DDRSS_PHY_462_DATA
+ DDRSS_PHY_463_DATA
+ DDRSS_PHY_464_DATA
+ DDRSS_PHY_465_DATA
+ DDRSS_PHY_466_DATA
+ DDRSS_PHY_467_DATA
+ DDRSS_PHY_468_DATA
+ DDRSS_PHY_469_DATA
+ DDRSS_PHY_470_DATA
+ DDRSS_PHY_471_DATA
+ DDRSS_PHY_472_DATA
+ DDRSS_PHY_473_DATA
+ DDRSS_PHY_474_DATA
+ DDRSS_PHY_475_DATA
+ DDRSS_PHY_476_DATA
+ DDRSS_PHY_477_DATA
+ DDRSS_PHY_478_DATA
+ DDRSS_PHY_479_DATA
+ DDRSS_PHY_480_DATA
+ DDRSS_PHY_481_DATA
+ DDRSS_PHY_482_DATA
+ DDRSS_PHY_483_DATA
+ DDRSS_PHY_484_DATA
+ DDRSS_PHY_485_DATA
+ DDRSS_PHY_486_DATA
+ DDRSS_PHY_487_DATA
+ DDRSS_PHY_488_DATA
+ DDRSS_PHY_489_DATA
+ DDRSS_PHY_490_DATA
+ DDRSS_PHY_491_DATA
+ DDRSS_PHY_492_DATA
+ DDRSS_PHY_493_DATA
+ DDRSS_PHY_494_DATA
+ DDRSS_PHY_495_DATA
+ DDRSS_PHY_496_DATA
+ DDRSS_PHY_497_DATA
+ DDRSS_PHY_498_DATA
+ DDRSS_PHY_499_DATA
+ DDRSS_PHY_500_DATA
+ DDRSS_PHY_501_DATA
+ DDRSS_PHY_502_DATA
+ DDRSS_PHY_503_DATA
+ DDRSS_PHY_504_DATA
+ DDRSS_PHY_505_DATA
+ DDRSS_PHY_506_DATA
+ DDRSS_PHY_507_DATA
+ DDRSS_PHY_508_DATA
+ DDRSS_PHY_509_DATA
+ DDRSS_PHY_510_DATA
+ DDRSS_PHY_511_DATA
+ DDRSS_PHY_512_DATA
+ DDRSS_PHY_513_DATA
+ DDRSS_PHY_514_DATA
+ DDRSS_PHY_515_DATA
+ DDRSS_PHY_516_DATA
+ DDRSS_PHY_517_DATA
+ DDRSS_PHY_518_DATA
+ DDRSS_PHY_519_DATA
+ DDRSS_PHY_520_DATA
+ DDRSS_PHY_521_DATA
+ DDRSS_PHY_522_DATA
+ DDRSS_PHY_523_DATA
+ DDRSS_PHY_524_DATA
+ DDRSS_PHY_525_DATA
+ DDRSS_PHY_526_DATA
+ DDRSS_PHY_527_DATA
+ DDRSS_PHY_528_DATA
+ DDRSS_PHY_529_DATA
+ DDRSS_PHY_530_DATA
+ DDRSS_PHY_531_DATA
+ DDRSS_PHY_532_DATA
+ DDRSS_PHY_533_DATA
+ DDRSS_PHY_534_DATA
+ DDRSS_PHY_535_DATA
+ DDRSS_PHY_536_DATA
+ DDRSS_PHY_537_DATA
+ DDRSS_PHY_538_DATA
+ DDRSS_PHY_539_DATA
+ DDRSS_PHY_540_DATA
+ DDRSS_PHY_541_DATA
+ DDRSS_PHY_542_DATA
+ DDRSS_PHY_543_DATA
+ DDRSS_PHY_544_DATA
+ DDRSS_PHY_545_DATA
+ DDRSS_PHY_546_DATA
+ DDRSS_PHY_547_DATA
+ DDRSS_PHY_548_DATA
+ DDRSS_PHY_549_DATA
+ DDRSS_PHY_550_DATA
+ DDRSS_PHY_551_DATA
+ DDRSS_PHY_552_DATA
+ DDRSS_PHY_553_DATA
+ DDRSS_PHY_554_DATA
+ DDRSS_PHY_555_DATA
+ DDRSS_PHY_556_DATA
+ DDRSS_PHY_557_DATA
+ DDRSS_PHY_558_DATA
+ DDRSS_PHY_559_DATA
+ DDRSS_PHY_560_DATA
+ DDRSS_PHY_561_DATA
+ DDRSS_PHY_562_DATA
+ DDRSS_PHY_563_DATA
+ DDRSS_PHY_564_DATA
+ DDRSS_PHY_565_DATA
+ DDRSS_PHY_566_DATA
+ DDRSS_PHY_567_DATA
+ DDRSS_PHY_568_DATA
+ DDRSS_PHY_569_DATA
+ DDRSS_PHY_570_DATA
+ DDRSS_PHY_571_DATA
+ DDRSS_PHY_572_DATA
+ DDRSS_PHY_573_DATA
+ DDRSS_PHY_574_DATA
+ DDRSS_PHY_575_DATA
+ DDRSS_PHY_576_DATA
+ DDRSS_PHY_577_DATA
+ DDRSS_PHY_578_DATA
+ DDRSS_PHY_579_DATA
+ DDRSS_PHY_580_DATA
+ DDRSS_PHY_581_DATA
+ DDRSS_PHY_582_DATA
+ DDRSS_PHY_583_DATA
+ DDRSS_PHY_584_DATA
+ DDRSS_PHY_585_DATA
+ DDRSS_PHY_586_DATA
+ DDRSS_PHY_587_DATA
+ DDRSS_PHY_588_DATA
+ DDRSS_PHY_589_DATA
+ DDRSS_PHY_590_DATA
+ DDRSS_PHY_591_DATA
+ DDRSS_PHY_592_DATA
+ DDRSS_PHY_593_DATA
+ DDRSS_PHY_594_DATA
+ DDRSS_PHY_595_DATA
+ DDRSS_PHY_596_DATA
+ DDRSS_PHY_597_DATA
+ DDRSS_PHY_598_DATA
+ DDRSS_PHY_599_DATA
+ DDRSS_PHY_600_DATA
+ DDRSS_PHY_601_DATA
+ DDRSS_PHY_602_DATA
+ DDRSS_PHY_603_DATA
+ DDRSS_PHY_604_DATA
+ DDRSS_PHY_605_DATA
+ DDRSS_PHY_606_DATA
+ DDRSS_PHY_607_DATA
+ DDRSS_PHY_608_DATA
+ DDRSS_PHY_609_DATA
+ DDRSS_PHY_610_DATA
+ DDRSS_PHY_611_DATA
+ DDRSS_PHY_612_DATA
+ DDRSS_PHY_613_DATA
+ DDRSS_PHY_614_DATA
+ DDRSS_PHY_615_DATA
+ DDRSS_PHY_616_DATA
+ DDRSS_PHY_617_DATA
+ DDRSS_PHY_618_DATA
+ DDRSS_PHY_619_DATA
+ DDRSS_PHY_620_DATA
+ DDRSS_PHY_621_DATA
+ DDRSS_PHY_622_DATA
+ DDRSS_PHY_623_DATA
+ DDRSS_PHY_624_DATA
+ DDRSS_PHY_625_DATA
+ DDRSS_PHY_626_DATA
+ DDRSS_PHY_627_DATA
+ DDRSS_PHY_628_DATA
+ DDRSS_PHY_629_DATA
+ DDRSS_PHY_630_DATA
+ DDRSS_PHY_631_DATA
+ DDRSS_PHY_632_DATA
+ DDRSS_PHY_633_DATA
+ DDRSS_PHY_634_DATA
+ DDRSS_PHY_635_DATA
+ DDRSS_PHY_636_DATA
+ DDRSS_PHY_637_DATA
+ DDRSS_PHY_638_DATA
+ DDRSS_PHY_639_DATA
+ DDRSS_PHY_640_DATA
+ DDRSS_PHY_641_DATA
+ DDRSS_PHY_642_DATA
+ DDRSS_PHY_643_DATA
+ DDRSS_PHY_644_DATA
+ DDRSS_PHY_645_DATA
+ DDRSS_PHY_646_DATA
+ DDRSS_PHY_647_DATA
+ DDRSS_PHY_648_DATA
+ DDRSS_PHY_649_DATA
+ DDRSS_PHY_650_DATA
+ DDRSS_PHY_651_DATA
+ DDRSS_PHY_652_DATA
+ DDRSS_PHY_653_DATA
+ DDRSS_PHY_654_DATA
+ DDRSS_PHY_655_DATA
+ DDRSS_PHY_656_DATA
+ DDRSS_PHY_657_DATA
+ DDRSS_PHY_658_DATA
+ DDRSS_PHY_659_DATA
+ DDRSS_PHY_660_DATA
+ DDRSS_PHY_661_DATA
+ DDRSS_PHY_662_DATA
+ DDRSS_PHY_663_DATA
+ DDRSS_PHY_664_DATA
+ DDRSS_PHY_665_DATA
+ DDRSS_PHY_666_DATA
+ DDRSS_PHY_667_DATA
+ DDRSS_PHY_668_DATA
+ DDRSS_PHY_669_DATA
+ DDRSS_PHY_670_DATA
+ DDRSS_PHY_671_DATA
+ DDRSS_PHY_672_DATA
+ DDRSS_PHY_673_DATA
+ DDRSS_PHY_674_DATA
+ DDRSS_PHY_675_DATA
+ DDRSS_PHY_676_DATA
+ DDRSS_PHY_677_DATA
+ DDRSS_PHY_678_DATA
+ DDRSS_PHY_679_DATA
+ DDRSS_PHY_680_DATA
+ DDRSS_PHY_681_DATA
+ DDRSS_PHY_682_DATA
+ DDRSS_PHY_683_DATA
+ DDRSS_PHY_684_DATA
+ DDRSS_PHY_685_DATA
+ DDRSS_PHY_686_DATA
+ DDRSS_PHY_687_DATA
+ DDRSS_PHY_688_DATA
+ DDRSS_PHY_689_DATA
+ DDRSS_PHY_690_DATA
+ DDRSS_PHY_691_DATA
+ DDRSS_PHY_692_DATA
+ DDRSS_PHY_693_DATA
+ DDRSS_PHY_694_DATA
+ DDRSS_PHY_695_DATA
+ DDRSS_PHY_696_DATA
+ DDRSS_PHY_697_DATA
+ DDRSS_PHY_698_DATA
+ DDRSS_PHY_699_DATA
+ DDRSS_PHY_700_DATA
+ DDRSS_PHY_701_DATA
+ DDRSS_PHY_702_DATA
+ DDRSS_PHY_703_DATA
+ DDRSS_PHY_704_DATA
+ DDRSS_PHY_705_DATA
+ DDRSS_PHY_706_DATA
+ DDRSS_PHY_707_DATA
+ DDRSS_PHY_708_DATA
+ DDRSS_PHY_709_DATA
+ DDRSS_PHY_710_DATA
+ DDRSS_PHY_711_DATA
+ DDRSS_PHY_712_DATA
+ DDRSS_PHY_713_DATA
+ DDRSS_PHY_714_DATA
+ DDRSS_PHY_715_DATA
+ DDRSS_PHY_716_DATA
+ DDRSS_PHY_717_DATA
+ DDRSS_PHY_718_DATA
+ DDRSS_PHY_719_DATA
+ DDRSS_PHY_720_DATA
+ DDRSS_PHY_721_DATA
+ DDRSS_PHY_722_DATA
+ DDRSS_PHY_723_DATA
+ DDRSS_PHY_724_DATA
+ DDRSS_PHY_725_DATA
+ DDRSS_PHY_726_DATA
+ DDRSS_PHY_727_DATA
+ DDRSS_PHY_728_DATA
+ DDRSS_PHY_729_DATA
+ DDRSS_PHY_730_DATA
+ DDRSS_PHY_731_DATA
+ DDRSS_PHY_732_DATA
+ DDRSS_PHY_733_DATA
+ DDRSS_PHY_734_DATA
+ DDRSS_PHY_735_DATA
+ DDRSS_PHY_736_DATA
+ DDRSS_PHY_737_DATA
+ DDRSS_PHY_738_DATA
+ DDRSS_PHY_739_DATA
+ DDRSS_PHY_740_DATA
+ DDRSS_PHY_741_DATA
+ DDRSS_PHY_742_DATA
+ DDRSS_PHY_743_DATA
+ DDRSS_PHY_744_DATA
+ DDRSS_PHY_745_DATA
+ DDRSS_PHY_746_DATA
+ DDRSS_PHY_747_DATA
+ DDRSS_PHY_748_DATA
+ DDRSS_PHY_749_DATA
+ DDRSS_PHY_750_DATA
+ DDRSS_PHY_751_DATA
+ DDRSS_PHY_752_DATA
+ DDRSS_PHY_753_DATA
+ DDRSS_PHY_754_DATA
+ DDRSS_PHY_755_DATA
+ DDRSS_PHY_756_DATA
+ DDRSS_PHY_757_DATA
+ DDRSS_PHY_758_DATA
+ DDRSS_PHY_759_DATA
+ DDRSS_PHY_760_DATA
+ DDRSS_PHY_761_DATA
+ DDRSS_PHY_762_DATA
+ DDRSS_PHY_763_DATA
+ DDRSS_PHY_764_DATA
+ DDRSS_PHY_765_DATA
+ DDRSS_PHY_766_DATA
+ DDRSS_PHY_767_DATA
+ DDRSS_PHY_768_DATA
+ DDRSS_PHY_769_DATA
+ DDRSS_PHY_770_DATA
+ DDRSS_PHY_771_DATA
+ DDRSS_PHY_772_DATA
+ DDRSS_PHY_773_DATA
+ DDRSS_PHY_774_DATA
+ DDRSS_PHY_775_DATA
+ DDRSS_PHY_776_DATA
+ DDRSS_PHY_777_DATA
+ DDRSS_PHY_778_DATA
+ DDRSS_PHY_779_DATA
+ DDRSS_PHY_780_DATA
+ DDRSS_PHY_781_DATA
+ DDRSS_PHY_782_DATA
+ DDRSS_PHY_783_DATA
+ DDRSS_PHY_784_DATA
+ DDRSS_PHY_785_DATA
+ DDRSS_PHY_786_DATA
+ DDRSS_PHY_787_DATA
+ DDRSS_PHY_788_DATA
+ DDRSS_PHY_789_DATA
+ DDRSS_PHY_790_DATA
+ DDRSS_PHY_791_DATA
+ DDRSS_PHY_792_DATA
+ DDRSS_PHY_793_DATA
+ DDRSS_PHY_794_DATA
+ DDRSS_PHY_795_DATA
+ DDRSS_PHY_796_DATA
+ DDRSS_PHY_797_DATA
+ DDRSS_PHY_798_DATA
+ DDRSS_PHY_799_DATA
+ DDRSS_PHY_800_DATA
+ DDRSS_PHY_801_DATA
+ DDRSS_PHY_802_DATA
+ DDRSS_PHY_803_DATA
+ DDRSS_PHY_804_DATA
+ DDRSS_PHY_805_DATA
+ DDRSS_PHY_806_DATA
+ DDRSS_PHY_807_DATA
+ DDRSS_PHY_808_DATA
+ DDRSS_PHY_809_DATA
+ DDRSS_PHY_810_DATA
+ DDRSS_PHY_811_DATA
+ DDRSS_PHY_812_DATA
+ DDRSS_PHY_813_DATA
+ DDRSS_PHY_814_DATA
+ DDRSS_PHY_815_DATA
+ DDRSS_PHY_816_DATA
+ DDRSS_PHY_817_DATA
+ DDRSS_PHY_818_DATA
+ DDRSS_PHY_819_DATA
+ DDRSS_PHY_820_DATA
+ DDRSS_PHY_821_DATA
+ DDRSS_PHY_822_DATA
+ DDRSS_PHY_823_DATA
+ DDRSS_PHY_824_DATA
+ DDRSS_PHY_825_DATA
+ DDRSS_PHY_826_DATA
+ DDRSS_PHY_827_DATA
+ DDRSS_PHY_828_DATA
+ DDRSS_PHY_829_DATA
+ DDRSS_PHY_830_DATA
+ DDRSS_PHY_831_DATA
+ DDRSS_PHY_832_DATA
+ DDRSS_PHY_833_DATA
+ DDRSS_PHY_834_DATA
+ DDRSS_PHY_835_DATA
+ DDRSS_PHY_836_DATA
+ DDRSS_PHY_837_DATA
+ DDRSS_PHY_838_DATA
+ DDRSS_PHY_839_DATA
+ DDRSS_PHY_840_DATA
+ DDRSS_PHY_841_DATA
+ DDRSS_PHY_842_DATA
+ DDRSS_PHY_843_DATA
+ DDRSS_PHY_844_DATA
+ DDRSS_PHY_845_DATA
+ DDRSS_PHY_846_DATA
+ DDRSS_PHY_847_DATA
+ DDRSS_PHY_848_DATA
+ DDRSS_PHY_849_DATA
+ DDRSS_PHY_850_DATA
+ DDRSS_PHY_851_DATA
+ DDRSS_PHY_852_DATA
+ DDRSS_PHY_853_DATA
+ DDRSS_PHY_854_DATA
+ DDRSS_PHY_855_DATA
+ DDRSS_PHY_856_DATA
+ DDRSS_PHY_857_DATA
+ DDRSS_PHY_858_DATA
+ DDRSS_PHY_859_DATA
+ DDRSS_PHY_860_DATA
+ DDRSS_PHY_861_DATA
+ DDRSS_PHY_862_DATA
+ DDRSS_PHY_863_DATA
+ DDRSS_PHY_864_DATA
+ DDRSS_PHY_865_DATA
+ DDRSS_PHY_866_DATA
+ DDRSS_PHY_867_DATA
+ DDRSS_PHY_868_DATA
+ DDRSS_PHY_869_DATA
+ DDRSS_PHY_870_DATA
+ DDRSS_PHY_871_DATA
+ DDRSS_PHY_872_DATA
+ DDRSS_PHY_873_DATA
+ DDRSS_PHY_874_DATA
+ DDRSS_PHY_875_DATA
+ DDRSS_PHY_876_DATA
+ DDRSS_PHY_877_DATA
+ DDRSS_PHY_878_DATA
+ DDRSS_PHY_879_DATA
+ DDRSS_PHY_880_DATA
+ DDRSS_PHY_881_DATA
+ DDRSS_PHY_882_DATA
+ DDRSS_PHY_883_DATA
+ DDRSS_PHY_884_DATA
+ DDRSS_PHY_885_DATA
+ DDRSS_PHY_886_DATA
+ DDRSS_PHY_887_DATA
+ DDRSS_PHY_888_DATA
+ DDRSS_PHY_889_DATA
+ DDRSS_PHY_890_DATA
+ DDRSS_PHY_891_DATA
+ DDRSS_PHY_892_DATA
+ DDRSS_PHY_893_DATA
+ DDRSS_PHY_894_DATA
+ DDRSS_PHY_895_DATA
+ DDRSS_PHY_896_DATA
+ DDRSS_PHY_897_DATA
+ DDRSS_PHY_898_DATA
+ DDRSS_PHY_899_DATA
+ DDRSS_PHY_900_DATA
+ DDRSS_PHY_901_DATA
+ DDRSS_PHY_902_DATA
+ DDRSS_PHY_903_DATA
+ DDRSS_PHY_904_DATA
+ DDRSS_PHY_905_DATA
+ DDRSS_PHY_906_DATA
+ DDRSS_PHY_907_DATA
+ DDRSS_PHY_908_DATA
+ DDRSS_PHY_909_DATA
+ DDRSS_PHY_910_DATA
+ DDRSS_PHY_911_DATA
+ DDRSS_PHY_912_DATA
+ DDRSS_PHY_913_DATA
+ DDRSS_PHY_914_DATA
+ DDRSS_PHY_915_DATA
+ DDRSS_PHY_916_DATA
+ DDRSS_PHY_917_DATA
+ DDRSS_PHY_918_DATA
+ DDRSS_PHY_919_DATA
+ DDRSS_PHY_920_DATA
+ DDRSS_PHY_921_DATA
+ DDRSS_PHY_922_DATA
+ DDRSS_PHY_923_DATA
+ DDRSS_PHY_924_DATA
+ DDRSS_PHY_925_DATA
+ DDRSS_PHY_926_DATA
+ DDRSS_PHY_927_DATA
+ DDRSS_PHY_928_DATA
+ DDRSS_PHY_929_DATA
+ DDRSS_PHY_930_DATA
+ DDRSS_PHY_931_DATA
+ DDRSS_PHY_932_DATA
+ DDRSS_PHY_933_DATA
+ DDRSS_PHY_934_DATA
+ DDRSS_PHY_935_DATA
+ DDRSS_PHY_936_DATA
+ DDRSS_PHY_937_DATA
+ DDRSS_PHY_938_DATA
+ DDRSS_PHY_939_DATA
+ DDRSS_PHY_940_DATA
+ DDRSS_PHY_941_DATA
+ DDRSS_PHY_942_DATA
+ DDRSS_PHY_943_DATA
+ DDRSS_PHY_944_DATA
+ DDRSS_PHY_945_DATA
+ DDRSS_PHY_946_DATA
+ DDRSS_PHY_947_DATA
+ DDRSS_PHY_948_DATA
+ DDRSS_PHY_949_DATA
+ DDRSS_PHY_950_DATA
+ DDRSS_PHY_951_DATA
+ DDRSS_PHY_952_DATA
+ DDRSS_PHY_953_DATA
+ DDRSS_PHY_954_DATA
+ DDRSS_PHY_955_DATA
+ DDRSS_PHY_956_DATA
+ DDRSS_PHY_957_DATA
+ DDRSS_PHY_958_DATA
+ DDRSS_PHY_959_DATA
+ DDRSS_PHY_960_DATA
+ DDRSS_PHY_961_DATA
+ DDRSS_PHY_962_DATA
+ DDRSS_PHY_963_DATA
+ DDRSS_PHY_964_DATA
+ DDRSS_PHY_965_DATA
+ DDRSS_PHY_966_DATA
+ DDRSS_PHY_967_DATA
+ DDRSS_PHY_968_DATA
+ DDRSS_PHY_969_DATA
+ DDRSS_PHY_970_DATA
+ DDRSS_PHY_971_DATA
+ DDRSS_PHY_972_DATA
+ DDRSS_PHY_973_DATA
+ DDRSS_PHY_974_DATA
+ DDRSS_PHY_975_DATA
+ DDRSS_PHY_976_DATA
+ DDRSS_PHY_977_DATA
+ DDRSS_PHY_978_DATA
+ DDRSS_PHY_979_DATA
+ DDRSS_PHY_980_DATA
+ DDRSS_PHY_981_DATA
+ DDRSS_PHY_982_DATA
+ DDRSS_PHY_983_DATA
+ DDRSS_PHY_984_DATA
+ DDRSS_PHY_985_DATA
+ DDRSS_PHY_986_DATA
+ DDRSS_PHY_987_DATA
+ DDRSS_PHY_988_DATA
+ DDRSS_PHY_989_DATA
+ DDRSS_PHY_990_DATA
+ DDRSS_PHY_991_DATA
+ DDRSS_PHY_992_DATA
+ DDRSS_PHY_993_DATA
+ DDRSS_PHY_994_DATA
+ DDRSS_PHY_995_DATA
+ DDRSS_PHY_996_DATA
+ DDRSS_PHY_997_DATA
+ DDRSS_PHY_998_DATA
+ DDRSS_PHY_999_DATA
+ DDRSS_PHY_1000_DATA
+ DDRSS_PHY_1001_DATA
+ DDRSS_PHY_1002_DATA
+ DDRSS_PHY_1003_DATA
+ DDRSS_PHY_1004_DATA
+ DDRSS_PHY_1005_DATA
+ DDRSS_PHY_1006_DATA
+ DDRSS_PHY_1007_DATA
+ DDRSS_PHY_1008_DATA
+ DDRSS_PHY_1009_DATA
+ DDRSS_PHY_1010_DATA
+ DDRSS_PHY_1011_DATA
+ DDRSS_PHY_1012_DATA
+ DDRSS_PHY_1013_DATA
+ DDRSS_PHY_1014_DATA
+ DDRSS_PHY_1015_DATA
+ DDRSS_PHY_1016_DATA
+ DDRSS_PHY_1017_DATA
+ DDRSS_PHY_1018_DATA
+ DDRSS_PHY_1019_DATA
+ DDRSS_PHY_1020_DATA
+ DDRSS_PHY_1021_DATA
+ DDRSS_PHY_1022_DATA
+ DDRSS_PHY_1023_DATA
+ DDRSS_PHY_1024_DATA
+ DDRSS_PHY_1025_DATA
+ DDRSS_PHY_1026_DATA
+ DDRSS_PHY_1027_DATA
+ DDRSS_PHY_1028_DATA
+ DDRSS_PHY_1029_DATA
+ DDRSS_PHY_1030_DATA
+ DDRSS_PHY_1031_DATA
+ DDRSS_PHY_1032_DATA
+ DDRSS_PHY_1033_DATA
+ DDRSS_PHY_1034_DATA
+ DDRSS_PHY_1035_DATA
+ DDRSS_PHY_1036_DATA
+ DDRSS_PHY_1037_DATA
+ DDRSS_PHY_1038_DATA
+ DDRSS_PHY_1039_DATA
+ DDRSS_PHY_1040_DATA
+ DDRSS_PHY_1041_DATA
+ DDRSS_PHY_1042_DATA
+ DDRSS_PHY_1043_DATA
+ DDRSS_PHY_1044_DATA
+ DDRSS_PHY_1045_DATA
+ DDRSS_PHY_1046_DATA
+ DDRSS_PHY_1047_DATA
+ DDRSS_PHY_1048_DATA
+ DDRSS_PHY_1049_DATA
+ DDRSS_PHY_1050_DATA
+ DDRSS_PHY_1051_DATA
+ DDRSS_PHY_1052_DATA
+ DDRSS_PHY_1053_DATA
+ DDRSS_PHY_1054_DATA
+ DDRSS_PHY_1055_DATA
+ DDRSS_PHY_1056_DATA
+ DDRSS_PHY_1057_DATA
+ DDRSS_PHY_1058_DATA
+ DDRSS_PHY_1059_DATA
+ DDRSS_PHY_1060_DATA
+ DDRSS_PHY_1061_DATA
+ DDRSS_PHY_1062_DATA
+ DDRSS_PHY_1063_DATA
+ DDRSS_PHY_1064_DATA
+ DDRSS_PHY_1065_DATA
+ DDRSS_PHY_1066_DATA
+ DDRSS_PHY_1067_DATA
+ DDRSS_PHY_1068_DATA
+ DDRSS_PHY_1069_DATA
+ DDRSS_PHY_1070_DATA
+ DDRSS_PHY_1071_DATA
+ DDRSS_PHY_1072_DATA
+ DDRSS_PHY_1073_DATA
+ DDRSS_PHY_1074_DATA
+ DDRSS_PHY_1075_DATA
+ DDRSS_PHY_1076_DATA
+ DDRSS_PHY_1077_DATA
+ DDRSS_PHY_1078_DATA
+ DDRSS_PHY_1079_DATA
+ DDRSS_PHY_1080_DATA
+ DDRSS_PHY_1081_DATA
+ DDRSS_PHY_1082_DATA
+ DDRSS_PHY_1083_DATA
+ DDRSS_PHY_1084_DATA
+ DDRSS_PHY_1085_DATA
+ DDRSS_PHY_1086_DATA
+ DDRSS_PHY_1087_DATA
+ DDRSS_PHY_1088_DATA
+ DDRSS_PHY_1089_DATA
+ DDRSS_PHY_1090_DATA
+ DDRSS_PHY_1091_DATA
+ DDRSS_PHY_1092_DATA
+ DDRSS_PHY_1093_DATA
+ DDRSS_PHY_1094_DATA
+ DDRSS_PHY_1095_DATA
+ DDRSS_PHY_1096_DATA
+ DDRSS_PHY_1097_DATA
+ DDRSS_PHY_1098_DATA
+ DDRSS_PHY_1099_DATA
+ DDRSS_PHY_1100_DATA
+ DDRSS_PHY_1101_DATA
+ DDRSS_PHY_1102_DATA
+ DDRSS_PHY_1103_DATA
+ DDRSS_PHY_1104_DATA
+ DDRSS_PHY_1105_DATA
+ DDRSS_PHY_1106_DATA
+ DDRSS_PHY_1107_DATA
+ DDRSS_PHY_1108_DATA
+ DDRSS_PHY_1109_DATA
+ DDRSS_PHY_1110_DATA
+ DDRSS_PHY_1111_DATA
+ DDRSS_PHY_1112_DATA
+ DDRSS_PHY_1113_DATA
+ DDRSS_PHY_1114_DATA
+ DDRSS_PHY_1115_DATA
+ DDRSS_PHY_1116_DATA
+ DDRSS_PHY_1117_DATA
+ DDRSS_PHY_1118_DATA
+ DDRSS_PHY_1119_DATA
+ DDRSS_PHY_1120_DATA
+ DDRSS_PHY_1121_DATA
+ DDRSS_PHY_1122_DATA
+ DDRSS_PHY_1123_DATA
+ DDRSS_PHY_1124_DATA
+ DDRSS_PHY_1125_DATA
+ DDRSS_PHY_1126_DATA
+ DDRSS_PHY_1127_DATA
+ DDRSS_PHY_1128_DATA
+ DDRSS_PHY_1129_DATA
+ DDRSS_PHY_1130_DATA
+ DDRSS_PHY_1131_DATA
+ DDRSS_PHY_1132_DATA
+ DDRSS_PHY_1133_DATA
+ DDRSS_PHY_1134_DATA
+ DDRSS_PHY_1135_DATA
+ DDRSS_PHY_1136_DATA
+ DDRSS_PHY_1137_DATA
+ DDRSS_PHY_1138_DATA
+ DDRSS_PHY_1139_DATA
+ DDRSS_PHY_1140_DATA
+ DDRSS_PHY_1141_DATA
+ DDRSS_PHY_1142_DATA
+ DDRSS_PHY_1143_DATA
+ DDRSS_PHY_1144_DATA
+ DDRSS_PHY_1145_DATA
+ DDRSS_PHY_1146_DATA
+ DDRSS_PHY_1147_DATA
+ DDRSS_PHY_1148_DATA
+ DDRSS_PHY_1149_DATA
+ DDRSS_PHY_1150_DATA
+ DDRSS_PHY_1151_DATA
+ DDRSS_PHY_1152_DATA
+ DDRSS_PHY_1153_DATA
+ DDRSS_PHY_1154_DATA
+ DDRSS_PHY_1155_DATA
+ DDRSS_PHY_1156_DATA
+ DDRSS_PHY_1157_DATA
+ DDRSS_PHY_1158_DATA
+ DDRSS_PHY_1159_DATA
+ DDRSS_PHY_1160_DATA
+ DDRSS_PHY_1161_DATA
+ DDRSS_PHY_1162_DATA
+ DDRSS_PHY_1163_DATA
+ DDRSS_PHY_1164_DATA
+ DDRSS_PHY_1165_DATA
+ DDRSS_PHY_1166_DATA
+ DDRSS_PHY_1167_DATA
+ DDRSS_PHY_1168_DATA
+ DDRSS_PHY_1169_DATA
+ DDRSS_PHY_1170_DATA
+ DDRSS_PHY_1171_DATA
+ DDRSS_PHY_1172_DATA
+ DDRSS_PHY_1173_DATA
+ DDRSS_PHY_1174_DATA
+ DDRSS_PHY_1175_DATA
+ DDRSS_PHY_1176_DATA
+ DDRSS_PHY_1177_DATA
+ DDRSS_PHY_1178_DATA
+ DDRSS_PHY_1179_DATA
+ DDRSS_PHY_1180_DATA
+ DDRSS_PHY_1181_DATA
+ DDRSS_PHY_1182_DATA
+ DDRSS_PHY_1183_DATA
+ DDRSS_PHY_1184_DATA
+ DDRSS_PHY_1185_DATA
+ DDRSS_PHY_1186_DATA
+ DDRSS_PHY_1187_DATA
+ DDRSS_PHY_1188_DATA
+ DDRSS_PHY_1189_DATA
+ DDRSS_PHY_1190_DATA
+ DDRSS_PHY_1191_DATA
+ DDRSS_PHY_1192_DATA
+ DDRSS_PHY_1193_DATA
+ DDRSS_PHY_1194_DATA
+ DDRSS_PHY_1195_DATA
+ DDRSS_PHY_1196_DATA
+ DDRSS_PHY_1197_DATA
+ DDRSS_PHY_1198_DATA
+ DDRSS_PHY_1199_DATA
+ DDRSS_PHY_1200_DATA
+ DDRSS_PHY_1201_DATA
+ DDRSS_PHY_1202_DATA
+ DDRSS_PHY_1203_DATA
+ DDRSS_PHY_1204_DATA
+ DDRSS_PHY_1205_DATA
+ DDRSS_PHY_1206_DATA
+ DDRSS_PHY_1207_DATA
+ DDRSS_PHY_1208_DATA
+ DDRSS_PHY_1209_DATA
+ DDRSS_PHY_1210_DATA
+ DDRSS_PHY_1211_DATA
+ DDRSS_PHY_1212_DATA
+ DDRSS_PHY_1213_DATA
+ DDRSS_PHY_1214_DATA
+ DDRSS_PHY_1215_DATA
+ DDRSS_PHY_1216_DATA
+ DDRSS_PHY_1217_DATA
+ DDRSS_PHY_1218_DATA
+ DDRSS_PHY_1219_DATA
+ DDRSS_PHY_1220_DATA
+ DDRSS_PHY_1221_DATA
+ DDRSS_PHY_1222_DATA
+ DDRSS_PHY_1223_DATA
+ DDRSS_PHY_1224_DATA
+ DDRSS_PHY_1225_DATA
+ DDRSS_PHY_1226_DATA
+ DDRSS_PHY_1227_DATA
+ DDRSS_PHY_1228_DATA
+ DDRSS_PHY_1229_DATA
+ DDRSS_PHY_1230_DATA
+ DDRSS_PHY_1231_DATA
+ DDRSS_PHY_1232_DATA
+ DDRSS_PHY_1233_DATA
+ DDRSS_PHY_1234_DATA
+ DDRSS_PHY_1235_DATA
+ DDRSS_PHY_1236_DATA
+ DDRSS_PHY_1237_DATA
+ DDRSS_PHY_1238_DATA
+ DDRSS_PHY_1239_DATA
+ DDRSS_PHY_1240_DATA
+ DDRSS_PHY_1241_DATA
+ DDRSS_PHY_1242_DATA
+ DDRSS_PHY_1243_DATA
+ DDRSS_PHY_1244_DATA
+ DDRSS_PHY_1245_DATA
+ DDRSS_PHY_1246_DATA
+ DDRSS_PHY_1247_DATA
+ DDRSS_PHY_1248_DATA
+ DDRSS_PHY_1249_DATA
+ DDRSS_PHY_1250_DATA
+ DDRSS_PHY_1251_DATA
+ DDRSS_PHY_1252_DATA
+ DDRSS_PHY_1253_DATA
+ DDRSS_PHY_1254_DATA
+ DDRSS_PHY_1255_DATA
+ DDRSS_PHY_1256_DATA
+ DDRSS_PHY_1257_DATA
+ DDRSS_PHY_1258_DATA
+ DDRSS_PHY_1259_DATA
+ DDRSS_PHY_1260_DATA
+ DDRSS_PHY_1261_DATA
+ DDRSS_PHY_1262_DATA
+ DDRSS_PHY_1263_DATA
+ DDRSS_PHY_1264_DATA
+ DDRSS_PHY_1265_DATA
+ DDRSS_PHY_1266_DATA
+ DDRSS_PHY_1267_DATA
+ DDRSS_PHY_1268_DATA
+ DDRSS_PHY_1269_DATA
+ DDRSS_PHY_1270_DATA
+ DDRSS_PHY_1271_DATA
+ DDRSS_PHY_1272_DATA
+ DDRSS_PHY_1273_DATA
+ DDRSS_PHY_1274_DATA
+ DDRSS_PHY_1275_DATA
+ DDRSS_PHY_1276_DATA
+ DDRSS_PHY_1277_DATA
+ DDRSS_PHY_1278_DATA
+ DDRSS_PHY_1279_DATA
+ DDRSS_PHY_1280_DATA
+ DDRSS_PHY_1281_DATA
+ DDRSS_PHY_1282_DATA
+ DDRSS_PHY_1283_DATA
+ DDRSS_PHY_1284_DATA
+ DDRSS_PHY_1285_DATA
+ DDRSS_PHY_1286_DATA
+ DDRSS_PHY_1287_DATA
+ DDRSS_PHY_1288_DATA
+ DDRSS_PHY_1289_DATA
+ DDRSS_PHY_1290_DATA
+ DDRSS_PHY_1291_DATA
+ DDRSS_PHY_1292_DATA
+ DDRSS_PHY_1293_DATA
+ DDRSS_PHY_1294_DATA
+ DDRSS_PHY_1295_DATA
+ DDRSS_PHY_1296_DATA
+ DDRSS_PHY_1297_DATA
+ DDRSS_PHY_1298_DATA
+ DDRSS_PHY_1299_DATA
+ DDRSS_PHY_1300_DATA
+ DDRSS_PHY_1301_DATA
+ DDRSS_PHY_1302_DATA
+ DDRSS_PHY_1303_DATA
+ DDRSS_PHY_1304_DATA
+ DDRSS_PHY_1305_DATA
+ DDRSS_PHY_1306_DATA
+ DDRSS_PHY_1307_DATA
+ DDRSS_PHY_1308_DATA
+ DDRSS_PHY_1309_DATA
+ DDRSS_PHY_1310_DATA
+ DDRSS_PHY_1311_DATA
+ DDRSS_PHY_1312_DATA
+ DDRSS_PHY_1313_DATA
+ DDRSS_PHY_1314_DATA
+ DDRSS_PHY_1315_DATA
+ DDRSS_PHY_1316_DATA
+ DDRSS_PHY_1317_DATA
+ DDRSS_PHY_1318_DATA
+ DDRSS_PHY_1319_DATA
+ DDRSS_PHY_1320_DATA
+ DDRSS_PHY_1321_DATA
+ DDRSS_PHY_1322_DATA
+ DDRSS_PHY_1323_DATA
+ DDRSS_PHY_1324_DATA
+ DDRSS_PHY_1325_DATA
+ DDRSS_PHY_1326_DATA
+ DDRSS_PHY_1327_DATA
+ DDRSS_PHY_1328_DATA
+ DDRSS_PHY_1329_DATA
+ DDRSS_PHY_1330_DATA
+ DDRSS_PHY_1331_DATA
+ DDRSS_PHY_1332_DATA
+ DDRSS_PHY_1333_DATA
+ DDRSS_PHY_1334_DATA
+ DDRSS_PHY_1335_DATA
+ DDRSS_PHY_1336_DATA
+ DDRSS_PHY_1337_DATA
+ DDRSS_PHY_1338_DATA
+ DDRSS_PHY_1339_DATA
+ DDRSS_PHY_1340_DATA
+ DDRSS_PHY_1341_DATA
+ DDRSS_PHY_1342_DATA
+ DDRSS_PHY_1343_DATA
+ DDRSS_PHY_1344_DATA
+ DDRSS_PHY_1345_DATA
+ DDRSS_PHY_1346_DATA
+ DDRSS_PHY_1347_DATA
+ DDRSS_PHY_1348_DATA
+ DDRSS_PHY_1349_DATA
+ DDRSS_PHY_1350_DATA
+ DDRSS_PHY_1351_DATA
+ DDRSS_PHY_1352_DATA
+ DDRSS_PHY_1353_DATA
+ DDRSS_PHY_1354_DATA
+ DDRSS_PHY_1355_DATA
+ DDRSS_PHY_1356_DATA
+ DDRSS_PHY_1357_DATA
+ DDRSS_PHY_1358_DATA
+ DDRSS_PHY_1359_DATA
+ DDRSS_PHY_1360_DATA
+ DDRSS_PHY_1361_DATA
+ DDRSS_PHY_1362_DATA
+ DDRSS_PHY_1363_DATA
+ DDRSS_PHY_1364_DATA
+ DDRSS_PHY_1365_DATA
+ DDRSS_PHY_1366_DATA
+ DDRSS_PHY_1367_DATA
+ DDRSS_PHY_1368_DATA
+ DDRSS_PHY_1369_DATA
+ DDRSS_PHY_1370_DATA
+ DDRSS_PHY_1371_DATA
+ DDRSS_PHY_1372_DATA
+ DDRSS_PHY_1373_DATA
+ DDRSS_PHY_1374_DATA
+ DDRSS_PHY_1375_DATA
+ DDRSS_PHY_1376_DATA
+ DDRSS_PHY_1377_DATA
+ DDRSS_PHY_1378_DATA
+ DDRSS_PHY_1379_DATA
+ DDRSS_PHY_1380_DATA
+ DDRSS_PHY_1381_DATA
+ DDRSS_PHY_1382_DATA
+ DDRSS_PHY_1383_DATA
+ DDRSS_PHY_1384_DATA
+ DDRSS_PHY_1385_DATA
+ DDRSS_PHY_1386_DATA
+ DDRSS_PHY_1387_DATA
+ DDRSS_PHY_1388_DATA
+ DDRSS_PHY_1389_DATA
+ DDRSS_PHY_1390_DATA
+ DDRSS_PHY_1391_DATA
+ DDRSS_PHY_1392_DATA
+ DDRSS_PHY_1393_DATA
+ DDRSS_PHY_1394_DATA
+ DDRSS_PHY_1395_DATA
+ DDRSS_PHY_1396_DATA
+ DDRSS_PHY_1397_DATA
+ DDRSS_PHY_1398_DATA
+ DDRSS_PHY_1399_DATA
+ DDRSS_PHY_1400_DATA
+ DDRSS_PHY_1401_DATA
+ DDRSS_PHY_1402_DATA
+ DDRSS_PHY_1403_DATA
+ DDRSS_PHY_1404_DATA
+ DDRSS_PHY_1405_DATA
+ >;
+ };
+};
diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
new file mode 100644
index 0000000..9a008df
--- /dev/null
+++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
@@ -0,0 +1,2187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This file was generated by the AM64x_DDR4_RegConfig_Tool, Revision: 0.6.0
+ * This file was generated on Oct 26 2020
+ * DDR4 Frequency = 800MHz (1600MTs)
+ * Density: 16Gb
+ * Number of Ranks: 1
+ */
+
+#define DDRSS_PLL_FHS_CNT 6
+#define DDRSS_PLL_FREQUENCY_1 400000000
+#define DDRSS_PLL_FREQUENCY_2 400000000
+
+#define DDRSS_CTL_0_DATA 0x00000A00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x000890B8
+#define DDRSS_CTL_8_DATA 0x00000000
+#define DDRSS_CTL_9_DATA 0x00000000
+#define DDRSS_CTL_10_DATA 0x00000000
+#define DDRSS_CTL_11_DATA 0x000890B8
+#define DDRSS_CTL_12_DATA 0x00000000
+#define DDRSS_CTL_13_DATA 0x00000000
+#define DDRSS_CTL_14_DATA 0x00000000
+#define DDRSS_CTL_15_DATA 0x000890B8
+#define DDRSS_CTL_16_DATA 0x00000000
+#define DDRSS_CTL_17_DATA 0x00000000
+#define DDRSS_CTL_18_DATA 0x00000000
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01000100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x00027100
+#define DDRSS_CTL_24_DATA 0x00061A80
+#define DDRSS_CTL_25_DATA 0x02550255
+#define DDRSS_CTL_26_DATA 0x00000255
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00000000
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x00000000
+#define DDRSS_CTL_35_DATA 0x00000000
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x04000918
+#define DDRSS_CTL_39_DATA 0x1C1C1C1C
+#define DDRSS_CTL_40_DATA 0x04000918
+#define DDRSS_CTL_41_DATA 0x1C1C1C1C
+#define DDRSS_CTL_42_DATA 0x04000918
+#define DDRSS_CTL_43_DATA 0x1C1C1C1C
+#define DDRSS_CTL_44_DATA 0x05050404
+#define DDRSS_CTL_45_DATA 0x00002706
+#define DDRSS_CTL_46_DATA 0x0602001D
+#define DDRSS_CTL_47_DATA 0x05001D0B
+#define DDRSS_CTL_48_DATA 0x00270605
+#define DDRSS_CTL_49_DATA 0x0602001D
+#define DDRSS_CTL_50_DATA 0x05001D0B
+#define DDRSS_CTL_51_DATA 0x00270605
+#define DDRSS_CTL_52_DATA 0x0602001D
+#define DDRSS_CTL_53_DATA 0x07001D0B
+#define DDRSS_CTL_54_DATA 0x00180807
+#define DDRSS_CTL_55_DATA 0x0400DB60
+#define DDRSS_CTL_56_DATA 0x07070009
+#define DDRSS_CTL_57_DATA 0x00001808
+#define DDRSS_CTL_58_DATA 0x0400DB60
+#define DDRSS_CTL_59_DATA 0x07070009
+#define DDRSS_CTL_60_DATA 0x00001808
+#define DDRSS_CTL_61_DATA 0x0400DB60
+#define DDRSS_CTL_62_DATA 0x03000009
+#define DDRSS_CTL_63_DATA 0x0D0C0002
+#define DDRSS_CTL_64_DATA 0x0D0C0D0C
+#define DDRSS_CTL_65_DATA 0x01010000
+#define DDRSS_CTL_66_DATA 0x03191919
+#define DDRSS_CTL_67_DATA 0x0B0B0B0B
+#define DDRSS_CTL_68_DATA 0x00000B0B
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x01180803
+#define DDRSS_CTL_73_DATA 0x00001860
+#define DDRSS_CTL_74_DATA 0x00000118
+#define DDRSS_CTL_75_DATA 0x00001860
+#define DDRSS_CTL_76_DATA 0x00000118
+#define DDRSS_CTL_77_DATA 0x00001860
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x00000000
+#define DDRSS_CTL_80_DATA 0x00000000
+#define DDRSS_CTL_81_DATA 0x00000000
+#define DDRSS_CTL_82_DATA 0x00000000
+#define DDRSS_CTL_83_DATA 0x00000000
+#define DDRSS_CTL_84_DATA 0x00000000
+#define DDRSS_CTL_85_DATA 0x00000000
+#define DDRSS_CTL_86_DATA 0x00000000
+#define DDRSS_CTL_87_DATA 0x00090009
+#define DDRSS_CTL_88_DATA 0x00000009
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x00000000
+#define DDRSS_CTL_91_DATA 0x00000000
+#define DDRSS_CTL_92_DATA 0x00000000
+#define DDRSS_CTL_93_DATA 0x00000000
+#define DDRSS_CTL_94_DATA 0x00010001
+#define DDRSS_CTL_95_DATA 0x00025501
+#define DDRSS_CTL_96_DATA 0x02550120
+#define DDRSS_CTL_97_DATA 0x02550120
+#define DDRSS_CTL_98_DATA 0x01200120
+#define DDRSS_CTL_99_DATA 0x01200120
+#define DDRSS_CTL_100_DATA 0x00000000
+#define DDRSS_CTL_101_DATA 0x00000000
+#define DDRSS_CTL_102_DATA 0x00000000
+#define DDRSS_CTL_103_DATA 0x00000000
+#define DDRSS_CTL_104_DATA 0x00000000
+#define DDRSS_CTL_105_DATA 0x00000000
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00061800
+#define DDRSS_CTL_120_DATA 0x00061800
+#define DDRSS_CTL_121_DATA 0x00061800
+#define DDRSS_CTL_122_DATA 0x00061800
+#define DDRSS_CTL_123_DATA 0x00061800
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000AAA0
+#define DDRSS_CTL_126_DATA 0x00061800
+#define DDRSS_CTL_127_DATA 0x00061800
+#define DDRSS_CTL_128_DATA 0x00061800
+#define DDRSS_CTL_129_DATA 0x00061800
+#define DDRSS_CTL_130_DATA 0x00061800
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x0000AAA0
+#define DDRSS_CTL_133_DATA 0x00061800
+#define DDRSS_CTL_134_DATA 0x00061800
+#define DDRSS_CTL_135_DATA 0x00061800
+#define DDRSS_CTL_136_DATA 0x00061800
+#define DDRSS_CTL_137_DATA 0x00061800
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x0000AAA0
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x080C0000
+#define DDRSS_CTL_157_DATA 0x080C080C
+#define DDRSS_CTL_158_DATA 0x00000000
+#define DDRSS_CTL_159_DATA 0x07010A09
+#define DDRSS_CTL_160_DATA 0x000E0A09
+#define DDRSS_CTL_161_DATA 0x010A0900
+#define DDRSS_CTL_162_DATA 0x0E0A0907
+#define DDRSS_CTL_163_DATA 0x0A090000
+#define DDRSS_CTL_164_DATA 0x0A090701
+#define DDRSS_CTL_165_DATA 0x0000000E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000000
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x00000000
+#define DDRSS_CTL_193_DATA 0x00000000
+#define DDRSS_CTL_194_DATA 0x00000000
+#define DDRSS_CTL_195_DATA 0x00000000
+#define DDRSS_CTL_196_DATA 0x00000000
+#define DDRSS_CTL_197_DATA 0x00000000
+#define DDRSS_CTL_198_DATA 0x00000000
+#define DDRSS_CTL_199_DATA 0x00000000
+#define DDRSS_CTL_200_DATA 0x00000000
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00041400
+#define DDRSS_CTL_205_DATA 0x00000301
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000414
+#define DDRSS_CTL_208_DATA 0x00000301
+#define DDRSS_CTL_209_DATA 0x00000000
+#define DDRSS_CTL_210_DATA 0x00000414
+#define DDRSS_CTL_211_DATA 0x00000301
+#define DDRSS_CTL_212_DATA 0x00000000
+#define DDRSS_CTL_213_DATA 0x00000414
+#define DDRSS_CTL_214_DATA 0x00000301
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000414
+#define DDRSS_CTL_217_DATA 0x00000301
+#define DDRSS_CTL_218_DATA 0x00000000
+#define DDRSS_CTL_219_DATA 0x00000414
+#define DDRSS_CTL_220_DATA 0x00000301
+#define DDRSS_CTL_221_DATA 0x00000000
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000000
+#define DDRSS_CTL_225_DATA 0x00000000
+#define DDRSS_CTL_226_DATA 0x00000000
+#define DDRSS_CTL_227_DATA 0x00000000
+#define DDRSS_CTL_228_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0x00000000
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000401
+#define DDRSS_CTL_237_DATA 0x00000401
+#define DDRSS_CTL_238_DATA 0x00000401
+#define DDRSS_CTL_239_DATA 0x00000401
+#define DDRSS_CTL_240_DATA 0x00000401
+#define DDRSS_CTL_241_DATA 0x00000401
+#define DDRSS_CTL_242_DATA 0x00000493
+#define DDRSS_CTL_243_DATA 0x00000493
+#define DDRSS_CTL_244_DATA 0x00000493
+#define DDRSS_CTL_245_DATA 0x00000493
+#define DDRSS_CTL_246_DATA 0x00000493
+#define DDRSS_CTL_247_DATA 0x00000493
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x00000000
+#define DDRSS_CTL_255_DATA 0x00000000
+#define DDRSS_CTL_256_DATA 0x00000000
+#define DDRSS_CTL_257_DATA 0x00000000
+#define DDRSS_CTL_258_DATA 0x00000000
+#define DDRSS_CTL_259_DATA 0x00000000
+#define DDRSS_CTL_260_DATA 0x00000000
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x00000000
+#define DDRSS_CTL_264_DATA 0x00000000
+#define DDRSS_CTL_265_DATA 0x00000000
+#define DDRSS_CTL_266_DATA 0x00000000
+#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_268_DATA 0x00000000
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00000000
+#define DDRSS_CTL_271_DATA 0x00000000
+#define DDRSS_CTL_272_DATA 0x00000000
+#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_274_DATA 0x00000000
+#define DDRSS_CTL_275_DATA 0x00000000
+#define DDRSS_CTL_276_DATA 0x00000000
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000000
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00040000
+#define DDRSS_CTL_306_DATA 0x00800200
+#define DDRSS_CTL_307_DATA 0x00000000
+#define DDRSS_CTL_308_DATA 0x02000400
+#define DDRSS_CTL_309_DATA 0x00000080
+#define DDRSS_CTL_310_DATA 0x00040000
+#define DDRSS_CTL_311_DATA 0x00800200
+#define DDRSS_CTL_312_DATA 0x00000000
+#define DDRSS_CTL_313_DATA 0x00000000
+#define DDRSS_CTL_314_DATA 0x00000000
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_322_DATA 0x0A000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x00000000
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x01000000
+#define DDRSS_CTL_331_DATA 0x01000000
+#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_333_DATA 0x00010000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x0C000000
+#define DDRSS_CTL_371_DATA 0x060C0606
+#define DDRSS_CTL_372_DATA 0x06060C06
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x02000000
+#define DDRSS_CTL_375_DATA 0x03020101
+#define DDRSS_CTL_376_DATA 0x00000303
+#define DDRSS_CTL_377_DATA 0x02020200
+#define DDRSS_CTL_378_DATA 0x02020202
+#define DDRSS_CTL_379_DATA 0x02020202
+#define DDRSS_CTL_380_DATA 0x02020202
+#define DDRSS_CTL_381_DATA 0x00000000
+#define DDRSS_CTL_382_DATA 0x00000000
+#define DDRSS_CTL_383_DATA 0x04000100
+#define DDRSS_CTL_384_DATA 0x1E000004
+#define DDRSS_CTL_385_DATA 0x000030C0
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x0000DB60
+#define DDRSS_CTL_391_DATA 0x0001E780
+#define DDRSS_CTL_392_DATA 0x0A0B0302
+#define DDRSS_CTL_393_DATA 0x001E090A
+#define DDRSS_CTL_394_DATA 0x000030C0
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x0000DB60
+#define DDRSS_CTL_400_DATA 0x0001E780
+#define DDRSS_CTL_401_DATA 0x0A0B0302
+#define DDRSS_CTL_402_DATA 0x001E090A
+#define DDRSS_CTL_403_DATA 0x000030C0
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x0000DB60
+#define DDRSS_CTL_409_DATA 0x0001E780
+#define DDRSS_CTL_410_DATA 0x0A0B0302
+#define DDRSS_CTL_411_DATA 0x0000090A
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x00000000
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000A00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000000
+#define DDRSS_PI_12_DATA 0x00000000
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x00000000
+#define DDRSS_PI_15_DATA 0x00010001
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00000000
+#define DDRSS_PI_24_DATA 0x280D0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x00060602
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x00000055
+#define DDRSS_PI_36_DATA 0x000000AA
+#define DDRSS_PI_37_DATA 0x000000AD
+#define DDRSS_PI_38_DATA 0x00000052
+#define DDRSS_PI_39_DATA 0x0000006A
+#define DDRSS_PI_40_DATA 0x00000095
+#define DDRSS_PI_41_DATA 0x00000095
+#define DDRSS_PI_42_DATA 0x000000AD
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000014
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x00000000
+#define DDRSS_PI_55_DATA 0x00010000
+#define DDRSS_PI_56_DATA 0x00000000
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x00001400
+#define DDRSS_PI_61_DATA 0x00000000
+#define DDRSS_PI_62_DATA 0x01000000
+#define DDRSS_PI_63_DATA 0x00000404
+#define DDRSS_PI_64_DATA 0x00000001
+#define DDRSS_PI_65_DATA 0x0001010E
+#define DDRSS_PI_66_DATA 0x02040100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x00000000
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000005
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x04000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000300
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010100
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x00027100
+#define DDRSS_PI_137_DATA 0x00061A80
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010000
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00007800
+#define DDRSS_PI_165_DATA 0x00780078
+#define DDRSS_PI_166_DATA 0x00141414
+#define DDRSS_PI_167_DATA 0x00000038
+#define DDRSS_PI_168_DATA 0x00000038
+#define DDRSS_PI_169_DATA 0x00040038
+#define DDRSS_PI_170_DATA 0x04000400
+#define DDRSS_PI_171_DATA 0xC8040009
+#define DDRSS_PI_172_DATA 0x04000918
+#define DDRSS_PI_173_DATA 0x000918C8
+#define DDRSS_PI_174_DATA 0x0018C804
+#define DDRSS_PI_175_DATA 0x00000118
+#define DDRSS_PI_176_DATA 0x00001860
+#define DDRSS_PI_177_DATA 0x00000118
+#define DDRSS_PI_178_DATA 0x00001860
+#define DDRSS_PI_179_DATA 0x00000118
+#define DDRSS_PI_180_DATA 0x04001860
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001901
+#define DDRSS_PI_183_DATA 0x00190019
+#define DDRSS_PI_184_DATA 0x010C010C
+#define DDRSS_PI_185_DATA 0x0000010C
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x03000000
+#define DDRSS_PI_188_DATA 0x01010303
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x00181818
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x0B000000
+#define DDRSS_PI_194_DATA 0x0A0A0B0B
+#define DDRSS_PI_195_DATA 0x0303030A
+#define DDRSS_PI_196_DATA 0x00000000
+#define DDRSS_PI_197_DATA 0x00000000
+#define DDRSS_PI_198_DATA 0x00000000
+#define DDRSS_PI_199_DATA 0x00000000
+#define DDRSS_PI_200_DATA 0x00000000
+#define DDRSS_PI_201_DATA 0x00000000
+#define DDRSS_PI_202_DATA 0x00000000
+#define DDRSS_PI_203_DATA 0x00000000
+#define DDRSS_PI_204_DATA 0x00000000
+#define DDRSS_PI_205_DATA 0x00000000
+#define DDRSS_PI_206_DATA 0x00000000
+#define DDRSS_PI_207_DATA 0x00000000
+#define DDRSS_PI_208_DATA 0x00000000
+#define DDRSS_PI_209_DATA 0x0D090000
+#define DDRSS_PI_210_DATA 0x0D09000D
+#define DDRSS_PI_211_DATA 0x0D09000D
+#define DDRSS_PI_212_DATA 0x0000000D
+#define DDRSS_PI_213_DATA 0x00000000
+#define DDRSS_PI_214_DATA 0x00000000
+#define DDRSS_PI_215_DATA 0x00000000
+#define DDRSS_PI_216_DATA 0x00000000
+#define DDRSS_PI_217_DATA 0x16000000
+#define DDRSS_PI_218_DATA 0x001600C8
+#define DDRSS_PI_219_DATA 0x001600C8
+#define DDRSS_PI_220_DATA 0x010100C8
+#define DDRSS_PI_221_DATA 0x00001B01
+#define DDRSS_PI_222_DATA 0x1F0F0051
+#define DDRSS_PI_223_DATA 0x03000001
+#define DDRSS_PI_224_DATA 0x001B0A0B
+#define DDRSS_PI_225_DATA 0x1F0F0051
+#define DDRSS_PI_226_DATA 0x03000001
+#define DDRSS_PI_227_DATA 0x001B0A0B
+#define DDRSS_PI_228_DATA 0x1F0F0051
+#define DDRSS_PI_229_DATA 0x03000001
+#define DDRSS_PI_230_DATA 0x00000A0B
+#define DDRSS_PI_231_DATA 0x0C0B0700
+#define DDRSS_PI_232_DATA 0x000D0605
+#define DDRSS_PI_233_DATA 0x0000C570
+#define DDRSS_PI_234_DATA 0x0000001D
+#define DDRSS_PI_235_DATA 0x180A0800
+#define DDRSS_PI_236_DATA 0x0B071C1C
+#define DDRSS_PI_237_DATA 0x0D06050C
+#define DDRSS_PI_238_DATA 0x0000C570
+#define DDRSS_PI_239_DATA 0x0000001D
+#define DDRSS_PI_240_DATA 0x180A0800
+#define DDRSS_PI_241_DATA 0x0B071C1C
+#define DDRSS_PI_242_DATA 0x0D06050C
+#define DDRSS_PI_243_DATA 0x0000C570
+#define DDRSS_PI_244_DATA 0x0000001D
+#define DDRSS_PI_245_DATA 0x180A0800
+#define DDRSS_PI_246_DATA 0x00001C1C
+#define DDRSS_PI_247_DATA 0x000030C0
+#define DDRSS_PI_248_DATA 0x0001E780
+#define DDRSS_PI_249_DATA 0x000030C0
+#define DDRSS_PI_250_DATA 0x0001E780
+#define DDRSS_PI_251_DATA 0x000030C0
+#define DDRSS_PI_252_DATA 0x0001E780
+#define DDRSS_PI_253_DATA 0x02550255
+#define DDRSS_PI_254_DATA 0x03030255
+#define DDRSS_PI_255_DATA 0x00025503
+#define DDRSS_PI_256_DATA 0x02550255
+#define DDRSS_PI_257_DATA 0x0C080C08
+#define DDRSS_PI_258_DATA 0x00000C08
+#define DDRSS_PI_259_DATA 0x000890B8
+#define DDRSS_PI_260_DATA 0x00000000
+#define DDRSS_PI_261_DATA 0x00000000
+#define DDRSS_PI_262_DATA 0x00000000
+#define DDRSS_PI_263_DATA 0x00000120
+#define DDRSS_PI_264_DATA 0x000890B8
+#define DDRSS_PI_265_DATA 0x00000000
+#define DDRSS_PI_266_DATA 0x00000000
+#define DDRSS_PI_267_DATA 0x00000000
+#define DDRSS_PI_268_DATA 0x00000120
+#define DDRSS_PI_269_DATA 0x000890B8
+#define DDRSS_PI_270_DATA 0x00000000
+#define DDRSS_PI_271_DATA 0x00000000
+#define DDRSS_PI_272_DATA 0x00000000
+#define DDRSS_PI_273_DATA 0x02000120
+#define DDRSS_PI_274_DATA 0x00000080
+#define DDRSS_PI_275_DATA 0x00020000
+#define DDRSS_PI_276_DATA 0x00000080
+#define DDRSS_PI_277_DATA 0x00020000
+#define DDRSS_PI_278_DATA 0x00000080
+#define DDRSS_PI_279_DATA 0x00000000
+#define DDRSS_PI_280_DATA 0x00000000
+#define DDRSS_PI_281_DATA 0x00040404
+#define DDRSS_PI_282_DATA 0x00000000
+#define DDRSS_PI_283_DATA 0x02010102
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000202
+#define DDRSS_PI_286_DATA 0x00000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x00000000
+#define DDRSS_PI_289_DATA 0x00000000
+#define DDRSS_PI_290_DATA 0x00000000
+#define DDRSS_PI_291_DATA 0x0D100F00
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000414
+#define DDRSS_PI_298_DATA 0x00000301
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000000
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00000401
+#define DDRSS_PI_303_DATA 0x00000493
+#define DDRSS_PI_304_DATA 0x00000000
+#define DDRSS_PI_305_DATA 0x00000414
+#define DDRSS_PI_306_DATA 0x00000301
+#define DDRSS_PI_307_DATA 0x00000000
+#define DDRSS_PI_308_DATA 0x00000000
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00000401
+#define DDRSS_PI_311_DATA 0x00000493
+#define DDRSS_PI_312_DATA 0x00000000
+#define DDRSS_PI_313_DATA 0x00000414
+#define DDRSS_PI_314_DATA 0x00000301
+#define DDRSS_PI_315_DATA 0x00000000
+#define DDRSS_PI_316_DATA 0x00000000
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00000401
+#define DDRSS_PI_319_DATA 0x00000493
+#define DDRSS_PI_320_DATA 0x00000000
+#define DDRSS_PI_321_DATA 0x00000414
+#define DDRSS_PI_322_DATA 0x00000301
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000000
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00000401
+#define DDRSS_PI_327_DATA 0x00000493
+#define DDRSS_PI_328_DATA 0x00000000
+#define DDRSS_PI_329_DATA 0x00000414
+#define DDRSS_PI_330_DATA 0x00000301
+#define DDRSS_PI_331_DATA 0x00000000
+#define DDRSS_PI_332_DATA 0x00000000
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000401
+#define DDRSS_PI_335_DATA 0x00000493
+#define DDRSS_PI_336_DATA 0x00000000
+#define DDRSS_PI_337_DATA 0x00000414
+#define DDRSS_PI_338_DATA 0x00000301
+#define DDRSS_PI_339_DATA 0x00000000
+#define DDRSS_PI_340_DATA 0x00000000
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00000401
+#define DDRSS_PI_343_DATA 0x00000493
+#define DDRSS_PI_344_DATA 0x00000000
+#define DDRSS_PHY_0_DATA 0x04C00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00000200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x00000000
+#define DDRSS_PHY_6_DATA 0x00000000
+#define DDRSS_PHY_7_DATA 0x00000000
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x010101FF
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00004
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660201
+#define DDRSS_PHY_16_DATA 0x00000000
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00070820
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000000
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CCB001
+#define DDRSS_PHY_75_DATA 0x2000CCB0
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x10100303
+#define DDRSS_PHY_80_DATA 0x10101010
+#define DDRSS_PHY_81_DATA 0x10101010
+#define DDRSS_PHY_82_DATA 0x00021010
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_88_DATA 0x51515041
+#define DDRSS_PHY_89_DATA 0x31804000
+#define DDRSS_PHY_90_DATA 0x04BF0340
+#define DDRSS_PHY_91_DATA 0x01008080
+#define DDRSS_PHY_92_DATA 0x04050000
+#define DDRSS_PHY_93_DATA 0x00000504
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C14
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x007A0120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001CC
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000005
+#define DDRSS_PHY_103_DATA 0x76543210
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x02800280
+#define DDRSS_PHY_106_DATA 0x02800280
+#define DDRSS_PHY_107_DATA 0x02800280
+#define DDRSS_PHY_108_DATA 0x02800280
+#define DDRSS_PHY_109_DATA 0x00000280
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01000080
+#define DDRSS_PHY_120_DATA 0x01A00000
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x00000000
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04C00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00000200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x00000000
+#define DDRSS_PHY_262_DATA 0x00000000
+#define DDRSS_PHY_263_DATA 0x00000000
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x010101FF
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00004
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660201
+#define DDRSS_PHY_272_DATA 0x00000000
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00070820
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CCB001
+#define DDRSS_PHY_331_DATA 0x2000CCB0
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x10100303
+#define DDRSS_PHY_336_DATA 0x10101010
+#define DDRSS_PHY_337_DATA 0x10101010
+#define DDRSS_PHY_338_DATA 0x00021010
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_344_DATA 0x51515041
+#define DDRSS_PHY_345_DATA 0x31804000
+#define DDRSS_PHY_346_DATA 0x04BF0340
+#define DDRSS_PHY_347_DATA 0x01008080
+#define DDRSS_PHY_348_DATA 0x04050000
+#define DDRSS_PHY_349_DATA 0x00000504
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C14
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x007A0120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001CC
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000005
+#define DDRSS_PHY_359_DATA 0x76543210
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x02800280
+#define DDRSS_PHY_362_DATA 0x02800280
+#define DDRSS_PHY_363_DATA 0x02800280
+#define DDRSS_PHY_364_DATA 0x02800280
+#define DDRSS_PHY_365_DATA 0x00000280
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01000080
+#define DDRSS_PHY_376_DATA 0x01A00000
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x00000000
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000100
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000000
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00000000
+#define DDRSS_PHY_524_DATA 0x00000000
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x00000000
+#define DDRSS_PHY_527_DATA 0x00000000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x00000000
+#define DDRSS_PHY_533_DATA 0x00000000
+#define DDRSS_PHY_534_DATA 0x00000000
+#define DDRSS_PHY_535_DATA 0x00000000
+#define DDRSS_PHY_536_DATA 0x00000000
+#define DDRSS_PHY_537_DATA 0x00000000
+#define DDRSS_PHY_538_DATA 0x00000000
+#define DDRSS_PHY_539_DATA 0x00000000
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x103F0000
+#define DDRSS_PHY_542_DATA 0x000F0100
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x020002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000003E
+#define DDRSS_PHY_553_DATA 0x00000000
+#define DDRSS_PHY_554_DATA 0x00000000
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000100
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000000
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00000000
+#define DDRSS_PHY_780_DATA 0x00000000
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x00000000
+#define DDRSS_PHY_783_DATA 0x00000000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x00000000
+#define DDRSS_PHY_789_DATA 0x00000000
+#define DDRSS_PHY_790_DATA 0x00000000
+#define DDRSS_PHY_791_DATA 0x00000000
+#define DDRSS_PHY_792_DATA 0x00000000
+#define DDRSS_PHY_793_DATA 0x00000000
+#define DDRSS_PHY_794_DATA 0x00000000
+#define DDRSS_PHY_795_DATA 0x00000000
+#define DDRSS_PHY_796_DATA 0x16A4A0E6
+#define DDRSS_PHY_797_DATA 0x103F0000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x020002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000003E
+#define DDRSS_PHY_809_DATA 0x00000000
+#define DDRSS_PHY_810_DATA 0x00000000
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000100
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000000
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00000000
+#define DDRSS_PHY_1036_DATA 0x00000000
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x00000000
+#define DDRSS_PHY_1039_DATA 0x00000000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x00000000
+#define DDRSS_PHY_1045_DATA 0x00000000
+#define DDRSS_PHY_1046_DATA 0x00000000
+#define DDRSS_PHY_1047_DATA 0x00000000
+#define DDRSS_PHY_1048_DATA 0x00000000
+#define DDRSS_PHY_1049_DATA 0x00000000
+#define DDRSS_PHY_1050_DATA 0x00000000
+#define DDRSS_PHY_1051_DATA 0x00000000
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10030000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x020002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000003E
+#define DDRSS_PHY_1065_DATA 0x00000000
+#define DDRSS_PHY_1066_DATA 0x00000000
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00000100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000100
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x01002000
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x00010100
+#define DDRSS_PHY_1297_DATA 0x00000001
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00040000
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07070001
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000046
+#define DDRSS_PHY_1334_DATA 0x00010000
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00000098
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000100
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1372_DATA 0x00020002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x03020400
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03900390
+#define DDRSS_PHY_1382_DATA 0x03900390
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x31823FC7
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000D3F
+#define DDRSS_PHY_1390_DATA 0x30000D3F
+#define DDRSS_PHY_1391_DATA 0x300D3F11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x000D3FCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x300D3F11
+#define DDRSS_PHY_1396_DATA 0x01990000
+#define DDRSS_PHY_1397_DATA 0x300C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x300C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x300D3F11
+#define DDRSS_PHY_1402_DATA 0x01990000
+#define DDRSS_PHY_1403_DATA 0x300D3F11
+#define DDRSS_PHY_1404_DATA 0x01990000
+#define DDRSS_PHY_1405_DATA 0x20040001
diff --git a/arch/arm/dts/k3-am64-main.dtsi b/arch/arm/dts/k3-am64-main.dtsi
new file mode 100644
index 0000000..6b5ebec
--- /dev/null
+++ b/arch/arm/dts/k3-am64-main.dtsi
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family Main Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+ oc_sram: sram@70000000 {
+ compatible = "mmio-sram";
+ reg = <0x00 0x70000000 0x00 0x200000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x70000000 0x200000>;
+
+ atf-sram@0 {
+ reg = <0x1a0000 0x1c000>;
+ };
+ };
+
+ gic500: interrupt-controller@1800000 {
+ compatible = "arm,gic-v3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
+ <0x00 0x01840000 0x00 0xC0000>; /* GICR */
+ /*
+ * vcpumntirq:
+ * virtual CPU interface maintenance interrupt
+ */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ gic_its: msi-controller@1820000 {
+ compatible = "arm,gic-v3-its";
+ reg = <0x00 0x01820000 0x00 0x10000>;
+ socionext,synquacer-pre-its = <0x1000000 0x400000>;
+ msi-controller;
+ #msi-cells = <1>;
+ };
+ };
+
+ dmss: dmss {
+ compatible = "simple-mfd";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges;
+ ranges;
+
+ ti,sci-dev-id = <25>;
+
+ secure_proxy_main: mailbox@4d000000 {
+ compatible = "ti,am654-secure-proxy";
+ #mbox-cells = <1>;
+ reg-names = "target_data", "rt", "scfg";
+ reg = <0x00 0x4d000000 0x00 0x80000>,
+ <0x00 0x4a600000 0x00 0x80000>,
+ <0x00 0x4a400000 0x00 0x80000>;
+ interrupt-names = "rx_012";
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ inta_main_dmss: interrupt-controller@48000000 {
+ compatible = "ti,sci-inta";
+ reg = <0x00 0x48000000 0x00 0x100000>;
+ #interrupt-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&gic500>;
+ msi-controller;
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <28>;
+ ti,interrupt-ranges = <4 68 36>;
+ ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
+ };
+
+ main_bcdma: dma-controller@485c0100 {
+ compatible = "ti,am64-dmss-bcdma";
+ reg = <0x00 0x485c0100 0x00 0x100>,
+ <0x00 0x4c000000 0x00 0x20000>,
+ <0x00 0x4a820000 0x00 0x20000>,
+ <0x00 0x4aa40000 0x00 0x20000>,
+ <0x00 0x4bc00000 0x00 0x100000>;
+ reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <3>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <26>;
+ ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
+ ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
+ ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
+ };
+
+ main_pktdma: dma-controller@485c0000 {
+ compatible = "ti,am64-dmss-pktdma";
+ reg = <0x00 0x485c0000 0x00 0x100>,
+ <0x00 0x4a800000 0x00 0x20000>,
+ <0x00 0x4aa00000 0x00 0x40000>,
+ <0x00 0x4b800000 0x00 0x400000>;
+ reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
+ msi-parent = <&inta_main_dmss>;
+ #dma-cells = <2>;
+
+ ti,sci = <&dmsc>;
+ ti,sci-dev-id = <30>;
+ ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
+ <0x24>, /* CPSW_TX_CHAN */
+ <0x25>, /* SAUL_TX_0_CHAN */
+ <0x26>, /* SAUL_TX_1_CHAN */
+ <0x27>, /* ICSSG_0_TX_CHAN */
+ <0x28>; /* ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
+ <0x11>, /* RING_CPSW_TX_CHAN */
+ <0x12>, /* RING_SAUL_TX_0_CHAN */
+ <0x13>, /* RING_SAUL_TX_1_CHAN */
+ <0x14>, /* RING_ICSSG_0_TX_CHAN */
+ <0x15>; /* RING_ICSSG_1_TX_CHAN */
+ ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
+ <0x2b>, /* CPSW_RX_CHAN */
+ <0x2d>, /* SAUL_RX_0_CHAN */
+ <0x2f>, /* SAUL_RX_1_CHAN */
+ <0x31>, /* SAUL_RX_2_CHAN */
+ <0x33>, /* SAUL_RX_3_CHAN */
+ <0x35>, /* ICSSG_0_RX_CHAN */
+ <0x37>; /* ICSSG_1_RX_CHAN */
+ ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
+ <0x2c>, /* FLOW_CPSW_RX_CHAN */
+ <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */
+ <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */
+ <0x36>, /* FLOW_ICSSG_0_RX_CHAN */
+ <0x38>; /* FLOW_ICSSG_1_RX_CHAN */
+ };
+ };
+
+ dmsc: dmsc@44043000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 12>,
+ <&secure_proxy_main 13>;
+ reg-names = "debug_messages";
+ reg = <0x00 0x44043000 0x00 0xfe0>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clocks {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
+
+ main_pmx0: pinctrl@f4000 {
+ compatible = "pinctrl-single";
+ reg = <0x00 0xf4000 0x00 0x2d0>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xffffffff>;
+ };
+
+ main_conf: syscon@43000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x00 0x43000000 0x00 0x20000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x43000000 0x20000>;
+
+ chipid@14 {
+ compatible = "ti,am654-chipid";
+ reg = <0x00000014 0x4>;
+ };
+
+ phy_gmii_sel: phy@4044 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4044 0x8>;
+ #phy-cells = <1>;
+ };
+ };
+
+ main_uart0: serial@2800000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02800000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 146 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart1: serial@2810000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02810000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 152 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart2: serial@2820000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02820000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 153 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart3: serial@2830000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02830000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 154 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart4: serial@2840000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02840000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 155 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart5: serial@2850000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02850000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 156 0>;
+ clock-names = "fclk";
+ };
+
+ main_uart6: serial@2860000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x02860000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 158 0>;
+ clock-names = "fclk";
+ };
+
+ main_i2c0: i2c@20000000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20000000 0x00 0x100>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 102 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c1: i2c@20010000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20010000 0x00 0x100>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 103 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c2: i2c@20020000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20020000 0x00 0x100>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 104 2>;
+ clock-names = "fck";
+ };
+
+ main_i2c3: i2c@20030000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20030000 0x00 0x100>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 2>;
+ clock-names = "fck";
+ };
+
+ main_spi0: spi@20100000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x20100000 0x00 0x400>;
+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 141 0>;
+ dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>;
+ dma-names = "tx0", "rx0";
+ };
+
+ main_spi1: spi@20110000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20110000 0x00 0x400>;
+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 142 0>;
+ };
+
+ main_spi2: spi@20120000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20120000 0x00 0x400>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 143 0>;
+ };
+
+ main_spi3: spi@20130000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20130000 0x00 0x400>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 144 0>;
+ };
+
+ main_spi4: spi@20140000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x20140000 0x00 0x400>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 145 0>;
+ };
+
+ sdhci0: mmc@fa10000 {
+ compatible = "ti,am64-sdhci-8bit";
+ reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 57 0>, <&k3_clks 57 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x7>;
+ ti,otap-del-sel-hs400 = <0x4>;
+ };
+
+ sdhci1: mmc@fa00000 {
+ compatible = "ti,am64-sdhci-4bit";
+ reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 58 3>, <&k3_clks 58 4>;
+ clock-names = "clk_ahb", "clk_xin";
+ ti,trm-icp = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0xf>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x6>;
+ ti,otap-del-sel-ddr50 = <0x9>;
+ ti,clkbuf-sel = <0x7>;
+ };
+
+ cpsw3g: ethernet@8000000 {
+ compatible = "ti,am642-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0x8000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>;
+ clocks = <&k3_clks 13 0>;
+ assigned-clocks = <&k3_clks 13 1>;
+ assigned-clock-parents = <&k3_clks 13 9>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_pktdma 0xC500 15>,
+ <&main_pktdma 0xC501 15>,
+ <&main_pktdma 0xC502 15>,
+ <&main_pktdma 0xC503 15>,
+ <&main_pktdma 0xC504 15>,
+ <&main_pktdma 0xC505 15>,
+ <&main_pktdma 0xC506 15>,
+ <&main_pktdma 0xC507 15>,
+ <&main_pktdma 0x4500 15>;
+ dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
+ "tx7", "rx";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ phys = <&phy_gmii_sel 1>;
+ mac-address = [00 00 de ad be ef];
+ };
+
+ cpsw_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ phys = <&phy_gmii_sel 2>;
+ mac-address = [00 01 de ad be ef];
+ };
+ };
+
+ cpsw3g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 13 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 13 1>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
+ main_gpio0: gpio@600000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00600000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <77 0 IRQ_TYPE_EDGE_RISING>,
+ <77 1 IRQ_TYPE_EDGE_RISING>,
+ <77 2 IRQ_TYPE_EDGE_RISING>,
+ <77 3 IRQ_TYPE_EDGE_RISING>,
+ <77 4 IRQ_TYPE_EDGE_RISING>,
+ <77 5 IRQ_TYPE_EDGE_RISING>,
+ <77 6 IRQ_TYPE_EDGE_RISING>,
+ <77 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 77 0>;
+ clock-names = "gpio";
+ };
+
+ usbss0: cdns-usb@f900000{
+ compatible = "ti,am64-usb", "ti,j721e-usb";
+ reg = <0x00 0xf900000 0x00 0x100>;
+ power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ usb0: usb@f400000{
+ compatible = "cdns,usb3";
+ reg = <0x00 0xf400000 0x00 0x10000>,
+ <0x00 0xf410000 0x00 0x10000>,
+ <0x00 0xf420000 0x00 0x10000>;
+ reg-names = "otg",
+ "xhci",
+ "dev";
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
+ interrupt-names = "host",
+ "peripheral",
+ "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
+ main_gpio1: gpio@601000 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x00601000 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <78 0 IRQ_TYPE_EDGE_RISING>,
+ <78 1 IRQ_TYPE_EDGE_RISING>,
+ <78 2 IRQ_TYPE_EDGE_RISING>,
+ <78 3 IRQ_TYPE_EDGE_RISING>,
+ <78 4 IRQ_TYPE_EDGE_RISING>,
+ <78 5 IRQ_TYPE_EDGE_RISING>,
+ <78 6 IRQ_TYPE_EDGE_RISING>,
+ <78 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 78 0>;
+ clock-names = "gpio";
+ };
+
+ main_i2c0: i2c@20000000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x20000000 0x0 0x100>;
+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 102 2>;
+ power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c1: i2c@20010000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x0 0x20010000 0x0 0x100>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 103 2>;
+ power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c2: i2c@20020000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20020000 0x0 0x100>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 104 2>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ };
+
+ main_i2c3: i2c@20030000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x20030000 0x0 0x100>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "fck";
+ clocks = <&k3_clks 105 2>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ };
+};
diff --git a/arch/arm/dts/k3-am64-mcu.dtsi b/arch/arm/dts/k3-am64-mcu.dtsi
new file mode 100644
index 0000000..1d2be48
--- /dev/null
+++ b/arch/arm/dts/k3-am64-mcu.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM64 SoC Family MCU Domain peripherals
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_mcu {
+ mcu_uart0: serial@4a00000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a00000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 149 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_uart1: serial@4a10000 {
+ compatible = "ti,am64-uart", "ti,am654-uart";
+ reg = <0x00 0x04a10000 0x00 0x100>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <48000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 160 0>;
+ clock-names = "fclk";
+ };
+
+ mcu_i2c0: i2c@4900000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04900000 0x00 0x100>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 106 2>;
+ clock-names = "fck";
+ };
+
+ mcu_i2c1: i2c@4910000 {
+ compatible = "ti,am64-i2c", "ti,omap4-i2c";
+ reg = <0x00 0x04910000 0x00 0x100>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 2>;
+ clock-names = "fck";
+ };
+
+ mcu_spi0: spi@4b00000 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04b00000 0x00 0x400>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 147 0>;
+ };
+
+ mcu_spi1: spi@4b10000 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x04b10000 0x00 0x400>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 148 0>;
+ };
+};
diff --git a/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
new file mode 100644
index 0000000..64a159f
--- /dev/null
+++ b/arch/arm/dts/k3-am64-sk-lp4-1333MTs.dtsi
@@ -0,0 +1,2190 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated with the
+ * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.06.00
+ * Mon Apr 26 2021 20:47:47 GMT-0500 (Central Daylight Time)
+ * DDR Type: LPDDR4
+ * F0 = 50MHz F1 = 666.7MHz F2 = 666.7MHz
+ * Density (per channel): 16Gb
+ * Number of Ranks: 1
+*/
+
+#define DDRSS_PLL_FHS_CNT 6
+#define DDRSS_PLL_FREQUENCY_1 333350000
+#define DDRSS_PLL_FREQUENCY_2 333350000
+
+#define DDRSS_CTL_0_DATA 0x00000B00
+#define DDRSS_CTL_1_DATA 0x00000000
+#define DDRSS_CTL_2_DATA 0x00000000
+#define DDRSS_CTL_3_DATA 0x00000000
+#define DDRSS_CTL_4_DATA 0x00000000
+#define DDRSS_CTL_5_DATA 0x00000000
+#define DDRSS_CTL_6_DATA 0x00000000
+#define DDRSS_CTL_7_DATA 0x00002710
+#define DDRSS_CTL_8_DATA 0x000186A0
+#define DDRSS_CTL_9_DATA 0x00000005
+#define DDRSS_CTL_10_DATA 0x00000064
+#define DDRSS_CTL_11_DATA 0x000208D6
+#define DDRSS_CTL_12_DATA 0x00145856
+#define DDRSS_CTL_13_DATA 0x00000005
+#define DDRSS_CTL_14_DATA 0x00000536
+#define DDRSS_CTL_15_DATA 0x000208D6
+#define DDRSS_CTL_16_DATA 0x00145856
+#define DDRSS_CTL_17_DATA 0x00000005
+#define DDRSS_CTL_18_DATA 0x00000536
+#define DDRSS_CTL_19_DATA 0x01010100
+#define DDRSS_CTL_20_DATA 0x01010100
+#define DDRSS_CTL_21_DATA 0x01000110
+#define DDRSS_CTL_22_DATA 0x02010002
+#define DDRSS_CTL_23_DATA 0x0000000A
+#define DDRSS_CTL_24_DATA 0x000186A0
+#define DDRSS_CTL_25_DATA 0x00000000
+#define DDRSS_CTL_26_DATA 0x00000000
+#define DDRSS_CTL_27_DATA 0x00000000
+#define DDRSS_CTL_28_DATA 0x00000000
+#define DDRSS_CTL_29_DATA 0x00020200
+#define DDRSS_CTL_30_DATA 0x00000000
+#define DDRSS_CTL_31_DATA 0x00000000
+#define DDRSS_CTL_32_DATA 0x00000000
+#define DDRSS_CTL_33_DATA 0x00000000
+#define DDRSS_CTL_34_DATA 0x02000010
+#define DDRSS_CTL_35_DATA 0x00001B1B
+#define DDRSS_CTL_36_DATA 0x00000000
+#define DDRSS_CTL_37_DATA 0x00000000
+#define DDRSS_CTL_38_DATA 0x0000040C
+#define DDRSS_CTL_39_DATA 0x00000000
+#define DDRSS_CTL_40_DATA 0x0000081C
+#define DDRSS_CTL_41_DATA 0x00000000
+#define DDRSS_CTL_42_DATA 0x0000081C
+#define DDRSS_CTL_43_DATA 0x00000000
+#define DDRSS_CTL_44_DATA 0x05000804
+#define DDRSS_CTL_45_DATA 0x00000700
+#define DDRSS_CTL_46_DATA 0x09090004
+#define DDRSS_CTL_47_DATA 0x00000203
+#define DDRSS_CTL_48_DATA 0x00290006
+#define DDRSS_CTL_49_DATA 0x0909001D
+#define DDRSS_CTL_50_DATA 0x0000150C
+#define DDRSS_CTL_51_DATA 0x00290006
+#define DDRSS_CTL_52_DATA 0x0909001D
+#define DDRSS_CTL_53_DATA 0x0900150C
+#define DDRSS_CTL_54_DATA 0x000A0A09
+#define DDRSS_CTL_55_DATA 0x040006DB
+#define DDRSS_CTL_56_DATA 0x09092004
+#define DDRSS_CTL_57_DATA 0x00000A0A
+#define DDRSS_CTL_58_DATA 0x05005B68
+#define DDRSS_CTL_59_DATA 0x09092005
+#define DDRSS_CTL_60_DATA 0x00000A0A
+#define DDRSS_CTL_61_DATA 0x05005B68
+#define DDRSS_CTL_62_DATA 0x03042005
+#define DDRSS_CTL_63_DATA 0x04050002
+#define DDRSS_CTL_64_DATA 0x0E0D0E0D
+#define DDRSS_CTL_65_DATA 0x01010008
+#define DDRSS_CTL_66_DATA 0x041A1A07
+#define DDRSS_CTL_67_DATA 0x030E0E03
+#define DDRSS_CTL_68_DATA 0x00000E0E
+#define DDRSS_CTL_69_DATA 0x00000101
+#define DDRSS_CTL_70_DATA 0x00000000
+#define DDRSS_CTL_71_DATA 0x01000000
+#define DDRSS_CTL_72_DATA 0x00130803
+#define DDRSS_CTL_73_DATA 0x000000BB
+#define DDRSS_CTL_74_DATA 0x000000FE
+#define DDRSS_CTL_75_DATA 0x00000A20
+#define DDRSS_CTL_76_DATA 0x000000FE
+#define DDRSS_CTL_77_DATA 0x00000A20
+#define DDRSS_CTL_78_DATA 0x00000005
+#define DDRSS_CTL_79_DATA 0x0000000A
+#define DDRSS_CTL_80_DATA 0x00000010
+#define DDRSS_CTL_81_DATA 0x0000007F
+#define DDRSS_CTL_82_DATA 0x0000013D
+#define DDRSS_CTL_83_DATA 0x0000007F
+#define DDRSS_CTL_84_DATA 0x0000013D
+#define DDRSS_CTL_85_DATA 0x03004000
+#define DDRSS_CTL_86_DATA 0x00001201
+#define DDRSS_CTL_87_DATA 0x00050005
+#define DDRSS_CTL_88_DATA 0x00000005
+#define DDRSS_CTL_89_DATA 0x00000000
+#define DDRSS_CTL_90_DATA 0x05101008
+#define DDRSS_CTL_91_DATA 0x05030A05
+#define DDRSS_CTL_92_DATA 0x05030A05
+#define DDRSS_CTL_93_DATA 0x01030A05
+#define DDRSS_CTL_94_DATA 0x02010201
+#define DDRSS_CTL_95_DATA 0x00001401
+#define DDRSS_CTL_96_DATA 0x01030014
+#define DDRSS_CTL_97_DATA 0x01030103
+#define DDRSS_CTL_98_DATA 0x00000103
+#define DDRSS_CTL_99_DATA 0x00000000
+#define DDRSS_CTL_100_DATA 0x05010303
+#define DDRSS_CTL_101_DATA 0x0A040505
+#define DDRSS_CTL_102_DATA 0x05050203
+#define DDRSS_CTL_103_DATA 0x030A0505
+#define DDRSS_CTL_104_DATA 0x05050502
+#define DDRSS_CTL_105_DATA 0x03030305
+#define DDRSS_CTL_106_DATA 0x03010000
+#define DDRSS_CTL_107_DATA 0x00010000
+#define DDRSS_CTL_108_DATA 0x00000000
+#define DDRSS_CTL_109_DATA 0x01000000
+#define DDRSS_CTL_110_DATA 0x80104002
+#define DDRSS_CTL_111_DATA 0x00040003
+#define DDRSS_CTL_112_DATA 0x00040005
+#define DDRSS_CTL_113_DATA 0x00030000
+#define DDRSS_CTL_114_DATA 0x00050004
+#define DDRSS_CTL_115_DATA 0x00000004
+#define DDRSS_CTL_116_DATA 0x00040003
+#define DDRSS_CTL_117_DATA 0x00040005
+#define DDRSS_CTL_118_DATA 0x00000000
+#define DDRSS_CTL_119_DATA 0x00002EC0
+#define DDRSS_CTL_120_DATA 0x00002EC0
+#define DDRSS_CTL_121_DATA 0x00002EC0
+#define DDRSS_CTL_122_DATA 0x00002EC0
+#define DDRSS_CTL_123_DATA 0x00002EC0
+#define DDRSS_CTL_124_DATA 0x00000000
+#define DDRSS_CTL_125_DATA 0x0000051D
+#define DDRSS_CTL_126_DATA 0x00028800
+#define DDRSS_CTL_127_DATA 0x00028800
+#define DDRSS_CTL_128_DATA 0x00028800
+#define DDRSS_CTL_129_DATA 0x00028800
+#define DDRSS_CTL_130_DATA 0x00028800
+#define DDRSS_CTL_131_DATA 0x00000000
+#define DDRSS_CTL_132_DATA 0x000046E0
+#define DDRSS_CTL_133_DATA 0x00028800
+#define DDRSS_CTL_134_DATA 0x00028800
+#define DDRSS_CTL_135_DATA 0x00028800
+#define DDRSS_CTL_136_DATA 0x00028800
+#define DDRSS_CTL_137_DATA 0x00028800
+#define DDRSS_CTL_138_DATA 0x00000000
+#define DDRSS_CTL_139_DATA 0x000046E0
+#define DDRSS_CTL_140_DATA 0x00000000
+#define DDRSS_CTL_141_DATA 0x00000000
+#define DDRSS_CTL_142_DATA 0x00000000
+#define DDRSS_CTL_143_DATA 0x00000000
+#define DDRSS_CTL_144_DATA 0x00000000
+#define DDRSS_CTL_145_DATA 0x00000000
+#define DDRSS_CTL_146_DATA 0x00000000
+#define DDRSS_CTL_147_DATA 0x00000000
+#define DDRSS_CTL_148_DATA 0x00000000
+#define DDRSS_CTL_149_DATA 0x00000000
+#define DDRSS_CTL_150_DATA 0x00000000
+#define DDRSS_CTL_151_DATA 0x00000000
+#define DDRSS_CTL_152_DATA 0x00000000
+#define DDRSS_CTL_153_DATA 0x00000000
+#define DDRSS_CTL_154_DATA 0x00000000
+#define DDRSS_CTL_155_DATA 0x00000000
+#define DDRSS_CTL_156_DATA 0x03050000
+#define DDRSS_CTL_157_DATA 0x03050305
+#define DDRSS_CTL_158_DATA 0x00000000
+#define DDRSS_CTL_159_DATA 0x07010A09
+#define DDRSS_CTL_160_DATA 0x000E0A09
+#define DDRSS_CTL_161_DATA 0x010A0900
+#define DDRSS_CTL_162_DATA 0x0E0A0907
+#define DDRSS_CTL_163_DATA 0x0A090000
+#define DDRSS_CTL_164_DATA 0x0A090701
+#define DDRSS_CTL_165_DATA 0x0000000E
+#define DDRSS_CTL_166_DATA 0x00040003
+#define DDRSS_CTL_167_DATA 0x00000007
+#define DDRSS_CTL_168_DATA 0x00000000
+#define DDRSS_CTL_169_DATA 0x00000000
+#define DDRSS_CTL_170_DATA 0x00000000
+#define DDRSS_CTL_171_DATA 0x00000000
+#define DDRSS_CTL_172_DATA 0x00000000
+#define DDRSS_CTL_173_DATA 0x00000000
+#define DDRSS_CTL_174_DATA 0x01000000
+#define DDRSS_CTL_175_DATA 0x00000000
+#define DDRSS_CTL_176_DATA 0x00001500
+#define DDRSS_CTL_177_DATA 0x0000100E
+#define DDRSS_CTL_178_DATA 0x00000002
+#define DDRSS_CTL_179_DATA 0x00000000
+#define DDRSS_CTL_180_DATA 0x00000001
+#define DDRSS_CTL_181_DATA 0x00000002
+#define DDRSS_CTL_182_DATA 0x00000C00
+#define DDRSS_CTL_183_DATA 0x00001000
+#define DDRSS_CTL_184_DATA 0x00000C00
+#define DDRSS_CTL_185_DATA 0x00001000
+#define DDRSS_CTL_186_DATA 0x00000C00
+#define DDRSS_CTL_187_DATA 0x00001000
+#define DDRSS_CTL_188_DATA 0x00000000
+#define DDRSS_CTL_189_DATA 0x00000000
+#define DDRSS_CTL_190_DATA 0x00000000
+#define DDRSS_CTL_191_DATA 0x00000000
+#define DDRSS_CTL_192_DATA 0x0005000A
+#define DDRSS_CTL_193_DATA 0x0404000D
+#define DDRSS_CTL_194_DATA 0x0000000D
+#define DDRSS_CTL_195_DATA 0x00430086
+#define DDRSS_CTL_196_DATA 0x050500A7
+#define DDRSS_CTL_197_DATA 0x000000A7
+#define DDRSS_CTL_198_DATA 0x00430086
+#define DDRSS_CTL_199_DATA 0x050500A7
+#define DDRSS_CTL_200_DATA 0x000000A7
+#define DDRSS_CTL_201_DATA 0x00000000
+#define DDRSS_CTL_202_DATA 0x00000000
+#define DDRSS_CTL_203_DATA 0x00000000
+#define DDRSS_CTL_204_DATA 0x00000000
+#define DDRSS_CTL_205_DATA 0x00000004
+#define DDRSS_CTL_206_DATA 0x00000000
+#define DDRSS_CTL_207_DATA 0x00000000
+#define DDRSS_CTL_208_DATA 0x00000024
+#define DDRSS_CTL_209_DATA 0x00000012
+#define DDRSS_CTL_210_DATA 0x00000000
+#define DDRSS_CTL_211_DATA 0x00000024
+#define DDRSS_CTL_212_DATA 0x00000012
+#define DDRSS_CTL_213_DATA 0x00000000
+#define DDRSS_CTL_214_DATA 0x00000004
+#define DDRSS_CTL_215_DATA 0x00000000
+#define DDRSS_CTL_216_DATA 0x00000000
+#define DDRSS_CTL_217_DATA 0x00000024
+#define DDRSS_CTL_218_DATA 0x00000012
+#define DDRSS_CTL_219_DATA 0x00000000
+#define DDRSS_CTL_220_DATA 0x00000024
+#define DDRSS_CTL_221_DATA 0x00000012
+#define DDRSS_CTL_222_DATA 0x00000000
+#define DDRSS_CTL_223_DATA 0x00000000
+#define DDRSS_CTL_224_DATA 0x00000031
+#define DDRSS_CTL_225_DATA 0x00000031
+#define DDRSS_CTL_226_DATA 0x00000031
+#define DDRSS_CTL_227_DATA 0x00000031
+#define DDRSS_CTL_228_DATA 0x00000031
+#define DDRSS_CTL_229_DATA 0x00000031
+#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_231_DATA 0x00000000
+#define DDRSS_CTL_232_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0x00000000
+#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_235_DATA 0x00000000
+#define DDRSS_CTL_236_DATA 0x00000000
+#define DDRSS_CTL_237_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0x00000000
+#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_240_DATA 0x00000000
+#define DDRSS_CTL_241_DATA 0x00000000
+#define DDRSS_CTL_242_DATA 0x00000000
+#define DDRSS_CTL_243_DATA 0x00000000
+#define DDRSS_CTL_244_DATA 0x00000000
+#define DDRSS_CTL_245_DATA 0x00000000
+#define DDRSS_CTL_246_DATA 0x00000000
+#define DDRSS_CTL_247_DATA 0x00000000
+#define DDRSS_CTL_248_DATA 0x00000000
+#define DDRSS_CTL_249_DATA 0x00000000
+#define DDRSS_CTL_250_DATA 0x00000000
+#define DDRSS_CTL_251_DATA 0x00000000
+#define DDRSS_CTL_252_DATA 0x00000000
+#define DDRSS_CTL_253_DATA 0x00000000
+#define DDRSS_CTL_254_DATA 0x66006666
+#define DDRSS_CTL_255_DATA 0x00002766
+#define DDRSS_CTL_256_DATA 0x00000027
+#define DDRSS_CTL_257_DATA 0x00000027
+#define DDRSS_CTL_258_DATA 0x00000027
+#define DDRSS_CTL_259_DATA 0x00000027
+#define DDRSS_CTL_260_DATA 0x00000027
+#define DDRSS_CTL_261_DATA 0x00000000
+#define DDRSS_CTL_262_DATA 0x00000000
+#define DDRSS_CTL_263_DATA 0x0000000F
+#define DDRSS_CTL_264_DATA 0x0000000F
+#define DDRSS_CTL_265_DATA 0x0000000F
+#define DDRSS_CTL_266_DATA 0x0000000F
+#define DDRSS_CTL_267_DATA 0x0000000F
+#define DDRSS_CTL_268_DATA 0x0000000F
+#define DDRSS_CTL_269_DATA 0x00000000
+#define DDRSS_CTL_270_DATA 0x00000000
+#define DDRSS_CTL_271_DATA 0x00000015
+#define DDRSS_CTL_272_DATA 0x00000015
+#define DDRSS_CTL_273_DATA 0x00000000
+#define DDRSS_CTL_274_DATA 0x00000015
+#define DDRSS_CTL_275_DATA 0x00000015
+#define DDRSS_CTL_276_DATA 0x00000020
+#define DDRSS_CTL_277_DATA 0x00010000
+#define DDRSS_CTL_278_DATA 0x00000100
+#define DDRSS_CTL_279_DATA 0x00000000
+#define DDRSS_CTL_280_DATA 0x00000000
+#define DDRSS_CTL_281_DATA 0x00000101
+#define DDRSS_CTL_282_DATA 0x00000000
+#define DDRSS_CTL_283_DATA 0x00000000
+#define DDRSS_CTL_284_DATA 0x00000000
+#define DDRSS_CTL_285_DATA 0x00000000
+#define DDRSS_CTL_286_DATA 0x00000000
+#define DDRSS_CTL_287_DATA 0x00000000
+#define DDRSS_CTL_288_DATA 0x00000000
+#define DDRSS_CTL_289_DATA 0x00000000
+#define DDRSS_CTL_290_DATA 0x0C181511
+#define DDRSS_CTL_291_DATA 0x00000304
+#define DDRSS_CTL_292_DATA 0x00000000
+#define DDRSS_CTL_293_DATA 0x00000000
+#define DDRSS_CTL_294_DATA 0x00000000
+#define DDRSS_CTL_295_DATA 0x00000000
+#define DDRSS_CTL_296_DATA 0x00000000
+#define DDRSS_CTL_297_DATA 0x00000000
+#define DDRSS_CTL_298_DATA 0x00000000
+#define DDRSS_CTL_299_DATA 0x00000000
+#define DDRSS_CTL_300_DATA 0x00000000
+#define DDRSS_CTL_301_DATA 0x00000000
+#define DDRSS_CTL_302_DATA 0x00000000
+#define DDRSS_CTL_303_DATA 0x00000000
+#define DDRSS_CTL_304_DATA 0x00000000
+#define DDRSS_CTL_305_DATA 0x00020000
+#define DDRSS_CTL_306_DATA 0x00400100
+#define DDRSS_CTL_307_DATA 0x00080032
+#define DDRSS_CTL_308_DATA 0x01000200
+#define DDRSS_CTL_309_DATA 0x029B0040
+#define DDRSS_CTL_310_DATA 0x00020014
+#define DDRSS_CTL_311_DATA 0x00400100
+#define DDRSS_CTL_312_DATA 0x0014029B
+#define DDRSS_CTL_313_DATA 0x00030000
+#define DDRSS_CTL_314_DATA 0x00220022
+#define DDRSS_CTL_315_DATA 0x00000100
+#define DDRSS_CTL_316_DATA 0x01010000
+#define DDRSS_CTL_317_DATA 0x00000000
+#define DDRSS_CTL_318_DATA 0x3FFF0000
+#define DDRSS_CTL_319_DATA 0x000FFF00
+#define DDRSS_CTL_320_DATA 0xFFFFFFFF
+#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_322_DATA 0x0B000000
+#define DDRSS_CTL_323_DATA 0x0001FFFF
+#define DDRSS_CTL_324_DATA 0x01010101
+#define DDRSS_CTL_325_DATA 0x01010101
+#define DDRSS_CTL_326_DATA 0x00000118
+#define DDRSS_CTL_327_DATA 0x00000C01
+#define DDRSS_CTL_328_DATA 0x01000100
+#define DDRSS_CTL_329_DATA 0x00000000
+#define DDRSS_CTL_330_DATA 0x01000000
+#define DDRSS_CTL_331_DATA 0x01030303
+#define DDRSS_CTL_332_DATA 0x00000000
+#define DDRSS_CTL_333_DATA 0x00000000
+#define DDRSS_CTL_334_DATA 0x00000000
+#define DDRSS_CTL_335_DATA 0x00000000
+#define DDRSS_CTL_336_DATA 0x00000000
+#define DDRSS_CTL_337_DATA 0x00000000
+#define DDRSS_CTL_338_DATA 0x00000000
+#define DDRSS_CTL_339_DATA 0x00000000
+#define DDRSS_CTL_340_DATA 0x00000000
+#define DDRSS_CTL_341_DATA 0x00000000
+#define DDRSS_CTL_342_DATA 0x00000000
+#define DDRSS_CTL_343_DATA 0x00000000
+#define DDRSS_CTL_344_DATA 0x00000000
+#define DDRSS_CTL_345_DATA 0x00000000
+#define DDRSS_CTL_346_DATA 0x00000000
+#define DDRSS_CTL_347_DATA 0x00000000
+#define DDRSS_CTL_348_DATA 0x00000000
+#define DDRSS_CTL_349_DATA 0x00000000
+#define DDRSS_CTL_350_DATA 0x00000000
+#define DDRSS_CTL_351_DATA 0x00000000
+#define DDRSS_CTL_352_DATA 0x00000000
+#define DDRSS_CTL_353_DATA 0x00000000
+#define DDRSS_CTL_354_DATA 0x00000000
+#define DDRSS_CTL_355_DATA 0x00000000
+#define DDRSS_CTL_356_DATA 0x00000000
+#define DDRSS_CTL_357_DATA 0x00000000
+#define DDRSS_CTL_358_DATA 0x00000000
+#define DDRSS_CTL_359_DATA 0x00000000
+#define DDRSS_CTL_360_DATA 0x00000000
+#define DDRSS_CTL_361_DATA 0x00000000
+#define DDRSS_CTL_362_DATA 0x00000000
+#define DDRSS_CTL_363_DATA 0x00000000
+#define DDRSS_CTL_364_DATA 0x00000000
+#define DDRSS_CTL_365_DATA 0x00000000
+#define DDRSS_CTL_366_DATA 0x00000000
+#define DDRSS_CTL_367_DATA 0x00000000
+#define DDRSS_CTL_368_DATA 0x00000000
+#define DDRSS_CTL_369_DATA 0x00000000
+#define DDRSS_CTL_370_DATA 0x00000000
+#define DDRSS_CTL_371_DATA 0x01000101
+#define DDRSS_CTL_372_DATA 0x01010001
+#define DDRSS_CTL_373_DATA 0x00010101
+#define DDRSS_CTL_374_DATA 0x01050503
+#define DDRSS_CTL_375_DATA 0x05020201
+#define DDRSS_CTL_376_DATA 0x08080B0B
+#define DDRSS_CTL_377_DATA 0x00080308
+#define DDRSS_CTL_378_DATA 0x000C030E
+#define DDRSS_CTL_379_DATA 0x000C0310
+#define DDRSS_CTL_380_DATA 0x0C0C0810
+#define DDRSS_CTL_381_DATA 0x01000000
+#define DDRSS_CTL_382_DATA 0x03010301
+#define DDRSS_CTL_383_DATA 0x04000101
+#define DDRSS_CTL_384_DATA 0x1B000004
+#define DDRSS_CTL_385_DATA 0x00000176
+#define DDRSS_CTL_386_DATA 0x00000200
+#define DDRSS_CTL_387_DATA 0x00000200
+#define DDRSS_CTL_388_DATA 0x00000200
+#define DDRSS_CTL_389_DATA 0x00000200
+#define DDRSS_CTL_390_DATA 0x00000693
+#define DDRSS_CTL_391_DATA 0x00000E9C
+#define DDRSS_CTL_392_DATA 0x03050202
+#define DDRSS_CTL_393_DATA 0x00240201
+#define DDRSS_CTL_394_DATA 0x00001440
+#define DDRSS_CTL_395_DATA 0x00000200
+#define DDRSS_CTL_396_DATA 0x00000200
+#define DDRSS_CTL_397_DATA 0x00000200
+#define DDRSS_CTL_398_DATA 0x00000200
+#define DDRSS_CTL_399_DATA 0x00005B20
+#define DDRSS_CTL_400_DATA 0x0000CA80
+#define DDRSS_CTL_401_DATA 0x080D0402
+#define DDRSS_CTL_402_DATA 0x00240405
+#define DDRSS_CTL_403_DATA 0x00001440
+#define DDRSS_CTL_404_DATA 0x00000200
+#define DDRSS_CTL_405_DATA 0x00000200
+#define DDRSS_CTL_406_DATA 0x00000200
+#define DDRSS_CTL_407_DATA 0x00000200
+#define DDRSS_CTL_408_DATA 0x00005B20
+#define DDRSS_CTL_409_DATA 0x0000CA80
+#define DDRSS_CTL_410_DATA 0x080D0402
+#define DDRSS_CTL_411_DATA 0x00000405
+#define DDRSS_CTL_412_DATA 0x00000000
+#define DDRSS_CTL_413_DATA 0x0302000A
+#define DDRSS_CTL_414_DATA 0x01000500
+#define DDRSS_CTL_415_DATA 0x01010001
+#define DDRSS_CTL_416_DATA 0x00010001
+#define DDRSS_CTL_417_DATA 0x01010001
+#define DDRSS_CTL_418_DATA 0x02010000
+#define DDRSS_CTL_419_DATA 0x00000200
+#define DDRSS_CTL_420_DATA 0x02000201
+#define DDRSS_CTL_421_DATA 0x10100600
+#define DDRSS_CTL_422_DATA 0x00202020
+#define DDRSS_PI_0_DATA 0x00000B00
+#define DDRSS_PI_1_DATA 0x00000000
+#define DDRSS_PI_2_DATA 0x00000000
+#define DDRSS_PI_3_DATA 0x01000000
+#define DDRSS_PI_4_DATA 0x00000001
+#define DDRSS_PI_5_DATA 0x00010064
+#define DDRSS_PI_6_DATA 0x00000000
+#define DDRSS_PI_7_DATA 0x00000000
+#define DDRSS_PI_8_DATA 0x00000000
+#define DDRSS_PI_9_DATA 0x00000000
+#define DDRSS_PI_10_DATA 0x00000000
+#define DDRSS_PI_11_DATA 0x00000002
+#define DDRSS_PI_12_DATA 0x00000007
+#define DDRSS_PI_13_DATA 0x00010001
+#define DDRSS_PI_14_DATA 0x08000000
+#define DDRSS_PI_15_DATA 0x00010300
+#define DDRSS_PI_16_DATA 0x00000005
+#define DDRSS_PI_17_DATA 0x00000000
+#define DDRSS_PI_18_DATA 0x00000000
+#define DDRSS_PI_19_DATA 0x00000000
+#define DDRSS_PI_20_DATA 0x00000000
+#define DDRSS_PI_21_DATA 0x00000000
+#define DDRSS_PI_22_DATA 0x00000000
+#define DDRSS_PI_23_DATA 0x00010000
+#define DDRSS_PI_24_DATA 0x280A0001
+#define DDRSS_PI_25_DATA 0x00000000
+#define DDRSS_PI_26_DATA 0x00010000
+#define DDRSS_PI_27_DATA 0x00003200
+#define DDRSS_PI_28_DATA 0x00000000
+#define DDRSS_PI_29_DATA 0x00000000
+#define DDRSS_PI_30_DATA 0x01010102
+#define DDRSS_PI_31_DATA 0x00000000
+#define DDRSS_PI_32_DATA 0x00000000
+#define DDRSS_PI_33_DATA 0x00000000
+#define DDRSS_PI_34_DATA 0x00000001
+#define DDRSS_PI_35_DATA 0x000000AA
+#define DDRSS_PI_36_DATA 0x00000055
+#define DDRSS_PI_37_DATA 0x000000B5
+#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_39_DATA 0x00000056
+#define DDRSS_PI_40_DATA 0x000000A9
+#define DDRSS_PI_41_DATA 0x000000A9
+#define DDRSS_PI_42_DATA 0x000000B5
+#define DDRSS_PI_43_DATA 0x00000000
+#define DDRSS_PI_44_DATA 0x00000000
+#define DDRSS_PI_45_DATA 0x00010100
+#define DDRSS_PI_46_DATA 0x00000014
+#define DDRSS_PI_47_DATA 0x000007D0
+#define DDRSS_PI_48_DATA 0x00000300
+#define DDRSS_PI_49_DATA 0x00000000
+#define DDRSS_PI_50_DATA 0x00000000
+#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_52_DATA 0x00010101
+#define DDRSS_PI_53_DATA 0x01000000
+#define DDRSS_PI_54_DATA 0x03000000
+#define DDRSS_PI_55_DATA 0x00000000
+#define DDRSS_PI_56_DATA 0x00001701
+#define DDRSS_PI_57_DATA 0x00000000
+#define DDRSS_PI_58_DATA 0x00000000
+#define DDRSS_PI_59_DATA 0x00000000
+#define DDRSS_PI_60_DATA 0x0A0A140A
+#define DDRSS_PI_61_DATA 0x10020101
+#define DDRSS_PI_62_DATA 0x01000210
+#define DDRSS_PI_63_DATA 0x05000404
+#define DDRSS_PI_64_DATA 0x00010001
+#define DDRSS_PI_65_DATA 0x0001000E
+#define DDRSS_PI_66_DATA 0x01010100
+#define DDRSS_PI_67_DATA 0x00010000
+#define DDRSS_PI_68_DATA 0x00000034
+#define DDRSS_PI_69_DATA 0x00000000
+#define DDRSS_PI_70_DATA 0x00000000
+#define DDRSS_PI_71_DATA 0x0000FFFF
+#define DDRSS_PI_72_DATA 0x00000000
+#define DDRSS_PI_73_DATA 0x00000000
+#define DDRSS_PI_74_DATA 0x00000000
+#define DDRSS_PI_75_DATA 0x00000000
+#define DDRSS_PI_76_DATA 0x01000000
+#define DDRSS_PI_77_DATA 0x08000100
+#define DDRSS_PI_78_DATA 0x00020000
+#define DDRSS_PI_79_DATA 0x00010002
+#define DDRSS_PI_80_DATA 0x00000001
+#define DDRSS_PI_81_DATA 0x00020001
+#define DDRSS_PI_82_DATA 0x00020002
+#define DDRSS_PI_83_DATA 0x00000000
+#define DDRSS_PI_84_DATA 0x00000000
+#define DDRSS_PI_85_DATA 0x00000000
+#define DDRSS_PI_86_DATA 0x00000000
+#define DDRSS_PI_87_DATA 0x00000000
+#define DDRSS_PI_88_DATA 0x00000000
+#define DDRSS_PI_89_DATA 0x00000000
+#define DDRSS_PI_90_DATA 0x00000000
+#define DDRSS_PI_91_DATA 0x00000400
+#define DDRSS_PI_92_DATA 0x0A090B0C
+#define DDRSS_PI_93_DATA 0x04060708
+#define DDRSS_PI_94_DATA 0x01000005
+#define DDRSS_PI_95_DATA 0x00000800
+#define DDRSS_PI_96_DATA 0x00000000
+#define DDRSS_PI_97_DATA 0x00010008
+#define DDRSS_PI_98_DATA 0x00000000
+#define DDRSS_PI_99_DATA 0x0000AA00
+#define DDRSS_PI_100_DATA 0x00000000
+#define DDRSS_PI_101_DATA 0x00010000
+#define DDRSS_PI_102_DATA 0x00000000
+#define DDRSS_PI_103_DATA 0x00000000
+#define DDRSS_PI_104_DATA 0x00000000
+#define DDRSS_PI_105_DATA 0x00000000
+#define DDRSS_PI_106_DATA 0x00000000
+#define DDRSS_PI_107_DATA 0x00000000
+#define DDRSS_PI_108_DATA 0x00000000
+#define DDRSS_PI_109_DATA 0x00000000
+#define DDRSS_PI_110_DATA 0x00000000
+#define DDRSS_PI_111_DATA 0x00000000
+#define DDRSS_PI_112_DATA 0x00000000
+#define DDRSS_PI_113_DATA 0x00000000
+#define DDRSS_PI_114_DATA 0x00000000
+#define DDRSS_PI_115_DATA 0x00000000
+#define DDRSS_PI_116_DATA 0x00000000
+#define DDRSS_PI_117_DATA 0x00000000
+#define DDRSS_PI_118_DATA 0x00000000
+#define DDRSS_PI_119_DATA 0x00000000
+#define DDRSS_PI_120_DATA 0x00000000
+#define DDRSS_PI_121_DATA 0x00000000
+#define DDRSS_PI_122_DATA 0x00000000
+#define DDRSS_PI_123_DATA 0x00000000
+#define DDRSS_PI_124_DATA 0x00000008
+#define DDRSS_PI_125_DATA 0x00000000
+#define DDRSS_PI_126_DATA 0x00000000
+#define DDRSS_PI_127_DATA 0x00000000
+#define DDRSS_PI_128_DATA 0x00000000
+#define DDRSS_PI_129_DATA 0x00000000
+#define DDRSS_PI_130_DATA 0x00000000
+#define DDRSS_PI_131_DATA 0x00000000
+#define DDRSS_PI_132_DATA 0x00000000
+#define DDRSS_PI_133_DATA 0x00010000
+#define DDRSS_PI_134_DATA 0x00000000
+#define DDRSS_PI_135_DATA 0x00000000
+#define DDRSS_PI_136_DATA 0x0000000A
+#define DDRSS_PI_137_DATA 0x000186A0
+#define DDRSS_PI_138_DATA 0x00000100
+#define DDRSS_PI_139_DATA 0x00000000
+#define DDRSS_PI_140_DATA 0x00000000
+#define DDRSS_PI_141_DATA 0x00000000
+#define DDRSS_PI_142_DATA 0x00000000
+#define DDRSS_PI_143_DATA 0x00000000
+#define DDRSS_PI_144_DATA 0x01000000
+#define DDRSS_PI_145_DATA 0x00010003
+#define DDRSS_PI_146_DATA 0x02000101
+#define DDRSS_PI_147_DATA 0x01030001
+#define DDRSS_PI_148_DATA 0x00010400
+#define DDRSS_PI_149_DATA 0x06000105
+#define DDRSS_PI_150_DATA 0x01070001
+#define DDRSS_PI_151_DATA 0x00000000
+#define DDRSS_PI_152_DATA 0x00000000
+#define DDRSS_PI_153_DATA 0x00000000
+#define DDRSS_PI_154_DATA 0x00010001
+#define DDRSS_PI_155_DATA 0x00000000
+#define DDRSS_PI_156_DATA 0x00000000
+#define DDRSS_PI_157_DATA 0x00000000
+#define DDRSS_PI_158_DATA 0x00000000
+#define DDRSS_PI_159_DATA 0x00010000
+#define DDRSS_PI_160_DATA 0x00000004
+#define DDRSS_PI_161_DATA 0x00000000
+#define DDRSS_PI_162_DATA 0x00000000
+#define DDRSS_PI_163_DATA 0x00000000
+#define DDRSS_PI_164_DATA 0x00000800
+#define DDRSS_PI_165_DATA 0x00640064
+#define DDRSS_PI_166_DATA 0x000E0E01
+#define DDRSS_PI_167_DATA 0x00000034
+#define DDRSS_PI_168_DATA 0x00000042
+#define DDRSS_PI_169_DATA 0x00020042
+#define DDRSS_PI_170_DATA 0x02000200
+#define DDRSS_PI_171_DATA 0x00000004
+#define DDRSS_PI_172_DATA 0x0000080C
+#define DDRSS_PI_173_DATA 0x00081C00
+#define DDRSS_PI_174_DATA 0x001C0000
+#define DDRSS_PI_175_DATA 0x00000013
+#define DDRSS_PI_176_DATA 0x000000BB
+#define DDRSS_PI_177_DATA 0x000000FE
+#define DDRSS_PI_178_DATA 0x00000A20
+#define DDRSS_PI_179_DATA 0x000000FE
+#define DDRSS_PI_180_DATA 0x04000A20
+#define DDRSS_PI_181_DATA 0x01010404
+#define DDRSS_PI_182_DATA 0x00001501
+#define DDRSS_PI_183_DATA 0x001B001B
+#define DDRSS_PI_184_DATA 0x01000100
+#define DDRSS_PI_185_DATA 0x00000100
+#define DDRSS_PI_186_DATA 0x00000000
+#define DDRSS_PI_187_DATA 0x05050503
+#define DDRSS_PI_188_DATA 0x01010B0B
+#define DDRSS_PI_189_DATA 0x01010101
+#define DDRSS_PI_190_DATA 0x000C0C0A
+#define DDRSS_PI_191_DATA 0x00000000
+#define DDRSS_PI_192_DATA 0x00000000
+#define DDRSS_PI_193_DATA 0x04000000
+#define DDRSS_PI_194_DATA 0x04020909
+#define DDRSS_PI_195_DATA 0x04040204
+#define DDRSS_PI_196_DATA 0x00090031
+#define DDRSS_PI_197_DATA 0x000F0037
+#define DDRSS_PI_198_DATA 0x000F0037
+#define DDRSS_PI_199_DATA 0x01010101
+#define DDRSS_PI_200_DATA 0x0001000D
+#define DDRSS_PI_201_DATA 0x000100A7
+#define DDRSS_PI_202_DATA 0x010000A7
+#define DDRSS_PI_203_DATA 0x000E000E
+#define DDRSS_PI_204_DATA 0x00A80100
+#define DDRSS_PI_205_DATA 0x010000A8
+#define DDRSS_PI_206_DATA 0x00A800A8
+#define DDRSS_PI_207_DATA 0x32103200
+#define DDRSS_PI_208_DATA 0x01013210
+#define DDRSS_PI_209_DATA 0x0A070601
+#define DDRSS_PI_210_DATA 0x0B08070D
+#define DDRSS_PI_211_DATA 0x0B08070D
+#define DDRSS_PI_212_DATA 0x000C000D
+#define DDRSS_PI_213_DATA 0x00001000
+#define DDRSS_PI_214_DATA 0x00000C00
+#define DDRSS_PI_215_DATA 0x00001000
+#define DDRSS_PI_216_DATA 0x00000C00
+#define DDRSS_PI_217_DATA 0x02001000
+#define DDRSS_PI_218_DATA 0x0015000D
+#define DDRSS_PI_219_DATA 0x001500A7
+#define DDRSS_PI_220_DATA 0x000000A7
+#define DDRSS_PI_221_DATA 0x00001900
+#define DDRSS_PI_222_DATA 0x32000056
+#define DDRSS_PI_223_DATA 0x06000301
+#define DDRSS_PI_224_DATA 0x001D0204
+#define DDRSS_PI_225_DATA 0x32120059
+#define DDRSS_PI_226_DATA 0x05000301
+#define DDRSS_PI_227_DATA 0x001D0409
+#define DDRSS_PI_228_DATA 0x32120059
+#define DDRSS_PI_229_DATA 0x05000301
+#define DDRSS_PI_230_DATA 0x00000409
+#define DDRSS_PI_231_DATA 0x05030900
+#define DDRSS_PI_232_DATA 0x00040900
+#define DDRSS_PI_233_DATA 0x0000062B
+#define DDRSS_PI_234_DATA 0x20010004
+#define DDRSS_PI_235_DATA 0x0A0A0A03
+#define DDRSS_PI_236_DATA 0x0E090000
+#define DDRSS_PI_237_DATA 0x0E09000D
+#define DDRSS_PI_238_DATA 0x00005244
+#define DDRSS_PI_239_DATA 0x2003001D
+#define DDRSS_PI_240_DATA 0x0A0A0A0A
+#define DDRSS_PI_241_DATA 0x0E090000
+#define DDRSS_PI_242_DATA 0x0E09000D
+#define DDRSS_PI_243_DATA 0x00005244
+#define DDRSS_PI_244_DATA 0x2003001D
+#define DDRSS_PI_245_DATA 0x0A0A0A0A
+#define DDRSS_PI_246_DATA 0x00000000
+#define DDRSS_PI_247_DATA 0x00000176
+#define DDRSS_PI_248_DATA 0x00000E9C
+#define DDRSS_PI_249_DATA 0x00001440
+#define DDRSS_PI_250_DATA 0x0000CA80
+#define DDRSS_PI_251_DATA 0x00001440
+#define DDRSS_PI_252_DATA 0x0000CA80
+#define DDRSS_PI_253_DATA 0x01030014
+#define DDRSS_PI_254_DATA 0x03030103
+#define DDRSS_PI_255_DATA 0x00000003
+#define DDRSS_PI_256_DATA 0x00000000
+#define DDRSS_PI_257_DATA 0x05030503
+#define DDRSS_PI_258_DATA 0x00000503
+#define DDRSS_PI_259_DATA 0x00002710
+#define DDRSS_PI_260_DATA 0x000186A0
+#define DDRSS_PI_261_DATA 0x00000005
+#define DDRSS_PI_262_DATA 0x00000064
+#define DDRSS_PI_263_DATA 0x00000014
+#define DDRSS_PI_264_DATA 0x000208D6
+#define DDRSS_PI_265_DATA 0x000186A0
+#define DDRSS_PI_266_DATA 0x00000005
+#define DDRSS_PI_267_DATA 0x00000536
+#define DDRSS_PI_268_DATA 0x00000103
+#define DDRSS_PI_269_DATA 0x000208D6
+#define DDRSS_PI_270_DATA 0x000186A0
+#define DDRSS_PI_271_DATA 0x00000005
+#define DDRSS_PI_272_DATA 0x00000536
+#define DDRSS_PI_273_DATA 0x01000103
+#define DDRSS_PI_274_DATA 0x00320040
+#define DDRSS_PI_275_DATA 0x00010008
+#define DDRSS_PI_276_DATA 0x029B0040
+#define DDRSS_PI_277_DATA 0x00010014
+#define DDRSS_PI_278_DATA 0x029B0040
+#define DDRSS_PI_279_DATA 0x00000314
+#define DDRSS_PI_280_DATA 0x00280021
+#define DDRSS_PI_281_DATA 0x03040404
+#define DDRSS_PI_282_DATA 0x00000303
+#define DDRSS_PI_283_DATA 0x02020101
+#define DDRSS_PI_284_DATA 0x67676767
+#define DDRSS_PI_285_DATA 0x00000000
+#define DDRSS_PI_286_DATA 0x55000000
+#define DDRSS_PI_287_DATA 0x00000000
+#define DDRSS_PI_288_DATA 0x3C00005A
+#define DDRSS_PI_289_DATA 0x00005500
+#define DDRSS_PI_290_DATA 0x00005A00
+#define DDRSS_PI_291_DATA 0x0D100F3C
+#define DDRSS_PI_292_DATA 0x0003020E
+#define DDRSS_PI_293_DATA 0x00000001
+#define DDRSS_PI_294_DATA 0x01000000
+#define DDRSS_PI_295_DATA 0x00020201
+#define DDRSS_PI_296_DATA 0x00000000
+#define DDRSS_PI_297_DATA 0x00000000
+#define DDRSS_PI_298_DATA 0x00000004
+#define DDRSS_PI_299_DATA 0x00000000
+#define DDRSS_PI_300_DATA 0x00000031
+#define DDRSS_PI_301_DATA 0x00000000
+#define DDRSS_PI_302_DATA 0x00000000
+#define DDRSS_PI_303_DATA 0x00000000
+#define DDRSS_PI_304_DATA 0x00000F27
+#define DDRSS_PI_305_DATA 0x00000000
+#define DDRSS_PI_306_DATA 0x00000024
+#define DDRSS_PI_307_DATA 0x00000012
+#define DDRSS_PI_308_DATA 0x00000031
+#define DDRSS_PI_309_DATA 0x00000000
+#define DDRSS_PI_310_DATA 0x00000000
+#define DDRSS_PI_311_DATA 0x66000000
+#define DDRSS_PI_312_DATA 0x00150F27
+#define DDRSS_PI_313_DATA 0x00000000
+#define DDRSS_PI_314_DATA 0x00000024
+#define DDRSS_PI_315_DATA 0x00000012
+#define DDRSS_PI_316_DATA 0x00000031
+#define DDRSS_PI_317_DATA 0x00000000
+#define DDRSS_PI_318_DATA 0x00000000
+#define DDRSS_PI_319_DATA 0x66000000
+#define DDRSS_PI_320_DATA 0x00150F27
+#define DDRSS_PI_321_DATA 0x00000000
+#define DDRSS_PI_322_DATA 0x00000004
+#define DDRSS_PI_323_DATA 0x00000000
+#define DDRSS_PI_324_DATA 0x00000031
+#define DDRSS_PI_325_DATA 0x00000000
+#define DDRSS_PI_326_DATA 0x00000000
+#define DDRSS_PI_327_DATA 0x00000000
+#define DDRSS_PI_328_DATA 0x00000F27
+#define DDRSS_PI_329_DATA 0x00000000
+#define DDRSS_PI_330_DATA 0x00000024
+#define DDRSS_PI_331_DATA 0x00000012
+#define DDRSS_PI_332_DATA 0x00000031
+#define DDRSS_PI_333_DATA 0x00000000
+#define DDRSS_PI_334_DATA 0x00000000
+#define DDRSS_PI_335_DATA 0x66000000
+#define DDRSS_PI_336_DATA 0x00150F27
+#define DDRSS_PI_337_DATA 0x00000000
+#define DDRSS_PI_338_DATA 0x00000024
+#define DDRSS_PI_339_DATA 0x00000012
+#define DDRSS_PI_340_DATA 0x00000031
+#define DDRSS_PI_341_DATA 0x00000000
+#define DDRSS_PI_342_DATA 0x00000000
+#define DDRSS_PI_343_DATA 0x66000000
+#define DDRSS_PI_344_DATA 0x00150F27
+#define DDRSS_PHY_0_DATA 0x04F00000
+#define DDRSS_PHY_1_DATA 0x00000000
+#define DDRSS_PHY_2_DATA 0x00030200
+#define DDRSS_PHY_3_DATA 0x00000000
+#define DDRSS_PHY_4_DATA 0x00000000
+#define DDRSS_PHY_5_DATA 0x01000000
+#define DDRSS_PHY_6_DATA 0x03000400
+#define DDRSS_PHY_7_DATA 0x00000001
+#define DDRSS_PHY_8_DATA 0x00000001
+#define DDRSS_PHY_9_DATA 0x00000000
+#define DDRSS_PHY_10_DATA 0x00000000
+#define DDRSS_PHY_11_DATA 0x01010000
+#define DDRSS_PHY_12_DATA 0x00010000
+#define DDRSS_PHY_13_DATA 0x00C00001
+#define DDRSS_PHY_14_DATA 0x00CC0008
+#define DDRSS_PHY_15_DATA 0x00660601
+#define DDRSS_PHY_16_DATA 0x00000003
+#define DDRSS_PHY_17_DATA 0x00000000
+#define DDRSS_PHY_18_DATA 0x00000000
+#define DDRSS_PHY_19_DATA 0x0000AAAA
+#define DDRSS_PHY_20_DATA 0x00005555
+#define DDRSS_PHY_21_DATA 0x0000B5B5
+#define DDRSS_PHY_22_DATA 0x00004A4A
+#define DDRSS_PHY_23_DATA 0x00005656
+#define DDRSS_PHY_24_DATA 0x0000A9A9
+#define DDRSS_PHY_25_DATA 0x0000B7B7
+#define DDRSS_PHY_26_DATA 0x00004848
+#define DDRSS_PHY_27_DATA 0x00000000
+#define DDRSS_PHY_28_DATA 0x00000000
+#define DDRSS_PHY_29_DATA 0x08000000
+#define DDRSS_PHY_30_DATA 0x0F000008
+#define DDRSS_PHY_31_DATA 0x00000F0F
+#define DDRSS_PHY_32_DATA 0x00E4E400
+#define DDRSS_PHY_33_DATA 0x00071020
+#define DDRSS_PHY_34_DATA 0x000C0020
+#define DDRSS_PHY_35_DATA 0x00062000
+#define DDRSS_PHY_36_DATA 0x00000000
+#define DDRSS_PHY_37_DATA 0x55555555
+#define DDRSS_PHY_38_DATA 0xAAAAAAAA
+#define DDRSS_PHY_39_DATA 0x55555555
+#define DDRSS_PHY_40_DATA 0xAAAAAAAA
+#define DDRSS_PHY_41_DATA 0x00005555
+#define DDRSS_PHY_42_DATA 0x01000100
+#define DDRSS_PHY_43_DATA 0x00800180
+#define DDRSS_PHY_44_DATA 0x00000001
+#define DDRSS_PHY_45_DATA 0x00000000
+#define DDRSS_PHY_46_DATA 0x00000000
+#define DDRSS_PHY_47_DATA 0x00000000
+#define DDRSS_PHY_48_DATA 0x00000000
+#define DDRSS_PHY_49_DATA 0x00000000
+#define DDRSS_PHY_50_DATA 0x00000000
+#define DDRSS_PHY_51_DATA 0x00000000
+#define DDRSS_PHY_52_DATA 0x00000000
+#define DDRSS_PHY_53_DATA 0x00000000
+#define DDRSS_PHY_54_DATA 0x00000000
+#define DDRSS_PHY_55_DATA 0x00000000
+#define DDRSS_PHY_56_DATA 0x00000000
+#define DDRSS_PHY_57_DATA 0x00000000
+#define DDRSS_PHY_58_DATA 0x00000000
+#define DDRSS_PHY_59_DATA 0x00000000
+#define DDRSS_PHY_60_DATA 0x00000000
+#define DDRSS_PHY_61_DATA 0x00000000
+#define DDRSS_PHY_62_DATA 0x00000000
+#define DDRSS_PHY_63_DATA 0x00000000
+#define DDRSS_PHY_64_DATA 0x00000000
+#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_66_DATA 0x00000000
+#define DDRSS_PHY_67_DATA 0x00000000
+#define DDRSS_PHY_68_DATA 0x00000000
+#define DDRSS_PHY_69_DATA 0x00000000
+#define DDRSS_PHY_70_DATA 0x00000000
+#define DDRSS_PHY_71_DATA 0x00000000
+#define DDRSS_PHY_72_DATA 0x041F07FF
+#define DDRSS_PHY_73_DATA 0x00000000
+#define DDRSS_PHY_74_DATA 0x01CC0B01
+#define DDRSS_PHY_75_DATA 0x1003CC0B
+#define DDRSS_PHY_76_DATA 0x20000140
+#define DDRSS_PHY_77_DATA 0x07FF0200
+#define DDRSS_PHY_78_DATA 0x0000DD01
+#define DDRSS_PHY_79_DATA 0x00100303
+#define DDRSS_PHY_80_DATA 0x00000000
+#define DDRSS_PHY_81_DATA 0x00000000
+#define DDRSS_PHY_82_DATA 0x00021000
+#define DDRSS_PHY_83_DATA 0x00100010
+#define DDRSS_PHY_84_DATA 0x00100010
+#define DDRSS_PHY_85_DATA 0x00100010
+#define DDRSS_PHY_86_DATA 0x00100010
+#define DDRSS_PHY_87_DATA 0x02000010
+#define DDRSS_PHY_88_DATA 0x51516041
+#define DDRSS_PHY_89_DATA 0x31C06000
+#define DDRSS_PHY_90_DATA 0x07AB0340
+#define DDRSS_PHY_91_DATA 0x0100C0C0
+#define DDRSS_PHY_92_DATA 0x03040000
+#define DDRSS_PHY_93_DATA 0x00000403
+#define DDRSS_PHY_94_DATA 0x42100010
+#define DDRSS_PHY_95_DATA 0x010C053E
+#define DDRSS_PHY_96_DATA 0x000F0C1A
+#define DDRSS_PHY_97_DATA 0x01000140
+#define DDRSS_PHY_98_DATA 0x00660120
+#define DDRSS_PHY_99_DATA 0x00000C00
+#define DDRSS_PHY_100_DATA 0x000001AA
+#define DDRSS_PHY_101_DATA 0x20100200
+#define DDRSS_PHY_102_DATA 0x00000004
+#define DDRSS_PHY_103_DATA 0x76543210
+#define DDRSS_PHY_104_DATA 0x00000008
+#define DDRSS_PHY_105_DATA 0x032A032A
+#define DDRSS_PHY_106_DATA 0x032A032A
+#define DDRSS_PHY_107_DATA 0x032A032A
+#define DDRSS_PHY_108_DATA 0x032A032A
+#define DDRSS_PHY_109_DATA 0x0000032A
+#define DDRSS_PHY_110_DATA 0x00008000
+#define DDRSS_PHY_111_DATA 0x00800080
+#define DDRSS_PHY_112_DATA 0x00800080
+#define DDRSS_PHY_113_DATA 0x00800080
+#define DDRSS_PHY_114_DATA 0x00800080
+#define DDRSS_PHY_115_DATA 0x00800080
+#define DDRSS_PHY_116_DATA 0x00800080
+#define DDRSS_PHY_117_DATA 0x00800080
+#define DDRSS_PHY_118_DATA 0x00800080
+#define DDRSS_PHY_119_DATA 0x01190080
+#define DDRSS_PHY_120_DATA 0x01A00001
+#define DDRSS_PHY_121_DATA 0x00000000
+#define DDRSS_PHY_122_DATA 0x00000000
+#define DDRSS_PHY_123_DATA 0x00080200
+#define DDRSS_PHY_124_DATA 0x00000000
+#define DDRSS_PHY_125_DATA 0x0000F0F0
+#define DDRSS_PHY_126_DATA 0x00000000
+#define DDRSS_PHY_127_DATA 0x00000000
+#define DDRSS_PHY_128_DATA 0x00000000
+#define DDRSS_PHY_129_DATA 0x00000000
+#define DDRSS_PHY_130_DATA 0x00000000
+#define DDRSS_PHY_131_DATA 0x00000000
+#define DDRSS_PHY_132_DATA 0x00000000
+#define DDRSS_PHY_133_DATA 0x00000000
+#define DDRSS_PHY_134_DATA 0x00000000
+#define DDRSS_PHY_135_DATA 0x00000000
+#define DDRSS_PHY_136_DATA 0x00000000
+#define DDRSS_PHY_137_DATA 0x00000000
+#define DDRSS_PHY_138_DATA 0x00000000
+#define DDRSS_PHY_139_DATA 0x00000000
+#define DDRSS_PHY_140_DATA 0x00000000
+#define DDRSS_PHY_141_DATA 0x00000000
+#define DDRSS_PHY_142_DATA 0x00000000
+#define DDRSS_PHY_143_DATA 0x00000000
+#define DDRSS_PHY_144_DATA 0x00000000
+#define DDRSS_PHY_145_DATA 0x00000000
+#define DDRSS_PHY_146_DATA 0x00000000
+#define DDRSS_PHY_147_DATA 0x00000000
+#define DDRSS_PHY_148_DATA 0x00000000
+#define DDRSS_PHY_149_DATA 0x00000000
+#define DDRSS_PHY_150_DATA 0x00000000
+#define DDRSS_PHY_151_DATA 0x00000000
+#define DDRSS_PHY_152_DATA 0x00000000
+#define DDRSS_PHY_153_DATA 0x00000000
+#define DDRSS_PHY_154_DATA 0x00000000
+#define DDRSS_PHY_155_DATA 0x00000000
+#define DDRSS_PHY_156_DATA 0x00000000
+#define DDRSS_PHY_157_DATA 0x00000000
+#define DDRSS_PHY_158_DATA 0x00000000
+#define DDRSS_PHY_159_DATA 0x00000000
+#define DDRSS_PHY_160_DATA 0x00000000
+#define DDRSS_PHY_161_DATA 0x00000000
+#define DDRSS_PHY_162_DATA 0x00000000
+#define DDRSS_PHY_163_DATA 0x00000000
+#define DDRSS_PHY_164_DATA 0x00000000
+#define DDRSS_PHY_165_DATA 0x00000000
+#define DDRSS_PHY_166_DATA 0x00000000
+#define DDRSS_PHY_167_DATA 0x00000000
+#define DDRSS_PHY_168_DATA 0x00000000
+#define DDRSS_PHY_169_DATA 0x00000000
+#define DDRSS_PHY_170_DATA 0x00000000
+#define DDRSS_PHY_171_DATA 0x00000000
+#define DDRSS_PHY_172_DATA 0x00000000
+#define DDRSS_PHY_173_DATA 0x00000000
+#define DDRSS_PHY_174_DATA 0x00000000
+#define DDRSS_PHY_175_DATA 0x00000000
+#define DDRSS_PHY_176_DATA 0x00000000
+#define DDRSS_PHY_177_DATA 0x00000000
+#define DDRSS_PHY_178_DATA 0x00000000
+#define DDRSS_PHY_179_DATA 0x00000000
+#define DDRSS_PHY_180_DATA 0x00000000
+#define DDRSS_PHY_181_DATA 0x00000000
+#define DDRSS_PHY_182_DATA 0x00000000
+#define DDRSS_PHY_183_DATA 0x00000000
+#define DDRSS_PHY_184_DATA 0x00000000
+#define DDRSS_PHY_185_DATA 0x00000000
+#define DDRSS_PHY_186_DATA 0x00000000
+#define DDRSS_PHY_187_DATA 0x00000000
+#define DDRSS_PHY_188_DATA 0x00000000
+#define DDRSS_PHY_189_DATA 0x00000000
+#define DDRSS_PHY_190_DATA 0x00000000
+#define DDRSS_PHY_191_DATA 0x00000000
+#define DDRSS_PHY_192_DATA 0x00000000
+#define DDRSS_PHY_193_DATA 0x00000000
+#define DDRSS_PHY_194_DATA 0x00000000
+#define DDRSS_PHY_195_DATA 0x00000000
+#define DDRSS_PHY_196_DATA 0x00000000
+#define DDRSS_PHY_197_DATA 0x00000000
+#define DDRSS_PHY_198_DATA 0x00000000
+#define DDRSS_PHY_199_DATA 0x00000000
+#define DDRSS_PHY_200_DATA 0x00000000
+#define DDRSS_PHY_201_DATA 0x00000000
+#define DDRSS_PHY_202_DATA 0x00000000
+#define DDRSS_PHY_203_DATA 0x00000000
+#define DDRSS_PHY_204_DATA 0x00000000
+#define DDRSS_PHY_205_DATA 0x00000000
+#define DDRSS_PHY_206_DATA 0x00000000
+#define DDRSS_PHY_207_DATA 0x00000000
+#define DDRSS_PHY_208_DATA 0x00000000
+#define DDRSS_PHY_209_DATA 0x00000000
+#define DDRSS_PHY_210_DATA 0x00000000
+#define DDRSS_PHY_211_DATA 0x00000000
+#define DDRSS_PHY_212_DATA 0x00000000
+#define DDRSS_PHY_213_DATA 0x00000000
+#define DDRSS_PHY_214_DATA 0x00000000
+#define DDRSS_PHY_215_DATA 0x00000000
+#define DDRSS_PHY_216_DATA 0x00000000
+#define DDRSS_PHY_217_DATA 0x00000000
+#define DDRSS_PHY_218_DATA 0x00000000
+#define DDRSS_PHY_219_DATA 0x00000000
+#define DDRSS_PHY_220_DATA 0x00000000
+#define DDRSS_PHY_221_DATA 0x00000000
+#define DDRSS_PHY_222_DATA 0x00000000
+#define DDRSS_PHY_223_DATA 0x00000000
+#define DDRSS_PHY_224_DATA 0x00000000
+#define DDRSS_PHY_225_DATA 0x00000000
+#define DDRSS_PHY_226_DATA 0x00000000
+#define DDRSS_PHY_227_DATA 0x00000000
+#define DDRSS_PHY_228_DATA 0x00000000
+#define DDRSS_PHY_229_DATA 0x00000000
+#define DDRSS_PHY_230_DATA 0x00000000
+#define DDRSS_PHY_231_DATA 0x00000000
+#define DDRSS_PHY_232_DATA 0x00000000
+#define DDRSS_PHY_233_DATA 0x00000000
+#define DDRSS_PHY_234_DATA 0x00000000
+#define DDRSS_PHY_235_DATA 0x00000000
+#define DDRSS_PHY_236_DATA 0x00000000
+#define DDRSS_PHY_237_DATA 0x00000000
+#define DDRSS_PHY_238_DATA 0x00000000
+#define DDRSS_PHY_239_DATA 0x00000000
+#define DDRSS_PHY_240_DATA 0x00000000
+#define DDRSS_PHY_241_DATA 0x00000000
+#define DDRSS_PHY_242_DATA 0x00000000
+#define DDRSS_PHY_243_DATA 0x00000000
+#define DDRSS_PHY_244_DATA 0x00000000
+#define DDRSS_PHY_245_DATA 0x00000000
+#define DDRSS_PHY_246_DATA 0x00000000
+#define DDRSS_PHY_247_DATA 0x00000000
+#define DDRSS_PHY_248_DATA 0x00000000
+#define DDRSS_PHY_249_DATA 0x00000000
+#define DDRSS_PHY_250_DATA 0x00000000
+#define DDRSS_PHY_251_DATA 0x00000000
+#define DDRSS_PHY_252_DATA 0x00000000
+#define DDRSS_PHY_253_DATA 0x00000000
+#define DDRSS_PHY_254_DATA 0x00000000
+#define DDRSS_PHY_255_DATA 0x00000000
+#define DDRSS_PHY_256_DATA 0x04F00000
+#define DDRSS_PHY_257_DATA 0x00000000
+#define DDRSS_PHY_258_DATA 0x00030200
+#define DDRSS_PHY_259_DATA 0x00000000
+#define DDRSS_PHY_260_DATA 0x00000000
+#define DDRSS_PHY_261_DATA 0x01000000
+#define DDRSS_PHY_262_DATA 0x03000400
+#define DDRSS_PHY_263_DATA 0x00000001
+#define DDRSS_PHY_264_DATA 0x00000001
+#define DDRSS_PHY_265_DATA 0x00000000
+#define DDRSS_PHY_266_DATA 0x00000000
+#define DDRSS_PHY_267_DATA 0x01010000
+#define DDRSS_PHY_268_DATA 0x00010000
+#define DDRSS_PHY_269_DATA 0x00C00001
+#define DDRSS_PHY_270_DATA 0x00CC0008
+#define DDRSS_PHY_271_DATA 0x00660601
+#define DDRSS_PHY_272_DATA 0x00000003
+#define DDRSS_PHY_273_DATA 0x00000000
+#define DDRSS_PHY_274_DATA 0x00000000
+#define DDRSS_PHY_275_DATA 0x0000AAAA
+#define DDRSS_PHY_276_DATA 0x00005555
+#define DDRSS_PHY_277_DATA 0x0000B5B5
+#define DDRSS_PHY_278_DATA 0x00004A4A
+#define DDRSS_PHY_279_DATA 0x00005656
+#define DDRSS_PHY_280_DATA 0x0000A9A9
+#define DDRSS_PHY_281_DATA 0x0000B7B7
+#define DDRSS_PHY_282_DATA 0x00004848
+#define DDRSS_PHY_283_DATA 0x00000000
+#define DDRSS_PHY_284_DATA 0x00000000
+#define DDRSS_PHY_285_DATA 0x08000000
+#define DDRSS_PHY_286_DATA 0x0F000008
+#define DDRSS_PHY_287_DATA 0x00000F0F
+#define DDRSS_PHY_288_DATA 0x00E4E400
+#define DDRSS_PHY_289_DATA 0x00071020
+#define DDRSS_PHY_290_DATA 0x000C0020
+#define DDRSS_PHY_291_DATA 0x00062000
+#define DDRSS_PHY_292_DATA 0x00000000
+#define DDRSS_PHY_293_DATA 0x55555555
+#define DDRSS_PHY_294_DATA 0xAAAAAAAA
+#define DDRSS_PHY_295_DATA 0x55555555
+#define DDRSS_PHY_296_DATA 0xAAAAAAAA
+#define DDRSS_PHY_297_DATA 0x00005555
+#define DDRSS_PHY_298_DATA 0x01000100
+#define DDRSS_PHY_299_DATA 0x00800180
+#define DDRSS_PHY_300_DATA 0x00000000
+#define DDRSS_PHY_301_DATA 0x00000000
+#define DDRSS_PHY_302_DATA 0x00000000
+#define DDRSS_PHY_303_DATA 0x00000000
+#define DDRSS_PHY_304_DATA 0x00000000
+#define DDRSS_PHY_305_DATA 0x00000000
+#define DDRSS_PHY_306_DATA 0x00000000
+#define DDRSS_PHY_307_DATA 0x00000000
+#define DDRSS_PHY_308_DATA 0x00000000
+#define DDRSS_PHY_309_DATA 0x00000000
+#define DDRSS_PHY_310_DATA 0x00000000
+#define DDRSS_PHY_311_DATA 0x00000000
+#define DDRSS_PHY_312_DATA 0x00000000
+#define DDRSS_PHY_313_DATA 0x00000000
+#define DDRSS_PHY_314_DATA 0x00000000
+#define DDRSS_PHY_315_DATA 0x00000000
+#define DDRSS_PHY_316_DATA 0x00000000
+#define DDRSS_PHY_317_DATA 0x00000000
+#define DDRSS_PHY_318_DATA 0x00000000
+#define DDRSS_PHY_319_DATA 0x00000000
+#define DDRSS_PHY_320_DATA 0x00000000
+#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_322_DATA 0x00000000
+#define DDRSS_PHY_323_DATA 0x00000000
+#define DDRSS_PHY_324_DATA 0x00000000
+#define DDRSS_PHY_325_DATA 0x00000000
+#define DDRSS_PHY_326_DATA 0x00000000
+#define DDRSS_PHY_327_DATA 0x00000000
+#define DDRSS_PHY_328_DATA 0x041F07FF
+#define DDRSS_PHY_329_DATA 0x00000000
+#define DDRSS_PHY_330_DATA 0x01CC0B01
+#define DDRSS_PHY_331_DATA 0x1003CC0B
+#define DDRSS_PHY_332_DATA 0x20000140
+#define DDRSS_PHY_333_DATA 0x07FF0200
+#define DDRSS_PHY_334_DATA 0x0000DD01
+#define DDRSS_PHY_335_DATA 0x00100303
+#define DDRSS_PHY_336_DATA 0x00000000
+#define DDRSS_PHY_337_DATA 0x00000000
+#define DDRSS_PHY_338_DATA 0x00021000
+#define DDRSS_PHY_339_DATA 0x00100010
+#define DDRSS_PHY_340_DATA 0x00100010
+#define DDRSS_PHY_341_DATA 0x00100010
+#define DDRSS_PHY_342_DATA 0x00100010
+#define DDRSS_PHY_343_DATA 0x02000010
+#define DDRSS_PHY_344_DATA 0x51516041
+#define DDRSS_PHY_345_DATA 0x31C06000
+#define DDRSS_PHY_346_DATA 0x07AB0340
+#define DDRSS_PHY_347_DATA 0x0100C0C0
+#define DDRSS_PHY_348_DATA 0x03040000
+#define DDRSS_PHY_349_DATA 0x00000403
+#define DDRSS_PHY_350_DATA 0x42100010
+#define DDRSS_PHY_351_DATA 0x010C053E
+#define DDRSS_PHY_352_DATA 0x000F0C1A
+#define DDRSS_PHY_353_DATA 0x01000140
+#define DDRSS_PHY_354_DATA 0x00660120
+#define DDRSS_PHY_355_DATA 0x00000C00
+#define DDRSS_PHY_356_DATA 0x000001AA
+#define DDRSS_PHY_357_DATA 0x20100200
+#define DDRSS_PHY_358_DATA 0x00000004
+#define DDRSS_PHY_359_DATA 0x76543210
+#define DDRSS_PHY_360_DATA 0x00000008
+#define DDRSS_PHY_361_DATA 0x032A032A
+#define DDRSS_PHY_362_DATA 0x032A032A
+#define DDRSS_PHY_363_DATA 0x032A032A
+#define DDRSS_PHY_364_DATA 0x032A032A
+#define DDRSS_PHY_365_DATA 0x0000032A
+#define DDRSS_PHY_366_DATA 0x00008000
+#define DDRSS_PHY_367_DATA 0x00800080
+#define DDRSS_PHY_368_DATA 0x00800080
+#define DDRSS_PHY_369_DATA 0x00800080
+#define DDRSS_PHY_370_DATA 0x00800080
+#define DDRSS_PHY_371_DATA 0x00800080
+#define DDRSS_PHY_372_DATA 0x00800080
+#define DDRSS_PHY_373_DATA 0x00800080
+#define DDRSS_PHY_374_DATA 0x00800080
+#define DDRSS_PHY_375_DATA 0x01190080
+#define DDRSS_PHY_376_DATA 0x01A00001
+#define DDRSS_PHY_377_DATA 0x00000000
+#define DDRSS_PHY_378_DATA 0x00000000
+#define DDRSS_PHY_379_DATA 0x00080200
+#define DDRSS_PHY_380_DATA 0x00000000
+#define DDRSS_PHY_381_DATA 0x0000F0F0
+#define DDRSS_PHY_382_DATA 0x00000000
+#define DDRSS_PHY_383_DATA 0x00000000
+#define DDRSS_PHY_384_DATA 0x00000000
+#define DDRSS_PHY_385_DATA 0x00000000
+#define DDRSS_PHY_386_DATA 0x00000000
+#define DDRSS_PHY_387_DATA 0x00000000
+#define DDRSS_PHY_388_DATA 0x00000000
+#define DDRSS_PHY_389_DATA 0x00000000
+#define DDRSS_PHY_390_DATA 0x00000000
+#define DDRSS_PHY_391_DATA 0x00000000
+#define DDRSS_PHY_392_DATA 0x00000000
+#define DDRSS_PHY_393_DATA 0x00000000
+#define DDRSS_PHY_394_DATA 0x00000000
+#define DDRSS_PHY_395_DATA 0x00000000
+#define DDRSS_PHY_396_DATA 0x00000000
+#define DDRSS_PHY_397_DATA 0x00000000
+#define DDRSS_PHY_398_DATA 0x00000000
+#define DDRSS_PHY_399_DATA 0x00000000
+#define DDRSS_PHY_400_DATA 0x00000000
+#define DDRSS_PHY_401_DATA 0x00000000
+#define DDRSS_PHY_402_DATA 0x00000000
+#define DDRSS_PHY_403_DATA 0x00000000
+#define DDRSS_PHY_404_DATA 0x00000000
+#define DDRSS_PHY_405_DATA 0x00000000
+#define DDRSS_PHY_406_DATA 0x00000000
+#define DDRSS_PHY_407_DATA 0x00000000
+#define DDRSS_PHY_408_DATA 0x00000000
+#define DDRSS_PHY_409_DATA 0x00000000
+#define DDRSS_PHY_410_DATA 0x00000000
+#define DDRSS_PHY_411_DATA 0x00000000
+#define DDRSS_PHY_412_DATA 0x00000000
+#define DDRSS_PHY_413_DATA 0x00000000
+#define DDRSS_PHY_414_DATA 0x00000000
+#define DDRSS_PHY_415_DATA 0x00000000
+#define DDRSS_PHY_416_DATA 0x00000000
+#define DDRSS_PHY_417_DATA 0x00000000
+#define DDRSS_PHY_418_DATA 0x00000000
+#define DDRSS_PHY_419_DATA 0x00000000
+#define DDRSS_PHY_420_DATA 0x00000000
+#define DDRSS_PHY_421_DATA 0x00000000
+#define DDRSS_PHY_422_DATA 0x00000000
+#define DDRSS_PHY_423_DATA 0x00000000
+#define DDRSS_PHY_424_DATA 0x00000000
+#define DDRSS_PHY_425_DATA 0x00000000
+#define DDRSS_PHY_426_DATA 0x00000000
+#define DDRSS_PHY_427_DATA 0x00000000
+#define DDRSS_PHY_428_DATA 0x00000000
+#define DDRSS_PHY_429_DATA 0x00000000
+#define DDRSS_PHY_430_DATA 0x00000000
+#define DDRSS_PHY_431_DATA 0x00000000
+#define DDRSS_PHY_432_DATA 0x00000000
+#define DDRSS_PHY_433_DATA 0x00000000
+#define DDRSS_PHY_434_DATA 0x00000000
+#define DDRSS_PHY_435_DATA 0x00000000
+#define DDRSS_PHY_436_DATA 0x00000000
+#define DDRSS_PHY_437_DATA 0x00000000
+#define DDRSS_PHY_438_DATA 0x00000000
+#define DDRSS_PHY_439_DATA 0x00000000
+#define DDRSS_PHY_440_DATA 0x00000000
+#define DDRSS_PHY_441_DATA 0x00000000
+#define DDRSS_PHY_442_DATA 0x00000000
+#define DDRSS_PHY_443_DATA 0x00000000
+#define DDRSS_PHY_444_DATA 0x00000000
+#define DDRSS_PHY_445_DATA 0x00000000
+#define DDRSS_PHY_446_DATA 0x00000000
+#define DDRSS_PHY_447_DATA 0x00000000
+#define DDRSS_PHY_448_DATA 0x00000000
+#define DDRSS_PHY_449_DATA 0x00000000
+#define DDRSS_PHY_450_DATA 0x00000000
+#define DDRSS_PHY_451_DATA 0x00000000
+#define DDRSS_PHY_452_DATA 0x00000000
+#define DDRSS_PHY_453_DATA 0x00000000
+#define DDRSS_PHY_454_DATA 0x00000000
+#define DDRSS_PHY_455_DATA 0x00000000
+#define DDRSS_PHY_456_DATA 0x00000000
+#define DDRSS_PHY_457_DATA 0x00000000
+#define DDRSS_PHY_458_DATA 0x00000000
+#define DDRSS_PHY_459_DATA 0x00000000
+#define DDRSS_PHY_460_DATA 0x00000000
+#define DDRSS_PHY_461_DATA 0x00000000
+#define DDRSS_PHY_462_DATA 0x00000000
+#define DDRSS_PHY_463_DATA 0x00000000
+#define DDRSS_PHY_464_DATA 0x00000000
+#define DDRSS_PHY_465_DATA 0x00000000
+#define DDRSS_PHY_466_DATA 0x00000000
+#define DDRSS_PHY_467_DATA 0x00000000
+#define DDRSS_PHY_468_DATA 0x00000000
+#define DDRSS_PHY_469_DATA 0x00000000
+#define DDRSS_PHY_470_DATA 0x00000000
+#define DDRSS_PHY_471_DATA 0x00000000
+#define DDRSS_PHY_472_DATA 0x00000000
+#define DDRSS_PHY_473_DATA 0x00000000
+#define DDRSS_PHY_474_DATA 0x00000000
+#define DDRSS_PHY_475_DATA 0x00000000
+#define DDRSS_PHY_476_DATA 0x00000000
+#define DDRSS_PHY_477_DATA 0x00000000
+#define DDRSS_PHY_478_DATA 0x00000000
+#define DDRSS_PHY_479_DATA 0x00000000
+#define DDRSS_PHY_480_DATA 0x00000000
+#define DDRSS_PHY_481_DATA 0x00000000
+#define DDRSS_PHY_482_DATA 0x00000000
+#define DDRSS_PHY_483_DATA 0x00000000
+#define DDRSS_PHY_484_DATA 0x00000000
+#define DDRSS_PHY_485_DATA 0x00000000
+#define DDRSS_PHY_486_DATA 0x00000000
+#define DDRSS_PHY_487_DATA 0x00000000
+#define DDRSS_PHY_488_DATA 0x00000000
+#define DDRSS_PHY_489_DATA 0x00000000
+#define DDRSS_PHY_490_DATA 0x00000000
+#define DDRSS_PHY_491_DATA 0x00000000
+#define DDRSS_PHY_492_DATA 0x00000000
+#define DDRSS_PHY_493_DATA 0x00000000
+#define DDRSS_PHY_494_DATA 0x00000000
+#define DDRSS_PHY_495_DATA 0x00000000
+#define DDRSS_PHY_496_DATA 0x00000000
+#define DDRSS_PHY_497_DATA 0x00000000
+#define DDRSS_PHY_498_DATA 0x00000000
+#define DDRSS_PHY_499_DATA 0x00000000
+#define DDRSS_PHY_500_DATA 0x00000000
+#define DDRSS_PHY_501_DATA 0x00000000
+#define DDRSS_PHY_502_DATA 0x00000000
+#define DDRSS_PHY_503_DATA 0x00000000
+#define DDRSS_PHY_504_DATA 0x00000000
+#define DDRSS_PHY_505_DATA 0x00000000
+#define DDRSS_PHY_506_DATA 0x00000000
+#define DDRSS_PHY_507_DATA 0x00000000
+#define DDRSS_PHY_508_DATA 0x00000000
+#define DDRSS_PHY_509_DATA 0x00000000
+#define DDRSS_PHY_510_DATA 0x00000000
+#define DDRSS_PHY_511_DATA 0x00000000
+#define DDRSS_PHY_512_DATA 0x00000000
+#define DDRSS_PHY_513_DATA 0x00000000
+#define DDRSS_PHY_514_DATA 0x00000000
+#define DDRSS_PHY_515_DATA 0x00000000
+#define DDRSS_PHY_516_DATA 0x00000000
+#define DDRSS_PHY_517_DATA 0x00000100
+#define DDRSS_PHY_518_DATA 0x00000200
+#define DDRSS_PHY_519_DATA 0x00000000
+#define DDRSS_PHY_520_DATA 0x00000000
+#define DDRSS_PHY_521_DATA 0x00000000
+#define DDRSS_PHY_522_DATA 0x00000000
+#define DDRSS_PHY_523_DATA 0x00400000
+#define DDRSS_PHY_524_DATA 0x00000080
+#define DDRSS_PHY_525_DATA 0x00DCBA98
+#define DDRSS_PHY_526_DATA 0x03000000
+#define DDRSS_PHY_527_DATA 0x00200000
+#define DDRSS_PHY_528_DATA 0x00000000
+#define DDRSS_PHY_529_DATA 0x00000000
+#define DDRSS_PHY_530_DATA 0x00000000
+#define DDRSS_PHY_531_DATA 0x00000000
+#define DDRSS_PHY_532_DATA 0x0000002A
+#define DDRSS_PHY_533_DATA 0x00000015
+#define DDRSS_PHY_534_DATA 0x00000015
+#define DDRSS_PHY_535_DATA 0x0000002A
+#define DDRSS_PHY_536_DATA 0x00000033
+#define DDRSS_PHY_537_DATA 0x0000000C
+#define DDRSS_PHY_538_DATA 0x0000000C
+#define DDRSS_PHY_539_DATA 0x00000033
+#define DDRSS_PHY_540_DATA 0x0A418820
+#define DDRSS_PHY_541_DATA 0x003F0000
+#define DDRSS_PHY_542_DATA 0x000F013F
+#define DDRSS_PHY_543_DATA 0x0000000F
+#define DDRSS_PHY_544_DATA 0x000002CC
+#define DDRSS_PHY_545_DATA 0x00030000
+#define DDRSS_PHY_546_DATA 0x00000300
+#define DDRSS_PHY_547_DATA 0x00000300
+#define DDRSS_PHY_548_DATA 0x00000300
+#define DDRSS_PHY_549_DATA 0x00000300
+#define DDRSS_PHY_550_DATA 0x00000300
+#define DDRSS_PHY_551_DATA 0x42080010
+#define DDRSS_PHY_552_DATA 0x0000803E
+#define DDRSS_PHY_553_DATA 0x00000003
+#define DDRSS_PHY_554_DATA 0x00000002
+#define DDRSS_PHY_555_DATA 0x00000000
+#define DDRSS_PHY_556_DATA 0x00000000
+#define DDRSS_PHY_557_DATA 0x00000000
+#define DDRSS_PHY_558_DATA 0x00000000
+#define DDRSS_PHY_559_DATA 0x00000000
+#define DDRSS_PHY_560_DATA 0x00000000
+#define DDRSS_PHY_561_DATA 0x00000000
+#define DDRSS_PHY_562_DATA 0x00000000
+#define DDRSS_PHY_563_DATA 0x00000000
+#define DDRSS_PHY_564_DATA 0x00000000
+#define DDRSS_PHY_565_DATA 0x00000000
+#define DDRSS_PHY_566_DATA 0x00000000
+#define DDRSS_PHY_567_DATA 0x00000000
+#define DDRSS_PHY_568_DATA 0x00000000
+#define DDRSS_PHY_569_DATA 0x00000000
+#define DDRSS_PHY_570_DATA 0x00000000
+#define DDRSS_PHY_571_DATA 0x00000000
+#define DDRSS_PHY_572_DATA 0x00000000
+#define DDRSS_PHY_573_DATA 0x00000000
+#define DDRSS_PHY_574_DATA 0x00000000
+#define DDRSS_PHY_575_DATA 0x00000000
+#define DDRSS_PHY_576_DATA 0x00000000
+#define DDRSS_PHY_577_DATA 0x00000000
+#define DDRSS_PHY_578_DATA 0x00000000
+#define DDRSS_PHY_579_DATA 0x00000000
+#define DDRSS_PHY_580_DATA 0x00000000
+#define DDRSS_PHY_581_DATA 0x00000000
+#define DDRSS_PHY_582_DATA 0x00000000
+#define DDRSS_PHY_583_DATA 0x00000000
+#define DDRSS_PHY_584_DATA 0x00000000
+#define DDRSS_PHY_585_DATA 0x00000000
+#define DDRSS_PHY_586_DATA 0x00000000
+#define DDRSS_PHY_587_DATA 0x00000000
+#define DDRSS_PHY_588_DATA 0x00000000
+#define DDRSS_PHY_589_DATA 0x00000000
+#define DDRSS_PHY_590_DATA 0x00000000
+#define DDRSS_PHY_591_DATA 0x00000000
+#define DDRSS_PHY_592_DATA 0x00000000
+#define DDRSS_PHY_593_DATA 0x00000000
+#define DDRSS_PHY_594_DATA 0x00000000
+#define DDRSS_PHY_595_DATA 0x00000000
+#define DDRSS_PHY_596_DATA 0x00000000
+#define DDRSS_PHY_597_DATA 0x00000000
+#define DDRSS_PHY_598_DATA 0x00000000
+#define DDRSS_PHY_599_DATA 0x00000000
+#define DDRSS_PHY_600_DATA 0x00000000
+#define DDRSS_PHY_601_DATA 0x00000000
+#define DDRSS_PHY_602_DATA 0x00000000
+#define DDRSS_PHY_603_DATA 0x00000000
+#define DDRSS_PHY_604_DATA 0x00000000
+#define DDRSS_PHY_605_DATA 0x00000000
+#define DDRSS_PHY_606_DATA 0x00000000
+#define DDRSS_PHY_607_DATA 0x00000000
+#define DDRSS_PHY_608_DATA 0x00000000
+#define DDRSS_PHY_609_DATA 0x00000000
+#define DDRSS_PHY_610_DATA 0x00000000
+#define DDRSS_PHY_611_DATA 0x00000000
+#define DDRSS_PHY_612_DATA 0x00000000
+#define DDRSS_PHY_613_DATA 0x00000000
+#define DDRSS_PHY_614_DATA 0x00000000
+#define DDRSS_PHY_615_DATA 0x00000000
+#define DDRSS_PHY_616_DATA 0x00000000
+#define DDRSS_PHY_617_DATA 0x00000000
+#define DDRSS_PHY_618_DATA 0x00000000
+#define DDRSS_PHY_619_DATA 0x00000000
+#define DDRSS_PHY_620_DATA 0x00000000
+#define DDRSS_PHY_621_DATA 0x00000000
+#define DDRSS_PHY_622_DATA 0x00000000
+#define DDRSS_PHY_623_DATA 0x00000000
+#define DDRSS_PHY_624_DATA 0x00000000
+#define DDRSS_PHY_625_DATA 0x00000000
+#define DDRSS_PHY_626_DATA 0x00000000
+#define DDRSS_PHY_627_DATA 0x00000000
+#define DDRSS_PHY_628_DATA 0x00000000
+#define DDRSS_PHY_629_DATA 0x00000000
+#define DDRSS_PHY_630_DATA 0x00000000
+#define DDRSS_PHY_631_DATA 0x00000000
+#define DDRSS_PHY_632_DATA 0x00000000
+#define DDRSS_PHY_633_DATA 0x00000000
+#define DDRSS_PHY_634_DATA 0x00000000
+#define DDRSS_PHY_635_DATA 0x00000000
+#define DDRSS_PHY_636_DATA 0x00000000
+#define DDRSS_PHY_637_DATA 0x00000000
+#define DDRSS_PHY_638_DATA 0x00000000
+#define DDRSS_PHY_639_DATA 0x00000000
+#define DDRSS_PHY_640_DATA 0x00000000
+#define DDRSS_PHY_641_DATA 0x00000000
+#define DDRSS_PHY_642_DATA 0x00000000
+#define DDRSS_PHY_643_DATA 0x00000000
+#define DDRSS_PHY_644_DATA 0x00000000
+#define DDRSS_PHY_645_DATA 0x00000000
+#define DDRSS_PHY_646_DATA 0x00000000
+#define DDRSS_PHY_647_DATA 0x00000000
+#define DDRSS_PHY_648_DATA 0x00000000
+#define DDRSS_PHY_649_DATA 0x00000000
+#define DDRSS_PHY_650_DATA 0x00000000
+#define DDRSS_PHY_651_DATA 0x00000000
+#define DDRSS_PHY_652_DATA 0x00000000
+#define DDRSS_PHY_653_DATA 0x00000000
+#define DDRSS_PHY_654_DATA 0x00000000
+#define DDRSS_PHY_655_DATA 0x00000000
+#define DDRSS_PHY_656_DATA 0x00000000
+#define DDRSS_PHY_657_DATA 0x00000000
+#define DDRSS_PHY_658_DATA 0x00000000
+#define DDRSS_PHY_659_DATA 0x00000000
+#define DDRSS_PHY_660_DATA 0x00000000
+#define DDRSS_PHY_661_DATA 0x00000000
+#define DDRSS_PHY_662_DATA 0x00000000
+#define DDRSS_PHY_663_DATA 0x00000000
+#define DDRSS_PHY_664_DATA 0x00000000
+#define DDRSS_PHY_665_DATA 0x00000000
+#define DDRSS_PHY_666_DATA 0x00000000
+#define DDRSS_PHY_667_DATA 0x00000000
+#define DDRSS_PHY_668_DATA 0x00000000
+#define DDRSS_PHY_669_DATA 0x00000000
+#define DDRSS_PHY_670_DATA 0x00000000
+#define DDRSS_PHY_671_DATA 0x00000000
+#define DDRSS_PHY_672_DATA 0x00000000
+#define DDRSS_PHY_673_DATA 0x00000000
+#define DDRSS_PHY_674_DATA 0x00000000
+#define DDRSS_PHY_675_DATA 0x00000000
+#define DDRSS_PHY_676_DATA 0x00000000
+#define DDRSS_PHY_677_DATA 0x00000000
+#define DDRSS_PHY_678_DATA 0x00000000
+#define DDRSS_PHY_679_DATA 0x00000000
+#define DDRSS_PHY_680_DATA 0x00000000
+#define DDRSS_PHY_681_DATA 0x00000000
+#define DDRSS_PHY_682_DATA 0x00000000
+#define DDRSS_PHY_683_DATA 0x00000000
+#define DDRSS_PHY_684_DATA 0x00000000
+#define DDRSS_PHY_685_DATA 0x00000000
+#define DDRSS_PHY_686_DATA 0x00000000
+#define DDRSS_PHY_687_DATA 0x00000000
+#define DDRSS_PHY_688_DATA 0x00000000
+#define DDRSS_PHY_689_DATA 0x00000000
+#define DDRSS_PHY_690_DATA 0x00000000
+#define DDRSS_PHY_691_DATA 0x00000000
+#define DDRSS_PHY_692_DATA 0x00000000
+#define DDRSS_PHY_693_DATA 0x00000000
+#define DDRSS_PHY_694_DATA 0x00000000
+#define DDRSS_PHY_695_DATA 0x00000000
+#define DDRSS_PHY_696_DATA 0x00000000
+#define DDRSS_PHY_697_DATA 0x00000000
+#define DDRSS_PHY_698_DATA 0x00000000
+#define DDRSS_PHY_699_DATA 0x00000000
+#define DDRSS_PHY_700_DATA 0x00000000
+#define DDRSS_PHY_701_DATA 0x00000000
+#define DDRSS_PHY_702_DATA 0x00000000
+#define DDRSS_PHY_703_DATA 0x00000000
+#define DDRSS_PHY_704_DATA 0x00000000
+#define DDRSS_PHY_705_DATA 0x00000000
+#define DDRSS_PHY_706_DATA 0x00000000
+#define DDRSS_PHY_707_DATA 0x00000000
+#define DDRSS_PHY_708_DATA 0x00000000
+#define DDRSS_PHY_709_DATA 0x00000000
+#define DDRSS_PHY_710_DATA 0x00000000
+#define DDRSS_PHY_711_DATA 0x00000000
+#define DDRSS_PHY_712_DATA 0x00000000
+#define DDRSS_PHY_713_DATA 0x00000000
+#define DDRSS_PHY_714_DATA 0x00000000
+#define DDRSS_PHY_715_DATA 0x00000000
+#define DDRSS_PHY_716_DATA 0x00000000
+#define DDRSS_PHY_717_DATA 0x00000000
+#define DDRSS_PHY_718_DATA 0x00000000
+#define DDRSS_PHY_719_DATA 0x00000000
+#define DDRSS_PHY_720_DATA 0x00000000
+#define DDRSS_PHY_721_DATA 0x00000000
+#define DDRSS_PHY_722_DATA 0x00000000
+#define DDRSS_PHY_723_DATA 0x00000000
+#define DDRSS_PHY_724_DATA 0x00000000
+#define DDRSS_PHY_725_DATA 0x00000000
+#define DDRSS_PHY_726_DATA 0x00000000
+#define DDRSS_PHY_727_DATA 0x00000000
+#define DDRSS_PHY_728_DATA 0x00000000
+#define DDRSS_PHY_729_DATA 0x00000000
+#define DDRSS_PHY_730_DATA 0x00000000
+#define DDRSS_PHY_731_DATA 0x00000000
+#define DDRSS_PHY_732_DATA 0x00000000
+#define DDRSS_PHY_733_DATA 0x00000000
+#define DDRSS_PHY_734_DATA 0x00000000
+#define DDRSS_PHY_735_DATA 0x00000000
+#define DDRSS_PHY_736_DATA 0x00000000
+#define DDRSS_PHY_737_DATA 0x00000000
+#define DDRSS_PHY_738_DATA 0x00000000
+#define DDRSS_PHY_739_DATA 0x00000000
+#define DDRSS_PHY_740_DATA 0x00000000
+#define DDRSS_PHY_741_DATA 0x00000000
+#define DDRSS_PHY_742_DATA 0x00000000
+#define DDRSS_PHY_743_DATA 0x00000000
+#define DDRSS_PHY_744_DATA 0x00000000
+#define DDRSS_PHY_745_DATA 0x00000000
+#define DDRSS_PHY_746_DATA 0x00000000
+#define DDRSS_PHY_747_DATA 0x00000000
+#define DDRSS_PHY_748_DATA 0x00000000
+#define DDRSS_PHY_749_DATA 0x00000000
+#define DDRSS_PHY_750_DATA 0x00000000
+#define DDRSS_PHY_751_DATA 0x00000000
+#define DDRSS_PHY_752_DATA 0x00000000
+#define DDRSS_PHY_753_DATA 0x00000000
+#define DDRSS_PHY_754_DATA 0x00000000
+#define DDRSS_PHY_755_DATA 0x00000000
+#define DDRSS_PHY_756_DATA 0x00000000
+#define DDRSS_PHY_757_DATA 0x00000000
+#define DDRSS_PHY_758_DATA 0x00000000
+#define DDRSS_PHY_759_DATA 0x00000000
+#define DDRSS_PHY_760_DATA 0x00000000
+#define DDRSS_PHY_761_DATA 0x00000000
+#define DDRSS_PHY_762_DATA 0x00000000
+#define DDRSS_PHY_763_DATA 0x00000000
+#define DDRSS_PHY_764_DATA 0x00000000
+#define DDRSS_PHY_765_DATA 0x00000000
+#define DDRSS_PHY_766_DATA 0x00000000
+#define DDRSS_PHY_767_DATA 0x00000000
+#define DDRSS_PHY_768_DATA 0x00000000
+#define DDRSS_PHY_769_DATA 0x00000000
+#define DDRSS_PHY_770_DATA 0x00000000
+#define DDRSS_PHY_771_DATA 0x00000000
+#define DDRSS_PHY_772_DATA 0x00000000
+#define DDRSS_PHY_773_DATA 0x00000100
+#define DDRSS_PHY_774_DATA 0x00000200
+#define DDRSS_PHY_775_DATA 0x00000000
+#define DDRSS_PHY_776_DATA 0x00000000
+#define DDRSS_PHY_777_DATA 0x00000000
+#define DDRSS_PHY_778_DATA 0x00000000
+#define DDRSS_PHY_779_DATA 0x00400000
+#define DDRSS_PHY_780_DATA 0x00000080
+#define DDRSS_PHY_781_DATA 0x00DCBA98
+#define DDRSS_PHY_782_DATA 0x03000000
+#define DDRSS_PHY_783_DATA 0x00200000
+#define DDRSS_PHY_784_DATA 0x00000000
+#define DDRSS_PHY_785_DATA 0x00000000
+#define DDRSS_PHY_786_DATA 0x00000000
+#define DDRSS_PHY_787_DATA 0x00000000
+#define DDRSS_PHY_788_DATA 0x0000002A
+#define DDRSS_PHY_789_DATA 0x00000015
+#define DDRSS_PHY_790_DATA 0x00000015
+#define DDRSS_PHY_791_DATA 0x0000002A
+#define DDRSS_PHY_792_DATA 0x00000033
+#define DDRSS_PHY_793_DATA 0x0000000C
+#define DDRSS_PHY_794_DATA 0x0000000C
+#define DDRSS_PHY_795_DATA 0x00000033
+#define DDRSS_PHY_796_DATA 0x00000000
+#define DDRSS_PHY_797_DATA 0x00000000
+#define DDRSS_PHY_798_DATA 0x000F0000
+#define DDRSS_PHY_799_DATA 0x0000000F
+#define DDRSS_PHY_800_DATA 0x000002CC
+#define DDRSS_PHY_801_DATA 0x00030000
+#define DDRSS_PHY_802_DATA 0x00000300
+#define DDRSS_PHY_803_DATA 0x00000300
+#define DDRSS_PHY_804_DATA 0x00000300
+#define DDRSS_PHY_805_DATA 0x00000300
+#define DDRSS_PHY_806_DATA 0x00000300
+#define DDRSS_PHY_807_DATA 0x42080010
+#define DDRSS_PHY_808_DATA 0x0000803E
+#define DDRSS_PHY_809_DATA 0x00000003
+#define DDRSS_PHY_810_DATA 0x00000002
+#define DDRSS_PHY_811_DATA 0x00000000
+#define DDRSS_PHY_812_DATA 0x00000000
+#define DDRSS_PHY_813_DATA 0x00000000
+#define DDRSS_PHY_814_DATA 0x00000000
+#define DDRSS_PHY_815_DATA 0x00000000
+#define DDRSS_PHY_816_DATA 0x00000000
+#define DDRSS_PHY_817_DATA 0x00000000
+#define DDRSS_PHY_818_DATA 0x00000000
+#define DDRSS_PHY_819_DATA 0x00000000
+#define DDRSS_PHY_820_DATA 0x00000000
+#define DDRSS_PHY_821_DATA 0x00000000
+#define DDRSS_PHY_822_DATA 0x00000000
+#define DDRSS_PHY_823_DATA 0x00000000
+#define DDRSS_PHY_824_DATA 0x00000000
+#define DDRSS_PHY_825_DATA 0x00000000
+#define DDRSS_PHY_826_DATA 0x00000000
+#define DDRSS_PHY_827_DATA 0x00000000
+#define DDRSS_PHY_828_DATA 0x00000000
+#define DDRSS_PHY_829_DATA 0x00000000
+#define DDRSS_PHY_830_DATA 0x00000000
+#define DDRSS_PHY_831_DATA 0x00000000
+#define DDRSS_PHY_832_DATA 0x00000000
+#define DDRSS_PHY_833_DATA 0x00000000
+#define DDRSS_PHY_834_DATA 0x00000000
+#define DDRSS_PHY_835_DATA 0x00000000
+#define DDRSS_PHY_836_DATA 0x00000000
+#define DDRSS_PHY_837_DATA 0x00000000
+#define DDRSS_PHY_838_DATA 0x00000000
+#define DDRSS_PHY_839_DATA 0x00000000
+#define DDRSS_PHY_840_DATA 0x00000000
+#define DDRSS_PHY_841_DATA 0x00000000
+#define DDRSS_PHY_842_DATA 0x00000000
+#define DDRSS_PHY_843_DATA 0x00000000
+#define DDRSS_PHY_844_DATA 0x00000000
+#define DDRSS_PHY_845_DATA 0x00000000
+#define DDRSS_PHY_846_DATA 0x00000000
+#define DDRSS_PHY_847_DATA 0x00000000
+#define DDRSS_PHY_848_DATA 0x00000000
+#define DDRSS_PHY_849_DATA 0x00000000
+#define DDRSS_PHY_850_DATA 0x00000000
+#define DDRSS_PHY_851_DATA 0x00000000
+#define DDRSS_PHY_852_DATA 0x00000000
+#define DDRSS_PHY_853_DATA 0x00000000
+#define DDRSS_PHY_854_DATA 0x00000000
+#define DDRSS_PHY_855_DATA 0x00000000
+#define DDRSS_PHY_856_DATA 0x00000000
+#define DDRSS_PHY_857_DATA 0x00000000
+#define DDRSS_PHY_858_DATA 0x00000000
+#define DDRSS_PHY_859_DATA 0x00000000
+#define DDRSS_PHY_860_DATA 0x00000000
+#define DDRSS_PHY_861_DATA 0x00000000
+#define DDRSS_PHY_862_DATA 0x00000000
+#define DDRSS_PHY_863_DATA 0x00000000
+#define DDRSS_PHY_864_DATA 0x00000000
+#define DDRSS_PHY_865_DATA 0x00000000
+#define DDRSS_PHY_866_DATA 0x00000000
+#define DDRSS_PHY_867_DATA 0x00000000
+#define DDRSS_PHY_868_DATA 0x00000000
+#define DDRSS_PHY_869_DATA 0x00000000
+#define DDRSS_PHY_870_DATA 0x00000000
+#define DDRSS_PHY_871_DATA 0x00000000
+#define DDRSS_PHY_872_DATA 0x00000000
+#define DDRSS_PHY_873_DATA 0x00000000
+#define DDRSS_PHY_874_DATA 0x00000000
+#define DDRSS_PHY_875_DATA 0x00000000
+#define DDRSS_PHY_876_DATA 0x00000000
+#define DDRSS_PHY_877_DATA 0x00000000
+#define DDRSS_PHY_878_DATA 0x00000000
+#define DDRSS_PHY_879_DATA 0x00000000
+#define DDRSS_PHY_880_DATA 0x00000000
+#define DDRSS_PHY_881_DATA 0x00000000
+#define DDRSS_PHY_882_DATA 0x00000000
+#define DDRSS_PHY_883_DATA 0x00000000
+#define DDRSS_PHY_884_DATA 0x00000000
+#define DDRSS_PHY_885_DATA 0x00000000
+#define DDRSS_PHY_886_DATA 0x00000000
+#define DDRSS_PHY_887_DATA 0x00000000
+#define DDRSS_PHY_888_DATA 0x00000000
+#define DDRSS_PHY_889_DATA 0x00000000
+#define DDRSS_PHY_890_DATA 0x00000000
+#define DDRSS_PHY_891_DATA 0x00000000
+#define DDRSS_PHY_892_DATA 0x00000000
+#define DDRSS_PHY_893_DATA 0x00000000
+#define DDRSS_PHY_894_DATA 0x00000000
+#define DDRSS_PHY_895_DATA 0x00000000
+#define DDRSS_PHY_896_DATA 0x00000000
+#define DDRSS_PHY_897_DATA 0x00000000
+#define DDRSS_PHY_898_DATA 0x00000000
+#define DDRSS_PHY_899_DATA 0x00000000
+#define DDRSS_PHY_900_DATA 0x00000000
+#define DDRSS_PHY_901_DATA 0x00000000
+#define DDRSS_PHY_902_DATA 0x00000000
+#define DDRSS_PHY_903_DATA 0x00000000
+#define DDRSS_PHY_904_DATA 0x00000000
+#define DDRSS_PHY_905_DATA 0x00000000
+#define DDRSS_PHY_906_DATA 0x00000000
+#define DDRSS_PHY_907_DATA 0x00000000
+#define DDRSS_PHY_908_DATA 0x00000000
+#define DDRSS_PHY_909_DATA 0x00000000
+#define DDRSS_PHY_910_DATA 0x00000000
+#define DDRSS_PHY_911_DATA 0x00000000
+#define DDRSS_PHY_912_DATA 0x00000000
+#define DDRSS_PHY_913_DATA 0x00000000
+#define DDRSS_PHY_914_DATA 0x00000000
+#define DDRSS_PHY_915_DATA 0x00000000
+#define DDRSS_PHY_916_DATA 0x00000000
+#define DDRSS_PHY_917_DATA 0x00000000
+#define DDRSS_PHY_918_DATA 0x00000000
+#define DDRSS_PHY_919_DATA 0x00000000
+#define DDRSS_PHY_920_DATA 0x00000000
+#define DDRSS_PHY_921_DATA 0x00000000
+#define DDRSS_PHY_922_DATA 0x00000000
+#define DDRSS_PHY_923_DATA 0x00000000
+#define DDRSS_PHY_924_DATA 0x00000000
+#define DDRSS_PHY_925_DATA 0x00000000
+#define DDRSS_PHY_926_DATA 0x00000000
+#define DDRSS_PHY_927_DATA 0x00000000
+#define DDRSS_PHY_928_DATA 0x00000000
+#define DDRSS_PHY_929_DATA 0x00000000
+#define DDRSS_PHY_930_DATA 0x00000000
+#define DDRSS_PHY_931_DATA 0x00000000
+#define DDRSS_PHY_932_DATA 0x00000000
+#define DDRSS_PHY_933_DATA 0x00000000
+#define DDRSS_PHY_934_DATA 0x00000000
+#define DDRSS_PHY_935_DATA 0x00000000
+#define DDRSS_PHY_936_DATA 0x00000000
+#define DDRSS_PHY_937_DATA 0x00000000
+#define DDRSS_PHY_938_DATA 0x00000000
+#define DDRSS_PHY_939_DATA 0x00000000
+#define DDRSS_PHY_940_DATA 0x00000000
+#define DDRSS_PHY_941_DATA 0x00000000
+#define DDRSS_PHY_942_DATA 0x00000000
+#define DDRSS_PHY_943_DATA 0x00000000
+#define DDRSS_PHY_944_DATA 0x00000000
+#define DDRSS_PHY_945_DATA 0x00000000
+#define DDRSS_PHY_946_DATA 0x00000000
+#define DDRSS_PHY_947_DATA 0x00000000
+#define DDRSS_PHY_948_DATA 0x00000000
+#define DDRSS_PHY_949_DATA 0x00000000
+#define DDRSS_PHY_950_DATA 0x00000000
+#define DDRSS_PHY_951_DATA 0x00000000
+#define DDRSS_PHY_952_DATA 0x00000000
+#define DDRSS_PHY_953_DATA 0x00000000
+#define DDRSS_PHY_954_DATA 0x00000000
+#define DDRSS_PHY_955_DATA 0x00000000
+#define DDRSS_PHY_956_DATA 0x00000000
+#define DDRSS_PHY_957_DATA 0x00000000
+#define DDRSS_PHY_958_DATA 0x00000000
+#define DDRSS_PHY_959_DATA 0x00000000
+#define DDRSS_PHY_960_DATA 0x00000000
+#define DDRSS_PHY_961_DATA 0x00000000
+#define DDRSS_PHY_962_DATA 0x00000000
+#define DDRSS_PHY_963_DATA 0x00000000
+#define DDRSS_PHY_964_DATA 0x00000000
+#define DDRSS_PHY_965_DATA 0x00000000
+#define DDRSS_PHY_966_DATA 0x00000000
+#define DDRSS_PHY_967_DATA 0x00000000
+#define DDRSS_PHY_968_DATA 0x00000000
+#define DDRSS_PHY_969_DATA 0x00000000
+#define DDRSS_PHY_970_DATA 0x00000000
+#define DDRSS_PHY_971_DATA 0x00000000
+#define DDRSS_PHY_972_DATA 0x00000000
+#define DDRSS_PHY_973_DATA 0x00000000
+#define DDRSS_PHY_974_DATA 0x00000000
+#define DDRSS_PHY_975_DATA 0x00000000
+#define DDRSS_PHY_976_DATA 0x00000000
+#define DDRSS_PHY_977_DATA 0x00000000
+#define DDRSS_PHY_978_DATA 0x00000000
+#define DDRSS_PHY_979_DATA 0x00000000
+#define DDRSS_PHY_980_DATA 0x00000000
+#define DDRSS_PHY_981_DATA 0x00000000
+#define DDRSS_PHY_982_DATA 0x00000000
+#define DDRSS_PHY_983_DATA 0x00000000
+#define DDRSS_PHY_984_DATA 0x00000000
+#define DDRSS_PHY_985_DATA 0x00000000
+#define DDRSS_PHY_986_DATA 0x00000000
+#define DDRSS_PHY_987_DATA 0x00000000
+#define DDRSS_PHY_988_DATA 0x00000000
+#define DDRSS_PHY_989_DATA 0x00000000
+#define DDRSS_PHY_990_DATA 0x00000000
+#define DDRSS_PHY_991_DATA 0x00000000
+#define DDRSS_PHY_992_DATA 0x00000000
+#define DDRSS_PHY_993_DATA 0x00000000
+#define DDRSS_PHY_994_DATA 0x00000000
+#define DDRSS_PHY_995_DATA 0x00000000
+#define DDRSS_PHY_996_DATA 0x00000000
+#define DDRSS_PHY_997_DATA 0x00000000
+#define DDRSS_PHY_998_DATA 0x00000000
+#define DDRSS_PHY_999_DATA 0x00000000
+#define DDRSS_PHY_1000_DATA 0x00000000
+#define DDRSS_PHY_1001_DATA 0x00000000
+#define DDRSS_PHY_1002_DATA 0x00000000
+#define DDRSS_PHY_1003_DATA 0x00000000
+#define DDRSS_PHY_1004_DATA 0x00000000
+#define DDRSS_PHY_1005_DATA 0x00000000
+#define DDRSS_PHY_1006_DATA 0x00000000
+#define DDRSS_PHY_1007_DATA 0x00000000
+#define DDRSS_PHY_1008_DATA 0x00000000
+#define DDRSS_PHY_1009_DATA 0x00000000
+#define DDRSS_PHY_1010_DATA 0x00000000
+#define DDRSS_PHY_1011_DATA 0x00000000
+#define DDRSS_PHY_1012_DATA 0x00000000
+#define DDRSS_PHY_1013_DATA 0x00000000
+#define DDRSS_PHY_1014_DATA 0x00000000
+#define DDRSS_PHY_1015_DATA 0x00000000
+#define DDRSS_PHY_1016_DATA 0x00000000
+#define DDRSS_PHY_1017_DATA 0x00000000
+#define DDRSS_PHY_1018_DATA 0x00000000
+#define DDRSS_PHY_1019_DATA 0x00000000
+#define DDRSS_PHY_1020_DATA 0x00000000
+#define DDRSS_PHY_1021_DATA 0x00000000
+#define DDRSS_PHY_1022_DATA 0x00000000
+#define DDRSS_PHY_1023_DATA 0x00000000
+#define DDRSS_PHY_1024_DATA 0x00000000
+#define DDRSS_PHY_1025_DATA 0x00000000
+#define DDRSS_PHY_1026_DATA 0x00000000
+#define DDRSS_PHY_1027_DATA 0x00000000
+#define DDRSS_PHY_1028_DATA 0x00000000
+#define DDRSS_PHY_1029_DATA 0x00000100
+#define DDRSS_PHY_1030_DATA 0x00000200
+#define DDRSS_PHY_1031_DATA 0x00000000
+#define DDRSS_PHY_1032_DATA 0x00000000
+#define DDRSS_PHY_1033_DATA 0x00000000
+#define DDRSS_PHY_1034_DATA 0x00000000
+#define DDRSS_PHY_1035_DATA 0x00400000
+#define DDRSS_PHY_1036_DATA 0x00000080
+#define DDRSS_PHY_1037_DATA 0x00DCBA98
+#define DDRSS_PHY_1038_DATA 0x03000000
+#define DDRSS_PHY_1039_DATA 0x00200000
+#define DDRSS_PHY_1040_DATA 0x00000000
+#define DDRSS_PHY_1041_DATA 0x00000000
+#define DDRSS_PHY_1042_DATA 0x00000000
+#define DDRSS_PHY_1043_DATA 0x00000000
+#define DDRSS_PHY_1044_DATA 0x0000002A
+#define DDRSS_PHY_1045_DATA 0x00000015
+#define DDRSS_PHY_1046_DATA 0x00000015
+#define DDRSS_PHY_1047_DATA 0x0000002A
+#define DDRSS_PHY_1048_DATA 0x00000033
+#define DDRSS_PHY_1049_DATA 0x0000000C
+#define DDRSS_PHY_1050_DATA 0x0000000C
+#define DDRSS_PHY_1051_DATA 0x00000033
+#define DDRSS_PHY_1052_DATA 0x2307B9AC
+#define DDRSS_PHY_1053_DATA 0x10000000
+#define DDRSS_PHY_1054_DATA 0x000F0000
+#define DDRSS_PHY_1055_DATA 0x0000000F
+#define DDRSS_PHY_1056_DATA 0x000002CC
+#define DDRSS_PHY_1057_DATA 0x00030000
+#define DDRSS_PHY_1058_DATA 0x00000300
+#define DDRSS_PHY_1059_DATA 0x00000300
+#define DDRSS_PHY_1060_DATA 0x00000300
+#define DDRSS_PHY_1061_DATA 0x00000300
+#define DDRSS_PHY_1062_DATA 0x00000300
+#define DDRSS_PHY_1063_DATA 0x42080010
+#define DDRSS_PHY_1064_DATA 0x0000803E
+#define DDRSS_PHY_1065_DATA 0x00000003
+#define DDRSS_PHY_1066_DATA 0x00000002
+#define DDRSS_PHY_1067_DATA 0x00000000
+#define DDRSS_PHY_1068_DATA 0x00000000
+#define DDRSS_PHY_1069_DATA 0x00000000
+#define DDRSS_PHY_1070_DATA 0x00000000
+#define DDRSS_PHY_1071_DATA 0x00000000
+#define DDRSS_PHY_1072_DATA 0x00000000
+#define DDRSS_PHY_1073_DATA 0x00000000
+#define DDRSS_PHY_1074_DATA 0x00000000
+#define DDRSS_PHY_1075_DATA 0x00000000
+#define DDRSS_PHY_1076_DATA 0x00000000
+#define DDRSS_PHY_1077_DATA 0x00000000
+#define DDRSS_PHY_1078_DATA 0x00000000
+#define DDRSS_PHY_1079_DATA 0x00000000
+#define DDRSS_PHY_1080_DATA 0x00000000
+#define DDRSS_PHY_1081_DATA 0x00000000
+#define DDRSS_PHY_1082_DATA 0x00000000
+#define DDRSS_PHY_1083_DATA 0x00000000
+#define DDRSS_PHY_1084_DATA 0x00000000
+#define DDRSS_PHY_1085_DATA 0x00000000
+#define DDRSS_PHY_1086_DATA 0x00000000
+#define DDRSS_PHY_1087_DATA 0x00000000
+#define DDRSS_PHY_1088_DATA 0x00000000
+#define DDRSS_PHY_1089_DATA 0x00000000
+#define DDRSS_PHY_1090_DATA 0x00000000
+#define DDRSS_PHY_1091_DATA 0x00000000
+#define DDRSS_PHY_1092_DATA 0x00000000
+#define DDRSS_PHY_1093_DATA 0x00000000
+#define DDRSS_PHY_1094_DATA 0x00000000
+#define DDRSS_PHY_1095_DATA 0x00000000
+#define DDRSS_PHY_1096_DATA 0x00000000
+#define DDRSS_PHY_1097_DATA 0x00000000
+#define DDRSS_PHY_1098_DATA 0x00000000
+#define DDRSS_PHY_1099_DATA 0x00000000
+#define DDRSS_PHY_1100_DATA 0x00000000
+#define DDRSS_PHY_1101_DATA 0x00000000
+#define DDRSS_PHY_1102_DATA 0x00000000
+#define DDRSS_PHY_1103_DATA 0x00000000
+#define DDRSS_PHY_1104_DATA 0x00000000
+#define DDRSS_PHY_1105_DATA 0x00000000
+#define DDRSS_PHY_1106_DATA 0x00000000
+#define DDRSS_PHY_1107_DATA 0x00000000
+#define DDRSS_PHY_1108_DATA 0x00000000
+#define DDRSS_PHY_1109_DATA 0x00000000
+#define DDRSS_PHY_1110_DATA 0x00000000
+#define DDRSS_PHY_1111_DATA 0x00000000
+#define DDRSS_PHY_1112_DATA 0x00000000
+#define DDRSS_PHY_1113_DATA 0x00000000
+#define DDRSS_PHY_1114_DATA 0x00000000
+#define DDRSS_PHY_1115_DATA 0x00000000
+#define DDRSS_PHY_1116_DATA 0x00000000
+#define DDRSS_PHY_1117_DATA 0x00000000
+#define DDRSS_PHY_1118_DATA 0x00000000
+#define DDRSS_PHY_1119_DATA 0x00000000
+#define DDRSS_PHY_1120_DATA 0x00000000
+#define DDRSS_PHY_1121_DATA 0x00000000
+#define DDRSS_PHY_1122_DATA 0x00000000
+#define DDRSS_PHY_1123_DATA 0x00000000
+#define DDRSS_PHY_1124_DATA 0x00000000
+#define DDRSS_PHY_1125_DATA 0x00000000
+#define DDRSS_PHY_1126_DATA 0x00000000
+#define DDRSS_PHY_1127_DATA 0x00000000
+#define DDRSS_PHY_1128_DATA 0x00000000
+#define DDRSS_PHY_1129_DATA 0x00000000
+#define DDRSS_PHY_1130_DATA 0x00000000
+#define DDRSS_PHY_1131_DATA 0x00000000
+#define DDRSS_PHY_1132_DATA 0x00000000
+#define DDRSS_PHY_1133_DATA 0x00000000
+#define DDRSS_PHY_1134_DATA 0x00000000
+#define DDRSS_PHY_1135_DATA 0x00000000
+#define DDRSS_PHY_1136_DATA 0x00000000
+#define DDRSS_PHY_1137_DATA 0x00000000
+#define DDRSS_PHY_1138_DATA 0x00000000
+#define DDRSS_PHY_1139_DATA 0x00000000
+#define DDRSS_PHY_1140_DATA 0x00000000
+#define DDRSS_PHY_1141_DATA 0x00000000
+#define DDRSS_PHY_1142_DATA 0x00000000
+#define DDRSS_PHY_1143_DATA 0x00000000
+#define DDRSS_PHY_1144_DATA 0x00000000
+#define DDRSS_PHY_1145_DATA 0x00000000
+#define DDRSS_PHY_1146_DATA 0x00000000
+#define DDRSS_PHY_1147_DATA 0x00000000
+#define DDRSS_PHY_1148_DATA 0x00000000
+#define DDRSS_PHY_1149_DATA 0x00000000
+#define DDRSS_PHY_1150_DATA 0x00000000
+#define DDRSS_PHY_1151_DATA 0x00000000
+#define DDRSS_PHY_1152_DATA 0x00000000
+#define DDRSS_PHY_1153_DATA 0x00000000
+#define DDRSS_PHY_1154_DATA 0x00000000
+#define DDRSS_PHY_1155_DATA 0x00000000
+#define DDRSS_PHY_1156_DATA 0x00000000
+#define DDRSS_PHY_1157_DATA 0x00000000
+#define DDRSS_PHY_1158_DATA 0x00000000
+#define DDRSS_PHY_1159_DATA 0x00000000
+#define DDRSS_PHY_1160_DATA 0x00000000
+#define DDRSS_PHY_1161_DATA 0x00000000
+#define DDRSS_PHY_1162_DATA 0x00000000
+#define DDRSS_PHY_1163_DATA 0x00000000
+#define DDRSS_PHY_1164_DATA 0x00000000
+#define DDRSS_PHY_1165_DATA 0x00000000
+#define DDRSS_PHY_1166_DATA 0x00000000
+#define DDRSS_PHY_1167_DATA 0x00000000
+#define DDRSS_PHY_1168_DATA 0x00000000
+#define DDRSS_PHY_1169_DATA 0x00000000
+#define DDRSS_PHY_1170_DATA 0x00000000
+#define DDRSS_PHY_1171_DATA 0x00000000
+#define DDRSS_PHY_1172_DATA 0x00000000
+#define DDRSS_PHY_1173_DATA 0x00000000
+#define DDRSS_PHY_1174_DATA 0x00000000
+#define DDRSS_PHY_1175_DATA 0x00000000
+#define DDRSS_PHY_1176_DATA 0x00000000
+#define DDRSS_PHY_1177_DATA 0x00000000
+#define DDRSS_PHY_1178_DATA 0x00000000
+#define DDRSS_PHY_1179_DATA 0x00000000
+#define DDRSS_PHY_1180_DATA 0x00000000
+#define DDRSS_PHY_1181_DATA 0x00000000
+#define DDRSS_PHY_1182_DATA 0x00000000
+#define DDRSS_PHY_1183_DATA 0x00000000
+#define DDRSS_PHY_1184_DATA 0x00000000
+#define DDRSS_PHY_1185_DATA 0x00000000
+#define DDRSS_PHY_1186_DATA 0x00000000
+#define DDRSS_PHY_1187_DATA 0x00000000
+#define DDRSS_PHY_1188_DATA 0x00000000
+#define DDRSS_PHY_1189_DATA 0x00000000
+#define DDRSS_PHY_1190_DATA 0x00000000
+#define DDRSS_PHY_1191_DATA 0x00000000
+#define DDRSS_PHY_1192_DATA 0x00000000
+#define DDRSS_PHY_1193_DATA 0x00000000
+#define DDRSS_PHY_1194_DATA 0x00000000
+#define DDRSS_PHY_1195_DATA 0x00000000
+#define DDRSS_PHY_1196_DATA 0x00000000
+#define DDRSS_PHY_1197_DATA 0x00000000
+#define DDRSS_PHY_1198_DATA 0x00000000
+#define DDRSS_PHY_1199_DATA 0x00000000
+#define DDRSS_PHY_1200_DATA 0x00000000
+#define DDRSS_PHY_1201_DATA 0x00000000
+#define DDRSS_PHY_1202_DATA 0x00000000
+#define DDRSS_PHY_1203_DATA 0x00000000
+#define DDRSS_PHY_1204_DATA 0x00000000
+#define DDRSS_PHY_1205_DATA 0x00000000
+#define DDRSS_PHY_1206_DATA 0x00000000
+#define DDRSS_PHY_1207_DATA 0x00000000
+#define DDRSS_PHY_1208_DATA 0x00000000
+#define DDRSS_PHY_1209_DATA 0x00000000
+#define DDRSS_PHY_1210_DATA 0x00000000
+#define DDRSS_PHY_1211_DATA 0x00000000
+#define DDRSS_PHY_1212_DATA 0x00000000
+#define DDRSS_PHY_1213_DATA 0x00000000
+#define DDRSS_PHY_1214_DATA 0x00000000
+#define DDRSS_PHY_1215_DATA 0x00000000
+#define DDRSS_PHY_1216_DATA 0x00000000
+#define DDRSS_PHY_1217_DATA 0x00000000
+#define DDRSS_PHY_1218_DATA 0x00000000
+#define DDRSS_PHY_1219_DATA 0x00000000
+#define DDRSS_PHY_1220_DATA 0x00000000
+#define DDRSS_PHY_1221_DATA 0x00000000
+#define DDRSS_PHY_1222_DATA 0x00000000
+#define DDRSS_PHY_1223_DATA 0x00000000
+#define DDRSS_PHY_1224_DATA 0x00000000
+#define DDRSS_PHY_1225_DATA 0x00000000
+#define DDRSS_PHY_1226_DATA 0x00000000
+#define DDRSS_PHY_1227_DATA 0x00000000
+#define DDRSS_PHY_1228_DATA 0x00000000
+#define DDRSS_PHY_1229_DATA 0x00000000
+#define DDRSS_PHY_1230_DATA 0x00000000
+#define DDRSS_PHY_1231_DATA 0x00000000
+#define DDRSS_PHY_1232_DATA 0x00000000
+#define DDRSS_PHY_1233_DATA 0x00000000
+#define DDRSS_PHY_1234_DATA 0x00000000
+#define DDRSS_PHY_1235_DATA 0x00000000
+#define DDRSS_PHY_1236_DATA 0x00000000
+#define DDRSS_PHY_1237_DATA 0x00000000
+#define DDRSS_PHY_1238_DATA 0x00000000
+#define DDRSS_PHY_1239_DATA 0x00000000
+#define DDRSS_PHY_1240_DATA 0x00000000
+#define DDRSS_PHY_1241_DATA 0x00000000
+#define DDRSS_PHY_1242_DATA 0x00000000
+#define DDRSS_PHY_1243_DATA 0x00000000
+#define DDRSS_PHY_1244_DATA 0x00000000
+#define DDRSS_PHY_1245_DATA 0x00000000
+#define DDRSS_PHY_1246_DATA 0x00000000
+#define DDRSS_PHY_1247_DATA 0x00000000
+#define DDRSS_PHY_1248_DATA 0x00000000
+#define DDRSS_PHY_1249_DATA 0x00000000
+#define DDRSS_PHY_1250_DATA 0x00000000
+#define DDRSS_PHY_1251_DATA 0x00000000
+#define DDRSS_PHY_1252_DATA 0x00000000
+#define DDRSS_PHY_1253_DATA 0x00000000
+#define DDRSS_PHY_1254_DATA 0x00000000
+#define DDRSS_PHY_1255_DATA 0x00000000
+#define DDRSS_PHY_1256_DATA 0x00000000
+#define DDRSS_PHY_1257_DATA 0x00000000
+#define DDRSS_PHY_1258_DATA 0x00000000
+#define DDRSS_PHY_1259_DATA 0x00000000
+#define DDRSS_PHY_1260_DATA 0x00000000
+#define DDRSS_PHY_1261_DATA 0x00000000
+#define DDRSS_PHY_1262_DATA 0x00000000
+#define DDRSS_PHY_1263_DATA 0x00000000
+#define DDRSS_PHY_1264_DATA 0x00000000
+#define DDRSS_PHY_1265_DATA 0x00000000
+#define DDRSS_PHY_1266_DATA 0x00000000
+#define DDRSS_PHY_1267_DATA 0x00000000
+#define DDRSS_PHY_1268_DATA 0x00000000
+#define DDRSS_PHY_1269_DATA 0x00000000
+#define DDRSS_PHY_1270_DATA 0x00000000
+#define DDRSS_PHY_1271_DATA 0x00000000
+#define DDRSS_PHY_1272_DATA 0x00000000
+#define DDRSS_PHY_1273_DATA 0x00000000
+#define DDRSS_PHY_1274_DATA 0x00000000
+#define DDRSS_PHY_1275_DATA 0x00000000
+#define DDRSS_PHY_1276_DATA 0x00000000
+#define DDRSS_PHY_1277_DATA 0x00000000
+#define DDRSS_PHY_1278_DATA 0x00000000
+#define DDRSS_PHY_1279_DATA 0x00000000
+#define DDRSS_PHY_1280_DATA 0x00000000
+#define DDRSS_PHY_1281_DATA 0x00010100
+#define DDRSS_PHY_1282_DATA 0x00000000
+#define DDRSS_PHY_1283_DATA 0x00000000
+#define DDRSS_PHY_1284_DATA 0x00000000
+#define DDRSS_PHY_1285_DATA 0x00000000
+#define DDRSS_PHY_1286_DATA 0x00050000
+#define DDRSS_PHY_1287_DATA 0x04000000
+#define DDRSS_PHY_1288_DATA 0x00000055
+#define DDRSS_PHY_1289_DATA 0x00000000
+#define DDRSS_PHY_1290_DATA 0x00000000
+#define DDRSS_PHY_1291_DATA 0x00000000
+#define DDRSS_PHY_1292_DATA 0x00000000
+#define DDRSS_PHY_1293_DATA 0x00002001
+#define DDRSS_PHY_1294_DATA 0x00004001
+#define DDRSS_PHY_1295_DATA 0x00020028
+#define DDRSS_PHY_1296_DATA 0x01010100
+#define DDRSS_PHY_1297_DATA 0x00000000
+#define DDRSS_PHY_1298_DATA 0x00000000
+#define DDRSS_PHY_1299_DATA 0x0F0F0E06
+#define DDRSS_PHY_1300_DATA 0x00010101
+#define DDRSS_PHY_1301_DATA 0x010F0004
+#define DDRSS_PHY_1302_DATA 0x00000000
+#define DDRSS_PHY_1303_DATA 0x00000000
+#define DDRSS_PHY_1304_DATA 0x00000064
+#define DDRSS_PHY_1305_DATA 0x00000000
+#define DDRSS_PHY_1306_DATA 0x00000000
+#define DDRSS_PHY_1307_DATA 0x01020103
+#define DDRSS_PHY_1308_DATA 0x0F020102
+#define DDRSS_PHY_1309_DATA 0x03030303
+#define DDRSS_PHY_1310_DATA 0x03030303
+#define DDRSS_PHY_1311_DATA 0x00041B42
+#define DDRSS_PHY_1312_DATA 0x00005201
+#define DDRSS_PHY_1313_DATA 0x00000000
+#define DDRSS_PHY_1314_DATA 0x00000000
+#define DDRSS_PHY_1315_DATA 0x00000000
+#define DDRSS_PHY_1316_DATA 0x00000000
+#define DDRSS_PHY_1317_DATA 0x00000000
+#define DDRSS_PHY_1318_DATA 0x00000000
+#define DDRSS_PHY_1319_DATA 0x07030101
+#define DDRSS_PHY_1320_DATA 0x00005400
+#define DDRSS_PHY_1321_DATA 0x000040A2
+#define DDRSS_PHY_1322_DATA 0x00024410
+#define DDRSS_PHY_1323_DATA 0x00004410
+#define DDRSS_PHY_1324_DATA 0x00004410
+#define DDRSS_PHY_1325_DATA 0x00004410
+#define DDRSS_PHY_1326_DATA 0x00004410
+#define DDRSS_PHY_1327_DATA 0x00004410
+#define DDRSS_PHY_1328_DATA 0x00004410
+#define DDRSS_PHY_1329_DATA 0x00004410
+#define DDRSS_PHY_1330_DATA 0x00004410
+#define DDRSS_PHY_1331_DATA 0x00004410
+#define DDRSS_PHY_1332_DATA 0x00000000
+#define DDRSS_PHY_1333_DATA 0x00000076
+#define DDRSS_PHY_1334_DATA 0x00010000
+#define DDRSS_PHY_1335_DATA 0x00000008
+#define DDRSS_PHY_1336_DATA 0x00000000
+#define DDRSS_PHY_1337_DATA 0x00000000
+#define DDRSS_PHY_1338_DATA 0x00000000
+#define DDRSS_PHY_1339_DATA 0x00000000
+#define DDRSS_PHY_1340_DATA 0x00000000
+#define DDRSS_PHY_1341_DATA 0x03000000
+#define DDRSS_PHY_1342_DATA 0x00000000
+#define DDRSS_PHY_1343_DATA 0x00000000
+#define DDRSS_PHY_1344_DATA 0x00000000
+#define DDRSS_PHY_1345_DATA 0x04102006
+#define DDRSS_PHY_1346_DATA 0x00041020
+#define DDRSS_PHY_1347_DATA 0x01C98C98
+#define DDRSS_PHY_1348_DATA 0x3F400000
+#define DDRSS_PHY_1349_DATA 0x3F3F1F3F
+#define DDRSS_PHY_1350_DATA 0x0000001F
+#define DDRSS_PHY_1351_DATA 0x00000000
+#define DDRSS_PHY_1352_DATA 0x00000000
+#define DDRSS_PHY_1353_DATA 0x00000000
+#define DDRSS_PHY_1354_DATA 0x00000001
+#define DDRSS_PHY_1355_DATA 0x00000000
+#define DDRSS_PHY_1356_DATA 0x00000000
+#define DDRSS_PHY_1357_DATA 0x00000000
+#define DDRSS_PHY_1358_DATA 0x00000000
+#define DDRSS_PHY_1359_DATA 0x76543210
+#define DDRSS_PHY_1360_DATA 0x00040198
+#define DDRSS_PHY_1361_DATA 0x00000000
+#define DDRSS_PHY_1362_DATA 0x00000000
+#define DDRSS_PHY_1363_DATA 0x00000000
+#define DDRSS_PHY_1364_DATA 0x00040700
+#define DDRSS_PHY_1365_DATA 0x00000000
+#define DDRSS_PHY_1366_DATA 0x00000000
+#define DDRSS_PHY_1367_DATA 0x00000000
+#define DDRSS_PHY_1368_DATA 0x00000002
+#define DDRSS_PHY_1369_DATA 0x00000000
+#define DDRSS_PHY_1370_DATA 0x00000000
+#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1372_DATA 0x00000002
+#define DDRSS_PHY_1373_DATA 0x00000000
+#define DDRSS_PHY_1374_DATA 0x00001142
+#define DDRSS_PHY_1375_DATA 0x030207AB
+#define DDRSS_PHY_1376_DATA 0x00000080
+#define DDRSS_PHY_1377_DATA 0x03900390
+#define DDRSS_PHY_1378_DATA 0x03900390
+#define DDRSS_PHY_1379_DATA 0x03900390
+#define DDRSS_PHY_1380_DATA 0x03900390
+#define DDRSS_PHY_1381_DATA 0x03000300
+#define DDRSS_PHY_1382_DATA 0x03000300
+#define DDRSS_PHY_1383_DATA 0x00000300
+#define DDRSS_PHY_1384_DATA 0x00000300
+#define DDRSS_PHY_1385_DATA 0x00000300
+#define DDRSS_PHY_1386_DATA 0x00000300
+#define DDRSS_PHY_1387_DATA 0x3183BF77
+#define DDRSS_PHY_1388_DATA 0x00000000
+#define DDRSS_PHY_1389_DATA 0x0C000DFF
+#define DDRSS_PHY_1390_DATA 0x30000DFF
+#define DDRSS_PHY_1391_DATA 0x3F0DFF11
+#define DDRSS_PHY_1392_DATA 0x01990000
+#define DDRSS_PHY_1393_DATA 0x780DFFCC
+#define DDRSS_PHY_1394_DATA 0x00000C11
+#define DDRSS_PHY_1395_DATA 0x00018011
+#define DDRSS_PHY_1396_DATA 0x0089FF00
+#define DDRSS_PHY_1397_DATA 0x000C3F11
+#define DDRSS_PHY_1398_DATA 0x01990000
+#define DDRSS_PHY_1399_DATA 0x000C3F11
+#define DDRSS_PHY_1400_DATA 0x01990000
+#define DDRSS_PHY_1401_DATA 0x3F0DFF11
+#define DDRSS_PHY_1402_DATA 0x019900E0
+#define DDRSS_PHY_1403_DATA 0x00018011
+#define DDRSS_PHY_1404_DATA 0x0089FF00
+#define DDRSS_PHY_1405_DATA 0x20040001
diff --git a/arch/arm/dts/k3-am64.dtsi b/arch/arm/dts/k3-am64.dtsi
new file mode 100644
index 0000000..6b2d080
--- /dev/null
+++ b/arch/arm/dts/k3-am64.dtsi
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC Family
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+/ {
+ model = "Texas Instruments K3 AM642 SoC";
+ compatible = "ti,am642";
+ interrupt-parent = <&gic500>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &mcu_uart0;
+ serial1 = &mcu_uart1;
+ serial2 = &main_uart0;
+ serial3 = &main_uart1;
+ serial4 = &main_uart2;
+ serial5 = &main_uart3;
+ serial6 = &main_uart4;
+ serial7 = &main_uart5;
+ serial8 = &main_uart6;
+ i2c0 = &main_i2c0;
+ i2c1 = &main_i2c1;
+ ethernet0 = &cpsw_port1;
+ ethernet1 = &cpsw_port2;
+ };
+
+ chosen { };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ a53_timer0: timer-cl0-cpu0 {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ cbass_main: bus@f4000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
+ <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
+ <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
+ <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
+ <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
+ <0x00 0x0f000000 0x00 0x0f000000 0x00 0x00c44200>, /* Second peripheral window */
+ <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
+ <0x00 0x30000000 0x00 0x30000000 0x00 0x000bc100>, /* ICSSG0/1 */
+ <0x00 0x37000000 0x00 0x37000000 0x00 0x00040000>, /* TIMERMGR0 TIMERS */
+ <0x00 0x39000000 0x00 0x39000000 0x00 0x00000400>, /* CPTS0 */
+ <0x00 0x3b000000 0x00 0x3b000000 0x00 0x00000400>, /* GPMC0_CFG */
+ <0x00 0x3cd00000 0x00 0x3cd00000 0x00 0x00000200>, /* TIMERMGR0_CONFIG */
+ <0x00 0x3f004000 0x00 0x3f004000 0x00 0x00000400>, /* GICSS0_REGS */
+ <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>, /* CTRL_MMR0 */
+ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
+ <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMASS */
+ <0x00 0x50000000 0x00 0x50000000 0x00 0x08000000>, /* GPMC0 DATA */
+ <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
+ <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe DAT0 */
+ <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* OC SRAM */
+ <0x00 0x78000000 0x00 0x78000000 0x00 0x00800000>, /* Main R5FSS */
+ <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe DAT1 */
+ <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
+
+ /* MCU Domain Range */
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>;
+
+ cbass_mcu: bus@4000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
+ };
+ };
+};
+
+/* Now include the peripherals for each bus segments */
+#include "k3-am64-main.dtsi"
+#include "k3-am64-mcu.dtsi"
diff --git a/arch/arm/dts/k3-am642-evm-u-boot.dtsi b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
new file mode 100644
index 0000000..ed38b72
--- /dev/null
+++ b/arch/arm/dts/k3-am642-evm-u-boot.dtsi
@@ -0,0 +1,116 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+};
+
+&cbass_main{
+ u-boot,dm-spl;
+ timer1: timer@2400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x2400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <250000000>;
+ u-boot,dm-spl;
+ };
+};
+
+&main_conf {
+ u-boot,dm-spl;
+ chipid@14 {
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+ >;
+ };
+};
+
+&main_i2c0 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_uart0 {
+ u-boot,dm-spl;
+};
+
+&usb0 {
+ dr_mode="peripheral";
+ u-boot,dm-spl;
+};
+
+&usbss0 {
+ u-boot,dm-spl;
+};
+
+&main_usb0_pins_default {
+ u-boot,dm-spl;
+};
+
+&dmss {
+ u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&dmsc {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&sdhci0 {
+ u-boot,dm-spl;
+};
+
+&sdhci1 {
+ u-boot,dm-spl;
+};
+
+&cpsw3g {
+ reg = <0x0 0x8000000 0x0 0x200000>,
+ <0x0 0x43000200 0x0 0x8>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel@04044 {
+ compatible = "ti,am64-phy-gmii-sel";
+ reg = <0x0 0x43004044 0x0 0x8>;
+ };
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am642-evm.dts b/arch/arm/dts/k3-am642-evm.dts
new file mode 100644
index 0000000..3a505d2
--- /dev/null
+++ b/arch/arm/dts/k3-am642-evm.dts
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am642.dtsi"
+
+/ {
+ compatible = "ti,am642-evm", "ti,am642";
+ model = "Texas Instruments AM642 EVM";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ evm_12v0: fixedregulator-evm12v0 {
+ /* main DC jack */
+ compatible = "regulator-fixed";
+ regulator-name = "evm_12v0";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_5v0: fixedregulator-vsys5v0 {
+ /* output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vsys_3v3: fixedregulator-vsys3v3 {
+ /* output of LM5140 */
+ compatible = "regulator-fixed";
+ regulator-name = "vsys_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&evm_12v0>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_mmc1: fixed-regulator-sd {
+ /* TPS2051BD */
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&exp1 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ vddb: fixedregulator-vddb {
+ compatible = "regulator-fixed";
+ regulator-name = "vddb_3v3_display";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vsys_3v3>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ label = "am64-evm:red:heartbeat";
+ gpios = <&exp1 16 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ function = LED_FUNCTION_HEARTBEAT;
+ default-state = "off";
+ };
+ };
+
+ mdio_mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ mdio-mux-1 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mdio_mux>;
+ mdio-parent-bus = <&cpsw3g_mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw3g_phy3: ethernet-phy@3 {
+ reg = <3>;
+ };
+ };
+ };
+};
+
+&main_pmx0 {
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */
+ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */
+ >;
+ };
+
+ main_uart0_pins_default: main-uart0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
+ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
+ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
+ >;
+ };
+
+ mdio1_pins_default: mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */
+ AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */
+ AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */
+ AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */
+ AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */
+ AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */
+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+ AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+ AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
+
+ main_usb0_pins_default: main-usb0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+ >;
+ };
+};
+
+&main_uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+};
+
+/* main_uart1 is reserved for firmware usage */
+&main_uart1 {
+ status = "reserved";
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&main_uart3 {
+ status = "disabled";
+};
+
+&main_uart4 {
+ status = "disabled";
+};
+
+&main_uart5 {
+ status = "disabled";
+};
+
+&main_uart6 {
+ status = "disabled";
+};
+
+&mcu_uart0 {
+ status = "disabled";
+};
+
+&mcu_uart1 {
+ status = "disabled";
+};
+
+&main_i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c1_pins_default>;
+ clock-frequency = <400000>;
+
+ exp1: gpio@22 {
+ compatible = "ti,tca6424";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL",
+ "GPIO_CPSW1_RST", "GPIO_RGMII1_RST",
+ "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT",
+ "MMC1_SD_EN", "FSI_FET_SEL",
+ "MCAN0_STB_3V3", "MCAN1_STB_3V3",
+ "CPSW_FET_SEL", "CPSW_FET2_SEL",
+ "PRG1_RGMII2_FET_SEL", "TEST_GPIO2",
+ "GPIO_OLED_RESETn", "VPP_LDO_EN",
+ "TEST_LED1", "TP92", "TP90", "TP88",
+ "TP87", "TP86", "TP89", "TP91";
+ };
+
+ /* osd9616p0899-10 */
+ display@3c {
+ compatible = "solomon,ssd1306fb-i2c";
+ reg = <0x3c>;
+ reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>;
+ vbat-supply = <&vddb>;
+ solomon,height = <16>;
+ solomon,width = <96>;
+ solomon,com-seq;
+ solomon,com-invdir;
+ solomon,page-offset = <0>;
+ solomon,prechargep1 = <2>;
+ solomon,prechargep2 = <13>;
+ };
+};
+
+&mcu_i2c0 {
+ status = "disabled";
+};
+
+&mcu_i2c1 {
+ status = "disabled";
+};
+
+&mcu_spi0 {
+ status = "disabled";
+};
+
+&mcu_spi1 {
+ status = "disabled";
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default
+ &rgmii1_pins_default
+ &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw_port2 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy3>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
+
+&sdhci0 {
+ /* emmc */
+ bus-width = <8>;
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ vmmc-supply = <&vdd_mmc1>;
+ pinctrl-names = "default";
+ bus-width = <4>;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb0_pins_default>;
+};
diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
new file mode 100644
index 0000000..cc48fd4
--- /dev/null
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am642.dtsi"
+#include "k3-am64-evm-ddr4-1600MTs.dtsi"
+#include "k3-am64-ddr.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1000000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ clk_200mhz: dummy-clock-200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-spl;
+ };
+
+ vtt_supply: vtt-supply {
+ compatible = "regulator-gpio";
+ regulator-name = "vtt";
+ regulator-min-microvolt = <0>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&main_gpio0 12 GPIO_ACTIVE_HIGH>;
+ states = <0 0x0 3300000 0x1>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_main {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
+ mbox-names = "tx", "rx";
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+ main_uart0_pins_default: main-uart0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
+ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
+ >;
+ };
+
+ main_uart1_pins_default: main-uart1-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
+ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
+ >;
+ };
+
+ main_mmc0_pins_default: main-mmc0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
+ AM64X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
+ AM64X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
+ AM64X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
+ AM64X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
+ AM64X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
+ AM64X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
+ AM64X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
+ AM64X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
+ AM64X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
+ AM64X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
+ >;
+ };
+
+ ddr_vtt_pins_default: ddr-vtt-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
+ >;
+ };
+
+ main_usb0_pins_default: main-usb0-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
+ >;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&main_uart0 {
+ /delete-property/ power-domains;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ status = "okay";
+};
+
+&main_uart1 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+};
+
+&memorycontroller {
+ vtt-supply = <&vtt_supply>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&ddr_vtt_pins_default>;
+};
+
+&sdhci0 {
+ /delete-property/ power-domains;
+ clocks = <&clk_200mhz>;
+ clock-names = "clk_xin";
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ pinctrl-0 = <&main_mmc0_pins_default>;
+};
+
+&sdhci1 {
+ /delete-property/ power-domains;
+ clocks = <&clk_200mhz>;
+ clock-names = "clk_xin";
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+};
+
+&main_gpio0 {
+ u-boot,dm-spl;
+ /delete-property/ power-domains;
+};
+
+/* EEPROM might be read before SYSFW is available */
+&main_i2c0 {
+ /delete-property/ power-domains;
+};
+
+&usbss0 {
+ ti,vbus-divider;
+ ti,usb2-only;
+};
+
+&usb0 {
+ dr_mode = "otg";
+ maximum-speed = "high-speed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_usb0_pins_default>;
+};
+
+#include "k3-am642-evm-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts
new file mode 100644
index 0000000..79eff82
--- /dev/null
+++ b/arch/arm/dts/k3-am642-r5-sk.dts
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am642.dtsi"
+#include "k3-am64-sk-lp4-1333MTs.dtsi"
+#include "k3-am64-ddr.dtsi"
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+
+ aliases {
+ remoteproc0 = &sysctrler;
+ remoteproc1 = &a53_0;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ a53_0: a53@0 {
+ compatible = "ti,am654-rproc";
+ reg = <0x00 0x00a90000 0x00 0x10>;
+ power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
+ <&k3_pds 135 TI_SCI_PD_EXCLUSIVE>;
+ resets = <&k3_reset 135 0>;
+ clocks = <&k3_clks 61 0>;
+ assigned-clocks = <&k3_clks 61 0>, <&k3_clks 135 0>;
+ assigned-clock-parents = <&k3_clks 61 2>;
+ assigned-clock-rates = <200000000>, <1000000000>;
+ ti,sci = <&dmsc>;
+ ti,sci-proc-id = <32>;
+ ti,sci-host-id = <10>;
+ u-boot,dm-spl;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ clk_200mhz: dummy-clock-200mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ u-boot,dm-spl;
+ };
+};
+
+&cbass_main {
+ sysctrler: sysctrler {
+ compatible = "ti,am654-system-controller";
+ mboxes= <&secure_proxy_main 1>, <&secure_proxy_main 0>;
+ mbox-names = "tx", "rx";
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+ main_uart0_pins_default: main-uart0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
+ AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
+ AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
+ AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
+ >;
+ };
+
+ main_uart1_pins_default: main-uart1-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
+ AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
+ AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
+ AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
+ >;
+ };
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
+ AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
+ AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
+ >;
+ };
+};
+
+&dmsc {
+ mboxes= <&secure_proxy_main 0>,
+ <&secure_proxy_main 1>,
+ <&secure_proxy_main 0>;
+ mbox-names = "rx", "tx", "notify";
+ ti,host-id = <35>;
+ ti,secure-host;
+};
+
+&main_uart0 {
+ /delete-property/ power-domains;
+ /delete-property/ clocks;
+ /delete-property/ clock-names;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart0_pins_default>;
+ status = "okay";
+};
+
+&main_uart1 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_uart1_pins_default>;
+};
+
+&sdhci1 {
+ /delete-property/ power-domains;
+ clocks = <&clk_200mhz>;
+ clock-names = "clk_xin";
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+};
+
+#include "k3-am642-sk-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-am642-sk-u-boot.dtsi b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
new file mode 100644
index 0000000..35b49df
--- /dev/null
+++ b/arch/arm/dts/k3-am642-sk-u-boot.dtsi
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/ {
+ chosen {
+ stdout-path = "serial2:115200n8";
+ tick-timer = &timer1;
+ };
+};
+
+&cbass_main{
+ u-boot,dm-spl;
+ timer1: timer@2400000 {
+ compatible = "ti,omap5430-timer";
+ reg = <0x0 0x2400000 0x0 0x80>;
+ ti,timer-alwon;
+ clock-frequency = <250000000>;
+ u-boot,dm-spl;
+ };
+};
+
+&main_conf {
+ u-boot,dm-spl;
+ chipid@14 {
+ u-boot,dm-spl;
+ };
+};
+
+&main_pmx0 {
+ u-boot,dm-spl;
+ main_i2c0_pins_default: main-i2c0-pins-default {
+ u-boot,dm-spl;
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
+ AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
+ >;
+ };
+};
+
+&main_i2c0 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c0_pins_default>;
+ clock-frequency = <400000>;
+};
+
+&main_uart0 {
+ u-boot,dm-spl;
+};
+
+&dmss {
+ u-boot,dm-spl;
+};
+
+&secure_proxy_main {
+ u-boot,dm-spl;
+};
+
+&dmsc {
+ u-boot,dm-spl;
+ k3_sysreset: sysreset-controller {
+ compatible = "ti,sci-sysreset";
+ u-boot,dm-spl;
+ };
+};
+
+&k3_pds {
+ u-boot,dm-spl;
+};
+
+&k3_clks {
+ u-boot,dm-spl;
+};
+
+&k3_reset {
+ u-boot,dm-spl;
+};
+
+&sdhci0 {
+ u-boot,dm-spl;
+};
+
+&sdhci1 {
+ u-boot,dm-spl;
+};
+
+&main_mmc1_pins_default {
+ u-boot,dm-spl;
+};
+
+&cpsw3g {
+ reg = <0x0 0x8000000 0x0 0x200000>,
+ <0x0 0x43000200 0x0 0x8>;
+ reg-names = "cpsw_nuss", "mac_efuse";
+ /delete-property/ ranges;
+
+ cpsw-phy-sel@04044 {
+ compatible = "ti,am64-phy-gmii-sel";
+ reg = <0x0 0x43004044 0x0 0x8>;
+ };
+};
+
+&cpsw_port2 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/k3-am642-sk.dts b/arch/arm/dts/k3-am642-sk.dts
new file mode 100644
index 0000000..df76c6e
--- /dev/null
+++ b/arch/arm/dts/k3-am642-sk.dts
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+#include "k3-am642.dtsi"
+
+/ {
+ compatible = "ti,am642-sk", "ti,am642";
+ model = "Texas Instruments AM642 SK";
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* 2G RAM */
+ reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
+
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ secure_ddr: optee@9e800000 {
+ reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+};
+
+&main_pmx0 {
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */
+ AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
+ AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */
+ AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */
+ AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */
+ AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */
+ AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */
+ AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */
+ >;
+ };
+
+ main_i2c1_pins_default: main-i2c1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
+ AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
+ >;
+ };
+
+ mdio1_pins_default: mdio1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
+ AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_pins_default: rgmii1-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
+ AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
+ AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
+ AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
+ AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
+ AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
+ AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
+ AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
+ AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
+ AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
+ AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
+ AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
+ >;
+ };
+
+ rgmii2_pins_default: rgmii2-pins-default {
+ pinctrl-single,pins = <
+ AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
+ AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
+ AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
+ AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
+ AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
+ AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
+ AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
+ AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
+ AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
+ AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
+ AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
+ AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
+ >;
+ };
+};
+
+&main_uart1 {
+ /* main_uart1 is reserved for firmware usage */
+ status = "reserved";
+};
+
+&main_uart2 {
+ status = "disabled";
+};
+
+&main_uart3 {
+ status = "disabled";
+};
+
+&main_uart4 {
+ status = "disabled";
+};
+
+&main_uart5 {
+ status = "disabled";
+};
+
+&main_uart6 {
+ status = "disabled";
+};
+
+&sdhci1 {
+ /* SD/MMC */
+ pinctrl-names = "default";
+ bus-width = <4>;
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&cpsw3g {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio1_pins_default
+ &rgmii1_pins_default
+ &rgmii2_pins_default>;
+};
+
+&cpsw_port1 {
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&cpsw3g_phy0>;
+};
+
+&cpsw3g_mdio {
+ cpsw3g_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ };
+};
diff --git a/arch/arm/dts/k3-am642.dtsi b/arch/arm/dts/k3-am642.dtsi
new file mode 100644
index 0000000..e2b397c
--- /dev/null
+++ b/arch/arm/dts/k3-am642.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for AM642 SoC family in Dual core configuration
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+
+#include "k3-am64.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0: cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ device_type = "cpu";
+ enable-method = "psci";
+ i-cache-size = <0x8000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <128>;
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x40000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+};
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index b0602d1..2840258 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -35,11 +35,25 @@
u-boot,dm-spl;
ringacc@2b800000 {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
u-boot,dm-spl;
ti,dma-ring-reset-quirk;
};
dma-controller@285c0000 {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
u-boot,dm-spl;
};
};
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index bd037be..41ce9fc 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -33,13 +33,39 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
- clock-frequency = <25000000>;
+ clock-frequency = <250000000>;
u-boot,dm-spl;
};
chipid@43000014 {
u-boot,dm-spl;
};
+
+ mcu-navss{
+ u-boot,dm-spl;
+
+ ringacc@2b800000 {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
+ u-boot,dm-spl;
+ };
+
+ dma-controller@285c0000 {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
+ u-boot,dm-spl;
+ };
+ };
};
&secure_proxy_main {
diff --git a/arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
similarity index 89%
rename from arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
rename to arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
index 12ffd91..42ac8c5 100644
--- a/arch/arm/dts/k3-j7200-ddr-evm-lp4-1600.dtsi
+++ b/arch/arm/dts/k3-j7200-ddr-evm-lp4-2666.dtsi
@@ -1,13 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * This file was generated by the AM752x_DRA82x_TDA4x_DDRSS_RegConfigTool, Revision: 0.3.0
- * This file was generated on 06/08/2020
- * Includes hand edits
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.5.0
+ * This file was generated on 08/07/2020
+ * Includes hand-edits
*/
#define DDRSS_PLL_FHS_CNT 10
-#define DDRSS_PLL_FREQUENCY_1 400000000
-#define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_PLL_FREQUENCY_1 666500000
+#define DDRSS_PLL_FREQUENCY_2 666500000
#define DDRSS_CTL_00_DATA 0x00000B00
#define DDRSS_CTL_01_DATA 0x00000000
@@ -20,14 +21,14 @@
#define DDRSS_CTL_08_DATA 0x000186A0
#define DDRSS_CTL_09_DATA 0x00000005
#define DDRSS_CTL_10_DATA 0x00000064
-#define DDRSS_CTL_11_DATA 0x00027100
-#define DDRSS_CTL_12_DATA 0x00186A00
+#define DDRSS_CTL_11_DATA 0x000411AB
+#define DDRSS_CTL_12_DATA 0x0028B0AB
#define DDRSS_CTL_13_DATA 0x00000005
-#define DDRSS_CTL_14_DATA 0x00000640
-#define DDRSS_CTL_15_DATA 0x00027100
-#define DDRSS_CTL_16_DATA 0x00186A00
+#define DDRSS_CTL_14_DATA 0x00000A6B
+#define DDRSS_CTL_15_DATA 0x000411AB
+#define DDRSS_CTL_16_DATA 0x0028B0AB
#define DDRSS_CTL_17_DATA 0x00000005
-#define DDRSS_CTL_18_DATA 0x00000640
+#define DDRSS_CTL_18_DATA 0x00000A6B
#define DDRSS_CTL_19_DATA 0x01010000
#define DDRSS_CTL_20_DATA 0x02011001
#define DDRSS_CTL_21_DATA 0x02010000
@@ -37,66 +38,66 @@
#define DDRSS_CTL_25_DATA 0x00000000
#define DDRSS_CTL_26_DATA 0x00000000
#define DDRSS_CTL_27_DATA 0x02020200
-#define DDRSS_CTL_28_DATA 0x00002020
+#define DDRSS_CTL_28_DATA 0x00003636
#define DDRSS_CTL_29_DATA 0x00100000
#define DDRSS_CTL_30_DATA 0x00000000
#define DDRSS_CTL_31_DATA 0x00000000
#define DDRSS_CTL_32_DATA 0x00000000
#define DDRSS_CTL_33_DATA 0x00000000
#define DDRSS_CTL_34_DATA 0x040C0000
-#define DDRSS_CTL_35_DATA 0x081C081C
+#define DDRSS_CTL_35_DATA 0x0C300C30
#define DDRSS_CTL_36_DATA 0x00050804
#define DDRSS_CTL_37_DATA 0x09040008
-#define DDRSS_CTL_38_DATA 0x08000204
-#define DDRSS_CTL_39_DATA 0x0B240034
-#define DDRSS_CTL_40_DATA 0x08001910
-#define DDRSS_CTL_41_DATA 0x0B240034
-#define DDRSS_CTL_42_DATA 0x20001910
+#define DDRSS_CTL_38_DATA 0x0D000204
+#define DDRSS_CTL_39_DATA 0x113C0057
+#define DDRSS_CTL_40_DATA 0x0D00291B
+#define DDRSS_CTL_41_DATA 0x113C0057
+#define DDRSS_CTL_42_DATA 0x2000291B
#define DDRSS_CTL_43_DATA 0x000A0A09
#define DDRSS_CTL_44_DATA 0x040006DB
-#define DDRSS_CTL_45_DATA 0x0C0A0904
-#define DDRSS_CTL_46_DATA 0x06006DB0
-#define DDRSS_CTL_47_DATA 0x0C0A0906
-#define DDRSS_CTL_48_DATA 0x06006DB0
-#define DDRSS_CTL_49_DATA 0x02030406
-#define DDRSS_CTL_50_DATA 0x11040500
-#define DDRSS_CTL_51_DATA 0x08121112
+#define DDRSS_CTL_45_DATA 0x130E0B04
+#define DDRSS_CTL_46_DATA 0x0A00B6D0
+#define DDRSS_CTL_47_DATA 0x130E0B0A
+#define DDRSS_CTL_48_DATA 0x0A00B6D0
+#define DDRSS_CTL_49_DATA 0x0203040A
+#define DDRSS_CTL_50_DATA 0x1C040500
+#define DDRSS_CTL_51_DATA 0x081D1C1D
#define DDRSS_CTL_52_DATA 0x14000D0A
#define DDRSS_CTL_53_DATA 0x02010A0A
#define DDRSS_CTL_54_DATA 0x01010002
-#define DDRSS_CTL_55_DATA 0x04222208
-#define DDRSS_CTL_56_DATA 0x04131304
-#define DDRSS_CTL_57_DATA 0x00001313
+#define DDRSS_CTL_55_DATA 0x04383808
+#define DDRSS_CTL_56_DATA 0x041F1F04
+#define DDRSS_CTL_57_DATA 0x00001F1F
#define DDRSS_CTL_58_DATA 0x00010100
#define DDRSS_CTL_59_DATA 0x03010000
#define DDRSS_CTL_60_DATA 0x00000E08
#define DDRSS_CTL_61_DATA 0x000000BB
-#define DDRSS_CTL_62_DATA 0x000000E0
-#define DDRSS_CTL_63_DATA 0x00000C28
-#define DDRSS_CTL_64_DATA 0x000000E0
-#define DDRSS_CTL_65_DATA 0x00000C28
+#define DDRSS_CTL_62_DATA 0x00000176
+#define DDRSS_CTL_63_DATA 0x00001448
+#define DDRSS_CTL_64_DATA 0x00000176
+#define DDRSS_CTL_65_DATA 0x00001448
#define DDRSS_CTL_66_DATA 0x00000005
#define DDRSS_CTL_67_DATA 0x00030000
-#define DDRSS_CTL_68_DATA 0x00380010
-#define DDRSS_CTL_69_DATA 0x0038017E
-#define DDRSS_CTL_70_DATA 0x0040017E
+#define DDRSS_CTL_68_DATA 0x005D0010
+#define DDRSS_CTL_69_DATA 0x005D0282
+#define DDRSS_CTL_70_DATA 0x00400282
#define DDRSS_CTL_71_DATA 0x00120103
-#define DDRSS_CTL_72_DATA 0x00060005
-#define DDRSS_CTL_73_DATA 0x14080006
-#define DDRSS_CTL_74_DATA 0x05050114
-#define DDRSS_CTL_75_DATA 0x0201030A
-#define DDRSS_CTL_76_DATA 0x030C0605
-#define DDRSS_CTL_77_DATA 0x06050201
-#define DDRSS_CTL_78_DATA 0x0001030C
+#define DDRSS_CTL_72_DATA 0x000A0005
+#define DDRSS_CTL_73_DATA 0x1F08000A
+#define DDRSS_CTL_74_DATA 0x0505011F
+#define DDRSS_CTL_75_DATA 0x0301030A
+#define DDRSS_CTL_76_DATA 0x03130A07
+#define DDRSS_CTL_77_DATA 0x0A070301
+#define DDRSS_CTL_78_DATA 0x00010313
#define DDRSS_CTL_79_DATA 0x000F000F
-#define DDRSS_CTL_80_DATA 0x00E600E6
-#define DDRSS_CTL_81_DATA 0x00E600E6
+#define DDRSS_CTL_80_DATA 0x01800180
+#define DDRSS_CTL_81_DATA 0x01800180
#define DDRSS_CTL_82_DATA 0x03050505
#define DDRSS_CTL_83_DATA 0x03010303
-#define DDRSS_CTL_84_DATA 0x0C050605
-#define DDRSS_CTL_85_DATA 0x03020603
-#define DDRSS_CTL_86_DATA 0x0C050605
-#define DDRSS_CTL_87_DATA 0x03020603
+#define DDRSS_CTL_84_DATA 0x14070A07
+#define DDRSS_CTL_85_DATA 0x03030A03
+#define DDRSS_CTL_86_DATA 0x14070A07
+#define DDRSS_CTL_87_DATA 0x03030A03
#define DDRSS_CTL_88_DATA 0x03010000
#define DDRSS_CTL_89_DATA 0x00010000
#define DDRSS_CTL_90_DATA 0x00000000
@@ -118,20 +119,20 @@
#define DDRSS_CTL_106_DATA 0x00002EC0
#define DDRSS_CTL_107_DATA 0x00000000
#define DDRSS_CTL_108_DATA 0x0000051D
-#define DDRSS_CTL_109_DATA 0x00030A00
-#define DDRSS_CTL_110_DATA 0x00030A00
-#define DDRSS_CTL_111_DATA 0x00030A00
-#define DDRSS_CTL_112_DATA 0x00030A00
-#define DDRSS_CTL_113_DATA 0x00030A00
+#define DDRSS_CTL_109_DATA 0x00051200
+#define DDRSS_CTL_110_DATA 0x00051200
+#define DDRSS_CTL_111_DATA 0x00051200
+#define DDRSS_CTL_112_DATA 0x00051200
+#define DDRSS_CTL_113_DATA 0x00051200
#define DDRSS_CTL_114_DATA 0x00000000
-#define DDRSS_CTL_115_DATA 0x00005518
-#define DDRSS_CTL_116_DATA 0x00030A00
-#define DDRSS_CTL_117_DATA 0x00030A00
-#define DDRSS_CTL_118_DATA 0x00030A00
-#define DDRSS_CTL_119_DATA 0x00030A00
-#define DDRSS_CTL_120_DATA 0x00030A00
+#define DDRSS_CTL_115_DATA 0x00008DF8
+#define DDRSS_CTL_116_DATA 0x00051200
+#define DDRSS_CTL_117_DATA 0x00051200
+#define DDRSS_CTL_118_DATA 0x00051200
+#define DDRSS_CTL_119_DATA 0x00051200
+#define DDRSS_CTL_120_DATA 0x00051200
#define DDRSS_CTL_121_DATA 0x00000000
-#define DDRSS_CTL_122_DATA 0x00005518
+#define DDRSS_CTL_122_DATA 0x00008DF8
#define DDRSS_CTL_123_DATA 0x00000000
#define DDRSS_CTL_124_DATA 0x00000000
#define DDRSS_CTL_125_DATA 0x00000000
@@ -140,8 +141,8 @@
#define DDRSS_CTL_128_DATA 0x00000000
#define DDRSS_CTL_129_DATA 0x00000000
#define DDRSS_CTL_130_DATA 0x00000000
-#define DDRSS_CTL_131_DATA 0x05030500
-#define DDRSS_CTL_132_DATA 0x00030503
+#define DDRSS_CTL_131_DATA 0x07030500
+#define DDRSS_CTL_132_DATA 0x00030703
#define DDRSS_CTL_133_DATA 0x0A090000
#define DDRSS_CTL_134_DATA 0x0A090701
#define DDRSS_CTL_135_DATA 0x0900000E
@@ -176,23 +177,23 @@
#define DDRSS_CTL_164_DATA 0x000A0000
#define DDRSS_CTL_165_DATA 0x000D0005
#define DDRSS_CTL_166_DATA 0x000D0404
-#define DDRSS_CTL_167_DATA 0x005000A0
-#define DDRSS_CTL_168_DATA 0x060600C8
-#define DDRSS_CTL_169_DATA 0x00A000C8
-#define DDRSS_CTL_170_DATA 0x00C80050
-#define DDRSS_CTL_171_DATA 0x00C80606
+#define DDRSS_CTL_167_DATA 0x0086010B
+#define DDRSS_CTL_168_DATA 0x0A0A014E
+#define DDRSS_CTL_169_DATA 0x010B014E
+#define DDRSS_CTL_170_DATA 0x014E0086
+#define DDRSS_CTL_171_DATA 0x014E0A0A
#define DDRSS_CTL_172_DATA 0x00000000
#define DDRSS_CTL_173_DATA 0x00000000
#define DDRSS_CTL_174_DATA 0x00000000
-#define DDRSS_CTL_175_DATA 0x12A40084
-#define DDRSS_CTL_176_DATA 0x2B0012A4
+#define DDRSS_CTL_175_DATA 0x24C40084
+#define DDRSS_CTL_176_DATA 0x2B0024C4
#define DDRSS_CTL_177_DATA 0x00002B2B
#define DDRSS_CTL_178_DATA 0x36000000
#define DDRSS_CTL_179_DATA 0x27270036
#define DDRSS_CTL_180_DATA 0x0F0F0000
#define DDRSS_CTL_181_DATA 0x00000000
#define DDRSS_CTL_182_DATA 0x00841515
-#define DDRSS_CTL_183_DATA 0x12A412A4
+#define DDRSS_CTL_183_DATA 0x24C424C4
#define DDRSS_CTL_184_DATA 0x2B2B2B00
#define DDRSS_CTL_185_DATA 0x00000000
#define DDRSS_CTL_186_DATA 0x00363600
@@ -270,12 +271,12 @@
#define DDRSS_CTL_258_DATA 0x00320040
#define DDRSS_CTL_259_DATA 0x00020008
#define DDRSS_CTL_260_DATA 0x00400100
-#define DDRSS_CTL_261_DATA 0x00180320
+#define DDRSS_CTL_261_DATA 0x00280536
#define DDRSS_CTL_262_DATA 0x01000200
-#define DDRSS_CTL_263_DATA 0x03200040
-#define DDRSS_CTL_264_DATA 0x00000018
-#define DDRSS_CTL_265_DATA 0x00280003
-#define DDRSS_CTL_266_DATA 0x01000028
+#define DDRSS_CTL_263_DATA 0x05360040
+#define DDRSS_CTL_264_DATA 0x00000028
+#define DDRSS_CTL_265_DATA 0x00430003
+#define DDRSS_CTL_266_DATA 0x01000043
#define DDRSS_CTL_267_DATA 0x00000000
#define DDRSS_CTL_268_DATA 0x01010000
#define DDRSS_CTL_269_DATA 0x00000202
@@ -327,14 +328,14 @@
#define DDRSS_CTL_315_DATA 0x01000101
#define DDRSS_CTL_316_DATA 0x01010001
#define DDRSS_CTL_317_DATA 0x00010101
-#define DDRSS_CTL_318_DATA 0x05050503
-#define DDRSS_CTL_319_DATA 0x08080C0C
-#define DDRSS_CTL_320_DATA 0x00090308
-#define DDRSS_CTL_321_DATA 0x000C030F
-#define DDRSS_CTL_322_DATA 0x000C0311
-#define DDRSS_CTL_323_DATA 0x0C090011
+#define DDRSS_CTL_318_DATA 0x05070703
+#define DDRSS_CTL_319_DATA 0x0A081414
+#define DDRSS_CTL_320_DATA 0x0009030A
+#define DDRSS_CTL_321_DATA 0x080C030F
+#define DDRSS_CTL_322_DATA 0x080C0306
+#define DDRSS_CTL_323_DATA 0x0C090006
#define DDRSS_CTL_324_DATA 0x0100000C
-#define DDRSS_CTL_325_DATA 0x03020301
+#define DDRSS_CTL_325_DATA 0x05020501
#define DDRSS_CTL_326_DATA 0x00000002
#define DDRSS_CTL_327_DATA 0x00000000
#define DDRSS_CTL_328_DATA 0x00010000
@@ -396,7 +397,7 @@
#define DDRSS_CTL_384_DATA 0x00000000
#define DDRSS_CTL_385_DATA 0x00000000
#define DDRSS_CTL_386_DATA 0x00000000
-#define DDRSS_CTL_387_DATA 0x26261B00
+#define DDRSS_CTL_387_DATA 0x2E2E1B00
#define DDRSS_CTL_388_DATA 0x000A0000
#define DDRSS_CTL_389_DATA 0x00000176
#define DDRSS_CTL_390_DATA 0x00000200
@@ -406,22 +407,22 @@
#define DDRSS_CTL_394_DATA 0x00000462
#define DDRSS_CTL_395_DATA 0x00000E9C
#define DDRSS_CTL_396_DATA 0x00000204
-#define DDRSS_CTL_397_DATA 0x00001850
+#define DDRSS_CTL_397_DATA 0x00002890
#define DDRSS_CTL_398_DATA 0x00000200
#define DDRSS_CTL_399_DATA 0x00000200
#define DDRSS_CTL_400_DATA 0x00000200
#define DDRSS_CTL_401_DATA 0x00000200
-#define DDRSS_CTL_402_DATA 0x000048F0
-#define DDRSS_CTL_403_DATA 0x0000F320
-#define DDRSS_CTL_404_DATA 0x00000408
-#define DDRSS_CTL_405_DATA 0x00001850
+#define DDRSS_CTL_402_DATA 0x000079B0
+#define DDRSS_CTL_403_DATA 0x000195A0
+#define DDRSS_CTL_404_DATA 0x0000080E
+#define DDRSS_CTL_405_DATA 0x00002890
#define DDRSS_CTL_406_DATA 0x00000200
#define DDRSS_CTL_407_DATA 0x00000200
#define DDRSS_CTL_408_DATA 0x00000200
#define DDRSS_CTL_409_DATA 0x00000200
-#define DDRSS_CTL_410_DATA 0x000048F0
-#define DDRSS_CTL_411_DATA 0x0000F320
-#define DDRSS_CTL_412_DATA 0x02020408
+#define DDRSS_CTL_410_DATA 0x000079B0
+#define DDRSS_CTL_411_DATA 0x000195A0
+#define DDRSS_CTL_412_DATA 0x0202080E
#define DDRSS_CTL_413_DATA 0x03030202
#define DDRSS_CTL_414_DATA 0x00000022
#define DDRSS_CTL_415_DATA 0x00000000
@@ -432,13 +433,13 @@
#define DDRSS_CTL_420_DATA 0x00000000
#define DDRSS_CTL_421_DATA 0x00030000
#define DDRSS_CTL_422_DATA 0x0006001E
-#define DDRSS_CTL_423_DATA 0x000E0026
-#define DDRSS_CTL_424_DATA 0x000E0026
+#define DDRSS_CTL_423_DATA 0x0013002B
+#define DDRSS_CTL_424_DATA 0x0013002B
#define DDRSS_CTL_425_DATA 0x00000000
#define DDRSS_CTL_426_DATA 0x00000000
#define DDRSS_CTL_427_DATA 0x02000000
#define DDRSS_CTL_428_DATA 0x01000404
-#define DDRSS_CTL_429_DATA 0x01080108
+#define DDRSS_CTL_429_DATA 0x05120512
#define DDRSS_CTL_430_DATA 0x00000105
#define DDRSS_CTL_431_DATA 0x00010101
#define DDRSS_CTL_432_DATA 0x00010101
@@ -447,8 +448,8 @@
#define DDRSS_CTL_435_DATA 0x02000201
#define DDRSS_CTL_436_DATA 0x02010000
#define DDRSS_CTL_437_DATA 0x00000200
-#define DDRSS_CTL_438_DATA 0x10060000
-#define DDRSS_CTL_439_DATA 0x00000110
+#define DDRSS_CTL_438_DATA 0x18060000
+#define DDRSS_CTL_439_DATA 0x00000118
#define DDRSS_CTL_440_DATA 0xFFFFFFFF
#define DDRSS_CTL_441_DATA 0xFFFFFFFF
#define DDRSS_CTL_442_DATA 0x00000000
@@ -504,10 +505,10 @@
#define DDRSS_PI_32_DATA 0x00000000
#define DDRSS_PI_33_DATA 0x01010102
#define DDRSS_PI_34_DATA 0x00000000
-#define DDRSS_PI_35_DATA 0x000000AA
-#define DDRSS_PI_36_DATA 0x00000055
-#define DDRSS_PI_37_DATA 0x000000B5
-#define DDRSS_PI_38_DATA 0x0000004A
+#define DDRSS_PI_35_DATA 0x55555A5A
+#define DDRSS_PI_36_DATA 0x5555A5A5
+#define DDRSS_PI_37_DATA 0x00005A5A
+#define DDRSS_PI_38_DATA 0x0000A5A5
#define DDRSS_PI_39_DATA 0x00000056
#define DDRSS_PI_40_DATA 0x000000A9
#define DDRSS_PI_41_DATA 0x000000A9
@@ -515,12 +516,12 @@
#define DDRSS_PI_43_DATA 0x00000000
#define DDRSS_PI_44_DATA 0x00000000
#define DDRSS_PI_45_DATA 0x000F0F00
-#define DDRSS_PI_46_DATA 0x00000015
+#define DDRSS_PI_46_DATA 0x00000017
#define DDRSS_PI_47_DATA 0x000007D0
#define DDRSS_PI_48_DATA 0x00000300
#define DDRSS_PI_49_DATA 0x00000000
#define DDRSS_PI_50_DATA 0x00000000
-#define DDRSS_PI_51_DATA 0x01000000
+#define DDRSS_PI_51_DATA 0x04080000
#define DDRSS_PI_52_DATA 0x00010101
#define DDRSS_PI_53_DATA 0x00000000
#define DDRSS_PI_54_DATA 0x00030000
@@ -632,18 +633,18 @@
#define DDRSS_PI_160_DATA 0x00000000
#define DDRSS_PI_161_DATA 0x00010000
#define DDRSS_PI_162_DATA 0x00000000
-#define DDRSS_PI_163_DATA 0x10100100
+#define DDRSS_PI_163_DATA 0x1B1B0100
#define DDRSS_PI_164_DATA 0x00000034
-#define DDRSS_PI_165_DATA 0x00000043
-#define DDRSS_PI_166_DATA 0x00020043
+#define DDRSS_PI_165_DATA 0x00000051
+#define DDRSS_PI_166_DATA 0x00020051
#define DDRSS_PI_167_DATA 0x02000200
-#define DDRSS_PI_168_DATA 0x1C080C04
-#define DDRSS_PI_169_DATA 0x000E1C08
+#define DDRSS_PI_168_DATA 0x300C0C04
+#define DDRSS_PI_169_DATA 0x000E300C
#define DDRSS_PI_170_DATA 0x000000BB
-#define DDRSS_PI_171_DATA 0x000000E0
-#define DDRSS_PI_172_DATA 0x00000C28
-#define DDRSS_PI_173_DATA 0x000000E0
-#define DDRSS_PI_174_DATA 0x04000C28
+#define DDRSS_PI_171_DATA 0x00000176
+#define DDRSS_PI_172_DATA 0x00001448
+#define DDRSS_PI_173_DATA 0x00000176
+#define DDRSS_PI_174_DATA 0x04001448
#define DDRSS_PI_175_DATA 0x01010404
#define DDRSS_PI_176_DATA 0x00001501
#define DDRSS_PI_177_DATA 0x00150015
@@ -652,82 +653,82 @@
#define DDRSS_PI_180_DATA 0x00000000
#define DDRSS_PI_181_DATA 0x01010101
#define DDRSS_PI_182_DATA 0x00000101
-#define DDRSS_PI_183_DATA 0x00000000
-#define DDRSS_PI_184_DATA 0x00000000
-#define DDRSS_PI_185_DATA 0x08040000
-#define DDRSS_PI_186_DATA 0x04040208
+#define DDRSS_PI_183_DATA 0x00000100
+#define DDRSS_PI_184_DATA 0x00000100
+#define DDRSS_PI_185_DATA 0x0E040100
+#define DDRSS_PI_186_DATA 0x0808020E
#define DDRSS_PI_187_DATA 0x00040402
#define DDRSS_PI_188_DATA 0x000C8034
-#define DDRSS_PI_189_DATA 0x0014003C
-#define DDRSS_PI_190_DATA 0x0014003C
+#define DDRSS_PI_189_DATA 0x00198041
+#define DDRSS_PI_190_DATA 0x00198041
#define DDRSS_PI_191_DATA 0x01010101
#define DDRSS_PI_192_DATA 0x0002000D
-#define DDRSS_PI_193_DATA 0x000200C8
-#define DDRSS_PI_194_DATA 0x010000C8
+#define DDRSS_PI_193_DATA 0x0002014E
+#define DDRSS_PI_194_DATA 0x0100014E
#define DDRSS_PI_195_DATA 0x000E000E
-#define DDRSS_PI_196_DATA 0x00C90100
-#define DDRSS_PI_197_DATA 0x010000C9
-#define DDRSS_PI_198_DATA 0x00C900C9
+#define DDRSS_PI_196_DATA 0x014F0100
+#define DDRSS_PI_197_DATA 0x0100014F
+#define DDRSS_PI_198_DATA 0x014F014F
#define DDRSS_PI_199_DATA 0x32103200
#define DDRSS_PI_200_DATA 0x01013210
#define DDRSS_PI_201_DATA 0x0A070601
-#define DDRSS_PI_202_DATA 0x0D09070D
-#define DDRSS_PI_203_DATA 0x0D09070D
-#define DDRSS_PI_204_DATA 0x0000C00D
+#define DDRSS_PI_202_DATA 0x140D080D
+#define DDRSS_PI_203_DATA 0x140D0810
+#define DDRSS_PI_204_DATA 0x0000C010
#define DDRSS_PI_205_DATA 0x00C01000
#define DDRSS_PI_206_DATA 0x00C01000
#define DDRSS_PI_207_DATA 0x00021000
-#define DDRSS_PI_208_DATA 0x0016000D
-#define DDRSS_PI_209_DATA 0x001600C8
-#define DDRSS_PI_210_DATA 0x001100C8
+#define DDRSS_PI_208_DATA 0x001C000D
+#define DDRSS_PI_209_DATA 0x001C014E
+#define DDRSS_PI_210_DATA 0x0011014E
#define DDRSS_PI_211_DATA 0x32000056
#define DDRSS_PI_212_DATA 0x00000301
-#define DDRSS_PI_213_DATA 0x00580020
+#define DDRSS_PI_213_DATA 0x005A002A
#define DDRSS_PI_214_DATA 0x03013212
-#define DDRSS_PI_215_DATA 0x00002000
-#define DDRSS_PI_216_DATA 0x32120058
+#define DDRSS_PI_215_DATA 0x00002A00
+#define DDRSS_PI_216_DATA 0x3212005A
#define DDRSS_PI_217_DATA 0x09000301
#define DDRSS_PI_218_DATA 0x04010504
#define DDRSS_PI_219_DATA 0x0400062B
#define DDRSS_PI_220_DATA 0x0A032001
-#define DDRSS_PI_221_DATA 0x1113090A
-#define DDRSS_PI_222_DATA 0x0000120C
-#define DDRSS_PI_223_DATA 0x240062B8
-#define DDRSS_PI_224_DATA 0x0C0C2003
-#define DDRSS_PI_225_DATA 0x1113090A
-#define DDRSS_PI_226_DATA 0x0000120C
-#define DDRSS_PI_227_DATA 0x240062B8
-#define DDRSS_PI_228_DATA 0x0C0C2003
-#define DDRSS_PI_229_DATA 0x0001760A
+#define DDRSS_PI_221_DATA 0x1C1F0B0A
+#define DDRSS_PI_222_DATA 0x00001D12
+#define DDRSS_PI_223_DATA 0x3C00A488
+#define DDRSS_PI_224_DATA 0x13142005
+#define DDRSS_PI_225_DATA 0x1C1F0B0E
+#define DDRSS_PI_226_DATA 0x00001D12
+#define DDRSS_PI_227_DATA 0x3C00A488
+#define DDRSS_PI_228_DATA 0x13142005
+#define DDRSS_PI_229_DATA 0x0001760E
#define DDRSS_PI_230_DATA 0x00000E9C
-#define DDRSS_PI_231_DATA 0x00001850
-#define DDRSS_PI_232_DATA 0x0000F320
-#define DDRSS_PI_233_DATA 0x00001850
-#define DDRSS_PI_234_DATA 0x0000F320
-#define DDRSS_PI_235_DATA 0x00E6000F
-#define DDRSS_PI_236_DATA 0x030300E6
+#define DDRSS_PI_231_DATA 0x00002890
+#define DDRSS_PI_232_DATA 0x000195A0
+#define DDRSS_PI_233_DATA 0x00002890
+#define DDRSS_PI_234_DATA 0x000195A0
+#define DDRSS_PI_235_DATA 0x0180000F
+#define DDRSS_PI_236_DATA 0x03030180
#define DDRSS_PI_237_DATA 0x00271003
#define DDRSS_PI_238_DATA 0x000186A0
#define DDRSS_PI_239_DATA 0x00000005
#define DDRSS_PI_240_DATA 0x00000064
#define DDRSS_PI_241_DATA 0x0000000F
-#define DDRSS_PI_242_DATA 0x00027100
+#define DDRSS_PI_242_DATA 0x000411AB
#define DDRSS_PI_243_DATA 0x000186A0
#define DDRSS_PI_244_DATA 0x00000005
-#define DDRSS_PI_245_DATA 0x00000640
-#define DDRSS_PI_246_DATA 0x000000E6
-#define DDRSS_PI_247_DATA 0x00027100
+#define DDRSS_PI_245_DATA 0x00000A6B
+#define DDRSS_PI_246_DATA 0x00000180
+#define DDRSS_PI_247_DATA 0x000411AB
#define DDRSS_PI_248_DATA 0x000186A0
#define DDRSS_PI_249_DATA 0x00000005
-#define DDRSS_PI_250_DATA 0x00000640
-#define DDRSS_PI_251_DATA 0x010000E6
+#define DDRSS_PI_250_DATA 0x00000A6B
+#define DDRSS_PI_251_DATA 0x01000180
#define DDRSS_PI_252_DATA 0x00320040
#define DDRSS_PI_253_DATA 0x00010008
-#define DDRSS_PI_254_DATA 0x03200040
-#define DDRSS_PI_255_DATA 0x00010018
-#define DDRSS_PI_256_DATA 0x03200040
-#define DDRSS_PI_257_DATA 0x00000318
-#define DDRSS_PI_258_DATA 0x00280028
+#define DDRSS_PI_254_DATA 0x05360040
+#define DDRSS_PI_255_DATA 0x00010028
+#define DDRSS_PI_256_DATA 0x05360040
+#define DDRSS_PI_257_DATA 0x00000328
+#define DDRSS_PI_258_DATA 0x00430043
#define DDRSS_PI_259_DATA 0x00040404
#define DDRSS_PI_260_DATA 0x00000055
#define DDRSS_PI_261_DATA 0x55003C5A
@@ -746,27 +747,27 @@
#define DDRSS_PI_274_DATA 0x00000000
#define DDRSS_PI_275_DATA 0x002B0084
#define DDRSS_PI_276_DATA 0x00150000
-#define DDRSS_PI_277_DATA 0x362B12A4
+#define DDRSS_PI_277_DATA 0x362B24C4
#define DDRSS_PI_278_DATA 0x00150F27
-#define DDRSS_PI_279_DATA 0x362B12A4
+#define DDRSS_PI_279_DATA 0x362B24C4
#define DDRSS_PI_280_DATA 0x00150F27
#define DDRSS_PI_281_DATA 0x002B0084
#define DDRSS_PI_282_DATA 0x00150000
-#define DDRSS_PI_283_DATA 0x362B12A4
+#define DDRSS_PI_283_DATA 0x362B24C4
#define DDRSS_PI_284_DATA 0x00150F27
-#define DDRSS_PI_285_DATA 0x362B12A4
+#define DDRSS_PI_285_DATA 0x362B24C4
#define DDRSS_PI_286_DATA 0x00150F27
#define DDRSS_PI_287_DATA 0x002B0084
#define DDRSS_PI_288_DATA 0x00150000
-#define DDRSS_PI_289_DATA 0x362B12A4
+#define DDRSS_PI_289_DATA 0x362B24C4
#define DDRSS_PI_290_DATA 0x00150F27
-#define DDRSS_PI_291_DATA 0x362B12A4
+#define DDRSS_PI_291_DATA 0x362B24C4
#define DDRSS_PI_292_DATA 0x00150F27
#define DDRSS_PI_293_DATA 0x002B0084
#define DDRSS_PI_294_DATA 0x00150000
-#define DDRSS_PI_295_DATA 0x362B12A4
+#define DDRSS_PI_295_DATA 0x362B24C4
#define DDRSS_PI_296_DATA 0x00150F27
-#define DDRSS_PI_297_DATA 0x362B12A4
+#define DDRSS_PI_297_DATA 0x362B24C4
#define DDRSS_PI_298_DATA 0x00150F27
#define DDRSS_PI_299_DATA 0x00000000
@@ -788,10 +789,10 @@
#define DDRSS_PHY_15_DATA 0x00030066
#define DDRSS_PHY_16_DATA 0x00000000
#define DDRSS_PHY_17_DATA 0x00000301
-#define DDRSS_PHY_18_DATA 0x0000AAAA
-#define DDRSS_PHY_19_DATA 0x00005555
-#define DDRSS_PHY_20_DATA 0x0000B5B5
-#define DDRSS_PHY_21_DATA 0x00004A4A
+#define DDRSS_PHY_18_DATA 0x55555A5A
+#define DDRSS_PHY_19_DATA 0x5555A5A5
+#define DDRSS_PHY_20_DATA 0x00005A5A
+#define DDRSS_PHY_21_DATA 0x0000A5A5
#define DDRSS_PHY_22_DATA 0x00005656
#define DDRSS_PHY_23_DATA 0x0000A9A9
#define DDRSS_PHY_24_DATA 0x0000A9A9
@@ -862,7 +863,7 @@
#define DDRSS_PHY_89_DATA 0x10100303
#define DDRSS_PHY_90_DATA 0x10101010
#define DDRSS_PHY_91_DATA 0x10101010
-#define DDRSS_PHY_92_DATA 0x00011010
+#define DDRSS_PHY_92_DATA 0x00021010
#define DDRSS_PHY_93_DATA 0x00100010
#define DDRSS_PHY_94_DATA 0x00100010
#define DDRSS_PHY_95_DATA 0x00100010
@@ -872,18 +873,18 @@
#define DDRSS_PHY_99_DATA 0x31C06000
#define DDRSS_PHY_100_DATA 0x07AB0340
#define DDRSS_PHY_101_DATA 0x00C0C001
-#define DDRSS_PHY_102_DATA 0x05040001
+#define DDRSS_PHY_102_DATA 0x09080001
#define DDRSS_PHY_103_DATA 0x10001000
-#define DDRSS_PHY_104_DATA 0x0C053E42
-#define DDRSS_PHY_105_DATA 0x0F0C1D01
+#define DDRSS_PHY_104_DATA 0x0C063E42
+#define DDRSS_PHY_105_DATA 0x0F0C2701
#define DDRSS_PHY_106_DATA 0x01000140
-#define DDRSS_PHY_107_DATA 0x0C000420
-#define DDRSS_PHY_108_DATA 0x000001CC
+#define DDRSS_PHY_107_DATA 0x04000420
+#define DDRSS_PHY_108_DATA 0x00000255
#define DDRSS_PHY_109_DATA 0x0A0000D0
#define DDRSS_PHY_110_DATA 0x00030200
#define DDRSS_PHY_111_DATA 0x02800000
#define DDRSS_PHY_112_DATA 0x80800000
-#define DDRSS_PHY_113_DATA 0x00052010
+#define DDRSS_PHY_113_DATA 0x00092010
#define DDRSS_PHY_114_DATA 0x76543210
#define DDRSS_PHY_115_DATA 0x00000008
#define DDRSS_PHY_116_DATA 0x02800280
@@ -900,8 +901,8 @@
#define DDRSS_PHY_127_DATA 0x00A000A0
#define DDRSS_PHY_128_DATA 0x00A000A0
#define DDRSS_PHY_129_DATA 0x00A000A0
-#define DDRSS_PHY_130_DATA 0x011900A0
-#define DDRSS_PHY_131_DATA 0x01A00002
+#define DDRSS_PHY_130_DATA 0x01C400A0
+#define DDRSS_PHY_131_DATA 0x01A00003
#define DDRSS_PHY_132_DATA 0x00000000
#define DDRSS_PHY_133_DATA 0x00000000
#define DDRSS_PHY_134_DATA 0x00080200
@@ -1044,10 +1045,10 @@
#define DDRSS_PHY_271_DATA 0x00030066
#define DDRSS_PHY_272_DATA 0x00000000
#define DDRSS_PHY_273_DATA 0x00000301
-#define DDRSS_PHY_274_DATA 0x0000AAAA
-#define DDRSS_PHY_275_DATA 0x00005555
-#define DDRSS_PHY_276_DATA 0x0000B5B5
-#define DDRSS_PHY_277_DATA 0x00004A4A
+#define DDRSS_PHY_274_DATA 0x55555A5A
+#define DDRSS_PHY_275_DATA 0x5555A5A5
+#define DDRSS_PHY_276_DATA 0x00005A5A
+#define DDRSS_PHY_277_DATA 0x0000A5A5
#define DDRSS_PHY_278_DATA 0x00005656
#define DDRSS_PHY_279_DATA 0x0000A9A9
#define DDRSS_PHY_280_DATA 0x0000A9A9
@@ -1118,7 +1119,7 @@
#define DDRSS_PHY_345_DATA 0x10100303
#define DDRSS_PHY_346_DATA 0x10101010
#define DDRSS_PHY_347_DATA 0x10101010
-#define DDRSS_PHY_348_DATA 0x00011010
+#define DDRSS_PHY_348_DATA 0x00021010
#define DDRSS_PHY_349_DATA 0x00100010
#define DDRSS_PHY_350_DATA 0x00100010
#define DDRSS_PHY_351_DATA 0x00100010
@@ -1128,18 +1129,18 @@
#define DDRSS_PHY_355_DATA 0x31C06000
#define DDRSS_PHY_356_DATA 0x07AB0340
#define DDRSS_PHY_357_DATA 0x00C0C001
-#define DDRSS_PHY_358_DATA 0x05040001
+#define DDRSS_PHY_358_DATA 0x09080001
#define DDRSS_PHY_359_DATA 0x10001000
-#define DDRSS_PHY_360_DATA 0x0C053E42
-#define DDRSS_PHY_361_DATA 0x0F0C1D01
+#define DDRSS_PHY_360_DATA 0x0C063E42
+#define DDRSS_PHY_361_DATA 0x0F0C2701
#define DDRSS_PHY_362_DATA 0x01000140
-#define DDRSS_PHY_363_DATA 0x0C000420
-#define DDRSS_PHY_364_DATA 0x000001CC
+#define DDRSS_PHY_363_DATA 0x04000420
+#define DDRSS_PHY_364_DATA 0x00000255
#define DDRSS_PHY_365_DATA 0x0A0000D0
#define DDRSS_PHY_366_DATA 0x00030200
#define DDRSS_PHY_367_DATA 0x02800000
#define DDRSS_PHY_368_DATA 0x80800000
-#define DDRSS_PHY_369_DATA 0x00052010
+#define DDRSS_PHY_369_DATA 0x00092010
#define DDRSS_PHY_370_DATA 0x76543210
#define DDRSS_PHY_371_DATA 0x00000008
#define DDRSS_PHY_372_DATA 0x02800280
@@ -1156,8 +1157,8 @@
#define DDRSS_PHY_383_DATA 0x00A000A0
#define DDRSS_PHY_384_DATA 0x00A000A0
#define DDRSS_PHY_385_DATA 0x00A000A0
-#define DDRSS_PHY_386_DATA 0x011900A0
-#define DDRSS_PHY_387_DATA 0x01A00002
+#define DDRSS_PHY_386_DATA 0x01C400A0
+#define DDRSS_PHY_387_DATA 0x01A00003
#define DDRSS_PHY_388_DATA 0x00000000
#define DDRSS_PHY_389_DATA 0x00000000
#define DDRSS_PHY_390_DATA 0x00080200
@@ -1300,10 +1301,10 @@
#define DDRSS_PHY_527_DATA 0x00030066
#define DDRSS_PHY_528_DATA 0x00000000
#define DDRSS_PHY_529_DATA 0x00000301
-#define DDRSS_PHY_530_DATA 0x0000AAAA
-#define DDRSS_PHY_531_DATA 0x00005555
-#define DDRSS_PHY_532_DATA 0x0000B5B5
-#define DDRSS_PHY_533_DATA 0x00004A4A
+#define DDRSS_PHY_530_DATA 0x55555A5A
+#define DDRSS_PHY_531_DATA 0x5555A5A5
+#define DDRSS_PHY_532_DATA 0x00005A5A
+#define DDRSS_PHY_533_DATA 0x0000A5A5
#define DDRSS_PHY_534_DATA 0x00005656
#define DDRSS_PHY_535_DATA 0x0000A9A9
#define DDRSS_PHY_536_DATA 0x0000A9A9
@@ -1374,7 +1375,7 @@
#define DDRSS_PHY_601_DATA 0x10100303
#define DDRSS_PHY_602_DATA 0x10101010
#define DDRSS_PHY_603_DATA 0x10101010
-#define DDRSS_PHY_604_DATA 0x00011010
+#define DDRSS_PHY_604_DATA 0x00021010
#define DDRSS_PHY_605_DATA 0x00100010
#define DDRSS_PHY_606_DATA 0x00100010
#define DDRSS_PHY_607_DATA 0x00100010
@@ -1384,18 +1385,18 @@
#define DDRSS_PHY_611_DATA 0x31C06000
#define DDRSS_PHY_612_DATA 0x07AB0340
#define DDRSS_PHY_613_DATA 0x00C0C001
-#define DDRSS_PHY_614_DATA 0x05040001
+#define DDRSS_PHY_614_DATA 0x09080001
#define DDRSS_PHY_615_DATA 0x10001000
-#define DDRSS_PHY_616_DATA 0x0C053E42
-#define DDRSS_PHY_617_DATA 0x0F0C1D01
+#define DDRSS_PHY_616_DATA 0x0C063E42
+#define DDRSS_PHY_617_DATA 0x0F0C2701
#define DDRSS_PHY_618_DATA 0x01000140
-#define DDRSS_PHY_619_DATA 0x0C000420
-#define DDRSS_PHY_620_DATA 0x000001CC
+#define DDRSS_PHY_619_DATA 0x04000420
+#define DDRSS_PHY_620_DATA 0x00000255
#define DDRSS_PHY_621_DATA 0x0A0000D0
#define DDRSS_PHY_622_DATA 0x00030200
#define DDRSS_PHY_623_DATA 0x02800000
#define DDRSS_PHY_624_DATA 0x80800000
-#define DDRSS_PHY_625_DATA 0x00052010
+#define DDRSS_PHY_625_DATA 0x00092010
#define DDRSS_PHY_626_DATA 0x76543210
#define DDRSS_PHY_627_DATA 0x00000008
#define DDRSS_PHY_628_DATA 0x02800280
@@ -1412,8 +1413,8 @@
#define DDRSS_PHY_639_DATA 0x00A000A0
#define DDRSS_PHY_640_DATA 0x00A000A0
#define DDRSS_PHY_641_DATA 0x00A000A0
-#define DDRSS_PHY_642_DATA 0x011900A0
-#define DDRSS_PHY_643_DATA 0x01A00002
+#define DDRSS_PHY_642_DATA 0x01C400A0
+#define DDRSS_PHY_643_DATA 0x01A00003
#define DDRSS_PHY_644_DATA 0x00000000
#define DDRSS_PHY_645_DATA 0x00000000
#define DDRSS_PHY_646_DATA 0x00080200
@@ -1556,10 +1557,10 @@
#define DDRSS_PHY_783_DATA 0x00030066
#define DDRSS_PHY_784_DATA 0x00000000
#define DDRSS_PHY_785_DATA 0x00000301
-#define DDRSS_PHY_786_DATA 0x0000AAAA
-#define DDRSS_PHY_787_DATA 0x00005555
-#define DDRSS_PHY_788_DATA 0x0000B5B5
-#define DDRSS_PHY_789_DATA 0x00004A4A
+#define DDRSS_PHY_786_DATA 0x55555A5A
+#define DDRSS_PHY_787_DATA 0x5555A5A5
+#define DDRSS_PHY_788_DATA 0x00005A5A
+#define DDRSS_PHY_789_DATA 0x0000A5A5
#define DDRSS_PHY_790_DATA 0x00005656
#define DDRSS_PHY_791_DATA 0x0000A9A9
#define DDRSS_PHY_792_DATA 0x0000A9A9
@@ -1630,7 +1631,7 @@
#define DDRSS_PHY_857_DATA 0x10100303
#define DDRSS_PHY_858_DATA 0x10101010
#define DDRSS_PHY_859_DATA 0x10101010
-#define DDRSS_PHY_860_DATA 0x00011010
+#define DDRSS_PHY_860_DATA 0x00021010
#define DDRSS_PHY_861_DATA 0x00100010
#define DDRSS_PHY_862_DATA 0x00100010
#define DDRSS_PHY_863_DATA 0x00100010
@@ -1640,18 +1641,18 @@
#define DDRSS_PHY_867_DATA 0x31C06000
#define DDRSS_PHY_868_DATA 0x07AB0340
#define DDRSS_PHY_869_DATA 0x00C0C001
-#define DDRSS_PHY_870_DATA 0x05040001
+#define DDRSS_PHY_870_DATA 0x09080001
#define DDRSS_PHY_871_DATA 0x10001000
-#define DDRSS_PHY_872_DATA 0x0C053E42
-#define DDRSS_PHY_873_DATA 0x0F0C1D01
+#define DDRSS_PHY_872_DATA 0x0C063E42
+#define DDRSS_PHY_873_DATA 0x0F0C2701
#define DDRSS_PHY_874_DATA 0x01000140
-#define DDRSS_PHY_875_DATA 0x0C000420
-#define DDRSS_PHY_876_DATA 0x000001CC
+#define DDRSS_PHY_875_DATA 0x04000420
+#define DDRSS_PHY_876_DATA 0x00000255
#define DDRSS_PHY_877_DATA 0x0A0000D0
#define DDRSS_PHY_878_DATA 0x00030200
#define DDRSS_PHY_879_DATA 0x02800000
#define DDRSS_PHY_880_DATA 0x80800000
-#define DDRSS_PHY_881_DATA 0x00052010
+#define DDRSS_PHY_881_DATA 0x00092010
#define DDRSS_PHY_882_DATA 0x76543210
#define DDRSS_PHY_883_DATA 0x00000008
#define DDRSS_PHY_884_DATA 0x02800280
@@ -1668,13 +1669,13 @@
#define DDRSS_PHY_895_DATA 0x00A000A0
#define DDRSS_PHY_896_DATA 0x00A000A0
#define DDRSS_PHY_897_DATA 0x00A000A0
-#define DDRSS_PHY_898_DATA 0x011900A0
-#define DDRSS_PHY_899_DATA 0x01A00002
+#define DDRSS_PHY_898_DATA 0x01C400A0
+#define DDRSS_PHY_899_DATA 0x01A00003
#define DDRSS_PHY_900_DATA 0x00000000
#define DDRSS_PHY_901_DATA 0x00000000
#define DDRSS_PHY_902_DATA 0x00080200
#define DDRSS_PHY_903_DATA 0x00000000
-#define DDRSS_PHY_904_DATA 0x20202010
+#define DDRSS_PHY_904_DATA 0x20202000
#define DDRSS_PHY_905_DATA 0x20202020
#define DDRSS_PHY_906_DATA 0xF0F02020
#define DDRSS_PHY_907_DATA 0x00000000
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 0491432..8dc1809 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -6,7 +6,7 @@
/dts-v1/;
#include "k3-j7200-som-p0.dtsi"
-#include "k3-j7200-ddr-evm-lp4-1600.dtsi"
+#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
#include "k3-j721e-ddr.dtsi"
/ {
@@ -79,6 +79,16 @@
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
};
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ u-boot,dm-spl;
+ };
};
&dmsc {
@@ -276,4 +286,11 @@
};
};
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
#include "k3-j7200-common-proc-board-u-boot.dtsi"
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
index 3384ed9..974dae8 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi
@@ -46,7 +46,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
- clock-frequency = <25000000>;
+ clock-frequency = <250000000>;
u-boot,dm-spl;
};
@@ -54,10 +54,24 @@
u-boot,dm-spl;
ringacc@2b800000 {
+ reg = <0x0 0x2b800000 0x0 0x400000>,
+ <0x0 0x2b000000 0x0 0x400000>,
+ <0x0 0x28590000 0x0 0x100>,
+ <0x0 0x2a500000 0x0 0x40000>,
+ <0x0 0x28440000 0x0 0x40000>;
+ reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
u-boot,dm-spl;
};
dma-controller@285c0000 {
+ reg = <0x0 0x285c0000 0x0 0x100>,
+ <0x0 0x284c0000 0x0 0x4000>,
+ <0x0 0x2a800000 0x0 0x40000>,
+ <0x0 0x284a0000 0x0 0x4000>,
+ <0x0 0x2aa00000 0x0 0x40000>,
+ <0x0 0x28400000 0x0 0x2000>;
+ reg-names = "gcfg", "rchan", "rchanrt", "tchan",
+ "tchanrt", "rflow";
u-boot,dm-spl;
};
};
@@ -193,3 +207,11 @@
&mcu_fss0_ospi1_pins_default {
u-boot,dm-spl;
};
+
+&main_r5fss0 {
+ ti,cluster-mode = <0>;
+};
+
+&main_r5fss1 {
+ ti,cluster-mode = <0>;
+};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 4e8422e..0542b2f 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -76,6 +76,16 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
+
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ u-boot,dm-spl;
+ };
};
&cbass_main {
@@ -345,3 +355,11 @@
u-boot,dm-spl;
};
};
+
+&mcu_ringacc {
+ ti,sci = <&dm_tifs>;
+};
+
+&mcu_udmap {
+ ti,sci = <&dm_tifs>;
+};
diff --git a/arch/arm/dts/meson-g12b-gtking-pro-u-boot.dtsi b/arch/arm/dts/meson-g12b-gtking-pro-u-boot.dtsi
new file mode 100644
index 0000000..236f246
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-gtking-pro-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
diff --git a/arch/arm/dts/meson-g12b-gtking-u-boot.dtsi b/arch/arm/dts/meson-g12b-gtking-u-boot.dtsi
new file mode 100644
index 0000000..236f246
--- /dev/null
+++ b/arch/arm/dts/meson-g12b-gtking-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+#include "meson-g12-common-u-boot.dtsi"
diff --git a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi
index fc0fa22..91515b8 100644
--- a/arch/arm/dts/phycore-imx8mm-u-boot.dtsi
+++ b/arch/arm/dts/phycore-imx8mm-u-boot.dtsi
@@ -4,6 +4,8 @@
* Author: Teresa Remmet <t.remmet@phytec.de>
*/
+#include "imx8mm-u-boot.dtsi"
+
/ {
wdt-reboot {
compatible = "wdt-reboot";
@@ -12,41 +14,6 @@
};
};
-&{/soc@0} {
- u-boot,dm-pre-reloc;
- u-boot,dm-spl;
-};
-
-&clk {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
- /delete-property/ assigned-clocks;
- /delete-property/ assigned-clock-parents;
- /delete-property/ assigned-clock-rates;
-};
-
-&osc_24m {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips1 {
- u-boot,dm-spl;
- u-boot,dm-pre-reloc;
-};
-
-&aips2 {
- u-boot,dm-spl;
-};
-
-&aips3 {
- u-boot,dm-spl;
-};
-
-&iomuxc {
- u-boot,dm-spl;
-};
-
&pinctrl_uart3 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi
index 83ff2e7..e367a31 100644
--- a/arch/arm/dts/stm32mp157c-odyssey-som.dtsi
+++ b/arch/arm/dts/stm32mp157c-odyssey-som.dtsi
@@ -258,6 +258,10 @@
status = "okay";
};
+&rng1 {
+ status = "okay";
+};
+
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a>;
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index a4227a3..06da009 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -12,6 +12,7 @@
/ {
aliases {
+ mmc0 = &mmc0;
mmc1 = &mmc2;
};
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
index aae3c62..8ec2e86 100644
--- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts
@@ -2,7 +2,7 @@
/*
* dts file for Xilinx Versal a2197 RevA System Controller
*
- * (C) Copyright 2019 - 2020, Xilinx, Inc.
+ * (C) Copyright 2019 - 2021, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@@ -163,20 +163,20 @@
"", "", "", "", "", /* 70 - 74 */
"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
"SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
- "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
- "", "", "", "", "", /* 85 - 89 */
- "", "", "", "", "", /* 90 - 94 */
- "", "", "", "", "", /* 95 - 99 */
+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "DC_PRSNT", "", /* 80 - 84 */
+ "SYSCTLR_JTAG_S0", "SYSCTLR_JTAG_S1", "SYSCTLR_IIC_MUX0_RESET_B", "SYSCTLR_IIC_MUX1_RESET_B", "", /* 85 - 89 */
+ "SYSCTLR_GPIO0", "SYSCTLR_GPIO1", "SYSCTLR_GPIO2", "SYSCTLR_GPIO3", "SYSCTLR_GPIO4", /* 90 - 94 */
+ "SYSCTLR_GPIO5", "", "", "", "", /* 95 - 99 */
"", "", "", "", "", /* 100 - 104 */
"", "", "", "", "", /* 105 - 109 */
"", "", "", "", "", /* 110 - 114 */
"", "", "", "", "", /* 115 - 119 */
"", "", "", "", "", /* 120 - 124 */
"", "", "", "", "", /* 125 - 129 */
- "", "", "", "", "", /* 130 - 134 */
+ "PMBUS1_INA226_ALERT", "PMBUS2_INA226_ALERT", "", "", "", /* 130 - 134 */
"", "", "", "", "", /* 135 - 139 */
- "", "", "", "", "", /* 140 - 144 */
- "", "", "", "", "", /* 145 - 149 */
+ "PMBUS_ALERT", "", "SYSCTLR_ETH_RESET_B", "SYSCTLR_VCC0V85_TG", "MAX6643_OT_B", /* 140 - 144 */
+ "MAX6643_FANFINAL_B", "MAX6643_FULLSPD", "", "", "", /* 145 - 149 */
"", "", "", "", "", /* 150 - 154 */
"", "", "", "", "", /* 155 - 159 */
"", "", "", "", "", /* 160 - 164 */
@@ -457,6 +457,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
+ i2c-mux-idle-disconnect;
/* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
dc_i2c: i2c@0 { /* DC_I2C */
#address-cells = <1>;
@@ -475,6 +476,7 @@
factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "ref_clk";
+ silabs,skip-recall;
};
/* and connector J212D */
};
@@ -504,6 +506,7 @@
factory-fout = <200000000>;
clock-frequency = <200000000>;
clock-output-names = "si570_ddrdimm1_clk";
+ silabs,skip-recall;
};
};
i2c@4 { /* LPDDR4_SI570_CLK2 */
@@ -559,6 +562,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
+ i2c-mux-idle-disconnect;
i2c@0 { /* SFP0_IIC */
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
index 19e1ebd..213149a 100644
--- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts
@@ -343,9 +343,10 @@
compatible = "silabs,si570";
reg = <0x5d>; /* FIXME addr */
temperature-stability = <50>;
- factory-fout = <156250000>; /* FIXME every chip can be different */
+ factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "REF_CLK"; /* FIXME */
+ silabs,skip-recall;
};
/* Connection via Samtec U20D */
/* Use for storing information about X-PRC card */
diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
index 46ec427..c458110 100644
--- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts
@@ -349,9 +349,10 @@
compatible = "silabs,si570";
reg = <0x5d>; /* FIXME addr */
temperature-stability = <50>;
- factory-fout = <156250000>; /* FIXME every chip can be different */
+ factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "REF_CLK"; /* FIXME */
+ silabs,skip-recall;
};
/* Connection via Samtec U20D */
/* Use for storing information about X-PRC card */
diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
index 6eb58e6..cee7ca1 100644
--- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
+++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts
@@ -339,9 +339,10 @@
compatible = "silabs,si570";
reg = <0x5d>; /* FIXME addr */
temperature-stability = <50>;
- factory-fout = <156250000>; /* FIXME every chip can be different */
+ factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "REF_CLK"; /* FIXME */
+ silabs,skip-recall;
};
/* Connection via Samtec U20D */
/* Use for storing information about X-PRC card */
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts
index 8467dd8..8d9f9ca 100644
--- a/arch/arm/dts/zynqmp-mini-emmc0.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc0.dts
@@ -41,6 +41,46 @@
clock-frequency = <200000000>;
};
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ #power-domain-cells = <1>;
+ method = "smc";
+ u-boot,dm-pre-reloc;
+
+ zynqmp_power: zynqmp-power {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-power";
+ mboxes = <&ipi_mailbox_pmu1 0>,
+ <&ipi_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
+ };
+
+ zynqmp_ipi: zynqmp_ipi {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ xlnx,ipi-id = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipi_mailbox_pmu1: mailbox@ff990400 {
+ u-boot,dm-pre-reloc;
+ reg = <0x0 0xff9905c0 0x0 0x20>,
+ <0x0 0xff9905e0 0x0 0x20>,
+ <0x0 0xff990e80 0x0 0x20>,
+ <0x0 0xff990ea0 0x0 0x20>;
+ reg-names = "local_request_region",
+ "local_response_region",
+ "remote_request_region",
+ "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <4>;
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts
index 2afcc77..5722b76 100644
--- a/arch/arm/dts/zynqmp-mini-emmc1.dts
+++ b/arch/arm/dts/zynqmp-mini-emmc1.dts
@@ -41,6 +41,46 @@
clock-frequency = <200000000>;
};
+ firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ #power-domain-cells = <1>;
+ method = "smc";
+ u-boot,dm-pre-reloc;
+
+ zynqmp_power: zynqmp-power {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-power";
+ mboxes = <&ipi_mailbox_pmu1 0>,
+ <&ipi_mailbox_pmu1 1>;
+ mbox-names = "tx", "rx";
+ };
+ };
+ };
+
+ zynqmp_ipi: zynqmp_ipi {
+ u-boot,dm-pre-reloc;
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ xlnx,ipi-id = <0>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ipi_mailbox_pmu1: mailbox@ff990400 {
+ u-boot,dm-pre-reloc;
+ reg = <0x0 0xff9905c0 0x0 0x20>,
+ <0x0 0xff9905e0 0x0 0x20>,
+ <0x0 0xff990e80 0x0 0x20>,
+ <0x0 0xff990ea0 0x0 0x20>;
+ reg-names = "local_request_region",
+ "local_response_region",
+ "remote_request_region",
+ "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx,ipi-id = <4>;
+ };
+ };
+
amba: amba {
compatible = "simple-bus";
#address-cells = <2>;
diff --git a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
index 4f7824a..1f5201a 100644
--- a/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
+++ b/arch/arm/dts/zynqmp-p-a2197-00-revA.dts
@@ -11,6 +11,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/ {
model = "Versal System Controller on a2197 Processor Char board RevA"; /* Tenzing */
@@ -43,6 +44,18 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
+
+ si5332_1: si5332_1 { /* clk0_sgmii - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <33333333>; /* FIXME */
+ };
+
+ si5332_2: si5332_2 { /* clk1_usb - u142 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
};
&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
@@ -70,6 +83,13 @@
xlnx,mio-bank = <1>;
};
+&psgtr {
+ status = "okay";
+ /* sgmii, usb3 */
+ clocks = <&si5332_1>, <&si5332_2>;
+ clock-names = "ref0", "ref1";
+};
+
&gem0 {
status = "okay";
phy-handle = <&phy0>;
@@ -390,6 +410,7 @@
factory-fout = <33333333>;
clock-frequency = <33333333>;
clock-output-names = "ref_clk";
+ silabs,skip-recall;
};
/* Connection via Samtec J212D */
/* Use for storing information about X-PRC card */
@@ -536,6 +557,8 @@
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
maximum-speed = "super-speed";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
};
&usb1 {
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dts b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
new file mode 100644
index 0000000..cad2d05
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dts
@@ -0,0 +1,373 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KV260 revA Carrier Card
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * SD level shifter:
+ * "A" – A01 board un-modified (NXP)
+ * "Y" – A01 board modified with legacy interposer (Nexperia)
+ * "Z" – A01 board modified with Diode interposer
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/net/ti-dp83867.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-sk-kv260-revA",
+ "xlnx,zynqmp-sk-kv260-revY",
+ "xlnx,zynqmp-sk-kv260-revZ",
+ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+
+ fragment1 {
+ target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ u14: ina260@40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+ };
+ };
+
+ fragment1a {
+ target = <&amba>;
+ __overlay__ {
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
+ si5332_0: si5332_0 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ si5332_1: si5332_1 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ si5332_2: si5332_2 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5332_3: si5332_3 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ si5332_4: si5332_4 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ si5332_5: si5332_5 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+ };
+ };
+
+/* DP/USB 3.0 and SATA */
+ fragment2 {
+ target = <&psgtr>;
+ __overlay__ {
+ status = "okay";
+ /* pcie, usb3, sata */
+ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+ clock-names = "ref0", "ref1", "ref2";
+ };
+ };
+
+ fragment3 {
+ target = <&sata>;
+ __overlay__ {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
+ };
+ };
+
+ fragment4 {
+ target = <&zynqmp_dpsub>;
+ __overlay__ {
+ status = "disabled";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+ };
+ };
+
+ fragment9 {
+ target = <&zynqmp_dpdma>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment10 {
+ target = <&usb0>;
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ usbhub: usb5744 { /* u43 */
+ compatible = "microchip,usb5744";
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+ };
+ };
+ };
+
+ fragment11 {
+ target = <&dwc3_0>;
+ __overlay__ {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+ maximum-speed = "super-speed";
+ };
+ };
+
+ fragment12 {
+ target = <&sdhci1>; /* on CC with tuned parameters */
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ /*
+ * SD 3.0 requires level shifter and this property
+ * should be removed if the board has level shifter and
+ * need to work in UHS mode
+ */
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+ };
+ };
+
+ fragment13 {
+ target = <&gem3>; /* required by spec */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy@1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+ };
+ };
+ };
+
+ fragment14 {
+ target = <&pinctrl0>; /* required by spec */
+ __overlay__ {
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO72", "MIO74";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO71", "MIO73", "MIO75";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66",
+ "MIO67", "MIO68", "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+ };
+ };
+ };
+ fragment15 {
+ target = <&uart1>;
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dts b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
new file mode 100644
index 0000000..6e46f57
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dts
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for KV260 revA Carrier Card
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/net/ti-dp83867.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
+/dts-v1/;
+/plugin/;
+
+/{
+ compatible = "xlnx,zynqmp-sk-kv260-rev1",
+ "xlnx,zynqmp-sk-kv260-revB", "xlnx,zynqmp-sk-kv260-revA",
+ "xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
+
+ fragment1 {
+ target = <&i2c1>; /* I2C_SCK C23/C24 - MIO from SOM */
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ u14: ina260@40 { /* u14 */
+ compatible = "ti,ina260";
+ #io-channel-cells = <1>;
+ label = "ina260-u14";
+ reg = <0x40>;
+ };
+ usbhub: usb5744@2d { /* u43 */
+ compatible = "microchip,usb5744";
+ reg = <0x2d>;
+ reset-gpios = <&gpio 44 GPIO_ACTIVE_HIGH>;
+ };
+ /* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
+ };
+ };
+
+ fragment1a {
+ target = <&amba>;
+ __overlay__ {
+ ina260-u14 {
+ compatible = "iio-hwmon";
+ io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
+ };
+
+ si5332_0: si5332_0 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <125000000>;
+ };
+
+ si5332_1: si5332_1 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ };
+
+ si5332_2: si5332_2 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ si5332_3: si5332_3 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ si5332_4: si5332_4 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ si5332_5: si5332_5 { /* u17 */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+ };
+ };
+
+/* DP/USB 3.0 */
+ fragment2 {
+ target = <&psgtr>;
+ __overlay__ {
+ status = "okay";
+ /* pcie, usb3, sata */
+ clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
+ clock-names = "ref0", "ref1", "ref2";
+ };
+ };
+
+ fragment4 {
+ target = <&zynqmp_dpsub>;
+ __overlay__ {
+ status = "disabled";
+ phy-names = "dp-phy0", "dp-phy1";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
+ };
+ };
+
+ fragment9 {
+ target = <&zynqmp_dpdma>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+
+ fragment10 {
+ target = <&usb0>;
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ };
+ };
+
+ fragment11 {
+ target = <&dwc3_0>;
+ __overlay__ {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
+ maximum-speed = "super-speed";
+ };
+ };
+
+ fragment12 {
+ target = <&sdhci1>; /* on CC with tuned parameters */
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ /*
+ * SD 3.0 requires level shifter and this property
+ * should be removed if the board has level shifter and
+ * need to work in UHS mode
+ */
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio-bank = <1>;
+ clk-phase-sd-hs = <126>, <60>;
+ clk-phase-uhs-sdr25 = <120>, <60>;
+ clk-phase-uhs-ddr50 = <126>, <48>;
+ };
+ };
+
+ fragment13 {
+ target = <&gem3>; /* required by spec */
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
+ reset-delay-us = <2>;
+
+ phy0: ethernet-phy@1 {
+ #phy-cells = <1>;
+ reg = <1>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,dp83867-rxctrl-strap-quirk;
+ };
+ };
+ };
+ };
+
+ fragment14 {
+ target = <&pinctrl0>; /* required by spec */
+ __overlay__ {
+ status = "okay";
+
+ pinctrl_uart1_default: uart1-default {
+ conf {
+ groups = "uart1_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO37";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO36";
+ bias-disable;
+ };
+
+ mux {
+ groups = "uart1_9_grp";
+ function = "uart1";
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ conf {
+ groups = "i2c1_6_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "i2c1_6_grp";
+ function = "i2c1";
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ conf {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux {
+ groups = "gpio0_24_grp", "gpio0_25_grp";
+ function = "gpio0";
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO72", "MIO74";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-bootstrap {
+ pins = "MIO71", "MIO73", "MIO75";
+ bias-disable;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66",
+ "MIO67", "MIO68", "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+ };
+ };
+ };
+ fragment15 {
+ target = <&uart1>;
+ __overlay__ {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ };
+ };
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
new file mode 100644
index 0000000..3f01233
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sm-k26-revA-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP K26/KV260 SD wiring
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci1 { /* on CC - MIO 39 - 51 */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ broken-cd;
+ xlnx,mio-bank = <1>;
+ /* Do not run SD in HS mode from bootloader */
+ sdhci-caps-mask = <0 0x200000>;
+ sdhci-caps = <0 0>;
+ max-frequency = <19000000>;
+};
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
new file mode 100644
index 0000000..e4cf382
--- /dev/null
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP SM-K26 Rev1/B/A";
+ compatible = "xlnx,zynqmp-sm-k26-rev1", "xlnx,zynqmp-sm-k26-revB",
+ "xlnx,zynqmp-sm-k26-revA", "xlnx,zynqmp-sm-k26",
+ "xlnx,zynqmp";
+
+ aliases {
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ spi1 = &spi0;
+ spi2 = &spi1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ nvmem0 = &eeprom;
+ nvmem1 = &eeprom_cc;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory"; /* 4GB */
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ fwuen {
+ label = "fwuen";
+ gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ ds35 {
+ label = "heartbeat";
+ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ ds36 {
+ label = "vbus_det";
+ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ ams {
+ compatible = "iio-hwmon";
+ io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
+ <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>,
+ <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>,
+ <&xilinx_ams 9>, <&xilinx_ams 10>, <&xilinx_ams 11>,
+ <&xilinx_ams 12>, <&xilinx_ams 13>, <&xilinx_ams 14>,
+ <&xilinx_ams 15>, <&xilinx_ams 16>, <&xilinx_ams 17>,
+ <&xilinx_ams 18>, <&xilinx_ams 19>, <&xilinx_ams 20>,
+ <&xilinx_ams 21>, <&xilinx_ams 22>, <&xilinx_ams 23>,
+ <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>,
+ <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>;
+ };
+};
+
+&uart1 { /* MIO36/MIO37 */
+ status = "okay";
+};
+
+&qspi { /* MIO 0-5 - U143 */
+ status = "okay";
+ flash@0 { /* MT25QU512A */
+ compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>; /* 40MHz */
+ partition@0 {
+ label = "Image Selector";
+ reg = <0x0 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@80000 {
+ label = "Image Selector Golden";
+ reg = <0x80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@100000 {
+ label = "Persistent Register";
+ reg = <0x100000 0x20000>; /* 128KB */
+ };
+ partition@120000 {
+ label = "Persistent Register Backup";
+ reg = <0x120000 0x20000>; /* 128KB */
+ };
+ partition@140000 {
+ label = "Open_1";
+ reg = <0x140000 0xC0000>; /* 768KB */
+ };
+ partition@200000 {
+ label = "Image A (FSBL, PMU, ATF, U-Boot)";
+ reg = <0x200000 0xD00000>; /* 13MB */
+ };
+ partition@f00000 {
+ label = "ImgSel Image A Catch";
+ reg = <0xF00000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@f80000 {
+ label = "Image B (FSBL, PMU, ATF, U-Boot)";
+ reg = <0xF80000 0xD00000>; /* 13MB */
+ };
+ partition@1c80000 {
+ label = "ImgSel Image B Catch";
+ reg = <0x1C80000 0x80000>; /* 512KB */
+ read-only;
+ lock;
+ };
+ partition@1d00000 {
+ label = "Open_2";
+ reg = <0x1D00000 0x100000>; /* 1MB */
+ };
+ partition@1e00000 {
+ label = "Recovery Image";
+ reg = <0x1E00000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2000000 {
+ label = "Recovery Image Backup";
+ reg = <0x2000000 0x200000>; /* 2MB */
+ read-only;
+ lock;
+ };
+ partition@2200000 {
+ label = "U-Boot storage variables";
+ reg = <0x2200000 0x20000>; /* 128KB */
+ };
+ partition@2220000 {
+ label = "U-Boot storage variables backup";
+ reg = <0x2220000 0x20000>; /* 128KB */
+ };
+ partition@2240000 {
+ label = "SHA256";
+ reg = <0x2240000 0x10000>; /* 256B but 64KB sector */
+ read-only;
+ lock;
+ };
+ partition@2250000 {
+ label = "User";
+ reg = <0x2250000 0x1db0000>; /* 29.5 MB */
+ };
+ };
+};
+
+&sdhci0 { /* MIO13-23 - 16GB emmc MTFC16GAPALBH-IT - U133A*/
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio-bank = <0>;
+};
+
+&spi1 { /* MIO6, 9-11 */
+ status = "okay";
+ label = "TPM";
+ num-cs = <1>;
+ tpm@0 { /* slm9670 - U144 */
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
+
+ eeprom: eeprom@50 { /* u46 - also at address 0x58 */
+ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
+ reg = <0x50>;
+ /* WP pin EE_WP_EN connected to slg7x644092@68 */
+ };
+
+ eeprom_cc: eeprom@51 { /* required by spec - also at address 0x59 */
+ compatible = "st,24c64", "atmel,24c64"; /* st m24c64 */
+ reg = <0x51>;
+ };
+
+ /* da9062@30 - u170 - also at address 0x31 */
+ /* da9131@33 - u167 */
+ da9131: pmic@33 {
+ compatible = "dlg,da9131";
+ reg = <0x33>;
+ regulators {
+ da9131_buck1: buck1 {
+ regulator-name = "da9131_buck1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ da9131_buck2: buck2 {
+ regulator-name = "da9131_buck2";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ /* da9130@32 - u166 */
+ da9130: pmic@32 {
+ compatible = "dlg,da9130";
+ reg = <0x32>;
+ regulators {
+ da9130_buck1: buck1 {
+ regulator-name = "da9130_buck1";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ /* slg7x644091@70 - u168 NOT accessible due to address conflict with stdp4320 */
+ /*
+ * stdp4320 - u27 FW has below two issues to be fixed in next board revision.
+ * Device acknowledging to addresses 0x5C, 0x5D, 0x70, 0x72, 0x76.
+ * Address conflict with slg7x644091@70 making both the devices NOT accessible.
+ * With the FW fix, stdp4320 should respond to address 0x73 only.
+ */
+ /* slg7x644092@68 - u169 */
+ /* Also connected via JA1C as C23/C24 */
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "QSPI_CLK", "QSPI_DQ1", "QSPI_DQ2", "QSPI_DQ3", "QSPI_DQ0", /* 0 - 4 */
+ "QSPI_CS_B", "SPI_CLK", "LED1", "LED2", "SPI_CS_B", /* 5 - 9 */
+ "SPI_MISO", "SPI_MOSI", "FWUEN", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST", "I2C1_SCL", /* 20 - 24 */
+ "I2C1_SDA", "", "", "", "", /* 25 - 29 */
+ "", "", "", "", "", /* 30 - 34 */
+ "", "", "", "", "", /* 35 - 39 */
+ "", "", "", "", "", /* 40 - 44 */
+ "", "", "", "", "", /* 45 - 49 */
+ "", "", "", "", "", /* 50 - 54 */
+ "", "", "", "", "", /* 55 - 59 */
+ "", "", "", "", "", /* 60 - 64 */
+ "", "", "", "", "", /* 65 - 69 */
+ "", "", "", "", "", /* 70 - 74 */
+ "", "", "", /* 75 - 77, MIO end and EMIO start */
+ "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 - 89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&xilinx_ams {
+ status = "okay";
+};
+
+&ams_ps {
+ status = "okay";
+};
+
+&ams_pl {
+ status = "okay";
+};
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
new file mode 100644
index 0000000..8e91067
--- /dev/null
+++ b/arch/arm/dts/zynqmp-smk-k26-revA-u-boot.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP Z2-VSOM
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/* SD0 only supports 3.3V, no level shifter */
+&sdhci1 { /* FIXME - on CC - MIO 39 - 51 */
+ status = "okay";
+ no-1-8-v;
+ disable-wp;
+ broken-cd;
+ xlnx,mio-bank = <1>;
+ /* Do not run SD in HS mode from bootloader */
+ sdhci-caps-mask = <0 0x200000>;
+ sdhci-caps = <0 0>;
+ max-frequency = <19000000>;
+};
diff --git a/arch/arm/dts/zynqmp-smk-k26-revA.dts b/arch/arm/dts/zynqmp-smk-k26-revA.dts
new file mode 100644
index 0000000..300edc8
--- /dev/null
+++ b/arch/arm/dts/zynqmp-smk-k26-revA.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx ZynqMP SMK-K26 rev1/B/A
+ *
+ * (C) Copyright 2020, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+#include "zynqmp-sm-k26-revA.dts"
+
+/ {
+ model = "ZynqMP SMK-K26 Rev1/B/A";
+ compatible = "xlnx,zynqmp-smk-k26-rev1", "xlnx,zynqmp-smk-k26-revB",
+ "xlnx,zynqmp-smk-k26-revA", "xlnx,zynqmp-smk-k26",
+ "xlnx,zynqmp";
+};
+
+&sdhci0 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index b8c5efb..039a8da 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -11,6 +11,9 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm015-dc1 RevA";
@@ -37,8 +40,33 @@
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
+
+ clock_si5338_0: clk27 { /* u55 SI5338-GM */
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ };
+
+ clock_si5338_2: clk26 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
+ clock_si5338_3: clk150 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <150000000>;
+ };
};
+&psgtr {
+ status = "okay";
+ /* dp, usb3, sata */
+ clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
+ clock-names = "ref1", "ref2", "ref3";
+};
+
&fpd_dma_chan1 {
status = "okay";
};
@@ -75,6 +103,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@0 {
reg = <0>;
};
@@ -82,6 +112,8 @@
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -91,6 +123,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
eeprom: eeprom@55 {
compatible = "atmel,24c64"; /* 24AA64 */
@@ -98,6 +135,216 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_9_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_9_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_36_grp", "gpio0_37_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_8_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_8_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO34";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO35";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_0_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio0_cd_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "sdio0_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio0_wp_0_grp";
+ function = "sdio0_wp";
+ };
+
+ conf-wp {
+ groups = "sdio0_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_38_grp";
+ };
+
+ conf {
+ groups = "gpio0_38_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
&qspi {
status = "okay";
flash@0 {
@@ -142,11 +389,15 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* eMMC */
&sdhci0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
bus-width = <8>;
xlnx,mio-bank = <0>;
};
@@ -158,21 +409,30 @@
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&zynqmp_dpdma {
diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
index 3204456..d6e9248 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts
@@ -11,6 +11,8 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
/ {
model = "ZynqMP zc1751-xm016-dc2 RevA";
@@ -43,10 +45,14 @@
&can0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can0_default>;
};
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&fpd_dma_chan1 {
@@ -85,6 +91,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem2_default>;
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
@@ -101,6 +109,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
tca6416_u26: gpio@20 {
compatible = "ti,tca6416";
@@ -118,6 +131,8 @@
&nand0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand0_default>;
arasan,has-mdma;
nand@0 {
@@ -190,6 +205,285 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_can0_default: can0-default {
+ mux {
+ function = "can0";
+ groups = "can0_9_grp";
+ };
+
+ conf {
+ groups = "can0_9_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO38";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO39";
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_8_grp";
+ };
+
+ conf {
+ groups = "can1_8_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO33";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO32";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_1_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_1_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_6_grp", "gpio0_7_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_6_grp", "gpio0_7_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_10_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_10_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO42";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO43";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_10_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_10_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO41";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO40";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+
+ conf {
+ groups = "usb1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem2_default: gem2-default {
+ mux {
+ function = "ethernet2";
+ groups = "ethernet2_0_grp";
+ };
+
+ conf {
+ groups = "ethernet2_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
+ "MIO63";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
+ "MIO57";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio2";
+ groups = "mdio2_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio2_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_nand0_default: nand0-default {
+ mux {
+ groups = "nand0_0_grp";
+ function = "nand0";
+ };
+
+ conf {
+ groups = "nand0_0_grp";
+ bias-pull-up;
+ };
+
+ mux-ce {
+ groups = "nand0_ce_0_grp";
+ function = "nand0_ce";
+ };
+
+ conf-ce {
+ groups = "nand0_ce_0_grp";
+ bias-pull-up;
+ };
+
+ mux-rb {
+ groups = "nand0_rb_0_grp";
+ function = "nand0_rb";
+ };
+
+ conf-rb {
+ groups = "nand0_rb_0_grp";
+ bias-pull-up;
+ };
+
+ mux-dqs {
+ groups = "nand0_dqs_0_grp";
+ function = "nand0_dqs";
+ };
+
+ conf-dqs {
+ groups = "nand0_dqs_0_grp";
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_spi0_default: spi0-default {
+ mux {
+ groups = "spi0_0_grp";
+ function = "spi0";
+ };
+
+ conf {
+ groups = "spi0_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
+ "spi0_ss_2_grp";
+ function = "spi0_ss";
+ };
+
+ conf-cs {
+ groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
+ "spi0_ss_2_grp";
+ bias-disable;
+ };
+ };
+
+ pinctrl_spi1_default: spi1-default {
+ mux {
+ groups = "spi1_3_grp";
+ function = "spi1";
+ };
+
+ conf {
+ groups = "spi1_3_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
+ "spi1_ss_11_grp";
+ function = "spi1_ss";
+ };
+
+ conf-cs {
+ groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
+ "spi1_ss_11_grp";
+ bias-disable;
+ };
+ };
+};
+
&rtc {
status = "okay";
};
@@ -197,6 +491,9 @@
&spi0 {
status = "okay";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+
spi0_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
@@ -214,6 +511,9 @@
&spi1 {
status = "okay";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
spi1_flash0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
@@ -231,6 +531,8 @@
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_default>;
};
&dwc3_1 {
@@ -240,8 +542,12 @@
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
index 8d8ebea..46b27a0 100644
--- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts
@@ -12,6 +12,9 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+
/ {
model = "ZynqMP zc1751-xm019-dc5 RevA";
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
@@ -73,6 +76,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem1_default>;
phy0: ethernet-phy@0 {
reg = <0>;
};
@@ -84,41 +89,366 @@
&i2c0 {
status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
};
&i2c1 {
status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
+
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_18_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_18_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_74_grp", "gpio0_75_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_74_grp", "gpio0_75_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_19_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_19_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_76_grp", "gpio0_77_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_76_grp", "gpio0_77_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_17_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO71";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_18_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_18_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO73";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO72";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem1_default: gem1-default {
+ mux {
+ function = "ethernet1";
+ groups = "ethernet1_0_grp";
+ };
+
+ conf {
+ groups = "ethernet1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
+ "MIO49";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
+ "MIO43";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio1";
+ groups = "mdio1_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_0_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio0_cd_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "sdio0_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio0_wp_0_grp";
+ function = "sdio0_wp";
+ };
+
+ conf-wp {
+ groups = "sdio0_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_watchdog0_default: watchdog0-default {
+ mux-clk {
+ groups = "swdt0_clk_1_grp";
+ function = "swdt0_clk";
+ };
+
+ conf-clk {
+ groups = "swdt0_clk_1_grp";
+ bias-pull-up;
+ };
+
+ mux-rst {
+ groups = "swdt0_rst_1_grp";
+ function = "swdt0_rst";
+ };
+
+ conf-rst {
+ groups = "swdt0_rst_1_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc0_default: ttc0-default {
+ mux-clk {
+ groups = "ttc0_clk_0_grp";
+ function = "ttc0_clk";
+ };
+
+ conf-clk {
+ groups = "ttc0_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc0_wav_0_grp";
+ function = "ttc0_wav";
+ };
+
+ conf-wav {
+ groups = "ttc0_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc1_default: ttc1-default {
+ mux-clk {
+ groups = "ttc1_clk_0_grp";
+ function = "ttc1_clk";
+ };
+
+ conf-clk {
+ groups = "ttc1_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc1_wav_0_grp";
+ function = "ttc1_wav";
+ };
+
+ conf-wav {
+ groups = "ttc1_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc2_default: ttc2-default {
+ mux-clk {
+ groups = "ttc2_clk_0_grp";
+ function = "ttc2_clk";
+ };
+
+ conf-clk {
+ groups = "ttc2_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc2_wav_0_grp";
+ function = "ttc2_wav";
+ };
+
+ conf-wav {
+ groups = "ttc2_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
+
+ pinctrl_ttc3_default: ttc3-default {
+ mux-clk {
+ groups = "ttc3_clk_0_grp";
+ function = "ttc3_clk";
+ };
+
+ conf-clk {
+ groups = "ttc3_clk_0_grp";
+ bias-pull-up;
+ };
+
+ mux-wav {
+ groups = "ttc3_wav_0_grp";
+ function = "ttc3_wav";
+ };
+
+ conf-wav {
+ groups = "ttc3_wav_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ };
+ };
};
&sdhci0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
no-1-8-v;
+ xlnx,mio-bank = <0>;
};
&ttc0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc0_default>;
};
&ttc1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc1_default>;
};
&ttc2 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc2_default>;
};
&ttc3 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ttc3_default>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
&watchdog0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_watchdog0_default>;
};
diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts
index bbcc69c..b83696c 100644
--- a/arch/arm/dts/zynqmp-zcu100-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu100-revC.dts
@@ -15,6 +15,7 @@
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -185,6 +186,11 @@
&i2c1 {
status = "okay";
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
clock-frequency = <100000>;
i2c-mux@75 { /* u11 */
compatible = "nxp,pca9548";
@@ -262,6 +268,221 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_1_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_1_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_4_grp", "gpio0_5_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_4_grp", "gpio0_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_sdhci0_default: sdhci0-default {
+ mux {
+ groups = "sdio0_3_grp";
+ function = "sdio0";
+ };
+
+ conf {
+ groups = "sdio0_3_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio0_cd_0_grp";
+ function = "sdio0_cd";
+ };
+
+ conf-cd {
+ groups = "sdio0_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_2_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_2_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_spi0_default: spi0-default {
+ mux {
+ groups = "spi0_3_grp";
+ function = "spi0";
+ };
+
+ conf {
+ groups = "spi0_3_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi0_ss_9_grp";
+ function = "spi0_ss";
+ };
+
+ conf-cs {
+ groups = "spi0_ss_9_grp";
+ bias-disable;
+ };
+
+ };
+
+ pinctrl_spi1_default: spi1-default {
+ mux {
+ groups = "spi1_0_grp";
+ function = "spi1";
+ };
+
+ conf {
+ groups = "spi1_0_grp";
+ bias-disable;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-cs {
+ groups = "spi1_ss_0_grp";
+ function = "spi1_ss";
+ };
+
+ conf-cs {
+ groups = "spi1_ss_0_grp";
+ bias-disable;
+ };
+
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_0_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO3";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO2";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_0_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO1";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO0";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb1_default: usb1-default {
+ mux {
+ groups = "usb1_0_grp";
+ function = "usb1";
+ };
+
+ conf {
+ groups = "usb1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO64", "MIO65", "MIO67";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
+ "MIO72", "MIO73", "MIO74", "MIO75";
+ bias-disable;
+ };
+ };
+};
+
&psgtr {
status = "okay";
/* usb3, dps */
@@ -278,12 +499,16 @@
status = "okay";
no-1-8-v;
disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0_default>;
xlnx,mio-bank = <0>;
};
&sdhci1 {
status = "okay";
bus-width = <0x4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <0>;
non-removable;
disable-wp;
@@ -304,16 +529,22 @@
status = "okay";
label = "LS-SPI0";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
};
&spi1 { /* High Speed connector */
status = "okay";
label = "HS-SPI1";
num-cs = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
bluetooth {
compatible = "ti,wl1831-st";
enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
@@ -322,28 +553,37 @@
&uart1 {
status = "okay";
-
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
status = "okay";
dr_mode = "peripheral";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
maximum-speed = "super-speed";
};
/* ULPI SMSC USB3320 */
&usb1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1_default>;
};
&dwc3_1 {
status = "okay";
dr_mode = "host";
+ phy-names = "usb3-phy";
+ phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
maximum-speed = "super-speed";
};
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 9323b8d..ec61b70 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -154,6 +155,8 @@
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
@@ -196,6 +199,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@21 {
reg = <21>;
ti,rx-internal-delay = <0x8>;
@@ -208,6 +213,8 @@
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -217,6 +224,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
@@ -476,6 +488,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */
@@ -658,6 +675,269 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux-sw {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf-sw {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22", "MIO23";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&pcie {
status = "okay";
};
@@ -726,26 +1006,36 @@
* removed for supporting UHS mode
*/
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts
index a95bd49..c25ac9a 100644
--- a/arch/arm/dts/zynqmp-zcu104-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revA.dts
@@ -12,6 +12,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -62,6 +63,8 @@
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
@@ -104,6 +107,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -124,6 +129,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */
@@ -215,6 +225,204 @@
};
};
+&pinctrl0 {
+ status = "okay";
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+};
+
&qspi {
status = "okay";
flash@0 {
@@ -274,27 +482,37 @@
&sdhci1 {
status = "okay";
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
disable-wp;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts
index 8f30a28..ce9d8fb 100644
--- a/arch/arm/dts/zynqmp-zcu104-revC.dts
+++ b/arch/arm/dts/zynqmp-zcu104-revC.dts
@@ -12,6 +12,7 @@
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -68,6 +69,8 @@
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
@@ -110,6 +113,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -130,6 +135,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
@@ -228,6 +238,204 @@
};
};
+&pinctrl0 {
+ status = "okay";
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ drive-strength = <12>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+};
+
&qspi {
status = "okay";
flash@0 {
@@ -287,27 +495,37 @@
&sdhci1 {
status = "okay";
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
disable-wp;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
maximum-speed = "super-speed";
};
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 971f76f..ae20e58 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -154,6 +155,8 @@
&can1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
};
&dcc {
@@ -208,6 +211,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -219,6 +224,8 @@
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -228,6 +235,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u97: gpio@20 {
compatible = "ti,tca6416";
@@ -486,6 +498,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
/* PL i2c via PCA9306 - u45 */
i2c-mux@74 { /* u34 */
@@ -678,6 +695,269 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO23", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
@@ -741,26 +1021,36 @@
* This property should be removed for supporting UHS mode
*/
no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
xlnx,mio-bank = <1>;
};
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
&uart1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
};
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&watchdog0 {
diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts
index 9e47008..d564f74 100644
--- a/arch/arm/dts/zynqmp-zcu111-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu111-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -170,6 +171,8 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
@@ -181,6 +184,8 @@
&gpio {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
};
&gpu {
@@ -190,6 +195,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u22: gpio@20 {
compatible = "ti,tca6416";
@@ -365,6 +375,11 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
i2c-mux@74 { /* u26 */
compatible = "nxp,pca9548";
@@ -554,6 +569,210 @@
};
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO23", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
&psgtr {
status = "okay";
/* nc, sata, usb3, dp */
@@ -607,12 +826,14 @@
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
phy-names = "sata-phy";
- phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
disable-wp;
/*
* This property should be removed for supporting UHS mode
@@ -623,12 +844,23 @@
&uart0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
};
/* ULPI SMSC USB3320 */
&usb0 {
status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+};
+
+&dwc3_0 {
+ status = "okay";
dr_mode = "host";
+ snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
&zynqmp_dpdma {
diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts
index 0e114cd..880281d 100644
--- a/arch/arm/dts/zynqmp-zcu208-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu208-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -221,6 +222,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u15: gpio@20 { /* u15 */
compatible = "ti,tca6416";
@@ -382,12 +388,18 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
i2c-mux@74 {
compatible = "nxp,pca9548"; /* u20 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
i2c_eeprom: i2c@0 {
#address-cells = <1>;
@@ -423,27 +435,27 @@
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
};
};
@@ -504,6 +516,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
i2c@0 {
#address-cells = <1>;
@@ -565,6 +578,63 @@
/* MSP430 */
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
&qspi {
status = "okay";
is-dual = <1>;
@@ -601,6 +671,7 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
@@ -628,4 +699,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts
index 2302b07..f899226 100644
--- a/arch/arm/dts/zynqmp-zcu216-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu216-revA.dts
@@ -13,6 +13,7 @@
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
/ {
@@ -232,6 +233,11 @@
&i2c0 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
tca6416_u15: gpio@20 { /* u15 */
compatible = "ti,tca6416";
@@ -393,12 +399,18 @@
&i2c1 {
status = "okay";
clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
i2c-mux@74 {
compatible = "nxp,pca9548"; /* u20 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
i2c_eeprom: i2c@0 {
#address-cells = <1>;
@@ -434,27 +446,27 @@
si5341_2: out@2 {
/* refclk2 for PS-GT, used for USB3 */
reg = <2>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_3: out@3 {
/* refclk3 for PS-GT, used for SATA */
reg = <3>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_5: out@5 {
/* refclk5 PL CLK100 */
reg = <5>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_6: out@6 {
/* refclk6 PL CLK125 */
reg = <6>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
si5341_9: out@9 {
/* refclk9 used for PS_REF_CLK 33.3 MHz */
reg = <9>;
- always-on; /* assigned-clocks does not enable, so do it here */
+ always-on;
};
};
};
@@ -515,6 +527,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <0x75>;
+ i2c-mux-idle-disconnect;
/* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
i2c@0 {
#address-cells = <1>;
@@ -576,6 +589,63 @@
/* MSP430 */
};
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+};
+
&qspi {
status = "okay";
is-dual = <1>;
@@ -605,6 +675,7 @@
ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
};
@@ -632,4 +703,6 @@
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
};
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index fba655f..2aff1c4 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -91,7 +91,7 @@
#include <asm-generic/global_data.h>
-#ifdef __clang__
+#if defined(__clang__) || defined(CONFIG_LTO)
#define DECLARE_GLOBAL_DATA_PTR
#define gd get_gd()
@@ -122,8 +122,10 @@
{
#ifdef CONFIG_ARM64
__asm__ volatile("ldr x18, %0\n" : : "m"(gd_ptr));
-#else
+#elif __ARM_ARCH >= 7
__asm__ volatile("ldr r9, %0\n" : : "m"(gd_ptr));
+#else
+ __asm__ volatile("mov r9, %0\n" : : "r"(gd_ptr));
#endif
}
diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h
index 64e5582..c7b00be 100644
--- a/arch/arm/include/asm/secure.h
+++ b/arch/arm/include/asm/secure.h
@@ -4,8 +4,8 @@
#include <config.h>
#include <asm/global_data.h>
-#define __secure __attribute__ ((section ("._secure.text")))
-#define __secure_data __attribute__ ((section ("._secure.data")))
+#define __secure __section("._secure.text")
+#define __secure_data __section("._secure.data")
#ifndef __ASSEMBLY__
@@ -22,7 +22,7 @@
*/
#define DECLARE_SECURE_SVC(_name, _id, _fn) \
static const secure_svc_tbl_t __secure_svc_ ## _name \
- __attribute__((used, section("._secure_svc_tbl_entries"))) \
+ __used __section("._secure_svc_tbl_entries") \
= { \
.id = _id, \
.func = _fn }
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 3a4e902..e0e2d7e 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -235,7 +235,7 @@
int (*parse)(const struct tag *);
};
-#define __tag __attribute__((unused, __section__(".taglist")))
+#define __tag __attribute__((unused)) __section(".taglist")
#define __tagtable(tag, fn) \
static struct tagtable __tagtable_##fn __tag = { tag, fn }
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 27b12e7..7f66332 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -45,6 +45,8 @@
obj-y += bdinfo.o
obj-y += sections.o
+CFLAGS_REMOVE_sections.o := $(LTO_CFLAGS)
+
obj-y += stack.o
ifdef CONFIG_CPU_V7M
obj-y += interrupts_m.o
@@ -64,6 +66,7 @@
obj-y += cache.o
obj-$(CONFIG_SYS_ARM_CACHE_CP15) += cache-cp15.o
+CFLAGS_REMOVE_cache-cp15.o := $(LTO_CFLAGS)
obj-y += psci-dt.o
diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c
index 3bb2d84..8578797 100644
--- a/arch/arm/lib/sections.c
+++ b/arch/arm/lib/sections.c
@@ -2,6 +2,7 @@
/*
* Copyright 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
+#include <linux/compiler.h>
/**
* These two symbols are declared in a C file so that the linker
@@ -18,18 +19,18 @@
* aliasing warnings.
*/
-char __bss_start[0] __attribute__((section(".__bss_start")));
-char __bss_end[0] __attribute__((section(".__bss_end")));
-char __image_copy_start[0] __attribute__((section(".__image_copy_start")));
-char __image_copy_end[0] __attribute__((section(".__image_copy_end")));
-char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start")));
-char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end")));
-char __secure_start[0] __attribute__((section(".__secure_start")));
-char __secure_end[0] __attribute__((section(".__secure_end")));
-char __secure_stack_start[0] __attribute__((section(".__secure_stack_start")));
-char __secure_stack_end[0] __attribute__((section(".__secure_stack_end")));
-char __efi_runtime_start[0] __attribute__((section(".__efi_runtime_start")));
-char __efi_runtime_stop[0] __attribute__((section(".__efi_runtime_stop")));
-char __efi_runtime_rel_start[0] __attribute__((section(".__efi_runtime_rel_start")));
-char __efi_runtime_rel_stop[0] __attribute__((section(".__efi_runtime_rel_stop")));
-char _end[0] __attribute__((section(".__end")));
+char __bss_start[0] __section(".__bss_start");
+char __bss_end[0] __section(".__bss_end");
+char __image_copy_start[0] __section(".__image_copy_start");
+char __image_copy_end[0] __section(".__image_copy_end");
+char __rel_dyn_start[0] __section(".__rel_dyn_start");
+char __rel_dyn_end[0] __section(".__rel_dyn_end");
+char __secure_start[0] __section(".__secure_start");
+char __secure_end[0] __section(".__secure_end");
+char __secure_stack_start[0] __section(".__secure_stack_start");
+char __secure_stack_end[0] __section(".__secure_stack_end");
+char __efi_runtime_start[0] __section(".__efi_runtime_start");
+char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
+char __efi_runtime_rel_start[0] __section(".__efi_runtime_rel_start");
+char __efi_runtime_rel_stop[0] __section(".__efi_runtime_rel_stop");
+char _end[0] __section(".__end");
diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c
index b2b54f2..8e2bdf3 100644
--- a/arch/arm/lib/spl.c
+++ b/arch/arm/lib/spl.c
@@ -26,7 +26,7 @@
* WARNING: This is going away very soon. Don't use it and don't submit
* pafches that rely on it. The global_data area is set up in crt0.S.
*/
-gd_t gdata __attribute__ ((section(".data")));
+gd_t gdata __section(".data");
#endif
/*
diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c
index 477ea94..45e9c45 100644
--- a/arch/arm/lib/zimage.c
+++ b/arch/arm/lib/zimage.c
@@ -25,18 +25,16 @@
if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC &&
zi->zi_magic != BAREBOX_IMAGE_MAGIC) {
-#ifndef CONFIG_SPL_FRAMEWORK
- puts("zimage: Bad magic!\n");
-#endif
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ puts("zimage: Bad magic!\n");
return 1;
}
*start = zi->zi_start;
*end = zi->zi_end;
-#ifndef CONFIG_SPL_FRAMEWORK
- printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n",
- image, *start, *end);
-#endif
+ if (!IS_ENABLED(CONFIG_SPL_BUILD))
+ printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n",
+ image, *start, *end);
return 0;
}
diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c
index 156150c..8d53799 100644
--- a/arch/arm/mach-at91/spl.c
+++ b/arch/arm/mach-at91/spl.c
@@ -26,7 +26,7 @@
#include <asm/arch/sama5_boot.h>
struct {
u32 r4;
-} bootrom_stash __attribute__((section(".data")));
+} bootrom_stash __section(".data");
u32 spl_boot_device(void)
{
diff --git a/arch/arm/mach-exynos/spl_boot.c b/arch/arm/mach-exynos/spl_boot.c
index 27f0dac..72244988 100644
--- a/arch/arm/mach-exynos/spl_boot.c
+++ b/arch/arm/mach-exynos/spl_boot.c
@@ -279,7 +279,7 @@
*/
static void setup_global_data(gd_t *gdp)
{
- gd = gdp;
+ set_gd(gdp);
memzero((void *)gd, sizeof(gd_t));
gd->flags |= GD_FLG_RELOC;
gd->baudrate = CONFIG_BAUDRATE;
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index c27fb24..0669363 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -28,6 +28,12 @@
prompt "NXP i.MX8M board select"
optional
+config TARGET_IMX8MQ_CM
+ bool "Ronetix iMX8MQ-CM SoM"
+ select BINMAN
+ select IMX8MQ
+ select IMX8M_LPDDR4
+
config TARGET_IMX8MQ_EVK
bool "imx8mq_evk"
select IMX8MQ
@@ -45,6 +51,24 @@
select SUPPORT_SPL
select IMX8M_LPDDR4
+config TARGET_IMX8MM_ICORE_MX8MM
+ bool "Engicam i.Core MX8M Mini SOM"
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
+ help
+ i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM.
+
+ i.Core MX8M Mini EDIMM2.2:
+ * EDIMM2.2 is a Form Factor Capacitive Evaluation Board.
+ * i.Core MX8M Mini needs to mount on top of EDIMM2.2 for
+ creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.
+
+ i.Core MX8M Mini C.TOUCH 2.0
+ * C.TOUCH 2.0 is a general purpose Carrier board.
+ * i.Core MX8M Mini needs to mount on top of this Carrier board
+ for creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
+
config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
select IMX8MM
@@ -106,19 +130,29 @@
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+
+config TARGET_IMX8MM_CL_IOT_GATE
+ bool "CompuLab iot-gate-imx8"
+ select BINMAN
+ select IMX8MM
+ select SUPPORT_SPL
+ select IMX8M_LPDDR4
endchoice
+source "board/beacon/imx8mm/Kconfig"
+source "board/beacon/imx8mn/Kconfig"
+source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
+source "board/engicam/imx8mm/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
source "board/freescale/imx8mn_evk/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
-source "board/technexion/pico-imx8mq/Kconfig"
-source "board/toradex/verdin-imx8mm/Kconfig"
-source "board/beacon/imx8mm/Kconfig"
-source "board/beacon/imx8mn/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
+source "board/ronetix/imx8mq-cm/Kconfig"
+source "board/technexion/pico-imx8mq/Kconfig"
+source "board/toradex/verdin-imx8mm/Kconfig"
endif
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 029d06f..65d476e 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -846,7 +846,7 @@
return 0;
}
-int imx_eqos_txclk_set_rate(u32 rate)
+int imx_eqos_txclk_set_rate(ulong rate)
{
u32 val;
u32 eqos_post_div;
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 36abb2e..0c44022 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -537,7 +537,7 @@
ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
((uintptr_t)&boot) ^ QUERY_BT_DEV);
- gd = pgd;
+ set_gd(pgd);
if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n");
diff --git a/arch/arm/mach-imx/mkimage_fit_atf.sh b/arch/arm/mach-imx/mkimage_fit_atf.sh
index fe12b7b..2a17968 100755
--- a/arch/arm/mach-imx/mkimage_fit_atf.sh
+++ b/arch/arm/mach-imx/mkimage_fit_atf.sh
@@ -16,7 +16,7 @@
exit 0
else
echo "$BL31 size: " >&2
- ls -lct $BL31 | awk '{print $5}' >&2
+ stat -c %s $BL31 >&2
fi
BL32="tee.bin"
@@ -26,7 +26,7 @@
else
echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
echo "$BL32 size: " >&2
- ls -lct $BL32 | awk '{print $5}' >&2
+ stat -c %s $BL32 >&2
fi
BL33="u-boot-nodtb.bin"
@@ -36,13 +36,13 @@
exit 0
else
echo "u-boot-nodtb.bin size: " >&2
- ls -lct u-boot-nodtb.bin | awk '{print $5}' >&2
+ stat -c %s u-boot-nodtb.bin >&2
fi
for dtname in $*
do
echo "$dtname size: " >&2
- ls -lct $dtname | awk '{print $5}' >&2
+ stat -c %s $dtname >&2
done
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index c8146c3..5c6fe42 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -35,6 +35,15 @@
select SUPPORT_SPL
imply CMD_DM
+config TARGET_IMX7_CM
+ bool "Ronetix iMX7-CM"
+ select BOARD_LATE_INIT
+ select DM
+ select DM_THERMAL
+ select MX7D
+ select SUPPORT_SPL
+ imply CMD_DM
+
config TARGET_MEERKAT96
bool "NovTech Meerkat96 board"
select BOARD_LATE_INIT
@@ -82,6 +91,7 @@
default "mx7"
source "board/compulab/cl-som-imx7/Kconfig"
+source "board/ronetix/imx7-cm/Kconfig"
source "board/freescale/mx7dsabresd/Kconfig"
source "board/novtech/meerkat96/Kconfig"
source "board/technexion/pico-imx7d/Kconfig"
diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index 9f4d959..d2085da 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -45,7 +45,7 @@
ret = g_rom_api->download_image(buf, offset, byte,
((uintptr_t)buf) ^ offset ^ byte);
- gd = pgd;
+ set_gd(pgd);
if (ret == ROM_API_OKAY)
return count;
@@ -73,7 +73,7 @@
ret |= g_rom_api->query_boot_infor(QUERY_IMG_OFF, &image_offset,
((uintptr_t)&image_offset) ^ QUERY_IMG_OFF);
- gd = pgd;
+ set_gd(pgd);
if (ret != ROM_API_OKAY) {
puts("ROMAPI: Failure query boot infor pagesize/offset\n");
@@ -94,7 +94,7 @@
size = ALIGN(sizeof(struct image_header), pagesize);
ret = g_rom_api->download_image((u8 *)header, offset, size,
((uintptr_t)header) ^ offset ^ size);
- gd = pgd;
+ set_gd(pgd);
if (ret != ROM_API_OKAY) {
printf("ROMAPI: download failure offset 0x%x size 0x%x\n",
@@ -180,7 +180,7 @@
ret = g_rom_api->query_boot_infor(QUERY_PAGE_SZ, &pagesize,
((uintptr_t)&pagesize) ^ QUERY_PAGE_SZ);
- gd = pgd;
+ set_gd(pgd);
if (ret != ROM_API_OKAY)
puts("failure at query_boot_info\n");
@@ -192,7 +192,7 @@
for (i = 0; i < 640; i++) {
ret = g_rom_api->download_image(p, 0, pg,
((uintptr_t)p) ^ pg);
- gd = pgd;
+ set_gd(pgd);
if (ret != ROM_API_OKAY) {
puts("Steam(USB) download failure\n");
@@ -213,7 +213,7 @@
if (p - pfit < sizeof(struct fdt_header)) {
ret = g_rom_api->download_image(p, 0, pg, ((uintptr_t)p) ^ pg);
- gd = pgd;
+ set_gd(pgd);
if (ret != ROM_API_OKAY) {
puts("Steam(USB) download failure\n");
@@ -237,7 +237,7 @@
ret = g_rom_api->download_image(p, 0, imagesize,
((uintptr_t)p) ^ imagesize);
- gd = pgd;
+ set_gd(pgd);
p += imagesize;
@@ -280,7 +280,7 @@
ret = g_rom_api->query_boot_infor(QUERY_BT_DEV, &boot,
((uintptr_t)&boot) ^ QUERY_BT_DEV);
- gd = pgd;
+ set_gd(pgd);
if (ret != ROM_API_OKAY) {
puts("ROMAPI: failure at query_boot_info\n");
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index c7d1861..fa8d134 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -10,6 +10,9 @@
config SOC_K3_J721E
bool "TI's K3 based J721E SoC Family Support"
+config SOC_K3_AM642
+ bool "TI's K3 based AM642 SoC Family Support"
+
endchoice
config SYS_SOC
@@ -19,16 +22,18 @@
hex
default 0x80000 if SOC_K3_AM6
default 0x100000 if SOC_K3_J721E
+ default 0x1c0000 if SOC_K3_AM642
help
- Describes the total size of the MCU MSRAM. This doesn't
- specify the total size of SPL as ROM can use some part
- of this RAM. Once ROM gives control to SPL then this
- complete size can be usable.
+ Describes the total size of the MCU or OCMC MSRAM present on
+ the SoC in use. This doesn't specify the total size of SPL as
+ ROM can use some part of this RAM. Once ROM gives control to
+ SPL then this complete size can be usable.
config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
hex
default 0x58000 if SOC_K3_AM6
default 0xc0000 if SOC_K3_J721E
+ default 0x180000 if SOC_K3_AM642
help
Describes the maximum size of the image that ROM can download
from any boot media.
@@ -51,6 +56,7 @@
hex
default 0x41c7fbfc if SOC_K3_AM6
default 0x41cffbfc if SOC_K3_J721E
+ default 0x701bebfc if SOC_K3_AM642
help
Address at which ROM stores the value which determines if SPL
is booted up by primary boot media or secondary boot media.
@@ -141,6 +147,25 @@
Enabling this will try to start Cortex-A (typically with ATF)
after SPL from R5.
+config K3_ATF_LOAD_ADDR
+ hex "Load address of ATF image"
+ default 0x70000000
+ help
+ The load address for the ATF image. This value defaults to 0x70000000
+ if not provided in the board defconfig file.
+
+config K3_DM_FW
+ bool "Separate DM firmware image"
+ depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
+ default y
+ help
+ Enabling this will indicate that the system has separate DM
+ and TIFS firmware images in place, instead of a single SYSFW
+ firmware. Due to DM being executed on the same core as R5 SPL
+ bootloader, it makes RM and PM services not being available
+ during R5 SPL execution time.
+
source "board/ti/am65x/Kconfig"
+source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"
endif
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 7572f56..47cf7b6 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -4,7 +4,8 @@
# Lokesh Vutla <lokeshvutla@ti.com>
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
+obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
new file mode 100644
index 0000000..579dbac
--- /dev/null
+++ b/arch/arm/mach-k3/am642_init.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AM642: SoC specific initialization
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ * Dave Gerlach <d-gerlach@ti.com>
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sysfw-loader.h>
+#include <asm/arch/sys_proto.h>
+#include "common.h"
+#include <asm/arch/sys_proto.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <dm/pinctrl.h>
+#include <mmc.h>
+#include <dm/root.h>
+
+#if defined(CONFIG_SPL_BUILD)
+
+static void ctrl_mmr_unlock(void)
+{
+ /* Unlock all PADCFG_MMR1 module registers */
+ mmr_unlock(PADCFG_MMR1_BASE, 1);
+
+ /* Unlock all CTRL_MMR0 module registers */
+ mmr_unlock(CTRL_MMR0_BASE, 0);
+ mmr_unlock(CTRL_MMR0_BASE, 1);
+ mmr_unlock(CTRL_MMR0_BASE, 2);
+ mmr_unlock(CTRL_MMR0_BASE, 3);
+ mmr_unlock(CTRL_MMR0_BASE, 5);
+ mmr_unlock(CTRL_MMR0_BASE, 6);
+}
+
+/*
+ * This uninitialized global variable would normal end up in the .bss section,
+ * but the .bss is cleared between writing and reading this variable, so move
+ * it to the .data section.
+ */
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(".data");
+
+static void store_boot_info_from_rom(void)
+{
+ bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
+ memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
+ sizeof(struct rom_extended_boot_data));
+}
+
+#if defined(CONFIG_K3_LOAD_SYSFW) && CONFIG_IS_ENABLED(DM_MMC)
+void k3_mmc_stop_clock(void)
+{
+ if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+ struct mmc *mmc = find_mmc_device(0);
+
+ if (!mmc)
+ return;
+
+ mmc->saved_clock = mmc->clock;
+ mmc_set_clock(mmc, 0, true);
+ }
+}
+
+void k3_mmc_restart_clock(void)
+{
+ if (spl_boot_device() == BOOT_DEVICE_MMC1) {
+ struct mmc *mmc = find_mmc_device(0);
+
+ if (!mmc)
+ return;
+
+ mmc_set_clock(mmc, mmc->saved_clock, false);
+ }
+}
+#else
+void k3_mmc_stop_clock(void) {}
+void k3_mmc_restart_clock(void) {}
+#endif
+
+#ifdef CONFIG_SPL_OF_LIST
+void do_dt_magic(void)
+{
+ int ret, rescan;
+
+ if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
+ do_board_detect();
+
+ /*
+ * Board detection has been done.
+ * Let us see if another dtb wouldn't be a better match
+ * for our board
+ */
+ if (IS_ENABLED(CONFIG_CPU_V7R)) {
+ ret = fdtdec_resetup(&rescan);
+ if (!ret && rescan) {
+ dm_uninit();
+ dm_init_and_scan(true);
+ }
+ }
+}
+#endif
+
+#if CONFIG_IS_ENABLED(USB_STORAGE)
+static int fixup_usb_boot(const void *fdt_blob)
+{
+ int ret = 0;
+
+ switch (spl_boot_device()) {
+ case BOOT_DEVICE_USB:
+ /*
+ * If the boot mode is host, fixup the dr_mode to host
+ * before cdns3 bind takes place
+ */
+ ret = fdt_find_and_setprop((void *)fdt_blob,
+ "/bus@f4000/cdns-usb@f900000/usb@f400000",
+ "dr_mode", "host", 5, 0);
+ if (ret)
+ printf("%s: fdt_find_and_setprop() failed:%d\n",
+ __func__, ret);
+ fallthrough;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+int fdtdec_board_setup(const void *fdt_blob)
+{
+ /* Can use the pointer from the function parameters */
+ return fixup_usb_boot(fdt_blob);
+}
+#endif
+
+void board_init_f(ulong dummy)
+{
+#if defined(CONFIG_K3_LOAD_SYSFW)
+ struct udevice *dev;
+ int ret;
+#endif
+
+#if defined(CONFIG_CPU_V7R)
+ setup_k3_mpu_regions();
+#endif
+
+ /*
+ * Cannot delay this further as there is a chance that
+ * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
+ */
+ store_boot_info_from_rom();
+
+ ctrl_mmr_unlock();
+
+ /* Init DM early */
+ spl_early_init();
+
+ preloader_console_init();
+
+ do_dt_magic();
+
+#if defined(CONFIG_K3_LOAD_SYSFW)
+ /*
+ * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue
+ * regardless of the result of pinctrl. Do this without probing the
+ * device, but instead by searching the device that would request the
+ * given sequence number if probed. The UART will be used by the system
+ * firmware (SYSFW) image for various purposes and SYSFW depends on us
+ * to initialize its pin settings.
+ */
+ ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev);
+ if (!ret)
+ pinctrl_select_state(dev, "default");
+
+ /*
+ * Load, start up, and configure system controller firmware.
+ * This will determine whether or not ROM has already loaded
+ * system firmware and if so, will only perform needed config
+ * and not attempt to load firmware again.
+ */
+ k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata), k3_mmc_stop_clock,
+ k3_mmc_restart_clock);
+#endif
+
+ /* Output System Firmware version info */
+ k3_sysfw_print_ver();
+
+#if defined(CONFIG_K3_AM64_DDRSS)
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret)
+ panic("DRAM init failed: %d\n", ret);
+#endif
+}
+
+u32 spl_boot_mode(const u32 boot_device)
+{
+ switch (boot_device) {
+ case BOOT_DEVICE_MMC1:
+ return MMCSD_MODE_EMMCBOOT;
+
+ case BOOT_DEVICE_MMC2:
+ return MMCSD_MODE_FS;
+
+ default:
+ return MMCSD_MODE_RAW;
+ }
+}
+
+static u32 __get_backup_bootmedia(u32 main_devstat)
+{
+ u32 bkup_bootmode =
+ (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT;
+ u32 bkup_bootmode_cfg =
+ (main_devstat & MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT;
+
+ switch (bkup_bootmode) {
+ case BACKUP_BOOT_DEVICE_UART:
+ return BOOT_DEVICE_UART;
+
+ case BACKUP_BOOT_DEVICE_DFU:
+ if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+
+
+ case BACKUP_BOOT_DEVICE_ETHERNET:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BACKUP_BOOT_DEVICE_MMC:
+ if (bkup_bootmode_cfg)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BACKUP_BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BACKUP_BOOT_DEVICE_I2C:
+ return BOOT_DEVICE_I2C;
+ };
+
+ return BOOT_DEVICE_RAM;
+}
+
+static u32 __get_primary_bootmedia(u32 main_devstat)
+{
+ u32 bootmode = (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
+ u32 bootmode_cfg =
+ (main_devstat & MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT;
+
+ switch (bootmode) {
+ case BOOT_DEVICE_OSPI:
+ fallthrough;
+ case BOOT_DEVICE_QSPI:
+ fallthrough;
+ case BOOT_DEVICE_XSPI:
+ fallthrough;
+ case BOOT_DEVICE_SPI:
+ return BOOT_DEVICE_SPI;
+
+ case BOOT_DEVICE_ETHERNET_RGMII:
+ fallthrough;
+ case BOOT_DEVICE_ETHERNET_RMII:
+ return BOOT_DEVICE_ETHERNET;
+
+ case BOOT_DEVICE_EMMC:
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_MMC:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT)
+ return BOOT_DEVICE_MMC2;
+ return BOOT_DEVICE_MMC1;
+
+ case BOOT_DEVICE_DFU:
+ if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
+ MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
+ return BOOT_DEVICE_USB;
+ return BOOT_DEVICE_DFU;
+
+ case BOOT_DEVICE_NOBOOT:
+ return BOOT_DEVICE_RAM;
+ }
+
+ return bootmode;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 devstat = readl(CTRLMMR_MAIN_DEVSTAT);
+
+ if (bootindex == K3_PRIMARY_BOOTMODE)
+ return __get_primary_bootmedia(devstat);
+ else
+ return __get_backup_bootmedia(devstat);
+}
+#endif
+
+#if defined(CONFIG_SYS_K3_SPL_ATF)
+
+#define AM64X_DEV_RTI8 127
+#define AM64X_DEV_RTI9 128
+#define AM64X_DEV_R5FSS0_CORE0 121
+#define AM64X_DEV_R5FSS0_CORE1 122
+
+void release_resources_for_core_shutdown(void)
+{
+ struct ti_sci_handle *ti_sci = get_ti_sci_handle();
+ struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
+ struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
+ int ret;
+ u32 i;
+
+ const u32 put_device_ids[] = {
+ AM64X_DEV_RTI9,
+ AM64X_DEV_RTI8,
+ };
+
+ /* Iterate through list of devices to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
+ u32 id = put_device_ids[i];
+
+ ret = dev_ops->put_device(ti_sci, id);
+ if (ret)
+ panic("Failed to put device %u (%d)\n", id, ret);
+ }
+
+ const u32 put_core_ids[] = {
+ AM64X_DEV_R5FSS0_CORE1,
+ AM64X_DEV_R5FSS0_CORE0, /* Handle CPU0 after CPU1 */
+ };
+
+ /* Iterate through list of cores to put (shutdown) */
+ for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
+ u32 id = put_core_ids[i];
+
+ /*
+ * Queue up the core shutdown request. Note that this call
+ * needs to be followed up by an actual invocation of an WFE
+ * or WFI CPU instruction.
+ */
+ ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
+ if (ret)
+ panic("Failed sending core %u shutdown message (%d)\n",
+ id, ret);
+ }
+}
+#endif
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c
index d78d2b8..425b3f9 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am6_init.c
@@ -77,7 +77,7 @@
* but the .bss is cleared between writing and reading this variable, so move
* it to the .data section.
*/
-u32 bootindex __attribute__((section(".data")));
+u32 bootindex __section(".data");
static void store_boot_index_from_rom(void)
{
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index a0da3df..94242e1 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -180,3 +180,44 @@
#endif /* CONFIG_TARGET_J7200_A72_EVM */
#endif /* CONFIG_SOC_K3_J721E */
+
+#ifdef CONFIG_SOC_K3_AM642
+/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
+#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
+
+/* ToDo: Add 64bit IO */
+struct mm_region am64_mem_map[NR_MMU_REGIONS] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x500000000UL,
+ .phys = 0x500000000UL,
+ .size = 0x400000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = am64_mem_map;
+#endif /* CONFIG_SOC_K3_AM642 */
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 9191f68..ab6d9bd 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -28,6 +28,27 @@
#include <elf.h>
#include <soc.h>
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
+enum {
+ IMAGE_ID_ATF,
+ IMAGE_ID_OPTEE,
+ IMAGE_ID_SPL,
+ IMAGE_ID_DM_FW,
+ IMAGE_AMT,
+};
+
+#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
+static const char *image_os_match[IMAGE_AMT] = {
+ "arm-trusted-firmware",
+ "tee",
+ "U-Boot",
+ "DM",
+};
+#endif
+
+static struct image_info fit_image_info[IMAGE_AMT];
+#endif
+
struct ti_sci_handle *get_ti_sci_handle(void)
{
struct udevice *dev;
@@ -107,7 +128,7 @@
}
#endif
-#ifdef CONFIG_SYS_K3_SPL_ATF
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
void init_env(void)
{
@@ -181,7 +202,7 @@
typedef void __noreturn (*image_entry_noargs_t)(void);
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
u32 loadaddr = 0;
- int ret, size;
+ int ret, size = 0;
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
@@ -191,16 +212,22 @@
panic("rproc failed to be initialized (%d)\n", ret);
init_env();
- start_non_linux_remote_cores();
- size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
- &loadaddr);
+ if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+ start_non_linux_remote_cores();
+ size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
+ &loadaddr);
+ }
/*
* It is assumed that remoteproc device 1 is the corresponding
* Cortex-A core which runs ATF. Make sure DT reflects the same.
*/
- ret = rproc_load(1, spl_image->entry_point, 0x200);
+ if (!fit_image_info[IMAGE_ID_ATF].image_start)
+ fit_image_info[IMAGE_ID_ATF].image_start =
+ spl_image->entry_point;
+
+ ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
if (ret)
panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
@@ -210,7 +237,8 @@
ret = rproc_start(1);
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
- if (!(size > 0 && valid_elf_image(loadaddr))) {
+ if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
+ !(size > 0 && valid_elf_image(loadaddr))) {
debug("Shutting down...\n");
release_resources_for_core_shutdown();
@@ -218,13 +246,54 @@
asm volatile("wfe");
}
+ if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
+ loadaddr = load_elf_image_phdr(loadaddr);
+ } else {
+ loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
+ if (valid_elf_image(loadaddr))
+ loadaddr = load_elf_image_phdr(loadaddr);
+ }
+
- image_entry_noargs_t image_entry =
- (image_entry_noargs_t)load_elf_image_phdr(loadaddr);
+ debug("%s: jumping to address %x\n", __func__, loadaddr);
+
+ image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
image_entry();
}
#endif
+#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
+{
+#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
+ int len;
+ int i;
+ const char *os;
+ u32 addr;
+
+ os = fdt_getprop(fit, node, "os", &len);
+ addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
+
+ debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
+ addr, *p_size, os);
+
+ for (i = 0; i < IMAGE_AMT; i++) {
+ if (!strcmp(os, image_os_match[i])) {
+ fit_image_info[i].image_start = addr;
+ fit_image_info[i].image_len = *p_size;
+ debug("%s: matched image for ID %d\n", __func__, i);
+ break;
+ }
+ }
+#endif
+
+#if IS_ENABLED(CONFIG_TI_SECURE_DEVICE)
+ ti_secure_image_post_process(p_image, p_size);
+#endif
+}
+#endif
+
#if defined(CONFIG_OF_LIBFDT)
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
{
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index a6dbc78..f421ed1 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -28,3 +28,4 @@
void spl_enable_dcache(void);
void mmr_unlock(phys_addr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
+void ti_secure_image_post_process(void **p_image, size_t *p_size);
diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index 41fee2b..da458bc 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -49,6 +49,10 @@
ifdef CONFIG_ARM64
+ifeq ($(CONFIG_SOC_K3_J721E),)
+export DM := /dev/null
+endif
+
ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
SPL_ITS := u-boot-spl-k3_HS.its
$(SPL_ITS): export IS_HS=1
@@ -67,6 +71,7 @@
quiet_cmd_k3_mkits = MKITS $@
cmd_k3_mkits = \
$(srctree)/tools/k3_fit_atf.sh \
+ $(CONFIG_K3_ATF_LOAD_ADDR) \
$(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@
$(SPL_ITS): FORCE
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
new file mode 100644
index 0000000..9638343
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: AM64 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#ifndef __ASM_ARCH_AM64_HARDWARE_H
+#define __ASM_ARCH_AM64_HARDWARE_H
+
+#define CTRL_MMR0_BASE 0x43000000
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+
+#define PADCFG_MMR1_BASE 0xf0000
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
+
+/* After the cfg mask and shifts have been applied */
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
+
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT 1
+#define MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK 0x02
+
+#define MAIN_DEVSTAT_BACKUP_USB_MODE_MASK 0x01
+
+/*
+ * The CTRL_MMR and PADCFG_MMR memory space is divided into several
+ * equally-spaced partitions, so defining the partition size allows us to
+ * determine register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE 0x4000
+
+/*
+ * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0 0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
+#define CTRLMMR_LOCK_KICK1 0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+
+#define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
+
+/* Use Last 2K as Scratch pad */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800
+
+#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h
new file mode 100644
index 0000000..607b09c
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am64_spl.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ */
+#ifndef _ASM_ARCH_AM64_SPL_H_
+#define _ASM_ARCH_AM64_SPL_H_
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_RAM 0x00
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_ETHERNET 0x04
+#define BOOT_DEVICE_ETHERNET_RGMII 0x04
+#define BOOT_DEVICE_ETHERNET_RMII 0x05
+#define BOOT_DEVICE_I2C 0x06
+#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_MMC 0x08
+#define BOOT_DEVICE_EMMC 0x09
+
+#define BOOT_DEVICE_USB 0x2A
+#define BOOT_DEVICE_DFU 0x0A
+#define BOOT_DEVICE_GPMC_NOR 0x0C
+#define BOOT_DEVICE_PCIE 0x0D
+#define BOOT_DEVICE_XSPI 0x0E
+
+#define BOOT_DEVICE_NOBOOT 0x0F
+
+#define BOOT_DEVICE_MMC2 0x08
+#define BOOT_DEVICE_MMC1 0x09
+/* INVALID */
+#define BOOT_DEVICE_MMC2_2 0x1F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_DFU 0x01
+#define BACKUP_BOOT_DEVICE_UART 0x03
+#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
+#define BACKUP_BOOT_DEVICE_MMC 0x05
+#define BACKUP_BOOT_DEVICE_SPI 0x06
+#define BACKUP_BOOT_DEVICE_I2C 0x07
+#define BACKUP_BOOT_DEVICE_USB 0x09
+
+#define K3_PRIMARY_BOOTMODE 0x0
+
+#endif
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 02b3df0..8725e7d 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -14,6 +14,10 @@
#include "j721e_hardware.h"
#endif
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_hardware.h"
+#endif
+
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_ID 0x43000014
#define JTAG_ID_VARIANT_SHIFT 28
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index a26c8ec..ef1c3fb 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -13,4 +13,8 @@
#ifdef CONFIG_SOC_K3_J721E
#include "j721e_spl.h"
#endif
+
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_spl.h"
+#endif
#endif /* _ASM_ARCH_SPL_H_ */
diff --git a/arch/arm/mach-k3/j7200/Makefile b/arch/arm/mach-k3/j7200/Makefile
new file mode 100644
index 0000000..ff9abd7
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c
new file mode 100644
index 0000000..93c0670
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -0,0 +1,547 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific clock platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ "osc_19_2_mhz",
+ "osc_20_mhz",
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ "osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi0_dqs_out",
+ "fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+ "wkup_fref_clksel_out0",
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "postdiv2_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_gpio0_clksel_out0_parents[] = {
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk",
+ "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+ "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out14_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out4_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const wkup_obsclk_mux_out0_parents[] = {
+ "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+ NULL,
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_1_hsdivout1_clk",
+ "hsdiv4_16fft_mcu_1_hsdivout2_clk",
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+ "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout2_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout3_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+ "gluelogic_hfosc0_clkout",
+ "board_0_wkup_lf_clkin_out",
+};
+
+static const char * const main_pll4_xref_sel_out0_parents[] = {
+ "main_pll_hfosc_sel_out4",
+ "board_0_ext_refclk1_out",
+};
+
+static const char * const mcu_clkout_mux_out0_parents[] = {
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+ "main_pll_hfosc_sel_out0",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const mcu_obsclk_outmux_out0_parents[] = {
+ "mcu_obsclk_div_out0",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const clkout_mux_out0_parents[] = {
+ "hsdiv4_16fft_main_3_hsdivout0_clk",
+ "hsdiv4_16fft_main_3_hsdivout0_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out1_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const gtc_clk_mux_out0_parents[] = {
+ "hsdiv4_16fft_main_3_hsdivout1_clk",
+ "postdiv2_16fft_main_0_hsdivout6_clk",
+ "board_0_mcu_cpts0_rft_clk_out",
+ "board_0_cpts0_rft_clk_out",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+ "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const obsclk1_mux_out0_parents[] = {
+ NULL,
+ "hsdiv0_16fft_main_8_hsdivout0_clk",
+ NULL,
+ NULL,
+};
+
+static const char * const gpmc_fclk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout3_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const audio_refclko_mux_out0_parents[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv2_16fft_main_4_hsdivout2_clk",
+ NULL,
+ NULL,
+ NULL,
+};
+
+static const char * const audio_refclko_mux_out1_parents[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv2_16fft_main_4_hsdivout2_clk",
+ NULL,
+ NULL,
+ NULL,
+};
+
+static const char * const obsclk0_mux_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+ "hsdiv4_16fft_main_1_hsdivout0_clk",
+ "hsdiv4_16fft_main_2_hsdivout0_clk",
+ "hsdiv4_16fft_main_3_hsdivout0_clk",
+ "hsdiv2_16fft_main_4_hsdivout0_clk",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv0_16fft_main_12_hsdivout0_clk",
+ "obsclk1_mux_out0",
+ "hsdiv1_16fft_main_14_hsdivout0_clk",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+ "board_0_wkup_lf_clkin_out",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+ "board_0_hfosc1_clk_out",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const struct clk_data clk_list[] = {
+ CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
+ CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+ CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+ CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+ CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
+ CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
+ CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+ CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
+ CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
+ CLK_FIXED_RATE("j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32550, 0),
+ CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
+ CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
+ CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
+ CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
+ CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
+ CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
+ CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
+ CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
+ CLK_DIV("postdiv2_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666),
+ CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
+ CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
+ CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
+ CLK_MUX("wkup_gpio0_clksel_out0", wkup_gpio0_clksel_out0_parents, 4, 0x43008070, 0, 2, 0),
+ CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
+ CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
+ CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("board_0_wkup_lf_clkin_out", 0, 0),
+ CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
+ CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
+ CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
+ CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
+ CLK_DIV("postdiv2_16fft_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
+ CLK_DIV("postdiv2_16fft_main_1_hsdivout7_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0),
+ CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0),
+ CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
+ CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
+ CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
+ CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
+ CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfracf_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
+ CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
+ CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0),
+ CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
+ CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0),
+ CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
+ CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
+ CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
+ CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0),
+ CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
+ CLK_DIV("hsdiv2_16fft_main_4_hsdivout0_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0),
+ CLK_DIV("hsdiv2_16fft_main_4_hsdivout2_clk", "pllfracf_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0),
+ CLK_MUX("audio_refclko_mux_out0", audio_refclko_mux_out0_parents, 32, 0x1082e0, 0, 5, 0),
+ CLK_MUX("audio_refclko_mux_out1", audio_refclko_mux_out1_parents, 32, 0x1082e4, 0, 5, 0),
+ CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0),
+ CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(8, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(8, 5, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+ DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(30, 1, "board_0_hfosc1_clk_out"),
+ DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+ DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+ DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+ DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(30, 10, "board_0_hfosc1_clk_out"),
+ DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(30, 12, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+ DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 1, "gtc_clk_mux_out0"),
+ DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+ DEV_CLK(61, 3, "postdiv2_16fft_main_0_hsdivout6_clk"),
+ DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
+ DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
+ DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
+ DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+ DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(91, 3, "emmcsd_refclk_sel_out0"),
+ DEV_CLK(91, 4, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(91, 5, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(91, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(91, 7, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(92, 0, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(92, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(92, 2, "emmcsd_refclk_sel_out1"),
+ DEV_CLK(92, 3, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(92, 4, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(92, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(92, 6, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(102, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(102, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(102, 5, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(102, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
+ DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+ DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(103, 4, "board_0_mcu_ospi0_dqs_out"),
+ DEV_CLK(103, 5, "mcu_ospi0_iclk_sel_out0"),
+ DEV_CLK(103, 6, "board_0_mcu_ospi0_dqs_out"),
+ DEV_CLK(103, 7, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(103, 8, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(104, 0, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+ DEV_CLK(104, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(113, 0, "wkup_gpio0_clksel_out0"),
+ DEV_CLK(113, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(113, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(113, 3, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk"),
+ DEV_CLK(113, 4, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+ DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(146, 2, "usart_programmable_clock_divider_out0"),
+ DEV_CLK(146, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(149, 2, "mcuusart_clk_sel_out0"),
+ DEV_CLK(149, 3, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+ DEV_CLK(149, 4, "postdiv2_16fft_main_1_hsdivout5_clk"),
+ DEV_CLK(149, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(154, 0, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+ DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(157, 5, "osbclk0_div_out0"),
+ DEV_CLK(157, 7, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+ DEV_CLK(157, 14, "mcu_obsclk_outmux_out0"),
+ DEV_CLK(157, 15, "mcu_obsclk_div_out0"),
+ DEV_CLK(157, 16, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(157, 35, "clkout_mux_out0"),
+ DEV_CLK(157, 36, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+ DEV_CLK(157, 37, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+ DEV_CLK(157, 38, "osbclk0_div_out0"),
+ DEV_CLK(157, 57, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
+ DEV_CLK(157, 65, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 69, "mcu_clkout_mux_out0"),
+ DEV_CLK(157, 70, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(157, 71, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(157, 77, "audio_refclko_mux_out1"),
+ DEV_CLK(157, 106, "hsdiv2_16fft_main_4_hsdivout2_clk"),
+ DEV_CLK(157, 110, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 114, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"),
+ DEV_CLK(157, 123, "mshsi2c_wkup_0_porscl"),
+ DEV_CLK(157, 131, "audio_refclko_mux_out0"),
+ DEV_CLK(157, 160, "hsdiv2_16fft_main_4_hsdivout2_clk"),
+ DEV_CLK(157, 169, "board_0_mcu_i2c0_scl_out"),
+ DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"),
+ DEV_CLK(157, 184, "gpmc_fclk_sel_out0"),
+ DEV_CLK(157, 187, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 192, "osbclk0_div_out0"),
+ DEV_CLK(157, 193, "hsdiv4_16fft_main_0_hsdivout0_clk"),
+ DEV_CLK(157, 194, "hsdiv4_16fft_main_1_hsdivout0_clk"),
+ DEV_CLK(157, 195, "hsdiv4_16fft_main_2_hsdivout0_clk"),
+ DEV_CLK(157, 196, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+ DEV_CLK(157, 197, "hsdiv2_16fft_main_4_hsdivout0_clk"),
+ DEV_CLK(157, 205, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+ DEV_CLK(157, 206, "obsclk1_mux_out0"),
+ DEV_CLK(157, 207, "hsdiv1_16fft_main_14_hsdivout0_clk"),
+ DEV_CLK(157, 220, "j7vc_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+ DEV_CLK(157, 221, "board_0_wkup_lf_clkin_out"),
+ DEV_CLK(157, 222, "hsdiv4_16fft_main_0_hsdivout0_clk"),
+ DEV_CLK(157, 223, "board_0_hfosc1_clk_out"),
+ DEV_CLK(157, 224, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(197, 0, "board_0_wkup_i2c0_scl_out"),
+ DEV_CLK(197, 1, "wkup_i2c0_mcupll_bypass_clksel_out0"),
+ DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"),
+ DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(288, 12, "usb0_refclk_sel_out0"),
+ DEV_CLK(288, 13, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(288, 14, "board_0_hfosc1_clk_out"),
+ DEV_CLK(288, 15, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(288, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+};
+
+const struct ti_k3_clk_platdata j7200_clk_platdata = {
+ .clk_list = clk_list,
+ .clk_list_cnt = 108,
+ .soc_dev_clk_data = soc_dev_clk_data,
+ .soc_dev_clk_data_cnt = 127,
+};
diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c
new file mode 100644
index 0000000..c68bcc5
--- /dev/null
+++ b/arch/arm/mach-k3/j7200/dev-data.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J7200 specific device platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+ [0] = PSC(0, 0x00400000),
+ [1] = PSC(1, 0x42000000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+ [0] = PSC_PD(0, &soc_psc_list[0], NULL),
+ [1] = PSC_PD(2, &soc_psc_list[0], &soc_pd_list[5]),
+ [2] = PSC_PD(14, &soc_psc_list[0], NULL),
+ [3] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[2]),
+ [4] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[2]),
+ [5] = PSC_PD(0, &soc_psc_list[1], NULL),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+ [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [1] = PSC_LPSC(9, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[14]),
+ [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]),
+ [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [5] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [6] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [7] = PSC_LPSC(54, &soc_psc_list[0], &soc_pd_list[1], NULL),
+ [8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[2], NULL),
+ [9] = PSC_LPSC(79, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
+ [10] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
+ [11] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[4], &soc_lpsc_list[8]),
+ [12] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[5], NULL),
+ [13] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[5], NULL),
+ [14] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[5], NULL),
+ [15] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[5], NULL),
+ [16] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[5], NULL),
+};
+
+static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(30, &soc_lpsc_list[0]),
+ PSC_DEV(61, &soc_lpsc_list[1]),
+ PSC_DEV(90, &soc_lpsc_list[2]),
+ PSC_DEV(8, &soc_lpsc_list[3]),
+ PSC_DEV(288, &soc_lpsc_list[4]),
+ PSC_DEV(92, &soc_lpsc_list[5]),
+ PSC_DEV(91, &soc_lpsc_list[6]),
+ PSC_DEV(146, &soc_lpsc_list[7]),
+ PSC_DEV(4, &soc_lpsc_list[8]),
+ PSC_DEV(4, &soc_lpsc_list[9]),
+ PSC_DEV(202, &soc_lpsc_list[10]),
+ PSC_DEV(203, &soc_lpsc_list[11]),
+ PSC_DEV(102, &soc_lpsc_list[12]),
+ PSC_DEV(103, &soc_lpsc_list[12]),
+ PSC_DEV(104, &soc_lpsc_list[12]),
+ PSC_DEV(154, &soc_lpsc_list[12]),
+ PSC_DEV(149, &soc_lpsc_list[12]),
+ PSC_DEV(113, &soc_lpsc_list[13]),
+ PSC_DEV(197, &soc_lpsc_list[13]),
+ PSC_DEV(103, &soc_lpsc_list[14]),
+ PSC_DEV(104, &soc_lpsc_list[15]),
+ PSC_DEV(102, &soc_lpsc_list[16]),
+};
+
+const struct ti_k3_pd_platdata j7200_pd_platdata = {
+ .psc = soc_psc_list,
+ .pd = soc_pd_list,
+ .lpsc = soc_lpsc_list,
+ .devs = soc_dev_list,
+ .num_psc = 2,
+ .num_pd = 6,
+ .num_lpsc = 17,
+ .num_devs = 22,
+};
diff --git a/arch/arm/mach-k3/j721e/Makefile b/arch/arm/mach-k3/j721e/Makefile
new file mode 100644
index 0000000..ff9abd7
--- /dev/null
+++ b/arch/arm/mach-k3/j721e/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+obj-y += clk-data.o
+obj-y += dev-data.o
diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c
new file mode 100644
index 0000000..953ac45
--- /dev/null
+++ b/arch/arm/mach-k3/j721e/clk-data.c
@@ -0,0 +1,781 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E specific clock platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-clk.h"
+
+static const char * const gluelogic_hfosc0_clkout_parents[] = {
+ "osc_19_2_mhz",
+ "osc_20_mhz",
+ "osc_24_mhz",
+ "osc_25_mhz",
+ "osc_26_mhz",
+ "osc_27_mhz",
+};
+
+static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi0_dqs_out",
+ "fss_mcu_0_ospi_0_ospi_oclk_clk",
+};
+
+static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
+ "board_0_mcu_ospi1_dqs_out",
+ "fss_mcu_0_ospi_1_ospi_oclk_clk",
+};
+
+static const char * const wkup_fref_clksel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+};
+
+static const char * const main_pll_hfosc_sel_out1_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
+ "wkup_fref_clksel_out0",
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+};
+
+static const char * const mcuusart_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "postdiv3_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const main_pll25_hfosc_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out12_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out13_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out14_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out15_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out16_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out17_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out18_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out19_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out2_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out23_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out3_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out4_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out5_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out6_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out7_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const main_pll_hfosc_sel_out8_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const usb0_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const usb1_refclk_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_hfosc1_clk_out",
+};
+
+static const char * const wkup_obsclk_mux_out0_parents[] = {
+ "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+ NULL,
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+ "hsdiv1_16fft_mcu_0_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_1_hsdivout1_clk",
+ "hsdiv4_16fft_mcu_1_hsdivout2_clk",
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "hsdiv4_16fft_mcu_1_hsdivout4_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+ "j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout2_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout3_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout4_clk",
+ "gluelogic_hfosc0_clkout",
+ "gluelogic_lpxosc_clkout",
+};
+
+static const char * const main_pll15_xref_sel_out0_parents[] = {
+ "main_pll_hfosc_sel_out15",
+ "board_0_ext_refclk1_out",
+};
+
+static const char * const main_pll24_hfosc_sel_out0_parents[] = {
+ "gluelogic_hfosc0_clkout",
+ "board_0_mlb0_mlbcp_out",
+};
+
+static const char * const main_pll4_xref_sel_out0_parents[] = {
+ "main_pll_hfosc_sel_out4",
+ "board_0_ext_refclk1_out",
+};
+
+static const char * const mcu_clkout_mux_out0_parents[] = {
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+ "hsdiv4_16fft_mcu_2_hsdivout0_clk",
+};
+
+static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
+ "main_pll_hfosc_sel_out0",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+};
+
+static const char * const mcu_obsclk_outmux_out0_parents[] = {
+ "mcu_obsclk_div_out0",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const char * const obsclk1_mux_out0_parents[] = {
+ "hsdiv0_16fft_main_7_hsdivout0_clk",
+ "hsdiv0_16fft_main_8_hsdivout0_clk",
+ "hsdiv3_16fft_main_13_hsdivout0_clk",
+ NULL,
+};
+
+static const char * const clkout_mux_out0_parents[] = {
+ "hsdiv4_16fft_main_3_hsdivout0_clk",
+ "hsdiv4_16fft_main_3_hsdivout0_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const emmcsd_refclk_sel_out1_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout2_clk",
+ "hsdiv4_16fft_main_1_hsdivout2_clk",
+ "hsdiv4_16fft_main_2_hsdivout2_clk",
+ "hsdiv4_16fft_main_3_hsdivout2_clk",
+};
+
+static const char * const gtc_clk_mux_out0_parents[] = {
+ "hsdiv4_16fft_main_3_hsdivout1_clk",
+ "postdiv3_16fft_main_0_hsdivout6_clk",
+ "board_0_mcu_cpts0_rft_clk_out",
+ "board_0_cpts0_rft_clk_out",
+ "board_0_mcu_ext_refclk0_out",
+ "board_0_ext_refclk1_out",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv4_16fft_mcu_2_hsdivout1_clk",
+ "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const gpmc_fclk_sel_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout3_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "hsdiv4_16fft_main_2_hsdivout1_clk",
+ "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+};
+
+static const char * const mcasp_ahclko_mux_out0_parents[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv3_16fft_main_4_hsdivout2_clk",
+ "hsdiv3_16fft_main_15_hsdivout2_clk",
+ NULL,
+ NULL,
+ "board_0_audio_ext_refclk0_out",
+};
+
+static const char * const mcasp_ahclko_mux_out1_parents[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv3_16fft_main_4_hsdivout2_clk",
+ "hsdiv3_16fft_main_15_hsdivout2_clk",
+ NULL,
+ NULL,
+ "board_0_audio_ext_refclk1_out",
+};
+
+static const char * const mcasp_ahclko_mux_out2_parents[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv3_16fft_main_4_hsdivout2_clk",
+ "hsdiv3_16fft_main_15_hsdivout2_clk",
+ NULL,
+ NULL,
+ "board_0_audio_ext_refclk2_out",
+};
+
+static const char * const mcasp_ahclko_mux_out3_parents[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv3_16fft_main_4_hsdivout2_clk",
+ "hsdiv3_16fft_main_15_hsdivout2_clk",
+ NULL,
+ NULL,
+ "board_0_audio_ext_refclk3_out",
+};
+
+static const char * const obsclk0_mux_out0_parents[] = {
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+ "hsdiv4_16fft_main_1_hsdivout0_clk",
+ "hsdiv4_16fft_main_2_hsdivout0_clk",
+ "hsdiv4_16fft_main_3_hsdivout0_clk",
+ "hsdiv3_16fft_main_4_hsdivout0_clk",
+ "hsdiv3_16fft_main_5_hsdivout0_clk",
+ "hsdiv0_16fft_main_6_hsdivout0_clk",
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv0_16fft_main_12_hsdivout0_clk",
+ "obsclk1_mux_out0",
+ "hsdiv1_16fft_main_14_hsdivout0_clk",
+ "hsdiv3_16fft_main_15_hsdivout0_clk",
+ "hsdiv1_16fft_main_16_hsdivout0_clk",
+ "hsdiv1_16fft_main_17_hsdivout0_clk",
+ "hsdiv1_16fft_main_18_hsdivout0_clk",
+ "hsdiv1_16fft_main_19_hsdivout0_clk",
+ NULL,
+ NULL,
+ NULL,
+ "hsdiv1_16fft_main_23_hsdivout0_clk",
+ "hsdiv0_16fft_main_24_hsdivout0_clk",
+ "hsdiv1_16fft_main_25_hsdivout0_clk",
+ NULL,
+ "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk",
+ "gluelogic_lpxosc_clkout",
+ "hsdiv4_16fft_main_0_hsdivout0_clk",
+ "board_0_hfosc1_clk_out",
+ "gluelogic_hfosc0_clkout",
+};
+
+static const struct clk_data clk_list[] = {
+ CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
+ CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
+ CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
+ CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
+ CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
+ CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
+ CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
+ CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
+ CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
+ CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
+ CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk", 12500000, 0),
+ CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
+ CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
+ CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
+ CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
+ CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
+ CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
+ CLK_DIV("pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
+ CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
+ CLK_PLL_DEFFREQ("pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
+ CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 166666666),
+ CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0),
+ CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
+ CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
+ CLK_MUX("mcuusart_clk_sel_out0", mcuusart_clk_sel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
+ CLK_MUX("wkup_i2c0_mcupll_bypass_clksel_out0", wkup_i2c0_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
+ CLK_FIXED_RATE("gluelogic_lpxosc_clkout", 32768, 0),
+ CLK_MUX("main_pll25_hfosc_sel_out0", main_pll25_hfosc_sel_out0_parents, 2, 0x430080e4, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out13", main_pll_hfosc_sel_out13_parents, 2, 0x430080b4, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out14", main_pll_hfosc_sel_out14_parents, 2, 0x430080b8, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out15", main_pll_hfosc_sel_out15_parents, 2, 0x430080bc, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out16", main_pll_hfosc_sel_out16_parents, 2, 0x430080c0, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out17", main_pll_hfosc_sel_out17_parents, 2, 0x430080c4, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out18", main_pll_hfosc_sel_out18_parents, 2, 0x430080c8, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out23", main_pll_hfosc_sel_out23_parents, 2, 0x430080dc, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out4", main_pll_hfosc_sel_out4_parents, 2, 0x43008090, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out5", main_pll_hfosc_sel_out5_parents, 2, 0x43008094, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out6", main_pll_hfosc_sel_out6_parents, 2, 0x43008098, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
+ CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
+ CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
+ CLK_MUX("usb1_refclk_sel_out0", usb1_refclk_sel_out0_parents, 2, 0x1080e4, 0, 1, 0),
+ CLK_FIXED_RATE("board_0_audio_ext_refclk0_out", 0, 0),
+ CLK_FIXED_RATE("board_0_audio_ext_refclk1_out", 0, 0),
+ CLK_FIXED_RATE("board_0_audio_ext_refclk2_out", 0, 0),
+ CLK_FIXED_RATE("board_0_audio_ext_refclk3_out", 0, 0),
+ CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
+ CLK_FIXED_RATE("board_0_mlb0_mlbcp_out", 0, 0),
+ CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck", 0, 0),
+ CLK_FIXED_RATE("ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n", 0, 0),
+ CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0),
+ CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
+ CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 192000000),
+ CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01088, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfrac2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0),
+ CLK_FIXED_RATE("j7_wakeup_16ff_wkup_0_wkup_rcosc_32k_clk", 32000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
+ CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
+ CLK_DIV("pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_13_foutvcop_clk", "main_pll_hfosc_sel_out13", 0x68d000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_16_foutvcop_clk", "main_pll_hfosc_sel_out16", 0x690000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_17_foutvcop_clk", "main_pll_hfosc_sel_out17", 0x691000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_18_foutvcop_clk", "main_pll_hfosc_sel_out18", 0x692000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_23_foutvcop_clk", "main_pll_hfosc_sel_out23", 0x697000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_25_foutvcop_clk", "main_pll25_hfosc_sel_out0", 0x699000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_5_foutvcop_clk", "main_pll_hfosc_sel_out5", 0x685000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_6_foutvcop_clk", "main_pll_hfosc_sel_out6", 0x686000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
+ CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
+ CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfrac2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0),
+ CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfrac2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0),
+ CLK_MUX("wkup_obsclk_mux_out0", wkup_obsclk_mux_out0_parents, 16, 0x43008000, 0, 4, 0),
+ CLK_MUX("main_pll15_xref_sel_out0", main_pll15_xref_sel_out0_parents, 2, 0x430080bc, 4, 1, 0),
+ CLK_MUX("main_pll24_hfosc_sel_out0", main_pll24_hfosc_sel_out0_parents, 2, 0x430080e0, 0, 1, 0),
+ CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0),
+ CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 48000000),
+ CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0),
+ CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0),
+ CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0),
+ CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_main_14_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_14_foutvcop_clk", 0x68e080, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_main_16_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_16_foutvcop_clk", 0x690080, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_main_17_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_17_foutvcop_clk", 0x691080, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_main_18_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_18_foutvcop_clk", 0x692080, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_main_23_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_23_foutvcop_clk", 0x697080, 0, 7, 0),
+ CLK_DIV("hsdiv1_16fft_main_25_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_25_foutvcop_clk", 0x699080, 0, 7, 0),
+ CLK_DIV("hsdiv3_16fft_main_13_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_13_foutvcop_clk", 0x68d080, 0, 7, 0),
+ CLK_DIV("hsdiv3_16fft_main_5_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_5_foutvcop_clk", 0x685080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfrac2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683080, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0),
+ CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0),
+ CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0),
+ CLK_DIV("mcu_obsclk_div_out0", "wkup_obsclk_mux_out0", 0x43008000, 8, 4, 0),
+ CLK_MUX("mcu_obsclk_outmux_out0", mcu_obsclk_outmux_out0_parents, 2, 0x43008000, 24, 1, 0),
+ CLK_MUX("obsclk1_mux_out0", obsclk1_mux_out0_parents, 4, 0x108004, 0, 2, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_15_foutvcop_clk", "main_pll15_xref_sel_out0", 0x68f000, 0),
+ CLK_PLL("pllfrac2_ssmod_16fft_main_4_foutvcop_clk", "main_pll4_xref_sel_out0", 0x684000, 0),
+ CLK_MUX("clkout_mux_out0", clkout_mux_out0_parents, 2, 0x108010, 0, 1, 0),
+ CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
+ CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
+ CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
+ CLK_MUX("gpmc_fclk_sel_out0", gpmc_fclk_sel_out0_parents, 4, 0x1080d0, 0, 2, 0),
+ CLK_DIV("hsdiv0_16fft_main_24_hsdivout0_clk", "plldeskew_16fft_main_24_foutp_clk", 0x698080, 0, 0, 0),
+ CLK_DIV("hsdiv3_16fft_main_15_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0),
+ CLK_DIV("hsdiv3_16fft_main_15_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_15_foutvcop_clk", 0x68f088, 0, 7, 0),
+ CLK_DIV("hsdiv3_16fft_main_4_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684080, 0, 7, 0),
+ CLK_DIV("hsdiv3_16fft_main_4_hsdivout2_clk", "pllfrac2_ssmod_16fft_main_4_foutvcop_clk", 0x684088, 0, 7, 0),
+ CLK_MUX("mcasp_ahclko_mux_out0", mcasp_ahclko_mux_out0_parents, 33, 0x1082e0, 0, 5, 0),
+ CLK_MUX("mcasp_ahclko_mux_out1", mcasp_ahclko_mux_out1_parents, 33, 0x1082e4, 0, 5, 0),
+ CLK_MUX("mcasp_ahclko_mux_out2", mcasp_ahclko_mux_out2_parents, 33, 0x1082e8, 0, 5, 0),
+ CLK_MUX("mcasp_ahclko_mux_out3", mcasp_ahclko_mux_out3_parents, 33, 0x1082ec, 0, 5, 0),
+ CLK_MUX("obsclk0_mux_out0", obsclk0_mux_out0_parents, 32, 0x108000, 0, 5, 0),
+ CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0),
+ CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0),
+};
+
+static const struct dev_clk soc_dev_clk_data[] = {
+ DEV_CLK(4, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(4, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(30, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(30, 1, "board_0_hfosc1_clk_out"),
+ DEV_CLK(30, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
+ DEV_CLK(30, 4, "hsdiv4_16fft_main_0_hsdivout1_clk"),
+ DEV_CLK(30, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(30, 6, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(30, 7, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(30, 8, "hsdiv4_16fft_main_0_hsdivout4_clk"),
+ DEV_CLK(30, 9, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(30, 10, "board_0_hfosc1_clk_out"),
+ DEV_CLK(30, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(30, 12, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+ DEV_CLK(47, 0, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(47, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(47, 2, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+ DEV_CLK(47, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(61, 1, "gtc_clk_mux_out0"),
+ DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
+ DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
+ DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
+ DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
+ DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
+ DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
+ DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
+ DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(91, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(91, 1, "emmcsd_refclk_sel_out0"),
+ DEV_CLK(91, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(91, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(91, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(91, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(92, 0, "emmcsd_refclk_sel_out1"),
+ DEV_CLK(92, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
+ DEV_CLK(92, 2, "hsdiv4_16fft_main_1_hsdivout2_clk"),
+ DEV_CLK(92, 3, "hsdiv4_16fft_main_2_hsdivout2_clk"),
+ DEV_CLK(92, 4, "hsdiv4_16fft_main_3_hsdivout2_clk"),
+ DEV_CLK(92, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(92, 6, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(102, 0, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(102, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(102, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(102, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(102, 4, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(103, 0, "mcu_ospi_ref_clk_sel_out0"),
+ DEV_CLK(103, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+ DEV_CLK(103, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(103, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(103, 4, "mcu_ospi0_iclk_sel_out0"),
+ DEV_CLK(103, 5, "board_0_mcu_ospi0_dqs_out"),
+ DEV_CLK(103, 6, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(103, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(103, 8, "board_0_mcu_ospi0_dqs_out"),
+ DEV_CLK(104, 0, "mcu_ospi_ref_clk_sel_out1"),
+ DEV_CLK(104, 1, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
+ DEV_CLK(104, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
+ DEV_CLK(104, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(104, 4, "mcu_ospi1_iclk_sel_out0"),
+ DEV_CLK(104, 5, "board_0_mcu_ospi1_dqs_out"),
+ DEV_CLK(104, 6, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+ DEV_CLK(104, 7, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(104, 8, "board_0_mcu_ospi1_dqs_out"),
+ DEV_CLK(113, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(133, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(133, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(138, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(138, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(146, 0, "usart_programmable_clock_divider_out0"),
+ DEV_CLK(146, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(149, 0, "mcuusart_clk_sel_out0"),
+ DEV_CLK(149, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+ DEV_CLK(149, 2, "postdiv3_16fft_main_1_hsdivout5_clk"),
+ DEV_CLK(149, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(154, 0, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+ DEV_CLK(154, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(154, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(157, 18, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 19, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
+ DEV_CLK(157, 21, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+ DEV_CLK(157, 22, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
+ DEV_CLK(157, 42, "mshsi2c_wkup_0_porscl"),
+ DEV_CLK(157, 50, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
+ DEV_CLK(157, 51, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
+ DEV_CLK(157, 91, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck"),
+ DEV_CLK(157, 92, "ddr32ss_16ffc_ew_dv_wrap_main_0_ddrss_io_ck_n"),
+ DEV_CLK(157, 99, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
+ DEV_CLK(157, 100, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
+ DEV_CLK(157, 104, "gpmc_fclk_sel_out0"),
+ DEV_CLK(157, 109, "hsdiv1_16fft_main_19_hsdivout0_clk"),
+ DEV_CLK(157, 111, "hsdiv1_16fft_main_23_hsdivout0_clk"),
+ DEV_CLK(157, 113, "osbclk0_div_out0"),
+ DEV_CLK(157, 114, "hsdiv4_16fft_main_0_hsdivout0_clk"),
+ DEV_CLK(157, 115, "hsdiv4_16fft_main_1_hsdivout0_clk"),
+ DEV_CLK(157, 116, "hsdiv4_16fft_main_2_hsdivout0_clk"),
+ DEV_CLK(157, 117, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+ DEV_CLK(157, 118, "hsdiv3_16fft_main_4_hsdivout0_clk"),
+ DEV_CLK(157, 119, "hsdiv3_16fft_main_5_hsdivout0_clk"),
+ DEV_CLK(157, 120, "hsdiv0_16fft_main_6_hsdivout0_clk"),
+ DEV_CLK(157, 126, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+ DEV_CLK(157, 127, "obsclk1_mux_out0"),
+ DEV_CLK(157, 128, "hsdiv1_16fft_main_14_hsdivout0_clk"),
+ DEV_CLK(157, 129, "hsdiv3_16fft_main_15_hsdivout0_clk"),
+ DEV_CLK(157, 130, "hsdiv1_16fft_main_16_hsdivout0_clk"),
+ DEV_CLK(157, 131, "hsdiv1_16fft_main_17_hsdivout0_clk"),
+ DEV_CLK(157, 132, "hsdiv1_16fft_main_18_hsdivout0_clk"),
+ DEV_CLK(157, 133, "hsdiv1_16fft_main_19_hsdivout0_clk"),
+ DEV_CLK(157, 137, "hsdiv1_16fft_main_23_hsdivout0_clk"),
+ DEV_CLK(157, 138, "hsdiv0_16fft_main_24_hsdivout0_clk"),
+ DEV_CLK(157, 139, "hsdiv1_16fft_main_25_hsdivout0_clk"),
+ DEV_CLK(157, 141, "j7_wakeup_16ff_wkup_0_wkup_rcosc_12p5m_clk"),
+ DEV_CLK(157, 142, "gluelogic_lpxosc_clkout"),
+ DEV_CLK(157, 143, "hsdiv4_16fft_main_0_hsdivout0_clk"),
+ DEV_CLK(157, 144, "board_0_hfosc1_clk_out"),
+ DEV_CLK(157, 145, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(157, 146, "obsclk1_mux_out0"),
+ DEV_CLK(157, 147, "hsdiv0_16fft_main_7_hsdivout0_clk"),
+ DEV_CLK(157, 148, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(157, 149, "hsdiv3_16fft_main_13_hsdivout0_clk"),
+ DEV_CLK(157, 152, "mcu_obsclk_outmux_out0"),
+ DEV_CLK(157, 153, "mcu_obsclk_div_out0"),
+ DEV_CLK(157, 154, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(157, 169, "k3_pll_ctrl_wrap_main_0_sysclkout_clk"),
+ DEV_CLK(157, 170, "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk"),
+ DEV_CLK(157, 172, "clkout_mux_out0"),
+ DEV_CLK(157, 173, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+ DEV_CLK(157, 174, "hsdiv4_16fft_main_3_hsdivout0_clk"),
+ DEV_CLK(157, 175, "mcu_clkout_mux_out0"),
+ DEV_CLK(157, 176, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(157, 177, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
+ DEV_CLK(157, 301, "mcasp_ahclko_mux_out0"),
+ DEV_CLK(157, 330, "hsdiv3_16fft_main_4_hsdivout2_clk"),
+ DEV_CLK(157, 331, "hsdiv3_16fft_main_15_hsdivout2_clk"),
+ DEV_CLK(157, 334, "board_0_audio_ext_refclk0_out"),
+ DEV_CLK(157, 336, "mcasp_ahclko_mux_out1"),
+ DEV_CLK(157, 365, "hsdiv3_16fft_main_4_hsdivout2_clk"),
+ DEV_CLK(157, 366, "hsdiv3_16fft_main_15_hsdivout2_clk"),
+ DEV_CLK(157, 369, "board_0_audio_ext_refclk1_out"),
+ DEV_CLK(157, 371, "mcasp_ahclko_mux_out2"),
+ DEV_CLK(157, 400, "hsdiv3_16fft_main_4_hsdivout2_clk"),
+ DEV_CLK(157, 401, "hsdiv3_16fft_main_15_hsdivout2_clk"),
+ DEV_CLK(157, 404, "board_0_audio_ext_refclk2_out"),
+ DEV_CLK(157, 406, "mcasp_ahclko_mux_out3"),
+ DEV_CLK(157, 435, "hsdiv3_16fft_main_4_hsdivout2_clk"),
+ DEV_CLK(157, 436, "hsdiv3_16fft_main_15_hsdivout2_clk"),
+ DEV_CLK(157, 439, "board_0_audio_ext_refclk3_out"),
+ DEV_CLK(197, 0, "wkup_i2c0_mcupll_bypass_clksel_out0"),
+ DEV_CLK(197, 1, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
+ DEV_CLK(197, 2, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(197, 3, "board_0_wkup_i2c0_scl_out"),
+ DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
+ DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
+ DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(288, 15, "usb0_refclk_sel_out0"),
+ DEV_CLK(288, 16, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(288, 17, "board_0_hfosc1_clk_out"),
+ DEV_CLK(288, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(288, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(289, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
+ DEV_CLK(289, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(289, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(289, 15, "usb1_refclk_sel_out0"),
+ DEV_CLK(289, 16, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(289, 17, "board_0_hfosc1_clk_out"),
+ DEV_CLK(289, 18, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(289, 19, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+};
+
+const struct ti_k3_clk_platdata j721e_clk_platdata = {
+ .clk_list = clk_list,
+ .clk_list_cnt = 156,
+ .soc_dev_clk_data = soc_dev_clk_data,
+ .soc_dev_clk_data_cnt = 171,
+};
diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c
new file mode 100644
index 0000000..96393c7
--- /dev/null
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * J721E specific device platform data
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#include "k3-dev.h"
+
+static struct ti_psc soc_psc_list[] = {
+ [0] = PSC(0, 0x00400000),
+ [1] = PSC(1, 0x42000000),
+};
+
+static struct ti_pd soc_pd_list[] = {
+ [0] = PSC_PD(0, &soc_psc_list[0], NULL),
+ [1] = PSC_PD(14, &soc_psc_list[0], NULL),
+ [2] = PSC_PD(15, &soc_psc_list[0], &soc_pd_list[1]),
+ [3] = PSC_PD(16, &soc_psc_list[0], &soc_pd_list[1]),
+ [4] = PSC_PD(0, &soc_psc_list[1], NULL),
+};
+
+static struct ti_lpsc soc_lpsc_list[] = {
+ [0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [1] = PSC_LPSC(7, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [2] = PSC_LPSC(14, &soc_psc_list[0], &soc_pd_list[0], &soc_lpsc_list[3]),
+ [3] = PSC_LPSC(15, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [4] = PSC_LPSC(20, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [5] = PSC_LPSC(21, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [6] = PSC_LPSC(23, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [7] = PSC_LPSC(25, &soc_psc_list[0], &soc_pd_list[0], NULL),
+ [8] = PSC_LPSC(78, &soc_psc_list[0], &soc_pd_list[1], NULL),
+ [9] = PSC_LPSC(80, &soc_psc_list[0], &soc_pd_list[2], &soc_lpsc_list[8]),
+ [10] = PSC_LPSC(81, &soc_psc_list[0], &soc_pd_list[3], &soc_lpsc_list[8]),
+ [11] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[4], NULL),
+ [12] = PSC_LPSC(3, &soc_psc_list[1], &soc_pd_list[4], NULL),
+ [13] = PSC_LPSC(10, &soc_psc_list[1], &soc_pd_list[4], NULL),
+ [14] = PSC_LPSC(11, &soc_psc_list[1], &soc_pd_list[4], NULL),
+ [15] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[4], NULL),
+};
+
+static struct ti_dev soc_dev_list[] = {
+ PSC_DEV(30, &soc_lpsc_list[0]),
+ PSC_DEV(61, &soc_lpsc_list[0]),
+ PSC_DEV(146, &soc_lpsc_list[1]),
+ PSC_DEV(90, &soc_lpsc_list[2]),
+ PSC_DEV(47, &soc_lpsc_list[3]),
+ PSC_DEV(288, &soc_lpsc_list[4]),
+ PSC_DEV(289, &soc_lpsc_list[5]),
+ PSC_DEV(92, &soc_lpsc_list[6]),
+ PSC_DEV(91, &soc_lpsc_list[7]),
+ PSC_DEV(4, &soc_lpsc_list[8]),
+ PSC_DEV(202, &soc_lpsc_list[9]),
+ PSC_DEV(203, &soc_lpsc_list[10]),
+ PSC_DEV(102, &soc_lpsc_list[11]),
+ PSC_DEV(103, &soc_lpsc_list[11]),
+ PSC_DEV(104, &soc_lpsc_list[11]),
+ PSC_DEV(154, &soc_lpsc_list[11]),
+ PSC_DEV(149, &soc_lpsc_list[11]),
+ PSC_DEV(113, &soc_lpsc_list[12]),
+ PSC_DEV(197, &soc_lpsc_list[12]),
+ PSC_DEV(103, &soc_lpsc_list[13]),
+ PSC_DEV(104, &soc_lpsc_list[14]),
+ PSC_DEV(102, &soc_lpsc_list[15]),
+};
+
+const struct ti_k3_pd_platdata j721e_pd_platdata = {
+ .psc = soc_psc_list,
+ .pd = soc_pd_list,
+ .lpsc = soc_lpsc_list,
+ .devs = soc_dev_list,
+ .num_psc = 2,
+ .num_pd = 5,
+ .num_lpsc = 16,
+ .num_devs = 22,
+};
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 1a4f796..e9e076c 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -125,8 +125,8 @@
* but the .bss is cleared between writing and reading this variable, so move
* it to the .data section.
*/
-u32 bootindex __attribute__((section(".data")));
-static struct rom_extended_boot_data bootdata __section(.data);
+u32 bootindex __section(".data");
+static struct rom_extended_boot_data bootdata __section(".data");
static void store_boot_info_from_rom(void)
{
@@ -180,6 +180,18 @@
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
k3_mmc_stop_clock, k3_mmc_restart_clock);
+ /*
+ * Force probe of clk_k3 driver here to ensure basic default clock
+ * configuration is always done.
+ */
+ if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(ti_clk),
+ &dev);
+ if (ret)
+ panic("Failed to initialize clk-k3!\n");
+ }
+
/* Prepare console output */
preloader_console_init();
diff --git a/arch/arm/mach-k3/security.c b/arch/arm/mach-k3/security.c
index 66f90a5..8de9739 100644
--- a/arch/arm/mach-k3/security.c
+++ b/arch/arm/mach-k3/security.c
@@ -18,7 +18,7 @@
#include <spl.h>
#include <asm/arch/sys_proto.h>
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void ti_secure_image_post_process(void **p_image, size_t *p_size)
{
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
diff --git a/arch/arm/mach-k3/sysfw-loader.c b/arch/arm/mach-k3/sysfw-loader.c
index 0bacfc4..d213e06 100644
--- a/arch/arm/mach-k3/sysfw-loader.c
+++ b/arch/arm/mach-k3/sysfw-loader.c
@@ -40,6 +40,46 @@
*/
#define K3_SYSTEM_CONTROLLER_RPROC_ID 0
+#define COMMON_HEADER_ADDRESS 0x41cffb00
+#define BOARDCFG_ADDRESS 0x41c80000
+
+#define COMP_TYPE_SBL_DATA 0x11
+#define DESC_TYPE_BOARDCFG_PM_INDEX 0x2
+#define DESC_TYPE_BOARDCFG_RM_INDEX 0x3
+
+#define BOARD_CONFIG_RM_DESC_TYPE 0x000c
+#define BOARD_CONFIG_PM_DESC_TYPE 0x000e
+
+struct extboot_comp {
+ u32 comp_type;
+ u32 boot_core;
+ u32 comp_opts;
+ u64 dest_addr;
+ u32 comp_size;
+};
+
+struct extboot_header {
+ u8 magic[8];
+ u32 num_comps;
+ struct extboot_comp comps[5];
+ u32 reserved;
+};
+
+struct bcfg_desc {
+ u16 type;
+ u16 offset;
+ u16 size;
+ u8 devgrp;
+ u8 reserved;
+} __packed;
+
+struct bcfg_header {
+ u8 num_elems;
+ u8 sw_rev;
+ struct bcfg_desc descs[4];
+ u16 reserved;
+} __packed;
+
static bool sysfw_loaded;
static void *sysfw_load_address;
@@ -131,6 +171,13 @@
const void *cfg_fragment_addr;
size_t cfg_fragment_size;
int ret;
+ u8 *buf;
+ struct extboot_header *common_header;
+ struct bcfg_header *bcfg_header;
+ struct extboot_comp *comp;
+ struct bcfg_desc *desc;
+ u32 addr;
+ bool copy_bcfg = false;
/* Find the node holding the images information */
images = fdt_path_offset(fit, FIT_IMAGES_PATH);
@@ -159,11 +206,53 @@
ret);
/* Apply power/clock (PM) specific configuration to SYSFW */
- ret = board_ops->board_config_pm(ti_sci,
- (u64)(u32)cfg_fragment_addr,
- (u32)cfg_fragment_size);
- if (ret)
- panic("Failed to set board PM configuration (%d)\n", ret);
+ if (!IS_ENABLED(CONFIG_K3_DM_FW)) {
+ ret = board_ops->board_config_pm(ti_sci,
+ (u64)(u32)cfg_fragment_addr,
+ (u32)cfg_fragment_size);
+ if (ret)
+ panic("Failed to set board PM configuration (%d)\n", ret);
+ } else {
+ /* Initialize shared memory boardconfig buffer */
+ buf = (u8 *)COMMON_HEADER_ADDRESS;
+ common_header = (struct extboot_header *)buf;
+
+ /* Check if we have a struct populated by ROM in memory already */
+ if (strcmp((char *)common_header->magic, "EXTBOOT"))
+ copy_bcfg = true;
+
+ if (copy_bcfg) {
+ strcpy((char *)common_header->magic, "EXTBOOT");
+ common_header->num_comps = 1;
+
+ comp = &common_header->comps[0];
+
+ comp->comp_type = COMP_TYPE_SBL_DATA;
+ comp->boot_core = 0x10;
+ comp->comp_opts = 0;
+ addr = (u32)BOARDCFG_ADDRESS;
+ comp->dest_addr = addr;
+ comp->comp_size = sizeof(*bcfg_header);
+
+ bcfg_header = (struct bcfg_header *)addr;
+
+ bcfg_header->num_elems = 2;
+ bcfg_header->sw_rev = 0;
+
+ desc = &bcfg_header->descs[0];
+
+ desc->type = BOARD_CONFIG_PM_DESC_TYPE;
+ desc->offset = sizeof(*bcfg_header);
+ desc->size = cfg_fragment_size;
+ comp->comp_size += desc->size;
+ desc->devgrp = 0;
+ desc->reserved = 0;
+ memcpy((u8 *)bcfg_header + desc->offset,
+ cfg_fragment_addr, cfg_fragment_size);
+
+ bcfg_header->descs[1].offset = desc->offset + desc->size;
+ }
+ }
/* Extract resource management (RM) specific configuration from FIT */
ret = fit_get_data_by_name(fit, images, SYSFW_CFG_RM,
@@ -172,6 +261,18 @@
panic("Error accessing %s node in FIT (%d)\n", SYSFW_CFG_RM,
ret);
+ if (copy_bcfg) {
+ desc = &bcfg_header->descs[1];
+
+ desc->type = BOARD_CONFIG_RM_DESC_TYPE;
+ desc->size = cfg_fragment_size;
+ comp->comp_size += desc->size;
+ desc->devgrp = 0;
+ desc->reserved = 0;
+ memcpy((u8 *)bcfg_header + desc->offset, cfg_fragment_addr,
+ cfg_fragment_size);
+ }
+
/* Apply resource management (RM) configuration to SYSFW */
ret = board_ops->board_config_rm(ti_sci,
(u64)(u32)cfg_fragment_addr,
diff --git a/arch/arm/mach-keystone/Makefile b/arch/arm/mach-keystone/Makefile
index 3e076e1..6c7c250 100644
--- a/arch/arm/mach-keystone/Makefile
+++ b/arch/arm/mach-keystone/Makefile
@@ -9,6 +9,7 @@
obj-y += psc.o
obj-y += clock.o
obj-y += mon.o
+CFLAGS_REMOVE_mon.o := $(LTO_CFLAGS)
ifndef CONFIG_SPL_BUILD
obj-y += cmd_clock.o
obj-y += cmd_mon.o
diff --git a/arch/arm/mach-keystone/mon.c b/arch/arm/mach-keystone/mon.c
index 58995d7..b863bab 100644
--- a/arch/arm/mach-keystone/mon.c
+++ b/arch/arm/mach-keystone/mon.c
@@ -103,7 +103,8 @@
return result;
}
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
int result = 0;
void *image = *p_image;
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 0299611..cda65f7 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -141,6 +141,13 @@
select BOARD_LATE_INIT
imply SCSI
+config TARGET_OCTEONTX2_CN913x
+ bool "Support CN913x platforms"
+ select ARMADA_8K
+ imply BOARD_EARLY_INIT_R
+ select BOARD_LATE_INIT
+ imply SCSI
+
config TARGET_DB_MV784MP_GP
bool "Support db-mv784mp-gp"
select MV78460
@@ -187,6 +194,7 @@
default "turris_omnia" if TARGET_TURRIS_OMNIA
default "turris_mox" if TARGET_TURRIS_MOX
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
+ default "octeontx2_cn913x" if TARGET_OCTEONTX2_CN913x
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
@@ -204,6 +212,7 @@
default "db-88f6820-gp" if TARGET_DB_88F6820_GP
default "db-88f6820-amc" if TARGET_DB_88F6820_AMC
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
+ default "mvebu_armada-8k" if TARGET_OCTEONTX2_CN913x
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
@@ -222,6 +231,7 @@
default "Marvell" if TARGET_DB_88F6820_GP
default "Marvell" if TARGET_DB_88F6820_AMC
default "Marvell" if TARGET_MVEBU_ARMADA_8K
+ default "Marvell" if TARGET_OCTEONTX2_CN913x
default "Marvell" if TARGET_DB_XC3_24G4XG
default "Marvell" if TARGET_MVEBU_DB_88F7040
default "solidrun" if TARGET_CLEARFOG
diff --git a/arch/arm/mach-mvebu/armada3700/cpu.c b/arch/arm/mach-mvebu/armada3700/cpu.c
index 0cf60d7..9aec0ce 100644
--- a/arch/arm/mach-mvebu/armada3700/cpu.c
+++ b/arch/arm/mach-mvebu/armada3700/cpu.c
@@ -8,6 +8,7 @@
#include <cpu_func.h>
#include <dm.h>
#include <fdtdec.h>
+#include <fdt_support.h>
#include <init.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
@@ -53,8 +54,6 @@
#define A3700_PTE_BLOCK_DEVICE \
(PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE)
-#define PCIE_PATH "/soc/pcie@d0070000"
-
DECLARE_GLOBAL_DATA_PTR;
static struct mm_region mvebu_mem_map[MAX_MEM_MAP_REGIONS] = {
@@ -282,36 +281,81 @@
return -1;
}
+static int fdt_setprop_inplace_u32_partial(void *blob, int node,
+ const char *name,
+ u32 idx, u32 val)
+{
+ val = cpu_to_fdt32(val);
+
+ return fdt_setprop_inplace_namelen_partial(blob, node, name,
+ strlen(name),
+ idx * sizeof(u32),
+ &val, sizeof(u32));
+}
+
int a3700_fdt_fix_pcie_regions(void *blob)
{
- u32 new_ranges[14], base;
+ int acells, pacells, scells;
+ u32 base, fix_offset;
const u32 *ranges;
- int node, len;
+ int node, pnode;
+ int ret, i, len;
- node = fdt_path_offset(blob, PCIE_PATH);
+ base = find_pcie_window_base();
+ if (base == -1)
+ return -ENOENT;
+
+ node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-3700-pcie");
if (node < 0)
return node;
ranges = fdt_getprop(blob, node, "ranges", &len);
- if (!ranges)
+ if (!ranges || len % sizeof(u32))
return -ENOENT;
- if (len != sizeof(new_ranges))
- return -EINVAL;
-
- memcpy(new_ranges, ranges, len);
+ /*
+ * The "ranges" property is an array of
+ * { <child address> <parent address> <size in child address space> }
+ *
+ * All 3 elements can span a diffent number of cells. Fetch their sizes.
+ */
+ pnode = fdt_parent_offset(blob, node);
+ acells = fdt_address_cells(blob, node);
+ pacells = fdt_address_cells(blob, pnode);
+ scells = fdt_size_cells(blob, node);
- base = find_pcie_window_base();
- if (base == -1)
+ /* Child PCI addresses always use 3 cells */
+ if (acells != 3)
return -ENOENT;
+ /* Calculate fixup offset from first child address (in last cell) */
+ fix_offset = base - fdt32_to_cpu(ranges[2]);
+
- new_ranges[2] = cpu_to_fdt32(base);
- new_ranges[4] = new_ranges[2];
+ /*
+ * Fix address (last cell) of each child address and each parent
+ * address
+ */
+ for (i = 0; i < len / sizeof(u32); i += acells + pacells + scells) {
+ int idx;
- new_ranges[9] = cpu_to_fdt32(base + 0x1000000);
- new_ranges[11] = new_ranges[9];
+ /* fix child address */
+ idx = i + acells - 1;
+ ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
+ fdt32_to_cpu(ranges[idx]) +
+ fix_offset);
+ if (ret)
+ return ret;
- return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len);
+ /* fix parent address */
+ idx = i + acells + pacells - 1;
+ ret = fdt_setprop_inplace_u32_partial(blob, node, "ranges", idx,
+ fdt32_to_cpu(ranges[idx]) +
+ fix_offset);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
void reset_cpu(void)
diff --git a/arch/arm/mach-mvebu/armada8k/cpu.c b/arch/arm/mach-mvebu/armada8k/cpu.c
index 474327a..939abce 100644
--- a/arch/arm/mach-mvebu/armada8k/cpu.c
+++ b/arch/arm/mach-mvebu/armada8k/cpu.c
@@ -8,11 +8,13 @@
#include <dm.h>
#include <fdtdec.h>
#include <linux/libfdt.h>
+#include <linux/sizes.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
+#include <mach/fw_info.h>
/* Armada 7k/8k */
#define MVEBU_RFU_BASE (MVEBU_REGISTER(0x6f0000))
@@ -23,62 +25,31 @@
#define BOOT_MODE_MASK 0x3f
#define BOOT_MODE_OFFSET 4
-/*
- * The following table includes all memory regions for Armada 7k and
- * 8k SoCs. The Armada 7k is missing the CP110 slave regions here. Lets
- * define these regions at the beginning of the struct so that they
- * can be easier removed later dynamically if an Armada 7k device is detected.
- * For a detailed memory map, please see doc/mvebu/armada-8k-memory.txt
- */
-#define ARMADA_7K8K_COMMON_REGIONS_START 2
static struct mm_region mvebu_mem_map[] = {
/* Armada 80x0 memory regions include the CP1 (slave) units */
{
- /* SRAM, MMIO regions - CP110 slave region */
- .phys = 0xf4000000UL,
- .virt = 0xf4000000UL,
- .size = 0x02000000UL, /* 32MiB internal registers */
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE
- },
- {
- /* PCI CP1 regions */
- .phys = 0xfa000000UL,
- .virt = 0xfa000000UL,
- .size = 0x04000000UL, /* 64MiB CP110 slave PCI space */
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE
- },
- /* Armada 80x0 and 70x0 common memory regions start here */
- {
- /* RAM */
+ /* RAM 0-64MB */
.phys = 0x0UL,
.virt = 0x0UL,
- .size = 0x80000000UL,
+ .size = ATF_REGION_START,
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE
},
- {
- /* SRAM, MMIO regions - AP806 region */
- .phys = 0xf0000000UL,
- .virt = 0xf0000000UL,
- .size = 0x01000000UL, /* 16MiB internal registers */
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE
- },
+ /* ATF and TEE region 0x4000000-0x5400000 not mapped */
{
- /* SRAM, MMIO regions - CP110 master region */
- .phys = 0xf2000000UL,
- .virt = 0xf2000000UL,
- .size = 0x02000000UL, /* 32MiB internal registers */
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE
+ /* RAM 66MB-2GB */
+ .phys = ATF_REGION_END,
+ .virt = ATF_REGION_END,
+ .size = SZ_2G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
},
{
- /* PCI CP0 regions */
- .phys = 0xf6000000UL,
- .virt = 0xf6000000UL,
- .size = 0x04000000UL, /* 64MiB CP110 master PCI space */
+ /* MMIO regions */
+ .phys = MMIO_REGS_PHY_BASE,
+ .virt = MMIO_REGS_PHY_BASE,
+ .size = SZ_1G,
+
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE
},
@@ -91,15 +62,6 @@
void enable_caches(void)
{
- /*
- * Armada 7k is not equipped with the CP110 slave CP. In case this
- * code runs on an Armada 7k device, lets remove the CP110 slave
- * entries from the memory mapping by moving the start to the
- * common regions.
- */
- if (of_machine_is_compatible("marvell,armada7040"))
- mem_map = &mvebu_mem_map[ARMADA_7K8K_COMMON_REGIONS_START];
-
icache_enable();
dcache_enable();
}
diff --git a/arch/arm/mach-mvebu/include/mach/fw_info.h b/arch/arm/mach-mvebu/include/mach/fw_info.h
new file mode 100644
index 0000000..1382438
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/fw_info.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ */
+
+#ifndef _FW_INFO_H_
+#define _FW_INFO_H_
+
+/* Protected ATF and TEE region */
+#define ATF_REGION_START 0x4000000
+#define ATF_REGION_END 0x5400000
+
+/* Firmware related definition used for SMC calls */
+#define MV_SIP_DRAM_SIZE 0x82000010
+
+#define MMIO_REGS_PHY_BASE 0xc0000000
+
+#endif /* _FW_INFO_H_ */
diff --git a/arch/arm/mach-mvebu/mbus.c b/arch/arm/mach-mvebu/mbus.c
index f29abe5..3b1b9f7 100644
--- a/arch/arm/mach-mvebu/mbus.c
+++ b/arch/arm/mach-mvebu/mbus.c
@@ -98,9 +98,9 @@
};
struct mvebu_mbus_state mbus_state
- __attribute__ ((section(".data")));
+ __section(".data");
static struct mbus_dram_target_info mbus_dram_info
- __attribute__ ((section(".data")));
+ __section(".data");
/*
* Functions to manipulate the address decoding windows
diff --git a/arch/arm/mach-mvebu/timer.c b/arch/arm/mach-mvebu/timer.c
index 43b3ed1..557a378 100644
--- a/arch/arm/mach-mvebu/timer.c
+++ b/arch/arm/mach-mvebu/timer.c
@@ -14,7 +14,7 @@
#define TIMER_LOAD_VAL 0xffffffff
-static int init_done __attribute__((section(".data"))) = 0;
+static int init_done __section(".data") = 0;
/*
* Timer initialization
diff --git a/arch/arm/mach-nexell/clock.c b/arch/arm/mach-nexell/clock.c
index a0ba2d8..d5b46a8 100644
--- a/arch/arm/mach-nexell/clock.c
+++ b/arch/arm/mach-nexell/clock.c
@@ -99,7 +99,7 @@
* in board_init_f(), respectively! I.e. global variables can not be used!
*/
static struct clk_dev_peri clk_periphs[]
- __attribute__((section(".data"))) = {
+ __section(".data") = {
CLK_PERI_1S(DEV_NAME_TIMER, 0, CLK_ID_TIMER_0,
PHY_BASEADDR_CLKGEN14, (I_PLL_0_2)),
CLK_PERI_1S(DEV_NAME_TIMER, 1, CLK_ID_TIMER_1,
@@ -167,7 +167,7 @@
#define MAX_DIVIDER ((1 << 8) - 1) /* 256, align 2 */
static struct clk_dev st_clk_devs[CLK_DEVS_NUM]
- __attribute__((section(".data")));
+ __section(".data");
#define clk_dev_get(n) ((struct clk_dev *)&st_clk_devs[n])
#define clk_container(p) (container_of(p, struct clk_dev, clk))
@@ -196,7 +196,7 @@
* in board_init_f(), respectively! I.e. global variables can not be used!
*/
/* core clock */
-static struct _core_hz_ core_hz __attribute__((section(".data")));
+static struct _core_hz_ core_hz __section(".data");
#define CORE_HZ_SIZE (sizeof(core_hz) / 4)
diff --git a/arch/arm/mach-nexell/timer.c b/arch/arm/mach-nexell/timer.c
index fecee67..3b311fd 100644
--- a/arch/arm/mach-nexell/timer.c
+++ b/arch/arm/mach-nexell/timer.c
@@ -23,9 +23,9 @@
* Section ".data" must be used because BSS is not available before relocation,
* in board_init_f(), respectively! I.e. global variables can not be used!
*/
-static unsigned long timestamp __attribute__ ((section(".data")));
-static unsigned long lastdec __attribute__ ((section(".data")));
-static int timerinit __attribute__ ((section(".data")));
+static unsigned long timestamp __section(".data");
+static unsigned long lastdec __section(".data");
+static int timerinit __section(".data");
/* macro to hw timer tick config */
static long TIMER_FREQ = 1000000;
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 9a98e8a..11e54cd 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -34,6 +34,7 @@
select DM_GPIO
select DM_SERIAL
select TI_I2C_BOARD_DETECT
+ select SUPPORT_EXTENSION_SCAN
imply CMD_DM
imply SPL_DM
imply SPL_DM_SEQ_ALIAS
diff --git a/arch/arm/mach-omap2/am33xx/clock_am33xx.c b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
index cf71192..3a7ac60 100644
--- a/arch/arm/mach-omap2/am33xx/clock_am33xx.c
+++ b/arch/arm/mach-omap2/am33xx/clock_am33xx.c
@@ -220,6 +220,7 @@
&cmper->gpio2clkctrl,
&cmper->gpio3clkctrl,
&cmper->i2c1clkctrl,
+ &cmper->i2c2clkctrl,
&cmper->cpgmac0clkctrl,
&cmper->spi0clkctrl,
&cmrtc->rtcclkctrl,
diff --git a/arch/arm/mach-omap2/omap3/Makefile b/arch/arm/mach-omap2/omap3/Makefile
index 91ed8eb..151bdf6 100644
--- a/arch/arm/mach-omap2/omap3/Makefile
+++ b/arch/arm/mach-omap2/omap3/Makefile
@@ -9,6 +9,7 @@
obj-y := lowlevel_init.o
obj-y += board.o
+CFLAGS_REMOVE_board.o := $(LTO_CFLAGS)
obj-y += boot.o
obj-y += clock.o
obj-y += sys_info.o
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index a7132da..4c2f990 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -36,6 +36,7 @@
select CMD_DDR3
select DRA7XX
select TI_I2C_BOARD_DETECT
+ select SUPPORT_EXTENSION_SCAN
imply DM_THERMAL
imply SCSI
imply SPL_THERMAL
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index 8cef3f5..41322b2 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -13,6 +13,7 @@
select ARM64
select PHY
select CMD_CACHE
+ select OF_BOARD_SETUP
select PINCTRL
select PINCONF
select PINCTRL_PFC
diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c
index c386b52..5304eb0 100644
--- a/arch/arm/mach-rockchip/board.c
+++ b/arch/arm/mach-rockchip/board.c
@@ -139,7 +139,7 @@
.hsphy_mode = USBPHY_INTERFACE_MODE_UTMIW,
};
-int usb_gadget_handle_interrupts(void)
+int usb_gadget_handle_interrupts(int index)
{
dwc3_uboot_handle_interrupt(0);
return 0;
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 650122f..36eecdc 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -103,7 +103,8 @@
#endif
#if IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS)
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH)) {
if (socfpga_vendor_authentication(p_image, p_size))
diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index 92231b5..b5f43f0 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -40,7 +40,7 @@
SOCFPGA_PHYS_OCRAM_SIZE - \
BOOTROM_SHARED_MEM_SIZE)
#define RST_STATUS_SHARED_ADDR (BOOTROM_SHARED_MEM_ADDR + 0x438)
-static u32 rst_mgr_status __section(.data);
+static u32 rst_mgr_status __section(".data");
/*
* Bootrom will clear the status register in reset manager and stores the
diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c
index 8115d58..592bfd4 100644
--- a/arch/arm/mach-stm32mp/cpu.c
+++ b/arch/arm/mach-stm32mp/cpu.c
@@ -12,6 +12,7 @@
#include <env.h>
#include <init.h>
#include <log.h>
+#include <lmb.h>
#include <misc.h>
#include <net.h>
#include <asm/io.h>
@@ -90,6 +91,8 @@
*/
u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
+struct lmb lmb;
+
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
#ifndef CONFIG_TFABOOT
static void security_init(void)
@@ -221,6 +224,8 @@
int i;
phys_addr_t start;
phys_size_t size;
+ bool use_lmb = false;
+ enum dcache_option option;
if (IS_ENABLED(CONFIG_SPL_BUILD)) {
start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE);
@@ -229,6 +234,7 @@
/* bd->bi_dram is available only after relocation */
start = bd->bi_dram[bank].start;
size = bd->bi_dram[bank].size;
+ use_lmb = true;
} else {
/* mark cacheable and executable the beggining of the DDR */
start = STM32_DDR_BASE;
@@ -237,8 +243,12 @@
for (i = start >> MMU_SECTION_SHIFT;
i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
- i++)
- set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+ i++) {
+ option = DCACHE_DEFAULT_OPTION;
+ if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP))
+ option = 0; /* INVALID ENTRY in TLB */
+ set_section_dcache(i, option);
+ }
}
/*
* initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
@@ -302,6 +312,9 @@
void enable_caches(void)
{
+ /* parse device tree when data cache is still activated */
+ lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob);
+
/* I-cache is already enabled in start.S: icache_enable() not needed */
/* deactivate the data cache, early enabled in arch_cpu_init() */
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c
index 66e81ba..3c09702 100644
--- a/arch/arm/mach-stm32mp/dram_init.c
+++ b/arch/arm/mach-stm32mp/dram_init.c
@@ -50,13 +50,16 @@
lmb_init(&lmb);
lmb_add(&lmb, gd->ram_base, gd->ram_size);
boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob);
- size = ALIGN(CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
+ /* add 8M for reserved memory for display, fdt, gd,... */
+ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
reg = lmb_alloc(&lmb, size, MMU_SECTION_SIZE);
if (!reg)
reg = gd->ram_top - size;
- mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
+ /* before relocation, mark the U-Boot memory as cacheable by default */
+ if (!(gd->flags & GD_FLG_RELOC))
+ mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION);
return reg + size;
}
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 8e9012d..bc8509b 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1089,3 +1089,12 @@
flipped elsewise.
endif
+
+config CHIP_DIP_SCAN
+ bool "Enable DIPs detection for CHIP board"
+ select SUPPORT_EXTENSION_SCAN
+ select W1
+ select W1_GPIO
+ select W1_EEPROM
+ select W1_EEPROM_DS24XXX
+ select CMD_EXTENSION
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 503538e..9b84132 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -39,7 +39,7 @@
uint32_t cr;
};
-struct fel_stash fel_stash __attribute__((section(".data")));
+struct fel_stash fel_stash __section(".data");
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
diff --git a/arch/arm/mach-tegra/board.c b/arch/arm/mach-tegra/board.c
index 21852e2..95d6555 100644
--- a/arch/arm/mach-tegra/board.c
+++ b/arch/arm/mach-tegra/board.c
@@ -45,7 +45,7 @@
UART_COUNT = 5,
};
-static bool from_spl __attribute__ ((section(".data")));
+static bool from_spl __section(".data");
#ifndef CONFIG_SPL_BUILD
void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
diff --git a/arch/arm/mach-tegra/cboot.c b/arch/arm/mach-tegra/cboot.c
index bb46fb2..55eb819 100644
--- a/arch/arm/mach-tegra/cboot.c
+++ b/arch/arm/mach-tegra/cboot.c
@@ -49,7 +49,7 @@
*/
/* The number of valid entries in ram_banks[] */
-static int ram_bank_count __attribute__((section(".data")));
+static int ram_bank_count __section(".data");
/*
* The usable top-of-RAM for U-Boot. This is both:
@@ -57,15 +57,15 @@
* b) At the end of a region that has enough space to hold the relocated U-Boot
* and all other allocations made around it (stack, heap, page tables, etc.)
*/
-static u64 ram_top __attribute__((section(".data")));
+static u64 ram_top __section(".data");
/* The base address of the region of RAM that ends at ram_top */
-static u64 region_base __attribute__((section(".data")));
+static u64 region_base __section(".data");
/*
* Explicitly put this in the .data section because it is written before the
* .bss section is zeroed out but it needs to persist.
*/
-unsigned long cboot_boot_x0 __attribute__((section(".data")));
+unsigned long cboot_boot_x0 __section(".data");
void cboot_save_boot_params(unsigned long x0, unsigned long x1,
unsigned long x2, unsigned long x3)
diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile
index faaf30d..bb17c90 100644
--- a/arch/arm/mach-tegra/tegra20/Makefile
+++ b/arch/arm/mach-tegra/tegra20/Makefile
@@ -10,6 +10,7 @@
# flags for any startup files it might use.
CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \
-D__LINUX_ARM_ARCH__=4
+CFLAGS_REMOVE_warmboot_avp.o := $(LTO_CFLAGS)
obj-y += clock.o funcmux.o pinmux.o
obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c
index c97c311..9b0518d 100644
--- a/arch/arm/mach-versal/mp.c
+++ b/arch/arm/mach-versal/mp.c
@@ -5,13 +5,10 @@
*/
#include <common.h>
-#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
-DECLARE_GLOBAL_DATA_PTR;
-
#define HALT 0
#define RELEASE 1
diff --git a/arch/m68k/lib/time.c b/arch/m68k/lib/time.c
index cbe29e7..ebb2ac5 100644
--- a/arch/m68k/lib/time.c
+++ b/arch/m68k/lib/time.c
@@ -71,7 +71,7 @@
timestamp++;
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
- if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
+ if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
WATCHDOG_RESET ();
}
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 77f563e..e548016 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -12,16 +12,6 @@
prompt "Target select"
optional
-config TARGET_QEMU_MIPS
- bool "Support qemu-mips"
- select ROM_EXCEPTION_VECTORS
- select SUPPORTS_BIG_ENDIAN
- select SUPPORTS_CPU_MIPS32_R1
- select SUPPORTS_CPU_MIPS32_R2
- select SUPPORTS_CPU_MIPS64_R1
- select SUPPORTS_CPU_MIPS64_R2
- select SUPPORTS_LITTLE_ENDIAN
-
config TARGET_MALTA
bool "Support malta"
select DM
@@ -174,7 +164,6 @@
source "board/imgtec/boston/Kconfig"
source "board/imgtec/malta/Kconfig"
source "board/imgtec/xilfpga/Kconfig"
-source "board/qemu-mips/Kconfig"
source "arch/mips/mach-ath79/Kconfig"
source "arch/mips/mach-mscc/Kconfig"
source "arch/mips/mach-bmips/Kconfig"
diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c
index 43f5651..fefba12 100644
--- a/arch/mips/mach-jz47xx/jz4780/jz4780.c
+++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c
@@ -23,7 +23,7 @@
#ifdef CONFIG_SPL_BUILD
/* Pointer to the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
-gd_t gdata __attribute__ ((section(".bss")));
+gd_t gdata __section(".bss");
void board_init_f(ulong dummy)
{
diff --git a/arch/nds32/include/asm/setup.h b/arch/nds32/include/asm/setup.h
index 8217bbf..a7d5237 100644
--- a/arch/nds32/include/asm/setup.h
+++ b/arch/nds32/include/asm/setup.h
@@ -155,7 +155,7 @@
#ifdef __KERNEL__
-#define __tag __used __attribute__((__section__(".taglist")))
+#define __tag __used __section(".taglist")
#define __tagtable(tag, fn) \
static struct tagtable __tagtable_##fn __tag = { tag, fn }
@@ -182,8 +182,8 @@
};
#define __early_param(name, fn) \
-static struct early_params __early_##fn __used \
-__attribute__((__section__("__early_param"))) = { name, fn }
+static struct early_params __early_##fn __used \
+__section("__early_param") = { name, fn }
#endif
#endif
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 6a2e88f..1334476 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -49,5 +49,6 @@
source "arch/powerpc/cpu/mpc85xx/Kconfig"
source "arch/powerpc/cpu/mpc86xx/Kconfig"
source "arch/powerpc/cpu/mpc8xx/Kconfig"
+source "arch/powerpc/lib/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 06a20c8..206ee76 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -153,7 +153,6 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
- imply CMD_SATA
imply PANIC_HANG
config TARGET_T1040D4RDB
@@ -162,7 +161,6 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
- imply CMD_SATA
imply PANIC_HANG
config TARGET_T1042RDB
@@ -171,7 +169,6 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
- imply CMD_SATA
config TARGET_T1042D4RDB
bool "Support T1042D4RDB"
@@ -179,7 +176,6 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
- imply CMD_SATA
imply PANIC_HANG
config TARGET_T1042RDB_PI
@@ -188,7 +184,6 @@
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
- imply CMD_SATA
imply PANIC_HANG
config TARGET_T2080QDS
@@ -806,9 +801,7 @@
select FSL_IFC
imply CMD_MTDPARTS
imply CMD_NAND
- imply CMD_SATA
imply CMD_REGINFO
- imply FSL_SATA
config ARCH_T1042
bool
@@ -830,9 +823,7 @@
select FSL_IFC
imply CMD_MTDPARTS
imply CMD_NAND
- imply CMD_SATA
imply CMD_REGINFO
- imply FSL_SATA
config ARCH_T2080
bool
@@ -882,10 +873,8 @@
select SYS_FSL_SEC_COMPAT_4
select SYS_PPC64
select FSL_IFC
- imply CMD_SATA
imply CMD_NAND
imply CMD_REGINFO
- imply FSL_SATA
config ARCH_T4240
bool
diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h
index 445a366..ac8eeb4 100644
--- a/arch/powerpc/include/asm/cache.h
+++ b/arch/powerpc/include/asm/cache.h
@@ -41,8 +41,8 @@
#define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
#else
#define __cacheline_aligned \
- __attribute__((__aligned__(L1_CACHE_BYTES), \
- __section__(".data.cacheline_aligned")))
+ __attribute__((__aligned__(L1_CACHE_BYTES))) \
+ __section(".data.cacheline_aligned")
#endif
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
diff --git a/arch/powerpc/lib/Kconfig b/arch/powerpc/lib/Kconfig
new file mode 100644
index 0000000..b30b5ed
--- /dev/null
+++ b/arch/powerpc/lib/Kconfig
@@ -0,0 +1,9 @@
+config CACHE_FLUSH_WATCHDOG_THRESHOLD
+ int "Bytes to flush between WATCHDOG_RESET calls"
+ default 0
+ help
+ The flush_cache() function periodically, and by default for
+ every cache line, calls WATCHDOG_RESET(). When flushing a
+ large area, that may add a significant amount of
+ overhead. This option allows you to set a threshold for how
+ many bytes to flush between each WATCHDOG_RESET call.
diff --git a/arch/powerpc/lib/cache.c b/arch/powerpc/lib/cache.c
index 3c3c470..1916251 100644
--- a/arch/powerpc/lib/cache.c
+++ b/arch/powerpc/lib/cache.c
@@ -9,10 +9,20 @@
#include <asm/cache.h>
#include <watchdog.h>
+static ulong maybe_watchdog_reset(ulong flushed)
+{
+ flushed += CONFIG_SYS_CACHELINE_SIZE;
+ if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) {
+ WATCHDOG_RESET();
+ flushed = 0;
+ }
+ return flushed;
+}
+
void flush_cache(ulong start_addr, ulong size)
{
-#ifndef CONFIG_5xx
ulong addr, start, end;
+ ulong flushed = 0;
start = start_addr & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
end = start_addr + size - 1;
@@ -20,7 +30,7 @@
for (addr = start; (addr <= end) && (addr >= start);
addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile("dcbst 0,%0" : : "r" (addr) : "memory");
- WATCHDOG_RESET();
+ flushed = maybe_watchdog_reset(flushed);
}
/* wait for all dcbst to complete on bus */
asm volatile("sync" : : : "memory");
@@ -28,10 +38,9 @@
for (addr = start; (addr <= end) && (addr >= start);
addr += CONFIG_SYS_CACHELINE_SIZE) {
asm volatile("icbi 0,%0" : : "r" (addr) : "memory");
- WATCHDOG_RESET();
+ flushed = maybe_watchdog_reset(flushed);
}
asm volatile("sync" : : : "memory");
/* flush prefetch queue */
asm volatile("isync" : : : "memory");
-#endif
}
diff --git a/arch/powerpc/lib/interrupts.c b/arch/powerpc/lib/interrupts.c
index 73f2700..5ba4cd0 100644
--- a/arch/powerpc/lib/interrupts.c
+++ b/arch/powerpc/lib/interrupts.c
@@ -80,7 +80,7 @@
timestamp++;
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
- if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
+ if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
WATCHDOG_RESET ();
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
diff --git a/arch/powerpc/lib/traps.c b/arch/powerpc/lib/traps.c
index c7bce82..ab8ca26 100644
--- a/arch/powerpc/lib/traps.c
+++ b/arch/powerpc/lib/traps.c
@@ -4,6 +4,7 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
+#include <common.h>
#include <init.h>
#include <asm/global_data.h>
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 3f221dc..b3d7fd8 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -20,6 +20,9 @@
config TARGET_SIFIVE_UNLEASHED
bool "Support SiFive Unleashed Board"
+config TARGET_SIFIVE_UNMATCHED
+ bool "Support SiFive Unmatched Board"
+
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
@@ -56,11 +59,13 @@
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
+source "board/sifive/unmatched/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
source "arch/riscv/cpu/fu540/Kconfig"
+source "arch/riscv/cpu/fu740/Kconfig"
source "arch/riscv/cpu/generic/Kconfig"
# architecture-specific options below
@@ -158,11 +163,18 @@
config SIFIVE_CLINT
bool
- depends on RISCV_MMODE || SPL_RISCV_MMODE
+ depends on RISCV_MMODE
help
The SiFive CLINT block holds memory-mapped control and status registers
associated with software and timer interrupts.
+config SPL_SIFIVE_CLINT
+ bool
+ depends on SPL_RISCV_MMODE
+ help
+ The SiFive CLINT block holds memory-mapped control and status registers
+ associated with software and timer interrupts.
+
config ANDES_PLIC
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
@@ -271,6 +283,8 @@
config OF_BOARD_FIXUP
default y if OF_SEPARATE && RISCV_SMODE
+menu "Use assembly optimized implementation of memory routines"
+
config USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy"
default y
@@ -350,3 +364,5 @@
but may increase the binary size.
endmenu
+
+endmenu
diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5..c894ac1 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -17,10 +17,10 @@
* before the bss section is available.
*/
#ifdef CONFIG_OF_PRIOR_STAGE
-phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
+phys_addr_t prior_stage_fdt_address __section(".data");
#endif
#ifndef CONFIG_XIP
-u32 hart_lottery __attribute__((section(".data"))) = 0;
+u32 hart_lottery __section(".data") = 0;
/*
* The main hart running U-Boot has acquired available_harts_lock until it has
@@ -140,3 +140,14 @@
{
return riscv_cpu_probe();
}
+
+/**
+ * harts_early_init() - A callback function called by start.S to configure
+ * feature settings of each hart.
+ *
+ * In a multi-core system, memory access shall be careful here, it shall
+ * take care of race conditions.
+ */
+__weak void harts_early_init(void)
+{
+}
diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig
index 616b256..05463b2 100644
--- a/arch/riscv/cpu/fu540/Kconfig
+++ b/arch/riscv/cpu/fu540/Kconfig
@@ -11,14 +11,14 @@
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply SPL_SIFIVE_CLINT
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
imply SPL_LOAD_FIT
imply SMP
imply CLK_SIFIVE
- imply CLK_SIFIVE_FU540_PRCI
+ imply CLK_SIFIVE_PRCI
imply SIFIVE_SERIAL
imply MACB
imply MII
diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
new file mode 100644
index 0000000..3a5f6e4
--- /dev/null
+++ b/arch/riscv/cpu/fu740/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel@sifive.com>
+
+config SIFIVE_FU740
+ bool
+ select ARCH_EARLY_INIT_R
+ select RAM
+ select SPL_RAM if SPL
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+ imply SPL_SIFIVE_CLINT
+ imply CMD_CPU
+ imply SPL_CPU
+ imply SPL_OPENSBI
+ imply SPL_LOAD_FIT
+ imply SMP
+ imply CLK_SIFIVE
+ imply CLK_SIFIVE_PRCI
+ imply SIFIVE_SERIAL
+ imply MACB
+ imply MII
+ imply SPI
+ imply SPI_SIFIVE
+ imply MMC
+ imply MMC_SPI
+ imply MMC_BROKEN_CD
+ imply CMD_MMC
+ imply DM_GPIO
+ imply SIFIVE_GPIO
+ imply CMD_GPIO
+ imply MISC
+ imply SIFIVE_OTP
+ imply DM_PWM
+ imply PWM_SIFIVE
diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile
new file mode 100644
index 0000000..5ef8ac1
--- /dev/null
+++ b/arch/riscv/cpu/fu740/Makefile
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 SiFive, Inc
+# Pragnesh Patel <pragnesh.patel@sifive.com>
+
+ifeq ($(CONFIG_SPL_BUILD),y)
+obj-y += spl.o
+else
+obj-y += dram.o
+obj-y += cpu.o
+obj-y += cache.o
+endif
diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
new file mode 100644
index 0000000..680955c
--- /dev/null
+++ b/arch/riscv/cpu/fu740/cache.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <asm/global_data.h>
+
+/* Register offsets */
+#define L2_CACHE_CONFIG 0x000
+#define L2_CACHE_ENABLE 0x008
+
+#define MASK_NUM_WAYS GENMASK(15, 8)
+#define NUM_WAYS_SHIFT 8
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int cache_enable_ways(void)
+{
+ const void *blob = gd->fdt_blob;
+ int node;
+ fdt_addr_t base;
+ u32 config;
+ u32 ways;
+
+ volatile u32 *enable;
+
+ node = fdt_node_offset_by_compatible(blob, -1,
+ "sifive,fu740-c000-ccache");
+
+ if (node < 0)
+ return node;
+
+ base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
+ NULL, false);
+ if (base == FDT_ADDR_T_NONE)
+ return FDT_ADDR_T_NONE;
+
+ config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
+ ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
+
+ enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
+
+ /* memory barrier */
+ mb();
+ (*enable) = ways - 1;
+ /* memory barrier */
+ mb();
+ return 0;
+}
diff --git a/arch/riscv/cpu/fu740/cpu.c b/arch/riscv/cpu/fu740/cpu.c
new file mode 100644
index 0000000..f13c189
--- /dev/null
+++ b/arch/riscv/cpu/fu740/cpu.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <irq_func.h>
+#include <asm/cache.h>
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+ cache_flush();
+
+ return 0;
+}
diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c
new file mode 100644
index 0000000..1dc77ef
--- /dev/null
+++ b/arch/riscv/cpu/fu740/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+ /*
+ * Ensure that we run from first 4GB so that all
+ * addresses used by U-Boot are 32bit addresses.
+ *
+ * This in-turn ensures that 32bit DMA capable
+ * devices work fine because DMA mapping APIs will
+ * provide 32bit DMA addresses only.
+ */
+ if (gd->ram_top > SZ_4G)
+ return SZ_4G;
+#endif
+ return gd->ram_top;
+}
diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c
new file mode 100644
index 0000000..55e3034
--- /dev/null
+++ b/arch/riscv/cpu/fu740/spl.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020-201 SiFive, Inc
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <dm.h>
+#include <log.h>
+#include <asm/csr.h>
+
+#define CSR_U74_FEATURE_DISABLE 0x7c1
+
+int spl_soc_init(void)
+{
+ int ret;
+ struct udevice *dev;
+
+ /* DDR init */
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+void harts_early_init(void)
+{
+ /*
+ * Feature Disable CSR
+ *
+ * Clear feature disable CSR to '0' to turn on all features for
+ * each core. This operation must be in M-mode.
+ */
+ if (CONFIG_IS_ENABLED(RISCV_MMODE))
+ csr_write(CSR_U74_FEATURE_DISABLE, 0);
+}
diff --git a/arch/riscv/cpu/generic/Kconfig b/arch/riscv/cpu/generic/Kconfig
index 198e36e..e025134 100644
--- a/arch/riscv/cpu/generic/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -4,11 +4,13 @@
config GENERIC_RISCV
bool
+ select BINMAN if SPL
select ARCH_EARLY_INIT_R
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
- imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
+ imply SIFIVE_CLINT if RISCV_MMODE
+ imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
imply CMD_CPU
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509..308b0a9 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,10 @@
mv sp, a0
#endif
+ /* Configure proprietary settings and customized CSRs of harts */
+call_harts_early_init:
+ jal harts_early_init
+
#ifndef CONFIG_XIP
/*
* Pick hart to initialize global data and run U-Boot. The other harts
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 8138d89..7778874 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,9 +1,11 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
+dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
+dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
-dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
targets += $(dtb-y)
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 3f8525f..a0ab5e9 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -1,5 +1,7 @@
/dts-v1/;
+#include "binman.dtsi"
+
/ {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 482c707..f654f48 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -1,5 +1,7 @@
/dts-v1/;
+#include "binman.dtsi"
+
/ {
#address-cells = <2>;
#size-cells = <2>;
diff --git a/arch/riscv/dts/binman.dtsi b/arch/riscv/dts/binman.dtsi
new file mode 100644
index 0000000..d26cfdb
--- /dev/null
+++ b/arch/riscv/dts/binman.dtsi
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <config.h>
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load OpenSBI before U-Boot";
+ #address-cells = <1>;
+ fit,fdt-list = "of-list";
+
+ images {
+ uboot {
+ description = "U-Boot";
+ type = "standalone";
+ os = "U-Boot";
+ arch = "riscv";
+ compression = "none";
+ load = <CONFIG_SYS_TEXT_BASE>;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ opensbi {
+ description = "OpenSBI fw_dynamic Firmware";
+ type = "firmware";
+ os = "opensbi";
+ arch = "riscv";
+ compression = "none";
+ load = <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+ entry = <CONFIG_SPL_OPENSBI_LOAD_ADDR>;
+
+ opensbi_blob: opensbi {
+ filename = "fw_dynamic.bin";
+ };
+ };
+
+#ifndef CONFIG_OF_PRIOR_STAGE
+ @fdt-SEQ {
+ description = "NAME";
+ type = "flat_dt";
+ compression = "none";
+ };
+#endif
+ };
+
+ configurations {
+ default = "conf-1";
+
+#ifndef CONFIG_OF_PRIOR_STAGE
+ @conf-SEQ {
+#else
+ conf-1 {
+#endif
+ description = "NAME";
+ firmware = "opensbi";
+ loadables = "uboot";
+#ifndef CONFIG_OF_PRIOR_STAGE
+ fdt = "fdt-SEQ";
+#endif
+ };
+ };
+ };
+ };
+};
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi b/arch/riscv/dts/fu740-c000-u-boot.dtsi
new file mode 100644
index 0000000..a5d0688
--- /dev/null
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020-2021 SiFive, Inc
+ */
+
+#include <dt-bindings/reset/sifive-fu740-prci.h>
+
+/ {
+ cpus {
+ assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+ assigned-clock-rates = <1200000000>;
+ u-boot,dm-spl;
+ cpu0: cpu@0 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ status = "okay";
+ cpu0_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu1: cpu@1 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu1_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu2: cpu@2 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu2_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu3: cpu@3 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu3_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ cpu4: cpu@4 {
+ clocks = <&prci PRCI_CLK_COREPLL>;
+ u-boot,dm-spl;
+ cpu4_intc: interrupt-controller {
+ u-boot,dm-spl;
+ };
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+ clint: clint@2000000 {
+ compatible = "riscv,clint0";
+ interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
+ &cpu1_intc 3 &cpu1_intc 7
+ &cpu2_intc 3 &cpu2_intc 7
+ &cpu3_intc 3 &cpu3_intc 7
+ &cpu4_intc 3 &cpu4_intc 7>;
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ u-boot,dm-spl;
+ };
+ prci: clock-controller@10000000 {
+ #reset-cells = <1>;
+ resets = <&prci PRCI_RST_DDR_CTRL_N>,
+ <&prci PRCI_RST_DDR_AXI_N>,
+ <&prci PRCI_RST_DDR_AHB_N>,
+ <&prci PRCI_RST_DDR_PHY_N>,
+ <&prci PRCI_RST_GEMGXL_N>,
+ <&prci PRCI_RST_CLTX_N>;
+ reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
+ "ddr_phy", "gemgxl_reset", "cltx_reset";
+ };
+ dmc: dmc@100b0000 {
+ compatible = "sifive,fu740-c000-ddr";
+ reg = <0x0 0x100b0000 0x0 0x0800
+ 0x0 0x100b2000 0x0 0x2000
+ 0x0 0x100b8000 0x0 0x1000>;
+ clocks = <&prci PRCI_CLK_DDRPLL>;
+ clock-frequency = <933333324>;
+ u-boot,dm-spl;
+ };
+ };
+};
+
+&prci {
+ u-boot,dm-spl;
+};
+
+&uart0 {
+ u-boot,dm-spl;
+};
+
+&spi0 {
+ u-boot,dm-spl;
+};
+
+ð0 {
+ assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+ assigned-clock-rates = <125125000>;
+};
+
+&ccache {
+ status = "okay";
+};
diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
new file mode 100644
index 0000000..649efe4
--- /dev/null
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 SiFive, Inc */
+
+/dts-v1/;
+
+#include <dt-bindings/clock/sifive-fu740-prci.h>
+#include <dt-bindings/reset/sifive-fu740-prci.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu740-c000", "sifive,fu740";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ ethernet0 = ð0;
+ };
+
+ chosen {
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ compatible = "sifive,bullet0", "riscv";
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <16384>;
+ next-level-cache = <&ccache>;
+ reg = <0x0>;
+ riscv,isa = "rv64imac";
+ status = "disabled";
+ cpu0_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu1: cpu@1 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x1>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu1_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu2: cpu@2 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x2>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu2_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu3: cpu@3 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x3>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu3_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ cpu4: cpu@4 {
+ compatible = "sifive,bullet0", "riscv";
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <128>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ reg = <0x4>;
+ riscv,isa = "rv64imafdc";
+ tlb-split;
+ cpu4_intc: interrupt-controller {
+ #interrupt-cells = <1>;
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ };
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
+ ranges;
+ plic0: interrupt-controller@c000000 {
+ #interrupt-cells = <1>;
+ compatible = "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ riscv,ndev = <69>;
+ interrupt-controller;
+ interrupts-extended = <
+ &cpu0_intc 0xffffffff
+ &cpu1_intc 0xffffffff &cpu1_intc 9
+ &cpu2_intc 0xffffffff &cpu2_intc 9
+ &cpu3_intc 0xffffffff &cpu3_intc 9
+ &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ };
+ prci: clock-controller@10000000 {
+ compatible = "sifive,fu740-c000-prci";
+ reg = <0x0 0x10000000 0x0 0x1000>;
+ clocks = <&hfclk>, <&rtcclk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+ uart0: serial@10010000 {
+ compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10010000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <39>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ uart1: serial@10011000 {
+ compatible = "sifive,fu740-c000-uart", "sifive,uart0";
+ reg = <0x0 0x10011000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <40>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ i2c0: i2c@10030000 {
+ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10030000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <52>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ i2c1: i2c@10031000 {
+ compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
+ reg = <0x0 0x10031000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ reg-shift = <2>;
+ reg-io-width = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi0: spi@10040000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10040000 0x0 0x1000
+ 0x0 0x20000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <41>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ qspi1: spi@10041000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10041000 0x0 0x1000
+ 0x0 0x30000000 0x0 0x10000000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <42>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ spi0: spi@10050000 {
+ compatible = "sifive,fu740-c000-spi", "sifive,spi0";
+ reg = <0x0 0x10050000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <43>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <55>;
+ reg = <0x0 0x10090000 0x0 0x2000
+ 0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ pwm0: pwm@10020000 {
+ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10020000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <44 45 46 47>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ pwm1: pwm@10021000 {
+ compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
+ reg = <0x0 0x10021000 0x0 0x1000>;
+ interrupt-parent = <&plic0>;
+ interrupts = <48 49 50 51>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ ccache: cache-controller@2010000 {
+ compatible = "sifive,fu740-c000-ccache", "cache";
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ interrupt-parent = <&plic0>;
+ interrupts = <19 21 22 20>;
+ reg = <0x0 0x2010000 0x0 0x1000>;
+ };
+ gpio: gpio@10060000 {
+ compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
+ interrupt-parent = <&plic0>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>, <31>, <32>, <33>, <34>, <35>, <36>,
+ <37>, <38>;
+ reg = <0x0 0x10060000 0x0 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&prci PRCI_CLK_PCLK>;
+ status = "disabled";
+ };
+ pcie@e00000000 {
+ #address-cells = <3>;
+ #interrupt-cells = <1>;
+ #num-lanes = <8>;
+ #size-cells = <2>;
+ compatible = "sifive,fu740-pcie";
+ reg = <0xe 0x00000000 0x1 0x0
+ 0xd 0xf0000000 0x0 0x10000000
+ 0x0 0x100d0000 0x0 0x1000>;
+ reg-names = "dbi", "config", "mgmt";
+ device_type = "pci";
+ dma-coherent;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000
+ 0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000
+ 0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000
+ 0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;
+ num-lanes = <0x8>;
+ interrupts = <56 57 58 59 60 61 62 63 64>;
+ interrupt-names = "msi", "inta", "intb", "intc", "intd";
+ interrupt-parent = <&plic0>;
+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+ interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
+ <0x0 0x0 0x0 0x2 &plic0 58>,
+ <0x0 0x0 0x0 0x3 &plic0 59>,
+ <0x0 0x0 0x0 0x4 &plic0 60>;
+ pwren-gpios = <&gpio 5 0>;
+ reset-gpios = <&gpio 8 0>;
+ clocks = <&prci PRCI_CLK_PCIEAUX>;
+ clock-names = "pcieaux";
+ resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;
+ reset-names = "rst_n";
+
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
new file mode 100644
index 0000000..fc3dfd1
--- /dev/null
+++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
@@ -0,0 +1,1489 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020-2021 SiFive, Inc
+ */
+
+&dmc {
+ sifive,ddr-params = <
+ 0x00000a00 /* DENALI_CTL_00_DATA */
+ 0x00000000 /* DENALI_CTL_01_DATA */
+ 0x00000000 /* DENALI_CTL_02_DATA */
+ 0x00000000 /* DENALI_CTL_03_DATA */
+ 0x00000000 /* DENALI_CTL_04_DATA */
+ 0x00000000 /* DENALI_CTL_05_DATA */
+ 0x0000000a /* DENALI_CTL_06_DATA */
+ 0x0002d362 /* DENALI_CTL_07_DATA */
+ 0x00071073 /* DENALI_CTL_08_DATA */
+ 0x0a1c0255 /* DENALI_CTL_09_DATA */
+ 0x1c1c0400 /* DENALI_CTL_10_DATA */
+ 0x0404c90b /* DENALI_CTL_11_DATA */
+ 0x2b050405 /* DENALI_CTL_12_DATA */
+ 0x0d0c081e /* DENALI_CTL_13_DATA */
+ 0x08090914 /* DENALI_CTL_14_DATA */
+ 0x00fde718 /* DENALI_CTL_15_DATA */
+ 0x00180a05 /* DENALI_CTL_16_DATA */
+ 0x008b130d /* DENALI_CTL_17_DATA */
+ 0x01000118 /* DENALI_CTL_18_DATA */
+ 0x0d032001 /* DENALI_CTL_19_DATA */
+ 0x00000000 /* DENALI_CTL_20_DATA */
+ 0x00000101 /* DENALI_CTL_21_DATA */
+ 0x00000000 /* DENALI_CTL_22_DATA */
+ 0x0a000000 /* DENALI_CTL_23_DATA */
+ 0x00000000 /* DENALI_CTL_24_DATA */
+ 0x01450100 /* DENALI_CTL_25_DATA */
+ 0x00001c36 /* DENALI_CTL_26_DATA */
+ 0x00000005 /* DENALI_CTL_27_DATA */
+ 0x00170006 /* DENALI_CTL_28_DATA */
+ 0x014e0400 /* DENALI_CTL_29_DATA */
+ 0x03010000 /* DENALI_CTL_30_DATA */
+ 0x000a0e00 /* DENALI_CTL_31_DATA */
+ 0x04030200 /* DENALI_CTL_32_DATA */
+ 0x0000031f /* DENALI_CTL_33_DATA */
+ 0x00070004 /* DENALI_CTL_34_DATA */
+ 0x00000000 /* DENALI_CTL_35_DATA */
+ 0x00000000 /* DENALI_CTL_36_DATA */
+ 0x00000000 /* DENALI_CTL_37_DATA */
+ 0x00000000 /* DENALI_CTL_38_DATA */
+ 0x00000000 /* DENALI_CTL_39_DATA */
+ 0x00000000 /* DENALI_CTL_40_DATA */
+ 0x00000000 /* DENALI_CTL_41_DATA */
+ 0x00000000 /* DENALI_CTL_42_DATA */
+ 0x00000000 /* DENALI_CTL_43_DATA */
+ 0x00000000 /* DENALI_CTL_44_DATA */
+ 0x00000000 /* DENALI_CTL_45_DATA */
+ 0x00000000 /* DENALI_CTL_46_DATA */
+ 0x00000000 /* DENALI_CTL_47_DATA */
+ 0x00000000 /* DENALI_CTL_48_DATA */
+ 0x00000000 /* DENALI_CTL_49_DATA */
+ 0x00000000 /* DENALI_CTL_50_DATA */
+ 0x00000000 /* DENALI_CTL_51_DATA */
+ 0x00000000 /* DENALI_CTL_52_DATA */
+ 0x00000000 /* DENALI_CTL_53_DATA */
+ 0x00000000 /* DENALI_CTL_54_DATA */
+ 0x00000000 /* DENALI_CTL_55_DATA */
+ 0x00000000 /* DENALI_CTL_56_DATA */
+ 0x00000000 /* DENALI_CTL_57_DATA */
+ 0x00000000 /* DENALI_CTL_58_DATA */
+ 0x00000000 /* DENALI_CTL_59_DATA */
+ 0x00000424 /* DENALI_CTL_60_DATA */
+ 0x00000201 /* DENALI_CTL_61_DATA */
+ 0x00001008 /* DENALI_CTL_62_DATA */
+ 0x00000000 /* DENALI_CTL_63_DATA */
+ 0x00000200 /* DENALI_CTL_64_DATA */
+ 0x00000800 /* DENALI_CTL_65_DATA */
+ 0x00000481 /* DENALI_CTL_66_DATA */
+ 0x00000400 /* DENALI_CTL_67_DATA */
+ 0x00000424 /* DENALI_CTL_68_DATA */
+ 0x00000201 /* DENALI_CTL_69_DATA */
+ 0x00001008 /* DENALI_CTL_70_DATA */
+ 0x00000000 /* DENALI_CTL_71_DATA */
+ 0x00000200 /* DENALI_CTL_72_DATA */
+ 0x00000800 /* DENALI_CTL_73_DATA */
+ 0x00000481 /* DENALI_CTL_74_DATA */
+ 0x00000400 /* DENALI_CTL_75_DATA */
+ 0x01010000 /* DENALI_CTL_76_DATA */
+ 0x00000000 /* DENALI_CTL_77_DATA */
+ 0x00000000 /* DENALI_CTL_78_DATA */
+ 0x00000000 /* DENALI_CTL_79_DATA */
+ 0x00000000 /* DENALI_CTL_80_DATA */
+ 0x00000000 /* DENALI_CTL_81_DATA */
+ 0x00000000 /* DENALI_CTL_82_DATA */
+ 0x00000000 /* DENALI_CTL_83_DATA */
+ 0x00000000 /* DENALI_CTL_84_DATA */
+ 0x00000000 /* DENALI_CTL_85_DATA */
+ 0x00000000 /* DENALI_CTL_86_DATA */
+ 0x00000000 /* DENALI_CTL_87_DATA */
+ 0x00000000 /* DENALI_CTL_88_DATA */
+ 0x00000000 /* DENALI_CTL_89_DATA */
+ 0x00000000 /* DENALI_CTL_90_DATA */
+ 0x00000000 /* DENALI_CTL_91_DATA */
+ 0x00000000 /* DENALI_CTL_92_DATA */
+ 0x00000000 /* DENALI_CTL_93_DATA */
+ 0x00000000 /* DENALI_CTL_94_DATA */
+ 0x00000000 /* DENALI_CTL_95_DATA */
+ 0x00000000 /* DENALI_CTL_96_DATA */
+ 0x00000000 /* DENALI_CTL_97_DATA */
+ 0x00000000 /* DENALI_CTL_98_DATA */
+ 0x00000000 /* DENALI_CTL_99_DATA */
+ 0x00000000 /* DENALI_CTL_100_DATA */
+ 0x00000000 /* DENALI_CTL_101_DATA */
+ 0x00000000 /* DENALI_CTL_102_DATA */
+ 0x00000000 /* DENALI_CTL_103_DATA */
+ 0x00000000 /* DENALI_CTL_104_DATA */
+ 0x00000003 /* DENALI_CTL_105_DATA */
+ 0x00000000 /* DENALI_CTL_106_DATA */
+ 0x00000000 /* DENALI_CTL_107_DATA */
+ 0x00000000 /* DENALI_CTL_108_DATA */
+ 0x00000000 /* DENALI_CTL_109_DATA */
+ 0x01000000 /* DENALI_CTL_110_DATA */
+ 0x00040000 /* DENALI_CTL_111_DATA */
+ 0x00800200 /* DENALI_CTL_112_DATA */
+ 0x00000200 /* DENALI_CTL_113_DATA */
+ 0x00000040 /* DENALI_CTL_114_DATA */
+ 0x01000100 /* DENALI_CTL_115_DATA */
+ 0x0a000002 /* DENALI_CTL_116_DATA */
+ 0x0101ffff /* DENALI_CTL_117_DATA */
+ 0x01010101 /* DENALI_CTL_118_DATA */
+ 0x01010101 /* DENALI_CTL_119_DATA */
+ 0x0000010b /* DENALI_CTL_120_DATA */
+ 0x00000c03 /* DENALI_CTL_121_DATA */
+ 0x00000000 /* DENALI_CTL_122_DATA */
+ 0x00000000 /* DENALI_CTL_123_DATA */
+ 0x00000000 /* DENALI_CTL_124_DATA */
+ 0x00000000 /* DENALI_CTL_125_DATA */
+ 0x00030300 /* DENALI_CTL_126_DATA */
+ 0x00000000 /* DENALI_CTL_127_DATA */
+ 0x00010101 /* DENALI_CTL_128_DATA */
+ 0x00000000 /* DENALI_CTL_129_DATA */
+ 0x00000000 /* DENALI_CTL_130_DATA */
+ 0x00000000 /* DENALI_CTL_131_DATA */
+ 0x00000000 /* DENALI_CTL_132_DATA */
+ 0x00000000 /* DENALI_CTL_133_DATA */
+ 0x00000000 /* DENALI_CTL_134_DATA */
+ 0x00000000 /* DENALI_CTL_135_DATA */
+ 0x00000000 /* DENALI_CTL_136_DATA */
+ 0x00000000 /* DENALI_CTL_137_DATA */
+ 0x00000000 /* DENALI_CTL_138_DATA */
+ 0x00000000 /* DENALI_CTL_139_DATA */
+ 0x00000000 /* DENALI_CTL_140_DATA */
+ 0x00000000 /* DENALI_CTL_141_DATA */
+ 0x00000000 /* DENALI_CTL_142_DATA */
+ 0x00000000 /* DENALI_CTL_143_DATA */
+ 0x00000000 /* DENALI_CTL_144_DATA */
+ 0x00000000 /* DENALI_CTL_145_DATA */
+ 0x00000000 /* DENALI_CTL_146_DATA */
+ 0x00000000 /* DENALI_CTL_147_DATA */
+ 0x00000000 /* DENALI_CTL_148_DATA */
+ 0x00000000 /* DENALI_CTL_149_DATA */
+ 0x00000000 /* DENALI_CTL_150_DATA */
+ 0x00000000 /* DENALI_CTL_151_DATA */
+ 0x00000000 /* DENALI_CTL_152_DATA */
+ 0x00000000 /* DENALI_CTL_153_DATA */
+ 0x00000000 /* DENALI_CTL_154_DATA */
+ 0x00000000 /* DENALI_CTL_155_DATA */
+ 0x00000000 /* DENALI_CTL_156_DATA */
+ 0x00000000 /* DENALI_CTL_157_DATA */
+ 0x00000000 /* DENALI_CTL_158_DATA */
+ 0x00000000 /* DENALI_CTL_159_DATA */
+ 0x00000000 /* DENALI_CTL_160_DATA */
+ 0x02010102 /* DENALI_CTL_161_DATA */
+ 0x0108070d /* DENALI_CTL_162_DATA */
+ 0x05050300 /* DENALI_CTL_163_DATA */
+ 0x04000503 /* DENALI_CTL_164_DATA */
+ 0x00000000 /* DENALI_CTL_165_DATA */
+ 0x00000000 /* DENALI_CTL_166_DATA */
+ 0x00000000 /* DENALI_CTL_167_DATA */
+ 0x00000000 /* DENALI_CTL_168_DATA */
+ 0x280d0000 /* DENALI_CTL_169_DATA */
+ 0x01000000 /* DENALI_CTL_170_DATA */
+ 0x00000000 /* DENALI_CTL_171_DATA */
+ 0x00030001 /* DENALI_CTL_172_DATA */
+ 0x00000000 /* DENALI_CTL_173_DATA */
+ 0x00000000 /* DENALI_CTL_174_DATA */
+ 0x00000000 /* DENALI_CTL_175_DATA */
+ 0x00000000 /* DENALI_CTL_176_DATA */
+ 0x00000000 /* DENALI_CTL_177_DATA */
+ 0x00000000 /* DENALI_CTL_178_DATA */
+ 0x00000000 /* DENALI_CTL_179_DATA */
+ 0x00000000 /* DENALI_CTL_180_DATA */
+ 0x01000000 /* DENALI_CTL_181_DATA */
+ 0x00000001 /* DENALI_CTL_182_DATA */
+ 0x00000100 /* DENALI_CTL_183_DATA */
+ 0x00010303 /* DENALI_CTL_184_DATA */
+ 0x67676701 /* DENALI_CTL_185_DATA */
+ 0x67676767 /* DENALI_CTL_186_DATA */
+ 0x67676767 /* DENALI_CTL_187_DATA */
+ 0x67676767 /* DENALI_CTL_188_DATA */
+ 0x67676767 /* DENALI_CTL_189_DATA */
+ 0x67676767 /* DENALI_CTL_190_DATA */
+ 0x67676767 /* DENALI_CTL_191_DATA */
+ 0x67676767 /* DENALI_CTL_192_DATA */
+ 0x67676767 /* DENALI_CTL_193_DATA */
+ 0x01000067 /* DENALI_CTL_194_DATA */
+ 0x00000001 /* DENALI_CTL_195_DATA */
+ 0x00000101 /* DENALI_CTL_196_DATA */
+ 0x00000000 /* DENALI_CTL_197_DATA */
+ 0x00000000 /* DENALI_CTL_198_DATA */
+ 0x00000000 /* DENALI_CTL_199_DATA */
+ 0x00000000 /* DENALI_CTL_200_DATA */
+ 0x00000000 /* DENALI_CTL_201_DATA */
+ 0x00000000 /* DENALI_CTL_202_DATA */
+ 0x00000000 /* DENALI_CTL_203_DATA */
+ 0x00000000 /* DENALI_CTL_204_DATA */
+ 0x00000000 /* DENALI_CTL_205_DATA */
+ 0x00000000 /* DENALI_CTL_206_DATA */
+ 0x00000000 /* DENALI_CTL_207_DATA */
+ 0x00000001 /* DENALI_CTL_208_DATA */
+ 0x00000000 /* DENALI_CTL_209_DATA */
+ 0x007fffff /* DENALI_CTL_210_DATA */
+ 0x00000000 /* DENALI_CTL_211_DATA */
+ 0x007fffff /* DENALI_CTL_212_DATA */
+ 0x00000000 /* DENALI_CTL_213_DATA */
+ 0x007fffff /* DENALI_CTL_214_DATA */
+ 0x00000000 /* DENALI_CTL_215_DATA */
+ 0x007fffff /* DENALI_CTL_216_DATA */
+ 0x00000000 /* DENALI_CTL_217_DATA */
+ 0x007fffff /* DENALI_CTL_218_DATA */
+ 0x00000000 /* DENALI_CTL_219_DATA */
+ 0x007fffff /* DENALI_CTL_220_DATA */
+ 0x00000000 /* DENALI_CTL_221_DATA */
+ 0x007fffff /* DENALI_CTL_222_DATA */
+ 0x00000000 /* DENALI_CTL_223_DATA */
+ 0x037fffff /* DENALI_CTL_224_DATA */
+ 0xffffffff /* DENALI_CTL_225_DATA */
+ 0x000f000f /* DENALI_CTL_226_DATA */
+ 0x00ffff03 /* DENALI_CTL_227_DATA */
+ 0x000fffff /* DENALI_CTL_228_DATA */
+ 0x0003000f /* DENALI_CTL_229_DATA */
+ 0xffffffff /* DENALI_CTL_230_DATA */
+ 0x000f000f /* DENALI_CTL_231_DATA */
+ 0x00ffff03 /* DENALI_CTL_232_DATA */
+ 0x000fffff /* DENALI_CTL_233_DATA */
+ 0x0003000f /* DENALI_CTL_234_DATA */
+ 0xffffffff /* DENALI_CTL_235_DATA */
+ 0x000f000f /* DENALI_CTL_236_DATA */
+ 0x00ffff03 /* DENALI_CTL_237_DATA */
+ 0x000fffff /* DENALI_CTL_238_DATA */
+ 0x0003000f /* DENALI_CTL_239_DATA */
+ 0xffffffff /* DENALI_CTL_240_DATA */
+ 0x000f000f /* DENALI_CTL_241_DATA */
+ 0x00ffff03 /* DENALI_CTL_242_DATA */
+ 0x000fffff /* DENALI_CTL_243_DATA */
+ 0x6407000f /* DENALI_CTL_244_DATA */
+ 0x01640001 /* DENALI_CTL_245_DATA */
+ 0x00000000 /* DENALI_CTL_246_DATA */
+ 0x00000000 /* DENALI_CTL_247_DATA */
+ 0x00001800 /* DENALI_CTL_248_DATA */
+ 0x00386c05 /* DENALI_CTL_249_DATA */
+ 0x02000200 /* DENALI_CTL_250_DATA */
+ 0x02000200 /* DENALI_CTL_251_DATA */
+ 0x0000386c /* DENALI_CTL_252_DATA */
+ 0x00023438 /* DENALI_CTL_253_DATA */
+ 0x02020d0f /* DENALI_CTL_254_DATA */
+ 0x00140303 /* DENALI_CTL_255_DATA */
+ 0x00000000 /* DENALI_CTL_256_DATA */
+ 0x00000000 /* DENALI_CTL_257_DATA */
+ 0x00001403 /* DENALI_CTL_258_DATA */
+ 0x00000000 /* DENALI_CTL_259_DATA */
+ 0x00000000 /* DENALI_CTL_260_DATA */
+ 0x00000000 /* DENALI_CTL_261_DATA */
+ 0x00000000 /* DENALI_CTL_262_DATA */
+ 0x0c010000 /* DENALI_CTL_263_DATA */
+ 0x00000008 /* DENALI_CTL_264_DATA */
+ 0x01375642 /* DENALI_PHY_00_DATA */
+ 0x0004c008 /* DENALI_PHY_01_DATA */
+ 0x000000da /* DENALI_PHY_02_DATA */
+ 0x00000000 /* DENALI_PHY_03_DATA */
+ 0x00000000 /* DENALI_PHY_04_DATA */
+ 0x00010000 /* DENALI_PHY_05_DATA */
+ 0x01DDDD90 /* DENALI_PHY_06_DATA */
+ 0x01DDDD90 /* DENALI_PHY_07_DATA */
+ 0x01030001 /* DENALI_PHY_08_DATA */
+ 0x01000000 /* DENALI_PHY_09_DATA */
+ 0x00c00000 /* DENALI_PHY_10_DATA */
+ 0x00000007 /* DENALI_PHY_11_DATA */
+ 0x00000000 /* DENALI_PHY_12_DATA */
+ 0x00000000 /* DENALI_PHY_13_DATA */
+ 0x04000408 /* DENALI_PHY_14_DATA */
+ 0x00000408 /* DENALI_PHY_15_DATA */
+ 0x00e4e400 /* DENALI_PHY_16_DATA */
+ 0x00000000 /* DENALI_PHY_17_DATA */
+ 0x00000000 /* DENALI_PHY_18_DATA */
+ 0x00000000 /* DENALI_PHY_19_DATA */
+ 0x00000000 /* DENALI_PHY_20_DATA */
+ 0x00000000 /* DENALI_PHY_21_DATA */
+ 0x00000000 /* DENALI_PHY_22_DATA */
+ 0x00000000 /* DENALI_PHY_23_DATA */
+ 0x00000000 /* DENALI_PHY_24_DATA */
+ 0x00000000 /* DENALI_PHY_25_DATA */
+ 0x00000000 /* DENALI_PHY_26_DATA */
+ 0x00000000 /* DENALI_PHY_27_DATA */
+ 0x00000000 /* DENALI_PHY_28_DATA */
+ 0x00000000 /* DENALI_PHY_29_DATA */
+ 0x00000000 /* DENALI_PHY_30_DATA */
+ 0x00000000 /* DENALI_PHY_31_DATA */
+ 0x00000000 /* DENALI_PHY_32_DATA */
+ 0x00200000 /* DENALI_PHY_33_DATA */
+ 0x00000000 /* DENALI_PHY_34_DATA */
+ 0x00000000 /* DENALI_PHY_35_DATA */
+ 0x00000000 /* DENALI_PHY_36_DATA */
+ 0x00000000 /* DENALI_PHY_37_DATA */
+ 0x00000000 /* DENALI_PHY_38_DATA */
+ 0x00000000 /* DENALI_PHY_39_DATA */
+ 0x02800280 /* DENALI_PHY_40_DATA */
+ 0x02800280 /* DENALI_PHY_41_DATA */
+ 0x02800280 /* DENALI_PHY_42_DATA */
+ 0x02800280 /* DENALI_PHY_43_DATA */
+ 0x00000280 /* DENALI_PHY_44_DATA */
+ 0x00000000 /* DENALI_PHY_45_DATA */
+ 0x00000000 /* DENALI_PHY_46_DATA */
+ 0x00000000 /* DENALI_PHY_47_DATA */
+ 0x00000000 /* DENALI_PHY_48_DATA */
+ 0x00000000 /* DENALI_PHY_49_DATA */
+ 0x00800080 /* DENALI_PHY_50_DATA */
+ 0x00800080 /* DENALI_PHY_51_DATA */
+ 0x00800080 /* DENALI_PHY_52_DATA */
+ 0x00800080 /* DENALI_PHY_53_DATA */
+ 0x00800080 /* DENALI_PHY_54_DATA */
+ 0x00800080 /* DENALI_PHY_55_DATA */
+ 0x00800080 /* DENALI_PHY_56_DATA */
+ 0x00800080 /* DENALI_PHY_57_DATA */
+ 0x00800080 /* DENALI_PHY_58_DATA */
+ 0x000100da /* DENALI_PHY_59_DATA */
+ 0x01ff0010 /* DENALI_PHY_60_DATA */
+ 0x00000000 /* DENALI_PHY_61_DATA */
+ 0x00000000 /* DENALI_PHY_62_DATA */
+ 0x00000002 /* DENALI_PHY_63_DATA */
+ 0x51313152 /* DENALI_PHY_64_DATA */
+ 0x80013130 /* DENALI_PHY_65_DATA */
+ 0x02000080 /* DENALI_PHY_66_DATA */
+ 0x00100001 /* DENALI_PHY_67_DATA */
+ 0x0c064208 /* DENALI_PHY_68_DATA */
+ 0x000f0c0f /* DENALI_PHY_69_DATA */
+ 0x01000140 /* DENALI_PHY_70_DATA */
+ 0x0000000c /* DENALI_PHY_71_DATA */
+ 0x00000000 /* DENALI_PHY_72_DATA */
+ 0x00000000 /* DENALI_PHY_73_DATA */
+ 0x00000000 /* DENALI_PHY_74_DATA */
+ 0x00000000 /* DENALI_PHY_75_DATA */
+ 0x00000000 /* DENALI_PHY_76_DATA */
+ 0x00000000 /* DENALI_PHY_77_DATA */
+ 0x00000000 /* DENALI_PHY_78_DATA */
+ 0x00000000 /* DENALI_PHY_79_DATA */
+ 0x00000000 /* DENALI_PHY_80_DATA */
+ 0x00000000 /* DENALI_PHY_81_DATA */
+ 0x00000000 /* DENALI_PHY_82_DATA */
+ 0x00000000 /* DENALI_PHY_83_DATA */
+ 0x00000000 /* DENALI_PHY_84_DATA */
+ 0x00000000 /* DENALI_PHY_85_DATA */
+ 0x00000000 /* DENALI_PHY_86_DATA */
+ 0x00000000 /* DENALI_PHY_87_DATA */
+ 0x00000000 /* DENALI_PHY_88_DATA */
+ 0x00000000 /* DENALI_PHY_89_DATA */
+ 0x00000000 /* DENALI_PHY_90_DATA */
+ 0x00000000 /* DENALI_PHY_91_DATA */
+ 0x00000000 /* DENALI_PHY_92_DATA */
+ 0x00000000 /* DENALI_PHY_93_DATA */
+ 0x00000000 /* DENALI_PHY_94_DATA */
+ 0x00000000 /* DENALI_PHY_95_DATA */
+ 0x00000000 /* DENALI_PHY_96_DATA */
+ 0x00000000 /* DENALI_PHY_97_DATA */
+ 0x00000000 /* DENALI_PHY_98_DATA */
+ 0x00000000 /* DENALI_PHY_99_DATA */
+ 0x00000000 /* DENALI_PHY_100_DATA */
+ 0x00000000 /* DENALI_PHY_101_DATA */
+ 0x00000000 /* DENALI_PHY_102_DATA */
+ 0x00000000 /* DENALI_PHY_103_DATA */
+ 0x00000000 /* DENALI_PHY_104_DATA */
+ 0x00000000 /* DENALI_PHY_105_DATA */
+ 0x00000000 /* DENALI_PHY_106_DATA */
+ 0x00000000 /* DENALI_PHY_107_DATA */
+ 0x00000000 /* DENALI_PHY_108_DATA */
+ 0x00000000 /* DENALI_PHY_109_DATA */
+ 0x00000000 /* DENALI_PHY_110_DATA */
+ 0x00000000 /* DENALI_PHY_111_DATA */
+ 0x00000000 /* DENALI_PHY_112_DATA */
+ 0x00000000 /* DENALI_PHY_113_DATA */
+ 0x00000000 /* DENALI_PHY_114_DATA */
+ 0x00000000 /* DENALI_PHY_115_DATA */
+ 0x00000000 /* DENALI_PHY_116_DATA */
+ 0x00000000 /* DENALI_PHY_117_DATA */
+ 0x00000000 /* DENALI_PHY_118_DATA */
+ 0x00000000 /* DENALI_PHY_119_DATA */
+ 0x00000000 /* DENALI_PHY_120_DATA */
+ 0x00000000 /* DENALI_PHY_121_DATA */
+ 0x00000000 /* DENALI_PHY_122_DATA */
+ 0x00000000 /* DENALI_PHY_123_DATA */
+ 0x00000000 /* DENALI_PHY_124_DATA */
+ 0x00000000 /* DENALI_PHY_125_DATA */
+ 0x00000000 /* DENALI_PHY_126_DATA */
+ 0x00000000 /* DENALI_PHY_127_DATA */
+ 0x40263571 /* DENALI_PHY_128_DATA */
+ 0x0004c008 /* DENALI_PHY_129_DATA */
+ 0x000000da /* DENALI_PHY_130_DATA */
+ 0x00000000 /* DENALI_PHY_131_DATA */
+ 0x00000000 /* DENALI_PHY_132_DATA */
+ 0x00010000 /* DENALI_PHY_133_DATA */
+ 0x01DDDD90 /* DENALI_PHY_134_DATA */
+ 0x01DDDD90 /* DENALI_PHY_135_DATA */
+ 0x01030001 /* DENALI_PHY_136_DATA */
+ 0x01000000 /* DENALI_PHY_137_DATA */
+ 0x00c00000 /* DENALI_PHY_138_DATA */
+ 0x00000007 /* DENALI_PHY_139_DATA */
+ 0x00000000 /* DENALI_PHY_140_DATA */
+ 0x00000000 /* DENALI_PHY_141_DATA */
+ 0x04000408 /* DENALI_PHY_142_DATA */
+ 0x00000408 /* DENALI_PHY_143_DATA */
+ 0x00e4e400 /* DENALI_PHY_144_DATA */
+ 0x00000000 /* DENALI_PHY_145_DATA */
+ 0x00000000 /* DENALI_PHY_146_DATA */
+ 0x00000000 /* DENALI_PHY_147_DATA */
+ 0x00000000 /* DENALI_PHY_148_DATA */
+ 0x00000000 /* DENALI_PHY_149_DATA */
+ 0x00000000 /* DENALI_PHY_150_DATA */
+ 0x00000000 /* DENALI_PHY_151_DATA */
+ 0x00000000 /* DENALI_PHY_152_DATA */
+ 0x00000000 /* DENALI_PHY_153_DATA */
+ 0x00000000 /* DENALI_PHY_154_DATA */
+ 0x00000000 /* DENALI_PHY_155_DATA */
+ 0x00000000 /* DENALI_PHY_156_DATA */
+ 0x00000000 /* DENALI_PHY_157_DATA */
+ 0x00000000 /* DENALI_PHY_158_DATA */
+ 0x00000000 /* DENALI_PHY_159_DATA */
+ 0x00000000 /* DENALI_PHY_160_DATA */
+ 0x00200000 /* DENALI_PHY_161_DATA */
+ 0x00000000 /* DENALI_PHY_162_DATA */
+ 0x00000000 /* DENALI_PHY_163_DATA */
+ 0x00000000 /* DENALI_PHY_164_DATA */
+ 0x00000000 /* DENALI_PHY_165_DATA */
+ 0x00000000 /* DENALI_PHY_166_DATA */
+ 0x00000000 /* DENALI_PHY_167_DATA */
+ 0x02800280 /* DENALI_PHY_168_DATA */
+ 0x02800280 /* DENALI_PHY_169_DATA */
+ 0x02800280 /* DENALI_PHY_170_DATA */
+ 0x02800280 /* DENALI_PHY_171_DATA */
+ 0x00000280 /* DENALI_PHY_172_DATA */
+ 0x00000000 /* DENALI_PHY_173_DATA */
+ 0x00000000 /* DENALI_PHY_174_DATA */
+ 0x00000000 /* DENALI_PHY_175_DATA */
+ 0x00000000 /* DENALI_PHY_176_DATA */
+ 0x00000000 /* DENALI_PHY_177_DATA */
+ 0x00800080 /* DENALI_PHY_178_DATA */
+ 0x00800080 /* DENALI_PHY_179_DATA */
+ 0x00800080 /* DENALI_PHY_180_DATA */
+ 0x00800080 /* DENALI_PHY_181_DATA */
+ 0x00800080 /* DENALI_PHY_182_DATA */
+ 0x00800080 /* DENALI_PHY_183_DATA */
+ 0x00800080 /* DENALI_PHY_184_DATA */
+ 0x00800080 /* DENALI_PHY_185_DATA */
+ 0x00800080 /* DENALI_PHY_186_DATA */
+ 0x000100da /* DENALI_PHY_187_DATA */
+ 0x01ff0010 /* DENALI_PHY_188_DATA */
+ 0x00000000 /* DENALI_PHY_189_DATA */
+ 0x00000000 /* DENALI_PHY_190_DATA */
+ 0x00000002 /* DENALI_PHY_191_DATA */
+ 0x51313152 /* DENALI_PHY_192_DATA */
+ 0x80013130 /* DENALI_PHY_193_DATA */
+ 0x02000080 /* DENALI_PHY_194_DATA */
+ 0x00100001 /* DENALI_PHY_195_DATA */
+ 0x0c064208 /* DENALI_PHY_196_DATA */
+ 0x000f0c0f /* DENALI_PHY_197_DATA */
+ 0x01000140 /* DENALI_PHY_198_DATA */
+ 0x0000000c /* DENALI_PHY_199_DATA */
+ 0x00000000 /* DENALI_PHY_200_DATA */
+ 0x00000000 /* DENALI_PHY_201_DATA */
+ 0x00000000 /* DENALI_PHY_202_DATA */
+ 0x00000000 /* DENALI_PHY_203_DATA */
+ 0x00000000 /* DENALI_PHY_204_DATA */
+ 0x00000000 /* DENALI_PHY_205_DATA */
+ 0x00000000 /* DENALI_PHY_206_DATA */
+ 0x00000000 /* DENALI_PHY_207_DATA */
+ 0x00000000 /* DENALI_PHY_208_DATA */
+ 0x00000000 /* DENALI_PHY_209_DATA */
+ 0x00000000 /* DENALI_PHY_210_DATA */
+ 0x00000000 /* DENALI_PHY_211_DATA */
+ 0x00000000 /* DENALI_PHY_212_DATA */
+ 0x00000000 /* DENALI_PHY_213_DATA */
+ 0x00000000 /* DENALI_PHY_214_DATA */
+ 0x00000000 /* DENALI_PHY_215_DATA */
+ 0x00000000 /* DENALI_PHY_216_DATA */
+ 0x00000000 /* DENALI_PHY_217_DATA */
+ 0x00000000 /* DENALI_PHY_218_DATA */
+ 0x00000000 /* DENALI_PHY_219_DATA */
+ 0x00000000 /* DENALI_PHY_220_DATA */
+ 0x00000000 /* DENALI_PHY_221_DATA */
+ 0x00000000 /* DENALI_PHY_222_DATA */
+ 0x00000000 /* DENALI_PHY_223_DATA */
+ 0x00000000 /* DENALI_PHY_224_DATA */
+ 0x00000000 /* DENALI_PHY_225_DATA */
+ 0x00000000 /* DENALI_PHY_226_DATA */
+ 0x00000000 /* DENALI_PHY_227_DATA */
+ 0x00000000 /* DENALI_PHY_228_DATA */
+ 0x00000000 /* DENALI_PHY_229_DATA */
+ 0x00000000 /* DENALI_PHY_230_DATA */
+ 0x00000000 /* DENALI_PHY_231_DATA */
+ 0x00000000 /* DENALI_PHY_232_DATA */
+ 0x00000000 /* DENALI_PHY_233_DATA */
+ 0x00000000 /* DENALI_PHY_234_DATA */
+ 0x00000000 /* DENALI_PHY_235_DATA */
+ 0x00000000 /* DENALI_PHY_236_DATA */
+ 0x00000000 /* DENALI_PHY_237_DATA */
+ 0x00000000 /* DENALI_PHY_238_DATA */
+ 0x00000000 /* DENALI_PHY_239_DATA */
+ 0x00000000 /* DENALI_PHY_240_DATA */
+ 0x00000000 /* DENALI_PHY_241_DATA */
+ 0x00000000 /* DENALI_PHY_242_DATA */
+ 0x00000000 /* DENALI_PHY_243_DATA */
+ 0x00000000 /* DENALI_PHY_244_DATA */
+ 0x00000000 /* DENALI_PHY_245_DATA */
+ 0x00000000 /* DENALI_PHY_246_DATA */
+ 0x00000000 /* DENALI_PHY_247_DATA */
+ 0x00000000 /* DENALI_PHY_248_DATA */
+ 0x00000000 /* DENALI_PHY_249_DATA */
+ 0x00000000 /* DENALI_PHY_250_DATA */
+ 0x00000000 /* DENALI_PHY_251_DATA */
+ 0x00000000 /* DENALI_PHY_252_DATA */
+ 0x00000000 /* DENALI_PHY_253_DATA */
+ 0x00000000 /* DENALI_PHY_254_DATA */
+ 0x00000000 /* DENALI_PHY_255_DATA */
+ 0x46052371 /* DENALI_PHY_256_DATA */
+ 0x0004c008 /* DENALI_PHY_257_DATA */
+ 0x000000da /* DENALI_PHY_258_DATA */
+ 0x00000000 /* DENALI_PHY_259_DATA */
+ 0x00000000 /* DENALI_PHY_260_DATA */
+ 0x00010000 /* DENALI_PHY_261_DATA */
+ 0x01DDDD90 /* DENALI_PHY_262_DATA */
+ 0x01DDDD90 /* DENALI_PHY_263_DATA */
+ 0x01030001 /* DENALI_PHY_264_DATA */
+ 0x01000000 /* DENALI_PHY_265_DATA */
+ 0x00c00000 /* DENALI_PHY_266_DATA */
+ 0x00000007 /* DENALI_PHY_267_DATA */
+ 0x00000000 /* DENALI_PHY_268_DATA */
+ 0x00000000 /* DENALI_PHY_269_DATA */
+ 0x04000408 /* DENALI_PHY_270_DATA */
+ 0x00000408 /* DENALI_PHY_271_DATA */
+ 0x00e4e400 /* DENALI_PHY_272_DATA */
+ 0x00000000 /* DENALI_PHY_273_DATA */
+ 0x00000000 /* DENALI_PHY_274_DATA */
+ 0x00000000 /* DENALI_PHY_275_DATA */
+ 0x00000000 /* DENALI_PHY_276_DATA */
+ 0x00000000 /* DENALI_PHY_277_DATA */
+ 0x00000000 /* DENALI_PHY_278_DATA */
+ 0x00000000 /* DENALI_PHY_279_DATA */
+ 0x00000000 /* DENALI_PHY_280_DATA */
+ 0x00000000 /* DENALI_PHY_281_DATA */
+ 0x00000000 /* DENALI_PHY_282_DATA */
+ 0x00000000 /* DENALI_PHY_283_DATA */
+ 0x00000000 /* DENALI_PHY_284_DATA */
+ 0x00000000 /* DENALI_PHY_285_DATA */
+ 0x00000000 /* DENALI_PHY_286_DATA */
+ 0x00000000 /* DENALI_PHY_287_DATA */
+ 0x00000000 /* DENALI_PHY_288_DATA */
+ 0x00200000 /* DENALI_PHY_289_DATA */
+ 0x00000000 /* DENALI_PHY_290_DATA */
+ 0x00000000 /* DENALI_PHY_291_DATA */
+ 0x00000000 /* DENALI_PHY_292_DATA */
+ 0x00000000 /* DENALI_PHY_293_DATA */
+ 0x00000000 /* DENALI_PHY_294_DATA */
+ 0x00000000 /* DENALI_PHY_295_DATA */
+ 0x02800280 /* DENALI_PHY_296_DATA */
+ 0x02800280 /* DENALI_PHY_297_DATA */
+ 0x02800280 /* DENALI_PHY_298_DATA */
+ 0x02800280 /* DENALI_PHY_299_DATA */
+ 0x00000280 /* DENALI_PHY_300_DATA */
+ 0x00000000 /* DENALI_PHY_301_DATA */
+ 0x00000000 /* DENALI_PHY_302_DATA */
+ 0x00000000 /* DENALI_PHY_303_DATA */
+ 0x00000000 /* DENALI_PHY_304_DATA */
+ 0x00000000 /* DENALI_PHY_305_DATA */
+ 0x00800080 /* DENALI_PHY_306_DATA */
+ 0x00800080 /* DENALI_PHY_307_DATA */
+ 0x00800080 /* DENALI_PHY_308_DATA */
+ 0x00800080 /* DENALI_PHY_309_DATA */
+ 0x00800080 /* DENALI_PHY_310_DATA */
+ 0x00800080 /* DENALI_PHY_311_DATA */
+ 0x00800080 /* DENALI_PHY_312_DATA */
+ 0x00800080 /* DENALI_PHY_313_DATA */
+ 0x00800080 /* DENALI_PHY_314_DATA */
+ 0x000100da /* DENALI_PHY_315_DATA */
+ 0x01ff0010 /* DENALI_PHY_316_DATA */
+ 0x00000000 /* DENALI_PHY_317_DATA */
+ 0x00000000 /* DENALI_PHY_318_DATA */
+ 0x00000002 /* DENALI_PHY_319_DATA */
+ 0x51313152 /* DENALI_PHY_320_DATA */
+ 0x80013130 /* DENALI_PHY_321_DATA */
+ 0x02000080 /* DENALI_PHY_322_DATA */
+ 0x00100001 /* DENALI_PHY_323_DATA */
+ 0x0c064208 /* DENALI_PHY_324_DATA */
+ 0x000f0c0f /* DENALI_PHY_325_DATA */
+ 0x01000140 /* DENALI_PHY_326_DATA */
+ 0x0000000c /* DENALI_PHY_327_DATA */
+ 0x00000000 /* DENALI_PHY_328_DATA */
+ 0x00000000 /* DENALI_PHY_329_DATA */
+ 0x00000000 /* DENALI_PHY_330_DATA */
+ 0x00000000 /* DENALI_PHY_331_DATA */
+ 0x00000000 /* DENALI_PHY_332_DATA */
+ 0x00000000 /* DENALI_PHY_333_DATA */
+ 0x00000000 /* DENALI_PHY_334_DATA */
+ 0x00000000 /* DENALI_PHY_335_DATA */
+ 0x00000000 /* DENALI_PHY_336_DATA */
+ 0x00000000 /* DENALI_PHY_337_DATA */
+ 0x00000000 /* DENALI_PHY_338_DATA */
+ 0x00000000 /* DENALI_PHY_339_DATA */
+ 0x00000000 /* DENALI_PHY_340_DATA */
+ 0x00000000 /* DENALI_PHY_341_DATA */
+ 0x00000000 /* DENALI_PHY_342_DATA */
+ 0x00000000 /* DENALI_PHY_343_DATA */
+ 0x00000000 /* DENALI_PHY_344_DATA */
+ 0x00000000 /* DENALI_PHY_345_DATA */
+ 0x00000000 /* DENALI_PHY_346_DATA */
+ 0x00000000 /* DENALI_PHY_347_DATA */
+ 0x00000000 /* DENALI_PHY_348_DATA */
+ 0x00000000 /* DENALI_PHY_349_DATA */
+ 0x00000000 /* DENALI_PHY_350_DATA */
+ 0x00000000 /* DENALI_PHY_351_DATA */
+ 0x00000000 /* DENALI_PHY_352_DATA */
+ 0x00000000 /* DENALI_PHY_353_DATA */
+ 0x00000000 /* DENALI_PHY_354_DATA */
+ 0x00000000 /* DENALI_PHY_355_DATA */
+ 0x00000000 /* DENALI_PHY_356_DATA */
+ 0x00000000 /* DENALI_PHY_357_DATA */
+ 0x00000000 /* DENALI_PHY_358_DATA */
+ 0x00000000 /* DENALI_PHY_359_DATA */
+ 0x00000000 /* DENALI_PHY_360_DATA */
+ 0x00000000 /* DENALI_PHY_361_DATA */
+ 0x00000000 /* DENALI_PHY_362_DATA */
+ 0x00000000 /* DENALI_PHY_363_DATA */
+ 0x00000000 /* DENALI_PHY_364_DATA */
+ 0x00000000 /* DENALI_PHY_365_DATA */
+ 0x00000000 /* DENALI_PHY_366_DATA */
+ 0x00000000 /* DENALI_PHY_367_DATA */
+ 0x00000000 /* DENALI_PHY_368_DATA */
+ 0x00000000 /* DENALI_PHY_369_DATA */
+ 0x00000000 /* DENALI_PHY_370_DATA */
+ 0x00000000 /* DENALI_PHY_371_DATA */
+ 0x00000000 /* DENALI_PHY_372_DATA */
+ 0x00000000 /* DENALI_PHY_373_DATA */
+ 0x00000000 /* DENALI_PHY_374_DATA */
+ 0x00000000 /* DENALI_PHY_375_DATA */
+ 0x00000000 /* DENALI_PHY_376_DATA */
+ 0x00000000 /* DENALI_PHY_377_DATA */
+ 0x00000000 /* DENALI_PHY_378_DATA */
+ 0x00000000 /* DENALI_PHY_379_DATA */
+ 0x00000000 /* DENALI_PHY_380_DATA */
+ 0x00000000 /* DENALI_PHY_381_DATA */
+ 0x00000000 /* DENALI_PHY_382_DATA */
+ 0x00000000 /* DENALI_PHY_383_DATA */
+ 0x37651240 /* DENALI_PHY_384_DATA */
+ 0x0004c008 /* DENALI_PHY_385_DATA */
+ 0x000000da /* DENALI_PHY_386_DATA */
+ 0x00000000 /* DENALI_PHY_387_DATA */
+ 0x00000000 /* DENALI_PHY_388_DATA */
+ 0x00010000 /* DENALI_PHY_389_DATA */
+ 0x01DDDD90 /* DENALI_PHY_390_DATA */
+ 0x01DDDD90 /* DENALI_PHY_391_DATA */
+ 0x01030001 /* DENALI_PHY_392_DATA */
+ 0x01000000 /* DENALI_PHY_393_DATA */
+ 0x00c00000 /* DENALI_PHY_394_DATA */
+ 0x00000007 /* DENALI_PHY_395_DATA */
+ 0x00000000 /* DENALI_PHY_396_DATA */
+ 0x00000000 /* DENALI_PHY_397_DATA */
+ 0x04000408 /* DENALI_PHY_398_DATA */
+ 0x00000408 /* DENALI_PHY_399_DATA */
+ 0x00e4e400 /* DENALI_PHY_400_DATA */
+ 0x00000000 /* DENALI_PHY_401_DATA */
+ 0x00000000 /* DENALI_PHY_402_DATA */
+ 0x00000000 /* DENALI_PHY_403_DATA */
+ 0x00000000 /* DENALI_PHY_404_DATA */
+ 0x00000000 /* DENALI_PHY_405_DATA */
+ 0x00000000 /* DENALI_PHY_406_DATA */
+ 0x00000000 /* DENALI_PHY_407_DATA */
+ 0x00000000 /* DENALI_PHY_408_DATA */
+ 0x00000000 /* DENALI_PHY_409_DATA */
+ 0x00000000 /* DENALI_PHY_410_DATA */
+ 0x00000000 /* DENALI_PHY_411_DATA */
+ 0x00000000 /* DENALI_PHY_412_DATA */
+ 0x00000000 /* DENALI_PHY_413_DATA */
+ 0x00000000 /* DENALI_PHY_414_DATA */
+ 0x00000000 /* DENALI_PHY_415_DATA */
+ 0x00000000 /* DENALI_PHY_416_DATA */
+ 0x00200000 /* DENALI_PHY_417_DATA */
+ 0x00000000 /* DENALI_PHY_418_DATA */
+ 0x00000000 /* DENALI_PHY_419_DATA */
+ 0x00000000 /* DENALI_PHY_420_DATA */
+ 0x00000000 /* DENALI_PHY_421_DATA */
+ 0x00000000 /* DENALI_PHY_422_DATA */
+ 0x00000000 /* DENALI_PHY_423_DATA */
+ 0x02800280 /* DENALI_PHY_424_DATA */
+ 0x02800280 /* DENALI_PHY_425_DATA */
+ 0x02800280 /* DENALI_PHY_426_DATA */
+ 0x02800280 /* DENALI_PHY_427_DATA */
+ 0x00000280 /* DENALI_PHY_428_DATA */
+ 0x00000000 /* DENALI_PHY_429_DATA */
+ 0x00000000 /* DENALI_PHY_430_DATA */
+ 0x00000000 /* DENALI_PHY_431_DATA */
+ 0x00000000 /* DENALI_PHY_432_DATA */
+ 0x00000000 /* DENALI_PHY_433_DATA */
+ 0x00800080 /* DENALI_PHY_434_DATA */
+ 0x00800080 /* DENALI_PHY_435_DATA */
+ 0x00800080 /* DENALI_PHY_436_DATA */
+ 0x00800080 /* DENALI_PHY_437_DATA */
+ 0x00800080 /* DENALI_PHY_438_DATA */
+ 0x00800080 /* DENALI_PHY_439_DATA */
+ 0x00800080 /* DENALI_PHY_440_DATA */
+ 0x00800080 /* DENALI_PHY_441_DATA */
+ 0x00800080 /* DENALI_PHY_442_DATA */
+ 0x000100da /* DENALI_PHY_443_DATA */
+ 0x01ff0010 /* DENALI_PHY_444_DATA */
+ 0x00000000 /* DENALI_PHY_445_DATA */
+ 0x00000000 /* DENALI_PHY_446_DATA */
+ 0x00000002 /* DENALI_PHY_447_DATA */
+ 0x51313152 /* DENALI_PHY_448_DATA */
+ 0x80013130 /* DENALI_PHY_449_DATA */
+ 0x02000080 /* DENALI_PHY_450_DATA */
+ 0x00100001 /* DENALI_PHY_451_DATA */
+ 0x0c064208 /* DENALI_PHY_452_DATA */
+ 0x000f0c0f /* DENALI_PHY_453_DATA */
+ 0x01000140 /* DENALI_PHY_454_DATA */
+ 0x0000000c /* DENALI_PHY_455_DATA */
+ 0x00000000 /* DENALI_PHY_456_DATA */
+ 0x00000000 /* DENALI_PHY_457_DATA */
+ 0x00000000 /* DENALI_PHY_458_DATA */
+ 0x00000000 /* DENALI_PHY_459_DATA */
+ 0x00000000 /* DENALI_PHY_460_DATA */
+ 0x00000000 /* DENALI_PHY_461_DATA */
+ 0x00000000 /* DENALI_PHY_462_DATA */
+ 0x00000000 /* DENALI_PHY_463_DATA */
+ 0x00000000 /* DENALI_PHY_464_DATA */
+ 0x00000000 /* DENALI_PHY_465_DATA */
+ 0x00000000 /* DENALI_PHY_466_DATA */
+ 0x00000000 /* DENALI_PHY_467_DATA */
+ 0x00000000 /* DENALI_PHY_468_DATA */
+ 0x00000000 /* DENALI_PHY_469_DATA */
+ 0x00000000 /* DENALI_PHY_470_DATA */
+ 0x00000000 /* DENALI_PHY_471_DATA */
+ 0x00000000 /* DENALI_PHY_472_DATA */
+ 0x00000000 /* DENALI_PHY_473_DATA */
+ 0x00000000 /* DENALI_PHY_474_DATA */
+ 0x00000000 /* DENALI_PHY_475_DATA */
+ 0x00000000 /* DENALI_PHY_476_DATA */
+ 0x00000000 /* DENALI_PHY_477_DATA */
+ 0x00000000 /* DENALI_PHY_478_DATA */
+ 0x00000000 /* DENALI_PHY_479_DATA */
+ 0x00000000 /* DENALI_PHY_480_DATA */
+ 0x00000000 /* DENALI_PHY_481_DATA */
+ 0x00000000 /* DENALI_PHY_482_DATA */
+ 0x00000000 /* DENALI_PHY_483_DATA */
+ 0x00000000 /* DENALI_PHY_484_DATA */
+ 0x00000000 /* DENALI_PHY_485_DATA */
+ 0x00000000 /* DENALI_PHY_486_DATA */
+ 0x00000000 /* DENALI_PHY_487_DATA */
+ 0x00000000 /* DENALI_PHY_488_DATA */
+ 0x00000000 /* DENALI_PHY_489_DATA */
+ 0x00000000 /* DENALI_PHY_490_DATA */
+ 0x00000000 /* DENALI_PHY_491_DATA */
+ 0x00000000 /* DENALI_PHY_492_DATA */
+ 0x00000000 /* DENALI_PHY_493_DATA */
+ 0x00000000 /* DENALI_PHY_494_DATA */
+ 0x00000000 /* DENALI_PHY_495_DATA */
+ 0x00000000 /* DENALI_PHY_496_DATA */
+ 0x00000000 /* DENALI_PHY_497_DATA */
+ 0x00000000 /* DENALI_PHY_498_DATA */
+ 0x00000000 /* DENALI_PHY_499_DATA */
+ 0x00000000 /* DENALI_PHY_500_DATA */
+ 0x00000000 /* DENALI_PHY_501_DATA */
+ 0x00000000 /* DENALI_PHY_502_DATA */
+ 0x00000000 /* DENALI_PHY_503_DATA */
+ 0x00000000 /* DENALI_PHY_504_DATA */
+ 0x00000000 /* DENALI_PHY_505_DATA */
+ 0x00000000 /* DENALI_PHY_506_DATA */
+ 0x00000000 /* DENALI_PHY_507_DATA */
+ 0x00000000 /* DENALI_PHY_508_DATA */
+ 0x00000000 /* DENALI_PHY_509_DATA */
+ 0x00000000 /* DENALI_PHY_510_DATA */
+ 0x00000000 /* DENALI_PHY_511_DATA */
+ 0x34216750 /* DENALI_PHY_512_DATA */
+ 0x0004c008 /* DENALI_PHY_513_DATA */
+ 0x000000da /* DENALI_PHY_514_DATA */
+ 0x00000000 /* DENALI_PHY_515_DATA */
+ 0x00000000 /* DENALI_PHY_516_DATA */
+ 0x00010000 /* DENALI_PHY_517_DATA */
+ 0x01DDDD90 /* DENALI_PHY_518_DATA */
+ 0x01DDDD90 /* DENALI_PHY_519_DATA */
+ 0x01030001 /* DENALI_PHY_520_DATA */
+ 0x01000000 /* DENALI_PHY_521_DATA */
+ 0x00c00000 /* DENALI_PHY_522_DATA */
+ 0x00000007 /* DENALI_PHY_523_DATA */
+ 0x00000000 /* DENALI_PHY_524_DATA */
+ 0x00000000 /* DENALI_PHY_525_DATA */
+ 0x04000408 /* DENALI_PHY_526_DATA */
+ 0x00000408 /* DENALI_PHY_527_DATA */
+ 0x00e4e400 /* DENALI_PHY_528_DATA */
+ 0x00000000 /* DENALI_PHY_529_DATA */
+ 0x00000000 /* DENALI_PHY_530_DATA */
+ 0x00000000 /* DENALI_PHY_531_DATA */
+ 0x00000000 /* DENALI_PHY_532_DATA */
+ 0x00000000 /* DENALI_PHY_533_DATA */
+ 0x00000000 /* DENALI_PHY_534_DATA */
+ 0x00000000 /* DENALI_PHY_535_DATA */
+ 0x00000000 /* DENALI_PHY_536_DATA */
+ 0x00000000 /* DENALI_PHY_537_DATA */
+ 0x00000000 /* DENALI_PHY_538_DATA */
+ 0x00000000 /* DENALI_PHY_539_DATA */
+ 0x00000000 /* DENALI_PHY_540_DATA */
+ 0x00000000 /* DENALI_PHY_541_DATA */
+ 0x00000000 /* DENALI_PHY_542_DATA */
+ 0x00000000 /* DENALI_PHY_543_DATA */
+ 0x00000000 /* DENALI_PHY_544_DATA */
+ 0x00200000 /* DENALI_PHY_545_DATA */
+ 0x00000000 /* DENALI_PHY_546_DATA */
+ 0x00000000 /* DENALI_PHY_547_DATA */
+ 0x00000000 /* DENALI_PHY_548_DATA */
+ 0x00000000 /* DENALI_PHY_549_DATA */
+ 0x00000000 /* DENALI_PHY_550_DATA */
+ 0x00000000 /* DENALI_PHY_551_DATA */
+ 0x02800280 /* DENALI_PHY_552_DATA */
+ 0x02800280 /* DENALI_PHY_553_DATA */
+ 0x02800280 /* DENALI_PHY_554_DATA */
+ 0x02800280 /* DENALI_PHY_555_DATA */
+ 0x00000280 /* DENALI_PHY_556_DATA */
+ 0x00000000 /* DENALI_PHY_557_DATA */
+ 0x00000000 /* DENALI_PHY_558_DATA */
+ 0x00000000 /* DENALI_PHY_559_DATA */
+ 0x00000000 /* DENALI_PHY_560_DATA */
+ 0x00000000 /* DENALI_PHY_561_DATA */
+ 0x00800080 /* DENALI_PHY_562_DATA */
+ 0x00800080 /* DENALI_PHY_563_DATA */
+ 0x00800080 /* DENALI_PHY_564_DATA */
+ 0x00800080 /* DENALI_PHY_565_DATA */
+ 0x00800080 /* DENALI_PHY_566_DATA */
+ 0x00800080 /* DENALI_PHY_567_DATA */
+ 0x00800080 /* DENALI_PHY_568_DATA */
+ 0x00800080 /* DENALI_PHY_569_DATA */
+ 0x00800080 /* DENALI_PHY_570_DATA */
+ 0x000100da /* DENALI_PHY_571_DATA */
+ 0x01ff0010 /* DENALI_PHY_572_DATA */
+ 0x00000000 /* DENALI_PHY_573_DATA */
+ 0x00000000 /* DENALI_PHY_574_DATA */
+ 0x00000002 /* DENALI_PHY_575_DATA */
+ 0x51313152 /* DENALI_PHY_576_DATA */
+ 0x80013130 /* DENALI_PHY_577_DATA */
+ 0x02000080 /* DENALI_PHY_578_DATA */
+ 0x00100001 /* DENALI_PHY_579_DATA */
+ 0x0c064208 /* DENALI_PHY_580_DATA */
+ 0x000f0c0f /* DENALI_PHY_581_DATA */
+ 0x01000140 /* DENALI_PHY_582_DATA */
+ 0x0000000c /* DENALI_PHY_583_DATA */
+ 0x00000000 /* DENALI_PHY_584_DATA */
+ 0x00000000 /* DENALI_PHY_585_DATA */
+ 0x00000000 /* DENALI_PHY_586_DATA */
+ 0x00000000 /* DENALI_PHY_587_DATA */
+ 0x00000000 /* DENALI_PHY_588_DATA */
+ 0x00000000 /* DENALI_PHY_589_DATA */
+ 0x00000000 /* DENALI_PHY_590_DATA */
+ 0x00000000 /* DENALI_PHY_591_DATA */
+ 0x00000000 /* DENALI_PHY_592_DATA */
+ 0x00000000 /* DENALI_PHY_593_DATA */
+ 0x00000000 /* DENALI_PHY_594_DATA */
+ 0x00000000 /* DENALI_PHY_595_DATA */
+ 0x00000000 /* DENALI_PHY_596_DATA */
+ 0x00000000 /* DENALI_PHY_597_DATA */
+ 0x00000000 /* DENALI_PHY_598_DATA */
+ 0x00000000 /* DENALI_PHY_599_DATA */
+ 0x00000000 /* DENALI_PHY_600_DATA */
+ 0x00000000 /* DENALI_PHY_601_DATA */
+ 0x00000000 /* DENALI_PHY_602_DATA */
+ 0x00000000 /* DENALI_PHY_603_DATA */
+ 0x00000000 /* DENALI_PHY_604_DATA */
+ 0x00000000 /* DENALI_PHY_605_DATA */
+ 0x00000000 /* DENALI_PHY_606_DATA */
+ 0x00000000 /* DENALI_PHY_607_DATA */
+ 0x00000000 /* DENALI_PHY_608_DATA */
+ 0x00000000 /* DENALI_PHY_609_DATA */
+ 0x00000000 /* DENALI_PHY_610_DATA */
+ 0x00000000 /* DENALI_PHY_611_DATA */
+ 0x00000000 /* DENALI_PHY_612_DATA */
+ 0x00000000 /* DENALI_PHY_613_DATA */
+ 0x00000000 /* DENALI_PHY_614_DATA */
+ 0x00000000 /* DENALI_PHY_615_DATA */
+ 0x00000000 /* DENALI_PHY_616_DATA */
+ 0x00000000 /* DENALI_PHY_617_DATA */
+ 0x00000000 /* DENALI_PHY_618_DATA */
+ 0x00000000 /* DENALI_PHY_619_DATA */
+ 0x00000000 /* DENALI_PHY_620_DATA */
+ 0x00000000 /* DENALI_PHY_621_DATA */
+ 0x00000000 /* DENALI_PHY_622_DATA */
+ 0x00000000 /* DENALI_PHY_623_DATA */
+ 0x00000000 /* DENALI_PHY_624_DATA */
+ 0x00000000 /* DENALI_PHY_625_DATA */
+ 0x00000000 /* DENALI_PHY_626_DATA */
+ 0x00000000 /* DENALI_PHY_627_DATA */
+ 0x00000000 /* DENALI_PHY_628_DATA */
+ 0x00000000 /* DENALI_PHY_629_DATA */
+ 0x00000000 /* DENALI_PHY_630_DATA */
+ 0x00000000 /* DENALI_PHY_631_DATA */
+ 0x00000000 /* DENALI_PHY_632_DATA */
+ 0x00000000 /* DENALI_PHY_633_DATA */
+ 0x00000000 /* DENALI_PHY_634_DATA */
+ 0x00000000 /* DENALI_PHY_635_DATA */
+ 0x00000000 /* DENALI_PHY_636_DATA */
+ 0x00000000 /* DENALI_PHY_637_DATA */
+ 0x00000000 /* DENALI_PHY_638_DATA */
+ 0x00000000 /* DENALI_PHY_639_DATA */
+ 0x35176402 /* DENALI_PHY_640_DATA */
+ 0x0004c008 /* DENALI_PHY_641_DATA */
+ 0x000000da /* DENALI_PHY_642_DATA */
+ 0x00000000 /* DENALI_PHY_643_DATA */
+ 0x00000000 /* DENALI_PHY_644_DATA */
+ 0x00010000 /* DENALI_PHY_645_DATA */
+ 0x01DDDD90 /* DENALI_PHY_646_DATA */
+ 0x01DDDD90 /* DENALI_PHY_647_DATA */
+ 0x01030001 /* DENALI_PHY_648_DATA */
+ 0x01000000 /* DENALI_PHY_649_DATA */
+ 0x00c00000 /* DENALI_PHY_650_DATA */
+ 0x00000007 /* DENALI_PHY_651_DATA */
+ 0x00000000 /* DENALI_PHY_652_DATA */
+ 0x00000000 /* DENALI_PHY_653_DATA */
+ 0x04000408 /* DENALI_PHY_654_DATA */
+ 0x00000408 /* DENALI_PHY_655_DATA */
+ 0x00e4e400 /* DENALI_PHY_656_DATA */
+ 0x00000000 /* DENALI_PHY_657_DATA */
+ 0x00000000 /* DENALI_PHY_658_DATA */
+ 0x00000000 /* DENALI_PHY_659_DATA */
+ 0x00000000 /* DENALI_PHY_660_DATA */
+ 0x00000000 /* DENALI_PHY_661_DATA */
+ 0x00000000 /* DENALI_PHY_662_DATA */
+ 0x00000000 /* DENALI_PHY_663_DATA */
+ 0x00000000 /* DENALI_PHY_664_DATA */
+ 0x00000000 /* DENALI_PHY_665_DATA */
+ 0x00000000 /* DENALI_PHY_666_DATA */
+ 0x00000000 /* DENALI_PHY_667_DATA */
+ 0x00000000 /* DENALI_PHY_668_DATA */
+ 0x00000000 /* DENALI_PHY_669_DATA */
+ 0x00000000 /* DENALI_PHY_670_DATA */
+ 0x00000000 /* DENALI_PHY_671_DATA */
+ 0x00000000 /* DENALI_PHY_672_DATA */
+ 0x00200000 /* DENALI_PHY_673_DATA */
+ 0x00000000 /* DENALI_PHY_674_DATA */
+ 0x00000000 /* DENALI_PHY_675_DATA */
+ 0x00000000 /* DENALI_PHY_676_DATA */
+ 0x00000000 /* DENALI_PHY_677_DATA */
+ 0x00000000 /* DENALI_PHY_678_DATA */
+ 0x00000000 /* DENALI_PHY_679_DATA */
+ 0x02800280 /* DENALI_PHY_680_DATA */
+ 0x02800280 /* DENALI_PHY_681_DATA */
+ 0x02800280 /* DENALI_PHY_682_DATA */
+ 0x02800280 /* DENALI_PHY_683_DATA */
+ 0x00000280 /* DENALI_PHY_684_DATA */
+ 0x00000000 /* DENALI_PHY_685_DATA */
+ 0x00000000 /* DENALI_PHY_686_DATA */
+ 0x00000000 /* DENALI_PHY_687_DATA */
+ 0x00000000 /* DENALI_PHY_688_DATA */
+ 0x00000000 /* DENALI_PHY_689_DATA */
+ 0x00800080 /* DENALI_PHY_690_DATA */
+ 0x00800080 /* DENALI_PHY_691_DATA */
+ 0x00800080 /* DENALI_PHY_692_DATA */
+ 0x00800080 /* DENALI_PHY_693_DATA */
+ 0x00800080 /* DENALI_PHY_694_DATA */
+ 0x00800080 /* DENALI_PHY_695_DATA */
+ 0x00800080 /* DENALI_PHY_696_DATA */
+ 0x00800080 /* DENALI_PHY_697_DATA */
+ 0x00800080 /* DENALI_PHY_698_DATA */
+ 0x000100da /* DENALI_PHY_699_DATA */
+ 0x01ff0010 /* DENALI_PHY_700_DATA */
+ 0x00000000 /* DENALI_PHY_701_DATA */
+ 0x00000000 /* DENALI_PHY_702_DATA */
+ 0x00000002 /* DENALI_PHY_703_DATA */
+ 0x51313152 /* DENALI_PHY_704_DATA */
+ 0x80013130 /* DENALI_PHY_705_DATA */
+ 0x02000080 /* DENALI_PHY_706_DATA */
+ 0x00100001 /* DENALI_PHY_707_DATA */
+ 0x0c064208 /* DENALI_PHY_708_DATA */
+ 0x000f0c0f /* DENALI_PHY_709_DATA */
+ 0x01000140 /* DENALI_PHY_710_DATA */
+ 0x0000000c /* DENALI_PHY_711_DATA */
+ 0x00000000 /* DENALI_PHY_712_DATA */
+ 0x00000000 /* DENALI_PHY_713_DATA */
+ 0x00000000 /* DENALI_PHY_714_DATA */
+ 0x00000000 /* DENALI_PHY_715_DATA */
+ 0x00000000 /* DENALI_PHY_716_DATA */
+ 0x00000000 /* DENALI_PHY_717_DATA */
+ 0x00000000 /* DENALI_PHY_718_DATA */
+ 0x00000000 /* DENALI_PHY_719_DATA */
+ 0x00000000 /* DENALI_PHY_720_DATA */
+ 0x00000000 /* DENALI_PHY_721_DATA */
+ 0x00000000 /* DENALI_PHY_722_DATA */
+ 0x00000000 /* DENALI_PHY_723_DATA */
+ 0x00000000 /* DENALI_PHY_724_DATA */
+ 0x00000000 /* DENALI_PHY_725_DATA */
+ 0x00000000 /* DENALI_PHY_726_DATA */
+ 0x00000000 /* DENALI_PHY_727_DATA */
+ 0x00000000 /* DENALI_PHY_728_DATA */
+ 0x00000000 /* DENALI_PHY_729_DATA */
+ 0x00000000 /* DENALI_PHY_730_DATA */
+ 0x00000000 /* DENALI_PHY_731_DATA */
+ 0x00000000 /* DENALI_PHY_732_DATA */
+ 0x00000000 /* DENALI_PHY_733_DATA */
+ 0x00000000 /* DENALI_PHY_734_DATA */
+ 0x00000000 /* DENALI_PHY_735_DATA */
+ 0x00000000 /* DENALI_PHY_736_DATA */
+ 0x00000000 /* DENALI_PHY_737_DATA */
+ 0x00000000 /* DENALI_PHY_738_DATA */
+ 0x00000000 /* DENALI_PHY_739_DATA */
+ 0x00000000 /* DENALI_PHY_740_DATA */
+ 0x00000000 /* DENALI_PHY_741_DATA */
+ 0x00000000 /* DENALI_PHY_742_DATA */
+ 0x00000000 /* DENALI_PHY_743_DATA */
+ 0x00000000 /* DENALI_PHY_744_DATA */
+ 0x00000000 /* DENALI_PHY_745_DATA */
+ 0x00000000 /* DENALI_PHY_746_DATA */
+ 0x00000000 /* DENALI_PHY_747_DATA */
+ 0x00000000 /* DENALI_PHY_748_DATA */
+ 0x00000000 /* DENALI_PHY_749_DATA */
+ 0x00000000 /* DENALI_PHY_750_DATA */
+ 0x00000000 /* DENALI_PHY_751_DATA */
+ 0x00000000 /* DENALI_PHY_752_DATA */
+ 0x00000000 /* DENALI_PHY_753_DATA */
+ 0x00000000 /* DENALI_PHY_754_DATA */
+ 0x00000000 /* DENALI_PHY_755_DATA */
+ 0x00000000 /* DENALI_PHY_756_DATA */
+ 0x00000000 /* DENALI_PHY_757_DATA */
+ 0x00000000 /* DENALI_PHY_758_DATA */
+ 0x00000000 /* DENALI_PHY_759_DATA */
+ 0x00000000 /* DENALI_PHY_760_DATA */
+ 0x00000000 /* DENALI_PHY_761_DATA */
+ 0x00000000 /* DENALI_PHY_762_DATA */
+ 0x00000000 /* DENALI_PHY_763_DATA */
+ 0x00000000 /* DENALI_PHY_764_DATA */
+ 0x00000000 /* DENALI_PHY_765_DATA */
+ 0x00000000 /* DENALI_PHY_766_DATA */
+ 0x00000000 /* DENALI_PHY_767_DATA */
+ 0x10526347 /* DENALI_PHY_768_DATA */
+ 0x0004c008 /* DENALI_PHY_769_DATA */
+ 0x000000da /* DENALI_PHY_770_DATA */
+ 0x00000000 /* DENALI_PHY_771_DATA */
+ 0x00000000 /* DENALI_PHY_772_DATA */
+ 0x00010000 /* DENALI_PHY_773_DATA */
+ 0x01DDDD90 /* DENALI_PHY_774_DATA */
+ 0x01DDDD90 /* DENALI_PHY_775_DATA */
+ 0x01030001 /* DENALI_PHY_776_DATA */
+ 0x01000000 /* DENALI_PHY_777_DATA */
+ 0x00c00000 /* DENALI_PHY_778_DATA */
+ 0x00000007 /* DENALI_PHY_779_DATA */
+ 0x00000000 /* DENALI_PHY_780_DATA */
+ 0x00000000 /* DENALI_PHY_781_DATA */
+ 0x04000408 /* DENALI_PHY_782_DATA */
+ 0x00000408 /* DENALI_PHY_783_DATA */
+ 0x00e4e400 /* DENALI_PHY_784_DATA */
+ 0x00000000 /* DENALI_PHY_785_DATA */
+ 0x00000000 /* DENALI_PHY_786_DATA */
+ 0x00000000 /* DENALI_PHY_787_DATA */
+ 0x00000000 /* DENALI_PHY_788_DATA */
+ 0x00000000 /* DENALI_PHY_789_DATA */
+ 0x00000000 /* DENALI_PHY_790_DATA */
+ 0x00000000 /* DENALI_PHY_791_DATA */
+ 0x00000000 /* DENALI_PHY_792_DATA */
+ 0x00000000 /* DENALI_PHY_793_DATA */
+ 0x00000000 /* DENALI_PHY_794_DATA */
+ 0x00000000 /* DENALI_PHY_795_DATA */
+ 0x00000000 /* DENALI_PHY_796_DATA */
+ 0x00000000 /* DENALI_PHY_797_DATA */
+ 0x00000000 /* DENALI_PHY_798_DATA */
+ 0x00000000 /* DENALI_PHY_799_DATA */
+ 0x00000000 /* DENALI_PHY_800_DATA */
+ 0x00200000 /* DENALI_PHY_801_DATA */
+ 0x00000000 /* DENALI_PHY_802_DATA */
+ 0x00000000 /* DENALI_PHY_803_DATA */
+ 0x00000000 /* DENALI_PHY_804_DATA */
+ 0x00000000 /* DENALI_PHY_805_DATA */
+ 0x00000000 /* DENALI_PHY_806_DATA */
+ 0x00000000 /* DENALI_PHY_807_DATA */
+ 0x02800280 /* DENALI_PHY_808_DATA */
+ 0x02800280 /* DENALI_PHY_809_DATA */
+ 0x02800280 /* DENALI_PHY_810_DATA */
+ 0x02800280 /* DENALI_PHY_811_DATA */
+ 0x00000280 /* DENALI_PHY_812_DATA */
+ 0x00000000 /* DENALI_PHY_813_DATA */
+ 0x00000000 /* DENALI_PHY_814_DATA */
+ 0x00000000 /* DENALI_PHY_815_DATA */
+ 0x00000000 /* DENALI_PHY_816_DATA */
+ 0x00000000 /* DENALI_PHY_817_DATA */
+ 0x00800080 /* DENALI_PHY_818_DATA */
+ 0x00800080 /* DENALI_PHY_819_DATA */
+ 0x00800080 /* DENALI_PHY_820_DATA */
+ 0x00800080 /* DENALI_PHY_821_DATA */
+ 0x00800080 /* DENALI_PHY_822_DATA */
+ 0x00800080 /* DENALI_PHY_823_DATA */
+ 0x00800080 /* DENALI_PHY_824_DATA */
+ 0x00800080 /* DENALI_PHY_825_DATA */
+ 0x00800080 /* DENALI_PHY_826_DATA */
+ 0x000100da /* DENALI_PHY_827_DATA */
+ 0x01ff0010 /* DENALI_PHY_828_DATA */
+ 0x00000000 /* DENALI_PHY_829_DATA */
+ 0x00000000 /* DENALI_PHY_830_DATA */
+ 0x00000002 /* DENALI_PHY_831_DATA */
+ 0x51313152 /* DENALI_PHY_832_DATA */
+ 0x80013130 /* DENALI_PHY_833_DATA */
+ 0x02000080 /* DENALI_PHY_834_DATA */
+ 0x00100001 /* DENALI_PHY_835_DATA */
+ 0x0c064208 /* DENALI_PHY_836_DATA */
+ 0x000f0c0f /* DENALI_PHY_837_DATA */
+ 0x01000140 /* DENALI_PHY_838_DATA */
+ 0x0000000c /* DENALI_PHY_839_DATA */
+ 0x00000000 /* DENALI_PHY_840_DATA */
+ 0x00000000 /* DENALI_PHY_841_DATA */
+ 0x00000000 /* DENALI_PHY_842_DATA */
+ 0x00000000 /* DENALI_PHY_843_DATA */
+ 0x00000000 /* DENALI_PHY_844_DATA */
+ 0x00000000 /* DENALI_PHY_845_DATA */
+ 0x00000000 /* DENALI_PHY_846_DATA */
+ 0x00000000 /* DENALI_PHY_847_DATA */
+ 0x00000000 /* DENALI_PHY_848_DATA */
+ 0x00000000 /* DENALI_PHY_849_DATA */
+ 0x00000000 /* DENALI_PHY_850_DATA */
+ 0x00000000 /* DENALI_PHY_851_DATA */
+ 0x00000000 /* DENALI_PHY_852_DATA */
+ 0x00000000 /* DENALI_PHY_853_DATA */
+ 0x00000000 /* DENALI_PHY_854_DATA */
+ 0x00000000 /* DENALI_PHY_855_DATA */
+ 0x00000000 /* DENALI_PHY_856_DATA */
+ 0x00000000 /* DENALI_PHY_857_DATA */
+ 0x00000000 /* DENALI_PHY_858_DATA */
+ 0x00000000 /* DENALI_PHY_859_DATA */
+ 0x00000000 /* DENALI_PHY_860_DATA */
+ 0x00000000 /* DENALI_PHY_861_DATA */
+ 0x00000000 /* DENALI_PHY_862_DATA */
+ 0x00000000 /* DENALI_PHY_863_DATA */
+ 0x00000000 /* DENALI_PHY_864_DATA */
+ 0x00000000 /* DENALI_PHY_865_DATA */
+ 0x00000000 /* DENALI_PHY_866_DATA */
+ 0x00000000 /* DENALI_PHY_867_DATA */
+ 0x00000000 /* DENALI_PHY_868_DATA */
+ 0x00000000 /* DENALI_PHY_869_DATA */
+ 0x00000000 /* DENALI_PHY_870_DATA */
+ 0x00000000 /* DENALI_PHY_871_DATA */
+ 0x00000000 /* DENALI_PHY_872_DATA */
+ 0x00000000 /* DENALI_PHY_873_DATA */
+ 0x00000000 /* DENALI_PHY_874_DATA */
+ 0x00000000 /* DENALI_PHY_875_DATA */
+ 0x00000000 /* DENALI_PHY_876_DATA */
+ 0x00000000 /* DENALI_PHY_877_DATA */
+ 0x00000000 /* DENALI_PHY_878_DATA */
+ 0x00000000 /* DENALI_PHY_879_DATA */
+ 0x00000000 /* DENALI_PHY_880_DATA */
+ 0x00000000 /* DENALI_PHY_881_DATA */
+ 0x00000000 /* DENALI_PHY_882_DATA */
+ 0x00000000 /* DENALI_PHY_883_DATA */
+ 0x00000000 /* DENALI_PHY_884_DATA */
+ 0x00000000 /* DENALI_PHY_885_DATA */
+ 0x00000000 /* DENALI_PHY_886_DATA */
+ 0x00000000 /* DENALI_PHY_887_DATA */
+ 0x00000000 /* DENALI_PHY_888_DATA */
+ 0x00000000 /* DENALI_PHY_889_DATA */
+ 0x00000000 /* DENALI_PHY_890_DATA */
+ 0x00000000 /* DENALI_PHY_891_DATA */
+ 0x00000000 /* DENALI_PHY_892_DATA */
+ 0x00000000 /* DENALI_PHY_893_DATA */
+ 0x00000000 /* DENALI_PHY_894_DATA */
+ 0x00000000 /* DENALI_PHY_895_DATA */
+ 0x41753260 /* DENALI_PHY_896_DATA */
+ 0x0004c008 /* DENALI_PHY_897_DATA */
+ 0x000000da /* DENALI_PHY_898_DATA */
+ 0x00000000 /* DENALI_PHY_899_DATA */
+ 0x00000000 /* DENALI_PHY_900_DATA */
+ 0x00010000 /* DENALI_PHY_901_DATA */
+ 0x01DDDD90 /* DENALI_PHY_902_DATA */
+ 0x01DDDD90 /* DENALI_PHY_903_DATA */
+ 0x01030001 /* DENALI_PHY_904_DATA */
+ 0x01000000 /* DENALI_PHY_905_DATA */
+ 0x00c00000 /* DENALI_PHY_906_DATA */
+ 0x00000007 /* DENALI_PHY_907_DATA */
+ 0x00000000 /* DENALI_PHY_908_DATA */
+ 0x00000000 /* DENALI_PHY_909_DATA */
+ 0x04000408 /* DENALI_PHY_910_DATA */
+ 0x00000408 /* DENALI_PHY_911_DATA */
+ 0x00e4e400 /* DENALI_PHY_912_DATA */
+ 0x00000000 /* DENALI_PHY_913_DATA */
+ 0x00000000 /* DENALI_PHY_914_DATA */
+ 0x00000000 /* DENALI_PHY_915_DATA */
+ 0x00000000 /* DENALI_PHY_916_DATA */
+ 0x00000000 /* DENALI_PHY_917_DATA */
+ 0x00000000 /* DENALI_PHY_918_DATA */
+ 0x00000000 /* DENALI_PHY_919_DATA */
+ 0x00000000 /* DENALI_PHY_920_DATA */
+ 0x00000000 /* DENALI_PHY_921_DATA */
+ 0x00000000 /* DENALI_PHY_922_DATA */
+ 0x00000000 /* DENALI_PHY_923_DATA */
+ 0x00000000 /* DENALI_PHY_924_DATA */
+ 0x00000000 /* DENALI_PHY_925_DATA */
+ 0x00000000 /* DENALI_PHY_926_DATA */
+ 0x00000000 /* DENALI_PHY_927_DATA */
+ 0x00000000 /* DENALI_PHY_928_DATA */
+ 0x00200000 /* DENALI_PHY_929_DATA */
+ 0x00000000 /* DENALI_PHY_930_DATA */
+ 0x00000000 /* DENALI_PHY_931_DATA */
+ 0x00000000 /* DENALI_PHY_932_DATA */
+ 0x00000000 /* DENALI_PHY_933_DATA */
+ 0x00000000 /* DENALI_PHY_934_DATA */
+ 0x00000000 /* DENALI_PHY_935_DATA */
+ 0x02800280 /* DENALI_PHY_936_DATA */
+ 0x02800280 /* DENALI_PHY_937_DATA */
+ 0x02800280 /* DENALI_PHY_938_DATA */
+ 0x02800280 /* DENALI_PHY_939_DATA */
+ 0x00000280 /* DENALI_PHY_940_DATA */
+ 0x00000000 /* DENALI_PHY_941_DATA */
+ 0x00000000 /* DENALI_PHY_942_DATA */
+ 0x00000000 /* DENALI_PHY_943_DATA */
+ 0x00000000 /* DENALI_PHY_944_DATA */
+ 0x00000000 /* DENALI_PHY_945_DATA */
+ 0x00800080 /* DENALI_PHY_946_DATA */
+ 0x00800080 /* DENALI_PHY_947_DATA */
+ 0x00800080 /* DENALI_PHY_948_DATA */
+ 0x00800080 /* DENALI_PHY_949_DATA */
+ 0x00800080 /* DENALI_PHY_950_DATA */
+ 0x00800080 /* DENALI_PHY_951_DATA */
+ 0x00800080 /* DENALI_PHY_952_DATA */
+ 0x00800080 /* DENALI_PHY_953_DATA */
+ 0x00800080 /* DENALI_PHY_954_DATA */
+ 0x000100da /* DENALI_PHY_955_DATA */
+ 0x01ff0010 /* DENALI_PHY_956_DATA */
+ 0x00000000 /* DENALI_PHY_957_DATA */
+ 0x00000000 /* DENALI_PHY_958_DATA */
+ 0x00000002 /* DENALI_PHY_959_DATA */
+ 0x51313152 /* DENALI_PHY_960_DATA */
+ 0x80013130 /* DENALI_PHY_961_DATA */
+ 0x02000080 /* DENALI_PHY_962_DATA */
+ 0x00100001 /* DENALI_PHY_963_DATA */
+ 0x0c064208 /* DENALI_PHY_964_DATA */
+ 0x000f0c0f /* DENALI_PHY_965_DATA */
+ 0x01000140 /* DENALI_PHY_966_DATA */
+ 0x0000000c /* DENALI_PHY_967_DATA */
+ 0x00000000 /* DENALI_PHY_968_DATA */
+ 0x00000000 /* DENALI_PHY_969_DATA */
+ 0x00000000 /* DENALI_PHY_970_DATA */
+ 0x00000000 /* DENALI_PHY_971_DATA */
+ 0x00000000 /* DENALI_PHY_972_DATA */
+ 0x00000000 /* DENALI_PHY_973_DATA */
+ 0x00000000 /* DENALI_PHY_974_DATA */
+ 0x00000000 /* DENALI_PHY_975_DATA */
+ 0x00000000 /* DENALI_PHY_976_DATA */
+ 0x00000000 /* DENALI_PHY_977_DATA */
+ 0x00000000 /* DENALI_PHY_978_DATA */
+ 0x00000000 /* DENALI_PHY_979_DATA */
+ 0x00000000 /* DENALI_PHY_980_DATA */
+ 0x00000000 /* DENALI_PHY_981_DATA */
+ 0x00000000 /* DENALI_PHY_982_DATA */
+ 0x00000000 /* DENALI_PHY_983_DATA */
+ 0x00000000 /* DENALI_PHY_984_DATA */
+ 0x00000000 /* DENALI_PHY_985_DATA */
+ 0x00000000 /* DENALI_PHY_986_DATA */
+ 0x00000000 /* DENALI_PHY_987_DATA */
+ 0x00000000 /* DENALI_PHY_988_DATA */
+ 0x00000000 /* DENALI_PHY_989_DATA */
+ 0x00000000 /* DENALI_PHY_990_DATA */
+ 0x00000000 /* DENALI_PHY_991_DATA */
+ 0x00000000 /* DENALI_PHY_992_DATA */
+ 0x00000000 /* DENALI_PHY_993_DATA */
+ 0x00000000 /* DENALI_PHY_994_DATA */
+ 0x00000000 /* DENALI_PHY_995_DATA */
+ 0x00000000 /* DENALI_PHY_996_DATA */
+ 0x00000000 /* DENALI_PHY_997_DATA */
+ 0x00000000 /* DENALI_PHY_998_DATA */
+ 0x00000000 /* DENALI_PHY_999_DATA */
+ 0x00000000 /* DENALI_PHY_1000_DATA */
+ 0x00000000 /* DENALI_PHY_1001_DATA */
+ 0x00000000 /* DENALI_PHY_1002_DATA */
+ 0x00000000 /* DENALI_PHY_1003_DATA */
+ 0x00000000 /* DENALI_PHY_1004_DATA */
+ 0x00000000 /* DENALI_PHY_1005_DATA */
+ 0x00000000 /* DENALI_PHY_1006_DATA */
+ 0x00000000 /* DENALI_PHY_1007_DATA */
+ 0x00000000 /* DENALI_PHY_1008_DATA */
+ 0x00000000 /* DENALI_PHY_1009_DATA */
+ 0x00000000 /* DENALI_PHY_1010_DATA */
+ 0x00000000 /* DENALI_PHY_1011_DATA */
+ 0x00000000 /* DENALI_PHY_1012_DATA */
+ 0x00000000 /* DENALI_PHY_1013_DATA */
+ 0x00000000 /* DENALI_PHY_1014_DATA */
+ 0x00000000 /* DENALI_PHY_1015_DATA */
+ 0x00000000 /* DENALI_PHY_1016_DATA */
+ 0x00000000 /* DENALI_PHY_1017_DATA */
+ 0x00000000 /* DENALI_PHY_1018_DATA */
+ 0x00000000 /* DENALI_PHY_1019_DATA */
+ 0x00000000 /* DENALI_PHY_1020_DATA */
+ 0x00000000 /* DENALI_PHY_1021_DATA */
+ 0x00000000 /* DENALI_PHY_1022_DATA */
+ 0x00000000 /* DENALI_PHY_1023_DATA */
+ 0x76543210 /* DENALI_PHY_1024_DATA */
+ 0x0004c008 /* DENALI_PHY_1025_DATA */
+ 0x000000da /* DENALI_PHY_1026_DATA */
+ 0x00000000 /* DENALI_PHY_1027_DATA */
+ 0x00000000 /* DENALI_PHY_1028_DATA */
+ 0x00010000 /* DENALI_PHY_1029_DATA */
+ 0x01665555 /* DENALI_PHY_1030_DATA */
+ 0x01665555 /* DENALI_PHY_1031_DATA */
+ 0x01030001 /* DENALI_PHY_1032_DATA */
+ 0x01000000 /* DENALI_PHY_1033_DATA */
+ 0x00c00000 /* DENALI_PHY_1034_DATA */
+ 0x00000007 /* DENALI_PHY_1035_DATA */
+ 0x00000000 /* DENALI_PHY_1036_DATA */
+ 0x00000000 /* DENALI_PHY_1037_DATA */
+ 0x04000408 /* DENALI_PHY_1038_DATA */
+ 0x00000408 /* DENALI_PHY_1039_DATA */
+ 0x00e4e400 /* DENALI_PHY_1040_DATA */
+ 0x00000000 /* DENALI_PHY_1041_DATA */
+ 0x00000000 /* DENALI_PHY_1042_DATA */
+ 0x00000000 /* DENALI_PHY_1043_DATA */
+ 0x00000000 /* DENALI_PHY_1044_DATA */
+ 0x00000000 /* DENALI_PHY_1045_DATA */
+ 0x00000000 /* DENALI_PHY_1046_DATA */
+ 0x00000000 /* DENALI_PHY_1047_DATA */
+ 0x00000000 /* DENALI_PHY_1048_DATA */
+ 0x00000000 /* DENALI_PHY_1049_DATA */
+ 0x00000000 /* DENALI_PHY_1050_DATA */
+ 0x00000000 /* DENALI_PHY_1051_DATA */
+ 0x00000000 /* DENALI_PHY_1052_DATA */
+ 0x00000000 /* DENALI_PHY_1053_DATA */
+ 0x00000000 /* DENALI_PHY_1054_DATA */
+ 0x00000000 /* DENALI_PHY_1055_DATA */
+ 0x00000000 /* DENALI_PHY_1056_DATA */
+ 0x00200000 /* DENALI_PHY_1057_DATA */
+ 0x00000000 /* DENALI_PHY_1058_DATA */
+ 0x00000000 /* DENALI_PHY_1059_DATA */
+ 0x00000000 /* DENALI_PHY_1060_DATA */
+ 0x00000000 /* DENALI_PHY_1061_DATA */
+ 0x00000000 /* DENALI_PHY_1062_DATA */
+ 0x00000000 /* DENALI_PHY_1063_DATA */
+ 0x02800280 /* DENALI_PHY_1064_DATA */
+ 0x02800280 /* DENALI_PHY_1065_DATA */
+ 0x02800280 /* DENALI_PHY_1066_DATA */
+ 0x02800280 /* DENALI_PHY_1067_DATA */
+ 0x00000280 /* DENALI_PHY_1068_DATA */
+ 0x00000000 /* DENALI_PHY_1069_DATA */
+ 0x00000000 /* DENALI_PHY_1070_DATA */
+ 0x00000000 /* DENALI_PHY_1071_DATA */
+ 0x00000000 /* DENALI_PHY_1072_DATA */
+ 0x00000000 /* DENALI_PHY_1073_DATA */
+ 0x00800080 /* DENALI_PHY_1074_DATA */
+ 0x00800080 /* DENALI_PHY_1075_DATA */
+ 0x00800080 /* DENALI_PHY_1076_DATA */
+ 0x00800080 /* DENALI_PHY_1077_DATA */
+ 0x00800080 /* DENALI_PHY_1078_DATA */
+ 0x00800080 /* DENALI_PHY_1079_DATA */
+ 0x00800080 /* DENALI_PHY_1080_DATA */
+ 0x00800080 /* DENALI_PHY_1081_DATA */
+ 0x00800080 /* DENALI_PHY_1082_DATA */
+ 0x000100da /* DENALI_PHY_1083_DATA */
+ 0x01ff0010 /* DENALI_PHY_1084_DATA */
+ 0x00000000 /* DENALI_PHY_1085_DATA */
+ 0x00000000 /* DENALI_PHY_1086_DATA */
+ 0x00000002 /* DENALI_PHY_1087_DATA */
+ 0x51313152 /* DENALI_PHY_1088_DATA */
+ 0x80013130 /* DENALI_PHY_1089_DATA */
+ 0x02000080 /* DENALI_PHY_1090_DATA */
+ 0x00100001 /* DENALI_PHY_1091_DATA */
+ 0x0c064208 /* DENALI_PHY_1092_DATA */
+ 0x000f0c0f /* DENALI_PHY_1093_DATA */
+ 0x01000140 /* DENALI_PHY_1094_DATA */
+ 0x0000000c /* DENALI_PHY_1095_DATA */
+ 0x00000000 /* DENALI_PHY_1096_DATA */
+ 0x00000000 /* DENALI_PHY_1097_DATA */
+ 0x00000000 /* DENALI_PHY_1098_DATA */
+ 0x00000000 /* DENALI_PHY_1099_DATA */
+ 0x00000000 /* DENALI_PHY_1100_DATA */
+ 0x00000000 /* DENALI_PHY_1101_DATA */
+ 0x00000000 /* DENALI_PHY_1102_DATA */
+ 0x00000000 /* DENALI_PHY_1103_DATA */
+ 0x00000000 /* DENALI_PHY_1104_DATA */
+ 0x00000000 /* DENALI_PHY_1105_DATA */
+ 0x00000000 /* DENALI_PHY_1106_DATA */
+ 0x00000000 /* DENALI_PHY_1107_DATA */
+ 0x00000000 /* DENALI_PHY_1108_DATA */
+ 0x00000000 /* DENALI_PHY_1109_DATA */
+ 0x00000000 /* DENALI_PHY_1110_DATA */
+ 0x00000000 /* DENALI_PHY_1111_DATA */
+ 0x00000000 /* DENALI_PHY_1112_DATA */
+ 0x00000000 /* DENALI_PHY_1113_DATA */
+ 0x00000000 /* DENALI_PHY_1114_DATA */
+ 0x00000000 /* DENALI_PHY_1115_DATA */
+ 0x00000000 /* DENALI_PHY_1116_DATA */
+ 0x00000000 /* DENALI_PHY_1117_DATA */
+ 0x00000000 /* DENALI_PHY_1118_DATA */
+ 0x00000000 /* DENALI_PHY_1119_DATA */
+ 0x00000000 /* DENALI_PHY_1120_DATA */
+ 0x00000000 /* DENALI_PHY_1121_DATA */
+ 0x00000000 /* DENALI_PHY_1122_DATA */
+ 0x00000000 /* DENALI_PHY_1123_DATA */
+ 0x00000000 /* DENALI_PHY_1124_DATA */
+ 0x00000000 /* DENALI_PHY_1125_DATA */
+ 0x00000000 /* DENALI_PHY_1126_DATA */
+ 0x00000000 /* DENALI_PHY_1127_DATA */
+ 0x00000000 /* DENALI_PHY_1128_DATA */
+ 0x00000000 /* DENALI_PHY_1129_DATA */
+ 0x00000000 /* DENALI_PHY_1130_DATA */
+ 0x00000000 /* DENALI_PHY_1131_DATA */
+ 0x00000000 /* DENALI_PHY_1132_DATA */
+ 0x00000000 /* DENALI_PHY_1133_DATA */
+ 0x00000000 /* DENALI_PHY_1134_DATA */
+ 0x00000000 /* DENALI_PHY_1135_DATA */
+ 0x00000000 /* DENALI_PHY_1136_DATA */
+ 0x00000000 /* DENALI_PHY_1137_DATA */
+ 0x00000000 /* DENALI_PHY_1138_DATA */
+ 0x00000000 /* DENALI_PHY_1139_DATA */
+ 0x00000000 /* DENALI_PHY_1140_DATA */
+ 0x00000000 /* DENALI_PHY_1141_DATA */
+ 0x00000000 /* DENALI_PHY_1142_DATA */
+ 0x00000000 /* DENALI_PHY_1143_DATA */
+ 0x00000000 /* DENALI_PHY_1144_DATA */
+ 0x00000000 /* DENALI_PHY_1145_DATA */
+ 0x00000000 /* DENALI_PHY_1146_DATA */
+ 0x00000000 /* DENALI_PHY_1147_DATA */
+ 0x00000000 /* DENALI_PHY_1148_DATA */
+ 0x00000000 /* DENALI_PHY_1149_DATA */
+ 0x00000000 /* DENALI_PHY_1150_DATA */
+ 0x00000000 /* DENALI_PHY_1151_DATA */
+ 0x00000000 /* DENALI_PHY_1152_DATA */
+ 0x00000000 /* DENALI_PHY_1153_DATA */
+ 0x00050000 /* DENALI_PHY_1154_DATA */
+ 0x00000000 /* DENALI_PHY_1155_DATA */
+ 0x00000000 /* DENALI_PHY_1156_DATA */
+ 0x00000000 /* DENALI_PHY_1157_DATA */
+ 0x00000100 /* DENALI_PHY_1158_DATA */
+ 0x00000000 /* DENALI_PHY_1159_DATA */
+ 0x00000000 /* DENALI_PHY_1160_DATA */
+ 0x00506401 /* DENALI_PHY_1161_DATA */
+ 0x01221102 /* DENALI_PHY_1162_DATA */
+ 0x00000122 /* DENALI_PHY_1163_DATA */
+ 0x00000000 /* DENALI_PHY_1164_DATA */
+ 0x000B1F00 /* DENALI_PHY_1165_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1166_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1167_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1168_DATA */
+ 0x0B1F0B1F /* DENALI_PHY_1169_DATA */
+ 0x00000B00 /* DENALI_PHY_1170_DATA */
+ 0x42080010 /* DENALI_PHY_1171_DATA */
+ 0x01000100 /* DENALI_PHY_1172_DATA */
+ 0x01000100 /* DENALI_PHY_1173_DATA */
+ 0x01000100 /* DENALI_PHY_1174_DATA */
+ 0x01000100 /* DENALI_PHY_1175_DATA */
+ 0x00000000 /* DENALI_PHY_1176_DATA */
+ 0x00000000 /* DENALI_PHY_1177_DATA */
+ 0x00000000 /* DENALI_PHY_1178_DATA */
+ 0x00000000 /* DENALI_PHY_1179_DATA */
+ 0x00000000 /* DENALI_PHY_1180_DATA */
+ 0x00000803 /* DENALI_PHY_1181_DATA */
+ 0x223FFF00 /* DENALI_PHY_1182_DATA */
+ 0x000008FF /* DENALI_PHY_1183_DATA */
+ 0x0000057F /* DENALI_PHY_1184_DATA */
+ 0x0000057F /* DENALI_PHY_1185_DATA */
+ 0x00037FFF /* DENALI_PHY_1186_DATA */
+ 0x00037FFF /* DENALI_PHY_1187_DATA */
+ 0x00004410 /* DENALI_PHY_1188_DATA */
+ 0x00004410 /* DENALI_PHY_1189_DATA */
+ 0x00004410 /* DENALI_PHY_1190_DATA */
+ 0x00004410 /* DENALI_PHY_1191_DATA */
+ 0x00004410 /* DENALI_PHY_1192_DATA */
+ 0x00000111 /* DENALI_PHY_1193_DATA */
+ 0x00000111 /* DENALI_PHY_1194_DATA */
+ 0x00000000 /* DENALI_PHY_1195_DATA */
+ 0x00000000 /* DENALI_PHY_1196_DATA */
+ 0x00000000 /* DENALI_PHY_1197_DATA */
+ 0x04000000 /* DENALI_PHY_1198_DATA */
+ 0x00000000 /* DENALI_PHY_1199_DATA */
+ 0x00000000 /* DENALI_PHY_1200_DATA */
+ 0x00000108 /* DENALI_PHY_1201_DATA */
+ 0x00000000 /* DENALI_PHY_1202_DATA */
+ 0x00000000 /* DENALI_PHY_1203_DATA */
+ 0x00000000 /* DENALI_PHY_1204_DATA */
+ 0x00000001 /* DENALI_PHY_1205_DATA */
+ 0x00000000 /* DENALI_PHY_1206_DATA */
+ 0x00000000 /* DENALI_PHY_1207_DATA */
+ 0x00000000 /* DENALI_PHY_1208_DATA */
+ 0x00000000 /* DENALI_PHY_1209_DATA */
+ 0x00000000 /* DENALI_PHY_1210_DATA */
+ 0x00000000 /* DENALI_PHY_1211_DATA */
+ 0x00020100 /* DENALI_PHY_1212_DATA */
+ 0x00000000 /* DENALI_PHY_1213_DATA */
+ 0x00000000 /* DENALI_PHY_1214_DATA */
+ >;
+};
diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
index 1996149..51b5661 100644
--- a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
+++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
@@ -3,6 +3,7 @@
* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
*/
+#include "binman.dtsi"
#include "fu540-c000-u-boot.dtsi"
#include "fu540-hifive-unleashed-a00-ddr.dtsi"
diff --git a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
new file mode 100644
index 0000000..c5475aa
--- /dev/null
+++ b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc
+ */
+
+#include "binman.dtsi"
+#include "fu740-c000-u-boot.dtsi"
+#include "fu740-hifive-unmatched-a00-ddr.dtsi"
+
+/ {
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory@80000000 {
+ u-boot,dm-spl;
+ };
+
+ hfclk {
+ u-boot,dm-spl;
+ };
+
+ rtcclk {
+ u-boot,dm-spl;
+ };
+
+};
+
+&clint {
+ clocks = <&rtcclk>;
+};
+
+&spi0 {
+ mmc@0 {
+ u-boot,dm-spl;
+ };
+};
+
+&gpio {
+ u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts
new file mode 100644
index 0000000..b44e8c1
--- /dev/null
+++ b/arch/riscv/dts/hifive-unmatched-a00.dts
@@ -0,0 +1,259 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2019-2021 SiFive, Inc */
+
+#include "fu740-c000.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ 1000000
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ model = "SiFive HiFive Unmatched A00";
+ compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+ "sifive,fu740";
+
+ chosen {
+ stdout-path = "serial0";
+ };
+
+ cpus {
+ timebase-frequency = <RTCCLK_FREQ>;
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x4 0x00000000>;
+ };
+
+ soc {
+ };
+
+ hfclk: hfclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <26000000>;
+ clock-output-names = "hfclk";
+ };
+
+ rtcclk: rtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <RTCCLK_FREQ>;
+ clock-output-names = "rtcclk";
+ };
+
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ temperature-sensor@4c {
+ compatible = "ti,tmp451";
+ reg = <0x4c>;
+ interrupt-parent = <&gpio>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ pmic@58 {
+ compatible = "dlg,da9063";
+ reg = <0x58>;
+ interrupt-parent = <&gpio>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+
+ regulators {
+ vdd_bcore1: bcore1 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <5000000>;
+ regulator-max-microamp = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_bcore2: bcore2 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <5000000>;
+ regulator-max-microamp = <5000000>;
+ regulator-always-on;
+ };
+
+ vdd_bpro: bpro {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <2500000>;
+ regulator-max-microamp = <2500000>;
+ regulator-always-on;
+ };
+
+ vdd_bperi: bperi {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <1500000>;
+ regulator-max-microamp = <1500000>;
+ regulator-always-on;
+ };
+
+ vdd_bmem: bmem {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_bio: bio {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3000000>;
+ regulator-max-microamp = <3000000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo1: ldo1 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <100000>;
+ regulator-max-microamp = <100000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo2: ldo2 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo3: ldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo4: ldo4 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo5: ldo5 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microamp = <100000>;
+ regulator-max-microamp = <100000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo6: ldo6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo7: ldo7 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ldo8: ldo8 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ regulator-always-on;
+ };
+
+ vdd_ld09: ldo9 {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-min-microamp = <200000>;
+ regulator-max-microamp = <200000>;
+ };
+
+ vdd_ldo10: ldo10 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-min-microamp = <300000>;
+ regulator-max-microamp = <300000>;
+ };
+
+ vdd_ldo11: ldo11 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-min-microamp = <300000>;
+ regulator-max-microamp = <300000>;
+ regulator-always-on;
+ };
+ };
+ };
+};
+
+&qspi0 {
+ status = "okay";
+ flash@0 {
+ compatible = "issi,is25wp256", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ m25p,fast-read;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+ mmc@0 {
+ compatible = "mmc-spi-slot";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ voltage-ranges = <3300 3300>;
+ disable-wp;
+ };
+};
+
+ð0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy0>;
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&gpio {
+ status = "okay";
+};
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 0b79a29..8bcd3ce 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -86,29 +86,20 @@
reg = <0x80000000 0x400000>,
<0x80400000 0x200000>,
<0x80600000 0x200000>;
- reg-names = "sram0", "sram1", "airam";
+ reg-names = "sram0", "sram1", "aisram";
clocks = <&sysclk K210_CLK_SRAM0>,
<&sysclk K210_CLK_SRAM1>,
- <&sysclk K210_CLK_PLL1>;
- clock-names = "sram0", "sram1", "airam";
+ <&sysclk K210_CLK_AI>;
+ clock-names = "sram0", "sram1", "aisram";
+ u-boot,dm-pre-reloc;
};
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- ai_reserved: ai@80600000 {
- reg = <0x80600000 0x200000>;
- reusable;
- };
- };
-
clocks {
in0: osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
+ u-boot,dm-pre-reloc;
};
};
@@ -177,7 +168,6 @@
reg = <0x40800000 0xc00000>;
interrupts = <25>;
clocks = <&sysclk K210_CLK_AI>;
- memory-region = <&ai_reserved>;
status = "disabled";
};
@@ -505,11 +495,15 @@
"syscon", "simple-mfd";
reg = <0x50440000 0x100>;
reg-io-width = <4>;
+ u-boot,dm-pre-reloc;
sysclk: clock-controller {
#clock-cells = <1>;
compatible = "kendryte,k210-clk";
clocks = <&in0>;
+ assigned-clocks = <&sysclk K210_CLK_PLL1>;
+ assigned-clock-rates = <390000000>;
+ u-boot,dm-pre-reloc;
};
sysrst: reset-controller {
diff --git a/arch/riscv/dts/qemu-virt.dts b/arch/riscv/dts/qemu-virt.dts
new file mode 100644
index 0000000..fecff54
--- /dev/null
+++ b/arch/riscv/dts/qemu-virt.dts
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "binman.dtsi"
diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h
new file mode 100644
index 0000000..7d4fe99
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu740/cache.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _CACHE_SIFIVE_H
+#define _CACHE_SIFIVE_H
+
+int cache_enable_ways(void);
+
+#endif /* _CACHE_SIFIVE_H */
diff --git a/arch/riscv/include/asm/arch-fu740/clk.h b/arch/riscv/include/asm/arch-fu740/clk.h
new file mode 100644
index 0000000..9f88361
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu740/clk.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020-2021 SiFive Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __CLK_SIFIVE_H
+#define __CLK_SIFIVE_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/arch/riscv/include/asm/arch-fu740/gpio.h b/arch/riscv/include/asm/arch-fu740/gpio.h
new file mode 100644
index 0000000..908e2e5
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu740/gpio.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ */
+
+#ifndef _GPIO_SIFIVE_H
+#define _GPIO_SIFIVE_H
+
+#define GPIO_INPUT_VAL 0x00
+#define GPIO_INPUT_EN 0x04
+#define GPIO_OUTPUT_EN 0x08
+#define GPIO_OUTPUT_VAL 0x0C
+#define GPIO_RISE_IE 0x18
+#define GPIO_RISE_IP 0x1C
+#define GPIO_FALL_IE 0x20
+#define GPIO_FALL_IP 0x24
+#define GPIO_HIGH_IE 0x28
+#define GPIO_HIGH_IP 0x2C
+#define GPIO_LOW_IE 0x30
+#define GPIO_LOW_IP 0x34
+#define GPIO_OUTPUT_XOR 0x40
+
+#define NR_GPIOS 16
+
+enum gpio_state {
+ LOW,
+ HIGH
+};
+
+/* Details about a GPIO bank */
+struct sifive_gpio_plat {
+ void *base; /* address of registers in physical memory */
+};
+
+#define SIFIVE_GENERIC_GPIO_NR(port, index) \
+ (((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
+
+#endif /* _GPIO_SIFIVE_H */
diff --git a/arch/riscv/include/asm/arch-fu740/reset.h b/arch/riscv/include/asm/arch-fu740/reset.h
new file mode 100644
index 0000000..538ef87
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu740/reset.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020-2021 SiFive, Inc.
+ *
+ * Author: Sagar Kadam <sagar.kadam@sifive.com>
+ */
+
+#ifndef __RESET_SIFIVE_H
+#define __RESET_SIFIVE_H
+
+int sifive_reset_bind(struct udevice *dev, ulong count);
+
+#endif
diff --git a/arch/riscv/include/asm/arch-fu740/spl.h b/arch/riscv/include/asm/arch-fu740/spl.h
new file mode 100644
index 0000000..15ad9e7
--- /dev/null
+++ b/arch/riscv/include/asm/arch-fu740/spl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifve.com>
+ */
+
+#ifndef _SPL_SIFIVE_H
+#define _SPL_SIFIVE_H
+
+int spl_soc_init(void);
+
+#endif /* _SPL_SIFIVE_H */
diff --git a/arch/riscv/include/asm/global_data.h b/arch/riscv/include/asm/global_data.h
index d3a0b1d..095484a 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -18,7 +18,7 @@
struct arch_global_data {
long boot_hart; /* boot hart id */
phys_addr_t firmware_fdt_addr;
-#ifdef CONFIG_SIFIVE_CLINT
+#if CONFIG_IS_ENABLED(SIFIVE_CLINT)
void __iomem *clint; /* clint base address */
#endif
#ifdef CONFIG_ANDES_PLIC
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index d08cbe9..c4cc414 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,7 +11,7 @@
obj-$(CONFIG_CMD_GO) += boot.o
obj-y += cache.o
ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
-obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
else
obj-$(CONFIG_SBI) += sbi.o
diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c
index 1f3f236..f636b28 100644
--- a/arch/riscv/lib/fdt_fixup.c
+++ b/arch/riscv/lib/fdt_fixup.c
@@ -151,14 +151,17 @@
}
chosen_offset = fdt_path_offset(blob, "/chosen");
if (chosen_offset < 0) {
- err = fdt_add_subnode(blob, 0, "chosen");
- if (err < 0) {
+ chosen_offset = fdt_add_subnode(blob, 0, "chosen");
+ if (chosen_offset < 0) {
log_err("chosen node cannot be added\n");
- return err;
+ return chosen_offset;
}
}
/* Overwrite the boot-hartid as U-Boot is the last stage BL */
- fdt_setprop_u32(blob, chosen_offset, "boot-hartid", gd->arch.boot_hart);
+ err = fdt_setprop_u32(blob, chosen_offset, "boot-hartid",
+ gd->arch.boot_hart);
+ if (err < 0)
+ return log_msg_ret("could not set boot-hartid", err);
#endif
/* Copy the reserved-memory node to the DT used by OS */
diff --git a/arch/riscv/lib/memcpy.S b/arch/riscv/lib/memcpy.S
index 51ab716..00672c1 100644
--- a/arch/riscv/lib/memcpy.S
+++ b/arch/riscv/lib/memcpy.S
@@ -9,100 +9,151 @@
/* void *memcpy(void *, const void *, size_t) */
ENTRY(__memcpy)
WEAK(memcpy)
- move t6, a0 /* Preserve return value */
+ /* Save for return value */
+ mv t6, a0
- /* Defer to byte-oriented copy for small sizes */
- sltiu a3, a2, 128
- bnez a3, 4f
- /* Use word-oriented copy only if low-order bits match */
- andi a3, t6, SZREG-1
- andi a4, a1, SZREG-1
- bne a3, a4, 4f
+ /*
+ * Register allocation for code below:
+ * a0 - start of uncopied dst
+ * a1 - start of uncopied src
+ * t0 - end of uncopied dst
+ */
+ add t0, a0, a2
- beqz a3, 2f /* Skip if already aligned */
/*
- * Round to nearest double word-aligned address
- * greater than or equal to start address
+ * Use bytewise copy if too small.
+ *
+ * This threshold must be at least 2*SZREG to ensure at least one
+ * wordwise copy is performed. It is chosen to be 16 because it will
+ * save at least 7 iterations of bytewise copy, which pays off the
+ * fixed overhead.
*/
- andi a3, a1, ~(SZREG-1)
- addi a3, a3, SZREG
- /* Handle initial misalignment */
- sub a4, a3, a1
+ li a3, 16
+ bltu a2, a3, .Lbyte_copy_tail
+
+ /*
+ * Bytewise copy first to align a0 to word boundary.
+ */
+ addi a2, a0, SZREG-1
+ andi a2, a2, ~(SZREG-1)
+ beq a0, a2, 2f
1:
- lb a5, 0(a1)
- addi a1, a1, 1
- sb a5, 0(t6)
- addi t6, t6, 1
- bltu a1, a3, 1b
- sub a2, a2, a4 /* Update count */
+ lb a5, 0(a1)
+ addi a1, a1, 1
+ sb a5, 0(a0)
+ addi a0, a0, 1
+ bne a0, a2, 1b
+2:
+ /*
+ * Now a0 is word-aligned. If a1 is also word aligned, we could perform
+ * aligned word-wise copy. Otherwise we need to perform misaligned
+ * word-wise copy.
+ */
+ andi a3, a1, SZREG-1
+ bnez a3, .Lmisaligned_word_copy
+
+ /* Unrolled wordwise copy */
+ addi t0, t0, -(16*SZREG-1)
+ bgeu a0, t0, 2f
+1:
+ REG_L a2, 0(a1)
+ REG_L a3, SZREG(a1)
+ REG_L a4, 2*SZREG(a1)
+ REG_L a5, 3*SZREG(a1)
+ REG_L a6, 4*SZREG(a1)
+ REG_L a7, 5*SZREG(a1)
+ REG_L t1, 6*SZREG(a1)
+ REG_L t2, 7*SZREG(a1)
+ REG_L t3, 8*SZREG(a1)
+ REG_L t4, 9*SZREG(a1)
+ REG_L t5, 10*SZREG(a1)
+ REG_S a2, 0(a0)
+ REG_S a3, SZREG(a0)
+ REG_S a4, 2*SZREG(a0)
+ REG_S a5, 3*SZREG(a0)
+ REG_S a6, 4*SZREG(a0)
+ REG_S a7, 5*SZREG(a0)
+ REG_S t1, 6*SZREG(a0)
+ REG_S t2, 7*SZREG(a0)
+ REG_S t3, 8*SZREG(a0)
+ REG_S t4, 9*SZREG(a0)
+ REG_S t5, 10*SZREG(a0)
+ REG_L a2, 11*SZREG(a1)
+ REG_L a3, 12*SZREG(a1)
+ REG_L a4, 13*SZREG(a1)
+ REG_L a5, 14*SZREG(a1)
+ REG_L a6, 15*SZREG(a1)
+ addi a1, a1, 16*SZREG
+ REG_S a2, 11*SZREG(a0)
+ REG_S a3, 12*SZREG(a0)
+ REG_S a4, 13*SZREG(a0)
+ REG_S a5, 14*SZREG(a0)
+ REG_S a6, 15*SZREG(a0)
+ addi a0, a0, 16*SZREG
+ bltu a0, t0, 1b
2:
- andi a4, a2, ~((16*SZREG)-1)
- beqz a4, 4f
- add a3, a1, a4
-3:
- REG_L a4, 0(a1)
- REG_L a5, SZREG(a1)
- REG_L a6, 2*SZREG(a1)
- REG_L a7, 3*SZREG(a1)
- REG_L t0, 4*SZREG(a1)
- REG_L t1, 5*SZREG(a1)
- REG_L t2, 6*SZREG(a1)
- REG_L t3, 7*SZREG(a1)
- REG_L t4, 8*SZREG(a1)
- REG_L t5, 9*SZREG(a1)
- REG_S a4, 0(t6)
- REG_S a5, SZREG(t6)
- REG_S a6, 2*SZREG(t6)
- REG_S a7, 3*SZREG(t6)
- REG_S t0, 4*SZREG(t6)
- REG_S t1, 5*SZREG(t6)
- REG_S t2, 6*SZREG(t6)
- REG_S t3, 7*SZREG(t6)
- REG_S t4, 8*SZREG(t6)
- REG_S t5, 9*SZREG(t6)
- REG_L a4, 10*SZREG(a1)
- REG_L a5, 11*SZREG(a1)
- REG_L a6, 12*SZREG(a1)
- REG_L a7, 13*SZREG(a1)
- REG_L t0, 14*SZREG(a1)
- REG_L t1, 15*SZREG(a1)
- addi a1, a1, 16*SZREG
- REG_S a4, 10*SZREG(t6)
- REG_S a5, 11*SZREG(t6)
- REG_S a6, 12*SZREG(t6)
- REG_S a7, 13*SZREG(t6)
- REG_S t0, 14*SZREG(t6)
- REG_S t1, 15*SZREG(t6)
- addi t6, t6, 16*SZREG
- bltu a1, a3, 3b
- andi a2, a2, (16*SZREG)-1 /* Update count */
+ /* Post-loop increment by 16*SZREG-1 and pre-loop decrement by SZREG-1 */
+ addi t0, t0, 15*SZREG
-4:
- /* Handle trailing misalignment */
- beqz a2, 6f
- add a3, a1, a2
+ /* Wordwise copy */
+ bgeu a0, t0, 2f
+1:
+ REG_L a5, 0(a1)
+ addi a1, a1, SZREG
+ REG_S a5, 0(a0)
+ addi a0, a0, SZREG
+ bltu a0, t0, 1b
+2:
+ addi t0, t0, SZREG-1
- /* Use word-oriented copy if co-aligned to word boundary */
- or a5, a1, t6
- or a5, a5, a3
- andi a5, a5, 3
- bnez a5, 5f
-7:
- lw a4, 0(a1)
- addi a1, a1, 4
- sw a4, 0(t6)
- addi t6, t6, 4
- bltu a1, a3, 7b
+.Lbyte_copy_tail:
+ /*
+ * Bytewise copy anything left.
+ */
+ beq a0, t0, 2f
+1:
+ lb a5, 0(a1)
+ addi a1, a1, 1
+ sb a5, 0(a0)
+ addi a0, a0, 1
+ bne a0, t0, 1b
+2:
+ mv a0, t6
ret
-5:
- lb a4, 0(a1)
- addi a1, a1, 1
- sb a4, 0(t6)
- addi t6, t6, 1
- bltu a1, a3, 5b
-6:
- ret
+.Lmisaligned_word_copy:
+ /*
+ * Misaligned word-wise copy.
+ * For misaligned copy we still perform word-wise copy, but we need to
+ * use the value fetched from the previous iteration and do some shifts.
+ * This is safe because we wouldn't access more words than necessary.
+ */
+
+ /* Calculate shifts */
+ slli t3, a3, 3
+ sub t4, x0, t3 /* negate is okay as shift will only look at LSBs */
+
+ /* Load the initial value and align a1 */
+ andi a1, a1, ~(SZREG-1)
+ REG_L a5, 0(a1)
+
+ addi t0, t0, -(SZREG-1)
+ /* At least one iteration will be executed here, no check */
+1:
+ srl a4, a5, t3
+ REG_L a5, SZREG(a1)
+ addi a1, a1, SZREG
+ sll a2, a5, t4
+ or a2, a2, a4
+ REG_S a2, 0(a0)
+ addi a0, a0, SZREG
+ bltu a0, t0, 1b
+
+ /* Update pointers to correct value */
+ addi t0, t0, SZREG-1
+ add a1, a1, a3
+
+ j .Lbyte_copy_tail
END(__memcpy)
diff --git a/arch/riscv/lib/memmove.S b/arch/riscv/lib/memmove.S
index 07d1d21..fbe6701 100644
--- a/arch/riscv/lib/memmove.S
+++ b/arch/riscv/lib/memmove.S
@@ -5,60 +5,124 @@
ENTRY(__memmove)
WEAK(memmove)
- move t0, a0
- move t1, a1
+ /*
+ * Here we determine if forward copy is possible. Forward copy is
+ * preferred to backward copy as it is more cache friendly.
+ *
+ * If a0 >= a1, t0 gives their distance, if t0 >= a2 then we can
+ * copy forward.
+ * If a0 < a1, we can always copy forward. This will make t0 negative,
+ * so a *unsigned* comparison will always have t0 >= a2.
+ *
+ * For forward copy we just delegate the task to memcpy.
+ */
+ sub t0, a0, a1
+ bltu t0, a2, 1f
+ tail __memcpy
+1:
- beq a0, a1, exit_memcpy
- beqz a2, exit_memcpy
- srli t2, a2, 0x2
+ /*
+ * Register allocation for code below:
+ * a0 - end of uncopied dst
+ * a1 - end of uncopied src
+ * t0 - start of uncopied dst
+ */
+ mv t0, a0
+ add a0, a0, a2
+ add a1, a1, a2
- slt t3, a0, a1
- beqz t3, do_reverse
+ /*
+ * Use bytewise copy if too small.
+ *
+ * This threshold must be at least 2*SZREG to ensure at least one
+ * wordwise copy is performed. It is chosen to be 16 because it will
+ * save at least 7 iterations of bytewise copy, which pays off the
+ * fixed overhead.
+ */
+ li a3, 16
+ bltu a2, a3, .Lbyte_copy_tail
- andi a2, a2, 0x3
- li t4, 1
- beqz t2, byte_copy
+ /*
+ * Bytewise copy first to align t0 to word boundary.
+ */
+ andi a2, a0, ~(SZREG-1)
+ beq a0, a2, 2f
+1:
+ addi a1, a1, -1
+ lb a5, 0(a1)
+ addi a0, a0, -1
+ sb a5, 0(a0)
+ bne a0, a2, 1b
+2:
-word_copy:
- lw t3, 0(a1)
- addi t2, t2, -1
- addi a1, a1, 4
- sw t3, 0(a0)
- addi a0, a0, 4
- bnez t2, word_copy
- beqz a2, exit_memcpy
- j byte_copy
+ /*
+ * Now a0 is word-aligned. If a1 is also word aligned, we could perform
+ * aligned word-wise copy. Otherwise we need to perform misaligned
+ * word-wise copy.
+ */
+ andi a3, a1, SZREG-1
+ bnez a3, .Lmisaligned_word_copy
-do_reverse:
- add a0, a0, a2
- add a1, a1, a2
- andi a2, a2, 0x3
- li t4, -1
- beqz t2, reverse_byte_copy
+ /* Wordwise copy */
+ addi t0, t0, SZREG-1
+ bleu a0, t0, 2f
+1:
+ addi a1, a1, -SZREG
+ REG_L a5, 0(a1)
+ addi a0, a0, -SZREG
+ REG_S a5, 0(a0)
+ bgtu a0, t0, 1b
+2:
+ addi t0, t0, -(SZREG-1)
-reverse_word_copy:
- addi a1, a1, -4
- addi t2, t2, -1
- lw t3, 0(a1)
- addi a0, a0, -4
- sw t3, 0(a0)
- bnez t2, reverse_word_copy
- beqz a2, exit_memcpy
+.Lbyte_copy_tail:
+ /*
+ * Bytewise copy anything left.
+ */
+ beq a0, t0, 2f
+1:
+ addi a1, a1, -1
+ lb a5, 0(a1)
+ addi a0, a0, -1
+ sb a5, 0(a0)
+ bne a0, t0, 1b
+2:
-reverse_byte_copy:
- addi a0, a0, -1
- addi a1, a1, -1
+ mv a0, t0
+ ret
-byte_copy:
- lb t3, 0(a1)
- addi a2, a2, -1
- sb t3, 0(a0)
- add a1, a1, t4
- add a0, a0, t4
- bnez a2, byte_copy
+.Lmisaligned_word_copy:
+ /*
+ * Misaligned word-wise copy.
+ * For misaligned copy we still perform word-wise copy, but we need to
+ * use the value fetched from the previous iteration and do some shifts.
+ * This is safe because we wouldn't access more words than necessary.
+ */
+
+ /* Calculate shifts */
+ slli t3, a3, 3
+ sub t4, x0, t3 /* negate is okay as shift will only look at LSBs */
+
+ /* Load the initial value and align a1 */
+ andi a1, a1, ~(SZREG-1)
+ REG_L a5, 0(a1)
+
+ addi t0, t0, SZREG-1
+ /* At least one iteration will be executed here, no check */
+1:
+ sll a4, a5, t4
+ addi a1, a1, -SZREG
+ REG_L a5, 0(a1)
+ srl a2, a5, t3
+ or a2, a2, a4
+ addi a0, a0, -SZREG
+ REG_S a2, 0(a0)
+ bgtu a0, t0, 1b
+
+ /* Update pointers to correct value */
+ addi t0, t0, -(SZREG-1)
+ add a1, a1, a3
+
+ j .Lbyte_copy_tail
-exit_memcpy:
- move a0, t0
- move a1, t1
- ret
END(__memmove)
diff --git a/arch/riscv/lib/mkimage_fit_opensbi.sh b/arch/riscv/lib/mkimage_fit_opensbi.sh
deleted file mode 100755
index d6f95e5..0000000
--- a/arch/riscv/lib/mkimage_fit_opensbi.sh
+++ /dev/null
@@ -1,100 +0,0 @@
-#!/bin/sh
-# SPDX-License-Identifier: GPL-2.0+
-#
-# script to generate FIT image source for RISC-V boards with OpenSBI
-# and, optionally, multiple device trees (given on the command line).
-#
-# usage: $0 [<dt_name> [<dt_name] ...]
-
-[ -z "$OPENSBI" ] && OPENSBI="fw_dynamic.bin"
-
-if [ -z "$UBOOT_LOAD_ADDR" ]; then
- UBOOT_LOAD_ADDR="$(grep "^CONFIG_SYS_TEXT_BASE=" .config | awk 'BEGIN{FS="="} {print $2}')"
-fi
-
-if [ -z "$OPENSBI_LOAD_ADDR" ]; then
- OPENSBI_LOAD_ADDR="$(grep "^CONFIG_SPL_OPENSBI_LOAD_ADDR=" .config | awk 'BEGIN{FS="="} {print $2}')"
-fi
-
-if [ ! -f $OPENSBI ]; then
- echo "WARNING: OpenSBI binary \"$OPENSBI\" not found, resulting binary is not functional." >&2
- OPENSBI=/dev/null
-fi
-
-cat << __HEADER_EOF
-/dts-v1/;
-
-/ {
- description = "Configuration to load OpenSBI before U-Boot";
-
- images {
- uboot {
- description = "U-Boot";
- data = /incbin/("u-boot-nodtb.bin");
- type = "standalone";
- os = "U-Boot";
- arch = "riscv";
- compression = "none";
- load = <$UBOOT_LOAD_ADDR>;
- };
- opensbi {
- description = "RISC-V OpenSBI";
- data = /incbin/("$OPENSBI");
- type = "firmware";
- os = "opensbi";
- arch = "riscv";
- compression = "none";
- load = <$OPENSBI_LOAD_ADDR>;
- entry = <$OPENSBI_LOAD_ADDR>;
- };
-__HEADER_EOF
-
-cnt=1
-for dtname in $*
-do
- cat << __FDT_IMAGE_EOF
- fdt_$cnt {
- description = "$(basename $dtname .dtb)";
- data = /incbin/("$dtname");
- type = "flat_dt";
- compression = "none";
- };
-__FDT_IMAGE_EOF
-cnt=$((cnt+1))
-done
-
-cat << __CONF_HEADER_EOF
- };
- configurations {
- default = "config_1";
-
-__CONF_HEADER_EOF
-
-if [ $# -eq 0 ]; then
-cat << __CONF_SECTION_EOF
- config_1 {
- description = "U-Boot FIT";
- firmware = "opensbi";
- loadables = "uboot";
- };
-__CONF_SECTION_EOF
-else
-cnt=1
-for dtname in $*
-do
-cat << __CONF_SECTION_EOF
- config_$cnt {
- description = "$(basename $dtname .dtb)";
- firmware = "opensbi";
- loadables = "uboot";
- fdt = "fdt_$cnt";
- };
-__CONF_SECTION_EOF
-cnt=$((cnt+1))
-done
-fi
-
-cat << __ITS_EOF
- };
-};
-__ITS_EOF
diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
index 189e9c2..1f8cb61 100644
--- a/arch/sandbox/config.mk
+++ b/arch/sandbox/config.mk
@@ -17,13 +17,21 @@
endif
cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds $(u-boot-init) \
- -Wl,--start-group $(u-boot-main) -Wl,--end-group \
+ $(LTO_FINAL_LDFLAGS) \
+ -Wl,--whole-archive \
+ $(u-boot-main) \
+ $(u-boot-keep-syms-lto) \
+ -Wl,--no-whole-archive \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map
cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \
+ $(LTO_FINAL_LDFLAGS) \
$(patsubst $(obj)/%,%,$(u-boot-spl-init)) \
- -Wl,--start-group $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \
- $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) -Wl,--end-group \
+ -Wl,--whole-archive \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-keep-syms-lto)) \
+ -Wl,--no-whole-archive \
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections)
CONFIG_ARCH_DEVICE_TREE := sandbox
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index b9ad341..0d21827 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -375,7 +375,8 @@
int os_parse_args(struct sandbox_state *state, int argc, char *argv[])
{
- struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start;
+ struct sandbox_cmdline_option **sb_opt =
+ __u_boot_sandbox_option_start();
size_t num_options = __u_boot_sandbox_option_count();
size_t i;
diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c
index e87365e..6bb9447 100644
--- a/arch/sandbox/cpu/start.c
+++ b/arch/sandbox/cpu/start.c
@@ -58,7 +58,8 @@
int sandbox_early_getopt_check(void)
{
struct sandbox_state *state = state_get_current();
- struct sandbox_cmdline_option **sb_opt = __u_boot_sandbox_option_start;
+ struct sandbox_cmdline_option **sb_opt =
+ __u_boot_sandbox_option_start();
size_t num_options = __u_boot_sandbox_option_count();
size_t i;
int max_arg_len, max_noarg_len;
@@ -435,10 +436,13 @@
int main(int argc, char *argv[])
{
struct sandbox_state *state;
+ void * text_base;
gd_t data;
int size;
int ret;
+ text_base = os_find_text_base();
+
/*
* Copy argv[] so that we can pass the arguments in the original
* sequence when resetting the sandbox.
@@ -451,7 +455,7 @@
memset(&data, '\0', sizeof(data));
gd = &data;
- gd->arch.text_base = os_find_text_base();
+ gd->arch.text_base = text_base;
ret = state_init();
if (ret)
diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds
index 1816043..6754f4e 100644
--- a/arch/sandbox/cpu/u-boot-spl.lds
+++ b/arch/sandbox/cpu/u-boot-spl.lds
@@ -21,9 +21,11 @@
__priv_data_end = .;
}
- __u_boot_sandbox_option_start = .;
- _u_boot_sandbox_getopt : { KEEP(*(.u_boot_sandbox_getopt)) }
- __u_boot_sandbox_option_end = .;
+ _u_boot_sandbox_getopt : {
+ *(.u_boot_sandbox_getopt_start)
+ KEEP(*(.u_boot_sandbox_getopt))
+ *(.u_boot_sandbox_getopt_end)
+ }
}
INSERT AFTER .data;
diff --git a/arch/sandbox/cpu/u-boot.lds b/arch/sandbox/cpu/u-boot.lds
index a1f509c..6d71061 100644
--- a/arch/sandbox/cpu/u-boot.lds
+++ b/arch/sandbox/cpu/u-boot.lds
@@ -13,9 +13,11 @@
KEEP(*(SORT(.u_boot_list*)));
}
- __u_boot_sandbox_option_start = .;
- _u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) }
- __u_boot_sandbox_option_end = .;
+ _u_boot_sandbox_getopt : {
+ *(.u_boot_sandbox_getopt_start)
+ *(.u_boot_sandbox_getopt)
+ *(.u_boot_sandbox_getopt_end)
+ }
.__efi_runtime_start : {
*(.__efi_runtime_start)
diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile
index d231dc2..3e5dc67 100644
--- a/arch/sandbox/dts/Makefile
+++ b/arch/sandbox/dts/Makefile
@@ -6,6 +6,7 @@
dtb-$(CONFIG_SANDBOX) += sandbox.dtb
endif
dtb-$(CONFIG_UT_DM) += test.dtb
+dtb-$(CONFIG_CMD_EXTENSION) += overlay0.dtbo overlay1.dtbo
targets += $(dtb-y)
diff --git a/arch/sandbox/dts/overlay0.dts b/arch/sandbox/dts/overlay0.dts
new file mode 100644
index 0000000..70c6cf7
--- /dev/null
+++ b/arch/sandbox/dts/overlay0.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+&{/buttons} {
+ btn3 {
+ gpios = <&gpio_a 5 0>;
+ label = "button3";
+ };
+};
diff --git a/arch/sandbox/dts/overlay1.dts b/arch/sandbox/dts/overlay1.dts
new file mode 100644
index 0000000..51621b3
--- /dev/null
+++ b/arch/sandbox/dts/overlay1.dts
@@ -0,0 +1,9 @@
+/dts-v1/;
+/plugin/;
+
+&{/buttons} {
+ btn4 {
+ gpios = <&gpio_a 5 0>;
+ label = "button4";
+ };
+};
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 48240aa..5ca3bc5 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -45,7 +45,6 @@
fdt-dummy1 = "/translation-test@8000/dev@1,100";
fdt-dummy2 = "/translation-test@8000/dev@2,200";
fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
- fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
usb0 = &usb_0;
usb1 = &usb_1;
usb2 = &usb_2;
@@ -53,6 +52,13 @@
osd0 = "/osd";
};
+ config {
+ environment {
+ from_fdt = "yes";
+ fdt_env_path = "";
+ };
+ };
+
audio: audio-codec {
compatible = "sandbox,audio-codec";
#sound-dai-cells = <1>;
@@ -997,8 +1003,8 @@
reset-ctl-test {
compatible = "sandbox,reset-ctl-test";
- resets = <&resetc 100>, <&resetc 2>;
- reset-names = "other", "test";
+ resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
+ reset-names = "other", "test", "test2", "test3";
};
rng {
@@ -1263,7 +1269,6 @@
1 0x100 0x9000 0x1000
2 0x200 0xA000 0x1000
3 0x300 0xB000 0x1000
- 4 0x400 0xC000 0x1000
>;
dma-ranges = <0 0x000 0x10000000 0x1000
@@ -1300,25 +1305,6 @@
reg = <0x42>;
};
};
-
- xlatebus@4,400 {
- compatible = "sandbox,zero-size-cells-bus";
- reg = <4 0x400 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 4 0x400 0x1000>;
-
- devs {
- #address-cells = <1>;
- #size-cells = <0>;
-
- dev@19 {
- compatible = "denx,u-boot-fdt-dummy";
- reg = <0x19>;
- };
- };
- };
-
};
osd {
@@ -1526,6 +1512,13 @@
compatible = "sandbox,sysinfo-sandbox";
};
+ sysinfo-gpio {
+ compatible = "gpio-sysinfo";
+ gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
+ revisions = <19>, <5>;
+ names = "rev_a", "foo";
+ };
+
some_regmapped-bus {
#address-cells = <0x1>;
#size-cells = <0x1>;
diff --git a/arch/sandbox/include/asm/getopt.h b/arch/sandbox/include/asm/getopt.h
index 3048c2c..d2145ad 100644
--- a/arch/sandbox/include/asm/getopt.h
+++ b/arch/sandbox/include/asm/getopt.h
@@ -44,7 +44,7 @@
.callback = sandbox_cmdline_cb_##f, \
}; \
/* Ppointer to the struct in a special section for the linker script */ \
- static __attribute__((section(".u_boot_sandbox_getopt"), used)) \
+ static __used __section(".u_boot_sandbox_getopt") \
struct sandbox_cmdline_option \
*sandbox_cmdline_option_##f##_ptr = \
&sandbox_cmdline_option_##f
diff --git a/arch/sandbox/include/asm/sections.h b/arch/sandbox/include/asm/sections.h
index fbc1bd1..f4351ae 100644
--- a/arch/sandbox/include/asm/sections.h
+++ b/arch/sandbox/include/asm/sections.h
@@ -13,12 +13,27 @@
struct sandbox_cmdline_option;
-extern struct sandbox_cmdline_option *__u_boot_sandbox_option_start[],
- *__u_boot_sandbox_option_end[];
+static inline struct sandbox_cmdline_option **
+__u_boot_sandbox_option_start(void)
+{
+ static char start[0] __aligned(4) __attribute__((unused))
+ __section(".u_boot_sandbox_getopt_start");
+
+ return (struct sandbox_cmdline_option **)&start;
+}
+
+static inline struct sandbox_cmdline_option **
+__u_boot_sandbox_option_end(void)
+{
+ static char end[0] __aligned(4) __attribute__((unused))
+ __section(".u_boot_sandbox_getopt_end");
+
+ return (struct sandbox_cmdline_option **)&end;
+}
static inline size_t __u_boot_sandbox_option_count(void)
{
- return __u_boot_sandbox_option_end - __u_boot_sandbox_option_start;
+ return __u_boot_sandbox_option_end() - __u_boot_sandbox_option_start();
}
#endif
diff --git a/arch/sandbox/lib/sections.c b/arch/sandbox/lib/sections.c
index 697a816..2559eee 100644
--- a/arch/sandbox/lib/sections.c
+++ b/arch/sandbox/lib/sections.c
@@ -3,10 +3,11 @@
* Copyright 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*
*/
+#include <linux/compiler.h>
-char __efi_runtime_start[0] __attribute__((section(".__efi_runtime_start")));
-char __efi_runtime_stop[0] __attribute__((section(".__efi_runtime_stop")));
+char __efi_runtime_start[0] __section(".__efi_runtime_start");
+char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
char __efi_runtime_rel_start[0]
- __attribute__((section(".__efi_runtime_rel_start")));
+ __section(".__efi_runtime_rel_start");
char __efi_runtime_rel_stop[0]
- __attribute__((section(".__efi_runtime_rel_stop")));
+ __section(".__efi_runtime_rel_stop");
diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c
index 7f133ce..3ad611a 100644
--- a/arch/x86/cpu/coreboot/timestamp.c
+++ b/arch/x86/cpu/coreboot/timestamp.c
@@ -11,7 +11,7 @@
#include <asm/cb_sysinfo.h>
#include <linux/compiler.h>
-static struct timestamp_table *ts_table __attribute__((section(".data")));
+static struct timestamp_table *ts_table __section(".data");
void timestamp_init(void)
{
diff --git a/arch/x86/lib/coreboot/cb_sysinfo.c b/arch/x86/lib/coreboot/cb_sysinfo.c
index e2c65bf..748fa4e 100644
--- a/arch/x86/lib/coreboot/cb_sysinfo.c
+++ b/arch/x86/lib/coreboot/cb_sysinfo.c
@@ -21,7 +21,7 @@
* with zeroes when transitioning from "ROM", which is really RAM, to other
* RAM.
*/
-struct sysinfo_t lib_sysinfo __attribute__((section(".data")));
+struct sysinfo_t lib_sysinfo __section(".data");
/*
* Some of this is x86 specific, and the rest of it is generic. Right now,
diff --git a/arch/x86/lib/sections.c b/arch/x86/lib/sections.c
index 8d17007..375029e 100644
--- a/arch/x86/lib/sections.c
+++ b/arch/x86/lib/sections.c
@@ -2,10 +2,11 @@
/*
* Copyright 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
+#include <linux/compiler.h>
-char __efi_runtime_start[0] __attribute__((section(".__efi_runtime_start")));
-char __efi_runtime_stop[0] __attribute__((section(".__efi_runtime_stop")));
+char __efi_runtime_start[0] __section(".__efi_runtime_start");
+char __efi_runtime_stop[0] __section(".__efi_runtime_stop");
char __efi_runtime_rel_start[0]
- __attribute__((section(".__efi_runtime_rel_start")));
+ __section(".__efi_runtime_rel_start");
char __efi_runtime_rel_stop[0]
- __attribute__((section(".__efi_runtime_rel_stop")));
+ __section(".__efi_runtime_rel_stop");
diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c
index 85d3464..a09e103 100644
--- a/arch/xtensa/cpu/cpu.c
+++ b/arch/xtensa/cpu/cpu.c
@@ -20,7 +20,7 @@
DECLARE_GLOBAL_DATA_PTR;
-gd_t *gd __attribute__((section(".data")));
+gd_t *gd __section(".data");
#if defined(CONFIG_DISPLAY_CPUINFO)
/*
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index 321dd0c..e50f505 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -31,6 +31,7 @@
def_bool y
select RISCV_NDS
select SUPPORT_SPL
+ select BINMAN if SPL
imply SMP
imply SPL_RAM_SUPPORT
imply SPL_RAM_DEVICE
diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c
index ef692b0..544e09f 100644
--- a/board/BuR/brxre1/board.c
+++ b/board/BuR/brxre1/board.c
@@ -164,12 +164,21 @@
br_resetc_bmode();
/* setup othbootargs for bootvx-command (vxWorks bootline) */
+#ifdef CONFIG_LCD
snprintf(othbootargs, sizeof(othbootargs),
"u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
(u32)gd->fb_base - 0x20,
(u32)env_get_ulong("vx_memtop", 16, gd->fb_base - 0x20),
(u32)env_get_ulong("vx_romfsbase", 16, 0),
(u32)env_get_ulong("vx_romfssize", 16, 0));
+#else
+ snprintf(othbootargs, sizeof(othbootargs),
+ "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x",
+ (u32)gd->relocaddr,
+ (u32)env_get_ulong("vx_memtop", 16, gd->relocaddr),
+ (u32)env_get_ulong("vx_romfsbase", 16, 0),
+ (u32)env_get_ulong("vx_romfssize", 16, 0));
+#endif
env_set("othbootargs", othbootargs);
/*
* reset VBAR registers to its reset location, VxWorks 6.9.3.2 does
diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c
index 486680a..15cbf92 100644
--- a/board/CZ.NIC/turris_mox/turris_mox.c
+++ b/board/CZ.NIC/turris_mox/turris_mox.c
@@ -216,13 +216,13 @@
if (sfpindex >= 0 && swindex >= 0) {
if (sfpindex < swindex)
- serdes_map[0].speed = PHY_SPEED_1_25G;
+ serdes_map[0].speed = COMPHY_SPEED_1_25G;
else
- serdes_map[0].speed = PHY_SPEED_3_125G;
+ serdes_map[0].speed = COMPHY_SPEED_3_125G;
} else if (sfpindex >= 0) {
- serdes_map[0].speed = PHY_SPEED_1_25G;
+ serdes_map[0].speed = COMPHY_SPEED_1_25G;
} else if (swindex >= 0) {
- serdes_map[0].speed = PHY_SPEED_3_125G;
+ serdes_map[0].speed = COMPHY_SPEED_3_125G;
}
return 0;
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 1d3cefe..ade923f 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -337,24 +337,6 @@
return env_set("regdomain", rd);
}
-/*
- * default factory reset bootcommand on Omnia first sets all the front LEDs
- * to green and then tries to load the rescue image from SPI flash memory and
- * boot it
- */
-#define OMNIA_FACTORY_RESET_BOOTCMD \
- "i2c dev 2; " \
- "i2c mw 0x2a.1 0x3 0x1c 1; " \
- "i2c mw 0x2a.1 0x4 0x1c 1; " \
- "mw.l 0x01000000 0x00ff000c; " \
- "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
- "setenv bootargs \"earlyprintk console=ttyS0,115200" \
- " omniarescue=$omnia_reset\"; " \
- "sf probe; " \
- "sf read 0x1000000 0x100000 0x700000; " \
- "bootm 0x1000000; " \
- "bootz 0x1000000"
-
static void handle_reset_button(void)
{
int ret;
@@ -370,8 +352,36 @@
env_set_ulong("omnia_reset", reset_status);
if (reset_status) {
+ const char * const vars[3] = {
+ "bootcmd",
+ "bootcmd_rescue",
+ "distro_bootcmd",
+ };
+
+ /*
+ * Set the above envs to their default values, in case the user
+ * managed to break them.
+ */
+ env_set_default_vars(3, (char * const *)vars, 0);
+
+ /* Ensure bootcmd_rescue is used by distroboot */
+ env_set("boot_targets", "rescue");
+
printf("RESET button was pressed, overwriting bootcmd!\n");
- env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
+ } else {
+ /*
+ * In case the user somehow managed to save environment with
+ * boot_targets=rescue, reset boot_targets to default value.
+ * This could happen in subsequent commands if bootcmd_rescue
+ * failed.
+ */
+ if (!strcmp(env_get("boot_targets"), "rescue")) {
+ const char * const vars[1] = {
+ "boot_targets",
+ };
+
+ env_set_default_vars(1, (char * const *)vars, 0);
+ }
}
}
#endif
diff --git a/board/Marvell/octeontx2_cn913x/MAINTAINERS b/board/Marvell/octeontx2_cn913x/MAINTAINERS
new file mode 100644
index 0000000..74c5fd1
--- /dev/null
+++ b/board/Marvell/octeontx2_cn913x/MAINTAINERS
@@ -0,0 +1,6 @@
+OCTEONTX2_CN913x BOARD
+M: Kostya Porotchkin <kostap@marvell.com>
+S: Maintained
+F: board/Marvell/octeontx2_cn913x/
+F: configs/mvebu_crb_cn9130_defconfig
+F: configs/mvebu_db_cn9130_defconfig
diff --git a/board/Marvell/octeontx2_cn913x/Makefile b/board/Marvell/octeontx2_cn913x/Makefile
new file mode 100644
index 0000000..8c6ffb9
--- /dev/null
+++ b/board/Marvell/octeontx2_cn913x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2016 Stefan Roese <sr@denx.de>
+# Copyright (C) 2019 Marvell International Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := board.o
diff --git a/board/Marvell/octeontx2_cn913x/README b/board/Marvell/octeontx2_cn913x/README
new file mode 100644
index 0000000..3d0c8b3
--- /dev/null
+++ b/board/Marvell/octeontx2_cn913x/README
@@ -0,0 +1,24 @@
+Not all board variants are represented with a specific defconfig in
+mainline U-Boot. Here a small documentation on how to generate U-Boot
+images for all other board variants, available via different dts
+files and defconfigs.
+
+Use a different dts than in the defconfig:
+
+make DEVICE_TREE=cn9131-db-B
+
+Use a different boot device (e.g. MMC or NAND instead of SPI NOR):
+
+For MMC, please make the following changes to the defconfig via
+e.g. "make menuconfig":
+Remove CONFIG_MVEBU_SPI_BOOT
+Select CONFIG_MVEBU_MMC_BOOT
+Remove CONFIG_ENV_IS_IN_SPI_FLASH
+Select CONFIG_ENV_IS_IN_MMC
+
+For NAND, please make the following changes to the defconfig via
+e.g. "make menuconfig":
+Remove CONFIG_MVEBU_SPI_BOOT
+Select CONFIG_MVEBU_NAND_BOOT
+Remove CONFIG_ENV_IS_IN_SPI_FLASH
+Select CONFIG_ENV_IS_IN_NAND
diff --git a/board/Marvell/octeontx2_cn913x/board.c b/board/Marvell/octeontx2_cn913x/board.c
new file mode 100644
index 0000000..953e9db
--- /dev/null
+++ b/board/Marvell/octeontx2_cn913x/board.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ * Copyright (C) 2020 Marvell International Ltd.
+ */
+
+#include <dm.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+__weak int soc_early_init_f(void)
+{
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ soc_early_init_f();
+
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ if (CONFIG_IS_ENABLED(DM_REGULATOR)) {
+ /* Check if any existing regulator should be turned down */
+ regulators_enable_boot_off(false);
+ }
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
diff --git a/board/beacon/beacon-rzg2m/Makefile b/board/beacon/beacon-rzg2m/Makefile
index 439f319..9131a92 100644
--- a/board/beacon/beacon-rzg2m/Makefile
+++ b/board/beacon/beacon-rzg2m/Makefile
@@ -6,4 +6,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := beacon-rzg2m.o
+obj-y := beacon-rzg2m.o ../../renesas/rcar-common/common.o
diff --git a/board/beacon/beacon-rzg2m/beacon-rzg2m.c b/board/beacon/beacon-rzg2m/beacon-rzg2m.c
index 0c7f8e5..c12ff77 100644
--- a/board/beacon/beacon-rzg2m/beacon-rzg2m.c
+++ b/board/beacon/beacon-rzg2m/beacon-rzg2m.c
@@ -28,21 +28,6 @@
return 0;
}
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- return -EINVAL;
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
#define RST_BASE 0xE6160000
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CODE 0xA5A5000F
diff --git a/board/bosch/shc/board.c b/board/bosch/shc/board.c
index e893781..86356e3 100644
--- a/board/bosch/shc/board.c
+++ b/board/bosch/shc/board.c
@@ -45,7 +45,7 @@
DECLARE_GLOBAL_DATA_PTR;
-static struct shc_eeprom __attribute__((section(".data"))) header;
+static struct shc_eeprom __section(".data") header;
static int shc_eeprom_valid;
/*
diff --git a/board/broadcom/bcmstb/bcmstb.c b/board/broadcom/bcmstb/bcmstb.c
index ee0a341..076ac94 100644
--- a/board/broadcom/bcmstb/bcmstb.c
+++ b/board/broadcom/bcmstb/bcmstb.c
@@ -22,7 +22,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#define BCMSTB_DATA_SECTION __attribute__((section(".data")))
+#define BCMSTB_DATA_SECTION __section(".data")
struct bcmstb_boot_parameters bcmstb_boot_parameters BCMSTB_DATA_SECTION;
diff --git a/board/compulab/imx8mm-cl-iot-gate/Kconfig b/board/compulab/imx8mm-cl-iot-gate/Kconfig
new file mode 100644
index 0000000..7f5c794
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MM_CL_IOT_GATE
+
+config SYS_BOARD
+ default "imx8mm-cl-iot-gate"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_CONFIG_NAME
+ default "imx8mm-cl-iot-gate"
+
+endif
diff --git a/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS b/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS
new file mode 100644
index 0000000..9c6b170
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/MAINTAINERS
@@ -0,0 +1,6 @@
+Compulab IOT-GATE-iMX8 BOARD
+M: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+S: Maintained
+F: board/compulab/imx8mm-cl-iot-gate/
+F: include/configs/imx8mm-cl-iot-gate.h
+F: configs/imx8mm-cl-iot-gate_defconfig
diff --git a/board/compulab/imx8mm-cl-iot-gate/Makefile b/board/compulab/imx8mm-cl-iot-gate/Makefile
new file mode 100644
index 0000000..3a2bfc4
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright 2018 NXP
+# Copyright 2020 Linaro
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mm-cl-iot-gate.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += ddr/
+endif
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile b/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile
new file mode 100644
index 0000000..5914796
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/Makefile
@@ -0,0 +1,8 @@
+obj-y += ddr.o
+obj-y += lpddr4_timing_ff020008.o
+obj-y += lpddr4_timing_ff000110.o
+ifdef CONFIG_TARGET_MCM_IMX8M_MINI
+obj-y += lpddr4_timing_01061010.o
+else
+obj-y += lpddr4_timing_01061010.1_2.o
+endif
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
new file mode 100644
index 0000000..42dd0db
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.c
@@ -0,0 +1,211 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2017 NXP
+ * Copyright 2020 Linaro
+ *
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <errno.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/arch/lpddr4_define.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include "ddr.h"
+
+static unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
+{
+ unsigned int tmp;
+
+ reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x1);
+ do {
+ tmp = reg32_read(DDRC_MRSTAT(0));
+ } while (tmp & 0x1);
+
+ reg32_write(DDRC_MRCTRL0(0), (mr_rank << 4) | 0x1);
+ reg32_write(DDRC_MRCTRL1(0), (mr_addr << 8));
+ reg32setbit(DDRC_MRCTRL0(0), 31);
+ do {
+ tmp = reg32_read(DRC_PERF_MON_MRR0_DAT(0));
+ } while ((tmp & 0x8) == 0);
+ tmp = reg32_read(DRC_PERF_MON_MRR1_DAT(0));
+ reg32_write(DRC_PERF_MON_MRR0_DAT(0), 0x4);
+ while (tmp) { //try to find a significant byte in the word
+ if (tmp & 0xff) {
+ tmp &= 0xff;
+ break;
+ }
+ tmp >>= 8;
+ }
+ return tmp;
+}
+
+struct lpddr4_desc {
+ char name[16];
+ unsigned int id;
+ unsigned int size;
+ unsigned int count;
+ /* an optional field
+ * use it if default is not the
+ * 1-st array entry
+ */
+ unsigned int _default;
+ /* An optional field to distiguish DRAM chips that
+ * have different geometry, though return the same MRR.
+ * Default value 0xff
+ */
+ u8 subind;
+ struct dram_timing_info *timing;
+ char *desc[4];
+};
+
+#define DEFAULT (('D' << 24) + ('E' << 16) + ('F' << 8) + 'A')
+static const struct lpddr4_desc lpddr4_array[] = {
+ { .name = "Nanya", .id = 0x05000010, .subind = 0xff,
+ .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
+ { .name = "Samsung", .id = 0x01061010, .subind = 0xff,
+ .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
+ { .name = "Kingston", .id = 0xff000010, .subind = 0x04,
+ .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+ { .name = "Kingston", .id = 0xff000010, .subind = 0x02,
+ .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
+ { .name = "Micron", .id = 0xff020008, .subind = 0xff,
+ .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008},
+ { .name = "Micron", .id = 0xff000110, .subind = 0xff,
+ .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+};
+
+static unsigned int lpddr4_get_mr(void)
+{
+ int i = 0, attempts = 5;
+ unsigned int ddr_info = 0;
+ unsigned int regs[] = { 5, 6, 7, 8 };
+
+ do {
+ for (i = 0 ; i < ARRAY_SIZE(regs) ; i++) {
+ unsigned int data = 0;
+
+ data = lpddr4_mr_read(0xF, regs[i]);
+ ddr_info <<= 8;
+ ddr_info += (data & 0xFF);
+ }
+ if (ddr_info != 0xFFFFFFFF && ddr_info != 0)
+ break; // The attempt was successful
+ } while (--attempts);
+ return ddr_info;
+}
+
+static void spl_tcm_init(struct lpddr4_tcm_desc *lpddr4_tcm_desc)
+{
+ if (lpddr4_tcm_desc->sign == DEFAULT)
+ return;
+
+ lpddr4_tcm_desc->sign = DEFAULT;
+ lpddr4_tcm_desc->index = 0;
+}
+
+static void spl_tcm_fini(struct lpddr4_tcm_desc *lpddr4_tcm_desc)
+{
+ if (lpddr4_tcm_desc->sign != DEFAULT)
+ return;
+
+ lpddr4_tcm_desc->sign = ~DEFAULT;
+ lpddr4_tcm_desc->index = 0;
+}
+
+#define SPL_TCM_DATA 0x7e0000
+#define SPL_TCM_INIT spl_tcm_init(lpddr4_tcm_desc)
+#define SPL_TCM_FINI spl_tcm_fini(lpddr4_tcm_desc)
+
+void spl_dram_init_compulab(void)
+{
+ unsigned int ddr_info = 0xdeadbeef;
+ unsigned int ddr_info_mrr = 0xdeadbeef;
+ unsigned int ddr_found = 0;
+ int i = 0;
+
+ struct lpddr4_tcm_desc *lpddr4_tcm_desc =
+ (struct lpddr4_tcm_desc *)SPL_TCM_DATA;
+
+ if (lpddr4_tcm_desc->sign != DEFAULT) {
+ /* if not in tcm scan mode */
+ for (i = 0; i < ARRAY_SIZE(lpddr4_array); i++) {
+ if (lpddr4_array[i].id == ddr_info &&
+ lpddr4_array[i].subind == 0xff) {
+ ddr_found = 1;
+ break;
+ }
+ }
+ }
+
+ /* Walk trought all available ddr ids and apply
+ * one by one. Save the index at the tcm memory that
+ * persists after the reset.
+ */
+ if (ddr_found == 0) {
+ SPL_TCM_INIT;
+
+ if (lpddr4_tcm_desc->index < ARRAY_SIZE(lpddr4_array)) {
+ printf("DDRINFO: Cfg attempt: [ %d/%lu ]\n",
+ lpddr4_tcm_desc->index + 1,
+ ARRAY_SIZE(lpddr4_array));
+ i = lpddr4_tcm_desc->index;
+ lpddr4_tcm_desc->index += 1;
+ } else {
+ /* Ran out all available ddr setings */
+ printf("DDRINFO: Ran out all [ %lu ] cfg attempts. A non supported configuration.\n",
+ ARRAY_SIZE(lpddr4_array));
+ while (1)
+ ;
+ }
+ ddr_info = lpddr4_array[i].id;
+ } else {
+ printf("DDRINFO(%s): %s %dG\n", (ddr_found ? "D" : "?"),
+ lpddr4_array[i].name,
+ lpddr4_array[i].size);
+ }
+
+ if (ddr_init(lpddr4_array[i].timing)) {
+ SPL_TCM_INIT;
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ ddr_info_mrr = lpddr4_get_mr();
+ if (ddr_info_mrr == 0xFFFFFFFF) {
+ printf("DDRINFO(M): mr5-8 [ 0x%x ] is invalid; reset\n",
+ ddr_info_mrr);
+ SPL_TCM_INIT;
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ printf("DDRINFO(M): mr5-8 [ 0x%x ]\n", ddr_info_mrr);
+ printf("DDRINFO(%s): mr5-8 [ 0x%x ]\n", (ddr_found ? "E" : "T"),
+ ddr_info);
+
+ if (ddr_info_mrr != ddr_info) {
+ SPL_TCM_INIT;
+ do_reset(NULL, 0, 0, NULL);
+ }
+
+ SPL_TCM_FINI;
+
+ /* Pass the dram size to th U-Boot through the tcm memory */
+ { /* To figure out what to store into the TCM buffer */
+ /* For debug purpouse only. To override the real memsize */
+ unsigned int ddr_tcm_size = 0;
+
+ if (ddr_tcm_size == 0 || ddr_tcm_size == -1)
+ ddr_tcm_size = lpddr4_array[i].size;
+
+ lpddr4_tcm_desc->size = ddr_tcm_size;
+ }
+}
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
new file mode 100644
index 0000000..59c1891
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/ddr.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ * Copyright 2020 Linaro
+ *
+ */
+
+#ifndef __COMPULAB_DDR_H__
+#define __COMPULAB_DDR_H__
+
+extern struct dram_timing_info ucm_dram_timing_ff020008;
+extern struct dram_timing_info ucm_dram_timing_ff000110;
+extern struct dram_timing_info ucm_dram_timing_01061010;
+
+void spl_dram_init_compulab(void);
+
+#define TCM_DATA_CFG 0x7e0000
+
+struct lpddr4_tcm_desc {
+ unsigned int size;
+ unsigned int sign;
+ unsigned int index;
+ unsigned int count;
+};
+
+#endif
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c
new file mode 100644
index 0000000..870a94a
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.1_2.c
@@ -0,0 +1,1848 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ {0x3d400304, 0x1},
+ {0x3d400030, 0x1},
+ {0x3d400000, 0xa1080020},
+ {0x3d400020, 0x223},
+ {0x3d400024, 0x2ee00},
+ {0x3d400064, 0x4900a8},
+ {0x3d4000d0, 0xc0030495},
+ {0x3d4000d4, 0x770000},
+ {0x3d4000dc, 0xc40024},
+ {0x3d4000e0, 0x310000},
+ {0x3d4000e8, 0x66004d},
+ {0x3d4000ec, 0x16004d},
+ {0x3d400100, 0x1618141a},
+ {0x3d400104, 0x504a6},
+ {0x3d40010c, 0x909000},
+ {0x3d400110, 0xb04060b},
+ {0x3d400114, 0x2030909},
+ {0x3d400118, 0x1010006},
+ {0x3d40011c, 0x301},
+ {0x3d400130, 0x20500},
+ {0x3d400134, 0xb100002},
+ {0x3d400138, 0xad},
+ {0x3d400144, 0x78003c},
+ {0x3d400180, 0x2580012},
+ {0x3d400184, 0x1e0493e},
+ {0x3d400188, 0x0},
+ {0x3d400190, 0x4938208},
+ {0x3d400194, 0x80303},
+ {0x3d4001b4, 0x1308},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0xdf00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x11},
+ {0x3d4001c0, 0x1},
+ {0x3d4001c4, 0x0},
+ {0x3d4000f4, 0xc99},
+ {0x3d400108, 0x60c1514},
+ {0x3d400200, 0x1f},
+ {0x3d40020c, 0x0},
+ {0x3d400210, 0x1f1f},
+ {0x3d400204, 0x80808},
+ {0x3d400214, 0x7070707},
+ {0x3d400218, 0x7070707},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x2c},
+ {0x3d40025c, 0x4000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x2005574},
+ {0x3d400400, 0x111},
+ {0x3d400408, 0x72ff},
+ {0x3d400494, 0x2100e07},
+ {0x3d400498, 0x620096},
+ {0x3d40049c, 0x1100e07},
+ {0x3d4004a0, 0xc8012c},
+ {0x3d402020, 0x21},
+ {0x3d402024, 0x7d00},
+ {0x3d402050, 0x20d040},
+ {0x3d402064, 0xc001c},
+ {0x3d4020dc, 0x840000},
+ {0x3d4020e0, 0x310000},
+ {0x3d4020e8, 0x66004d},
+ {0x3d4020ec, 0x16004d},
+ {0x3d402100, 0xa040305},
+ {0x3d402104, 0x30407},
+ {0x3d402108, 0x203060b},
+ {0x3d40210c, 0x505000},
+ {0x3d402110, 0x2040202},
+ {0x3d402114, 0x2030202},
+ {0x3d402118, 0x1010004},
+ {0x3d40211c, 0x301},
+ {0x3d402130, 0x20300},
+ {0x3d402134, 0xa100002},
+ {0x3d402138, 0x1d},
+ {0x3d402144, 0x14000a},
+ {0x3d402180, 0x640004},
+ {0x3d402190, 0x3818200},
+ {0x3d402194, 0x80303},
+ {0x3d4021b4, 0x100},
+ {0x3d403020, 0x21},
+ {0x3d403024, 0x1f40},
+ {0x3d403050, 0x20d040},
+ {0x3d403064, 0x30007},
+ {0x3d4030dc, 0x840000},
+ {0x3d4030e0, 0x310000},
+ {0x3d4030e8, 0x66004d},
+ {0x3d4030ec, 0x16004d},
+ {0x3d403100, 0xa010102},
+ {0x3d403104, 0x30404},
+ {0x3d403108, 0x203060b},
+ {0x3d40310c, 0x505000},
+ {0x3d403110, 0x2040202},
+ {0x3d403114, 0x2030202},
+ {0x3d403118, 0x1010004},
+ {0x3d40311c, 0x301},
+ {0x3d403130, 0x20300},
+ {0x3d403134, 0xa100002},
+ {0x3d403138, 0x8},
+ {0x3d403144, 0x50003},
+ {0x3d403180, 0x190004},
+ {0x3d403190, 0x3818200},
+ {0x3d403194, 0x80303},
+ {0x3d4031b4, 0x100},
+ {0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x0},
+ {0x100a1, 0x1},
+ {0x100a2, 0x2},
+ {0x100a3, 0x3},
+ {0x100a4, 0x4},
+ {0x100a5, 0x5},
+ {0x100a6, 0x6},
+ {0x100a7, 0x7},
+ {0x110a0, 0x0},
+ {0x110a1, 0x1},
+ {0x110a2, 0x3},
+ {0x110a3, 0x4},
+ {0x110a4, 0x5},
+ {0x110a5, 0x2},
+ {0x110a6, 0x7},
+ {0x110a7, 0x6},
+ {0x120a0, 0x0},
+ {0x120a1, 0x1},
+ {0x120a2, 0x3},
+ {0x120a3, 0x2},
+ {0x120a4, 0x5},
+ {0x120a5, 0x4},
+ {0x120a6, 0x7},
+ {0x120a7, 0x6},
+ {0x130a0, 0x0},
+ {0x130a1, 0x1},
+ {0x130a2, 0x2},
+ {0x130a3, 0x3},
+ {0x130a4, 0x4},
+ {0x130a5, 0x5},
+ {0x130a6, 0x6},
+ {0x130a7, 0x7},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x1205f, 0x1ff},
+ {0x1215f, 0x1ff},
+ {0x1305f, 0x1ff},
+ {0x1315f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x11205f, 0x1ff},
+ {0x11215f, 0x1ff},
+ {0x11305f, 0x1ff},
+ {0x11315f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x21205f, 0x1ff},
+ {0x21215f, 0x1ff},
+ {0x21305f, 0x1ff},
+ {0x21315f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x3055, 0x1ff},
+ {0x4055, 0x1ff},
+ {0x5055, 0x1ff},
+ {0x6055, 0x1ff},
+ {0x7055, 0x1ff},
+ {0x8055, 0x1ff},
+ {0x9055, 0x1ff},
+ {0x200c5, 0xa},
+ {0x1200c5, 0x7},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x120024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x220024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x20056, 0x2},
+ {0x120056, 0xa},
+ {0x220056, 0xa},
+ {0x1004d, 0xe00},
+ {0x1014d, 0xe00},
+ {0x1104d, 0xe00},
+ {0x1114d, 0xe00},
+ {0x1204d, 0xe00},
+ {0x1214d, 0xe00},
+ {0x1304d, 0xe00},
+ {0x1314d, 0xe00},
+ {0x11004d, 0xe00},
+ {0x11014d, 0xe00},
+ {0x11104d, 0xe00},
+ {0x11114d, 0xe00},
+ {0x11204d, 0xe00},
+ {0x11214d, 0xe00},
+ {0x11304d, 0xe00},
+ {0x11314d, 0xe00},
+ {0x21004d, 0xe00},
+ {0x21014d, 0xe00},
+ {0x21104d, 0xe00},
+ {0x21114d, 0xe00},
+ {0x21204d, 0xe00},
+ {0x21214d, 0xe00},
+ {0x21304d, 0xe00},
+ {0x21314d, 0xe00},
+ {0x10049, 0xeba},
+ {0x10149, 0xeba},
+ {0x11049, 0xeba},
+ {0x11149, 0xeba},
+ {0x12049, 0xeba},
+ {0x12149, 0xeba},
+ {0x13049, 0xeba},
+ {0x13149, 0xeba},
+ {0x110049, 0xeba},
+ {0x110149, 0xeba},
+ {0x111049, 0xeba},
+ {0x111149, 0xeba},
+ {0x112049, 0xeba},
+ {0x112149, 0xeba},
+ {0x113049, 0xeba},
+ {0x113149, 0xeba},
+ {0x210049, 0xeba},
+ {0x210149, 0xeba},
+ {0x211049, 0xeba},
+ {0x211149, 0xeba},
+ {0x212049, 0xeba},
+ {0x212149, 0xeba},
+ {0x213049, 0xeba},
+ {0x213149, 0xeba},
+ {0x43, 0x63},
+ {0x1043, 0x63},
+ {0x2043, 0x63},
+ {0x3043, 0x63},
+ {0x4043, 0x63},
+ {0x5043, 0x63},
+ {0x6043, 0x63},
+ {0x7043, 0x63},
+ {0x8043, 0x63},
+ {0x9043, 0x63},
+ {0x20018, 0x3},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x20008, 0x258},
+ {0x120008, 0x64},
+ {0x220008, 0x19},
+ {0x20088, 0x9},
+ {0x200b2, 0xdc},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x12043, 0x5a1},
+ {0x12143, 0x5a1},
+ {0x13043, 0x5a1},
+ {0x13143, 0x5a1},
+ {0x1200b2, 0xdc},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x112043, 0x5a1},
+ {0x112143, 0x5a1},
+ {0x113043, 0x5a1},
+ {0x113143, 0x5a1},
+ {0x2200b2, 0xdc},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x212043, 0x5a1},
+ {0x212143, 0x5a1},
+ {0x213043, 0x5a1},
+ {0x213143, 0x5a1},
+ {0x200fa, 0x1},
+ {0x1200fa, 0x1},
+ {0x2200fa, 0x1},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x660},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5665},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+ {0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0},
+ { 0x1200b2, 0x0},
+ { 0x2200b2, 0x0},
+ { 0x200cb, 0x0},
+ { 0x10043, 0x0},
+ { 0x110043, 0x0},
+ { 0x210043, 0x0},
+ { 0x10143, 0x0},
+ { 0x110143, 0x0},
+ { 0x210143, 0x0},
+ { 0x11043, 0x0},
+ { 0x111043, 0x0},
+ { 0x211043, 0x0},
+ { 0x11143, 0x0},
+ { 0x111143, 0x0},
+ { 0x211143, 0x0},
+ { 0x12043, 0x0},
+ { 0x112043, 0x0},
+ { 0x212043, 0x0},
+ { 0x12143, 0x0},
+ { 0x112143, 0x0},
+ { 0x212143, 0x0},
+ { 0x13043, 0x0},
+ { 0x113043, 0x0},
+ { 0x213043, 0x0},
+ { 0x13143, 0x0},
+ { 0x113143, 0x0},
+ { 0x213143, 0x0},
+ { 0x80, 0x0},
+ { 0x100080, 0x0},
+ { 0x200080, 0x0},
+ { 0x1080, 0x0},
+ { 0x101080, 0x0},
+ { 0x201080, 0x0},
+ { 0x2080, 0x0},
+ { 0x102080, 0x0},
+ { 0x202080, 0x0},
+ { 0x3080, 0x0},
+ { 0x103080, 0x0},
+ { 0x203080, 0x0},
+ { 0x4080, 0x0},
+ { 0x104080, 0x0},
+ { 0x204080, 0x0},
+ { 0x5080, 0x0},
+ { 0x105080, 0x0},
+ { 0x205080, 0x0},
+ { 0x6080, 0x0},
+ { 0x106080, 0x0},
+ { 0x206080, 0x0},
+ { 0x7080, 0x0},
+ { 0x107080, 0x0},
+ { 0x207080, 0x0},
+ { 0x8080, 0x0},
+ { 0x108080, 0x0},
+ { 0x208080, 0x0},
+ { 0x9080, 0x0},
+ { 0x109080, 0x0},
+ { 0x209080, 0x0},
+ { 0x10080, 0x0},
+ { 0x110080, 0x0},
+ { 0x210080, 0x0},
+ { 0x10180, 0x0},
+ { 0x110180, 0x0},
+ { 0x210180, 0x0},
+ { 0x11080, 0x0},
+ { 0x111080, 0x0},
+ { 0x211080, 0x0},
+ { 0x11180, 0x0},
+ { 0x111180, 0x0},
+ { 0x211180, 0x0},
+ { 0x12080, 0x0},
+ { 0x112080, 0x0},
+ { 0x212080, 0x0},
+ { 0x12180, 0x0},
+ { 0x112180, 0x0},
+ { 0x212180, 0x0},
+ { 0x13080, 0x0},
+ { 0x113080, 0x0},
+ { 0x213080, 0x0},
+ { 0x13180, 0x0},
+ { 0x113180, 0x0},
+ { 0x213180, 0x0},
+ { 0x10081, 0x0},
+ { 0x110081, 0x0},
+ { 0x210081, 0x0},
+ { 0x10181, 0x0},
+ { 0x110181, 0x0},
+ { 0x210181, 0x0},
+ { 0x11081, 0x0},
+ { 0x111081, 0x0},
+ { 0x211081, 0x0},
+ { 0x11181, 0x0},
+ { 0x111181, 0x0},
+ { 0x211181, 0x0},
+ { 0x12081, 0x0},
+ { 0x112081, 0x0},
+ { 0x212081, 0x0},
+ { 0x12181, 0x0},
+ { 0x112181, 0x0},
+ { 0x212181, 0x0},
+ { 0x13081, 0x0},
+ { 0x113081, 0x0},
+ { 0x213081, 0x0},
+ { 0x13181, 0x0},
+ { 0x113181, 0x0},
+ { 0x213181, 0x0},
+ { 0x100d0, 0x0},
+ { 0x1100d0, 0x0},
+ { 0x2100d0, 0x0},
+ { 0x101d0, 0x0},
+ { 0x1101d0, 0x0},
+ { 0x2101d0, 0x0},
+ { 0x110d0, 0x0},
+ { 0x1110d0, 0x0},
+ { 0x2110d0, 0x0},
+ { 0x111d0, 0x0},
+ { 0x1111d0, 0x0},
+ { 0x2111d0, 0x0},
+ { 0x120d0, 0x0},
+ { 0x1120d0, 0x0},
+ { 0x2120d0, 0x0},
+ { 0x121d0, 0x0},
+ { 0x1121d0, 0x0},
+ { 0x2121d0, 0x0},
+ { 0x130d0, 0x0},
+ { 0x1130d0, 0x0},
+ { 0x2130d0, 0x0},
+ { 0x131d0, 0x0},
+ { 0x1131d0, 0x0},
+ { 0x2131d0, 0x0},
+ { 0x100d1, 0x0},
+ { 0x1100d1, 0x0},
+ { 0x2100d1, 0x0},
+ { 0x101d1, 0x0},
+ { 0x1101d1, 0x0},
+ { 0x2101d1, 0x0},
+ { 0x110d1, 0x0},
+ { 0x1110d1, 0x0},
+ { 0x2110d1, 0x0},
+ { 0x111d1, 0x0},
+ { 0x1111d1, 0x0},
+ { 0x2111d1, 0x0},
+ { 0x120d1, 0x0},
+ { 0x1120d1, 0x0},
+ { 0x2120d1, 0x0},
+ { 0x121d1, 0x0},
+ { 0x1121d1, 0x0},
+ { 0x2121d1, 0x0},
+ { 0x130d1, 0x0},
+ { 0x1130d1, 0x0},
+ { 0x2130d1, 0x0},
+ { 0x131d1, 0x0},
+ { 0x1131d1, 0x0},
+ { 0x2131d1, 0x0},
+ { 0x10068, 0x0},
+ { 0x10168, 0x0},
+ { 0x10268, 0x0},
+ { 0x10368, 0x0},
+ { 0x10468, 0x0},
+ { 0x10568, 0x0},
+ { 0x10668, 0x0},
+ { 0x10768, 0x0},
+ { 0x10868, 0x0},
+ { 0x11068, 0x0},
+ { 0x11168, 0x0},
+ { 0x11268, 0x0},
+ { 0x11368, 0x0},
+ { 0x11468, 0x0},
+ { 0x11568, 0x0},
+ { 0x11668, 0x0},
+ { 0x11768, 0x0},
+ { 0x11868, 0x0},
+ { 0x12068, 0x0},
+ { 0x12168, 0x0},
+ { 0x12268, 0x0},
+ { 0x12368, 0x0},
+ { 0x12468, 0x0},
+ { 0x12568, 0x0},
+ { 0x12668, 0x0},
+ { 0x12768, 0x0},
+ { 0x12868, 0x0},
+ { 0x13068, 0x0},
+ { 0x13168, 0x0},
+ { 0x13268, 0x0},
+ { 0x13368, 0x0},
+ { 0x13468, 0x0},
+ { 0x13568, 0x0},
+ { 0x13668, 0x0},
+ { 0x13768, 0x0},
+ { 0x13868, 0x0},
+ { 0x10069, 0x0},
+ { 0x10169, 0x0},
+ { 0x10269, 0x0},
+ { 0x10369, 0x0},
+ { 0x10469, 0x0},
+ { 0x10569, 0x0},
+ { 0x10669, 0x0},
+ { 0x10769, 0x0},
+ { 0x10869, 0x0},
+ { 0x11069, 0x0},
+ { 0x11169, 0x0},
+ { 0x11269, 0x0},
+ { 0x11369, 0x0},
+ { 0x11469, 0x0},
+ { 0x11569, 0x0},
+ { 0x11669, 0x0},
+ { 0x11769, 0x0},
+ { 0x11869, 0x0},
+ { 0x12069, 0x0},
+ { 0x12169, 0x0},
+ { 0x12269, 0x0},
+ { 0x12369, 0x0},
+ { 0x12469, 0x0},
+ { 0x12569, 0x0},
+ { 0x12669, 0x0},
+ { 0x12769, 0x0},
+ { 0x12869, 0x0},
+ { 0x13069, 0x0},
+ { 0x13169, 0x0},
+ { 0x13269, 0x0},
+ { 0x13369, 0x0},
+ { 0x13469, 0x0},
+ { 0x13569, 0x0},
+ { 0x13669, 0x0},
+ { 0x13769, 0x0},
+ { 0x13869, 0x0},
+ { 0x1008c, 0x0},
+ { 0x11008c, 0x0},
+ { 0x21008c, 0x0},
+ { 0x1018c, 0x0},
+ { 0x11018c, 0x0},
+ { 0x21018c, 0x0},
+ { 0x1108c, 0x0},
+ { 0x11108c, 0x0},
+ { 0x21108c, 0x0},
+ { 0x1118c, 0x0},
+ { 0x11118c, 0x0},
+ { 0x21118c, 0x0},
+ { 0x1208c, 0x0},
+ { 0x11208c, 0x0},
+ { 0x21208c, 0x0},
+ { 0x1218c, 0x0},
+ { 0x11218c, 0x0},
+ { 0x21218c, 0x0},
+ { 0x1308c, 0x0},
+ { 0x11308c, 0x0},
+ { 0x21308c, 0x0},
+ { 0x1318c, 0x0},
+ { 0x11318c, 0x0},
+ { 0x21318c, 0x0},
+ { 0x1008d, 0x0},
+ { 0x11008d, 0x0},
+ { 0x21008d, 0x0},
+ { 0x1018d, 0x0},
+ { 0x11018d, 0x0},
+ { 0x21018d, 0x0},
+ { 0x1108d, 0x0},
+ { 0x11108d, 0x0},
+ { 0x21108d, 0x0},
+ { 0x1118d, 0x0},
+ { 0x11118d, 0x0},
+ { 0x21118d, 0x0},
+ { 0x1208d, 0x0},
+ { 0x11208d, 0x0},
+ { 0x21208d, 0x0},
+ { 0x1218d, 0x0},
+ { 0x11218d, 0x0},
+ { 0x21218d, 0x0},
+ { 0x1308d, 0x0},
+ { 0x11308d, 0x0},
+ { 0x21308d, 0x0},
+ { 0x1318d, 0x0},
+ { 0x11318d, 0x0},
+ { 0x21318d, 0x0},
+ { 0x100c0, 0x0},
+ { 0x1100c0, 0x0},
+ { 0x2100c0, 0x0},
+ { 0x101c0, 0x0},
+ { 0x1101c0, 0x0},
+ { 0x2101c0, 0x0},
+ { 0x102c0, 0x0},
+ { 0x1102c0, 0x0},
+ { 0x2102c0, 0x0},
+ { 0x103c0, 0x0},
+ { 0x1103c0, 0x0},
+ { 0x2103c0, 0x0},
+ { 0x104c0, 0x0},
+ { 0x1104c0, 0x0},
+ { 0x2104c0, 0x0},
+ { 0x105c0, 0x0},
+ { 0x1105c0, 0x0},
+ { 0x2105c0, 0x0},
+ { 0x106c0, 0x0},
+ { 0x1106c0, 0x0},
+ { 0x2106c0, 0x0},
+ { 0x107c0, 0x0},
+ { 0x1107c0, 0x0},
+ { 0x2107c0, 0x0},
+ { 0x108c0, 0x0},
+ { 0x1108c0, 0x0},
+ { 0x2108c0, 0x0},
+ { 0x110c0, 0x0},
+ { 0x1110c0, 0x0},
+ { 0x2110c0, 0x0},
+ { 0x111c0, 0x0},
+ { 0x1111c0, 0x0},
+ { 0x2111c0, 0x0},
+ { 0x112c0, 0x0},
+ { 0x1112c0, 0x0},
+ { 0x2112c0, 0x0},
+ { 0x113c0, 0x0},
+ { 0x1113c0, 0x0},
+ { 0x2113c0, 0x0},
+ { 0x114c0, 0x0},
+ { 0x1114c0, 0x0},
+ { 0x2114c0, 0x0},
+ { 0x115c0, 0x0},
+ { 0x1115c0, 0x0},
+ { 0x2115c0, 0x0},
+ { 0x116c0, 0x0},
+ { 0x1116c0, 0x0},
+ { 0x2116c0, 0x0},
+ { 0x117c0, 0x0},
+ { 0x1117c0, 0x0},
+ { 0x2117c0, 0x0},
+ { 0x118c0, 0x0},
+ { 0x1118c0, 0x0},
+ { 0x2118c0, 0x0},
+ { 0x120c0, 0x0},
+ { 0x1120c0, 0x0},
+ { 0x2120c0, 0x0},
+ { 0x121c0, 0x0},
+ { 0x1121c0, 0x0},
+ { 0x2121c0, 0x0},
+ { 0x122c0, 0x0},
+ { 0x1122c0, 0x0},
+ { 0x2122c0, 0x0},
+ { 0x123c0, 0x0},
+ { 0x1123c0, 0x0},
+ { 0x2123c0, 0x0},
+ { 0x124c0, 0x0},
+ { 0x1124c0, 0x0},
+ { 0x2124c0, 0x0},
+ { 0x125c0, 0x0},
+ { 0x1125c0, 0x0},
+ { 0x2125c0, 0x0},
+ { 0x126c0, 0x0},
+ { 0x1126c0, 0x0},
+ { 0x2126c0, 0x0},
+ { 0x127c0, 0x0},
+ { 0x1127c0, 0x0},
+ { 0x2127c0, 0x0},
+ { 0x128c0, 0x0},
+ { 0x1128c0, 0x0},
+ { 0x2128c0, 0x0},
+ { 0x130c0, 0x0},
+ { 0x1130c0, 0x0},
+ { 0x2130c0, 0x0},
+ { 0x131c0, 0x0},
+ { 0x1131c0, 0x0},
+ { 0x2131c0, 0x0},
+ { 0x132c0, 0x0},
+ { 0x1132c0, 0x0},
+ { 0x2132c0, 0x0},
+ { 0x133c0, 0x0},
+ { 0x1133c0, 0x0},
+ { 0x2133c0, 0x0},
+ { 0x134c0, 0x0},
+ { 0x1134c0, 0x0},
+ { 0x2134c0, 0x0},
+ { 0x135c0, 0x0},
+ { 0x1135c0, 0x0},
+ { 0x2135c0, 0x0},
+ { 0x136c0, 0x0},
+ { 0x1136c0, 0x0},
+ { 0x2136c0, 0x0},
+ { 0x137c0, 0x0},
+ { 0x1137c0, 0x0},
+ { 0x2137c0, 0x0},
+ { 0x138c0, 0x0},
+ { 0x1138c0, 0x0},
+ { 0x2138c0, 0x0},
+ { 0x100c1, 0x0},
+ { 0x1100c1, 0x0},
+ { 0x2100c1, 0x0},
+ { 0x101c1, 0x0},
+ { 0x1101c1, 0x0},
+ { 0x2101c1, 0x0},
+ { 0x102c1, 0x0},
+ { 0x1102c1, 0x0},
+ { 0x2102c1, 0x0},
+ { 0x103c1, 0x0},
+ { 0x1103c1, 0x0},
+ { 0x2103c1, 0x0},
+ { 0x104c1, 0x0},
+ { 0x1104c1, 0x0},
+ { 0x2104c1, 0x0},
+ { 0x105c1, 0x0},
+ { 0x1105c1, 0x0},
+ { 0x2105c1, 0x0},
+ { 0x106c1, 0x0},
+ { 0x1106c1, 0x0},
+ { 0x2106c1, 0x0},
+ { 0x107c1, 0x0},
+ { 0x1107c1, 0x0},
+ { 0x2107c1, 0x0},
+ { 0x108c1, 0x0},
+ { 0x1108c1, 0x0},
+ { 0x2108c1, 0x0},
+ { 0x110c1, 0x0},
+ { 0x1110c1, 0x0},
+ { 0x2110c1, 0x0},
+ { 0x111c1, 0x0},
+ { 0x1111c1, 0x0},
+ { 0x2111c1, 0x0},
+ { 0x112c1, 0x0},
+ { 0x1112c1, 0x0},
+ { 0x2112c1, 0x0},
+ { 0x113c1, 0x0},
+ { 0x1113c1, 0x0},
+ { 0x2113c1, 0x0},
+ { 0x114c1, 0x0},
+ { 0x1114c1, 0x0},
+ { 0x2114c1, 0x0},
+ { 0x115c1, 0x0},
+ { 0x1115c1, 0x0},
+ { 0x2115c1, 0x0},
+ { 0x116c1, 0x0},
+ { 0x1116c1, 0x0},
+ { 0x2116c1, 0x0},
+ { 0x117c1, 0x0},
+ { 0x1117c1, 0x0},
+ { 0x2117c1, 0x0},
+ { 0x118c1, 0x0},
+ { 0x1118c1, 0x0},
+ { 0x2118c1, 0x0},
+ { 0x120c1, 0x0},
+ { 0x1120c1, 0x0},
+ { 0x2120c1, 0x0},
+ { 0x121c1, 0x0},
+ { 0x1121c1, 0x0},
+ { 0x2121c1, 0x0},
+ { 0x122c1, 0x0},
+ { 0x1122c1, 0x0},
+ { 0x2122c1, 0x0},
+ { 0x123c1, 0x0},
+ { 0x1123c1, 0x0},
+ { 0x2123c1, 0x0},
+ { 0x124c1, 0x0},
+ { 0x1124c1, 0x0},
+ { 0x2124c1, 0x0},
+ { 0x125c1, 0x0},
+ { 0x1125c1, 0x0},
+ { 0x2125c1, 0x0},
+ { 0x126c1, 0x0},
+ { 0x1126c1, 0x0},
+ { 0x2126c1, 0x0},
+ { 0x127c1, 0x0},
+ { 0x1127c1, 0x0},
+ { 0x2127c1, 0x0},
+ { 0x128c1, 0x0},
+ { 0x1128c1, 0x0},
+ { 0x2128c1, 0x0},
+ { 0x130c1, 0x0},
+ { 0x1130c1, 0x0},
+ { 0x2130c1, 0x0},
+ { 0x131c1, 0x0},
+ { 0x1131c1, 0x0},
+ { 0x2131c1, 0x0},
+ { 0x132c1, 0x0},
+ { 0x1132c1, 0x0},
+ { 0x2132c1, 0x0},
+ { 0x133c1, 0x0},
+ { 0x1133c1, 0x0},
+ { 0x2133c1, 0x0},
+ { 0x134c1, 0x0},
+ { 0x1134c1, 0x0},
+ { 0x2134c1, 0x0},
+ { 0x135c1, 0x0},
+ { 0x1135c1, 0x0},
+ { 0x2135c1, 0x0},
+ { 0x136c1, 0x0},
+ { 0x1136c1, 0x0},
+ { 0x2136c1, 0x0},
+ { 0x137c1, 0x0},
+ { 0x1137c1, 0x0},
+ { 0x2137c1, 0x0},
+ { 0x138c1, 0x0},
+ { 0x1138c1, 0x0},
+ { 0x2138c1, 0x0},
+ { 0x10020, 0x0},
+ { 0x110020, 0x0},
+ { 0x210020, 0x0},
+ { 0x11020, 0x0},
+ { 0x111020, 0x0},
+ { 0x211020, 0x0},
+ { 0x12020, 0x0},
+ { 0x112020, 0x0},
+ { 0x212020, 0x0},
+ { 0x13020, 0x0},
+ { 0x113020, 0x0},
+ { 0x213020, 0x0},
+ { 0x20072, 0x0},
+ { 0x20073, 0x0},
+ { 0x20074, 0x0},
+ { 0x100aa, 0x0},
+ { 0x110aa, 0x0},
+ { 0x120aa, 0x0},
+ { 0x130aa, 0x0},
+ { 0x20010, 0x0},
+ { 0x120010, 0x0},
+ { 0x220010, 0x0},
+ { 0x20011, 0x0},
+ { 0x120011, 0x0},
+ { 0x220011, 0x0},
+ { 0x100ae, 0x0},
+ { 0x1100ae, 0x0},
+ { 0x2100ae, 0x0},
+ { 0x100af, 0x0},
+ { 0x1100af, 0x0},
+ { 0x2100af, 0x0},
+ { 0x110ae, 0x0},
+ { 0x1110ae, 0x0},
+ { 0x2110ae, 0x0},
+ { 0x110af, 0x0},
+ { 0x1110af, 0x0},
+ { 0x2110af, 0x0},
+ { 0x120ae, 0x0},
+ { 0x1120ae, 0x0},
+ { 0x2120ae, 0x0},
+ { 0x120af, 0x0},
+ { 0x1120af, 0x0},
+ { 0x2120af, 0x0},
+ { 0x130ae, 0x0},
+ { 0x1130ae, 0x0},
+ { 0x2130ae, 0x0},
+ { 0x130af, 0x0},
+ { 0x1130af, 0x0},
+ { 0x2130af, 0x0},
+ { 0x20020, 0x0},
+ { 0x120020, 0x0},
+ { 0x220020, 0x0},
+ { 0x100a0, 0x0},
+ { 0x100a1, 0x0},
+ { 0x100a2, 0x0},
+ { 0x100a3, 0x0},
+ { 0x100a4, 0x0},
+ { 0x100a5, 0x0},
+ { 0x100a6, 0x0},
+ { 0x100a7, 0x0},
+ { 0x110a0, 0x0},
+ { 0x110a1, 0x0},
+ { 0x110a2, 0x0},
+ { 0x110a3, 0x0},
+ { 0x110a4, 0x0},
+ { 0x110a5, 0x0},
+ { 0x110a6, 0x0},
+ { 0x110a7, 0x0},
+ { 0x120a0, 0x0},
+ { 0x120a1, 0x0},
+ { 0x120a2, 0x0},
+ { 0x120a3, 0x0},
+ { 0x120a4, 0x0},
+ { 0x120a5, 0x0},
+ { 0x120a6, 0x0},
+ { 0x120a7, 0x0},
+ { 0x130a0, 0x0},
+ { 0x130a1, 0x0},
+ { 0x130a2, 0x0},
+ { 0x130a3, 0x0},
+ { 0x130a4, 0x0},
+ { 0x130a5, 0x0},
+ { 0x130a6, 0x0},
+ { 0x130a7, 0x0},
+ { 0x2007c, 0x0},
+ { 0x12007c, 0x0},
+ { 0x22007c, 0x0},
+ { 0x2007d, 0x0},
+ { 0x12007d, 0x0},
+ { 0x22007d, 0x0},
+ { 0x400fd, 0x0},
+ { 0x400c0, 0x0},
+ { 0x90201, 0x0},
+ { 0x190201, 0x0},
+ { 0x290201, 0x0},
+ { 0x90202, 0x0},
+ { 0x190202, 0x0},
+ { 0x290202, 0x0},
+ { 0x90203, 0x0},
+ { 0x190203, 0x0},
+ { 0x290203, 0x0},
+ { 0x90204, 0x0},
+ { 0x190204, 0x0},
+ { 0x290204, 0x0},
+ { 0x90205, 0x0},
+ { 0x190205, 0x0},
+ { 0x290205, 0x0},
+ { 0x90206, 0x0},
+ { 0x190206, 0x0},
+ { 0x290206, 0x0},
+ { 0x90207, 0x0},
+ { 0x190207, 0x0},
+ { 0x290207, 0x0},
+ { 0x90208, 0x0},
+ { 0x190208, 0x0},
+ { 0x290208, 0x0},
+ { 0x10062, 0x0},
+ { 0x10162, 0x0},
+ { 0x10262, 0x0},
+ { 0x10362, 0x0},
+ { 0x10462, 0x0},
+ { 0x10562, 0x0},
+ { 0x10662, 0x0},
+ { 0x10762, 0x0},
+ { 0x10862, 0x0},
+ { 0x11062, 0x0},
+ { 0x11162, 0x0},
+ { 0x11262, 0x0},
+ { 0x11362, 0x0},
+ { 0x11462, 0x0},
+ { 0x11562, 0x0},
+ { 0x11662, 0x0},
+ { 0x11762, 0x0},
+ { 0x11862, 0x0},
+ { 0x12062, 0x0},
+ { 0x12162, 0x0},
+ { 0x12262, 0x0},
+ { 0x12362, 0x0},
+ { 0x12462, 0x0},
+ { 0x12562, 0x0},
+ { 0x12662, 0x0},
+ { 0x12762, 0x0},
+ { 0x12862, 0x0},
+ { 0x13062, 0x0},
+ { 0x13162, 0x0},
+ { 0x13262, 0x0},
+ { 0x13362, 0x0},
+ { 0x13462, 0x0},
+ { 0x13562, 0x0},
+ { 0x13662, 0x0},
+ { 0x13762, 0x0},
+ { 0x13862, 0x0},
+ { 0x20077, 0x0},
+ { 0x10001, 0x0},
+ { 0x11001, 0x0},
+ { 0x12001, 0x0},
+ { 0x13001, 0x0},
+ { 0x10040, 0x0},
+ { 0x10140, 0x0},
+ { 0x10240, 0x0},
+ { 0x10340, 0x0},
+ { 0x10440, 0x0},
+ { 0x10540, 0x0},
+ { 0x10640, 0x0},
+ { 0x10740, 0x0},
+ { 0x10840, 0x0},
+ { 0x10030, 0x0},
+ { 0x10130, 0x0},
+ { 0x10230, 0x0},
+ { 0x10330, 0x0},
+ { 0x10430, 0x0},
+ { 0x10530, 0x0},
+ { 0x10630, 0x0},
+ { 0x10730, 0x0},
+ { 0x10830, 0x0},
+ { 0x11040, 0x0},
+ { 0x11140, 0x0},
+ { 0x11240, 0x0},
+ { 0x11340, 0x0},
+ { 0x11440, 0x0},
+ { 0x11540, 0x0},
+ { 0x11640, 0x0},
+ { 0x11740, 0x0},
+ { 0x11840, 0x0},
+ { 0x11030, 0x0},
+ { 0x11130, 0x0},
+ { 0x11230, 0x0},
+ { 0x11330, 0x0},
+ { 0x11430, 0x0},
+ { 0x11530, 0x0},
+ { 0x11630, 0x0},
+ { 0x11730, 0x0},
+ { 0x11830, 0x0},
+ { 0x12040, 0x0},
+ { 0x12140, 0x0},
+ { 0x12240, 0x0},
+ { 0x12340, 0x0},
+ { 0x12440, 0x0},
+ { 0x12540, 0x0},
+ { 0x12640, 0x0},
+ { 0x12740, 0x0},
+ { 0x12840, 0x0},
+ { 0x12030, 0x0},
+ { 0x12130, 0x0},
+ { 0x12230, 0x0},
+ { 0x12330, 0x0},
+ { 0x12430, 0x0},
+ { 0x12530, 0x0},
+ { 0x12630, 0x0},
+ { 0x12730, 0x0},
+ { 0x12830, 0x0},
+ { 0x13040, 0x0},
+ { 0x13140, 0x0},
+ { 0x13240, 0x0},
+ { 0x13340, 0x0},
+ { 0x13440, 0x0},
+ { 0x13540, 0x0},
+ { 0x13640, 0x0},
+ { 0x13740, 0x0},
+ { 0x13840, 0x0},
+ { 0x13030, 0x0},
+ { 0x13130, 0x0},
+ { 0x13230, 0x0},
+ { 0x13330, 0x0},
+ { 0x13430, 0x0},
+ { 0x13530, 0x0},
+ { 0x13630, 0x0},
+ { 0x13730, 0x0},
+ { 0x13830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x960},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x24c4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x24c4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0xc400},
+ {0x54033, 0x3124},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xc400},
+ {0x54039, 0x3124},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x101},
+ {0x54003, 0x190},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x64},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0x960},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400f, 0x100},
+ {0x54010, 0x1f7f},
+ {0x54012, 0x110},
+ {0x54019, 0x24c4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x24c4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0xc400},
+ {0x54033, 0x3124},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xc400},
+ {0x54039, 0x3124},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xf},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x630},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x630},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x630},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x630},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x630},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x630},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x630},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x630},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x630},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x630},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x630},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x630},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xa},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x2},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x900a4, 0x10},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x623},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x623},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x790},
+ {0x900a9, 0x11a},
+ {0x900aa, 0x8},
+ {0x900ab, 0x7aa},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x10},
+ {0x900ae, 0x7b2},
+ {0x900af, 0x2a},
+ {0x900b0, 0x0},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x0},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xc},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x0},
+ {0x90169, 0x8},
+ {0x9016a, 0x8},
+ {0x9016b, 0x448},
+ {0x9016c, 0x109},
+ {0x9016d, 0xf},
+ {0x9016e, 0x7c0},
+ {0x9016f, 0x109},
+ {0x90170, 0x0},
+ {0x90171, 0xe8},
+ {0x90172, 0x109},
+ {0x90173, 0x47},
+ {0x90174, 0x630},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0x618},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0xe0},
+ {0x9017b, 0x109},
+ {0x9017c, 0x0},
+ {0x9017d, 0x7c8},
+ {0x9017e, 0x109},
+ {0x9017f, 0x8},
+ {0x90180, 0x8140},
+ {0x90181, 0x10c},
+ {0x90182, 0x0},
+ {0x90183, 0x1},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x4},
+ {0x90187, 0x8},
+ {0x90188, 0x8},
+ {0x90189, 0x7c8},
+ {0x9018a, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2a},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x4b},
+ {0x2000c, 0x96},
+ {0x2000d, 0x5dc},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x60},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x220010, 0x5a},
+ {0x220011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x12011, 0x1},
+ {0x12012, 0x1},
+ {0x12013, 0x180},
+ {0x12018, 0x1},
+ {0x12002, 0x6209},
+ {0x120b2, 0x1},
+ {0x121b4, 0x1},
+ {0x122b4, 0x1},
+ {0x123b4, 0x1},
+ {0x124b4, 0x1},
+ {0x125b4, 0x1},
+ {0x126b4, 0x1},
+ {0x127b4, 0x1},
+ {0x128b4, 0x1},
+ {0x13011, 0x1},
+ {0x13012, 0x1},
+ {0x13013, 0x180},
+ {0x13018, 0x1},
+ {0x13002, 0x6209},
+ {0x130b2, 0x1},
+ {0x131b4, 0x1},
+ {0x132b4, 0x1},
+ {0x133b4, 0x1},
+ {0x134b4, 0x1},
+ {0x135b4, 0x1},
+ {0x136b4, 0x1},
+ {0x137b4, 0x1},
+ {0x138b4, 0x1},
+ {0x2003a, 0x2},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 2400mts 1D */
+ .drate = 2400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 2400mts 2D */
+ .drate = 2400,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info ucm_dram_timing_01061010 = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 2400, 400, 100, },
+};
+
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c
new file mode 100644
index 0000000..5141c04
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_01061010.c
@@ -0,0 +1,1847 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ {0x3d400304, 0x1},
+ {0x3d400030, 0x1},
+ {0x3d400000, 0xa1080020},
+ {0x3d400020, 0x223},
+ {0x3d400024, 0x3a980},
+ {0x3d400064, 0x5b00d2},
+ {0x3d4000d0, 0xc00305ba},
+ {0x3d4000d4, 0x940000},
+ {0x3d4000dc, 0xd4002d},
+ {0x3d4000e0, 0x310000},
+ {0x3d4000e8, 0x66004d},
+ {0x3d4000ec, 0x16004d},
+ {0x3d400100, 0x191e1920},
+ {0x3d400104, 0x60630},
+ {0x3d40010c, 0xb0b000},
+ {0x3d400110, 0xe04080e},
+ {0x3d400114, 0x2040c0c},
+ {0x3d400118, 0x1010007},
+ {0x3d40011c, 0x401},
+ {0x3d400130, 0x20600},
+ {0x3d400134, 0xc100002},
+ {0x3d400138, 0xd8},
+ {0x3d400144, 0x96004b},
+ {0x3d400180, 0x2ee0017},
+ {0x3d400184, 0x2605b8e},
+ {0x3d400188, 0x0},
+ {0x3d400190, 0x497820a},
+ {0x3d400194, 0x80303},
+ {0x3d4001b4, 0x170a},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0xdf00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x11},
+ {0x3d4001c0, 0x1},
+ {0x3d4001c4, 0x0},
+ {0x3d4000f4, 0xc99},
+ {0x3d400108, 0x70e1617},
+ {0x3d400200, 0x1f},
+ {0x3d40020c, 0x0},
+ {0x3d400210, 0x1f1f},
+ {0x3d400204, 0x80808},
+ {0x3d400214, 0x7070707},
+ {0x3d400218, 0x7070707},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x2c},
+ {0x3d40025c, 0x4000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x2005574},
+ {0x3d400400, 0x111},
+ {0x3d400408, 0x72ff},
+ {0x3d400494, 0x2100e07},
+ {0x3d400498, 0x620096},
+ {0x3d40049c, 0x1100e07},
+ {0x3d4004a0, 0xc8012c},
+ {0x3d402020, 0x21},
+ {0x3d402024, 0x7d00},
+ {0x3d402050, 0x20d040},
+ {0x3d402064, 0xc001c},
+ {0x3d4020dc, 0x840000},
+ {0x3d4020e0, 0x310000},
+ {0x3d4020e8, 0x66004d},
+ {0x3d4020ec, 0x16004d},
+ {0x3d402100, 0xa040305},
+ {0x3d402104, 0x30407},
+ {0x3d402108, 0x203060b},
+ {0x3d40210c, 0x505000},
+ {0x3d402110, 0x2040202},
+ {0x3d402114, 0x2030202},
+ {0x3d402118, 0x1010004},
+ {0x3d40211c, 0x301},
+ {0x3d402130, 0x20300},
+ {0x3d402134, 0xa100002},
+ {0x3d402138, 0x1d},
+ {0x3d402144, 0x14000a},
+ {0x3d402180, 0x640004},
+ {0x3d402190, 0x3818200},
+ {0x3d402194, 0x80303},
+ {0x3d4021b4, 0x100},
+ {0x3d403020, 0x21},
+ {0x3d403024, 0x1f40},
+ {0x3d403050, 0x20d040},
+ {0x3d403064, 0x30007},
+ {0x3d4030dc, 0x840000},
+ {0x3d4030e0, 0x310000},
+ {0x3d4030e8, 0x66004d},
+ {0x3d4030ec, 0x16004d},
+ {0x3d403100, 0xa010102},
+ {0x3d403104, 0x30404},
+ {0x3d403108, 0x203060b},
+ {0x3d40310c, 0x505000},
+ {0x3d403110, 0x2040202},
+ {0x3d403114, 0x2030202},
+ {0x3d403118, 0x1010004},
+ {0x3d40311c, 0x301},
+ {0x3d403130, 0x20300},
+ {0x3d403134, 0xa100002},
+ {0x3d403138, 0x8},
+ {0x3d403144, 0x50003},
+ {0x3d403180, 0x190004},
+ {0x3d403190, 0x3818200},
+ {0x3d403194, 0x80303},
+ {0x3d4031b4, 0x100},
+ {0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x0},
+ {0x100a1, 0x1},
+ {0x100a2, 0x2},
+ {0x100a3, 0x3},
+ {0x100a4, 0x4},
+ {0x100a5, 0x5},
+ {0x100a6, 0x6},
+ {0x100a7, 0x7},
+ {0x110a0, 0x0},
+ {0x110a1, 0x1},
+ {0x110a2, 0x3},
+ {0x110a3, 0x4},
+ {0x110a4, 0x5},
+ {0x110a5, 0x2},
+ {0x110a6, 0x7},
+ {0x110a7, 0x6},
+ {0x120a0, 0x0},
+ {0x120a1, 0x1},
+ {0x120a2, 0x3},
+ {0x120a3, 0x2},
+ {0x120a4, 0x5},
+ {0x120a5, 0x4},
+ {0x120a6, 0x7},
+ {0x120a7, 0x6},
+ {0x130a0, 0x0},
+ {0x130a1, 0x1},
+ {0x130a2, 0x2},
+ {0x130a3, 0x3},
+ {0x130a4, 0x4},
+ {0x130a5, 0x5},
+ {0x130a6, 0x6},
+ {0x130a7, 0x7},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x1205f, 0x1ff},
+ {0x1215f, 0x1ff},
+ {0x1305f, 0x1ff},
+ {0x1315f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x11205f, 0x1ff},
+ {0x11215f, 0x1ff},
+ {0x11305f, 0x1ff},
+ {0x11315f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x21205f, 0x1ff},
+ {0x21215f, 0x1ff},
+ {0x21305f, 0x1ff},
+ {0x21315f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x3055, 0x1ff},
+ {0x4055, 0x1ff},
+ {0x5055, 0x1ff},
+ {0x6055, 0x1ff},
+ {0x7055, 0x1ff},
+ {0x8055, 0x1ff},
+ {0x9055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0x7},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x120024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x220024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x20056, 0x3},
+ {0x120056, 0xa},
+ {0x220056, 0xa},
+ {0x1004d, 0xe00},
+ {0x1014d, 0xe00},
+ {0x1104d, 0xe00},
+ {0x1114d, 0xe00},
+ {0x1204d, 0xe00},
+ {0x1214d, 0xe00},
+ {0x1304d, 0xe00},
+ {0x1314d, 0xe00},
+ {0x11004d, 0xe00},
+ {0x11014d, 0xe00},
+ {0x11104d, 0xe00},
+ {0x11114d, 0xe00},
+ {0x11204d, 0xe00},
+ {0x11214d, 0xe00},
+ {0x11304d, 0xe00},
+ {0x11314d, 0xe00},
+ {0x21004d, 0xe00},
+ {0x21014d, 0xe00},
+ {0x21104d, 0xe00},
+ {0x21114d, 0xe00},
+ {0x21204d, 0xe00},
+ {0x21214d, 0xe00},
+ {0x21304d, 0xe00},
+ {0x21314d, 0xe00},
+ {0x10049, 0xeba},
+ {0x10149, 0xeba},
+ {0x11049, 0xeba},
+ {0x11149, 0xeba},
+ {0x12049, 0xeba},
+ {0x12149, 0xeba},
+ {0x13049, 0xeba},
+ {0x13149, 0xeba},
+ {0x110049, 0xeba},
+ {0x110149, 0xeba},
+ {0x111049, 0xeba},
+ {0x111149, 0xeba},
+ {0x112049, 0xeba},
+ {0x112149, 0xeba},
+ {0x113049, 0xeba},
+ {0x113149, 0xeba},
+ {0x210049, 0xeba},
+ {0x210149, 0xeba},
+ {0x211049, 0xeba},
+ {0x211149, 0xeba},
+ {0x212049, 0xeba},
+ {0x212149, 0xeba},
+ {0x213049, 0xeba},
+ {0x213149, 0xeba},
+ {0x43, 0x63},
+ {0x1043, 0x63},
+ {0x2043, 0x63},
+ {0x3043, 0x63},
+ {0x4043, 0x63},
+ {0x5043, 0x63},
+ {0x6043, 0x63},
+ {0x7043, 0x63},
+ {0x8043, 0x63},
+ {0x9043, 0x63},
+ {0x20018, 0x3},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x20008, 0x2ee},
+ {0x120008, 0x64},
+ {0x220008, 0x19},
+ {0x20088, 0x9},
+ {0x200b2, 0xdc},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x12043, 0x5a1},
+ {0x12143, 0x5a1},
+ {0x13043, 0x5a1},
+ {0x13143, 0x5a1},
+ {0x1200b2, 0xdc},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x112043, 0x5a1},
+ {0x112143, 0x5a1},
+ {0x113043, 0x5a1},
+ {0x113143, 0x5a1},
+ {0x2200b2, 0xdc},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x212043, 0x5a1},
+ {0x212143, 0x5a1},
+ {0x213043, 0x5a1},
+ {0x213143, 0x5a1},
+ {0x200fa, 0x1},
+ {0x1200fa, 0x1},
+ {0x2200fa, 0x1},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x660},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5665},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+ {0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0},
+ { 0x1200b2, 0x0},
+ { 0x2200b2, 0x0},
+ { 0x200cb, 0x0},
+ { 0x10043, 0x0},
+ { 0x110043, 0x0},
+ { 0x210043, 0x0},
+ { 0x10143, 0x0},
+ { 0x110143, 0x0},
+ { 0x210143, 0x0},
+ { 0x11043, 0x0},
+ { 0x111043, 0x0},
+ { 0x211043, 0x0},
+ { 0x11143, 0x0},
+ { 0x111143, 0x0},
+ { 0x211143, 0x0},
+ { 0x12043, 0x0},
+ { 0x112043, 0x0},
+ { 0x212043, 0x0},
+ { 0x12143, 0x0},
+ { 0x112143, 0x0},
+ { 0x212143, 0x0},
+ { 0x13043, 0x0},
+ { 0x113043, 0x0},
+ { 0x213043, 0x0},
+ { 0x13143, 0x0},
+ { 0x113143, 0x0},
+ { 0x213143, 0x0},
+ { 0x80, 0x0},
+ { 0x100080, 0x0},
+ { 0x200080, 0x0},
+ { 0x1080, 0x0},
+ { 0x101080, 0x0},
+ { 0x201080, 0x0},
+ { 0x2080, 0x0},
+ { 0x102080, 0x0},
+ { 0x202080, 0x0},
+ { 0x3080, 0x0},
+ { 0x103080, 0x0},
+ { 0x203080, 0x0},
+ { 0x4080, 0x0},
+ { 0x104080, 0x0},
+ { 0x204080, 0x0},
+ { 0x5080, 0x0},
+ { 0x105080, 0x0},
+ { 0x205080, 0x0},
+ { 0x6080, 0x0},
+ { 0x106080, 0x0},
+ { 0x206080, 0x0},
+ { 0x7080, 0x0},
+ { 0x107080, 0x0},
+ { 0x207080, 0x0},
+ { 0x8080, 0x0},
+ { 0x108080, 0x0},
+ { 0x208080, 0x0},
+ { 0x9080, 0x0},
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+ { 0x13762, 0x0},
+ { 0x13862, 0x0},
+ { 0x20077, 0x0},
+ { 0x10001, 0x0},
+ { 0x11001, 0x0},
+ { 0x12001, 0x0},
+ { 0x13001, 0x0},
+ { 0x10040, 0x0},
+ { 0x10140, 0x0},
+ { 0x10240, 0x0},
+ { 0x10340, 0x0},
+ { 0x10440, 0x0},
+ { 0x10540, 0x0},
+ { 0x10640, 0x0},
+ { 0x10740, 0x0},
+ { 0x10840, 0x0},
+ { 0x10030, 0x0},
+ { 0x10130, 0x0},
+ { 0x10230, 0x0},
+ { 0x10330, 0x0},
+ { 0x10430, 0x0},
+ { 0x10530, 0x0},
+ { 0x10630, 0x0},
+ { 0x10730, 0x0},
+ { 0x10830, 0x0},
+ { 0x11040, 0x0},
+ { 0x11140, 0x0},
+ { 0x11240, 0x0},
+ { 0x11340, 0x0},
+ { 0x11440, 0x0},
+ { 0x11540, 0x0},
+ { 0x11640, 0x0},
+ { 0x11740, 0x0},
+ { 0x11840, 0x0},
+ { 0x11030, 0x0},
+ { 0x11130, 0x0},
+ { 0x11230, 0x0},
+ { 0x11330, 0x0},
+ { 0x11430, 0x0},
+ { 0x11530, 0x0},
+ { 0x11630, 0x0},
+ { 0x11730, 0x0},
+ { 0x11830, 0x0},
+ { 0x12040, 0x0},
+ { 0x12140, 0x0},
+ { 0x12240, 0x0},
+ { 0x12340, 0x0},
+ { 0x12440, 0x0},
+ { 0x12540, 0x0},
+ { 0x12640, 0x0},
+ { 0x12740, 0x0},
+ { 0x12840, 0x0},
+ { 0x12030, 0x0},
+ { 0x12130, 0x0},
+ { 0x12230, 0x0},
+ { 0x12330, 0x0},
+ { 0x12430, 0x0},
+ { 0x12530, 0x0},
+ { 0x12630, 0x0},
+ { 0x12730, 0x0},
+ { 0x12830, 0x0},
+ { 0x13040, 0x0},
+ { 0x13140, 0x0},
+ { 0x13240, 0x0},
+ { 0x13340, 0x0},
+ { 0x13440, 0x0},
+ { 0x13540, 0x0},
+ { 0x13640, 0x0},
+ { 0x13740, 0x0},
+ { 0x13840, 0x0},
+ { 0x13030, 0x0},
+ { 0x13130, 0x0},
+ { 0x13230, 0x0},
+ { 0x13330, 0x0},
+ { 0x13430, 0x0},
+ { 0x13530, 0x0},
+ { 0x13630, 0x0},
+ { 0x13730, 0x0},
+ { 0x13830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x101},
+ {0x54003, 0x190},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x64},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400f, 0x100},
+ {0x54010, 0x1f7f},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xf},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x630},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x630},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x630},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x630},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x630},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x630},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x630},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x630},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x630},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x630},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x630},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x630},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xa},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x2},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x900a4, 0x10},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x623},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x623},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x790},
+ {0x900a9, 0x11a},
+ {0x900aa, 0x8},
+ {0x900ab, 0x7aa},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x10},
+ {0x900ae, 0x7b2},
+ {0x900af, 0x2a},
+ {0x900b0, 0x0},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x0},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xc},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x0},
+ {0x90169, 0x8},
+ {0x9016a, 0x8},
+ {0x9016b, 0x448},
+ {0x9016c, 0x109},
+ {0x9016d, 0xf},
+ {0x9016e, 0x7c0},
+ {0x9016f, 0x109},
+ {0x90170, 0x0},
+ {0x90171, 0xe8},
+ {0x90172, 0x109},
+ {0x90173, 0x47},
+ {0x90174, 0x630},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0x618},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0xe0},
+ {0x9017b, 0x109},
+ {0x9017c, 0x0},
+ {0x9017d, 0x7c8},
+ {0x9017e, 0x109},
+ {0x9017f, 0x8},
+ {0x90180, 0x8140},
+ {0x90181, 0x10c},
+ {0x90182, 0x0},
+ {0x90183, 0x1},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x4},
+ {0x90187, 0x8},
+ {0x90188, 0x8},
+ {0x90189, 0x7c8},
+ {0x9018a, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2a},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x5d},
+ {0x2000c, 0xbb},
+ {0x2000d, 0x753},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x60},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x220010, 0x5a},
+ {0x220011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x12011, 0x1},
+ {0x12012, 0x1},
+ {0x12013, 0x180},
+ {0x12018, 0x1},
+ {0x12002, 0x6209},
+ {0x120b2, 0x1},
+ {0x121b4, 0x1},
+ {0x122b4, 0x1},
+ {0x123b4, 0x1},
+ {0x124b4, 0x1},
+ {0x125b4, 0x1},
+ {0x126b4, 0x1},
+ {0x127b4, 0x1},
+ {0x128b4, 0x1},
+ {0x13011, 0x1},
+ {0x13012, 0x1},
+ {0x13013, 0x180},
+ {0x13018, 0x1},
+ {0x13002, 0x6209},
+ {0x130b2, 0x1},
+ {0x131b4, 0x1},
+ {0x132b4, 0x1},
+ {0x133b4, 0x1},
+ {0x134b4, 0x1},
+ {0x135b4, 0x1},
+ {0x136b4, 0x1},
+ {0x137b4, 0x1},
+ {0x138b4, 0x1},
+ {0x2003a, 0x2},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info ucm_dram_timing_01061010 = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c
new file mode 100644
index 0000000..2334722
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff000110.c
@@ -0,0 +1,1847 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ {0x3d400304, 0x1},
+ {0x3d400030, 0x1},
+ {0x3d400000, 0xa3080020},
+ {0x3d400020, 0x223},
+ {0x3d400024, 0x3a980},
+ {0x3d400064, 0x5b00d2},
+ {0x3d4000d0, 0xc00305ba},
+ {0x3d4000d4, 0x940000},
+ {0x3d4000dc, 0xd4002d},
+ {0x3d4000e0, 0x310000},
+ {0x3d4000e8, 0x66004d},
+ {0x3d4000ec, 0x16004d},
+ {0x3d400100, 0x191e1920},
+ {0x3d400104, 0x60630},
+ {0x3d40010c, 0xb0b000},
+ {0x3d400110, 0xe04080e},
+ {0x3d400114, 0x2040c0c},
+ {0x3d400118, 0x1010007},
+ {0x3d40011c, 0x401},
+ {0x3d400130, 0x20600},
+ {0x3d400134, 0xc100002},
+ {0x3d400138, 0xd8},
+ {0x3d400144, 0x96004b},
+ {0x3d400180, 0x2ee0017},
+ {0x3d400184, 0x2605b8e},
+ {0x3d400188, 0x0},
+ {0x3d400190, 0x497820a},
+ {0x3d400194, 0x80303},
+ {0x3d4001b4, 0x170a},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0xdf00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x11},
+ {0x3d4001c0, 0x1},
+ {0x3d4001c4, 0x0},
+ {0x3d4000f4, 0xc99},
+ {0x3d400108, 0x70e1617},
+ {0x3d400200, 0x17},
+ {0x3d40020c, 0x0},
+ {0x3d400210, 0x1f1f},
+ {0x3d400204, 0x80808},
+ {0x3d400214, 0x7070707},
+ {0x3d400218, 0x7070707},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x2c},
+ {0x3d40025c, 0x4000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x2005574},
+ {0x3d400400, 0x111},
+ {0x3d400408, 0x72ff},
+ {0x3d400494, 0x2100e07},
+ {0x3d400498, 0x620096},
+ {0x3d40049c, 0x1100e07},
+ {0x3d4004a0, 0xc8012c},
+ {0x3d402020, 0x21},
+ {0x3d402024, 0x7d00},
+ {0x3d402050, 0x20d040},
+ {0x3d402064, 0xc001c},
+ {0x3d4020dc, 0x840000},
+ {0x3d4020e0, 0x310000},
+ {0x3d4020e8, 0x66004d},
+ {0x3d4020ec, 0x16004d},
+ {0x3d402100, 0xa040305},
+ {0x3d402104, 0x30407},
+ {0x3d402108, 0x203060b},
+ {0x3d40210c, 0x505000},
+ {0x3d402110, 0x2040202},
+ {0x3d402114, 0x2030202},
+ {0x3d402118, 0x1010004},
+ {0x3d40211c, 0x301},
+ {0x3d402130, 0x20300},
+ {0x3d402134, 0xa100002},
+ {0x3d402138, 0x1d},
+ {0x3d402144, 0x14000a},
+ {0x3d402180, 0x640004},
+ {0x3d402190, 0x3818200},
+ {0x3d402194, 0x80303},
+ {0x3d4021b4, 0x100},
+ {0x3d403020, 0x21},
+ {0x3d403024, 0x1f40},
+ {0x3d403050, 0x20d040},
+ {0x3d403064, 0x30007},
+ {0x3d4030dc, 0x840000},
+ {0x3d4030e0, 0x310000},
+ {0x3d4030e8, 0x66004d},
+ {0x3d4030ec, 0x16004d},
+ {0x3d403100, 0xa010102},
+ {0x3d403104, 0x30404},
+ {0x3d403108, 0x203060b},
+ {0x3d40310c, 0x505000},
+ {0x3d403110, 0x2040202},
+ {0x3d403114, 0x2030202},
+ {0x3d403118, 0x1010004},
+ {0x3d40311c, 0x301},
+ {0x3d403130, 0x20300},
+ {0x3d403134, 0xa100002},
+ {0x3d403138, 0x8},
+ {0x3d403144, 0x50003},
+ {0x3d403180, 0x190004},
+ {0x3d403190, 0x3818200},
+ {0x3d403194, 0x80303},
+ {0x3d4031b4, 0x100},
+ {0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x0},
+ {0x100a1, 0x1},
+ {0x100a2, 0x2},
+ {0x100a3, 0x3},
+ {0x100a4, 0x4},
+ {0x100a5, 0x5},
+ {0x100a6, 0x6},
+ {0x100a7, 0x7},
+ {0x110a0, 0x0},
+ {0x110a1, 0x1},
+ {0x110a2, 0x3},
+ {0x110a3, 0x4},
+ {0x110a4, 0x5},
+ {0x110a5, 0x2},
+ {0x110a6, 0x7},
+ {0x110a7, 0x6},
+ {0x120a0, 0x0},
+ {0x120a1, 0x1},
+ {0x120a2, 0x3},
+ {0x120a3, 0x2},
+ {0x120a4, 0x5},
+ {0x120a5, 0x4},
+ {0x120a6, 0x7},
+ {0x120a7, 0x6},
+ {0x130a0, 0x0},
+ {0x130a1, 0x1},
+ {0x130a2, 0x2},
+ {0x130a3, 0x3},
+ {0x130a4, 0x4},
+ {0x130a5, 0x5},
+ {0x130a6, 0x6},
+ {0x130a7, 0x7},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x1205f, 0x1ff},
+ {0x1215f, 0x1ff},
+ {0x1305f, 0x1ff},
+ {0x1315f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x11205f, 0x1ff},
+ {0x11215f, 0x1ff},
+ {0x11305f, 0x1ff},
+ {0x11315f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x21205f, 0x1ff},
+ {0x21215f, 0x1ff},
+ {0x21305f, 0x1ff},
+ {0x21315f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x3055, 0x1ff},
+ {0x4055, 0x1ff},
+ {0x5055, 0x1ff},
+ {0x6055, 0x1ff},
+ {0x7055, 0x1ff},
+ {0x8055, 0x1ff},
+ {0x9055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0x7},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x120024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x220024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x20056, 0x3},
+ {0x120056, 0xa},
+ {0x220056, 0xa},
+ {0x1004d, 0xe00},
+ {0x1014d, 0xe00},
+ {0x1104d, 0xe00},
+ {0x1114d, 0xe00},
+ {0x1204d, 0xe00},
+ {0x1214d, 0xe00},
+ {0x1304d, 0xe00},
+ {0x1314d, 0xe00},
+ {0x11004d, 0xe00},
+ {0x11014d, 0xe00},
+ {0x11104d, 0xe00},
+ {0x11114d, 0xe00},
+ {0x11204d, 0xe00},
+ {0x11214d, 0xe00},
+ {0x11304d, 0xe00},
+ {0x11314d, 0xe00},
+ {0x21004d, 0xe00},
+ {0x21014d, 0xe00},
+ {0x21104d, 0xe00},
+ {0x21114d, 0xe00},
+ {0x21204d, 0xe00},
+ {0x21214d, 0xe00},
+ {0x21304d, 0xe00},
+ {0x21314d, 0xe00},
+ {0x10049, 0xeba},
+ {0x10149, 0xeba},
+ {0x11049, 0xeba},
+ {0x11149, 0xeba},
+ {0x12049, 0xeba},
+ {0x12149, 0xeba},
+ {0x13049, 0xeba},
+ {0x13149, 0xeba},
+ {0x110049, 0xeba},
+ {0x110149, 0xeba},
+ {0x111049, 0xeba},
+ {0x111149, 0xeba},
+ {0x112049, 0xeba},
+ {0x112149, 0xeba},
+ {0x113049, 0xeba},
+ {0x113149, 0xeba},
+ {0x210049, 0xeba},
+ {0x210149, 0xeba},
+ {0x211049, 0xeba},
+ {0x211149, 0xeba},
+ {0x212049, 0xeba},
+ {0x212149, 0xeba},
+ {0x213049, 0xeba},
+ {0x213149, 0xeba},
+ {0x43, 0x63},
+ {0x1043, 0x63},
+ {0x2043, 0x63},
+ {0x3043, 0x63},
+ {0x4043, 0x63},
+ {0x5043, 0x63},
+ {0x6043, 0x63},
+ {0x7043, 0x63},
+ {0x8043, 0x63},
+ {0x9043, 0x63},
+ {0x20018, 0x3},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x20008, 0x2ee},
+ {0x120008, 0x64},
+ {0x220008, 0x19},
+ {0x20088, 0x9},
+ {0x200b2, 0xdc},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x12043, 0x5a1},
+ {0x12143, 0x5a1},
+ {0x13043, 0x5a1},
+ {0x13143, 0x5a1},
+ {0x1200b2, 0xdc},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x112043, 0x5a1},
+ {0x112143, 0x5a1},
+ {0x113043, 0x5a1},
+ {0x113143, 0x5a1},
+ {0x2200b2, 0xdc},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x212043, 0x5a1},
+ {0x212143, 0x5a1},
+ {0x213043, 0x5a1},
+ {0x213143, 0x5a1},
+ {0x200fa, 0x1},
+ {0x1200fa, 0x1},
+ {0x2200fa, 0x1},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x660},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5665},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+ {0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0},
+ { 0x1200b2, 0x0},
+ { 0x2200b2, 0x0},
+ { 0x200cb, 0x0},
+ { 0x10043, 0x0},
+ { 0x110043, 0x0},
+ { 0x210043, 0x0},
+ { 0x10143, 0x0},
+ { 0x110143, 0x0},
+ { 0x210143, 0x0},
+ { 0x11043, 0x0},
+ { 0x111043, 0x0},
+ { 0x211043, 0x0},
+ { 0x11143, 0x0},
+ { 0x111143, 0x0},
+ { 0x211143, 0x0},
+ { 0x12043, 0x0},
+ { 0x112043, 0x0},
+ { 0x212043, 0x0},
+ { 0x12143, 0x0},
+ { 0x112143, 0x0},
+ { 0x212143, 0x0},
+ { 0x13043, 0x0},
+ { 0x113043, 0x0},
+ { 0x213043, 0x0},
+ { 0x13143, 0x0},
+ { 0x113143, 0x0},
+ { 0x213143, 0x0},
+ { 0x80, 0x0},
+ { 0x100080, 0x0},
+ { 0x200080, 0x0},
+ { 0x1080, 0x0},
+ { 0x101080, 0x0},
+ { 0x201080, 0x0},
+ { 0x2080, 0x0},
+ { 0x102080, 0x0},
+ { 0x202080, 0x0},
+ { 0x3080, 0x0},
+ { 0x103080, 0x0},
+ { 0x203080, 0x0},
+ { 0x4080, 0x0},
+ { 0x104080, 0x0},
+ { 0x204080, 0x0},
+ { 0x5080, 0x0},
+ { 0x105080, 0x0},
+ { 0x205080, 0x0},
+ { 0x6080, 0x0},
+ { 0x106080, 0x0},
+ { 0x206080, 0x0},
+ { 0x7080, 0x0},
+ { 0x107080, 0x0},
+ { 0x207080, 0x0},
+ { 0x8080, 0x0},
+ { 0x108080, 0x0},
+ { 0x208080, 0x0},
+ { 0x9080, 0x0},
+ { 0x109080, 0x0},
+ { 0x209080, 0x0},
+ { 0x10080, 0x0},
+ { 0x110080, 0x0},
+ { 0x210080, 0x0},
+ { 0x10180, 0x0},
+ { 0x110180, 0x0},
+ { 0x210180, 0x0},
+ { 0x11080, 0x0},
+ { 0x111080, 0x0},
+ { 0x211080, 0x0},
+ { 0x11180, 0x0},
+ { 0x111180, 0x0},
+ { 0x211180, 0x0},
+ { 0x12080, 0x0},
+ { 0x112080, 0x0},
+ { 0x212080, 0x0},
+ { 0x12180, 0x0},
+ { 0x112180, 0x0},
+ { 0x212180, 0x0},
+ { 0x13080, 0x0},
+ { 0x113080, 0x0},
+ { 0x213080, 0x0},
+ { 0x13180, 0x0},
+ { 0x113180, 0x0},
+ { 0x213180, 0x0},
+ { 0x10081, 0x0},
+ { 0x110081, 0x0},
+ { 0x210081, 0x0},
+ { 0x10181, 0x0},
+ { 0x110181, 0x0},
+ { 0x210181, 0x0},
+ { 0x11081, 0x0},
+ { 0x111081, 0x0},
+ { 0x211081, 0x0},
+ { 0x11181, 0x0},
+ { 0x111181, 0x0},
+ { 0x211181, 0x0},
+ { 0x12081, 0x0},
+ { 0x112081, 0x0},
+ { 0x212081, 0x0},
+ { 0x12181, 0x0},
+ { 0x112181, 0x0},
+ { 0x212181, 0x0},
+ { 0x13081, 0x0},
+ { 0x113081, 0x0},
+ { 0x213081, 0x0},
+ { 0x13181, 0x0},
+ { 0x113181, 0x0},
+ { 0x213181, 0x0},
+ { 0x100d0, 0x0},
+ { 0x1100d0, 0x0},
+ { 0x2100d0, 0x0},
+ { 0x101d0, 0x0},
+ { 0x1101d0, 0x0},
+ { 0x2101d0, 0x0},
+ { 0x110d0, 0x0},
+ { 0x1110d0, 0x0},
+ { 0x2110d0, 0x0},
+ { 0x111d0, 0x0},
+ { 0x1111d0, 0x0},
+ { 0x2111d0, 0x0},
+ { 0x120d0, 0x0},
+ { 0x1120d0, 0x0},
+ { 0x2120d0, 0x0},
+ { 0x121d0, 0x0},
+ { 0x1121d0, 0x0},
+ { 0x2121d0, 0x0},
+ { 0x130d0, 0x0},
+ { 0x1130d0, 0x0},
+ { 0x2130d0, 0x0},
+ { 0x131d0, 0x0},
+ { 0x1131d0, 0x0},
+ { 0x2131d0, 0x0},
+ { 0x100d1, 0x0},
+ { 0x1100d1, 0x0},
+ { 0x2100d1, 0x0},
+ { 0x101d1, 0x0},
+ { 0x1101d1, 0x0},
+ { 0x2101d1, 0x0},
+ { 0x110d1, 0x0},
+ { 0x1110d1, 0x0},
+ { 0x2110d1, 0x0},
+ { 0x111d1, 0x0},
+ { 0x1111d1, 0x0},
+ { 0x2111d1, 0x0},
+ { 0x120d1, 0x0},
+ { 0x1120d1, 0x0},
+ { 0x2120d1, 0x0},
+ { 0x121d1, 0x0},
+ { 0x1121d1, 0x0},
+ { 0x2121d1, 0x0},
+ { 0x130d1, 0x0},
+ { 0x1130d1, 0x0},
+ { 0x2130d1, 0x0},
+ { 0x131d1, 0x0},
+ { 0x1131d1, 0x0},
+ { 0x2131d1, 0x0},
+ { 0x10068, 0x0},
+ { 0x10168, 0x0},
+ { 0x10268, 0x0},
+ { 0x10368, 0x0},
+ { 0x10468, 0x0},
+ { 0x10568, 0x0},
+ { 0x10668, 0x0},
+ { 0x10768, 0x0},
+ { 0x10868, 0x0},
+ { 0x11068, 0x0},
+ { 0x11168, 0x0},
+ { 0x11268, 0x0},
+ { 0x11368, 0x0},
+ { 0x11468, 0x0},
+ { 0x11568, 0x0},
+ { 0x11668, 0x0},
+ { 0x11768, 0x0},
+ { 0x11868, 0x0},
+ { 0x12068, 0x0},
+ { 0x12168, 0x0},
+ { 0x12268, 0x0},
+ { 0x12368, 0x0},
+ { 0x12468, 0x0},
+ { 0x12568, 0x0},
+ { 0x12668, 0x0},
+ { 0x12768, 0x0},
+ { 0x12868, 0x0},
+ { 0x13068, 0x0},
+ { 0x13168, 0x0},
+ { 0x13268, 0x0},
+ { 0x13368, 0x0},
+ { 0x13468, 0x0},
+ { 0x13568, 0x0},
+ { 0x13668, 0x0},
+ { 0x13768, 0x0},
+ { 0x13868, 0x0},
+ { 0x10069, 0x0},
+ { 0x10169, 0x0},
+ { 0x10269, 0x0},
+ { 0x10369, 0x0},
+ { 0x10469, 0x0},
+ { 0x10569, 0x0},
+ { 0x10669, 0x0},
+ { 0x10769, 0x0},
+ { 0x10869, 0x0},
+ { 0x11069, 0x0},
+ { 0x11169, 0x0},
+ { 0x11269, 0x0},
+ { 0x11369, 0x0},
+ { 0x11469, 0x0},
+ { 0x11569, 0x0},
+ { 0x11669, 0x0},
+ { 0x11769, 0x0},
+ { 0x11869, 0x0},
+ { 0x12069, 0x0},
+ { 0x12169, 0x0},
+ { 0x12269, 0x0},
+ { 0x12369, 0x0},
+ { 0x12469, 0x0},
+ { 0x12569, 0x0},
+ { 0x12669, 0x0},
+ { 0x12769, 0x0},
+ { 0x12869, 0x0},
+ { 0x13069, 0x0},
+ { 0x13169, 0x0},
+ { 0x13269, 0x0},
+ { 0x13369, 0x0},
+ { 0x13469, 0x0},
+ { 0x13569, 0x0},
+ { 0x13669, 0x0},
+ { 0x13769, 0x0},
+ { 0x13869, 0x0},
+ { 0x1008c, 0x0},
+ { 0x11008c, 0x0},
+ { 0x21008c, 0x0},
+ { 0x1018c, 0x0},
+ { 0x11018c, 0x0},
+ { 0x21018c, 0x0},
+ { 0x1108c, 0x0},
+ { 0x11108c, 0x0},
+ { 0x21108c, 0x0},
+ { 0x1118c, 0x0},
+ { 0x11118c, 0x0},
+ { 0x21118c, 0x0},
+ { 0x1208c, 0x0},
+ { 0x11208c, 0x0},
+ { 0x21208c, 0x0},
+ { 0x1218c, 0x0},
+ { 0x11218c, 0x0},
+ { 0x21218c, 0x0},
+ { 0x1308c, 0x0},
+ { 0x11308c, 0x0},
+ { 0x21308c, 0x0},
+ { 0x1318c, 0x0},
+ { 0x11318c, 0x0},
+ { 0x21318c, 0x0},
+ { 0x1008d, 0x0},
+ { 0x11008d, 0x0},
+ { 0x21008d, 0x0},
+ { 0x1018d, 0x0},
+ { 0x11018d, 0x0},
+ { 0x21018d, 0x0},
+ { 0x1108d, 0x0},
+ { 0x11108d, 0x0},
+ { 0x21108d, 0x0},
+ { 0x1118d, 0x0},
+ { 0x11118d, 0x0},
+ { 0x21118d, 0x0},
+ { 0x1208d, 0x0},
+ { 0x11208d, 0x0},
+ { 0x21208d, 0x0},
+ { 0x1218d, 0x0},
+ { 0x11218d, 0x0},
+ { 0x21218d, 0x0},
+ { 0x1308d, 0x0},
+ { 0x11308d, 0x0},
+ { 0x21308d, 0x0},
+ { 0x1318d, 0x0},
+ { 0x11318d, 0x0},
+ { 0x21318d, 0x0},
+ { 0x100c0, 0x0},
+ { 0x1100c0, 0x0},
+ { 0x2100c0, 0x0},
+ { 0x101c0, 0x0},
+ { 0x1101c0, 0x0},
+ { 0x2101c0, 0x0},
+ { 0x102c0, 0x0},
+ { 0x1102c0, 0x0},
+ { 0x2102c0, 0x0},
+ { 0x103c0, 0x0},
+ { 0x1103c0, 0x0},
+ { 0x2103c0, 0x0},
+ { 0x104c0, 0x0},
+ { 0x1104c0, 0x0},
+ { 0x2104c0, 0x0},
+ { 0x105c0, 0x0},
+ { 0x1105c0, 0x0},
+ { 0x2105c0, 0x0},
+ { 0x106c0, 0x0},
+ { 0x1106c0, 0x0},
+ { 0x2106c0, 0x0},
+ { 0x107c0, 0x0},
+ { 0x1107c0, 0x0},
+ { 0x2107c0, 0x0},
+ { 0x108c0, 0x0},
+ { 0x1108c0, 0x0},
+ { 0x2108c0, 0x0},
+ { 0x110c0, 0x0},
+ { 0x1110c0, 0x0},
+ { 0x2110c0, 0x0},
+ { 0x111c0, 0x0},
+ { 0x1111c0, 0x0},
+ { 0x2111c0, 0x0},
+ { 0x112c0, 0x0},
+ { 0x1112c0, 0x0},
+ { 0x2112c0, 0x0},
+ { 0x113c0, 0x0},
+ { 0x1113c0, 0x0},
+ { 0x2113c0, 0x0},
+ { 0x114c0, 0x0},
+ { 0x1114c0, 0x0},
+ { 0x2114c0, 0x0},
+ { 0x115c0, 0x0},
+ { 0x1115c0, 0x0},
+ { 0x2115c0, 0x0},
+ { 0x116c0, 0x0},
+ { 0x1116c0, 0x0},
+ { 0x2116c0, 0x0},
+ { 0x117c0, 0x0},
+ { 0x1117c0, 0x0},
+ { 0x2117c0, 0x0},
+ { 0x118c0, 0x0},
+ { 0x1118c0, 0x0},
+ { 0x2118c0, 0x0},
+ { 0x120c0, 0x0},
+ { 0x1120c0, 0x0},
+ { 0x2120c0, 0x0},
+ { 0x121c0, 0x0},
+ { 0x1121c0, 0x0},
+ { 0x2121c0, 0x0},
+ { 0x122c0, 0x0},
+ { 0x1122c0, 0x0},
+ { 0x2122c0, 0x0},
+ { 0x123c0, 0x0},
+ { 0x1123c0, 0x0},
+ { 0x2123c0, 0x0},
+ { 0x124c0, 0x0},
+ { 0x1124c0, 0x0},
+ { 0x2124c0, 0x0},
+ { 0x125c0, 0x0},
+ { 0x1125c0, 0x0},
+ { 0x2125c0, 0x0},
+ { 0x126c0, 0x0},
+ { 0x1126c0, 0x0},
+ { 0x2126c0, 0x0},
+ { 0x127c0, 0x0},
+ { 0x1127c0, 0x0},
+ { 0x2127c0, 0x0},
+ { 0x128c0, 0x0},
+ { 0x1128c0, 0x0},
+ { 0x2128c0, 0x0},
+ { 0x130c0, 0x0},
+ { 0x1130c0, 0x0},
+ { 0x2130c0, 0x0},
+ { 0x131c0, 0x0},
+ { 0x1131c0, 0x0},
+ { 0x2131c0, 0x0},
+ { 0x132c0, 0x0},
+ { 0x1132c0, 0x0},
+ { 0x2132c0, 0x0},
+ { 0x133c0, 0x0},
+ { 0x1133c0, 0x0},
+ { 0x2133c0, 0x0},
+ { 0x134c0, 0x0},
+ { 0x1134c0, 0x0},
+ { 0x2134c0, 0x0},
+ { 0x135c0, 0x0},
+ { 0x1135c0, 0x0},
+ { 0x2135c0, 0x0},
+ { 0x136c0, 0x0},
+ { 0x1136c0, 0x0},
+ { 0x2136c0, 0x0},
+ { 0x137c0, 0x0},
+ { 0x1137c0, 0x0},
+ { 0x2137c0, 0x0},
+ { 0x138c0, 0x0},
+ { 0x1138c0, 0x0},
+ { 0x2138c0, 0x0},
+ { 0x100c1, 0x0},
+ { 0x1100c1, 0x0},
+ { 0x2100c1, 0x0},
+ { 0x101c1, 0x0},
+ { 0x1101c1, 0x0},
+ { 0x2101c1, 0x0},
+ { 0x102c1, 0x0},
+ { 0x1102c1, 0x0},
+ { 0x2102c1, 0x0},
+ { 0x103c1, 0x0},
+ { 0x1103c1, 0x0},
+ { 0x2103c1, 0x0},
+ { 0x104c1, 0x0},
+ { 0x1104c1, 0x0},
+ { 0x2104c1, 0x0},
+ { 0x105c1, 0x0},
+ { 0x1105c1, 0x0},
+ { 0x2105c1, 0x0},
+ { 0x106c1, 0x0},
+ { 0x1106c1, 0x0},
+ { 0x2106c1, 0x0},
+ { 0x107c1, 0x0},
+ { 0x1107c1, 0x0},
+ { 0x2107c1, 0x0},
+ { 0x108c1, 0x0},
+ { 0x1108c1, 0x0},
+ { 0x2108c1, 0x0},
+ { 0x110c1, 0x0},
+ { 0x1110c1, 0x0},
+ { 0x2110c1, 0x0},
+ { 0x111c1, 0x0},
+ { 0x1111c1, 0x0},
+ { 0x2111c1, 0x0},
+ { 0x112c1, 0x0},
+ { 0x1112c1, 0x0},
+ { 0x2112c1, 0x0},
+ { 0x113c1, 0x0},
+ { 0x1113c1, 0x0},
+ { 0x2113c1, 0x0},
+ { 0x114c1, 0x0},
+ { 0x1114c1, 0x0},
+ { 0x2114c1, 0x0},
+ { 0x115c1, 0x0},
+ { 0x1115c1, 0x0},
+ { 0x2115c1, 0x0},
+ { 0x116c1, 0x0},
+ { 0x1116c1, 0x0},
+ { 0x2116c1, 0x0},
+ { 0x117c1, 0x0},
+ { 0x1117c1, 0x0},
+ { 0x2117c1, 0x0},
+ { 0x118c1, 0x0},
+ { 0x1118c1, 0x0},
+ { 0x2118c1, 0x0},
+ { 0x120c1, 0x0},
+ { 0x1120c1, 0x0},
+ { 0x2120c1, 0x0},
+ { 0x121c1, 0x0},
+ { 0x1121c1, 0x0},
+ { 0x2121c1, 0x0},
+ { 0x122c1, 0x0},
+ { 0x1122c1, 0x0},
+ { 0x2122c1, 0x0},
+ { 0x123c1, 0x0},
+ { 0x1123c1, 0x0},
+ { 0x2123c1, 0x0},
+ { 0x124c1, 0x0},
+ { 0x1124c1, 0x0},
+ { 0x2124c1, 0x0},
+ { 0x125c1, 0x0},
+ { 0x1125c1, 0x0},
+ { 0x2125c1, 0x0},
+ { 0x126c1, 0x0},
+ { 0x1126c1, 0x0},
+ { 0x2126c1, 0x0},
+ { 0x127c1, 0x0},
+ { 0x1127c1, 0x0},
+ { 0x2127c1, 0x0},
+ { 0x128c1, 0x0},
+ { 0x1128c1, 0x0},
+ { 0x2128c1, 0x0},
+ { 0x130c1, 0x0},
+ { 0x1130c1, 0x0},
+ { 0x2130c1, 0x0},
+ { 0x131c1, 0x0},
+ { 0x1131c1, 0x0},
+ { 0x2131c1, 0x0},
+ { 0x132c1, 0x0},
+ { 0x1132c1, 0x0},
+ { 0x2132c1, 0x0},
+ { 0x133c1, 0x0},
+ { 0x1133c1, 0x0},
+ { 0x2133c1, 0x0},
+ { 0x134c1, 0x0},
+ { 0x1134c1, 0x0},
+ { 0x2134c1, 0x0},
+ { 0x135c1, 0x0},
+ { 0x1135c1, 0x0},
+ { 0x2135c1, 0x0},
+ { 0x136c1, 0x0},
+ { 0x1136c1, 0x0},
+ { 0x2136c1, 0x0},
+ { 0x137c1, 0x0},
+ { 0x1137c1, 0x0},
+ { 0x2137c1, 0x0},
+ { 0x138c1, 0x0},
+ { 0x1138c1, 0x0},
+ { 0x2138c1, 0x0},
+ { 0x10020, 0x0},
+ { 0x110020, 0x0},
+ { 0x210020, 0x0},
+ { 0x11020, 0x0},
+ { 0x111020, 0x0},
+ { 0x211020, 0x0},
+ { 0x12020, 0x0},
+ { 0x112020, 0x0},
+ { 0x212020, 0x0},
+ { 0x13020, 0x0},
+ { 0x113020, 0x0},
+ { 0x213020, 0x0},
+ { 0x20072, 0x0},
+ { 0x20073, 0x0},
+ { 0x20074, 0x0},
+ { 0x100aa, 0x0},
+ { 0x110aa, 0x0},
+ { 0x120aa, 0x0},
+ { 0x130aa, 0x0},
+ { 0x20010, 0x0},
+ { 0x120010, 0x0},
+ { 0x220010, 0x0},
+ { 0x20011, 0x0},
+ { 0x120011, 0x0},
+ { 0x220011, 0x0},
+ { 0x100ae, 0x0},
+ { 0x1100ae, 0x0},
+ { 0x2100ae, 0x0},
+ { 0x100af, 0x0},
+ { 0x1100af, 0x0},
+ { 0x2100af, 0x0},
+ { 0x110ae, 0x0},
+ { 0x1110ae, 0x0},
+ { 0x2110ae, 0x0},
+ { 0x110af, 0x0},
+ { 0x1110af, 0x0},
+ { 0x2110af, 0x0},
+ { 0x120ae, 0x0},
+ { 0x1120ae, 0x0},
+ { 0x2120ae, 0x0},
+ { 0x120af, 0x0},
+ { 0x1120af, 0x0},
+ { 0x2120af, 0x0},
+ { 0x130ae, 0x0},
+ { 0x1130ae, 0x0},
+ { 0x2130ae, 0x0},
+ { 0x130af, 0x0},
+ { 0x1130af, 0x0},
+ { 0x2130af, 0x0},
+ { 0x20020, 0x0},
+ { 0x120020, 0x0},
+ { 0x220020, 0x0},
+ { 0x100a0, 0x0},
+ { 0x100a1, 0x0},
+ { 0x100a2, 0x0},
+ { 0x100a3, 0x0},
+ { 0x100a4, 0x0},
+ { 0x100a5, 0x0},
+ { 0x100a6, 0x0},
+ { 0x100a7, 0x0},
+ { 0x110a0, 0x0},
+ { 0x110a1, 0x0},
+ { 0x110a2, 0x0},
+ { 0x110a3, 0x0},
+ { 0x110a4, 0x0},
+ { 0x110a5, 0x0},
+ { 0x110a6, 0x0},
+ { 0x110a7, 0x0},
+ { 0x120a0, 0x0},
+ { 0x120a1, 0x0},
+ { 0x120a2, 0x0},
+ { 0x120a3, 0x0},
+ { 0x120a4, 0x0},
+ { 0x120a5, 0x0},
+ { 0x120a6, 0x0},
+ { 0x120a7, 0x0},
+ { 0x130a0, 0x0},
+ { 0x130a1, 0x0},
+ { 0x130a2, 0x0},
+ { 0x130a3, 0x0},
+ { 0x130a4, 0x0},
+ { 0x130a5, 0x0},
+ { 0x130a6, 0x0},
+ { 0x130a7, 0x0},
+ { 0x2007c, 0x0},
+ { 0x12007c, 0x0},
+ { 0x22007c, 0x0},
+ { 0x2007d, 0x0},
+ { 0x12007d, 0x0},
+ { 0x22007d, 0x0},
+ { 0x400fd, 0x0},
+ { 0x400c0, 0x0},
+ { 0x90201, 0x0},
+ { 0x190201, 0x0},
+ { 0x290201, 0x0},
+ { 0x90202, 0x0},
+ { 0x190202, 0x0},
+ { 0x290202, 0x0},
+ { 0x90203, 0x0},
+ { 0x190203, 0x0},
+ { 0x290203, 0x0},
+ { 0x90204, 0x0},
+ { 0x190204, 0x0},
+ { 0x290204, 0x0},
+ { 0x90205, 0x0},
+ { 0x190205, 0x0},
+ { 0x290205, 0x0},
+ { 0x90206, 0x0},
+ { 0x190206, 0x0},
+ { 0x290206, 0x0},
+ { 0x90207, 0x0},
+ { 0x190207, 0x0},
+ { 0x290207, 0x0},
+ { 0x90208, 0x0},
+ { 0x190208, 0x0},
+ { 0x290208, 0x0},
+ { 0x10062, 0x0},
+ { 0x10162, 0x0},
+ { 0x10262, 0x0},
+ { 0x10362, 0x0},
+ { 0x10462, 0x0},
+ { 0x10562, 0x0},
+ { 0x10662, 0x0},
+ { 0x10762, 0x0},
+ { 0x10862, 0x0},
+ { 0x11062, 0x0},
+ { 0x11162, 0x0},
+ { 0x11262, 0x0},
+ { 0x11362, 0x0},
+ { 0x11462, 0x0},
+ { 0x11562, 0x0},
+ { 0x11662, 0x0},
+ { 0x11762, 0x0},
+ { 0x11862, 0x0},
+ { 0x12062, 0x0},
+ { 0x12162, 0x0},
+ { 0x12262, 0x0},
+ { 0x12362, 0x0},
+ { 0x12462, 0x0},
+ { 0x12562, 0x0},
+ { 0x12662, 0x0},
+ { 0x12762, 0x0},
+ { 0x12862, 0x0},
+ { 0x13062, 0x0},
+ { 0x13162, 0x0},
+ { 0x13262, 0x0},
+ { 0x13362, 0x0},
+ { 0x13462, 0x0},
+ { 0x13562, 0x0},
+ { 0x13662, 0x0},
+ { 0x13762, 0x0},
+ { 0x13862, 0x0},
+ { 0x20077, 0x0},
+ { 0x10001, 0x0},
+ { 0x11001, 0x0},
+ { 0x12001, 0x0},
+ { 0x13001, 0x0},
+ { 0x10040, 0x0},
+ { 0x10140, 0x0},
+ { 0x10240, 0x0},
+ { 0x10340, 0x0},
+ { 0x10440, 0x0},
+ { 0x10540, 0x0},
+ { 0x10640, 0x0},
+ { 0x10740, 0x0},
+ { 0x10840, 0x0},
+ { 0x10030, 0x0},
+ { 0x10130, 0x0},
+ { 0x10230, 0x0},
+ { 0x10330, 0x0},
+ { 0x10430, 0x0},
+ { 0x10530, 0x0},
+ { 0x10630, 0x0},
+ { 0x10730, 0x0},
+ { 0x10830, 0x0},
+ { 0x11040, 0x0},
+ { 0x11140, 0x0},
+ { 0x11240, 0x0},
+ { 0x11340, 0x0},
+ { 0x11440, 0x0},
+ { 0x11540, 0x0},
+ { 0x11640, 0x0},
+ { 0x11740, 0x0},
+ { 0x11840, 0x0},
+ { 0x11030, 0x0},
+ { 0x11130, 0x0},
+ { 0x11230, 0x0},
+ { 0x11330, 0x0},
+ { 0x11430, 0x0},
+ { 0x11530, 0x0},
+ { 0x11630, 0x0},
+ { 0x11730, 0x0},
+ { 0x11830, 0x0},
+ { 0x12040, 0x0},
+ { 0x12140, 0x0},
+ { 0x12240, 0x0},
+ { 0x12340, 0x0},
+ { 0x12440, 0x0},
+ { 0x12540, 0x0},
+ { 0x12640, 0x0},
+ { 0x12740, 0x0},
+ { 0x12840, 0x0},
+ { 0x12030, 0x0},
+ { 0x12130, 0x0},
+ { 0x12230, 0x0},
+ { 0x12330, 0x0},
+ { 0x12430, 0x0},
+ { 0x12530, 0x0},
+ { 0x12630, 0x0},
+ { 0x12730, 0x0},
+ { 0x12830, 0x0},
+ { 0x13040, 0x0},
+ { 0x13140, 0x0},
+ { 0x13240, 0x0},
+ { 0x13340, 0x0},
+ { 0x13440, 0x0},
+ { 0x13540, 0x0},
+ { 0x13640, 0x0},
+ { 0x13740, 0x0},
+ { 0x13840, 0x0},
+ { 0x13030, 0x0},
+ { 0x13130, 0x0},
+ { 0x13230, 0x0},
+ { 0x13330, 0x0},
+ { 0x13430, 0x0},
+ { 0x13530, 0x0},
+ { 0x13630, 0x0},
+ { 0x13730, 0x0},
+ { 0x13830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x101},
+ {0x54003, 0x190},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x64},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400f, 0x100},
+ {0x54010, 0x1f7f},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xf},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x630},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x630},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x630},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x630},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x630},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x630},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x630},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x630},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x630},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x630},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x630},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x630},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xa},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x2},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x900a4, 0x10},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x623},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x623},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x790},
+ {0x900a9, 0x11a},
+ {0x900aa, 0x8},
+ {0x900ab, 0x7aa},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x10},
+ {0x900ae, 0x7b2},
+ {0x900af, 0x2a},
+ {0x900b0, 0x0},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x0},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xc},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x0},
+ {0x90169, 0x8},
+ {0x9016a, 0x8},
+ {0x9016b, 0x448},
+ {0x9016c, 0x109},
+ {0x9016d, 0xf},
+ {0x9016e, 0x7c0},
+ {0x9016f, 0x109},
+ {0x90170, 0x0},
+ {0x90171, 0xe8},
+ {0x90172, 0x109},
+ {0x90173, 0x47},
+ {0x90174, 0x630},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0x618},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0xe0},
+ {0x9017b, 0x109},
+ {0x9017c, 0x0},
+ {0x9017d, 0x7c8},
+ {0x9017e, 0x109},
+ {0x9017f, 0x8},
+ {0x90180, 0x8140},
+ {0x90181, 0x10c},
+ {0x90182, 0x0},
+ {0x90183, 0x1},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x4},
+ {0x90187, 0x8},
+ {0x90188, 0x8},
+ {0x90189, 0x7c8},
+ {0x9018a, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2a},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x5d},
+ {0x2000c, 0xbb},
+ {0x2000d, 0x753},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x60},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x220010, 0x5a},
+ {0x220011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x12011, 0x1},
+ {0x12012, 0x1},
+ {0x12013, 0x180},
+ {0x12018, 0x1},
+ {0x12002, 0x6209},
+ {0x120b2, 0x1},
+ {0x121b4, 0x1},
+ {0x122b4, 0x1},
+ {0x123b4, 0x1},
+ {0x124b4, 0x1},
+ {0x125b4, 0x1},
+ {0x126b4, 0x1},
+ {0x127b4, 0x1},
+ {0x128b4, 0x1},
+ {0x13011, 0x1},
+ {0x13012, 0x1},
+ {0x13013, 0x180},
+ {0x13018, 0x1},
+ {0x13002, 0x6209},
+ {0x130b2, 0x1},
+ {0x131b4, 0x1},
+ {0x132b4, 0x1},
+ {0x133b4, 0x1},
+ {0x134b4, 0x1},
+ {0x135b4, 0x1},
+ {0x136b4, 0x1},
+ {0x137b4, 0x1},
+ {0x138b4, 0x1},
+ {0x2003a, 0x2},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info ucm_dram_timing_ff000110 = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c
new file mode 100644
index 0000000..e65445e
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/ddr/lpddr4_timing_ff020008.c
@@ -0,0 +1,1847 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+static struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /** Initialize DDRC registers **/
+ {0x3d400304, 0x1},
+ {0x3d400030, 0x1},
+ {0x3d400000, 0xa3080020},
+ {0x3d400020, 0x223},
+ {0x3d400024, 0x3a980},
+ {0x3d400064, 0x5b00d2},
+ {0x3d4000d0, 0xc00305ba},
+ {0x3d4000d4, 0x940000},
+ {0x3d4000dc, 0xd4002d},
+ {0x3d4000e0, 0x310000},
+ {0x3d4000e8, 0x66004d},
+ {0x3d4000ec, 0x16004d},
+ {0x3d400100, 0x191e1920},
+ {0x3d400104, 0x60630},
+ {0x3d40010c, 0xb0b000},
+ {0x3d400110, 0xe04080e},
+ {0x3d400114, 0x2040c0c},
+ {0x3d400118, 0x1010007},
+ {0x3d40011c, 0x401},
+ {0x3d400130, 0x20600},
+ {0x3d400134, 0xc100002},
+ {0x3d400138, 0xd8},
+ {0x3d400144, 0x96004b},
+ {0x3d400180, 0x2ee0017},
+ {0x3d400184, 0x2605b8e},
+ {0x3d400188, 0x0},
+ {0x3d400190, 0x497820a},
+ {0x3d400194, 0x80303},
+ {0x3d4001b4, 0x170a},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0xdf00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x11},
+ {0x3d4001c0, 0x1},
+ {0x3d4001c4, 0x0},
+ {0x3d4000f4, 0xc99},
+ {0x3d400108, 0x70e1617},
+ {0x3d400200, 0x16},
+ {0x3d40020c, 0x0},
+ {0x3d400210, 0x1f1f},
+ {0x3d400204, 0x80808},
+ {0x3d400214, 0x7070707},
+ {0x3d400218, 0xf070707},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x2c},
+ {0x3d40025c, 0x4000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x2005574},
+ {0x3d400400, 0x111},
+ {0x3d400408, 0x72ff},
+ {0x3d400494, 0x2100e07},
+ {0x3d400498, 0x620096},
+ {0x3d40049c, 0x1100e07},
+ {0x3d4004a0, 0xc8012c},
+ {0x3d402020, 0x21},
+ {0x3d402024, 0x7d00},
+ {0x3d402050, 0x20d040},
+ {0x3d402064, 0xc001c},
+ {0x3d4020dc, 0x840000},
+ {0x3d4020e0, 0x310000},
+ {0x3d4020e8, 0x66004d},
+ {0x3d4020ec, 0x16004d},
+ {0x3d402100, 0xa040305},
+ {0x3d402104, 0x30407},
+ {0x3d402108, 0x203060b},
+ {0x3d40210c, 0x505000},
+ {0x3d402110, 0x2040202},
+ {0x3d402114, 0x2030202},
+ {0x3d402118, 0x1010004},
+ {0x3d40211c, 0x301},
+ {0x3d402130, 0x20300},
+ {0x3d402134, 0xa100002},
+ {0x3d402138, 0x1d},
+ {0x3d402144, 0x14000a},
+ {0x3d402180, 0x640004},
+ {0x3d402190, 0x3818200},
+ {0x3d402194, 0x80303},
+ {0x3d4021b4, 0x100},
+ {0x3d403020, 0x21},
+ {0x3d403024, 0x1f40},
+ {0x3d403050, 0x20d040},
+ {0x3d403064, 0x30007},
+ {0x3d4030dc, 0x840000},
+ {0x3d4030e0, 0x310000},
+ {0x3d4030e8, 0x66004d},
+ {0x3d4030ec, 0x16004d},
+ {0x3d403100, 0xa010102},
+ {0x3d403104, 0x30404},
+ {0x3d403108, 0x203060b},
+ {0x3d40310c, 0x505000},
+ {0x3d403110, 0x2040202},
+ {0x3d403114, 0x2030202},
+ {0x3d403118, 0x1010004},
+ {0x3d40311c, 0x301},
+ {0x3d403130, 0x20300},
+ {0x3d403134, 0xa100002},
+ {0x3d403138, 0x8},
+ {0x3d403144, 0x50003},
+ {0x3d403180, 0x190004},
+ {0x3d403190, 0x3818200},
+ {0x3d403194, 0x80303},
+ {0x3d4031b4, 0x100},
+ {0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+static struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x0},
+ {0x100a1, 0x1},
+ {0x100a2, 0x2},
+ {0x100a3, 0x3},
+ {0x100a4, 0x4},
+ {0x100a5, 0x5},
+ {0x100a6, 0x6},
+ {0x100a7, 0x7},
+ {0x110a0, 0x0},
+ {0x110a1, 0x1},
+ {0x110a2, 0x3},
+ {0x110a3, 0x4},
+ {0x110a4, 0x5},
+ {0x110a5, 0x2},
+ {0x110a6, 0x7},
+ {0x110a7, 0x6},
+ {0x120a0, 0x0},
+ {0x120a1, 0x1},
+ {0x120a2, 0x3},
+ {0x120a3, 0x2},
+ {0x120a4, 0x5},
+ {0x120a5, 0x4},
+ {0x120a6, 0x7},
+ {0x120a7, 0x6},
+ {0x130a0, 0x0},
+ {0x130a1, 0x1},
+ {0x130a2, 0x2},
+ {0x130a3, 0x3},
+ {0x130a4, 0x4},
+ {0x130a5, 0x5},
+ {0x130a6, 0x6},
+ {0x130a7, 0x7},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x1205f, 0x1ff},
+ {0x1215f, 0x1ff},
+ {0x1305f, 0x1ff},
+ {0x1315f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x11205f, 0x1ff},
+ {0x11215f, 0x1ff},
+ {0x11305f, 0x1ff},
+ {0x11315f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x21205f, 0x1ff},
+ {0x21215f, 0x1ff},
+ {0x21305f, 0x1ff},
+ {0x21315f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x3055, 0x1ff},
+ {0x4055, 0x1ff},
+ {0x5055, 0x1ff},
+ {0x6055, 0x1ff},
+ {0x7055, 0x1ff},
+ {0x8055, 0x1ff},
+ {0x9055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0x7},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x120024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x220024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x20056, 0x3},
+ {0x120056, 0xa},
+ {0x220056, 0xa},
+ {0x1004d, 0xe00},
+ {0x1014d, 0xe00},
+ {0x1104d, 0xe00},
+ {0x1114d, 0xe00},
+ {0x1204d, 0xe00},
+ {0x1214d, 0xe00},
+ {0x1304d, 0xe00},
+ {0x1314d, 0xe00},
+ {0x11004d, 0xe00},
+ {0x11014d, 0xe00},
+ {0x11104d, 0xe00},
+ {0x11114d, 0xe00},
+ {0x11204d, 0xe00},
+ {0x11214d, 0xe00},
+ {0x11304d, 0xe00},
+ {0x11314d, 0xe00},
+ {0x21004d, 0xe00},
+ {0x21014d, 0xe00},
+ {0x21104d, 0xe00},
+ {0x21114d, 0xe00},
+ {0x21204d, 0xe00},
+ {0x21214d, 0xe00},
+ {0x21304d, 0xe00},
+ {0x21314d, 0xe00},
+ {0x10049, 0xeba},
+ {0x10149, 0xeba},
+ {0x11049, 0xeba},
+ {0x11149, 0xeba},
+ {0x12049, 0xeba},
+ {0x12149, 0xeba},
+ {0x13049, 0xeba},
+ {0x13149, 0xeba},
+ {0x110049, 0xeba},
+ {0x110149, 0xeba},
+ {0x111049, 0xeba},
+ {0x111149, 0xeba},
+ {0x112049, 0xeba},
+ {0x112149, 0xeba},
+ {0x113049, 0xeba},
+ {0x113149, 0xeba},
+ {0x210049, 0xeba},
+ {0x210149, 0xeba},
+ {0x211049, 0xeba},
+ {0x211149, 0xeba},
+ {0x212049, 0xeba},
+ {0x212149, 0xeba},
+ {0x213049, 0xeba},
+ {0x213149, 0xeba},
+ {0x43, 0x63},
+ {0x1043, 0x63},
+ {0x2043, 0x63},
+ {0x3043, 0x63},
+ {0x4043, 0x63},
+ {0x5043, 0x63},
+ {0x6043, 0x63},
+ {0x7043, 0x63},
+ {0x8043, 0x63},
+ {0x9043, 0x63},
+ {0x20018, 0x3},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x20008, 0x2ee},
+ {0x120008, 0x64},
+ {0x220008, 0x19},
+ {0x20088, 0x9},
+ {0x200b2, 0xdc},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x12043, 0x5a1},
+ {0x12143, 0x5a1},
+ {0x13043, 0x5a1},
+ {0x13143, 0x5a1},
+ {0x1200b2, 0xdc},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x112043, 0x5a1},
+ {0x112143, 0x5a1},
+ {0x113043, 0x5a1},
+ {0x113143, 0x5a1},
+ {0x2200b2, 0xdc},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x212043, 0x5a1},
+ {0x212143, 0x5a1},
+ {0x213043, 0x5a1},
+ {0x213143, 0x5a1},
+ {0x200fa, 0x1},
+ {0x1200fa, 0x1},
+ {0x2200fa, 0x1},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x660},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5665},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+ {0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+static struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0},
+ { 0x1200b2, 0x0},
+ { 0x2200b2, 0x0},
+ { 0x200cb, 0x0},
+ { 0x10043, 0x0},
+ { 0x110043, 0x0},
+ { 0x210043, 0x0},
+ { 0x10143, 0x0},
+ { 0x110143, 0x0},
+ { 0x210143, 0x0},
+ { 0x11043, 0x0},
+ { 0x111043, 0x0},
+ { 0x211043, 0x0},
+ { 0x11143, 0x0},
+ { 0x111143, 0x0},
+ { 0x211143, 0x0},
+ { 0x12043, 0x0},
+ { 0x112043, 0x0},
+ { 0x212043, 0x0},
+ { 0x12143, 0x0},
+ { 0x112143, 0x0},
+ { 0x212143, 0x0},
+ { 0x13043, 0x0},
+ { 0x113043, 0x0},
+ { 0x213043, 0x0},
+ { 0x13143, 0x0},
+ { 0x113143, 0x0},
+ { 0x213143, 0x0},
+ { 0x80, 0x0},
+ { 0x100080, 0x0},
+ { 0x200080, 0x0},
+ { 0x1080, 0x0},
+ { 0x101080, 0x0},
+ { 0x201080, 0x0},
+ { 0x2080, 0x0},
+ { 0x102080, 0x0},
+ { 0x202080, 0x0},
+ { 0x3080, 0x0},
+ { 0x103080, 0x0},
+ { 0x203080, 0x0},
+ { 0x4080, 0x0},
+ { 0x104080, 0x0},
+ { 0x204080, 0x0},
+ { 0x5080, 0x0},
+ { 0x105080, 0x0},
+ { 0x205080, 0x0},
+ { 0x6080, 0x0},
+ { 0x106080, 0x0},
+ { 0x206080, 0x0},
+ { 0x7080, 0x0},
+ { 0x107080, 0x0},
+ { 0x207080, 0x0},
+ { 0x8080, 0x0},
+ { 0x108080, 0x0},
+ { 0x208080, 0x0},
+ { 0x9080, 0x0},
+ { 0x109080, 0x0},
+ { 0x209080, 0x0},
+ { 0x10080, 0x0},
+ { 0x110080, 0x0},
+ { 0x210080, 0x0},
+ { 0x10180, 0x0},
+ { 0x110180, 0x0},
+ { 0x210180, 0x0},
+ { 0x11080, 0x0},
+ { 0x111080, 0x0},
+ { 0x211080, 0x0},
+ { 0x11180, 0x0},
+ { 0x111180, 0x0},
+ { 0x211180, 0x0},
+ { 0x12080, 0x0},
+ { 0x112080, 0x0},
+ { 0x212080, 0x0},
+ { 0x12180, 0x0},
+ { 0x112180, 0x0},
+ { 0x212180, 0x0},
+ { 0x13080, 0x0},
+ { 0x113080, 0x0},
+ { 0x213080, 0x0},
+ { 0x13180, 0x0},
+ { 0x113180, 0x0},
+ { 0x213180, 0x0},
+ { 0x10081, 0x0},
+ { 0x110081, 0x0},
+ { 0x210081, 0x0},
+ { 0x10181, 0x0},
+ { 0x110181, 0x0},
+ { 0x210181, 0x0},
+ { 0x11081, 0x0},
+ { 0x111081, 0x0},
+ { 0x211081, 0x0},
+ { 0x11181, 0x0},
+ { 0x111181, 0x0},
+ { 0x211181, 0x0},
+ { 0x12081, 0x0},
+ { 0x112081, 0x0},
+ { 0x212081, 0x0},
+ { 0x12181, 0x0},
+ { 0x112181, 0x0},
+ { 0x212181, 0x0},
+ { 0x13081, 0x0},
+ { 0x113081, 0x0},
+ { 0x213081, 0x0},
+ { 0x13181, 0x0},
+ { 0x113181, 0x0},
+ { 0x213181, 0x0},
+ { 0x100d0, 0x0},
+ { 0x1100d0, 0x0},
+ { 0x2100d0, 0x0},
+ { 0x101d0, 0x0},
+ { 0x1101d0, 0x0},
+ { 0x2101d0, 0x0},
+ { 0x110d0, 0x0},
+ { 0x1110d0, 0x0},
+ { 0x2110d0, 0x0},
+ { 0x111d0, 0x0},
+ { 0x1111d0, 0x0},
+ { 0x2111d0, 0x0},
+ { 0x120d0, 0x0},
+ { 0x1120d0, 0x0},
+ { 0x2120d0, 0x0},
+ { 0x121d0, 0x0},
+ { 0x1121d0, 0x0},
+ { 0x2121d0, 0x0},
+ { 0x130d0, 0x0},
+ { 0x1130d0, 0x0},
+ { 0x2130d0, 0x0},
+ { 0x131d0, 0x0},
+ { 0x1131d0, 0x0},
+ { 0x2131d0, 0x0},
+ { 0x100d1, 0x0},
+ { 0x1100d1, 0x0},
+ { 0x2100d1, 0x0},
+ { 0x101d1, 0x0},
+ { 0x1101d1, 0x0},
+ { 0x2101d1, 0x0},
+ { 0x110d1, 0x0},
+ { 0x1110d1, 0x0},
+ { 0x2110d1, 0x0},
+ { 0x111d1, 0x0},
+ { 0x1111d1, 0x0},
+ { 0x2111d1, 0x0},
+ { 0x120d1, 0x0},
+ { 0x1120d1, 0x0},
+ { 0x2120d1, 0x0},
+ { 0x121d1, 0x0},
+ { 0x1121d1, 0x0},
+ { 0x2121d1, 0x0},
+ { 0x130d1, 0x0},
+ { 0x1130d1, 0x0},
+ { 0x2130d1, 0x0},
+ { 0x131d1, 0x0},
+ { 0x1131d1, 0x0},
+ { 0x2131d1, 0x0},
+ { 0x10068, 0x0},
+ { 0x10168, 0x0},
+ { 0x10268, 0x0},
+ { 0x10368, 0x0},
+ { 0x10468, 0x0},
+ { 0x10568, 0x0},
+ { 0x10668, 0x0},
+ { 0x10768, 0x0},
+ { 0x10868, 0x0},
+ { 0x11068, 0x0},
+ { 0x11168, 0x0},
+ { 0x11268, 0x0},
+ { 0x11368, 0x0},
+ { 0x11468, 0x0},
+ { 0x11568, 0x0},
+ { 0x11668, 0x0},
+ { 0x11768, 0x0},
+ { 0x11868, 0x0},
+ { 0x12068, 0x0},
+ { 0x12168, 0x0},
+ { 0x12268, 0x0},
+ { 0x12368, 0x0},
+ { 0x12468, 0x0},
+ { 0x12568, 0x0},
+ { 0x12668, 0x0},
+ { 0x12768, 0x0},
+ { 0x12868, 0x0},
+ { 0x13068, 0x0},
+ { 0x13168, 0x0},
+ { 0x13268, 0x0},
+ { 0x13368, 0x0},
+ { 0x13468, 0x0},
+ { 0x13568, 0x0},
+ { 0x13668, 0x0},
+ { 0x13768, 0x0},
+ { 0x13868, 0x0},
+ { 0x10069, 0x0},
+ { 0x10169, 0x0},
+ { 0x10269, 0x0},
+ { 0x10369, 0x0},
+ { 0x10469, 0x0},
+ { 0x10569, 0x0},
+ { 0x10669, 0x0},
+ { 0x10769, 0x0},
+ { 0x10869, 0x0},
+ { 0x11069, 0x0},
+ { 0x11169, 0x0},
+ { 0x11269, 0x0},
+ { 0x11369, 0x0},
+ { 0x11469, 0x0},
+ { 0x11569, 0x0},
+ { 0x11669, 0x0},
+ { 0x11769, 0x0},
+ { 0x11869, 0x0},
+ { 0x12069, 0x0},
+ { 0x12169, 0x0},
+ { 0x12269, 0x0},
+ { 0x12369, 0x0},
+ { 0x12469, 0x0},
+ { 0x12569, 0x0},
+ { 0x12669, 0x0},
+ { 0x12769, 0x0},
+ { 0x12869, 0x0},
+ { 0x13069, 0x0},
+ { 0x13169, 0x0},
+ { 0x13269, 0x0},
+ { 0x13369, 0x0},
+ { 0x13469, 0x0},
+ { 0x13569, 0x0},
+ { 0x13669, 0x0},
+ { 0x13769, 0x0},
+ { 0x13869, 0x0},
+ { 0x1008c, 0x0},
+ { 0x11008c, 0x0},
+ { 0x21008c, 0x0},
+ { 0x1018c, 0x0},
+ { 0x11018c, 0x0},
+ { 0x21018c, 0x0},
+ { 0x1108c, 0x0},
+ { 0x11108c, 0x0},
+ { 0x21108c, 0x0},
+ { 0x1118c, 0x0},
+ { 0x11118c, 0x0},
+ { 0x21118c, 0x0},
+ { 0x1208c, 0x0},
+ { 0x11208c, 0x0},
+ { 0x21208c, 0x0},
+ { 0x1218c, 0x0},
+ { 0x11218c, 0x0},
+ { 0x21218c, 0x0},
+ { 0x1308c, 0x0},
+ { 0x11308c, 0x0},
+ { 0x21308c, 0x0},
+ { 0x1318c, 0x0},
+ { 0x11318c, 0x0},
+ { 0x21318c, 0x0},
+ { 0x1008d, 0x0},
+ { 0x11008d, 0x0},
+ { 0x21008d, 0x0},
+ { 0x1018d, 0x0},
+ { 0x11018d, 0x0},
+ { 0x21018d, 0x0},
+ { 0x1108d, 0x0},
+ { 0x11108d, 0x0},
+ { 0x21108d, 0x0},
+ { 0x1118d, 0x0},
+ { 0x11118d, 0x0},
+ { 0x21118d, 0x0},
+ { 0x1208d, 0x0},
+ { 0x11208d, 0x0},
+ { 0x21208d, 0x0},
+ { 0x1218d, 0x0},
+ { 0x11218d, 0x0},
+ { 0x21218d, 0x0},
+ { 0x1308d, 0x0},
+ { 0x11308d, 0x0},
+ { 0x21308d, 0x0},
+ { 0x1318d, 0x0},
+ { 0x11318d, 0x0},
+ { 0x21318d, 0x0},
+ { 0x100c0, 0x0},
+ { 0x1100c0, 0x0},
+ { 0x2100c0, 0x0},
+ { 0x101c0, 0x0},
+ { 0x1101c0, 0x0},
+ { 0x2101c0, 0x0},
+ { 0x102c0, 0x0},
+ { 0x1102c0, 0x0},
+ { 0x2102c0, 0x0},
+ { 0x103c0, 0x0},
+ { 0x1103c0, 0x0},
+ { 0x2103c0, 0x0},
+ { 0x104c0, 0x0},
+ { 0x1104c0, 0x0},
+ { 0x2104c0, 0x0},
+ { 0x105c0, 0x0},
+ { 0x1105c0, 0x0},
+ { 0x2105c0, 0x0},
+ { 0x106c0, 0x0},
+ { 0x1106c0, 0x0},
+ { 0x2106c0, 0x0},
+ { 0x107c0, 0x0},
+ { 0x1107c0, 0x0},
+ { 0x2107c0, 0x0},
+ { 0x108c0, 0x0},
+ { 0x1108c0, 0x0},
+ { 0x2108c0, 0x0},
+ { 0x110c0, 0x0},
+ { 0x1110c0, 0x0},
+ { 0x2110c0, 0x0},
+ { 0x111c0, 0x0},
+ { 0x1111c0, 0x0},
+ { 0x2111c0, 0x0},
+ { 0x112c0, 0x0},
+ { 0x1112c0, 0x0},
+ { 0x2112c0, 0x0},
+ { 0x113c0, 0x0},
+ { 0x1113c0, 0x0},
+ { 0x2113c0, 0x0},
+ { 0x114c0, 0x0},
+ { 0x1114c0, 0x0},
+ { 0x2114c0, 0x0},
+ { 0x115c0, 0x0},
+ { 0x1115c0, 0x0},
+ { 0x2115c0, 0x0},
+ { 0x116c0, 0x0},
+ { 0x1116c0, 0x0},
+ { 0x2116c0, 0x0},
+ { 0x117c0, 0x0},
+ { 0x1117c0, 0x0},
+ { 0x2117c0, 0x0},
+ { 0x118c0, 0x0},
+ { 0x1118c0, 0x0},
+ { 0x2118c0, 0x0},
+ { 0x120c0, 0x0},
+ { 0x1120c0, 0x0},
+ { 0x2120c0, 0x0},
+ { 0x121c0, 0x0},
+ { 0x1121c0, 0x0},
+ { 0x2121c0, 0x0},
+ { 0x122c0, 0x0},
+ { 0x1122c0, 0x0},
+ { 0x2122c0, 0x0},
+ { 0x123c0, 0x0},
+ { 0x1123c0, 0x0},
+ { 0x2123c0, 0x0},
+ { 0x124c0, 0x0},
+ { 0x1124c0, 0x0},
+ { 0x2124c0, 0x0},
+ { 0x125c0, 0x0},
+ { 0x1125c0, 0x0},
+ { 0x2125c0, 0x0},
+ { 0x126c0, 0x0},
+ { 0x1126c0, 0x0},
+ { 0x2126c0, 0x0},
+ { 0x127c0, 0x0},
+ { 0x1127c0, 0x0},
+ { 0x2127c0, 0x0},
+ { 0x128c0, 0x0},
+ { 0x1128c0, 0x0},
+ { 0x2128c0, 0x0},
+ { 0x130c0, 0x0},
+ { 0x1130c0, 0x0},
+ { 0x2130c0, 0x0},
+ { 0x131c0, 0x0},
+ { 0x1131c0, 0x0},
+ { 0x2131c0, 0x0},
+ { 0x132c0, 0x0},
+ { 0x1132c0, 0x0},
+ { 0x2132c0, 0x0},
+ { 0x133c0, 0x0},
+ { 0x1133c0, 0x0},
+ { 0x2133c0, 0x0},
+ { 0x134c0, 0x0},
+ { 0x1134c0, 0x0},
+ { 0x2134c0, 0x0},
+ { 0x135c0, 0x0},
+ { 0x1135c0, 0x0},
+ { 0x2135c0, 0x0},
+ { 0x136c0, 0x0},
+ { 0x1136c0, 0x0},
+ { 0x2136c0, 0x0},
+ { 0x137c0, 0x0},
+ { 0x1137c0, 0x0},
+ { 0x2137c0, 0x0},
+ { 0x138c0, 0x0},
+ { 0x1138c0, 0x0},
+ { 0x2138c0, 0x0},
+ { 0x100c1, 0x0},
+ { 0x1100c1, 0x0},
+ { 0x2100c1, 0x0},
+ { 0x101c1, 0x0},
+ { 0x1101c1, 0x0},
+ { 0x2101c1, 0x0},
+ { 0x102c1, 0x0},
+ { 0x1102c1, 0x0},
+ { 0x2102c1, 0x0},
+ { 0x103c1, 0x0},
+ { 0x1103c1, 0x0},
+ { 0x2103c1, 0x0},
+ { 0x104c1, 0x0},
+ { 0x1104c1, 0x0},
+ { 0x2104c1, 0x0},
+ { 0x105c1, 0x0},
+ { 0x1105c1, 0x0},
+ { 0x2105c1, 0x0},
+ { 0x106c1, 0x0},
+ { 0x1106c1, 0x0},
+ { 0x2106c1, 0x0},
+ { 0x107c1, 0x0},
+ { 0x1107c1, 0x0},
+ { 0x2107c1, 0x0},
+ { 0x108c1, 0x0},
+ { 0x1108c1, 0x0},
+ { 0x2108c1, 0x0},
+ { 0x110c1, 0x0},
+ { 0x1110c1, 0x0},
+ { 0x2110c1, 0x0},
+ { 0x111c1, 0x0},
+ { 0x1111c1, 0x0},
+ { 0x2111c1, 0x0},
+ { 0x112c1, 0x0},
+ { 0x1112c1, 0x0},
+ { 0x2112c1, 0x0},
+ { 0x113c1, 0x0},
+ { 0x1113c1, 0x0},
+ { 0x2113c1, 0x0},
+ { 0x114c1, 0x0},
+ { 0x1114c1, 0x0},
+ { 0x2114c1, 0x0},
+ { 0x115c1, 0x0},
+ { 0x1115c1, 0x0},
+ { 0x2115c1, 0x0},
+ { 0x116c1, 0x0},
+ { 0x1116c1, 0x0},
+ { 0x2116c1, 0x0},
+ { 0x117c1, 0x0},
+ { 0x1117c1, 0x0},
+ { 0x2117c1, 0x0},
+ { 0x118c1, 0x0},
+ { 0x1118c1, 0x0},
+ { 0x2118c1, 0x0},
+ { 0x120c1, 0x0},
+ { 0x1120c1, 0x0},
+ { 0x2120c1, 0x0},
+ { 0x121c1, 0x0},
+ { 0x1121c1, 0x0},
+ { 0x2121c1, 0x0},
+ { 0x122c1, 0x0},
+ { 0x1122c1, 0x0},
+ { 0x2122c1, 0x0},
+ { 0x123c1, 0x0},
+ { 0x1123c1, 0x0},
+ { 0x2123c1, 0x0},
+ { 0x124c1, 0x0},
+ { 0x1124c1, 0x0},
+ { 0x2124c1, 0x0},
+ { 0x125c1, 0x0},
+ { 0x1125c1, 0x0},
+ { 0x2125c1, 0x0},
+ { 0x126c1, 0x0},
+ { 0x1126c1, 0x0},
+ { 0x2126c1, 0x0},
+ { 0x127c1, 0x0},
+ { 0x1127c1, 0x0},
+ { 0x2127c1, 0x0},
+ { 0x128c1, 0x0},
+ { 0x1128c1, 0x0},
+ { 0x2128c1, 0x0},
+ { 0x130c1, 0x0},
+ { 0x1130c1, 0x0},
+ { 0x2130c1, 0x0},
+ { 0x131c1, 0x0},
+ { 0x1131c1, 0x0},
+ { 0x2131c1, 0x0},
+ { 0x132c1, 0x0},
+ { 0x1132c1, 0x0},
+ { 0x2132c1, 0x0},
+ { 0x133c1, 0x0},
+ { 0x1133c1, 0x0},
+ { 0x2133c1, 0x0},
+ { 0x134c1, 0x0},
+ { 0x1134c1, 0x0},
+ { 0x2134c1, 0x0},
+ { 0x135c1, 0x0},
+ { 0x1135c1, 0x0},
+ { 0x2135c1, 0x0},
+ { 0x136c1, 0x0},
+ { 0x1136c1, 0x0},
+ { 0x2136c1, 0x0},
+ { 0x137c1, 0x0},
+ { 0x1137c1, 0x0},
+ { 0x2137c1, 0x0},
+ { 0x138c1, 0x0},
+ { 0x1138c1, 0x0},
+ { 0x2138c1, 0x0},
+ { 0x10020, 0x0},
+ { 0x110020, 0x0},
+ { 0x210020, 0x0},
+ { 0x11020, 0x0},
+ { 0x111020, 0x0},
+ { 0x211020, 0x0},
+ { 0x12020, 0x0},
+ { 0x112020, 0x0},
+ { 0x212020, 0x0},
+ { 0x13020, 0x0},
+ { 0x113020, 0x0},
+ { 0x213020, 0x0},
+ { 0x20072, 0x0},
+ { 0x20073, 0x0},
+ { 0x20074, 0x0},
+ { 0x100aa, 0x0},
+ { 0x110aa, 0x0},
+ { 0x120aa, 0x0},
+ { 0x130aa, 0x0},
+ { 0x20010, 0x0},
+ { 0x120010, 0x0},
+ { 0x220010, 0x0},
+ { 0x20011, 0x0},
+ { 0x120011, 0x0},
+ { 0x220011, 0x0},
+ { 0x100ae, 0x0},
+ { 0x1100ae, 0x0},
+ { 0x2100ae, 0x0},
+ { 0x100af, 0x0},
+ { 0x1100af, 0x0},
+ { 0x2100af, 0x0},
+ { 0x110ae, 0x0},
+ { 0x1110ae, 0x0},
+ { 0x2110ae, 0x0},
+ { 0x110af, 0x0},
+ { 0x1110af, 0x0},
+ { 0x2110af, 0x0},
+ { 0x120ae, 0x0},
+ { 0x1120ae, 0x0},
+ { 0x2120ae, 0x0},
+ { 0x120af, 0x0},
+ { 0x1120af, 0x0},
+ { 0x2120af, 0x0},
+ { 0x130ae, 0x0},
+ { 0x1130ae, 0x0},
+ { 0x2130ae, 0x0},
+ { 0x130af, 0x0},
+ { 0x1130af, 0x0},
+ { 0x2130af, 0x0},
+ { 0x20020, 0x0},
+ { 0x120020, 0x0},
+ { 0x220020, 0x0},
+ { 0x100a0, 0x0},
+ { 0x100a1, 0x0},
+ { 0x100a2, 0x0},
+ { 0x100a3, 0x0},
+ { 0x100a4, 0x0},
+ { 0x100a5, 0x0},
+ { 0x100a6, 0x0},
+ { 0x100a7, 0x0},
+ { 0x110a0, 0x0},
+ { 0x110a1, 0x0},
+ { 0x110a2, 0x0},
+ { 0x110a3, 0x0},
+ { 0x110a4, 0x0},
+ { 0x110a5, 0x0},
+ { 0x110a6, 0x0},
+ { 0x110a7, 0x0},
+ { 0x120a0, 0x0},
+ { 0x120a1, 0x0},
+ { 0x120a2, 0x0},
+ { 0x120a3, 0x0},
+ { 0x120a4, 0x0},
+ { 0x120a5, 0x0},
+ { 0x120a6, 0x0},
+ { 0x120a7, 0x0},
+ { 0x130a0, 0x0},
+ { 0x130a1, 0x0},
+ { 0x130a2, 0x0},
+ { 0x130a3, 0x0},
+ { 0x130a4, 0x0},
+ { 0x130a5, 0x0},
+ { 0x130a6, 0x0},
+ { 0x130a7, 0x0},
+ { 0x2007c, 0x0},
+ { 0x12007c, 0x0},
+ { 0x22007c, 0x0},
+ { 0x2007d, 0x0},
+ { 0x12007d, 0x0},
+ { 0x22007d, 0x0},
+ { 0x400fd, 0x0},
+ { 0x400c0, 0x0},
+ { 0x90201, 0x0},
+ { 0x190201, 0x0},
+ { 0x290201, 0x0},
+ { 0x90202, 0x0},
+ { 0x190202, 0x0},
+ { 0x290202, 0x0},
+ { 0x90203, 0x0},
+ { 0x190203, 0x0},
+ { 0x290203, 0x0},
+ { 0x90204, 0x0},
+ { 0x190204, 0x0},
+ { 0x290204, 0x0},
+ { 0x90205, 0x0},
+ { 0x190205, 0x0},
+ { 0x290205, 0x0},
+ { 0x90206, 0x0},
+ { 0x190206, 0x0},
+ { 0x290206, 0x0},
+ { 0x90207, 0x0},
+ { 0x190207, 0x0},
+ { 0x290207, 0x0},
+ { 0x90208, 0x0},
+ { 0x190208, 0x0},
+ { 0x290208, 0x0},
+ { 0x10062, 0x0},
+ { 0x10162, 0x0},
+ { 0x10262, 0x0},
+ { 0x10362, 0x0},
+ { 0x10462, 0x0},
+ { 0x10562, 0x0},
+ { 0x10662, 0x0},
+ { 0x10762, 0x0},
+ { 0x10862, 0x0},
+ { 0x11062, 0x0},
+ { 0x11162, 0x0},
+ { 0x11262, 0x0},
+ { 0x11362, 0x0},
+ { 0x11462, 0x0},
+ { 0x11562, 0x0},
+ { 0x11662, 0x0},
+ { 0x11762, 0x0},
+ { 0x11862, 0x0},
+ { 0x12062, 0x0},
+ { 0x12162, 0x0},
+ { 0x12262, 0x0},
+ { 0x12362, 0x0},
+ { 0x12462, 0x0},
+ { 0x12562, 0x0},
+ { 0x12662, 0x0},
+ { 0x12762, 0x0},
+ { 0x12862, 0x0},
+ { 0x13062, 0x0},
+ { 0x13162, 0x0},
+ { 0x13262, 0x0},
+ { 0x13362, 0x0},
+ { 0x13462, 0x0},
+ { 0x13562, 0x0},
+ { 0x13662, 0x0},
+ { 0x13762, 0x0},
+ { 0x13862, 0x0},
+ { 0x20077, 0x0},
+ { 0x10001, 0x0},
+ { 0x11001, 0x0},
+ { 0x12001, 0x0},
+ { 0x13001, 0x0},
+ { 0x10040, 0x0},
+ { 0x10140, 0x0},
+ { 0x10240, 0x0},
+ { 0x10340, 0x0},
+ { 0x10440, 0x0},
+ { 0x10540, 0x0},
+ { 0x10640, 0x0},
+ { 0x10740, 0x0},
+ { 0x10840, 0x0},
+ { 0x10030, 0x0},
+ { 0x10130, 0x0},
+ { 0x10230, 0x0},
+ { 0x10330, 0x0},
+ { 0x10430, 0x0},
+ { 0x10530, 0x0},
+ { 0x10630, 0x0},
+ { 0x10730, 0x0},
+ { 0x10830, 0x0},
+ { 0x11040, 0x0},
+ { 0x11140, 0x0},
+ { 0x11240, 0x0},
+ { 0x11340, 0x0},
+ { 0x11440, 0x0},
+ { 0x11540, 0x0},
+ { 0x11640, 0x0},
+ { 0x11740, 0x0},
+ { 0x11840, 0x0},
+ { 0x11030, 0x0},
+ { 0x11130, 0x0},
+ { 0x11230, 0x0},
+ { 0x11330, 0x0},
+ { 0x11430, 0x0},
+ { 0x11530, 0x0},
+ { 0x11630, 0x0},
+ { 0x11730, 0x0},
+ { 0x11830, 0x0},
+ { 0x12040, 0x0},
+ { 0x12140, 0x0},
+ { 0x12240, 0x0},
+ { 0x12340, 0x0},
+ { 0x12440, 0x0},
+ { 0x12540, 0x0},
+ { 0x12640, 0x0},
+ { 0x12740, 0x0},
+ { 0x12840, 0x0},
+ { 0x12030, 0x0},
+ { 0x12130, 0x0},
+ { 0x12230, 0x0},
+ { 0x12330, 0x0},
+ { 0x12430, 0x0},
+ { 0x12530, 0x0},
+ { 0x12630, 0x0},
+ { 0x12730, 0x0},
+ { 0x12830, 0x0},
+ { 0x13040, 0x0},
+ { 0x13140, 0x0},
+ { 0x13240, 0x0},
+ { 0x13340, 0x0},
+ { 0x13440, 0x0},
+ { 0x13540, 0x0},
+ { 0x13640, 0x0},
+ { 0x13740, 0x0},
+ { 0x13840, 0x0},
+ { 0x13030, 0x0},
+ { 0x13130, 0x0},
+ { 0x13230, 0x0},
+ { 0x13330, 0x0},
+ { 0x13430, 0x0},
+ { 0x13530, 0x0},
+ { 0x13630, 0x0},
+ { 0x13730, 0x0},
+ { 0x13830, 0x0},
+};
+
+/* P0 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x101},
+ {0x54003, 0x190},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x64},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x310},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+static struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400f, 0x100},
+ {0x54010, 0x1f7f},
+ {0x54012, 0x310},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x3},
+ {0x54032, 0xd400},
+ {0x54033, 0x312d},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0xd400},
+ {0x54039, 0x312d},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+static struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xf},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x630},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x630},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x630},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x630},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x630},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x630},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x630},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x630},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x630},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x630},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x630},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x630},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xa},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x2},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x900a4, 0x10},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x623},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x623},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x790},
+ {0x900a9, 0x11a},
+ {0x900aa, 0x8},
+ {0x900ab, 0x7aa},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x10},
+ {0x900ae, 0x7b2},
+ {0x900af, 0x2a},
+ {0x900b0, 0x0},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x0},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xc},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x0},
+ {0x90169, 0x8},
+ {0x9016a, 0x8},
+ {0x9016b, 0x448},
+ {0x9016c, 0x109},
+ {0x9016d, 0xf},
+ {0x9016e, 0x7c0},
+ {0x9016f, 0x109},
+ {0x90170, 0x0},
+ {0x90171, 0xe8},
+ {0x90172, 0x109},
+ {0x90173, 0x47},
+ {0x90174, 0x630},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0x618},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0xe0},
+ {0x9017b, 0x109},
+ {0x9017c, 0x0},
+ {0x9017d, 0x7c8},
+ {0x9017e, 0x109},
+ {0x9017f, 0x8},
+ {0x90180, 0x8140},
+ {0x90181, 0x10c},
+ {0x90182, 0x0},
+ {0x90183, 0x1},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x4},
+ {0x90187, 0x8},
+ {0x90188, 0x8},
+ {0x90189, 0x7c8},
+ {0x9018a, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2a},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x5d},
+ {0x2000c, 0xbb},
+ {0x2000d, 0x753},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x60},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x220010, 0x5a},
+ {0x220011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x12011, 0x1},
+ {0x12012, 0x1},
+ {0x12013, 0x180},
+ {0x12018, 0x1},
+ {0x12002, 0x6209},
+ {0x120b2, 0x1},
+ {0x121b4, 0x1},
+ {0x122b4, 0x1},
+ {0x123b4, 0x1},
+ {0x124b4, 0x1},
+ {0x125b4, 0x1},
+ {0x126b4, 0x1},
+ {0x127b4, 0x1},
+ {0x128b4, 0x1},
+ {0x13011, 0x1},
+ {0x13012, 0x1},
+ {0x13013, 0x180},
+ {0x13018, 0x1},
+ {0x13002, 0x6209},
+ {0x130b2, 0x1},
+ {0x131b4, 0x1},
+ {0x132b4, 0x1},
+ {0x133b4, 0x1},
+ {0x134b4, 0x1},
+ {0x135b4, 0x1},
+ {0x136b4, 0x1},
+ {0x137b4, 0x1},
+ {0x138b4, 0x1},
+ {0x2003a, 0x2},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1}
+};
+
+static struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info ucm_dram_timing_ff020008 = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
new file mode 100644
index 0000000..eabcc84
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ * Copyright 2020 Linaro
+ */
+
+#include <common.h>
+#include <env.h>
+#include <init.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int setup_fec(void)
+{
+ if (IS_ENABLED(CONFIG_FEC_MXC)) {
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 0x2000, 0);
+ }
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ if (IS_ENABLED(CONFIG_FEC_MXC)) {
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ }
+ return 0;
+}
+
+int board_init(void)
+{
+ if (IS_ENABLED(CONFIG_FEC_MXC))
+ setup_fec();
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+ env_set("board_name", "IOT-GATE-IMX8");
+ env_set("board_rev", "SBC-IOTMX8");
+ }
+
+ return 0;
+}
diff --git a/board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg b/board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg
new file mode 100644
index 0000000..b89092a
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM sd
+LOADER mkimage.flash.mkimage 0x7E1000
diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c
new file mode 100644
index 0000000..8f59245
--- /dev/null
+++ b/board/compulab/imx8mm-cl-iot-gate/spl.c
@@ -0,0 +1,187 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2020 Linaro
+ */
+
+#include <common.h>
+#include <command.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <image.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/arch/ddr.h>
+
+#include <dm/uclass.h>
+#include <dm/device.h>
+#include <dm/uclass-internal.h>
+#include <dm/device-internal.h>
+
+#include <power/pmic.h>
+#include <power/bd71837.h>
+
+#include "ddr/ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC2;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = IMX8MM_PAD_I2C2_SCL_I2C2_SCL | PC,
+ .gpio_mode = IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 | PC,
+ .gp = IMX_GPIO_NR(5, 16),
+ },
+ .sda = {
+ .i2c_mode = IMX8MM_PAD_I2C2_SDA_I2C2_SDA | PC,
+ .gpio_mode = IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 | PC,
+ .gp = IMX_GPIO_NR(5, 17),
+ },
+};
+
+static void spl_dram_init(void)
+{
+ spl_dram_init_compulab();
+}
+
+void spl_board_init(void)
+{
+ puts("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+static int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = pmic_get("pmic@4b", &dev);
+ if (ret == -ENODEV) {
+ puts("No pmic\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ /* decrease RESET key long push time from the default 10s to 10ms */
+ pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
+
+ /* unlock the PMIC regs */
+ pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
+
+ /* increase VDD_SOC to typical value 0.85v before first DRAM access */
+ pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
+
+ /* increase VDD_DRAM to 0.975v for 3Ghz DDR */
+ pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
+
+ /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */
+ pmic_reg_write(dev, BD718XX_4TH_NODVS_BUCK_VOLT, 0x28);
+
+ /* lock the PMIC regs */
+ pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ struct udevice *dev;
+ int ret;
+
+ arch_cpu_init();
+
+ board_early_init_f();
+
+ init_uart_clk(2);
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@30380000",
+ &dev);
+ if (ret < 0) {
+ printf("Failed to find clock node. Check device tree\n");
+ hang();
+ }
+
+ enable_tzc380();
+
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ power_init_board();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/dhelectronics/dh_stm32mp1/MAINTAINERS b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
index fd70131..9ce21c3 100644
--- a/board/dhelectronics/dh_stm32mp1/MAINTAINERS
+++ b/board/dhelectronics/dh_stm32mp1/MAINTAINERS
@@ -1,5 +1,6 @@
DH_STM32MP1_PDK2 BOARD
M: Marek Vasut <marex@denx.de>
+L: u-boot@dh-electronics.com
S: Maintained
F: arch/arm/dts/stm32mp15xx-dhcom*
F: board/dhelectronics/dh_stm32mp1/
diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c
index 49b12c4..ac1af71 100644
--- a/board/dhelectronics/dh_stm32mp1/board.c
+++ b/board/dhelectronics/dh_stm32mp1/board.c
@@ -86,6 +86,8 @@
#define KS_CCR_EEPROM BIT(9)
#define KS_BE0 BIT(12)
#define KS_BE1 BIT(13)
+#define KS_CIDER 0xC0
+#define CIDER_ID 0x8870
int setup_mac_address(void)
{
@@ -123,11 +125,18 @@
* is present. If EEPROM is present, it must contain valid
* MAC address.
*/
- u32 reg, ccr;
+ u32 reg, cider, ccr;
reg = fdt_get_base_address(gd->fdt_blob, off);
if (!reg)
goto out_set_ethaddr;
+ writew(KS_BE0 | KS_BE1 | KS_CIDER, reg + 2);
+ cider = readw(reg);
+ if ((cider & 0xfff0) != CIDER_ID) {
+ skip_eth1 = true;
+ goto out_set_ethaddr;
+ }
+
writew(KS_BE0 | KS_BE1 | KS_CCR, reg + 2);
ccr = readw(reg);
if (ccr & KS_CCR_EEPROM) {
diff --git a/board/emulation/common/qemu_capsule.c b/board/emulation/common/qemu_capsule.c
index 5cb461d..6b8a870 100644
--- a/board/emulation/common/qemu_capsule.c
+++ b/board/emulation/common/qemu_capsule.c
@@ -41,9 +41,3 @@
return 0;
}
-
-bool efi_capsule_auth_enabled(void)
-{
- return env_get("capsule_authentication_enabled") != NULL ?
- true : false;
-}
diff --git a/board/engicam/imx8mm/Kconfig b/board/engicam/imx8mm/Kconfig
new file mode 100644
index 0000000..ed68516
--- /dev/null
+++ b/board/engicam/imx8mm/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8MM_ICORE_MX8MM
+
+config SYS_BOARD
+ default "imx8mm"
+
+config SYS_VENDOR
+ default "engicam"
+
+config SYS_CONFIG_NAME
+ default "imx8mm_icore_mx8mm"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/engicam/imx8mm/MAINTAINERS b/board/engicam/imx8mm/MAINTAINERS
new file mode 100644
index 0000000..2e99a59
--- /dev/null
+++ b/board/engicam/imx8mm/MAINTAINERS
@@ -0,0 +1,13 @@
+i.Core-MX8M-Mini-CTOUCH2.0
+M: Jagan Teki <jagan@amarulasolutions.com>
+M: Matteo Lisi <matteo.lisi@engicam.com>
+S: Maintained
+F: configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+
+i.Core-MX8M-Mini-EDIMM2.2
+M: Jagan Teki <jagan@amarulasolutions.com>
+M: Matteo Lisi <matteo.lisi@engicam.com>
+S: Maintained
+F: board/engicam/imx8mm
+F: include/configs/imx8mm_icore_mx8mm.h
+F: configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
diff --git a/board/engicam/imx8mm/Makefile b/board/engicam/imx8mm/Makefile
new file mode 100644
index 0000000..3392d61
--- /dev/null
+++ b/board/engicam/imx8mm/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2020 Amarula Solutions(India)
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += icore_mx8mm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-y += lpddr4_timing.o
+endif
diff --git a/board/engicam/imx8mm/icore_mx8mm.c b/board/engicam/imx8mm/icore_mx8mm.c
new file mode 100644
index 0000000..4f7c699
--- /dev/null
+++ b/board/engicam/imx8mm/icore_mx8mm.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Amarula Solutions B.V.
+ * Copyright (C) 2016 Engicam S.r.l.
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+
+#include <linux/delay.h>
+
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if IS_ENABLED(CONFIG_FEC_MXC)
+
+#define FEC_RST_PAD IMX_GPIO_NR(3, 7)
+static iomux_v3_cfg_t const fec1_rst_pads[] = {
+ IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_fec(void)
+{
+ imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
+ ARRAY_SIZE(fec1_rst_pads));
+
+ gpio_request(FEC_RST_PAD, "fec1_rst");
+ gpio_direction_output(FEC_RST_PAD, 0);
+ udelay(500);
+ gpio_direction_output(FEC_RST_PAD, 1);
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ setup_iomux_fec();
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], 13, 0);
+
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ if (IS_ENABLED(CONFIG_FEC_MXC))
+ setup_fec();
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
diff --git a/board/engicam/imx8mm/lpddr4_timing.c b/board/engicam/imx8mm/lpddr4_timing.c
new file mode 100644
index 0000000..8212127
--- /dev/null
+++ b/board/engicam/imx8mm/lpddr4_timing.c
@@ -0,0 +1,1846 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ * Generated code from MX8M_DDR_tool
+ * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
+ */
+
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+struct dram_cfg_param ddr_ddrc_cfg[] = {
+ /* Initialize DDRC registers */
+ {0x3d400304, 0x1},
+ {0x3d400030, 0x1},
+ {0x3d400000, 0xa1080020},
+ {0x3d400020, 0x223},
+ {0x3d400024, 0x3a980},
+ {0x3d400064, 0x5b0087},
+ {0x3d4000d0, 0xc00305ba},
+ {0x3d4000d4, 0x940000},
+ {0x3d4000dc, 0xd4002d},
+ {0x3d4000e0, 0x210000},
+ {0x3d4000e8, 0x44004d},
+ {0x3d4000ec, 0x14004d},
+ {0x3d400100, 0x191f1920},
+ {0x3d400104, 0x60630},
+ {0x3d40010c, 0xb0b000},
+ {0x3d400110, 0xe04080e},
+ {0x3d400114, 0x2040c0c},
+ {0x3d400118, 0x1010007},
+ {0x3d40011c, 0x401},
+ {0x3d400130, 0x20600},
+ {0x3d400134, 0xc100002},
+ {0x3d400138, 0x8d},
+ {0x3d400144, 0x96004b},
+ {0x3d400180, 0x2ee0017},
+ {0x3d400184, 0x2605b8e},
+ {0x3d400188, 0x0},
+ {0x3d400190, 0x497820a},
+ {0x3d400194, 0x80303},
+ {0x3d4001b4, 0x170a},
+ {0x3d4001a0, 0xe0400018},
+ {0x3d4001a4, 0xdf00e4},
+ {0x3d4001a8, 0x80000000},
+ {0x3d4001b0, 0x11},
+ {0x3d4001c0, 0x1},
+ {0x3d4001c4, 0x0},
+ {0x3d4000f4, 0xc99},
+ {0x3d400108, 0x70e1617},
+ {0x3d400200, 0x1f},
+ {0x3d40020c, 0x0},
+ {0x3d400210, 0x1f1f},
+ {0x3d400204, 0x80808},
+ {0x3d400214, 0x7070707},
+ {0x3d400218, 0xf070707},
+ {0x3d400250, 0x29001701},
+ {0x3d400254, 0x2c},
+ {0x3d40025c, 0x4000030},
+ {0x3d400264, 0x900093e7},
+ {0x3d40026c, 0x2005574},
+ {0x3d400400, 0x111},
+ {0x3d400408, 0x72ff},
+ {0x3d400494, 0x2100e07},
+ {0x3d400498, 0x620096},
+ {0x3d40049c, 0x1100e07},
+ {0x3d4004a0, 0xc8012c},
+ {0x3d402020, 0x21},
+ {0x3d402024, 0x7d00},
+ {0x3d402050, 0x20d040},
+ {0x3d402064, 0xc0012},
+ {0x3d4020dc, 0x840000},
+ {0x3d4020e0, 0x310000},
+ {0x3d4020e8, 0x66004d},
+ {0x3d4020ec, 0x16004d},
+ {0x3d402100, 0xa050305},
+ {0x3d402104, 0x30407},
+ {0x3d402108, 0x203060b},
+ {0x3d40210c, 0x505000},
+ {0x3d402110, 0x2040202},
+ {0x3d402114, 0x2030202},
+ {0x3d402118, 0x1010004},
+ {0x3d40211c, 0x301},
+ {0x3d402130, 0x20300},
+ {0x3d402134, 0xa100002},
+ {0x3d402138, 0x13},
+ {0x3d402144, 0x14000a},
+ {0x3d402180, 0x640004},
+ {0x3d402190, 0x3818200},
+ {0x3d402194, 0x80303},
+ {0x3d4021b4, 0x100},
+ {0x3d403020, 0x21},
+ {0x3d403024, 0x1f40},
+ {0x3d403050, 0x20d040},
+ {0x3d403064, 0x30005},
+ {0x3d4030dc, 0x840000},
+ {0x3d4030e0, 0x310000},
+ {0x3d4030e8, 0x66004d},
+ {0x3d4030ec, 0x16004d},
+ {0x3d403100, 0xa020102},
+ {0x3d403104, 0x30404},
+ {0x3d403108, 0x203060b},
+ {0x3d40310c, 0x505000},
+ {0x3d403110, 0x2040202},
+ {0x3d403114, 0x2030202},
+ {0x3d403118, 0x1010004},
+ {0x3d40311c, 0x301},
+ {0x3d403130, 0x20300},
+ {0x3d403134, 0xa100002},
+ {0x3d403138, 0x5},
+ {0x3d403144, 0x50003},
+ {0x3d403180, 0x190004},
+ {0x3d403190, 0x3818200},
+ {0x3d403194, 0x80303},
+ {0x3d4031b4, 0x100},
+ {0x3d400028, 0x0},
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param ddr_ddrphy_cfg[] = {
+ {0x100a0, 0x0},
+ {0x100a1, 0x1},
+ {0x100a2, 0x2},
+ {0x100a3, 0x3},
+ {0x100a4, 0x4},
+ {0x100a5, 0x5},
+ {0x100a6, 0x6},
+ {0x100a7, 0x7},
+ {0x110a0, 0x0},
+ {0x110a1, 0x1},
+ {0x110a2, 0x3},
+ {0x110a3, 0x4},
+ {0x110a4, 0x5},
+ {0x110a5, 0x2},
+ {0x110a6, 0x7},
+ {0x110a7, 0x6},
+ {0x120a0, 0x0},
+ {0x120a1, 0x1},
+ {0x120a2, 0x3},
+ {0x120a3, 0x2},
+ {0x120a4, 0x5},
+ {0x120a5, 0x4},
+ {0x120a6, 0x7},
+ {0x120a7, 0x6},
+ {0x130a0, 0x0},
+ {0x130a1, 0x1},
+ {0x130a2, 0x2},
+ {0x130a3, 0x3},
+ {0x130a4, 0x4},
+ {0x130a5, 0x5},
+ {0x130a6, 0x6},
+ {0x130a7, 0x7},
+ {0x1005f, 0x1ff},
+ {0x1015f, 0x1ff},
+ {0x1105f, 0x1ff},
+ {0x1115f, 0x1ff},
+ {0x1205f, 0x1ff},
+ {0x1215f, 0x1ff},
+ {0x1305f, 0x1ff},
+ {0x1315f, 0x1ff},
+ {0x11005f, 0x1ff},
+ {0x11015f, 0x1ff},
+ {0x11105f, 0x1ff},
+ {0x11115f, 0x1ff},
+ {0x11205f, 0x1ff},
+ {0x11215f, 0x1ff},
+ {0x11305f, 0x1ff},
+ {0x11315f, 0x1ff},
+ {0x21005f, 0x1ff},
+ {0x21015f, 0x1ff},
+ {0x21105f, 0x1ff},
+ {0x21115f, 0x1ff},
+ {0x21205f, 0x1ff},
+ {0x21215f, 0x1ff},
+ {0x21305f, 0x1ff},
+ {0x21315f, 0x1ff},
+ {0x55, 0x1ff},
+ {0x1055, 0x1ff},
+ {0x2055, 0x1ff},
+ {0x3055, 0x1ff},
+ {0x4055, 0x1ff},
+ {0x5055, 0x1ff},
+ {0x6055, 0x1ff},
+ {0x7055, 0x1ff},
+ {0x8055, 0x1ff},
+ {0x9055, 0x1ff},
+ {0x200c5, 0x19},
+ {0x1200c5, 0x7},
+ {0x2200c5, 0x7},
+ {0x2002e, 0x2},
+ {0x12002e, 0x2},
+ {0x22002e, 0x2},
+ {0x90204, 0x0},
+ {0x190204, 0x0},
+ {0x290204, 0x0},
+ {0x20024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x120024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x220024, 0x1ab},
+ {0x2003a, 0x0},
+ {0x20056, 0x3},
+ {0x120056, 0xa},
+ {0x220056, 0xa},
+ {0x1004d, 0xe00},
+ {0x1014d, 0xe00},
+ {0x1104d, 0xe00},
+ {0x1114d, 0xe00},
+ {0x1204d, 0xe00},
+ {0x1214d, 0xe00},
+ {0x1304d, 0xe00},
+ {0x1314d, 0xe00},
+ {0x11004d, 0xe00},
+ {0x11014d, 0xe00},
+ {0x11104d, 0xe00},
+ {0x11114d, 0xe00},
+ {0x11204d, 0xe00},
+ {0x11214d, 0xe00},
+ {0x11304d, 0xe00},
+ {0x11314d, 0xe00},
+ {0x21004d, 0xe00},
+ {0x21014d, 0xe00},
+ {0x21104d, 0xe00},
+ {0x21114d, 0xe00},
+ {0x21204d, 0xe00},
+ {0x21214d, 0xe00},
+ {0x21304d, 0xe00},
+ {0x21314d, 0xe00},
+ {0x10049, 0xeba},
+ {0x10149, 0xeba},
+ {0x11049, 0xeba},
+ {0x11149, 0xeba},
+ {0x12049, 0xeba},
+ {0x12149, 0xeba},
+ {0x13049, 0xeba},
+ {0x13149, 0xeba},
+ {0x110049, 0xeba},
+ {0x110149, 0xeba},
+ {0x111049, 0xeba},
+ {0x111149, 0xeba},
+ {0x112049, 0xeba},
+ {0x112149, 0xeba},
+ {0x113049, 0xeba},
+ {0x113149, 0xeba},
+ {0x210049, 0xeba},
+ {0x210149, 0xeba},
+ {0x211049, 0xeba},
+ {0x211149, 0xeba},
+ {0x212049, 0xeba},
+ {0x212149, 0xeba},
+ {0x213049, 0xeba},
+ {0x213149, 0xeba},
+ {0x43, 0x63},
+ {0x1043, 0x63},
+ {0x2043, 0x63},
+ {0x3043, 0x63},
+ {0x4043, 0x63},
+ {0x5043, 0x63},
+ {0x6043, 0x63},
+ {0x7043, 0x63},
+ {0x8043, 0x63},
+ {0x9043, 0x63},
+ {0x20018, 0x3},
+ {0x20075, 0x4},
+ {0x20050, 0x0},
+ {0x20008, 0x2ee},
+ {0x120008, 0x64},
+ {0x220008, 0x19},
+ {0x20088, 0x9},
+ {0x200b2, 0xdc},
+ {0x10043, 0x5a1},
+ {0x10143, 0x5a1},
+ {0x11043, 0x5a1},
+ {0x11143, 0x5a1},
+ {0x12043, 0x5a1},
+ {0x12143, 0x5a1},
+ {0x13043, 0x5a1},
+ {0x13143, 0x5a1},
+ {0x1200b2, 0xdc},
+ {0x110043, 0x5a1},
+ {0x110143, 0x5a1},
+ {0x111043, 0x5a1},
+ {0x111143, 0x5a1},
+ {0x112043, 0x5a1},
+ {0x112143, 0x5a1},
+ {0x113043, 0x5a1},
+ {0x113143, 0x5a1},
+ {0x2200b2, 0xdc},
+ {0x210043, 0x5a1},
+ {0x210143, 0x5a1},
+ {0x211043, 0x5a1},
+ {0x211143, 0x5a1},
+ {0x212043, 0x5a1},
+ {0x212143, 0x5a1},
+ {0x213043, 0x5a1},
+ {0x213143, 0x5a1},
+ {0x200fa, 0x1},
+ {0x1200fa, 0x1},
+ {0x2200fa, 0x1},
+ {0x20019, 0x1},
+ {0x120019, 0x1},
+ {0x220019, 0x1},
+ {0x200f0, 0x660},
+ {0x200f1, 0x0},
+ {0x200f2, 0x4444},
+ {0x200f3, 0x8888},
+ {0x200f4, 0x5665},
+ {0x200f5, 0x0},
+ {0x200f6, 0x0},
+ {0x200f7, 0xf000},
+ {0x20025, 0x0},
+ {0x2002d, 0x0},
+ {0x12002d, 0x0},
+ {0x22002d, 0x0},
+ {0x200c7, 0x21},
+ {0x1200c7, 0x21},
+ {0x2200c7, 0x21},
+ {0x200ca, 0x24},
+ {0x1200ca, 0x24},
+ {0x2200ca, 0x24},
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x131f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x21},
+ {0x5401b, 0x4d44},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x14},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x21},
+ {0x54021, 0x4d44},
+ {0x54022, 0x4d00},
+ {0x54024, 0x14},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0xd400},
+ {0x54033, 0x212d},
+ {0x54034, 0x4400},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1400},
+ {0x54038, 0xd400},
+ {0x54039, 0x212d},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1400},
+ {0xd0000, 0x1},
+};
+
+/* P1 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp1_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x101},
+ {0x54003, 0x190},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P2 message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp2_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54002, 0x102},
+ {0x54003, 0x64},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x121f},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400d, 0x100},
+ {0x54012, 0x110},
+ {0x54019, 0x84},
+ {0x5401a, 0x31},
+ {0x5401b, 0x4d66},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x16},
+ {0x5401f, 0x84},
+ {0x54020, 0x31},
+ {0x54021, 0x4d66},
+ {0x54022, 0x4d00},
+ {0x54024, 0x16},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0x8400},
+ {0x54033, 0x3100},
+ {0x54034, 0x6600},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1600},
+ {0x54038, 0x8400},
+ {0x54039, 0x3100},
+ {0x5403a, 0x6600},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1600},
+ {0xd0000, 0x1},
+};
+
+/* P0 2D message block paremeter for training firmware */
+struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
+ {0xd0000, 0x0},
+ {0x54003, 0xbb8},
+ {0x54004, 0x2},
+ {0x54005, 0x2228},
+ {0x54006, 0x11},
+ {0x54008, 0x61},
+ {0x54009, 0xc8},
+ {0x5400b, 0x2},
+ {0x5400f, 0x100},
+ {0x54010, 0x1f7f},
+ {0x54012, 0x110},
+ {0x54019, 0x2dd4},
+ {0x5401a, 0x21},
+ {0x5401b, 0x4d44},
+ {0x5401c, 0x4d00},
+ {0x5401e, 0x14},
+ {0x5401f, 0x2dd4},
+ {0x54020, 0x21},
+ {0x54021, 0x4d44},
+ {0x54022, 0x4d00},
+ {0x54024, 0x14},
+ {0x5402b, 0x1000},
+ {0x5402c, 0x1},
+ {0x54032, 0xd400},
+ {0x54033, 0x212d},
+ {0x54034, 0x4400},
+ {0x54035, 0x4d},
+ {0x54036, 0x4d},
+ {0x54037, 0x1400},
+ {0x54038, 0xd400},
+ {0x54039, 0x212d},
+ {0x5403a, 0x4400},
+ {0x5403b, 0x4d},
+ {0x5403c, 0x4d},
+ {0x5403d, 0x1400},
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param ddr_phy_pie[] = {
+ {0xd0000, 0x0},
+ {0x90000, 0x10},
+ {0x90001, 0x400},
+ {0x90002, 0x10e},
+ {0x90003, 0x0},
+ {0x90004, 0x0},
+ {0x90005, 0x8},
+ {0x90029, 0xb},
+ {0x9002a, 0x480},
+ {0x9002b, 0x109},
+ {0x9002c, 0x8},
+ {0x9002d, 0x448},
+ {0x9002e, 0x139},
+ {0x9002f, 0x8},
+ {0x90030, 0x478},
+ {0x90031, 0x109},
+ {0x90032, 0x0},
+ {0x90033, 0xe8},
+ {0x90034, 0x109},
+ {0x90035, 0x2},
+ {0x90036, 0x10},
+ {0x90037, 0x139},
+ {0x90038, 0xf},
+ {0x90039, 0x7c0},
+ {0x9003a, 0x139},
+ {0x9003b, 0x44},
+ {0x9003c, 0x630},
+ {0x9003d, 0x159},
+ {0x9003e, 0x14f},
+ {0x9003f, 0x630},
+ {0x90040, 0x159},
+ {0x90041, 0x47},
+ {0x90042, 0x630},
+ {0x90043, 0x149},
+ {0x90044, 0x4f},
+ {0x90045, 0x630},
+ {0x90046, 0x179},
+ {0x90047, 0x8},
+ {0x90048, 0xe0},
+ {0x90049, 0x109},
+ {0x9004a, 0x0},
+ {0x9004b, 0x7c8},
+ {0x9004c, 0x109},
+ {0x9004d, 0x0},
+ {0x9004e, 0x1},
+ {0x9004f, 0x8},
+ {0x90050, 0x0},
+ {0x90051, 0x45a},
+ {0x90052, 0x9},
+ {0x90053, 0x0},
+ {0x90054, 0x448},
+ {0x90055, 0x109},
+ {0x90056, 0x40},
+ {0x90057, 0x630},
+ {0x90058, 0x179},
+ {0x90059, 0x1},
+ {0x9005a, 0x618},
+ {0x9005b, 0x109},
+ {0x9005c, 0x40c0},
+ {0x9005d, 0x630},
+ {0x9005e, 0x149},
+ {0x9005f, 0x8},
+ {0x90060, 0x4},
+ {0x90061, 0x48},
+ {0x90062, 0x4040},
+ {0x90063, 0x630},
+ {0x90064, 0x149},
+ {0x90065, 0x0},
+ {0x90066, 0x4},
+ {0x90067, 0x48},
+ {0x90068, 0x40},
+ {0x90069, 0x630},
+ {0x9006a, 0x149},
+ {0x9006b, 0x10},
+ {0x9006c, 0x4},
+ {0x9006d, 0x18},
+ {0x9006e, 0x0},
+ {0x9006f, 0x4},
+ {0x90070, 0x78},
+ {0x90071, 0x549},
+ {0x90072, 0x630},
+ {0x90073, 0x159},
+ {0x90074, 0xd49},
+ {0x90075, 0x630},
+ {0x90076, 0x159},
+ {0x90077, 0x94a},
+ {0x90078, 0x630},
+ {0x90079, 0x159},
+ {0x9007a, 0x441},
+ {0x9007b, 0x630},
+ {0x9007c, 0x149},
+ {0x9007d, 0x42},
+ {0x9007e, 0x630},
+ {0x9007f, 0x149},
+ {0x90080, 0x1},
+ {0x90081, 0x630},
+ {0x90082, 0x149},
+ {0x90083, 0x0},
+ {0x90084, 0xe0},
+ {0x90085, 0x109},
+ {0x90086, 0xa},
+ {0x90087, 0x10},
+ {0x90088, 0x109},
+ {0x90089, 0x9},
+ {0x9008a, 0x3c0},
+ {0x9008b, 0x149},
+ {0x9008c, 0x9},
+ {0x9008d, 0x3c0},
+ {0x9008e, 0x159},
+ {0x9008f, 0x18},
+ {0x90090, 0x10},
+ {0x90091, 0x109},
+ {0x90092, 0x0},
+ {0x90093, 0x3c0},
+ {0x90094, 0x109},
+ {0x90095, 0x18},
+ {0x90096, 0x4},
+ {0x90097, 0x48},
+ {0x90098, 0x18},
+ {0x90099, 0x4},
+ {0x9009a, 0x58},
+ {0x9009b, 0xa},
+ {0x9009c, 0x10},
+ {0x9009d, 0x109},
+ {0x9009e, 0x2},
+ {0x9009f, 0x10},
+ {0x900a0, 0x109},
+ {0x900a1, 0x5},
+ {0x900a2, 0x7c0},
+ {0x900a3, 0x109},
+ {0x900a4, 0x10},
+ {0x900a5, 0x10},
+ {0x900a6, 0x109},
+ {0x40000, 0x811},
+ {0x40020, 0x880},
+ {0x40040, 0x0},
+ {0x40060, 0x0},
+ {0x40001, 0x4008},
+ {0x40021, 0x83},
+ {0x40041, 0x4f},
+ {0x40061, 0x0},
+ {0x40002, 0x4040},
+ {0x40022, 0x83},
+ {0x40042, 0x51},
+ {0x40062, 0x0},
+ {0x40003, 0x811},
+ {0x40023, 0x880},
+ {0x40043, 0x0},
+ {0x40063, 0x0},
+ {0x40004, 0x720},
+ {0x40024, 0xf},
+ {0x40044, 0x1740},
+ {0x40064, 0x0},
+ {0x40005, 0x16},
+ {0x40025, 0x83},
+ {0x40045, 0x4b},
+ {0x40065, 0x0},
+ {0x40006, 0x716},
+ {0x40026, 0xf},
+ {0x40046, 0x2001},
+ {0x40066, 0x0},
+ {0x40007, 0x716},
+ {0x40027, 0xf},
+ {0x40047, 0x2800},
+ {0x40067, 0x0},
+ {0x40008, 0x716},
+ {0x40028, 0xf},
+ {0x40048, 0xf00},
+ {0x40068, 0x0},
+ {0x40009, 0x720},
+ {0x40029, 0xf},
+ {0x40049, 0x1400},
+ {0x40069, 0x0},
+ {0x4000a, 0xe08},
+ {0x4002a, 0xc15},
+ {0x4004a, 0x0},
+ {0x4006a, 0x0},
+ {0x4000b, 0x623},
+ {0x4002b, 0x15},
+ {0x4004b, 0x0},
+ {0x4006b, 0x0},
+ {0x4000c, 0x4028},
+ {0x4002c, 0x80},
+ {0x4004c, 0x0},
+ {0x4006c, 0x0},
+ {0x4000d, 0xe08},
+ {0x4002d, 0xc1a},
+ {0x4004d, 0x0},
+ {0x4006d, 0x0},
+ {0x4000e, 0x623},
+ {0x4002e, 0x1a},
+ {0x4004e, 0x0},
+ {0x4006e, 0x0},
+ {0x4000f, 0x4040},
+ {0x4002f, 0x80},
+ {0x4004f, 0x0},
+ {0x4006f, 0x0},
+ {0x40010, 0x2604},
+ {0x40030, 0x15},
+ {0x40050, 0x0},
+ {0x40070, 0x0},
+ {0x40011, 0x708},
+ {0x40031, 0x5},
+ {0x40051, 0x0},
+ {0x40071, 0x2002},
+ {0x40012, 0x8},
+ {0x40032, 0x80},
+ {0x40052, 0x0},
+ {0x40072, 0x0},
+ {0x40013, 0x2604},
+ {0x40033, 0x1a},
+ {0x40053, 0x0},
+ {0x40073, 0x0},
+ {0x40014, 0x708},
+ {0x40034, 0xa},
+ {0x40054, 0x0},
+ {0x40074, 0x2002},
+ {0x40015, 0x4040},
+ {0x40035, 0x80},
+ {0x40055, 0x0},
+ {0x40075, 0x0},
+ {0x40016, 0x60a},
+ {0x40036, 0x15},
+ {0x40056, 0x1200},
+ {0x40076, 0x0},
+ {0x40017, 0x61a},
+ {0x40037, 0x15},
+ {0x40057, 0x1300},
+ {0x40077, 0x0},
+ {0x40018, 0x60a},
+ {0x40038, 0x1a},
+ {0x40058, 0x1200},
+ {0x40078, 0x0},
+ {0x40019, 0x642},
+ {0x40039, 0x1a},
+ {0x40059, 0x1300},
+ {0x40079, 0x0},
+ {0x4001a, 0x4808},
+ {0x4003a, 0x880},
+ {0x4005a, 0x0},
+ {0x4007a, 0x0},
+ {0x900a7, 0x0},
+ {0x900a8, 0x790},
+ {0x900a9, 0x11a},
+ {0x900aa, 0x8},
+ {0x900ab, 0x7aa},
+ {0x900ac, 0x2a},
+ {0x900ad, 0x10},
+ {0x900ae, 0x7b2},
+ {0x900af, 0x2a},
+ {0x900b0, 0x0},
+ {0x900b1, 0x7c8},
+ {0x900b2, 0x109},
+ {0x900b3, 0x10},
+ {0x900b4, 0x2a8},
+ {0x900b5, 0x129},
+ {0x900b6, 0x8},
+ {0x900b7, 0x370},
+ {0x900b8, 0x129},
+ {0x900b9, 0xa},
+ {0x900ba, 0x3c8},
+ {0x900bb, 0x1a9},
+ {0x900bc, 0xc},
+ {0x900bd, 0x408},
+ {0x900be, 0x199},
+ {0x900bf, 0x14},
+ {0x900c0, 0x790},
+ {0x900c1, 0x11a},
+ {0x900c2, 0x8},
+ {0x900c3, 0x4},
+ {0x900c4, 0x18},
+ {0x900c5, 0xe},
+ {0x900c6, 0x408},
+ {0x900c7, 0x199},
+ {0x900c8, 0x8},
+ {0x900c9, 0x8568},
+ {0x900ca, 0x108},
+ {0x900cb, 0x18},
+ {0x900cc, 0x790},
+ {0x900cd, 0x16a},
+ {0x900ce, 0x8},
+ {0x900cf, 0x1d8},
+ {0x900d0, 0x169},
+ {0x900d1, 0x10},
+ {0x900d2, 0x8558},
+ {0x900d3, 0x168},
+ {0x900d4, 0x70},
+ {0x900d5, 0x788},
+ {0x900d6, 0x16a},
+ {0x900d7, 0x1ff8},
+ {0x900d8, 0x85a8},
+ {0x900d9, 0x1e8},
+ {0x900da, 0x50},
+ {0x900db, 0x798},
+ {0x900dc, 0x16a},
+ {0x900dd, 0x60},
+ {0x900de, 0x7a0},
+ {0x900df, 0x16a},
+ {0x900e0, 0x8},
+ {0x900e1, 0x8310},
+ {0x900e2, 0x168},
+ {0x900e3, 0x8},
+ {0x900e4, 0xa310},
+ {0x900e5, 0x168},
+ {0x900e6, 0xa},
+ {0x900e7, 0x408},
+ {0x900e8, 0x169},
+ {0x900e9, 0x6e},
+ {0x900ea, 0x0},
+ {0x900eb, 0x68},
+ {0x900ec, 0x0},
+ {0x900ed, 0x408},
+ {0x900ee, 0x169},
+ {0x900ef, 0x0},
+ {0x900f0, 0x8310},
+ {0x900f1, 0x168},
+ {0x900f2, 0x0},
+ {0x900f3, 0xa310},
+ {0x900f4, 0x168},
+ {0x900f5, 0x1ff8},
+ {0x900f6, 0x85a8},
+ {0x900f7, 0x1e8},
+ {0x900f8, 0x68},
+ {0x900f9, 0x798},
+ {0x900fa, 0x16a},
+ {0x900fb, 0x78},
+ {0x900fc, 0x7a0},
+ {0x900fd, 0x16a},
+ {0x900fe, 0x68},
+ {0x900ff, 0x790},
+ {0x90100, 0x16a},
+ {0x90101, 0x8},
+ {0x90102, 0x8b10},
+ {0x90103, 0x168},
+ {0x90104, 0x8},
+ {0x90105, 0xab10},
+ {0x90106, 0x168},
+ {0x90107, 0xa},
+ {0x90108, 0x408},
+ {0x90109, 0x169},
+ {0x9010a, 0x58},
+ {0x9010b, 0x0},
+ {0x9010c, 0x68},
+ {0x9010d, 0x0},
+ {0x9010e, 0x408},
+ {0x9010f, 0x169},
+ {0x90110, 0x0},
+ {0x90111, 0x8b10},
+ {0x90112, 0x168},
+ {0x90113, 0x0},
+ {0x90114, 0xab10},
+ {0x90115, 0x168},
+ {0x90116, 0x0},
+ {0x90117, 0x1d8},
+ {0x90118, 0x169},
+ {0x90119, 0x80},
+ {0x9011a, 0x790},
+ {0x9011b, 0x16a},
+ {0x9011c, 0x18},
+ {0x9011d, 0x7aa},
+ {0x9011e, 0x6a},
+ {0x9011f, 0xa},
+ {0x90120, 0x0},
+ {0x90121, 0x1e9},
+ {0x90122, 0x8},
+ {0x90123, 0x8080},
+ {0x90124, 0x108},
+ {0x90125, 0xf},
+ {0x90126, 0x408},
+ {0x90127, 0x169},
+ {0x90128, 0xc},
+ {0x90129, 0x0},
+ {0x9012a, 0x68},
+ {0x9012b, 0x9},
+ {0x9012c, 0x0},
+ {0x9012d, 0x1a9},
+ {0x9012e, 0x0},
+ {0x9012f, 0x408},
+ {0x90130, 0x169},
+ {0x90131, 0x0},
+ {0x90132, 0x8080},
+ {0x90133, 0x108},
+ {0x90134, 0x8},
+ {0x90135, 0x7aa},
+ {0x90136, 0x6a},
+ {0x90137, 0x0},
+ {0x90138, 0x8568},
+ {0x90139, 0x108},
+ {0x9013a, 0xb7},
+ {0x9013b, 0x790},
+ {0x9013c, 0x16a},
+ {0x9013d, 0x1f},
+ {0x9013e, 0x0},
+ {0x9013f, 0x68},
+ {0x90140, 0x8},
+ {0x90141, 0x8558},
+ {0x90142, 0x168},
+ {0x90143, 0xf},
+ {0x90144, 0x408},
+ {0x90145, 0x169},
+ {0x90146, 0xc},
+ {0x90147, 0x0},
+ {0x90148, 0x68},
+ {0x90149, 0x0},
+ {0x9014a, 0x408},
+ {0x9014b, 0x169},
+ {0x9014c, 0x0},
+ {0x9014d, 0x8558},
+ {0x9014e, 0x168},
+ {0x9014f, 0x8},
+ {0x90150, 0x3c8},
+ {0x90151, 0x1a9},
+ {0x90152, 0x3},
+ {0x90153, 0x370},
+ {0x90154, 0x129},
+ {0x90155, 0x20},
+ {0x90156, 0x2aa},
+ {0x90157, 0x9},
+ {0x90158, 0x0},
+ {0x90159, 0x400},
+ {0x9015a, 0x10e},
+ {0x9015b, 0x8},
+ {0x9015c, 0xe8},
+ {0x9015d, 0x109},
+ {0x9015e, 0x0},
+ {0x9015f, 0x8140},
+ {0x90160, 0x10c},
+ {0x90161, 0x10},
+ {0x90162, 0x8138},
+ {0x90163, 0x10c},
+ {0x90164, 0x8},
+ {0x90165, 0x7c8},
+ {0x90166, 0x101},
+ {0x90167, 0x8},
+ {0x90168, 0x0},
+ {0x90169, 0x8},
+ {0x9016a, 0x8},
+ {0x9016b, 0x448},
+ {0x9016c, 0x109},
+ {0x9016d, 0xf},
+ {0x9016e, 0x7c0},
+ {0x9016f, 0x109},
+ {0x90170, 0x0},
+ {0x90171, 0xe8},
+ {0x90172, 0x109},
+ {0x90173, 0x47},
+ {0x90174, 0x630},
+ {0x90175, 0x109},
+ {0x90176, 0x8},
+ {0x90177, 0x618},
+ {0x90178, 0x109},
+ {0x90179, 0x8},
+ {0x9017a, 0xe0},
+ {0x9017b, 0x109},
+ {0x9017c, 0x0},
+ {0x9017d, 0x7c8},
+ {0x9017e, 0x109},
+ {0x9017f, 0x8},
+ {0x90180, 0x8140},
+ {0x90181, 0x10c},
+ {0x90182, 0x0},
+ {0x90183, 0x1},
+ {0x90184, 0x8},
+ {0x90185, 0x8},
+ {0x90186, 0x4},
+ {0x90187, 0x8},
+ {0x90188, 0x8},
+ {0x90189, 0x7c8},
+ {0x9018a, 0x101},
+ {0x90006, 0x0},
+ {0x90007, 0x0},
+ {0x90008, 0x8},
+ {0x90009, 0x0},
+ {0x9000a, 0x0},
+ {0x9000b, 0x0},
+ {0xd00e7, 0x400},
+ {0x90017, 0x0},
+ {0x9001f, 0x2a},
+ {0x90026, 0x6a},
+ {0x400d0, 0x0},
+ {0x400d1, 0x101},
+ {0x400d2, 0x105},
+ {0x400d3, 0x107},
+ {0x400d4, 0x10f},
+ {0x400d5, 0x202},
+ {0x400d6, 0x20a},
+ {0x400d7, 0x20b},
+ {0x2003a, 0x2},
+ {0x2000b, 0x5d},
+ {0x2000c, 0xbb},
+ {0x2000d, 0x753},
+ {0x2000e, 0x2c},
+ {0x12000b, 0xc},
+ {0x12000c, 0x19},
+ {0x12000d, 0xfa},
+ {0x12000e, 0x10},
+ {0x22000b, 0x3},
+ {0x22000c, 0x6},
+ {0x22000d, 0x3e},
+ {0x22000e, 0x10},
+ {0x9000c, 0x0},
+ {0x9000d, 0x173},
+ {0x9000e, 0x60},
+ {0x9000f, 0x6110},
+ {0x90010, 0x2152},
+ {0x90011, 0xdfbd},
+ {0x90012, 0x60},
+ {0x90013, 0x6152},
+ {0x20010, 0x5a},
+ {0x20011, 0x3},
+ {0x120010, 0x5a},
+ {0x120011, 0x3},
+ {0x220010, 0x5a},
+ {0x220011, 0x3},
+ {0x40080, 0xe0},
+ {0x40081, 0x12},
+ {0x40082, 0xe0},
+ {0x40083, 0x12},
+ {0x40084, 0xe0},
+ {0x40085, 0x12},
+ {0x140080, 0xe0},
+ {0x140081, 0x12},
+ {0x140082, 0xe0},
+ {0x140083, 0x12},
+ {0x140084, 0xe0},
+ {0x140085, 0x12},
+ {0x240080, 0xe0},
+ {0x240081, 0x12},
+ {0x240082, 0xe0},
+ {0x240083, 0x12},
+ {0x240084, 0xe0},
+ {0x240085, 0x12},
+ {0x400fd, 0xf},
+ {0x10011, 0x1},
+ {0x10012, 0x1},
+ {0x10013, 0x180},
+ {0x10018, 0x1},
+ {0x10002, 0x6209},
+ {0x100b2, 0x1},
+ {0x101b4, 0x1},
+ {0x102b4, 0x1},
+ {0x103b4, 0x1},
+ {0x104b4, 0x1},
+ {0x105b4, 0x1},
+ {0x106b4, 0x1},
+ {0x107b4, 0x1},
+ {0x108b4, 0x1},
+ {0x11011, 0x1},
+ {0x11012, 0x1},
+ {0x11013, 0x180},
+ {0x11018, 0x1},
+ {0x11002, 0x6209},
+ {0x110b2, 0x1},
+ {0x111b4, 0x1},
+ {0x112b4, 0x1},
+ {0x113b4, 0x1},
+ {0x114b4, 0x1},
+ {0x115b4, 0x1},
+ {0x116b4, 0x1},
+ {0x117b4, 0x1},
+ {0x118b4, 0x1},
+ {0x12011, 0x1},
+ {0x12012, 0x1},
+ {0x12013, 0x180},
+ {0x12018, 0x1},
+ {0x12002, 0x6209},
+ {0x120b2, 0x1},
+ {0x121b4, 0x1},
+ {0x122b4, 0x1},
+ {0x123b4, 0x1},
+ {0x124b4, 0x1},
+ {0x125b4, 0x1},
+ {0x126b4, 0x1},
+ {0x127b4, 0x1},
+ {0x128b4, 0x1},
+ {0x13011, 0x1},
+ {0x13012, 0x1},
+ {0x13013, 0x180},
+ {0x13018, 0x1},
+ {0x13002, 0x6209},
+ {0x130b2, 0x1},
+ {0x131b4, 0x1},
+ {0x132b4, 0x1},
+ {0x133b4, 0x1},
+ {0x134b4, 0x1},
+ {0x135b4, 0x1},
+ {0x136b4, 0x1},
+ {0x137b4, 0x1},
+ {0x138b4, 0x1},
+ {0x2003a, 0x2},
+ {0xc0080, 0x2},
+ {0xd0000, 0x1}
+};
+
+struct dram_fsp_msg ddr_dram_fsp_msg[] = {
+ {
+ /* P0 3000mts 1D */
+ .drate = 3000,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
+ },
+ {
+ /* P2 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = ddr_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
+ },
+ {
+ /* P0 3000mts 2D */
+ .drate = 3000,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = ddr_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
+ },
+};
+
+/* ddr timing config params */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = ddr_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
+ .ddrphy_cfg = ddr_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
+ .fsp_msg = ddr_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = ddr_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+ .fsp_table = { 3000, 400, 100, },
+};
diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c
new file mode 100644
index 0000000..f9be769
--- /dev/null
+++ b/board/engicam/imx8mm/spl.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Engicam s.r.l.
+ * Copyright (C) 2020 Amarula Solutions(India)
+ * Author: Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
+#include <spl.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx8mm_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/arch/ddr.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int spl_board_boot_device(enum boot_device boot_dev_spl)
+{
+ switch (boot_dev_spl) {
+ case SD1_BOOT:
+ case SD2_BOOT:
+ case MMC2_BOOT:
+ return BOOT_DEVICE_MMC1;
+ case SD3_BOOT:
+ case MMC3_BOOT:
+ return BOOT_DEVICE_MMC2;
+ default:
+ return BOOT_DEVICE_NONE;
+ }
+}
+
+static void spl_dram_init(void)
+{
+ ddr_init(&dram_timing);
+}
+
+void spl_board_init(void)
+{
+ debug("Normal Boot\n");
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* Just empty function now - can't decide what to choose */
+ debug("%s: %s\n", __func__, name);
+
+ return 0;
+}
+#endif
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MM_PAD_UART2_RXD_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MM_PAD_UART2_TXD_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ arch_cpu_init();
+
+ init_uart_clk(1);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_early_init();
+ if (ret) {
+ debug("spl_early_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/freescale/imx8qm_mek/README b/board/freescale/imx8qm_mek/README
index a187ad8..570ed7e 100644
--- a/board/freescale/imx8qm_mek/README
+++ b/board/freescale/imx8qm_mek/README
@@ -17,8 +17,12 @@
$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
$ make PLAT=imx8qm bl31
+And copy the resulting bl31.bin to u-boot directory:
+
+$ cp build/imx8qm/release/bl31.bin path/to/u-boot/
+
Get scfw_tcm.bin and ahab-container.img
-==============================
+=======================================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
$ chmod +x imx-sc-firmware-1.1.bin
@@ -27,15 +31,11 @@
$ chmod +x firmware-imx-8.0.bin
$ ./firmware-imx-8.0.bin
-Copy the following binaries to U-Boot folder:
-$ cp imx-atf/build/imx8qm/release/bl31.bin .
-$ cp u-boot/u-boot.bin .
+And copy the following firmwares to U-Boot folder:
-Copy the following firmwares U-Boot folder :
-
-$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
-$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin .
+* `imx-sc-firmware-1.1/mx8qm-mek-scfw-tcm.bin`
+* `firmware-imx-8.0/firmware/seco/mx8qm-ahab-container.img`
Build U-Boot
============
@@ -51,4 +51,4 @@
Boot
====
-Set Boot switch SW2: 1100.
+Set Boot switch SW2: 001100.
diff --git a/board/freescale/t102xrdb/MAINTAINERS b/board/freescale/t102xrdb/MAINTAINERS
index 6c24f77..ebb17b8 100644
--- a/board/freescale/t102xrdb/MAINTAINERS
+++ b/board/freescale/t102xrdb/MAINTAINERS
@@ -12,4 +12,3 @@
F: configs/T1023RDB_NAND_defconfig
F: configs/T1023RDB_SDCARD_defconfig
F: configs/T1023RDB_SPIFLASH_defconfig
-F: configs/T1023RDB_SECURE_BOOT_defconfig
diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS
index 8e32679..4e82f7f 100644
--- a/board/freescale/t104xrdb/MAINTAINERS
+++ b/board/freescale/t104xrdb/MAINTAINERS
@@ -25,14 +25,7 @@
F: configs/T1042D4RDB_SDCARD_defconfig
F: configs/T1042RDB_PI_SDCARD_defconfig
-T1040RDB_SECURE_BOOT BOARD
+T1042D4RDB_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
-F: configs/T1040RDB_SECURE_BOOT_defconfig
-F: configs/T1040D4RDB_SECURE_BOOT_defconfig
-F: configs/T1042RDB_SECURE_BOOT_defconfig
F: configs/T1042D4RDB_SECURE_BOOT_defconfig
-
-M: Sumit Garg <sumit.garg@nxp.com>
-S: Maintained
-F: configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
diff --git a/board/gateworks/gw_ventana/eeprom.c b/board/gateworks/gw_ventana/eeprom.c
index a5a151d..b9862c7 100644
--- a/board/gateworks/gw_ventana/eeprom.c
+++ b/board/gateworks/gw_ventana/eeprom.c
@@ -42,6 +42,7 @@
}
/* read eeprom config section */
+ mdelay(10);
if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
puts("EEPROM: Failed to read EEPROM\n");
return GW_UNKNOWN;
diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c
index c11fc40..7fcebba 100644
--- a/board/ge/bx50v3/bx50v3.c
+++ b/board/ge/bx50v3/bx50v3.c
@@ -31,6 +31,7 @@
#include <asm/arch/sys_proto.h>
#include <power/regulator.h>
#include <power/da9063_pmic.h>
+#include <power/pmic.h>
#include <input.h>
#include <pwm.h>
#include <version.h>
@@ -432,6 +433,29 @@
};
#endif
+
+/*
+ * The SoM used by these boards has XTAL not connected despite datasheet
+ * suggesting connecting unused XTAL pins to ground. Without explicitly
+ * clearing the CRYSTAL bit the system runs unstable and sometimes reboots
+ * unexpectedly.
+ */
+static void pmic_crystal_fix(void)
+{
+ struct udevice *pmic;
+ static const uint EN_32K_CRYSTAL = (1 << 3);
+
+ if (pmic_get("pmic@58", &pmic)) {
+ puts("failed to get device for PMIC\n");
+ return;
+ }
+
+ if (pmic_clrsetbits(pmic, DA9063_REG_EN_32K, EN_32K_CRYSTAL, 0) < 0) {
+ puts("failed to clear CRYSTAL bit\n");
+ return;
+ }
+}
+
void pmic_init(void)
{
struct udevice *reg;
@@ -445,6 +469,8 @@
"bperi",
};
+ pmic_crystal_fix();
+
for (i = 0; i < ARRAY_SIZE(bucks); i++) {
ret = regulator_get_by_devname(bucks[i], ®);
if (reg < 0) {
diff --git a/board/nokia/rx51/rx51.c b/board/nokia/rx51/rx51.c
index 7bd5fbd..fd3cec8 100644
--- a/board/nokia/rx51/rx51.c
+++ b/board/nokia/rx51/rx51.c
@@ -26,6 +26,7 @@
#include <env.h>
#include <init.h>
#include <watchdog.h>
+#include <wdt.h>
#include <malloc.h>
#include <twl4030.h>
#include <i2c.h>
@@ -487,20 +488,20 @@
static unsigned long int twl_i2c_lock;
/*
- * Routine: hw_watchdog_reset
+ * Routine: rx51_watchdog_reset
* Description: Reset timeout of twl4030 watchdog.
*/
-void hw_watchdog_reset(void)
+static int rx51_watchdog_reset(struct udevice *dev)
{
u8 timeout = 0;
/* do not reset watchdog too often - max every 4s */
if (get_timer(twl_wd_time) < 4 * CONFIG_SYS_HZ)
- return;
+ return 0;
/* localy lock twl4030 i2c bus */
if (test_and_set_bit(0, &twl_i2c_lock))
- return;
+ return 0;
/* read actual watchdog timeout */
twl4030_i2c_read_u8(TWL4030_CHIP_PM_RECEIVER,
@@ -517,8 +518,32 @@
/* localy unlock twl4030 i2c bus */
test_and_clear_bit(0, &twl_i2c_lock);
+
+ return 0;
+}
+
+static int rx51_watchdog_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ return 0;
}
+static int rx51_watchdog_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static const struct wdt_ops rx51_watchdog_ops = {
+ .start = rx51_watchdog_start,
+ .reset = rx51_watchdog_reset,
+};
+
+U_BOOT_DRIVER(rx51_watchdog) = {
+ .name = "rx51_watchdog",
+ .id = UCLASS_WDT,
+ .ops = &rx51_watchdog_ops,
+ .probe = rx51_watchdog_probe,
+};
+
/*
* TWL4030 keypad handler for cfb_console
*/
@@ -722,3 +747,7 @@
{ "i2c_omap", &rx51_i2c[1] },
{ "i2c_omap", &rx51_i2c[2] },
};
+
+U_BOOT_DRVINFOS(rx51_watchdog) = {
+ { "rx51_watchdog" },
+};
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
deleted file mode 100644
index e696a12..0000000
--- a/board/qemu-mips/Kconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-if TARGET_QEMU_MIPS
-
-config SYS_BOARD
- default "qemu-mips"
-
-config SYS_CONFIG_NAME
- default "qemu-mips" if 32BIT
- default "qemu-mips64" if 64BIT
-
-config SYS_TEXT_BASE
- default 0xbfc00000 if 32BIT
- default 0xffffffffbfc00000 if 64BIT
-
-config SYS_DCACHE_SIZE
- default 16384
-
-config SYS_DCACHE_LINE_SIZE
- default 32
-
-config SYS_ICACHE_SIZE
- default 16384
-
-config SYS_ICACHE_LINE_SIZE
- default 32
-
-endif
diff --git a/board/qemu-mips/MAINTAINERS b/board/qemu-mips/MAINTAINERS
deleted file mode 100644
index 334f9d8..0000000
--- a/board/qemu-mips/MAINTAINERS
+++ /dev/null
@@ -1,14 +0,0 @@
-QEMU-MIPS BOARD
-M: Vlad Lungu <vlad.lungu@windriver.com>
-S: Maintained
-F: board/qemu-mips/
-F: include/configs/qemu-mips.h
-F: configs/qemu_mips_defconfig
-
-QEMU_MIPSEL BOARD
-#M: -
-S: Maintained
-F: configs/qemu_mipsel_defconfig
-F: include/configs/qemu-mips64.h
-F: configs/qemu_mips64_defconfig
-F: configs/qemu_mips64el_defconfig
diff --git a/board/qemu-mips/Makefile b/board/qemu-mips/Makefile
deleted file mode 100644
index 98e3874..0000000
--- a/board/qemu-mips/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2003-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y = qemu-mips.o
-obj-y += lowlevel_init.o
diff --git a/board/qemu-mips/lowlevel_init.S b/board/qemu-mips/lowlevel_init.S
deleted file mode 100644
index b0f7072..0000000
--- a/board/qemu-mips/lowlevel_init.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Memory sub-system initialization code */
-
-#include <config.h>
-#include <asm/regdef.h>
-#include <asm/mipsregs.h>
-
- .text
- .set noreorder
- .set mips32
-
- .globl lowlevel_init
-lowlevel_init:
-
- /*
- * Step 2) Establish Status Register
- * (set BEV, clear ERL, clear EXL, clear IE)
- */
- li t1, 0x00400000
- mtc0 t1, CP0_STATUS
-
- /*
- * Step 3) Establish CP0 Config0
- * (set K0=3)
- */
- li t1, 0x00000003
- mtc0 t1, CP0_CONFIG
-
- /*
- * Step 7) Establish Cause
- * (set IV bit)
- */
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* Establish Wired (and Random) */
- mtc0 zero, CP0_WIRED
- nop
-
- jr ra
- nop
diff --git a/board/qemu-mips/qemu-mips.c b/board/qemu-mips/qemu-mips.c
deleted file mode 100644
index f570917..0000000
--- a/board/qemu-mips/qemu-mips.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2007
- * Vlad Lungu vlad.lungu@windriver.com
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <net.h>
-#include <asm/global_data.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
- /* Sdram is setup by assembler code */
- /* If memory could be changed, we should return the true value here */
- gd->ram_size = MEM_SIZE * 1024 * 1024;
-
- return 0;
-}
-
-int checkboard(void)
-{
- u32 proc_id;
- u32 config1;
-
- proc_id = read_c0_prid();
- printf("Board: Qemu -M mips CPU: ");
- switch (proc_id) {
- case 0x00018000:
- printf("4Kc");
- break;
- case 0x00018400:
- printf("4KEcR1");
- break;
- case 0x00019000:
- printf("4KEc");
- break;
- case 0x00019300:
- config1 = read_c0_config1();
- if (config1 & 1)
- printf("24Kf");
- else
- printf("24Kc");
- break;
- case 0x00019500:
- printf("34Kf");
- break;
- case 0x00000400:
- printf("R4000");
- break;
- case 0x00018100:
- config1 = read_c0_config1();
- if (config1 & 1)
- printf("5Kf");
- else
- printf("5Kc");
- break;
- case 0x000182a0:
- printf("20Kc");
- break;
-
- default:
- printf("unknown");
- }
- printf(" proc_id=0x%x\n", proc_id);
-
- return 0;
-}
-
-int misc_init_r(void)
-{
- set_io_port_base(0);
- return 0;
-}
-
-int board_eth_init(struct bd_info *bis)
-{
- return ne2k_register();
-}
diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c
index e773579..0352d34 100644
--- a/board/renesas/rcar-common/common.c
+++ b/board/renesas/rcar-common/common.c
@@ -43,4 +43,84 @@
return 0;
}
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node)
+{
+ struct fdt_resource first_mem_res, curr_mem_res;
+ int curr_mem_reg, first_mem_reg = 0;
+ int ret;
+
+ for (;;) {
+ ret = fdt_get_resource(blob, first_mem_node, "reg",
+ first_mem_reg++, &first_mem_res);
+ if (ret) /* No more entries, no overlap found */
+ return 0;
+
+ curr_mem_reg = 0;
+ for (;;) {
+ ret = fdt_get_resource(blob, curr_mem_node, "reg",
+ curr_mem_reg++, &curr_mem_res);
+ if (ret) /* No more entries, check next tuple */
+ break;
+
+ if (curr_mem_res.end < first_mem_res.start)
+ continue;
+
+ if (curr_mem_res.start >= first_mem_res.end)
+ continue;
+
+ printf("Overlap found: 0x%llx..0x%llx / 0x%llx..0x%llx\n",
+ first_mem_res.start, first_mem_res.end,
+ curr_mem_res.start, curr_mem_res.end);
+
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /*
+ * Scrub duplicate /memory@* node entries here. Some R-Car DTs might
+ * contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
+ * either generates single /memory node or updates the first /memory
+ * node. Any remaining memory nodes are thus potential duplicates.
+ *
+ * However, it is not possible to delete all the memory nodes right
+ * away, since some of those might not be DRAM memory nodes, but some
+ * sort of other memory. Thus, delete only the memory nodes which are
+ * in the R-Car3 DBSC ranges.
+ */
+ int mem = 0, first_mem_node = 0;
+
+ for (;;) {
+ mem = fdt_node_offset_by_prop_value(blob, mem,
+ "device_type", "memory", 7);
+ if (mem < 0)
+ break;
+ if (!fdtdec_get_is_enabled(blob, mem))
+ continue;
+
+ /* First memory node, patched by U-Boot */
+ if (!first_mem_node) {
+ first_mem_node = mem;
+ continue;
+ }
+
+ /* Check the remaining nodes and delete duplicates */
+ if (!is_mem_overlap(blob, first_mem_node, mem))
+ continue;
+
+ /* Delete duplicate node, start again */
+ fdt_del_node(blob, mem);
+ first_mem_node = 0;
+ mem = 0;
+ }
+
+ return 0;
+}
+#endif
#endif
diff --git a/board/ronetix/imx7-cm/Kconfig b/board/ronetix/imx7-cm/Kconfig
new file mode 100644
index 0000000..a4bc48f
--- /dev/null
+++ b/board/ronetix/imx7-cm/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_IMX7_CM
+
+config SYS_BOARD
+ default "imx7-cm"
+
+config SYS_VENDOR
+ default "ronetix"
+
+config SYS_SOC
+ default "mx7"
+
+config SYS_CONFIG_NAME
+ default "imx7-cm"
+
+endif
diff --git a/board/ronetix/imx7-cm/MAINTAINERS b/board/ronetix/imx7-cm/MAINTAINERS
new file mode 100644
index 0000000..184c887
--- /dev/null
+++ b/board/ronetix/imx7-cm/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX7-CM BOARD
+M: Ilko Iliev <iliev@ronetix.com>
+S: Maintained
+F: board/ronetix/imx7_cm/
+F: include/configs/imx7_cm.h
+F: configs/imx7_cm_defconfig
\ No newline at end of file
diff --git a/board/ronetix/imx7-cm/Makefile b/board/ronetix/imx7-cm/Makefile
new file mode 100644
index 0000000..7e08f23
--- /dev/null
+++ b/board/ronetix/imx7-cm/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+# (C) Copyright 2017 NXP Semiconductors
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+else
+obj-y += imx7-cm.o
+endif
diff --git a/board/ronetix/imx7-cm/README b/board/ronetix/imx7-cm/README
new file mode 100644
index 0000000..43e8c4f
--- /dev/null
+++ b/board/ronetix/imx7-cm/README
@@ -0,0 +1,11 @@
+U-Boot for the Ronetix i.MX7-CM board
+
+Build U-Boot
+============
+$ make imx7_cm_defconfig
+$ make
+
+Burn the images to a SD card
+============================
+$ sudo dd if=SPL of=/dev/sdX bs=1k seek=1; sync
+$ sudo dd if=u-boot-dtb.img of=/dev/sdX bs=1k seek=69; sync
diff --git a/board/ronetix/imx7-cm/imx7-cm.c b/board/ronetix/imx7-cm/imx7-cm.c
new file mode 100644
index 0000000..c23097f
--- /dev/null
+++ b/board/ronetix/imx7-cm/imx7-cm.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Ronetix GmbH
+ */
+
+#include <init.h>
+#include <net.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/gpio.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <asm/io.h>
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <power/pmic.h>
+#include <power/pfuze3000_pmic.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ gd->ram_size = imx_ddr_size();
+ return 0;
+}
+
+int power_init_board(void)
+{
+ struct udevice *dev;
+ int ret;
+ unsigned int reg, rev;
+
+ ret = pmic_get("pmic@8", &dev);
+ if (ret == -ENODEV) {
+ puts("No pmic\n");
+ return 0;
+ }
+ if (ret != 0)
+ return ret;
+
+ reg = pmic_reg_read(dev, PFUZE3000_DEVICEID);
+ rev = pmic_reg_read(dev, PFUZE3000_REVID);
+ printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev);
+
+ /* disable Low Power Mode during standby mode */
+ reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
+ reg |= 0x1;
+ pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
+
+ /* SW1A/1B mode set to APS/APS */
+ reg = 0x8;
+ pmic_reg_write(dev, PFUZE3000_SW1AMODE, reg);
+ pmic_reg_write(dev, PFUZE3000_SW1BMODE, reg);
+
+ /* SW1A/1B standby voltage set to 1.025V */
+ reg = 0xd;
+ pmic_reg_write(dev, PFUZE3000_SW1ASTBY, reg);
+ pmic_reg_write(dev, PFUZE3000_SW1BSTBY, reg);
+
+ /* decrease SW1B normal voltage to 0.975V */
+ reg = pmic_reg_read(dev, PFUZE3000_SW1BVOLT);
+ reg &= ~0x1f;
+ reg |= PFUZE3000_SW1AB_SETP(975);
+ pmic_reg_write(dev, PFUZE3000_SW1BVOLT, reg);
+
+ return 0;
+}
+
+static int setup_fec(void)
+{
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ setup_fec();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: iMX7-CM\n");
+ return 0;
+}
diff --git a/board/ronetix/imx7-cm/spl.c b/board/ronetix/imx7-cm/spl.c
new file mode 100644
index 0000000..d36f734
--- /dev/null
+++ b/board/ronetix/imx7-cm/spl.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Ronetix GmbH
+ *
+ * Author: Ilko Iliev <iliev@ronetix.at>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/crm_regs.h>
+#include <asm/arch/mx7-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch-mx7/mx7-ddr.h>
+#include <asm/mach-imx/iomux-v3.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc_imx.h>
+#include <spl.h>
+
+static struct ddrc ddrc_regs_val = {
+ .mstr = 0x01040001,
+ .rfshtmg = 0x00400046,
+ .init1 = 0x00690000,
+ .init0 = 0x00020083,
+ .init3 = 0x09300004,
+ .init4 = 0x04080000,
+ .init5 = 0x00100004,
+ .rankctl = 0x0000033F,
+ .dramtmg0 = 0x09081109,
+ .dramtmg1 = 0x0007020d,
+ .dramtmg2 = 0x03040407,
+ .dramtmg3 = 0x00002006,
+ .dramtmg4 = 0x04020205,
+ .dramtmg5 = 0x03030202,
+ .dramtmg8 = 0x00000803,
+ .zqctl0 = 0x00800020,
+ .dfitmg0 = 0x02098204,
+ .dfitmg1 = 0x00030303,
+ .dfiupd0 = 0x80400003,
+ .dfiupd1 = 0x00100020,
+ .dfiupd2 = 0x80100004,
+ .addrmap4 = 0x00000F0F,
+ .odtcfg = 0x06000604,
+ .odtmap = 0x00000001,
+ .rfshtmg = 0x00400046,
+ .dramtmg0 = 0x09081109,
+ .addrmap0 = 0x0000001f,
+ .addrmap1 = 0x00080808,
+ .addrmap4 = 0x00000f0f,
+ .addrmap5 = 0x07070707,
+ .addrmap6 = 0x0f0f0707,
+};
+
+static struct ddrc_mp ddrc_mp_val = {
+ .pctrl_0 = 0x00000001,
+};
+
+static struct ddr_phy ddr_phy_regs_val = {
+ .phy_con0 = 0x17420f40,
+ .phy_con1 = 0x10210100,
+ .phy_con4 = 0x00060807,
+ .mdll_con0 = 0x1010007e,
+ .drvds_con0 = 0x00000d6e,
+ .cmd_sdll_con0 = 0x00000010,
+ .offset_lp_con0 = 0x0000000f,
+ .offset_rd_con0 = 0x0a0a0a0a,
+ .offset_wr_con0 = 0x06060606,
+};
+
+static struct mx7_calibration calib_param = {
+ .num_val = 5,
+ .values = {
+ 0x0E407304,
+ 0x0E447304,
+ 0x0E447306,
+ 0x0E447304,
+ 0x0E447304,
+ },
+};
+
+static void ddr_init(void)
+{
+ mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, &calib_param);
+}
+
+#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
+ PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
+
+static iomux_v3_cfg_t const uart1_pads[] = {
+ MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+void uart1_pads_set(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+void board_init_f(ulong dummy)
+{
+ arch_cpu_init();
+
+ uart1_pads_set();
+
+ timer_init();
+
+ preloader_console_init();
+
+ ddr_init();
+
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(void)
+{
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | \
+ PAD_CTL_PUS_PU47KOHM)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
+void usdhc1_pads_set(void)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+}
+
+static struct fsl_esdhc_cfg usdhc_cfg = {
+ USDHC1_BASE_ADDR, 0, 4
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+ usdhc1_pads_set();
+ usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg);
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return 1;
+}
diff --git a/board/ronetix/imx8mq-cm/Kconfig b/board/ronetix/imx8mq-cm/Kconfig
new file mode 100644
index 0000000..9dd6a86
--- /dev/null
+++ b/board/ronetix/imx8mq-cm/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_IMX8MQ_CM
+
+config SYS_BOARD
+ default "imx8mq-cm"
+
+config SYS_VENDOR
+ default "ronetix"
+
+config SYS_CONFIG_NAME
+ default "imx8mq_cm"
+
+endif
diff --git a/board/ronetix/imx8mq-cm/MAINTAINERS b/board/ronetix/imx8mq-cm/MAINTAINERS
new file mode 100644
index 0000000..962a832
--- /dev/null
+++ b/board/ronetix/imx8mq-cm/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8MQ-CM BOARD
+M: Ilko Iliev <iliev@ronetix.at>
+S: Maintained
+F: board/ronetix/imx8mq-cm/
+F: include/configs/imx8mq_cm.h
+F: configs/imx8mq_cm_defconfig
diff --git a/board/ronetix/imx8mq-cm/Makefile b/board/ronetix/imx8mq-cm/Makefile
new file mode 100644
index 0000000..0d9d8e6
--- /dev/null
+++ b/board/ronetix/imx8mq-cm/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8mq_cm.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
+endif
diff --git a/board/ronetix/imx8mq-cm/README b/board/ronetix/imx8mq-cm/README
new file mode 100644
index 0000000..1d43fa5
--- /dev/null
+++ b/board/ronetix/imx8mq-cm/README
@@ -0,0 +1,42 @@
+U-Boot for the Ronetix i.MX8MQ-CM board
+
+Quick Start
+===========
+- Build the ARM Trusted firmware binary
+- Get ddr firmware
+- Build U-Boot
+- Boot
+
+Get and Build the ARM Trusted firmware
+======================================
+$ git clone https://source.codeaurora.org/external/imx/imx-atf
+$ cd imx-atf
+$ git checkout imx_4.19.35_1.0.0
+$ make PLAT=imx8mq bl31
+$ cd ..
+$ cp imx-atf/build/imx8mq/release/bl31.bin .
+
+Get the ddr firmware
+====================
+$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
+$ chmod +x firmware-imx-8.9.bin
+$ ./firmware-imx-8.9.bin
+$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin .
+
+Build U-Boot
+============
+$ /opt/cross/aarch64-ronetix-linux-9.2/bin/aarch64-ronetix-linux-gnu-
+$ make imx8mq_cm_defconfig
+$ make
+
+Burn the flash.bin to MicroSD card offset 33KB
+==============================================
+$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33 conv=sync
+$sudo dd if=u-boot.itb of=/dev/sd[x] bs=1024 seek=384 conv=sync
+
+Boot
+====
+Set Boot switch on base board iMX8M-MB to SD boot:
+ SW1[8:1]: OFF OFF OFF ON - OFF ON OFF OFF
+ SW4[2:1]: OFF OFF
+ J4: 1,2 - open; 3,4 - close; 5,6 - open
diff --git a/board/ronetix/imx8mq-cm/imx8mq_cm.c b/board/ronetix/imx8mq-cm/imx8mq_cm.c
new file mode 100644
index 0000000..9805a3a
--- /dev/null
+++ b/board/ronetix/imx8mq-cm/imx8mq_cm.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm-generic/gpio.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
+
+#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
+
+static iomux_v3_cfg_t const wdog_pads[] = {
+ IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const uart_pads[] = {
+ IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+int board_early_init_f(void)
+{
+ struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+
+ imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
+ set_wdog_reset(wdog);
+
+ imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
+
+ return 0;
+}
+
+static int setup_fec(void)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ /* Use 125M anatop REF_CLK1 for ENET1, not from external */
+ clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
+ return set_clk_enet(ENET_125MHZ);
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+ return 0;
+}
+
+int board_init(void)
+{
+ setup_fec();
+
+ return 0;
+}
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {
+ env_set("board_name", "imx8mq-cm");
+ env_set("board_rev", "v2.0");
+ }
+
+ return 0;
+}
diff --git a/board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg b/board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg
new file mode 100644
index 0000000..268b5ae
--- /dev/null
+++ b/board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 NXP
+ */
+
+#define __ASSEMBLY__
+
+BOOT_FROM sd
+LOADER mkimage.flash.mkimage 0x7E1000
\ No newline at end of file
diff --git a/board/ronetix/imx8mq-cm/lpddr4_timing.c b/board/ronetix/imx8mq-cm/lpddr4_timing.c
new file mode 100644
index 0000000..685600e
--- /dev/null
+++ b/board/ronetix/imx8mq-cm/lpddr4_timing.c
@@ -0,0 +1,1866 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <linux/kernel.h>
+#include <common.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/lpddr4_define.h>
+
+#define WR_POST_EXT_3200 /* recommend to define */
+
+struct dram_cfg_param lpddr4_ddrc_cfg[] = {
+ /* Start to config, default 3200mbps */
+ { DDRC_DBG1(0), 0x00000001 },
+ { DDRC_PWRCTL(0), 0x00000001 },
+ { DDRC_MSTR(0), 0xa1080020 },
+ { DDRC_MSTR2(0), 0x00000000 },
+ { DDRC_RFSHTMG(0), 0x006100E0 },
+ { DDRC_INIT0(0), 0xc003061c },
+ { DDRC_INIT1(0), 0x9e0000 },
+ { DDRC_INIT3(0), 0xd4002d },
+#ifdef WR_POST_EXT_3200
+ { DDRC_INIT4(0), 0x00330008 },
+#else
+ { DDRC_INIT4(0), 0x00310008 },
+#endif
+ { DDRC_INIT6(0), 0x0066004a },
+ { DDRC_INIT7(0), 0x0016004a },
+
+ { DDRC_DRAMTMG0(0), 0x1A201B22 },
+ { DDRC_DRAMTMG1(0), 0x00060633 },
+ { DDRC_DRAMTMG3(0), 0x00C0C000 },
+ { DDRC_DRAMTMG4(0), 0x0F04080F },
+ { DDRC_DRAMTMG5(0), 0x02040C0C },
+ { DDRC_DRAMTMG6(0), 0x01010007 },
+ { DDRC_DRAMTMG7(0), 0x00000401 },
+ { DDRC_DRAMTMG12(0), 0x00020600 },
+ { DDRC_DRAMTMG13(0), 0x0C100002 },
+ { DDRC_DRAMTMG14(0), 0x00000096 },
+ { DDRC_DRAMTMG17(0), 0x00A00050 },
+
+ { DDRC_ZQCTL0(0), 0xc3200018 },
+ { DDRC_ZQCTL1(0), 0x028061A8 },
+ { DDRC_ZQCTL2(0), 0x00000000 },
+
+ { DDRC_DFITMG0(0), 0x0497820A },
+ { DDRC_DFITMG1(0), 0x00080303 },
+ { DDRC_DFIUPD0(0), 0xE0400018 },
+ { DDRC_DFIUPD1(0), 0x00DF00E4 },
+ { DDRC_DFIUPD2(0), 0x80000000 },
+ { DDRC_DFIMISC(0), 0x00000011 },
+ { DDRC_DFITMG2(0), 0x0000170A },
+
+ { DDRC_DBICTL(0), 0x00000001 },
+ { DDRC_DFIPHYMSTR(0), 0x00000001 },
+ { DDRC_RANKCTL(0), 0x00000639 },
+ { DDRC_DRAMTMG2(0), 0x70e1617 },
+
+ /* address mapping */
+ { DDRC_ADDRMAP0(0), 0x0000001F },
+ { DDRC_ADDRMAP3(0), 0x00000000 },
+ { DDRC_ADDRMAP4(0), 0x00001F1F },
+ /* bank interleave */
+ { DDRC_ADDRMAP1(0), 0x00080808 },
+ { DDRC_ADDRMAP5(0), 0x07070707 },
+ { DDRC_ADDRMAP6(0), 0xf070707 },
+
+ /* performance setting */
+ { DDRC_ODTCFG(0), 0x0b060908 },
+ { DDRC_ODTMAP(0), 0x00000000 },
+ { DDRC_SCHED(0), 0x29001505 },
+ { DDRC_SCHED1(0), 0x0000002c },
+ { DDRC_PERFHPR1(0), 0x5900575b },
+ /* 150T starve and 0x90 max tran len */
+ { DDRC_PERFLPR1(0), 0x90000096 },
+ /* 300T starve and 0x10 max tran len */
+ { DDRC_PERFWR1(0), 0x1000012c },
+ { DDRC_DBG0(0), 0x00000016 },
+ { DDRC_DBG1(0), 0x00000000 },
+ { DDRC_DBGCMD(0), 0x00000000 },
+ { DDRC_SWCTL(0), 0x00000001 },
+ { DDRC_POISONCFG(0), 0x00000011 },
+ { DDRC_PCCFG(0), 0x00000111 },
+ { DDRC_PCFGR_0(0), 0x000010f3 },
+ { DDRC_PCFGW_0(0), 0x000072ff },
+ { DDRC_PCTRL_0(0), 0x00000001 },
+ /* disable Read Qos*/
+ { DDRC_PCFGQOS0_0(0), 0x00000e00 },
+ { DDRC_PCFGQOS1_0(0), 0x0062ffff },
+ /* disable Write Qos*/
+ { DDRC_PCFGWQOS0_0(0), 0x00000e00 },
+ { DDRC_PCFGWQOS1_0(0), 0x0000ffff },
+
+ /* Frequency 1: 400mbps */
+ { DDRC_FREQ1_DRAMTMG0(0), 0x0a040305 },
+ { DDRC_FREQ1_DRAMTMG1(0), 0x00030407 },
+ { DDRC_FREQ1_DRAMTMG2(0), 0x0203060b },
+ { DDRC_FREQ1_DRAMTMG3(0), 0x00505000 },
+ { DDRC_FREQ1_DRAMTMG4(0), 0x02040202 },
+ { DDRC_FREQ1_DRAMTMG5(0), 0x02030202 },
+ { DDRC_FREQ1_DRAMTMG6(0), 0x01010004 },
+ { DDRC_FREQ1_DRAMTMG7(0), 0x00000301 },
+ { DDRC_FREQ1_DRAMTMG14(0), 0x00000013 },
+ { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
+ { DDRC_FREQ1_DRAMTMG17(0), 0x0014000a },
+ { DDRC_FREQ1_DERATEINT(0), 0x00007d00 },
+ { DDRC_FREQ1_DFITMG0(0), 0x3818200 },
+ { DDRC_FREQ1_DFITMG2(0), 0x00000100 },
+ { DDRC_FREQ1_RFSHTMG(0), 0xc0012 },
+ { DDRC_FREQ1_INIT3(0), 0x840000 },
+ { DDRC_FREQ1_INIT4(0), 0x310000 },
+ { DDRC_FREQ1_INIT6(0), 0x66004a },
+ { DDRC_FREQ1_INIT7(0), 0x16004a },
+
+ /* Frequency 2: 100mbps */
+ { DDRC_FREQ2_DRAMTMG0(0), 0xa010102 },
+ { DDRC_FREQ2_DRAMTMG1(0), 0x30404 },
+ { DDRC_FREQ2_DRAMTMG2(0), 0x203060b },
+ { DDRC_FREQ2_DRAMTMG3(0), 0x505000 },
+ { DDRC_FREQ2_DRAMTMG4(0), 0x2040202 },
+ { DDRC_FREQ2_DRAMTMG5(0), 0x2030202 },
+ { DDRC_FREQ2_DRAMTMG6(0), 0x1010004 },
+ { DDRC_FREQ2_DRAMTMG7(0), 0x301 },
+ { DDRC_FREQ2_DRAMTMG14(0), 0x5 },
+ { DDRC_FREQ2_DRAMTMG17(0), 0x50003 },
+ { DDRC_FREQ2_DERATEINT(0), 0x1f40 },
+ { DDRC_FREQ2_DFITMG0(0), 0x3818200 },
+ { DDRC_FREQ2_DFITMG2(0), 0x00000100 },
+ { DDRC_FREQ2_RFSHTMG(0), 0x30005 },
+ { DDRC_FREQ2_INIT3(0), 0x840000 },
+ { DDRC_FREQ2_INIT4(0), 0x310000 },
+ { DDRC_FREQ2_INIT6(0), 0x66004a },
+ { DDRC_FREQ2_INIT7(0), 0x16004a },
+};
+
+/* PHY Initialize Configuration */
+struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x1 },
+ { 0x100a2, 0x2 },
+ { 0x100a3, 0x3 },
+ { 0x100a4, 0x4 },
+ { 0x100a5, 0x5 },
+ { 0x100a6, 0x6 },
+ { 0x100a7, 0x7 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x1 },
+ { 0x110a2, 0x2 },
+ { 0x110a3, 0x3 },
+ { 0x110a4, 0x4 },
+ { 0x110a5, 0x5 },
+ { 0x110a6, 0x6 },
+ { 0x110a7, 0x7 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x1 },
+ { 0x120a2, 0x2 },
+ { 0x120a3, 0x3 },
+ { 0x120a4, 0x4 },
+ { 0x120a5, 0x5 },
+ { 0x120a6, 0x6 },
+ { 0x120a7, 0x7 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x1 },
+ { 0x130a2, 0x2 },
+ { 0x130a3, 0x3 },
+ { 0x130a4, 0x4 },
+ { 0x130a5, 0x5 },
+ { 0x130a6, 0x6 },
+ { 0x130a7, 0x7 },
+ { 0x1005f, 0x1ff },
+ { 0x1015f, 0x1ff },
+ { 0x1105f, 0x1ff },
+ { 0x1115f, 0x1ff },
+ { 0x1205f, 0x1ff },
+ { 0x1215f, 0x1ff },
+ { 0x1305f, 0x1ff },
+ { 0x1315f, 0x1ff },
+ { 0x11005f, 0x1ff },
+ { 0x11015f, 0x1ff },
+ { 0x11105f, 0x1ff },
+ { 0x11115f, 0x1ff },
+ { 0x11205f, 0x1ff },
+ { 0x11215f, 0x1ff },
+ { 0x11305f, 0x1ff },
+ { 0x11315f, 0x1ff },
+ { 0x21005f, 0x1ff },
+ { 0x21015f, 0x1ff },
+ { 0x21105f, 0x1ff },
+ { 0x21115f, 0x1ff },
+ { 0x21205f, 0x1ff },
+ { 0x21215f, 0x1ff },
+ { 0x21305f, 0x1ff },
+ { 0x21315f, 0x1ff },
+ { 0x55, 0x1ff },
+ { 0x1055, 0x1ff },
+ { 0x2055, 0x1ff },
+ { 0x3055, 0x1ff },
+ { 0x4055, 0x1ff },
+ { 0x5055, 0x1ff },
+ { 0x6055, 0x1ff },
+ { 0x7055, 0x1ff },
+ { 0x8055, 0x1ff },
+ { 0x9055, 0x1ff },
+ { 0x200c5, 0x19 },
+ { 0x1200c5, 0x7 },
+ { 0x2200c5, 0x7 },
+ { 0x2002e, 0x2 },
+ { 0x12002e, 0x2 },
+ { 0x22002e, 0x2 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x20024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x120024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x220024, 0x1ab },
+ { 0x2003a, 0x0 },
+ { 0x20056, 0x3 },
+ { 0x120056, 0x3 },
+ { 0x220056, 0x3 },
+ { 0x1004d, 0xe00 },
+ { 0x1014d, 0xe00 },
+ { 0x1104d, 0xe00 },
+ { 0x1114d, 0xe00 },
+ { 0x1204d, 0xe00 },
+ { 0x1214d, 0xe00 },
+ { 0x1304d, 0xe00 },
+ { 0x1314d, 0xe00 },
+ { 0x11004d, 0xe00 },
+ { 0x11014d, 0xe00 },
+ { 0x11104d, 0xe00 },
+ { 0x11114d, 0xe00 },
+ { 0x11204d, 0xe00 },
+ { 0x11214d, 0xe00 },
+ { 0x11304d, 0xe00 },
+ { 0x11314d, 0xe00 },
+ { 0x21004d, 0xe00 },
+ { 0x21014d, 0xe00 },
+ { 0x21104d, 0xe00 },
+ { 0x21114d, 0xe00 },
+ { 0x21204d, 0xe00 },
+ { 0x21214d, 0xe00 },
+ { 0x21304d, 0xe00 },
+ { 0x21314d, 0xe00 },
+ { 0x10049, 0xeba },
+ { 0x10149, 0xeba },
+ { 0x11049, 0xeba },
+ { 0x11149, 0xeba },
+ { 0x12049, 0xeba },
+ { 0x12149, 0xeba },
+ { 0x13049, 0xeba },
+ { 0x13149, 0xeba },
+ { 0x110049, 0xeba },
+ { 0x110149, 0xeba },
+ { 0x111049, 0xeba },
+ { 0x111149, 0xeba },
+ { 0x112049, 0xeba },
+ { 0x112149, 0xeba },
+ { 0x113049, 0xeba },
+ { 0x113149, 0xeba },
+ { 0x210049, 0xeba },
+ { 0x210149, 0xeba },
+ { 0x211049, 0xeba },
+ { 0x211149, 0xeba },
+ { 0x212049, 0xeba },
+ { 0x212149, 0xeba },
+ { 0x213049, 0xeba },
+ { 0x213149, 0xeba },
+ { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
+ { 0x20018, 0x3 },
+ { 0x20075, 0x4 },
+ { 0x20050, 0x0 },
+ { 0x20008, 0x320 },
+ { 0x120008, 0x64 },
+ { 0x220008, 0x19 },
+ { 0x20088, 0x9 },
+ { 0x200b2, 0xdc },
+ { 0x10043, 0x5a1 },
+ { 0x10143, 0x5a1 },
+ { 0x11043, 0x5a1 },
+ { 0x11143, 0x5a1 },
+ { 0x12043, 0x5a1 },
+ { 0x12143, 0x5a1 },
+ { 0x13043, 0x5a1 },
+ { 0x13143, 0x5a1 },
+ { 0x1200b2, 0xdc },
+ { 0x110043, 0x5a1 },
+ { 0x110143, 0x5a1 },
+ { 0x111043, 0x5a1 },
+ { 0x111143, 0x5a1 },
+ { 0x112043, 0x5a1 },
+ { 0x112143, 0x5a1 },
+ { 0x113043, 0x5a1 },
+ { 0x113143, 0x5a1 },
+ { 0x2200b2, 0xdc },
+ { 0x210043, 0x5a1 },
+ { 0x210143, 0x5a1 },
+ { 0x211043, 0x5a1 },
+ { 0x211143, 0x5a1 },
+ { 0x212043, 0x5a1 },
+ { 0x212143, 0x5a1 },
+ { 0x213043, 0x5a1 },
+ { 0x213143, 0x5a1 },
+ { 0x200fa, 0x1 },
+ { 0x1200fa, 0x1 },
+ { 0x2200fa, 0x1 },
+ { 0x20019, 0x1 },
+ { 0x120019, 0x1 },
+ { 0x220019, 0x1 },
+ { 0x200f0, 0x660 },
+ { 0x200f1, 0x0 },
+ { 0x200f2, 0x4444 },
+ { 0x200f3, 0x8888 },
+ { 0x200f4, 0x5665 },
+ { 0x200f5, 0x0 },
+ { 0x200f6, 0x0 },
+ { 0x200f7, 0xf000 },
+ { 0x20025, 0x0 },
+ { 0x2002d, 0x0 },
+ { 0x12002d, 0x0 },
+ { 0x22002d, 0x0 },
+ { 0x200c7, 0x80 },
+ { 0x1200c7, 0x80 },
+ { 0x2200c7, 0x80 },
+ { 0x200ca, 0x106 },
+ { 0x1200ca, 0x106 },
+ { 0x2200ca, 0x106 },
+ { 0x20110, 0x2 },
+ { 0x20111, 0x3 },
+ { 0x20112, 0x4 },
+ { 0x20113, 0x5 },
+ { 0x20114, 0x0 },
+ { 0x20115, 0x1 },
+};
+
+/* ddr phy trained csr */
+struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
+ { 0x200b2, 0x0 },
+ { 0x1200b2, 0x0 },
+ { 0x2200b2, 0x0 },
+ { 0x200cb, 0x0 },
+ { 0x10043, 0x0 },
+ { 0x110043, 0x0 },
+ { 0x210043, 0x0 },
+ { 0x10143, 0x0 },
+ { 0x110143, 0x0 },
+ { 0x210143, 0x0 },
+ { 0x11043, 0x0 },
+ { 0x111043, 0x0 },
+ { 0x211043, 0x0 },
+ { 0x11143, 0x0 },
+ { 0x111143, 0x0 },
+ { 0x211143, 0x0 },
+ { 0x12043, 0x0 },
+ { 0x112043, 0x0 },
+ { 0x212043, 0x0 },
+ { 0x12143, 0x0 },
+ { 0x112143, 0x0 },
+ { 0x212143, 0x0 },
+ { 0x13043, 0x0 },
+ { 0x113043, 0x0 },
+ { 0x213043, 0x0 },
+ { 0x13143, 0x0 },
+ { 0x113143, 0x0 },
+ { 0x213143, 0x0 },
+ { 0x80, 0x0 },
+ { 0x100080, 0x0 },
+ { 0x200080, 0x0 },
+ { 0x1080, 0x0 },
+ { 0x101080, 0x0 },
+ { 0x201080, 0x0 },
+ { 0x2080, 0x0 },
+ { 0x102080, 0x0 },
+ { 0x202080, 0x0 },
+ { 0x3080, 0x0 },
+ { 0x103080, 0x0 },
+ { 0x203080, 0x0 },
+ { 0x4080, 0x0 },
+ { 0x104080, 0x0 },
+ { 0x204080, 0x0 },
+ { 0x5080, 0x0 },
+ { 0x105080, 0x0 },
+ { 0x205080, 0x0 },
+ { 0x6080, 0x0 },
+ { 0x106080, 0x0 },
+ { 0x206080, 0x0 },
+ { 0x7080, 0x0 },
+ { 0x107080, 0x0 },
+ { 0x207080, 0x0 },
+ { 0x8080, 0x0 },
+ { 0x108080, 0x0 },
+ { 0x208080, 0x0 },
+ { 0x9080, 0x0 },
+ { 0x109080, 0x0 },
+ { 0x209080, 0x0 },
+ { 0x10080, 0x0 },
+ { 0x110080, 0x0 },
+ { 0x210080, 0x0 },
+ { 0x10180, 0x0 },
+ { 0x110180, 0x0 },
+ { 0x210180, 0x0 },
+ { 0x11080, 0x0 },
+ { 0x111080, 0x0 },
+ { 0x211080, 0x0 },
+ { 0x11180, 0x0 },
+ { 0x111180, 0x0 },
+ { 0x211180, 0x0 },
+ { 0x12080, 0x0 },
+ { 0x112080, 0x0 },
+ { 0x212080, 0x0 },
+ { 0x12180, 0x0 },
+ { 0x112180, 0x0 },
+ { 0x212180, 0x0 },
+ { 0x13080, 0x0 },
+ { 0x113080, 0x0 },
+ { 0x213080, 0x0 },
+ { 0x13180, 0x0 },
+ { 0x113180, 0x0 },
+ { 0x213180, 0x0 },
+ { 0x10081, 0x0 },
+ { 0x110081, 0x0 },
+ { 0x210081, 0x0 },
+ { 0x10181, 0x0 },
+ { 0x110181, 0x0 },
+ { 0x210181, 0x0 },
+ { 0x11081, 0x0 },
+ { 0x111081, 0x0 },
+ { 0x211081, 0x0 },
+ { 0x11181, 0x0 },
+ { 0x111181, 0x0 },
+ { 0x211181, 0x0 },
+ { 0x12081, 0x0 },
+ { 0x112081, 0x0 },
+ { 0x212081, 0x0 },
+ { 0x12181, 0x0 },
+ { 0x112181, 0x0 },
+ { 0x212181, 0x0 },
+ { 0x13081, 0x0 },
+ { 0x113081, 0x0 },
+ { 0x213081, 0x0 },
+ { 0x13181, 0x0 },
+ { 0x113181, 0x0 },
+ { 0x213181, 0x0 },
+ { 0x100d0, 0x0 },
+ { 0x1100d0, 0x0 },
+ { 0x2100d0, 0x0 },
+ { 0x101d0, 0x0 },
+ { 0x1101d0, 0x0 },
+ { 0x2101d0, 0x0 },
+ { 0x110d0, 0x0 },
+ { 0x1110d0, 0x0 },
+ { 0x2110d0, 0x0 },
+ { 0x111d0, 0x0 },
+ { 0x1111d0, 0x0 },
+ { 0x2111d0, 0x0 },
+ { 0x120d0, 0x0 },
+ { 0x1120d0, 0x0 },
+ { 0x2120d0, 0x0 },
+ { 0x121d0, 0x0 },
+ { 0x1121d0, 0x0 },
+ { 0x2121d0, 0x0 },
+ { 0x130d0, 0x0 },
+ { 0x1130d0, 0x0 },
+ { 0x2130d0, 0x0 },
+ { 0x131d0, 0x0 },
+ { 0x1131d0, 0x0 },
+ { 0x2131d0, 0x0 },
+ { 0x100d1, 0x0 },
+ { 0x1100d1, 0x0 },
+ { 0x2100d1, 0x0 },
+ { 0x101d1, 0x0 },
+ { 0x1101d1, 0x0 },
+ { 0x2101d1, 0x0 },
+ { 0x110d1, 0x0 },
+ { 0x1110d1, 0x0 },
+ { 0x2110d1, 0x0 },
+ { 0x111d1, 0x0 },
+ { 0x1111d1, 0x0 },
+ { 0x2111d1, 0x0 },
+ { 0x120d1, 0x0 },
+ { 0x1120d1, 0x0 },
+ { 0x2120d1, 0x0 },
+ { 0x121d1, 0x0 },
+ { 0x1121d1, 0x0 },
+ { 0x2121d1, 0x0 },
+ { 0x130d1, 0x0 },
+ { 0x1130d1, 0x0 },
+ { 0x2130d1, 0x0 },
+ { 0x131d1, 0x0 },
+ { 0x1131d1, 0x0 },
+ { 0x2131d1, 0x0 },
+ { 0x10068, 0x0 },
+ { 0x10168, 0x0 },
+ { 0x10268, 0x0 },
+ { 0x10368, 0x0 },
+ { 0x10468, 0x0 },
+ { 0x10568, 0x0 },
+ { 0x10668, 0x0 },
+ { 0x10768, 0x0 },
+ { 0x10868, 0x0 },
+ { 0x11068, 0x0 },
+ { 0x11168, 0x0 },
+ { 0x11268, 0x0 },
+ { 0x11368, 0x0 },
+ { 0x11468, 0x0 },
+ { 0x11568, 0x0 },
+ { 0x11668, 0x0 },
+ { 0x11768, 0x0 },
+ { 0x11868, 0x0 },
+ { 0x12068, 0x0 },
+ { 0x12168, 0x0 },
+ { 0x12268, 0x0 },
+ { 0x12368, 0x0 },
+ { 0x12468, 0x0 },
+ { 0x12568, 0x0 },
+ { 0x12668, 0x0 },
+ { 0x12768, 0x0 },
+ { 0x12868, 0x0 },
+ { 0x13068, 0x0 },
+ { 0x13168, 0x0 },
+ { 0x13268, 0x0 },
+ { 0x13368, 0x0 },
+ { 0x13468, 0x0 },
+ { 0x13568, 0x0 },
+ { 0x13668, 0x0 },
+ { 0x13768, 0x0 },
+ { 0x13868, 0x0 },
+ { 0x10069, 0x0 },
+ { 0x10169, 0x0 },
+ { 0x10269, 0x0 },
+ { 0x10369, 0x0 },
+ { 0x10469, 0x0 },
+ { 0x10569, 0x0 },
+ { 0x10669, 0x0 },
+ { 0x10769, 0x0 },
+ { 0x10869, 0x0 },
+ { 0x11069, 0x0 },
+ { 0x11169, 0x0 },
+ { 0x11269, 0x0 },
+ { 0x11369, 0x0 },
+ { 0x11469, 0x0 },
+ { 0x11569, 0x0 },
+ { 0x11669, 0x0 },
+ { 0x11769, 0x0 },
+ { 0x11869, 0x0 },
+ { 0x12069, 0x0 },
+ { 0x12169, 0x0 },
+ { 0x12269, 0x0 },
+ { 0x12369, 0x0 },
+ { 0x12469, 0x0 },
+ { 0x12569, 0x0 },
+ { 0x12669, 0x0 },
+ { 0x12769, 0x0 },
+ { 0x12869, 0x0 },
+ { 0x13069, 0x0 },
+ { 0x13169, 0x0 },
+ { 0x13269, 0x0 },
+ { 0x13369, 0x0 },
+ { 0x13469, 0x0 },
+ { 0x13569, 0x0 },
+ { 0x13669, 0x0 },
+ { 0x13769, 0x0 },
+ { 0x13869, 0x0 },
+ { 0x1008c, 0x0 },
+ { 0x11008c, 0x0 },
+ { 0x21008c, 0x0 },
+ { 0x1018c, 0x0 },
+ { 0x11018c, 0x0 },
+ { 0x21018c, 0x0 },
+ { 0x1108c, 0x0 },
+ { 0x11108c, 0x0 },
+ { 0x21108c, 0x0 },
+ { 0x1118c, 0x0 },
+ { 0x11118c, 0x0 },
+ { 0x21118c, 0x0 },
+ { 0x1208c, 0x0 },
+ { 0x11208c, 0x0 },
+ { 0x21208c, 0x0 },
+ { 0x1218c, 0x0 },
+ { 0x11218c, 0x0 },
+ { 0x21218c, 0x0 },
+ { 0x1308c, 0x0 },
+ { 0x11308c, 0x0 },
+ { 0x21308c, 0x0 },
+ { 0x1318c, 0x0 },
+ { 0x11318c, 0x0 },
+ { 0x21318c, 0x0 },
+ { 0x1008d, 0x0 },
+ { 0x11008d, 0x0 },
+ { 0x21008d, 0x0 },
+ { 0x1018d, 0x0 },
+ { 0x11018d, 0x0 },
+ { 0x21018d, 0x0 },
+ { 0x1108d, 0x0 },
+ { 0x11108d, 0x0 },
+ { 0x21108d, 0x0 },
+ { 0x1118d, 0x0 },
+ { 0x11118d, 0x0 },
+ { 0x21118d, 0x0 },
+ { 0x1208d, 0x0 },
+ { 0x11208d, 0x0 },
+ { 0x21208d, 0x0 },
+ { 0x1218d, 0x0 },
+ { 0x11218d, 0x0 },
+ { 0x21218d, 0x0 },
+ { 0x1308d, 0x0 },
+ { 0x11308d, 0x0 },
+ { 0x21308d, 0x0 },
+ { 0x1318d, 0x0 },
+ { 0x11318d, 0x0 },
+ { 0x21318d, 0x0 },
+ { 0x100c0, 0x0 },
+ { 0x1100c0, 0x0 },
+ { 0x2100c0, 0x0 },
+ { 0x101c0, 0x0 },
+ { 0x1101c0, 0x0 },
+ { 0x2101c0, 0x0 },
+ { 0x102c0, 0x0 },
+ { 0x1102c0, 0x0 },
+ { 0x2102c0, 0x0 },
+ { 0x103c0, 0x0 },
+ { 0x1103c0, 0x0 },
+ { 0x2103c0, 0x0 },
+ { 0x104c0, 0x0 },
+ { 0x1104c0, 0x0 },
+ { 0x2104c0, 0x0 },
+ { 0x105c0, 0x0 },
+ { 0x1105c0, 0x0 },
+ { 0x2105c0, 0x0 },
+ { 0x106c0, 0x0 },
+ { 0x1106c0, 0x0 },
+ { 0x2106c0, 0x0 },
+ { 0x107c0, 0x0 },
+ { 0x1107c0, 0x0 },
+ { 0x2107c0, 0x0 },
+ { 0x108c0, 0x0 },
+ { 0x1108c0, 0x0 },
+ { 0x2108c0, 0x0 },
+ { 0x110c0, 0x0 },
+ { 0x1110c0, 0x0 },
+ { 0x2110c0, 0x0 },
+ { 0x111c0, 0x0 },
+ { 0x1111c0, 0x0 },
+ { 0x2111c0, 0x0 },
+ { 0x112c0, 0x0 },
+ { 0x1112c0, 0x0 },
+ { 0x2112c0, 0x0 },
+ { 0x113c0, 0x0 },
+ { 0x1113c0, 0x0 },
+ { 0x2113c0, 0x0 },
+ { 0x114c0, 0x0 },
+ { 0x1114c0, 0x0 },
+ { 0x2114c0, 0x0 },
+ { 0x115c0, 0x0 },
+ { 0x1115c0, 0x0 },
+ { 0x2115c0, 0x0 },
+ { 0x116c0, 0x0 },
+ { 0x1116c0, 0x0 },
+ { 0x2116c0, 0x0 },
+ { 0x117c0, 0x0 },
+ { 0x1117c0, 0x0 },
+ { 0x2117c0, 0x0 },
+ { 0x118c0, 0x0 },
+ { 0x1118c0, 0x0 },
+ { 0x2118c0, 0x0 },
+ { 0x120c0, 0x0 },
+ { 0x1120c0, 0x0 },
+ { 0x2120c0, 0x0 },
+ { 0x121c0, 0x0 },
+ { 0x1121c0, 0x0 },
+ { 0x2121c0, 0x0 },
+ { 0x122c0, 0x0 },
+ { 0x1122c0, 0x0 },
+ { 0x2122c0, 0x0 },
+ { 0x123c0, 0x0 },
+ { 0x1123c0, 0x0 },
+ { 0x2123c0, 0x0 },
+ { 0x124c0, 0x0 },
+ { 0x1124c0, 0x0 },
+ { 0x2124c0, 0x0 },
+ { 0x125c0, 0x0 },
+ { 0x1125c0, 0x0 },
+ { 0x2125c0, 0x0 },
+ { 0x126c0, 0x0 },
+ { 0x1126c0, 0x0 },
+ { 0x2126c0, 0x0 },
+ { 0x127c0, 0x0 },
+ { 0x1127c0, 0x0 },
+ { 0x2127c0, 0x0 },
+ { 0x128c0, 0x0 },
+ { 0x1128c0, 0x0 },
+ { 0x2128c0, 0x0 },
+ { 0x130c0, 0x0 },
+ { 0x1130c0, 0x0 },
+ { 0x2130c0, 0x0 },
+ { 0x131c0, 0x0 },
+ { 0x1131c0, 0x0 },
+ { 0x2131c0, 0x0 },
+ { 0x132c0, 0x0 },
+ { 0x1132c0, 0x0 },
+ { 0x2132c0, 0x0 },
+ { 0x133c0, 0x0 },
+ { 0x1133c0, 0x0 },
+ { 0x2133c0, 0x0 },
+ { 0x134c0, 0x0 },
+ { 0x1134c0, 0x0 },
+ { 0x2134c0, 0x0 },
+ { 0x135c0, 0x0 },
+ { 0x1135c0, 0x0 },
+ { 0x2135c0, 0x0 },
+ { 0x136c0, 0x0 },
+ { 0x1136c0, 0x0 },
+ { 0x2136c0, 0x0 },
+ { 0x137c0, 0x0 },
+ { 0x1137c0, 0x0 },
+ { 0x2137c0, 0x0 },
+ { 0x138c0, 0x0 },
+ { 0x1138c0, 0x0 },
+ { 0x2138c0, 0x0 },
+ { 0x100c1, 0x0 },
+ { 0x1100c1, 0x0 },
+ { 0x2100c1, 0x0 },
+ { 0x101c1, 0x0 },
+ { 0x1101c1, 0x0 },
+ { 0x2101c1, 0x0 },
+ { 0x102c1, 0x0 },
+ { 0x1102c1, 0x0 },
+ { 0x2102c1, 0x0 },
+ { 0x103c1, 0x0 },
+ { 0x1103c1, 0x0 },
+ { 0x2103c1, 0x0 },
+ { 0x104c1, 0x0 },
+ { 0x1104c1, 0x0 },
+ { 0x2104c1, 0x0 },
+ { 0x105c1, 0x0 },
+ { 0x1105c1, 0x0 },
+ { 0x2105c1, 0x0 },
+ { 0x106c1, 0x0 },
+ { 0x1106c1, 0x0 },
+ { 0x2106c1, 0x0 },
+ { 0x107c1, 0x0 },
+ { 0x1107c1, 0x0 },
+ { 0x2107c1, 0x0 },
+ { 0x108c1, 0x0 },
+ { 0x1108c1, 0x0 },
+ { 0x2108c1, 0x0 },
+ { 0x110c1, 0x0 },
+ { 0x1110c1, 0x0 },
+ { 0x2110c1, 0x0 },
+ { 0x111c1, 0x0 },
+ { 0x1111c1, 0x0 },
+ { 0x2111c1, 0x0 },
+ { 0x112c1, 0x0 },
+ { 0x1112c1, 0x0 },
+ { 0x2112c1, 0x0 },
+ { 0x113c1, 0x0 },
+ { 0x1113c1, 0x0 },
+ { 0x2113c1, 0x0 },
+ { 0x114c1, 0x0 },
+ { 0x1114c1, 0x0 },
+ { 0x2114c1, 0x0 },
+ { 0x115c1, 0x0 },
+ { 0x1115c1, 0x0 },
+ { 0x2115c1, 0x0 },
+ { 0x116c1, 0x0 },
+ { 0x1116c1, 0x0 },
+ { 0x2116c1, 0x0 },
+ { 0x117c1, 0x0 },
+ { 0x1117c1, 0x0 },
+ { 0x2117c1, 0x0 },
+ { 0x118c1, 0x0 },
+ { 0x1118c1, 0x0 },
+ { 0x2118c1, 0x0 },
+ { 0x120c1, 0x0 },
+ { 0x1120c1, 0x0 },
+ { 0x2120c1, 0x0 },
+ { 0x121c1, 0x0 },
+ { 0x1121c1, 0x0 },
+ { 0x2121c1, 0x0 },
+ { 0x122c1, 0x0 },
+ { 0x1122c1, 0x0 },
+ { 0x2122c1, 0x0 },
+ { 0x123c1, 0x0 },
+ { 0x1123c1, 0x0 },
+ { 0x2123c1, 0x0 },
+ { 0x124c1, 0x0 },
+ { 0x1124c1, 0x0 },
+ { 0x2124c1, 0x0 },
+ { 0x125c1, 0x0 },
+ { 0x1125c1, 0x0 },
+ { 0x2125c1, 0x0 },
+ { 0x126c1, 0x0 },
+ { 0x1126c1, 0x0 },
+ { 0x2126c1, 0x0 },
+ { 0x127c1, 0x0 },
+ { 0x1127c1, 0x0 },
+ { 0x2127c1, 0x0 },
+ { 0x128c1, 0x0 },
+ { 0x1128c1, 0x0 },
+ { 0x2128c1, 0x0 },
+ { 0x130c1, 0x0 },
+ { 0x1130c1, 0x0 },
+ { 0x2130c1, 0x0 },
+ { 0x131c1, 0x0 },
+ { 0x1131c1, 0x0 },
+ { 0x2131c1, 0x0 },
+ { 0x132c1, 0x0 },
+ { 0x1132c1, 0x0 },
+ { 0x2132c1, 0x0 },
+ { 0x133c1, 0x0 },
+ { 0x1133c1, 0x0 },
+ { 0x2133c1, 0x0 },
+ { 0x134c1, 0x0 },
+ { 0x1134c1, 0x0 },
+ { 0x2134c1, 0x0 },
+ { 0x135c1, 0x0 },
+ { 0x1135c1, 0x0 },
+ { 0x2135c1, 0x0 },
+ { 0x136c1, 0x0 },
+ { 0x1136c1, 0x0 },
+ { 0x2136c1, 0x0 },
+ { 0x137c1, 0x0 },
+ { 0x1137c1, 0x0 },
+ { 0x2137c1, 0x0 },
+ { 0x138c1, 0x0 },
+ { 0x1138c1, 0x0 },
+ { 0x2138c1, 0x0 },
+ { 0x10020, 0x0 },
+ { 0x110020, 0x0 },
+ { 0x210020, 0x0 },
+ { 0x11020, 0x0 },
+ { 0x111020, 0x0 },
+ { 0x211020, 0x0 },
+ { 0x12020, 0x0 },
+ { 0x112020, 0x0 },
+ { 0x212020, 0x0 },
+ { 0x13020, 0x0 },
+ { 0x113020, 0x0 },
+ { 0x213020, 0x0 },
+ { 0x20072, 0x0 },
+ { 0x20073, 0x0 },
+ { 0x20074, 0x0 },
+ { 0x100aa, 0x0 },
+ { 0x110aa, 0x0 },
+ { 0x120aa, 0x0 },
+ { 0x130aa, 0x0 },
+ { 0x20010, 0x0 },
+ { 0x120010, 0x0 },
+ { 0x220010, 0x0 },
+ { 0x20011, 0x0 },
+ { 0x120011, 0x0 },
+ { 0x220011, 0x0 },
+ { 0x100ae, 0x0 },
+ { 0x1100ae, 0x0 },
+ { 0x2100ae, 0x0 },
+ { 0x100af, 0x0 },
+ { 0x1100af, 0x0 },
+ { 0x2100af, 0x0 },
+ { 0x110ae, 0x0 },
+ { 0x1110ae, 0x0 },
+ { 0x2110ae, 0x0 },
+ { 0x110af, 0x0 },
+ { 0x1110af, 0x0 },
+ { 0x2110af, 0x0 },
+ { 0x120ae, 0x0 },
+ { 0x1120ae, 0x0 },
+ { 0x2120ae, 0x0 },
+ { 0x120af, 0x0 },
+ { 0x1120af, 0x0 },
+ { 0x2120af, 0x0 },
+ { 0x130ae, 0x0 },
+ { 0x1130ae, 0x0 },
+ { 0x2130ae, 0x0 },
+ { 0x130af, 0x0 },
+ { 0x1130af, 0x0 },
+ { 0x2130af, 0x0 },
+ { 0x20020, 0x0 },
+ { 0x120020, 0x0 },
+ { 0x220020, 0x0 },
+ { 0x100a0, 0x0 },
+ { 0x100a1, 0x0 },
+ { 0x100a2, 0x0 },
+ { 0x100a3, 0x0 },
+ { 0x100a4, 0x0 },
+ { 0x100a5, 0x0 },
+ { 0x100a6, 0x0 },
+ { 0x100a7, 0x0 },
+ { 0x110a0, 0x0 },
+ { 0x110a1, 0x0 },
+ { 0x110a2, 0x0 },
+ { 0x110a3, 0x0 },
+ { 0x110a4, 0x0 },
+ { 0x110a5, 0x0 },
+ { 0x110a6, 0x0 },
+ { 0x110a7, 0x0 },
+ { 0x120a0, 0x0 },
+ { 0x120a1, 0x0 },
+ { 0x120a2, 0x0 },
+ { 0x120a3, 0x0 },
+ { 0x120a4, 0x0 },
+ { 0x120a5, 0x0 },
+ { 0x120a6, 0x0 },
+ { 0x120a7, 0x0 },
+ { 0x130a0, 0x0 },
+ { 0x130a1, 0x0 },
+ { 0x130a2, 0x0 },
+ { 0x130a3, 0x0 },
+ { 0x130a4, 0x0 },
+ { 0x130a5, 0x0 },
+ { 0x130a6, 0x0 },
+ { 0x130a7, 0x0 },
+ { 0x2007c, 0x0 },
+ { 0x12007c, 0x0 },
+ { 0x22007c, 0x0 },
+ { 0x2007d, 0x0 },
+ { 0x12007d, 0x0 },
+ { 0x22007d, 0x0 },
+ { 0x400fd, 0x0 },
+ { 0x400c0, 0x0 },
+ { 0x90201, 0x0 },
+ { 0x190201, 0x0 },
+ { 0x290201, 0x0 },
+ { 0x90202, 0x0 },
+ { 0x190202, 0x0 },
+ { 0x290202, 0x0 },
+ { 0x90203, 0x0 },
+ { 0x190203, 0x0 },
+ { 0x290203, 0x0 },
+ { 0x90204, 0x0 },
+ { 0x190204, 0x0 },
+ { 0x290204, 0x0 },
+ { 0x90205, 0x0 },
+ { 0x190205, 0x0 },
+ { 0x290205, 0x0 },
+ { 0x90206, 0x0 },
+ { 0x190206, 0x0 },
+ { 0x290206, 0x0 },
+ { 0x90207, 0x0 },
+ { 0x190207, 0x0 },
+ { 0x290207, 0x0 },
+ { 0x90208, 0x0 },
+ { 0x190208, 0x0 },
+ { 0x290208, 0x0 },
+ { 0x10062, 0x0 },
+ { 0x10162, 0x0 },
+ { 0x10262, 0x0 },
+ { 0x10362, 0x0 },
+ { 0x10462, 0x0 },
+ { 0x10562, 0x0 },
+ { 0x10662, 0x0 },
+ { 0x10762, 0x0 },
+ { 0x10862, 0x0 },
+ { 0x11062, 0x0 },
+ { 0x11162, 0x0 },
+ { 0x11262, 0x0 },
+ { 0x11362, 0x0 },
+ { 0x11462, 0x0 },
+ { 0x11562, 0x0 },
+ { 0x11662, 0x0 },
+ { 0x11762, 0x0 },
+ { 0x11862, 0x0 },
+ { 0x12062, 0x0 },
+ { 0x12162, 0x0 },
+ { 0x12262, 0x0 },
+ { 0x12362, 0x0 },
+ { 0x12462, 0x0 },
+ { 0x12562, 0x0 },
+ { 0x12662, 0x0 },
+ { 0x12762, 0x0 },
+ { 0x12862, 0x0 },
+ { 0x13062, 0x0 },
+ { 0x13162, 0x0 },
+ { 0x13262, 0x0 },
+ { 0x13362, 0x0 },
+ { 0x13462, 0x0 },
+ { 0x13562, 0x0 },
+ { 0x13662, 0x0 },
+ { 0x13762, 0x0 },
+ { 0x13862, 0x0 },
+ { 0x20077, 0x0 },
+ { 0x10001, 0x0 },
+ { 0x11001, 0x0 },
+ { 0x12001, 0x0 },
+ { 0x13001, 0x0 },
+ { 0x10040, 0x0 },
+ { 0x10140, 0x0 },
+ { 0x10240, 0x0 },
+ { 0x10340, 0x0 },
+ { 0x10440, 0x0 },
+ { 0x10540, 0x0 },
+ { 0x10640, 0x0 },
+ { 0x10740, 0x0 },
+ { 0x10840, 0x0 },
+ { 0x10030, 0x0 },
+ { 0x10130, 0x0 },
+ { 0x10230, 0x0 },
+ { 0x10330, 0x0 },
+ { 0x10430, 0x0 },
+ { 0x10530, 0x0 },
+ { 0x10630, 0x0 },
+ { 0x10730, 0x0 },
+ { 0x10830, 0x0 },
+ { 0x11040, 0x0 },
+ { 0x11140, 0x0 },
+ { 0x11240, 0x0 },
+ { 0x11340, 0x0 },
+ { 0x11440, 0x0 },
+ { 0x11540, 0x0 },
+ { 0x11640, 0x0 },
+ { 0x11740, 0x0 },
+ { 0x11840, 0x0 },
+ { 0x11030, 0x0 },
+ { 0x11130, 0x0 },
+ { 0x11230, 0x0 },
+ { 0x11330, 0x0 },
+ { 0x11430, 0x0 },
+ { 0x11530, 0x0 },
+ { 0x11630, 0x0 },
+ { 0x11730, 0x0 },
+ { 0x11830, 0x0 },
+ { 0x12040, 0x0 },
+ { 0x12140, 0x0 },
+ { 0x12240, 0x0 },
+ { 0x12340, 0x0 },
+ { 0x12440, 0x0 },
+ { 0x12540, 0x0 },
+ { 0x12640, 0x0 },
+ { 0x12740, 0x0 },
+ { 0x12840, 0x0 },
+ { 0x12030, 0x0 },
+ { 0x12130, 0x0 },
+ { 0x12230, 0x0 },
+ { 0x12330, 0x0 },
+ { 0x12430, 0x0 },
+ { 0x12530, 0x0 },
+ { 0x12630, 0x0 },
+ { 0x12730, 0x0 },
+ { 0x12830, 0x0 },
+ { 0x13040, 0x0 },
+ { 0x13140, 0x0 },
+ { 0x13240, 0x0 },
+ { 0x13340, 0x0 },
+ { 0x13440, 0x0 },
+ { 0x13540, 0x0 },
+ { 0x13640, 0x0 },
+ { 0x13740, 0x0 },
+ { 0x13840, 0x0 },
+ { 0x13030, 0x0 },
+ { 0x13130, 0x0 },
+ { 0x13230, 0x0 },
+ { 0x13330, 0x0 },
+ { 0x13430, 0x0 },
+ { 0x13530, 0x0 },
+ { 0x13630, 0x0 },
+ { 0x13730, 0x0 },
+ { 0x13830, 0x0 },
+};
+
+/* P0 message block parameter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P1 message block parameter for training firmware */
+struct dram_cfg_param lpddr4_fsp1_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x101 },
+ { 0x54003, 0x190 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P2 message block parameter for training firmware */
+struct dram_cfg_param lpddr4_fsp2_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54002, 0x102 },
+ { 0x54003, 0x64 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x121f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x84 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x84 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0x8400 },
+ { 0x54033, 0x3100 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0x8400 },
+ { 0x54039, 0x3100 },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* P0 2D message block parameter for training firmware */
+struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
+ { 0xd0000, 0x0 },
+ { 0x54003, 0xc80 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x11 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x110 },
+ { 0x54019, 0x2dd4 },
+ { 0x5401a, 0x31 },
+ { 0x5401b, 0x4a66 },
+ { 0x5401c, 0x4a08 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x2dd4 },
+ { 0x54020, 0x31 },
+ { 0x54021, 0x4a66 },
+ { 0x54022, 0x4a08 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x1 },
+ { 0x54032, 0xd400 },
+ { 0x54033, 0x312d },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x84a },
+ { 0x54036, 0x4a },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xd400 },
+ { 0x54039, 0x312d },
+ { 0x5403a, 0x6600 },
+ { 0x5403b, 0x84a },
+ { 0x5403c, 0x4a },
+ { 0x5403d, 0x1600 },
+ { 0xd0000, 0x1 },
+};
+
+/* DRAM PHY init engine image */
+struct dram_cfg_param lpddr4_phy_pie[] = {
+ { 0xd0000, 0x0 },
+ { 0x90000, 0x10 },
+ { 0x90001, 0x400 },
+ { 0x90002, 0x10e },
+ { 0x90003, 0x0 },
+ { 0x90004, 0x0 },
+ { 0x90005, 0x8 },
+ { 0x90029, 0xb },
+ { 0x9002a, 0x480 },
+ { 0x9002b, 0x109 },
+ { 0x9002c, 0x8 },
+ { 0x9002d, 0x448 },
+ { 0x9002e, 0x139 },
+ { 0x9002f, 0x8 },
+ { 0x90030, 0x478 },
+ { 0x90031, 0x109 },
+ { 0x90032, 0x0 },
+ { 0x90033, 0xe8 },
+ { 0x90034, 0x109 },
+ { 0x90035, 0x2 },
+ { 0x90036, 0x10 },
+ { 0x90037, 0x139 },
+ { 0x90038, 0xf },
+ { 0x90039, 0x7c0 },
+ { 0x9003a, 0x139 },
+ { 0x9003b, 0x44 },
+ { 0x9003c, 0x630 },
+ { 0x9003d, 0x159 },
+ { 0x9003e, 0x14f },
+ { 0x9003f, 0x630 },
+ { 0x90040, 0x159 },
+ { 0x90041, 0x47 },
+ { 0x90042, 0x630 },
+ { 0x90043, 0x149 },
+ { 0x90044, 0x4f },
+ { 0x90045, 0x630 },
+ { 0x90046, 0x179 },
+ { 0x90047, 0x8 },
+ { 0x90048, 0xe0 },
+ { 0x90049, 0x109 },
+ { 0x9004a, 0x0 },
+ { 0x9004b, 0x7c8 },
+ { 0x9004c, 0x109 },
+ { 0x9004d, 0x0 },
+ { 0x9004e, 0x1 },
+ { 0x9004f, 0x8 },
+ { 0x90050, 0x0 },
+ { 0x90051, 0x45a },
+ { 0x90052, 0x9 },
+ { 0x90053, 0x0 },
+ { 0x90054, 0x448 },
+ { 0x90055, 0x109 },
+ { 0x90056, 0x40 },
+ { 0x90057, 0x630 },
+ { 0x90058, 0x179 },
+ { 0x90059, 0x1 },
+ { 0x9005a, 0x618 },
+ { 0x9005b, 0x109 },
+ { 0x9005c, 0x40c0 },
+ { 0x9005d, 0x630 },
+ { 0x9005e, 0x149 },
+ { 0x9005f, 0x8 },
+ { 0x90060, 0x4 },
+ { 0x90061, 0x48 },
+ { 0x90062, 0x4040 },
+ { 0x90063, 0x630 },
+ { 0x90064, 0x149 },
+ { 0x90065, 0x0 },
+ { 0x90066, 0x4 },
+ { 0x90067, 0x48 },
+ { 0x90068, 0x40 },
+ { 0x90069, 0x630 },
+ { 0x9006a, 0x149 },
+ { 0x9006b, 0x10 },
+ { 0x9006c, 0x4 },
+ { 0x9006d, 0x18 },
+ { 0x9006e, 0x0 },
+ { 0x9006f, 0x4 },
+ { 0x90070, 0x78 },
+ { 0x90071, 0x549 },
+ { 0x90072, 0x630 },
+ { 0x90073, 0x159 },
+ { 0x90074, 0xd49 },
+ { 0x90075, 0x630 },
+ { 0x90076, 0x159 },
+ { 0x90077, 0x94a },
+ { 0x90078, 0x630 },
+ { 0x90079, 0x159 },
+ { 0x9007a, 0x441 },
+ { 0x9007b, 0x630 },
+ { 0x9007c, 0x149 },
+ { 0x9007d, 0x42 },
+ { 0x9007e, 0x630 },
+ { 0x9007f, 0x149 },
+ { 0x90080, 0x1 },
+ { 0x90081, 0x630 },
+ { 0x90082, 0x149 },
+ { 0x90083, 0x0 },
+ { 0x90084, 0xe0 },
+ { 0x90085, 0x109 },
+ { 0x90086, 0xa },
+ { 0x90087, 0x10 },
+ { 0x90088, 0x109 },
+ { 0x90089, 0x9 },
+ { 0x9008a, 0x3c0 },
+ { 0x9008b, 0x149 },
+ { 0x9008c, 0x9 },
+ { 0x9008d, 0x3c0 },
+ { 0x9008e, 0x159 },
+ { 0x9008f, 0x18 },
+ { 0x90090, 0x10 },
+ { 0x90091, 0x109 },
+ { 0x90092, 0x0 },
+ { 0x90093, 0x3c0 },
+ { 0x90094, 0x109 },
+ { 0x90095, 0x18 },
+ { 0x90096, 0x4 },
+ { 0x90097, 0x48 },
+ { 0x90098, 0x18 },
+ { 0x90099, 0x4 },
+ { 0x9009a, 0x58 },
+ { 0x9009b, 0xa },
+ { 0x9009c, 0x10 },
+ { 0x9009d, 0x109 },
+ { 0x9009e, 0x2 },
+ { 0x9009f, 0x10 },
+ { 0x900a0, 0x109 },
+ { 0x900a1, 0x5 },
+ { 0x900a2, 0x7c0 },
+ { 0x900a3, 0x109 },
+ { 0x900a4, 0x10 },
+ { 0x900a5, 0x10 },
+ { 0x900a6, 0x109 },
+ { 0x40000, 0x811 },
+ { 0x40020, 0x880 },
+ { 0x40040, 0x0 },
+ { 0x40060, 0x0 },
+ { 0x40001, 0x4008 },
+ { 0x40021, 0x83 },
+ { 0x40041, 0x4f },
+ { 0x40061, 0x0 },
+ { 0x40002, 0x4040 },
+ { 0x40022, 0x83 },
+ { 0x40042, 0x51 },
+ { 0x40062, 0x0 },
+ { 0x40003, 0x811 },
+ { 0x40023, 0x880 },
+ { 0x40043, 0x0 },
+ { 0x40063, 0x0 },
+ { 0x40004, 0x720 },
+ { 0x40024, 0xf },
+ { 0x40044, 0x1740 },
+ { 0x40064, 0x0 },
+ { 0x40005, 0x16 },
+ { 0x40025, 0x83 },
+ { 0x40045, 0x4b },
+ { 0x40065, 0x0 },
+ { 0x40006, 0x716 },
+ { 0x40026, 0xf },
+ { 0x40046, 0x2001 },
+ { 0x40066, 0x0 },
+ { 0x40007, 0x716 },
+ { 0x40027, 0xf },
+ { 0x40047, 0x2800 },
+ { 0x40067, 0x0 },
+ { 0x40008, 0x716 },
+ { 0x40028, 0xf },
+ { 0x40048, 0xf00 },
+ { 0x40068, 0x0 },
+ { 0x40009, 0x720 },
+ { 0x40029, 0xf },
+ { 0x40049, 0x1400 },
+ { 0x40069, 0x0 },
+ { 0x4000a, 0xe08 },
+ { 0x4002a, 0xc15 },
+ { 0x4004a, 0x0 },
+ { 0x4006a, 0x0 },
+ { 0x4000b, 0x623 },
+ { 0x4002b, 0x15 },
+ { 0x4004b, 0x0 },
+ { 0x4006b, 0x0 },
+ { 0x4000c, 0x4028 },
+ { 0x4002c, 0x80 },
+ { 0x4004c, 0x0 },
+ { 0x4006c, 0x0 },
+ { 0x4000d, 0xe08 },
+ { 0x4002d, 0xc1a },
+ { 0x4004d, 0x0 },
+ { 0x4006d, 0x0 },
+ { 0x4000e, 0x623 },
+ { 0x4002e, 0x1a },
+ { 0x4004e, 0x0 },
+ { 0x4006e, 0x0 },
+ { 0x4000f, 0x4040 },
+ { 0x4002f, 0x80 },
+ { 0x4004f, 0x0 },
+ { 0x4006f, 0x0 },
+ { 0x40010, 0x2604 },
+ { 0x40030, 0x15 },
+ { 0x40050, 0x0 },
+ { 0x40070, 0x0 },
+ { 0x40011, 0x708 },
+ { 0x40031, 0x5 },
+ { 0x40051, 0x0 },
+ { 0x40071, 0x2002 },
+ { 0x40012, 0x8 },
+ { 0x40032, 0x80 },
+ { 0x40052, 0x0 },
+ { 0x40072, 0x0 },
+ { 0x40013, 0x2604 },
+ { 0x40033, 0x1a },
+ { 0x40053, 0x0 },
+ { 0x40073, 0x0 },
+ { 0x40014, 0x708 },
+ { 0x40034, 0xa },
+ { 0x40054, 0x0 },
+ { 0x40074, 0x2002 },
+ { 0x40015, 0x4040 },
+ { 0x40035, 0x80 },
+ { 0x40055, 0x0 },
+ { 0x40075, 0x0 },
+ { 0x40016, 0x60a },
+ { 0x40036, 0x15 },
+ { 0x40056, 0x1200 },
+ { 0x40076, 0x0 },
+ { 0x40017, 0x61a },
+ { 0x40037, 0x15 },
+ { 0x40057, 0x1300 },
+ { 0x40077, 0x0 },
+ { 0x40018, 0x60a },
+ { 0x40038, 0x1a },
+ { 0x40058, 0x1200 },
+ { 0x40078, 0x0 },
+ { 0x40019, 0x642 },
+ { 0x40039, 0x1a },
+ { 0x40059, 0x1300 },
+ { 0x40079, 0x0 },
+ { 0x4001a, 0x4808 },
+ { 0x4003a, 0x880 },
+ { 0x4005a, 0x0 },
+ { 0x4007a, 0x0 },
+ { 0x900a7, 0x0 },
+ { 0x900a8, 0x790 },
+ { 0x900a9, 0x11a },
+ { 0x900aa, 0x8 },
+ { 0x900ab, 0x7aa },
+ { 0x900ac, 0x2a },
+ { 0x900ad, 0x10 },
+ { 0x900ae, 0x7b2 },
+ { 0x900af, 0x2a },
+ { 0x900b0, 0x0 },
+ { 0x900b1, 0x7c8 },
+ { 0x900b2, 0x109 },
+ { 0x900b3, 0x10 },
+ { 0x900b4, 0x2a8 },
+ { 0x900b5, 0x129 },
+ { 0x900b6, 0x8 },
+ { 0x900b7, 0x370 },
+ { 0x900b8, 0x129 },
+ { 0x900b9, 0xa },
+ { 0x900ba, 0x3c8 },
+ { 0x900bb, 0x1a9 },
+ { 0x900bc, 0xc },
+ { 0x900bd, 0x408 },
+ { 0x900be, 0x199 },
+ { 0x900bf, 0x14 },
+ { 0x900c0, 0x790 },
+ { 0x900c1, 0x11a },
+ { 0x900c2, 0x8 },
+ { 0x900c3, 0x4 },
+ { 0x900c4, 0x18 },
+ { 0x900c5, 0xe },
+ { 0x900c6, 0x408 },
+ { 0x900c7, 0x199 },
+ { 0x900c8, 0x8 },
+ { 0x900c9, 0x8568 },
+ { 0x900ca, 0x108 },
+ { 0x900cb, 0x18 },
+ { 0x900cc, 0x790 },
+ { 0x900cd, 0x16a },
+ { 0x900ce, 0x8 },
+ { 0x900cf, 0x1d8 },
+ { 0x900d0, 0x169 },
+ { 0x900d1, 0x10 },
+ { 0x900d2, 0x8558 },
+ { 0x900d3, 0x168 },
+ { 0x900d4, 0x70 },
+ { 0x900d5, 0x788 },
+ { 0x900d6, 0x16a },
+ { 0x900d7, 0x1ff8 },
+ { 0x900d8, 0x85a8 },
+ { 0x900d9, 0x1e8 },
+ { 0x900da, 0x50 },
+ { 0x900db, 0x798 },
+ { 0x900dc, 0x16a },
+ { 0x900dd, 0x60 },
+ { 0x900de, 0x7a0 },
+ { 0x900df, 0x16a },
+ { 0x900e0, 0x8 },
+ { 0x900e1, 0x8310 },
+ { 0x900e2, 0x168 },
+ { 0x900e3, 0x8 },
+ { 0x900e4, 0xa310 },
+ { 0x900e5, 0x168 },
+ { 0x900e6, 0xa },
+ { 0x900e7, 0x408 },
+ { 0x900e8, 0x169 },
+ { 0x900e9, 0x6e },
+ { 0x900ea, 0x0 },
+ { 0x900eb, 0x68 },
+ { 0x900ec, 0x0 },
+ { 0x900ed, 0x408 },
+ { 0x900ee, 0x169 },
+ { 0x900ef, 0x0 },
+ { 0x900f0, 0x8310 },
+ { 0x900f1, 0x168 },
+ { 0x900f2, 0x0 },
+ { 0x900f3, 0xa310 },
+ { 0x900f4, 0x168 },
+ { 0x900f5, 0x1ff8 },
+ { 0x900f6, 0x85a8 },
+ { 0x900f7, 0x1e8 },
+ { 0x900f8, 0x68 },
+ { 0x900f9, 0x798 },
+ { 0x900fa, 0x16a },
+ { 0x900fb, 0x78 },
+ { 0x900fc, 0x7a0 },
+ { 0x900fd, 0x16a },
+ { 0x900fe, 0x68 },
+ { 0x900ff, 0x790 },
+ { 0x90100, 0x16a },
+ { 0x90101, 0x8 },
+ { 0x90102, 0x8b10 },
+ { 0x90103, 0x168 },
+ { 0x90104, 0x8 },
+ { 0x90105, 0xab10 },
+ { 0x90106, 0x168 },
+ { 0x90107, 0xa },
+ { 0x90108, 0x408 },
+ { 0x90109, 0x169 },
+ { 0x9010a, 0x58 },
+ { 0x9010b, 0x0 },
+ { 0x9010c, 0x68 },
+ { 0x9010d, 0x0 },
+ { 0x9010e, 0x408 },
+ { 0x9010f, 0x169 },
+ { 0x90110, 0x0 },
+ { 0x90111, 0x8b10 },
+ { 0x90112, 0x168 },
+ { 0x90113, 0x0 },
+ { 0x90114, 0xab10 },
+ { 0x90115, 0x168 },
+ { 0x90116, 0x0 },
+ { 0x90117, 0x1d8 },
+ { 0x90118, 0x169 },
+ { 0x90119, 0x80 },
+ { 0x9011a, 0x790 },
+ { 0x9011b, 0x16a },
+ { 0x9011c, 0x18 },
+ { 0x9011d, 0x7aa },
+ { 0x9011e, 0x6a },
+ { 0x9011f, 0xa },
+ { 0x90120, 0x0 },
+ { 0x90121, 0x1e9 },
+ { 0x90122, 0x8 },
+ { 0x90123, 0x8080 },
+ { 0x90124, 0x108 },
+ { 0x90125, 0xf },
+ { 0x90126, 0x408 },
+ { 0x90127, 0x169 },
+ { 0x90128, 0xc },
+ { 0x90129, 0x0 },
+ { 0x9012a, 0x68 },
+ { 0x9012b, 0x9 },
+ { 0x9012c, 0x0 },
+ { 0x9012d, 0x1a9 },
+ { 0x9012e, 0x0 },
+ { 0x9012f, 0x408 },
+ { 0x90130, 0x169 },
+ { 0x90131, 0x0 },
+ { 0x90132, 0x8080 },
+ { 0x90133, 0x108 },
+ { 0x90134, 0x8 },
+ { 0x90135, 0x7aa },
+ { 0x90136, 0x6a },
+ { 0x90137, 0x0 },
+ { 0x90138, 0x8568 },
+ { 0x90139, 0x108 },
+ { 0x9013a, 0xb7 },
+ { 0x9013b, 0x790 },
+ { 0x9013c, 0x16a },
+ { 0x9013d, 0x1f },
+ { 0x9013e, 0x0 },
+ { 0x9013f, 0x68 },
+ { 0x90140, 0x8 },
+ { 0x90141, 0x8558 },
+ { 0x90142, 0x168 },
+ { 0x90143, 0xf },
+ { 0x90144, 0x408 },
+ { 0x90145, 0x169 },
+ { 0x90146, 0xc },
+ { 0x90147, 0x0 },
+ { 0x90148, 0x68 },
+ { 0x90149, 0x0 },
+ { 0x9014a, 0x408 },
+ { 0x9014b, 0x169 },
+ { 0x9014c, 0x0 },
+ { 0x9014d, 0x8558 },
+ { 0x9014e, 0x168 },
+ { 0x9014f, 0x8 },
+ { 0x90150, 0x3c8 },
+ { 0x90151, 0x1a9 },
+ { 0x90152, 0x3 },
+ { 0x90153, 0x370 },
+ { 0x90154, 0x129 },
+ { 0x90155, 0x20 },
+ { 0x90156, 0x2aa },
+ { 0x90157, 0x9 },
+ { 0x90158, 0x0 },
+ { 0x90159, 0x400 },
+ { 0x9015a, 0x10e },
+ { 0x9015b, 0x8 },
+ { 0x9015c, 0xe8 },
+ { 0x9015d, 0x109 },
+ { 0x9015e, 0x0 },
+ { 0x9015f, 0x8140 },
+ { 0x90160, 0x10c },
+ { 0x90161, 0x10 },
+ { 0x90162, 0x8138 },
+ { 0x90163, 0x10c },
+ { 0x90164, 0x8 },
+ { 0x90165, 0x7c8 },
+ { 0x90166, 0x101 },
+ { 0x90167, 0x8 },
+ { 0x90168, 0x0 },
+ { 0x90169, 0x8 },
+ { 0x9016a, 0x8 },
+ { 0x9016b, 0x448 },
+ { 0x9016c, 0x109 },
+ { 0x9016d, 0xf },
+ { 0x9016e, 0x7c0 },
+ { 0x9016f, 0x109 },
+ { 0x90170, 0x0 },
+ { 0x90171, 0xe8 },
+ { 0x90172, 0x109 },
+ { 0x90173, 0x47 },
+ { 0x90174, 0x630 },
+ { 0x90175, 0x109 },
+ { 0x90176, 0x8 },
+ { 0x90177, 0x618 },
+ { 0x90178, 0x109 },
+ { 0x90179, 0x8 },
+ { 0x9017a, 0xe0 },
+ { 0x9017b, 0x109 },
+ { 0x9017c, 0x0 },
+ { 0x9017d, 0x7c8 },
+ { 0x9017e, 0x109 },
+ { 0x9017f, 0x8 },
+ { 0x90180, 0x8140 },
+ { 0x90181, 0x10c },
+ { 0x90182, 0x0 },
+ { 0x90183, 0x1 },
+ { 0x90184, 0x8 },
+ { 0x90185, 0x8 },
+ { 0x90186, 0x4 },
+ { 0x90187, 0x8 },
+ { 0x90188, 0x8 },
+ { 0x90189, 0x7c8 },
+ { 0x9018a, 0x101 },
+ { 0x90006, 0x0 },
+ { 0x90007, 0x0 },
+ { 0x90008, 0x8 },
+ { 0x90009, 0x0 },
+ { 0x9000a, 0x0 },
+ { 0x9000b, 0x0 },
+ { 0xd00e7, 0x400 },
+ { 0x90017, 0x0 },
+ { 0x9001f, 0x2a },
+ { 0x90026, 0x6a },
+ { 0x400d0, 0x0 },
+ { 0x400d1, 0x101 },
+ { 0x400d2, 0x105 },
+ { 0x400d3, 0x107 },
+ { 0x400d4, 0x10f },
+ { 0x400d5, 0x202 },
+ { 0x400d6, 0x20a },
+ { 0x400d7, 0x20b },
+ { 0x2003a, 0x2 },
+ { 0x2000b, 0x64 },
+ { 0x2000c, 0xc8 },
+ { 0x2000d, 0x7d0 },
+ { 0x2000e, 0x2c },
+ { 0x12000b, 0xc },
+ { 0x12000c, 0x19 },
+ { 0x12000d, 0xfa },
+ { 0x12000e, 0x10 },
+ { 0x22000b, 0x3 },
+ { 0x22000c, 0x6 },
+ { 0x22000d, 0x3e },
+ { 0x22000e, 0x10 },
+ { 0x9000c, 0x0 },
+ { 0x9000d, 0x173 },
+ { 0x9000e, 0x60 },
+ { 0x9000f, 0x6110 },
+ { 0x90010, 0x2152 },
+ { 0x90011, 0xdfbd },
+ { 0x90012, 0x60 },
+ { 0x90013, 0x6152 },
+ { 0x20010, 0x5a },
+ { 0x20011, 0x3 },
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+ { 0x40080, 0xe0 },
+ { 0x40081, 0x12 },
+ { 0x40082, 0xe0 },
+ { 0x40083, 0x12 },
+ { 0x40084, 0xe0 },
+ { 0x40085, 0x12 },
+ { 0x140080, 0xe0 },
+ { 0x140081, 0x12 },
+ { 0x140082, 0xe0 },
+ { 0x140083, 0x12 },
+ { 0x140084, 0xe0 },
+ { 0x140085, 0x12 },
+ { 0x240080, 0xe0 },
+ { 0x240081, 0x12 },
+ { 0x240082, 0xe0 },
+ { 0x240083, 0x12 },
+ { 0x240084, 0xe0 },
+ { 0x240085, 0x12 },
+ { 0x400fd, 0xf },
+ { 0x10011, 0x1 },
+ { 0x10012, 0x1 },
+ { 0x10013, 0x180 },
+ { 0x10018, 0x1 },
+ { 0x10002, 0x6209 },
+ { 0x100b2, 0x1 },
+ { 0x101b4, 0x1 },
+ { 0x102b4, 0x1 },
+ { 0x103b4, 0x1 },
+ { 0x104b4, 0x1 },
+ { 0x105b4, 0x1 },
+ { 0x106b4, 0x1 },
+ { 0x107b4, 0x1 },
+ { 0x108b4, 0x1 },
+ { 0x11011, 0x1 },
+ { 0x11012, 0x1 },
+ { 0x11013, 0x180 },
+ { 0x11018, 0x1 },
+ { 0x11002, 0x6209 },
+ { 0x110b2, 0x1 },
+ { 0x111b4, 0x1 },
+ { 0x112b4, 0x1 },
+ { 0x113b4, 0x1 },
+ { 0x114b4, 0x1 },
+ { 0x115b4, 0x1 },
+ { 0x116b4, 0x1 },
+ { 0x117b4, 0x1 },
+ { 0x118b4, 0x1 },
+ { 0x12011, 0x1 },
+ { 0x12012, 0x1 },
+ { 0x12013, 0x180 },
+ { 0x12018, 0x1 },
+ { 0x12002, 0x6209 },
+ { 0x120b2, 0x1 },
+ { 0x121b4, 0x1 },
+ { 0x122b4, 0x1 },
+ { 0x123b4, 0x1 },
+ { 0x124b4, 0x1 },
+ { 0x125b4, 0x1 },
+ { 0x126b4, 0x1 },
+ { 0x127b4, 0x1 },
+ { 0x128b4, 0x1 },
+ { 0x13011, 0x1 },
+ { 0x13012, 0x1 },
+ { 0x13013, 0x180 },
+ { 0x13018, 0x1 },
+ { 0x13002, 0x6209 },
+ { 0x130b2, 0x1 },
+ { 0x131b4, 0x1 },
+ { 0x132b4, 0x1 },
+ { 0x133b4, 0x1 },
+ { 0x134b4, 0x1 },
+ { 0x135b4, 0x1 },
+ { 0x136b4, 0x1 },
+ { 0x137b4, 0x1 },
+ { 0x138b4, 0x1 },
+ { 0x2003a, 0x2 },
+ { 0xc0080, 0x2 },
+ { 0xd0000, 0x1 },
+};
+
+struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
+ {
+ /* P0 3200mts 1D */
+ .drate = 3200,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
+ },
+ {
+ /* P1 400mts 1D */
+ .drate = 400,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp1_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
+ },
+ {
+ /* P1 100mts 1D */
+ .drate = 100,
+ .fw_type = FW_1D_IMAGE,
+ .fsp_cfg = lpddr4_fsp2_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
+ },
+ {
+ /* P0 3200mts 2D */
+ .drate = 3200,
+ .fw_type = FW_2D_IMAGE,
+ .fsp_cfg = lpddr4_fsp0_2d_cfg,
+ .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
+ },
+};
+
+/* lpddr4 timing config params on EVK board */
+struct dram_timing_info dram_timing = {
+ .ddrc_cfg = lpddr4_ddrc_cfg,
+ .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
+ .ddrphy_cfg = lpddr4_ddrphy_cfg,
+ .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
+ .fsp_msg = lpddr4_dram_fsp_msg,
+ .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
+ .ddrphy_trained_csr = ddr_ddrphy_trained_csr,
+ .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
+ .ddrphy_pie = lpddr4_phy_pie,
+ .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
+ .fsp_table = { 3200, 400, 100, },
+};
diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c
new file mode 100644
index 0000000..c32a06f
--- /dev/null
+++ b/board/ronetix/imx8mq-cm/spl.c
@@ -0,0 +1,165 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ *
+ */
+
+#include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/imx8mq_pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/clock.h>
+#include <asm/mach-imx/gpio.h>
+#include <asm/mach-imx/mxc_i2c.h>
+#include <fsl_esdhc_imx.h>
+#include <linux/delay.h>
+#include <spl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void spl_dram_init(void)
+{
+ /* ddr init */
+ ddr_init(&dram_timing);
+}
+
+#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
+#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+ int ret = 0;
+
+ switch (cfg->esdhc_base) {
+ case USDHC1_BASE_ADDR:
+ ret = 1;
+ break;
+ case USDHC2_BASE_ADDR:
+ ret = gpio_get_value(USDHC2_CD_GPIO);
+ return ret;
+ }
+
+ return 1;
+}
+
+#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
+ PAD_CTL_FSEL2)
+#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
+
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+ IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+ IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
+};
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+ {USDHC1_BASE_ADDR, 0, 8},
+ {USDHC2_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_init(struct bd_info *bis)
+{
+ int i, ret;
+ /*
+ * According to the board_mmc_init() the following map is done:
+ * (U-Boot device node) (Physical Port)
+ * mmc0 USDHC1
+ * mmc1 USDHC2
+ */
+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+ switch (i) {
+ case 0:
+ init_clk_usdhc(0);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
+ ARRAY_SIZE(usdhc1_pads));
+ gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
+ gpio_direction_output(USDHC1_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC1_PWR_GPIO, 1);
+ break;
+ case 1:
+ init_clk_usdhc(1);
+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
+ imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
+ ARRAY_SIZE(usdhc2_pads));
+ gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
+ gpio_direction_output(USDHC2_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC2_PWR_GPIO, 1);
+ break;
+ default:
+ printf("Warning: you configured more USDHC controllers(%d)"
+ " than supported by the board\n", i + 1);
+ return -EINVAL;
+ }
+
+ ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+void spl_board_init(void)
+{
+ puts("Normal Boot\n");
+}
+
+void board_init_f(ulong dummy)
+{
+ int ret;
+
+ /* Clear global data */
+ memset((void *)gd, 0, sizeof(gd_t));
+
+ arch_cpu_init();
+
+ init_uart_clk(0);
+
+ board_early_init_f();
+
+ timer_init();
+
+ preloader_console_init();
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ ret = spl_init();
+ if (ret) {
+ debug("spl_init() failed: %d\n", ret);
+ hang();
+ }
+
+ enable_tzc380();
+
+ /* DDR initialization */
+ spl_dram_init();
+
+ board_init_r(NULL, 0);
+}
diff --git a/board/samsung/arndale/arndale_spl.c b/board/samsung/arndale/arndale_spl.c
index baa5048..6ad0273 100644
--- a/board/samsung/arndale/arndale_spl.c
+++ b/board/samsung/arndale/arndale_spl.c
@@ -10,7 +10,7 @@
/* Parameters of early board initialization in SPL */
static struct spl_machine_param machine_param
- __attribute__((section(".machine_param"))) = {
+ __section(".machine_param") = {
.signature = SIGNATURE,
.version = 1,
.params = "vmubfasirM",
diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c
index 4463cdc..1318ea7 100644
--- a/board/samsung/common/exynos5-dt.c
+++ b/board/samsung/common/exynos5-dt.c
@@ -126,7 +126,7 @@
.index = 0,
};
-int usb_gadget_handle_interrupts(void)
+int usb_gadget_handle_interrupts(int index)
{
dwc3_uboot_handle_interrupt(0);
return 0;
diff --git a/board/samsung/smdk5250/smdk5250_spl.c b/board/samsung/smdk5250/smdk5250_spl.c
index eb25dfc..b0ef34d 100644
--- a/board/samsung/smdk5250/smdk5250_spl.c
+++ b/board/samsung/smdk5250/smdk5250_spl.c
@@ -12,7 +12,7 @@
/* Parameters of early board initialization in SPL */
static struct spl_machine_param machine_param
- __attribute__((section(".machine_param"))) = {
+ __section(".machine_param") = {
.signature = SIGNATURE,
.version = 1,
.params = "vmubfasirM",
diff --git a/board/samsung/smdk5420/smdk5420_spl.c b/board/samsung/smdk5420/smdk5420_spl.c
index 72748ec..84126f5 100644
--- a/board/samsung/smdk5420/smdk5420_spl.c
+++ b/board/samsung/smdk5420/smdk5420_spl.c
@@ -12,7 +12,7 @@
/* Parameters of early board initialization in SPL */
static struct spl_machine_param machine_param
- __attribute__((section(".machine_param"))) = {
+ __section(".machine_param") = {
.signature = SIGNATURE,
.version = 1,
.params = "vmubfasirM",
diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c
index 902b99e..dcd7345 100644
--- a/board/sandbox/sandbox.c
+++ b/board/sandbox/sandbox.c
@@ -14,6 +14,9 @@
#include <asm/global_data.h>
#include <asm/test.h>
#include <asm/u-boot-sandbox.h>
+#include <malloc.h>
+
+#include <extension_board.h>
/*
* Pointer to initial global data area
@@ -79,6 +82,26 @@
return fdt_add_mem_rsv(fdt, 0x00d02000, 0x4000);
}
+#ifdef CONFIG_CMD_EXTENSION
+int extension_board_scan(struct list_head *extension_list)
+{
+ struct extension *extension;
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->overlay, sizeof(extension->overlay), "overlay%d.dtbo", i);
+ snprintf(extension->name, sizeof(extension->name), "extension board %d", i);
+ snprintf(extension->owner, sizeof(extension->owner), "sandbox");
+ snprintf(extension->version, sizeof(extension->version), "1.1");
+ snprintf(extension->other, sizeof(extension->other), "Fictionnal extension board");
+ list_add_tail(&extension->list, extension_list);
+ }
+
+ return i;
+}
+#endif
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c
index b512bdb..01fdfb5 100644
--- a/board/siemens/draco/board.c
+++ b/board/siemens/draco/board.c
@@ -41,7 +41,7 @@
#include <nand.h>
#ifdef CONFIG_SPL_BUILD
-static struct draco_baseboard_id __attribute__((section(".data"))) settings;
+static struct draco_baseboard_id __section(".data") settings;
#if DDR_PLL_FREQ == 303
#if !defined(CONFIG_TARGET_ETAMIN)
diff --git a/board/sifive/unleashed/Kconfig b/board/sifive/unleashed/Kconfig
index dbffd59..b3b4342 100644
--- a/board/sifive/unleashed/Kconfig
+++ b/board/sifive/unleashed/Kconfig
@@ -27,6 +27,8 @@
def_bool y
select SIFIVE_FU540
select ENV_IS_IN_SPI_FLASH
+ select BINMAN
+ select RESET_SIFIVE
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
diff --git a/board/sifive/unmatched/Kconfig b/board/sifive/unmatched/Kconfig
new file mode 100644
index 0000000..88b5883
--- /dev/null
+++ b/board/sifive/unmatched/Kconfig
@@ -0,0 +1,51 @@
+if TARGET_SIFIVE_UNMATCHED
+
+config SYS_BOARD
+ default "unmatched"
+
+config SYS_VENDOR
+ default "sifive"
+
+config SYS_CPU
+ default "fu740"
+
+config SYS_CONFIG_NAME
+ default "sifive-unmatched"
+
+config SYS_TEXT_BASE
+ default 0x80200000 if SPL
+ default 0x80000000 if !RISCV_SMODE
+ default 0x80200000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+ default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+ default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select SIFIVE_FU740
+ select SUPPORT_SPL
+ select RESET_SIFIVE
+ select BINMAN
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_GPT
+ imply PARTITION_TYPE_GUID
+ imply CMD_NET
+ imply CMD_PING
+ imply CMD_SF
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply PHY_LIB
+ imply PHY_MSCC
+ imply SYSRESET
+ imply SYSRESET_GPIO
+
+endif
diff --git a/board/sifive/unmatched/MAINTAINERS b/board/sifive/unmatched/MAINTAINERS
new file mode 100644
index 0000000..94c9510
--- /dev/null
+++ b/board/sifive/unmatched/MAINTAINERS
@@ -0,0 +1,9 @@
+SiFive HiFive Unmatched FU740 BOARD
+M: Paul Walmsley <paul.walmsley@sifive.com>
+M: Pragnesh Patel <pragnesh.patel@sifive.com>
+M: Green Wan <green.wan@sifive.com>
+S: Maintained
+F: board/sifive/unmatched/
+F: doc/board/sifive/hifive-unmatched-fu740.rst
+F: include/configs/sifive-unmatched.h
+F: configs/sifive_unmatched_defconfig
diff --git a/board/sifive/unmatched/Makefile b/board/sifive/unmatched/Makefile
new file mode 100644
index 0000000..6308c80
--- /dev/null
+++ b/board/sifive/unmatched/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020-2021 SiFive, Inc
+
+obj-y += unmatched.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/sifive/unmatched/spl.c b/board/sifive/unmatched/spl.c
new file mode 100644
index 0000000..5e1333b
--- /dev/null
+++ b/board/sifive/unmatched/spl.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020-2021 SiFive, Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <init.h>
+#include <spl.h>
+#include <misc.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+
+#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
+
+#define MODE_SELECT_REG 0x1000
+#define MODE_SELECT_SD 0xb
+#define MODE_SELECT_MASK GENMASK(3, 0)
+
+int spl_board_init_f(void)
+{
+ int ret;
+
+ ret = spl_soc_init();
+ if (ret) {
+ debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * GEMGXL init VSC8541 PHY reset sequence;
+ * leave pull-down active for 2ms
+ */
+ udelay(2000);
+ ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
+ if (ret) {
+ debug("gem_phy_reset gpio request failed: %d\n", ret);
+ return ret;
+ }
+
+ /* Set GPIO 12 (PHY NRESET) */
+ ret = gpio_direction_output(GEM_PHY_RESET, 1);
+ if (ret) {
+ debug("gem_phy_reset gpio direction set failed: %d\n", ret);
+ return ret;
+ }
+
+ udelay(1);
+
+ /* Reset PHY again to enter unmanaged mode */
+ gpio_set_value(GEM_PHY_RESET, 0);
+ udelay(1);
+ gpio_set_value(GEM_PHY_RESET, 1);
+ mdelay(15);
+
+ return 0;
+}
+
+u32 spl_boot_device(void)
+{
+ u32 mode_select = readl((void *)MODE_SELECT_REG);
+ u32 boot_device = mode_select & MODE_SELECT_MASK;
+
+ switch (boot_device) {
+ case MODE_SELECT_SD:
+ return BOOT_DEVICE_MMC1;
+ default:
+ debug("Unsupported boot device 0x%x but trying MMC1\n",
+ boot_device);
+ return BOOT_DEVICE_MMC1;
+ }
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+ /* boot using first FIT config */
+ return 0;
+}
+#endif
diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c
new file mode 100644
index 0000000..6d60559
--- /dev/null
+++ b/board/sifive/unmatched/unmatched.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020-2021, SiFive Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/cache.h>
+
+int board_init(void)
+{
+ int ret;
+
+ /* enable all cache ways */
+ ret = cache_enable_ways();
+ if (ret) {
+ debug("%s: could not enable cache ways\n", __func__);
+ return ret;
+ }
+ return 0;
+}
diff --git a/board/sipeed/maix/Kconfig b/board/sipeed/maix/Kconfig
index adf6abb..b1d7a7a 100644
--- a/board/sipeed/maix/Kconfig
+++ b/board/sipeed/maix/Kconfig
@@ -37,8 +37,6 @@
imply SIFIVE_CLINT
imply POWER_DOMAIN
imply SIMPLE_PM_BUS
- imply CLK_CCF
- imply CLK_COMPOSITE_CCF
imply CLK_K210
imply DM_RESET
imply RESET_SYSCON
diff --git a/board/sipeed/maix/maix.c b/board/sipeed/maix/maix.c
index cbcb23c..52e4fee 100644
--- a/board/sipeed/maix/maix.c
+++ b/board/sipeed/maix/maix.c
@@ -14,10 +14,10 @@
return CONFIG_SYS_SDRAM_SIZE;
}
-int board_init(void)
+static int sram_init(void)
{
int ret, i;
- const char * const banks[] = { "sram0", "sram1", "airam" };
+ const char * const banks[] = { "sram0", "sram1", "aisram" };
ofnode memory;
struct clk clk;
@@ -37,5 +37,15 @@
return ret;
}
+ return 0;
+}
+
+int board_early_init_f(void)
+{
+ return sram_init();
+}
+
+int board_init(void)
+{
return 0;
}
diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile
index c4e13f8..d96b789 100644
--- a/board/sunxi/Makefile
+++ b/board/sunxi/Makefile
@@ -11,3 +11,4 @@
obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o
+obj-$(CONFIG_CHIP_DIP_SCAN) += chip.o
diff --git a/board/sunxi/chip.c b/board/sunxi/chip.c
new file mode 100644
index 0000000..cde04be
--- /dev/null
+++ b/board/sunxi/chip.c
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ * Based on initial code from Maxime Ripard
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm.h>
+#include <w1.h>
+#include <w1-eeprom.h>
+#include <dm/device-internal.h>
+
+#include <asm/arch/gpio.h>
+
+#include <extension_board.h>
+
+#define for_each_w1_device(b, d) \
+ for (device_find_first_child(b, d); *d; device_find_next_child(d))
+
+#define dip_convert(field) \
+ ( \
+ (sizeof(field) == 1) ? field : \
+ (sizeof(field) == 2) ? be16_to_cpu(field) : \
+ (sizeof(field) == 4) ? be32_to_cpu(field) : \
+ -1 \
+ )
+
+#define DIP_MAGIC 0x50494843 /* CHIP */
+
+struct dip_w1_header {
+ u32 magic; /* CHIP */
+ u8 version; /* spec version */
+ u32 vendor_id;
+ u16 product_id;
+ u8 product_version;
+ char vendor_name[32];
+ char product_name[32];
+ u8 rsvd[36]; /* rsvd for future spec versions */
+ u8 data[16]; /* user data, per-dip specific */
+} __packed;
+
+int extension_board_scan(struct list_head *extension_list)
+{
+ struct extension *dip;
+ struct dip_w1_header w1_header;
+ struct udevice *bus, *dev;
+ u32 vid;
+ u16 pid;
+ int ret;
+
+ int num_dip = 0;
+
+ sunxi_gpio_set_pull(SUNXI_GPD(2), SUNXI_GPIO_PULL_UP);
+
+ ret = w1_get_bus(0, &bus);
+ if (ret) {
+ printf("one wire interface not found\n");
+ return 0;
+ }
+
+ for_each_w1_device(bus, &dev) {
+ if (w1_get_device_family(dev) != W1_FAMILY_DS2431)
+ continue;
+
+ ret = device_probe(dev);
+ if (ret) {
+ printf("Couldn't probe device %s: error %d",
+ dev->name, ret);
+ continue;
+ }
+
+ w1_eeprom_read_buf(dev, 0, (u8 *)&w1_header, sizeof(w1_header));
+
+ if (w1_header.magic != DIP_MAGIC)
+ continue;
+
+ vid = dip_convert(w1_header.vendor_id);
+ pid = dip_convert(w1_header.product_id);
+
+ printf("DIP: %s (0x%x) from %s (0x%x)\n",
+ w1_header.product_name, pid,
+ w1_header.vendor_name, vid);
+
+ dip = calloc(1, sizeof(struct extension));
+ if (!dip) {
+ printf("Error in memory allocation\n");
+ return num_dip;
+ }
+
+ snprintf(dip->overlay, sizeof(dip->overlay), "dip-%x-%x.dtbo",
+ vid, pid);
+ strncpy(dip->name, w1_header.product_name, 32);
+ strncpy(dip->owner, w1_header.vendor_name, 32);
+ list_add_tail(&dip->list, extension_list);
+ num_dip++;
+ }
+ return num_dip;
+}
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index bc1657e..5c156a5 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -44,6 +44,7 @@
#include <env_internal.h>
#include <watchdog.h>
#include "../common/board_detect.h"
+#include "../common/cape_detect.h"
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -77,8 +78,10 @@
void do_board_detect(void)
{
enable_i2c0_pin_mux();
+ enable_i2c2_pin_mux();
#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED2, CONFIG_SYS_OMAP24_I2C_SLAVE2);
#endif
if (ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
CONFIG_EEPROM_CHIP_ADDRESS))
@@ -957,7 +960,8 @@
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
diff --git a/board/ti/am335x/board.h b/board/ti/am335x/board.h
index 48df914..c296211 100644
--- a/board/ti/am335x/board.h
+++ b/board/ti/am335x/board.h
@@ -93,5 +93,6 @@
void enable_uart4_pin_mux(void);
void enable_uart5_pin_mux(void);
void enable_i2c0_pin_mux(void);
+void enable_i2c2_pin_mux(void);
void enable_board_pin_mux(void);
#endif
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index 03adcd2..e450ff6 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -124,6 +124,14 @@
{-1},
};
+static struct module_pin_mux i2c2_pin_mux[] = {
+ {OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE |
+ PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_DATA */
+ {OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE |
+ PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* I2C_SCLK */
+ {-1},
+};
+
static struct module_pin_mux spi0_pin_mux[] = {
{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
@@ -308,6 +316,11 @@
configure_module_pin_mux(i2c0_pin_mux);
}
+void enable_i2c2_pin_mux(void)
+{
+ configure_module_pin_mux(i2c2_pin_mux);
+}
+
/*
* The AM335x GP EVM, if daughter card(s) are connected, can have 8
* different profiles. These profiles determine what peripherals are
@@ -367,6 +380,7 @@
#else
configure_module_pin_mux(mmc1_pin_mux);
#endif
+ configure_module_pin_mux(i2c2_pin_mux);
} else if (board_is_gp_evm()) {
/* General Purpose EVM */
unsigned short profile = detect_daughter_board_profile();
@@ -411,6 +425,7 @@
#else
configure_module_pin_mux(mmc1_pin_mux);
#endif
+ configure_module_pin_mux(i2c2_pin_mux);
} else if (board_is_pb()) {
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c
index e9febb9..a71b588 100644
--- a/board/ti/am43xx/board.c
+++ b/board/ti/am43xx/board.c
@@ -896,7 +896,8 @@
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 73063fa..399a2e5 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -43,6 +43,7 @@
#include <hang.h>
#include "../common/board_detect.h"
+#include "../common/cape_detect.h"
#include "mux_data.h"
#ifdef CONFIG_SUPPORT_EMMC_BOOT
@@ -1198,7 +1199,8 @@
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig
new file mode 100644
index 0000000..d4ec759
--- /dev/null
+++ b/board/ti/am64x/Kconfig
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+
+choice
+ prompt "K3 AM64 based boards"
+ optional
+
+config TARGET_AM642_A53_EVM
+ bool "TI K3 based AM642 EVM running on A53"
+ select ARM64
+ select SOC_K3_AM642
+ imply BOARD
+ imply SPL_BOARD
+ imply TI_I2C_BOARD_DETECT
+
+config TARGET_AM642_R5_EVM
+ bool "TI K3 based AM642 EVM running on R5"
+ select CPU_V7R
+ select SYS_THUMB_BUILD
+ select K3_LOAD_SYSFW
+ select SOC_K3_AM642
+ select RAM
+ select SPL_RAM
+ select K3_DDRSS
+ imply SYS_K3_SPL_ATF
+ imply TI_I2C_BOARD_DETECT
+
+endchoice
+
+if TARGET_AM642_A53_EVM
+
+config SYS_BOARD
+ default "am64x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am64x_evm"
+
+source "board/ti/common/Kconfig"
+
+endif
+
+if TARGET_AM642_R5_EVM
+
+config SYS_BOARD
+ default "am64x"
+
+config SYS_VENDOR
+ default "ti"
+
+config SYS_CONFIG_NAME
+ default "am64x_evm"
+
+config SPL_LDSCRIPT
+ default "arch/arm/mach-omap2/u-boot-spl.lds"
+
+source "board/ti/common/Kconfig"
+
+endif
diff --git a/board/ti/am64x/MAINTAINERS b/board/ti/am64x/MAINTAINERS
new file mode 100644
index 0000000..d384a33
--- /dev/null
+++ b/board/ti/am64x/MAINTAINERS
@@ -0,0 +1,8 @@
+AM64x BOARD
+M: Dave Gerlach <d-gerlach@ti.com>
+M: Lokesh Vutla <lokeshvutla@ti.com>
+S: Maintained
+F: board/ti/am64x/
+F: include/configs/am64x_evm.h
+F: configs/am64x_evm_r5_defconfig
+F: configs/am64x_evm_a53_defconfig
diff --git a/board/ti/am64x/Makefile b/board/ti/am64x/Makefile
new file mode 100644
index 0000000..8b98e6f
--- /dev/null
+++ b/board/ti/am64x/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+# Keerthy <j-keerthy@ti.com>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += evm.o
diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
new file mode 100644
index 0000000..cdbb9a8
--- /dev/null
+++ b/board/ti/am64x/evm.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board specific initialization for AM642 EVM
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <spl.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/sys_proto.h>
+#include <env.h>
+
+#include "../common/board_detect.h"
+
+#define board_is_am64x_gpevm() board_ti_k3_is("AM64-GPEVM")
+#define board_is_am64x_skevm() board_ti_k3_is("AM64-SKEVM")
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = 0x80000000;
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ /* Bank 0 declares the memory available in the DDR low region */
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = 0x80000000;
+ gd->ram_size = 0x80000000;
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_LOAD_FIT)
+int board_fit_config_name_match(const char *name)
+{
+ bool eeprom_read = board_ti_was_eeprom_read();
+
+ if (!eeprom_read || board_is_am64x_gpevm()) {
+ if (!strcmp(name, "k3-am642-r5-evm") || !strcmp(name, "k3-am642-evm"))
+ return 0;
+ } else if (board_is_am64x_skevm()) {
+ if (!strcmp(name, "k3-am642-r5-sk") || !strcmp(name, "k3-am642-sk"))
+ return 0;
+ }
+
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_TI_I2C_BOARD_DETECT
+int do_board_detect(void)
+{
+ int ret;
+
+ ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS);
+ if (ret) {
+ printf("EEPROM not available at 0x%02x, trying to read at 0x%02x\n",
+ CONFIG_EEPROM_CHIP_ADDRESS, CONFIG_EEPROM_CHIP_ADDRESS + 1);
+ ret = ti_i2c_eeprom_am6_get_base(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS + 1);
+ if (ret)
+ pr_err("Reading on-board EEPROM at 0x%02x failed %d\n",
+ CONFIG_EEPROM_CHIP_ADDRESS + 1, ret);
+ }
+
+ return ret;
+}
+
+int checkboard(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ if (!do_board_detect())
+ printf("Board: %s rev %s\n", ep->name, ep->version);
+
+ return 0;
+}
+
+#ifdef CONFIG_BOARD_LATE_INIT
+static void setup_board_eeprom_env(void)
+{
+ char *name = "am64x_gpevm";
+
+ if (do_board_detect())
+ goto invalid_eeprom;
+
+ if (board_is_am64x_gpevm())
+ name = "am64x_gpevm";
+ else if (board_is_am64x_skevm())
+ name = "am64x_skevm";
+ else
+ printf("Unidentified board claims %s in eeprom header\n",
+ board_ti_get_name());
+
+invalid_eeprom:
+ set_board_info_env_am6(name);
+}
+
+static void setup_serial(void)
+{
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+ unsigned long board_serial;
+ char *endp;
+ char serial_string[17] = { 0 };
+
+ if (env_get("serial#"))
+ return;
+
+ board_serial = simple_strtoul(ep->serial, &endp, 16);
+ if (*endp != '\0') {
+ pr_err("Error: Can't set serial# to %s\n", ep->serial);
+ return;
+ }
+
+ snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
+ env_set("serial#", serial_string);
+}
+#endif
+#endif
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
+ struct ti_am6_eeprom *ep = TI_AM6_EEPROM_DATA;
+
+ setup_board_eeprom_env();
+ setup_serial();
+ /*
+ * The first MAC address for ethernet a.k.a. ethernet0 comes from
+ * efuse populated via the am654 gigabit eth switch subsystem driver.
+ * All the other ones are populated via EEPROM, hence continue with
+ * an index of 1.
+ */
+ board_ti_am6_set_ethaddr(1, ep->mac_addr_cnt);
+ }
+
+ return 0;
+}
+#endif
+
+#define CTRLMMR_USB0_PHY_CTRL 0x43004008
+#define CORE_VOLTAGE 0x80000000
+
+#ifdef CONFIG_SPL_BOARD_INIT
+void spl_board_init(void)
+{
+ u32 val;
+ /* Set USB PHY core voltage to 0.85V */
+ val = readl(CTRLMMR_USB0_PHY_CTRL);
+ val &= ~(CORE_VOLTAGE);
+ writel(val, CTRLMMR_USB0_PHY_CTRL);
+}
+#endif
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index 9ead7ca..49edd98 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -16,6 +16,12 @@
default 0x50
depends on TI_I2C_BOARD_DETECT
+config CAPE_EEPROM_BUS_NUM
+ int "Cape EEPROM's I2C bus address"
+ range 0 8
+ default 2
+ depends on CMD_EXTENSION
+
config TI_COMMON_CMD_OPTIONS
bool "Enable cmd options on TI platforms"
imply CMD_ASKENV
diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile
index cb97f22..3172d87b 100644
--- a/board/ti/common/Makefile
+++ b/board/ti/common/Makefile
@@ -2,3 +2,4 @@
# Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o
+obj-${CONFIG_CMD_EXTENSION} += cape_detect.o
diff --git a/board/ti/common/cape_detect.c b/board/ti/common/cape_detect.c
new file mode 100644
index 0000000..2e6105c
--- /dev/null
+++ b/board/ti/common/cape_detect.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <i2c.h>
+#include <extension_board.h>
+
+#include "cape_detect.h"
+
+static void sanitize_field(char *text, size_t size)
+{
+ char *c = NULL;
+
+ for (c = text; c < text + (int)size; c++) {
+ if (*c == 0xFF)
+ *c = 0;
+ }
+}
+
+int extension_board_scan(struct list_head *extension_list)
+{
+ struct extension *cape;
+ struct am335x_cape_eeprom_id eeprom_header;
+
+ int num_capes = 0;
+ int ret, i;
+ struct udevice *dev;
+ unsigned char addr;
+
+ char process_cape_part_number[17] = {'0'};
+ char process_cape_version[5] = {'0'};
+ uint8_t cursor = 0;
+
+ for (addr = CAPE_EEPROM_FIRST_ADDR; addr <= CAPE_EEPROM_LAST_ADDR; addr++) {
+ ret = i2c_get_chip_for_busnum(CONFIG_CAPE_EEPROM_BUS_NUM, addr, 1, &dev);
+ if (ret)
+ continue;
+
+ /* Move the read cursor to the beginning of the EEPROM */
+ dm_i2c_write(dev, 0, &cursor, 1);
+ ret = dm_i2c_read(dev, 0, (uint8_t *)&eeprom_header,
+ sizeof(struct am335x_cape_eeprom_id));
+ if (ret) {
+ printf("Cannot read i2c EEPROM\n");
+ continue;
+ }
+
+ if (eeprom_header.header != CAPE_MAGIC)
+ continue;
+
+ sanitize_field(eeprom_header.board_name, sizeof(eeprom_header.board_name));
+ sanitize_field(eeprom_header.version, sizeof(eeprom_header.version));
+ sanitize_field(eeprom_header.manufacturer, sizeof(eeprom_header.manufacturer));
+ sanitize_field(eeprom_header.part_number, sizeof(eeprom_header.part_number));
+
+ /* Process cape part_number */
+ memset(process_cape_part_number, 0, sizeof(process_cape_part_number));
+ strncpy(process_cape_part_number, eeprom_header.part_number, 16);
+ /* Some capes end with '.' */
+ for (i = 15; i >= 0; i--) {
+ if (process_cape_part_number[i] == '.')
+ process_cape_part_number[i] = '\0';
+ else
+ break;
+ }
+
+ /* Process cape version */
+ memset(process_cape_version, 0, sizeof(process_cape_version));
+ strncpy(process_cape_version, eeprom_header.version, 4);
+ for (i = 0; i < 4; i++) {
+ if (process_cape_version[i] == 0)
+ process_cape_version[i] = '0';
+ }
+
+ printf("BeagleBone Cape: %s (0x%x)\n", eeprom_header.board_name, addr);
+
+ cape = calloc(1, sizeof(struct extension));
+ if (!cape) {
+ printf("Error in memory allocation\n");
+ return num_capes;
+ }
+
+ snprintf(cape->overlay, sizeof(cape->overlay), "%s-%s.dtbo",
+ process_cape_part_number, process_cape_version);
+ strncpy(cape->name, eeprom_header.board_name, 32);
+ strncpy(cape->version, process_cape_version, 4);
+ strncpy(cape->owner, eeprom_header.manufacturer, 16);
+ list_add_tail(&cape->list, extension_list);
+ num_capes++;
+ }
+ return num_capes;
+}
diff --git a/board/ti/common/cape_detect.h b/board/ti/common/cape_detect.h
new file mode 100644
index 0000000..b0d5c9f
--- /dev/null
+++ b/board/ti/common/cape_detect.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#ifndef __CAPE_DETECT_H
+#define __CAPE_DETECT_H
+
+struct am335x_cape_eeprom_id {
+ unsigned int header;
+ char eeprom_rev[2];
+ char board_name[32];
+ char version[4];
+ char manufacturer[16];
+ char part_number[16];
+};
+
+#define CAPE_EEPROM_FIRST_ADDR 0x54
+#define CAPE_EEPROM_LAST_ADDR 0x57
+
+#define CAPE_EEPROM_ADDR_LEN 0x10
+
+#define CAPE_MAGIC 0xEE3355AA
+
+int extension_board_scan(struct list_head *extension_list);
+
+#endif /* __CAPE_DETECT_H */
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 05f251f..23e8005 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -1065,7 +1065,8 @@
#endif
#ifdef CONFIG_TI_SECURE_DEVICE
-void board_fit_image_post_process(void **p_image, size_t *p_size)
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size)
{
secure_boot_verify_image(p_image, p_size);
}
diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig
index 2cbe2b2..c28752a 100644
--- a/board/ti/j721e/Kconfig
+++ b/board/ti/j721e/Kconfig
@@ -23,7 +23,7 @@
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
- select K3_J721E_DDRSS
+ select K3_DDRSS
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
@@ -43,7 +43,7 @@
select K3_LOAD_SYSFW
select RAM
select SPL_RAM
- select K3_J721E_DDRSS
+ select K3_DDRSS
imply SYS_K3_SPL_ATF
imply TI_I2C_BOARD_DETECT
diff --git a/board/ti/j721e/README b/board/ti/j721e/README
index c33afa4..b1c9145 100644
--- a/board/ti/j721e/README
+++ b/board/ti/j721e/README
@@ -73,12 +73,12 @@
| | | | +-------------+ | | |
| | |<--------|---| Start A72 | | | |
| | | | | and jump to | | | |
-| | | | | next image | | | |
+| | | | | DM fw image | | | |
| | | | +-------------+ | | |
| | | | | +-----------+ | |
| | |---------|-----------------------|---->| Reset rls | | |
| | | | | +-----------+ | |
-| | DMSC | | | : | |
+| | TIFS | | | : | |
| |Services | | | +-----------+ | |
| | |<--------|-----------------------|---->|*ATF/OPTEE*| | |
| | | | | +-----------+ | |
@@ -154,7 +154,7 @@
4.2. A72:
$ make CROSS_COMPILE=aarch64-linux-gnu- j721e_evm_a72_defconfig O=/tmp/a72
-$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin O=/tmp/a72
+$ make CROSS_COMPILE=aarch64-linux-gnu- ATF=<path to ATF dir>/build/k3/generic/release/bl31.bin TEE=<path to OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<path to DM firmware image> O=/tmp/a72
Target Images
--------------
@@ -197,6 +197,9 @@
| | A72 OPTEE | |
| +-------------------+ |
| | | |
+ | | R5 DM FW | |
+ | +-------------------+ |
+ | | | |
| | A72 SPL | |
| +-------------------+ |
| | | |
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 475628b..92b61d8 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -378,14 +378,12 @@
int i, id, macid = 0;
struct xilinx_board_description *desc;
phys_size_t bootm_size = gd->ram_size;
- struct bd_info *bd = gd->bd;
- if (!CONFIG_IS_ENABLED(MICROBLAZE) && bd->bi_dram[0].start) {
+ if (!CONFIG_IS_ENABLED(MICROBLAZE)) {
ulong scriptaddr;
scriptaddr = env_get_hex("scriptaddr", 0);
- ret |= env_set_hex("scriptaddr",
- bd->bi_dram[0].start + scriptaddr);
+ ret |= env_set_hex("scriptaddr", gd->ram_base + scriptaddr);
}
if (CONFIG_IS_ENABLED(ARCH_ZYNQ) || CONFIG_IS_ENABLED(MICROBLAZE))
diff --git a/board/xilinx/common/fru_ops.c b/board/xilinx/common/fru_ops.c
index 44f0913..6ed63bb 100644
--- a/board/xilinx/common/fru_ops.c
+++ b/board/xilinx/common/fru_ops.c
@@ -14,7 +14,7 @@
#include "fru.h"
-struct fru_table fru_data __section(.data);
+struct fru_table fru_data __section(".data");
static u16 fru_cal_area_len(u8 len)
{
diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c
index e2f9d13..6045eb2 100644
--- a/board/xilinx/versal/board.c
+++ b/board/xilinx/versal/board.c
@@ -9,6 +9,7 @@
#include <env.h>
#include <fdtdec.h>
#include <init.h>
+#include <env_internal.h>
#include <log.h>
#include <malloc.h>
#include <time.h>
@@ -129,7 +130,7 @@
switch (bootmode) {
case USB_MODE:
puts("USB_MODE\n");
- mode = "dfu_usb";
+ mode = "usb_dfu0 usb_dfu1";
break;
case JTAG_MODE:
puts("JTAG_MODE\n");
@@ -245,3 +246,32 @@
void reset_cpu(void)
{
}
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u32 bootmode = versal_get_bootmode();
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (bootmode) {
+ case EMMC_MODE:
+ case SD_MODE:
+ case SD1_LSHFT_MODE:
+ case SD_MODE1:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+ return ENVL_EXT4;
+ return ENVL_UNKNOWN;
+ case OSPI_MODE:
+ case QSPI_MODE_24BIT:
+ case QSPI_MODE_32BIT:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ return ENVL_UNKNOWN;
+ case JTAG_MODE:
+ default:
+ return ENVL_NOWHERE;
+ }
+}
diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 7533ddd..e2e9b3f 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -9,6 +9,7 @@
#include <log.h>
#include <dm/uclass.h>
#include <env.h>
+#include <env_internal.h>
#include <fdtdec.h>
#include <fpga.h>
#include <malloc.h>
@@ -119,3 +120,34 @@
return 0;
}
#endif
+
+enum env_location env_get_location(enum env_operation op, int prio)
+{
+ u32 bootmode = zynq_slcr_get_boot_mode() & ZYNQ_BM_MASK;
+
+ if (prio)
+ return ENVL_UNKNOWN;
+
+ switch (bootmode) {
+ case ZYNQ_BM_SD:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
+ return ENVL_FAT;
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
+ return ENVL_EXT4;
+ return ENVL_UNKNOWN;
+ case ZYNQ_BM_NAND:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
+ return ENVL_NAND;
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
+ return ENVL_UBI;
+ return ENVL_UNKNOWN;
+ case ZYNQ_BM_NOR:
+ case ZYNQ_BM_QSPI:
+ if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
+ return ENVL_SPI_FLASH;
+ return ENVL_UNKNOWN;
+ case ZYNQ_BM_JTAG:
+ default:
+ return ENVL_NOWHERE;
+ }
+}
diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c
index 23c12f4..d05f0b2 100644
--- a/board/xilinx/zynqmp/zynqmp.c
+++ b/board/xilinx/zynqmp/zynqmp.c
@@ -571,7 +571,7 @@
switch (bootmode) {
case USB_MODE:
puts("USB_MODE\n");
- mode = "usb";
+ mode = "usb_dfu0 usb_dfu1";
env_set("modeboot", "usb_dfu_spl");
break;
case JTAG_MODE:
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 9e8b692..f962bb7 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -332,6 +332,18 @@
help
Do FDT related setup before booting into the Operating System.
+config SUPPORT_EXTENSION_SCAN
+ bool
+
+config CMD_EXTENSION
+ bool "Extension board management command"
+ select CMD_FDT
+ depends on SUPPORT_EXTENSION_SCAN
+ help
+ Enables the "extension" command, which allows to detect
+ extension boards connected to the system, and apply
+ corresponding Device Tree overlays.
+
config CMD_GO
bool "go"
default y
diff --git a/cmd/Makefile b/cmd/Makefile
index 4977fa1..9d10e07 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -54,6 +54,7 @@
endif
obj-$(CONFIG_CMD_ADTIMG) += adtimg.o
obj-$(CONFIG_CMD_ABOOTIMG) += abootimg.o
+obj-$(CONFIG_CMD_EXTENSION) += extension_board.o
obj-$(CONFIG_CMD_ECHO) += echo.o
obj-$(CONFIG_ENV_IS_IN_EEPROM) += eeprom.o
obj-$(CONFIG_CMD_EEPROM) += eeprom.o
diff --git a/cmd/clk.c b/cmd/clk.c
index e3c3d2f..7ece245 100644
--- a/cmd/clk.c
+++ b/cmd/clk.c
@@ -18,11 +18,14 @@
{
int i, is_last;
struct udevice *child;
- struct clk *clkp;
+ struct clk *clkp, *parent;
u32 rate;
clkp = dev_get_clk_ptr(dev);
if (device_get_uclass_id(dev) == UCLASS_CLK && clkp) {
+ parent = clk_get_parent(clkp);
+ if (!IS_ERR(parent) && depth == -1)
+ return;
depth++;
rate = clk_get_rate(clkp);
@@ -47,6 +50,9 @@
}
list_for_each_entry(child, &dev->child_head, sibling_node) {
+ if (child == dev)
+ continue;
+
is_last = list_is_last(&child->sibling_node, &dev->child_head);
show_clks(child, depth, (last_flag << 1) | is_last);
}
@@ -54,14 +60,19 @@
int __weak soc_clk_dump(void)
{
- struct udevice *root;
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
- root = dm_root();
- if (root) {
- printf(" Rate Usecnt Name\n");
- printf("------------------------------------------\n");
- show_clks(root, -1, 0);
- }
+ ret = uclass_get(UCLASS_CLK, &uc);
+ if (ret)
+ return ret;
+
+ printf(" Rate Usecnt Name\n");
+ printf("------------------------------------------\n");
+
+ uclass_foreach_dev(dev, uc)
+ show_clks(dev, -1, 0);
return 0;
}
@@ -86,9 +97,57 @@
return ret;
}
+
+#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK)
+struct udevice *clk_lookup(const char *name)
+{
+ int i = 0;
+ struct udevice *dev;
+
+ do {
+ uclass_get_device(UCLASS_CLK, i++, &dev);
+ if (!strcmp(name, dev->name))
+ return dev;
+ } while (dev);
+
+ return NULL;
+}
+
+static int do_clk_setfreq(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct clk *clk = NULL;
+ s32 freq;
+ struct udevice *dev;
+
+ freq = simple_strtoul(argv[2], NULL, 10);
+
+ dev = clk_lookup(argv[1]);
+
+ if (dev)
+ clk = dev_get_clk_ptr(dev);
+
+ if (!clk) {
+ printf("clock '%s' not found.\n", argv[1]);
+ return -EINVAL;
+ }
+
+ freq = clk_set_rate(clk, freq);
+ if (freq < 0) {
+ printf("set_rate failed: %d\n", freq);
+ return CMD_RET_FAILURE;
+ }
+
+ printf("set_rate returns %u\n", freq);
+ return 0;
+}
+#endif
static struct cmd_tbl cmd_clk_sub[] = {
U_BOOT_CMD_MKENT(dump, 1, 1, do_clk_dump, "", ""),
+#if CONFIG_IS_ENABLED(DM) && CONFIG_IS_ENABLED(CLK)
+ U_BOOT_CMD_MKENT(setfreq, 3, 1, do_clk_setfreq, "", ""),
+#endif
};
static int do_clk(struct cmd_tbl *cmdtp, int flag, int argc,
@@ -113,7 +172,8 @@
#ifdef CONFIG_SYS_LONGHELP
static char clk_help_text[] =
- "dump - Print clock frequencies";
+ "dump - Print clock frequencies\n"
+ "setfreq [clk] [freq] - Set clock frequency";
#endif
-U_BOOT_CMD(clk, 2, 1, do_clk, "CLK sub-system", clk_help_text);
+U_BOOT_CMD(clk, 4, 1, do_clk, "CLK sub-system", clk_help_text);
diff --git a/cmd/dfu.c b/cmd/dfu.c
index ef4f897..4a288f7 100644
--- a/cmd/dfu.c
+++ b/cmd/dfu.c
@@ -68,7 +68,7 @@
int controller_index = simple_strtoul(usb_controller, NULL, 0);
bool retry = false;
do {
- run_usb_dnl_gadget(controller_index, "usb_dnl_dfu");
+ ret = run_usb_dnl_gadget(controller_index, "usb_dnl_dfu");
if (dfu_reinit_needed) {
dfu_free_entities();
diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 0bf7b88..c635271 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -12,6 +12,7 @@
#include <efi_load_initrd.h>
#include <efi_loader.h>
#include <efi_rng.h>
+#include <efi_variable.h>
#include <exports.h>
#include <hexdump.h>
#include <log.h>
@@ -227,8 +228,7 @@
{
int capsule_id;
char *endp;
- char var_name[12];
- u16 var_name16[12], *p;
+ u16 var_name16[12];
efi_guid_t guid;
struct efi_capsule_result_variable_header *result = NULL;
efi_uintn_t size;
@@ -240,8 +240,9 @@
guid = efi_guid_capsule_report;
if (argc == 1) {
size = sizeof(var_name16);
- ret = EFI_CALL(RT->get_variable(L"CapsuleLast", &guid, NULL,
- &size, var_name16));
+ ret = efi_get_variable_int(L"CapsuleLast", &guid, NULL,
+ &size, var_name16, NULL);
+
if (ret != EFI_SUCCESS) {
if (ret == EFI_NOT_FOUND)
printf("CapsuleLast doesn't exist\n");
@@ -259,19 +260,18 @@
if (capsule_id < 0 || capsule_id > 0xffff)
return CMD_RET_USAGE;
- sprintf(var_name, "Capsule%04X", capsule_id);
- p = var_name16;
- utf8_utf16_strncpy(&p, var_name, 9);
+ efi_create_indexed_name(var_name16, sizeof(var_name16),
+ "Capsule", capsule_id);
}
size = 0;
- ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size, NULL));
+ ret = efi_get_variable_int(var_name16, &guid, NULL, &size, NULL, NULL);
if (ret == EFI_BUFFER_TOO_SMALL) {
result = malloc(size);
if (!result)
return CMD_RET_FAILURE;
- ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
- result));
+ ret = efi_get_variable_int(var_name16, &guid, NULL, &size,
+ result, NULL);
}
if (ret != EFI_SUCCESS) {
free(result);
@@ -954,8 +954,7 @@
{
int id;
char *endp;
- char var_name[9];
- u16 var_name16[9], *p;
+ u16 var_name16[9];
efi_guid_t guid;
size_t label_len, label_len16;
u16 *label;
@@ -988,9 +987,8 @@
if (*endp != '\0' || id > 0xffff)
return CMD_RET_USAGE;
- sprintf(var_name, "Boot%04X", id);
- p = var_name16;
- utf8_utf16_strncpy(&p, var_name, 9);
+ efi_create_indexed_name(var_name16, sizeof(var_name16),
+ "Boot", id);
/* label */
label_len = strlen(argv[2]);
@@ -1066,11 +1064,11 @@
goto out;
}
- ret = EFI_CALL(efi_set_variable(var_name16, &guid,
- EFI_VARIABLE_NON_VOLATILE |
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
- size, data));
+ ret = efi_set_variable_int(var_name16, &guid,
+ EFI_VARIABLE_NON_VOLATILE |
+ EFI_VARIABLE_BOOTSERVICE_ACCESS |
+ EFI_VARIABLE_RUNTIME_ACCESS,
+ size, data, false);
if (ret != EFI_SUCCESS) {
printf("Cannot set %ls\n", var_name16);
r = CMD_RET_FAILURE;
@@ -1107,8 +1105,7 @@
efi_guid_t guid;
int id, i;
char *endp;
- char var_name[9];
- u16 var_name16[9], *p;
+ u16 var_name16[9];
efi_status_t ret;
if (argc == 1)
@@ -1120,11 +1117,10 @@
if (*endp != '\0' || id > 0xffff)
return CMD_RET_FAILURE;
- sprintf(var_name, "Boot%04X", id);
- p = var_name16;
- utf8_utf16_strncpy(&p, var_name, 9);
-
- ret = EFI_CALL(efi_set_variable(var_name16, &guid, 0, 0, NULL));
+ efi_create_indexed_name(var_name16, sizeof(var_name16),
+ "Boot", id);
+ ret = efi_set_variable_int(var_name16, &guid, 0, 0, NULL,
+ false);
if (ret) {
printf("Cannot remove %ls\n", var_name16);
return CMD_RET_FAILURE;
@@ -1147,8 +1143,6 @@
{
struct efi_device_path *initrd_path = NULL;
struct efi_load_option lo;
- char *label, *p;
- size_t label_len16, label_len;
u16 *dp_str;
efi_status_t ret;
efi_uintn_t initrd_dp_size;
@@ -1160,14 +1154,6 @@
return;
}
- label_len16 = u16_strlen(lo.label);
- label_len = utf16_utf8_strnlen(lo.label, label_len16);
- label = malloc(label_len + 1);
- if (!label)
- return;
- p = label;
- utf16_utf8_strncpy(&p, lo.label, label_len16);
-
printf("%ls:\nattributes: %c%c%c (0x%08x)\n",
varname16,
/* ACTIVE */
@@ -1177,7 +1163,7 @@
/* HIDDEN */
lo.attributes & LOAD_OPTION_HIDDEN ? 'H' : '-',
lo.attributes);
- printf(" label: %s\n", label);
+ printf(" label: %ls\n", lo.label);
dp_str = efi_dp_str(lo.file_path);
printf(" file_path: %ls\n", dp_str);
@@ -1194,7 +1180,6 @@
printf(" data:\n");
print_hex_dump(" ", DUMP_PREFIX_OFFSET, 16, 1,
lo.optional_data, *size, true);
- free(label);
}
/**
@@ -1324,12 +1309,9 @@
u16 *bootorder;
efi_uintn_t size;
int num, i;
- char var_name[9];
- u16 var_name16[9], *p16;
+ u16 var_name16[9];
void *data;
struct efi_load_option lo;
- char *label, *p;
- size_t label_len16, label_len;
efi_status_t ret;
size = 0;
@@ -1357,16 +1339,15 @@
num = size / sizeof(u16);
for (i = 0; i < num; i++) {
- sprintf(var_name, "Boot%04X", bootorder[i]);
- p16 = var_name16;
- utf8_utf16_strncpy(&p16, var_name, 9);
+ efi_create_indexed_name(var_name16, sizeof(var_name16),
+ "Boot", i);
size = 0;
ret = EFI_CALL(efi_get_variable(var_name16,
&efi_global_variable_guid, NULL,
&size, NULL));
if (ret != EFI_BUFFER_TOO_SMALL) {
- printf("%2d: %s: (not defined)\n", i + 1, var_name);
+ printf("%2d: %ls: (not defined)\n", i + 1, var_name16);
continue;
}
@@ -1391,18 +1372,7 @@
goto out;
}
- label_len16 = u16_strlen(lo.label);
- label_len = utf16_utf8_strnlen(lo.label, label_len16);
- label = malloc(label_len + 1);
- if (!label) {
- free(data);
- ret = CMD_RET_FAILURE;
- goto out;
- }
- p = label;
- utf16_utf8_strncpy(&p, lo.label, label_len16);
- printf("%2d: %s: %s\n", i + 1, var_name, label);
- free(label);
+ printf("%2d: %ls: %ls\n", i + 1, var_name16, lo.label);
free(data);
}
@@ -1449,11 +1419,11 @@
guid = efi_global_variable_guid;
size = sizeof(u16);
- ret = EFI_CALL(efi_set_variable(L"BootNext", &guid,
+ ret = efi_set_variable_int(L"BootNext", &guid,
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
- size, &bootnext));
+ size, &bootnext, false);
if (ret != EFI_SUCCESS) {
printf("Cannot set BootNext\n");
r = CMD_RET_FAILURE;
@@ -1510,11 +1480,11 @@
}
guid = efi_global_variable_guid;
- ret = EFI_CALL(efi_set_variable(L"BootOrder", &guid,
+ ret = efi_set_variable_int(L"BootOrder", &guid,
EFI_VARIABLE_NON_VOLATILE |
EFI_VARIABLE_BOOTSERVICE_ACCESS |
EFI_VARIABLE_RUNTIME_ACCESS,
- size, bootorder));
+ size, bootorder, true);
if (ret != EFI_SUCCESS) {
printf("Cannot set BootOrder\n");
r = CMD_RET_FAILURE;
diff --git a/cmd/extension_board.c b/cmd/extension_board.c
new file mode 100644
index 0000000..bbb4812
--- /dev/null
+++ b/cmd/extension_board.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <extension_board.h>
+#include <mapmem.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+static LIST_HEAD(extension_list);
+
+static int extension_apply(struct extension *extension)
+{
+ char *overlay_cmd;
+ ulong extrasize, overlay_addr;
+ struct fdt_header *blob;
+
+ if (!working_fdt) {
+ printf("No FDT memory address configured. Please configure\n"
+ "the FDT address via \"fdt addr <address>\" command.\n");
+ return CMD_RET_FAILURE;
+ }
+
+ overlay_cmd = env_get("extension_overlay_cmd");
+ if (!overlay_cmd) {
+ printf("Environment extension_overlay_cmd is missing\n");
+ return CMD_RET_FAILURE;
+ }
+
+ overlay_addr = env_get_hex("extension_overlay_addr", 0);
+ if (!overlay_addr) {
+ printf("Environment extension_overlay_addr is missing\n");
+ return CMD_RET_FAILURE;
+ }
+
+ env_set("extension_overlay_name", extension->overlay);
+ if (run_command(overlay_cmd, 0) != 0)
+ return CMD_RET_FAILURE;
+
+ extrasize = env_get_hex("filesize", 0);
+ if (!extrasize)
+ return CMD_RET_FAILURE;
+
+ fdt_shrink_to_minimum(working_fdt, extrasize);
+
+ blob = map_sysmem(overlay_addr, 0);
+ if (!fdt_valid(&blob))
+ return CMD_RET_FAILURE;
+
+ /* apply method prints messages on error */
+ if (fdt_overlay_apply_verbose(working_fdt, blob))
+ return CMD_RET_FAILURE;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_extension_list(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ int i = 0;
+ struct extension *extension;
+
+ if (list_empty(&extension_list)) {
+ printf("No extension registered - Please run \"extension scan\"\n");
+ return CMD_RET_SUCCESS;
+ }
+
+ list_for_each_entry(extension, &extension_list, list) {
+ printf("Extension %d: %s\n", i++, extension->name);
+ printf("\tManufacturer: \t\t%s\n", extension->owner);
+ printf("\tVersion: \t\t%s\n", extension->version);
+ printf("\tDevicetree overlay: \t%s\n", extension->overlay);
+ printf("\tOther information: \t%s\n", extension->other);
+ }
+ return CMD_RET_SUCCESS;
+}
+
+static int do_extension_scan(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ struct extension *extension, *next;
+ int extension_num;
+
+ list_for_each_entry_safe(extension, next, &extension_list, list) {
+ list_del(&extension->list);
+ free(extension);
+ }
+ extension_num = extension_board_scan(&extension_list);
+
+ if (extension_num < 0)
+ return CMD_RET_FAILURE;
+
+ printf("Found %d extension board(s).\n", extension_num);
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_extension_apply(struct cmd_tbl *cmdtp, int flag,
+ int argc, char *const argv[])
+{
+ struct extension *extension = NULL;
+ struct list_head *entry;
+ int i = 0, extension_id, ret;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ if (strcmp(argv[1], "all") == 0) {
+ list_for_each_entry(extension, &extension_list, list) {
+ ret = extension_apply(extension);
+ if (ret != CMD_RET_SUCCESS)
+ break;
+ }
+ } else {
+ extension_id = simple_strtol(argv[1], NULL, 10);
+ list_for_each(entry, &extension_list) {
+ if (i == extension_id) {
+ extension = list_entry(entry, struct extension, list);
+ break;
+ }
+ i++;
+ }
+
+ if (!extension) {
+ printf("Wrong extension number\n");
+ return CMD_RET_FAILURE;
+ }
+
+ ret = extension_apply(extension);
+ }
+
+ return ret;
+}
+
+static struct cmd_tbl cmd_extension[] = {
+ U_BOOT_CMD_MKENT(scan, 1, 1, do_extension_scan, "", ""),
+ U_BOOT_CMD_MKENT(list, 1, 0, do_extension_list, "", ""),
+ U_BOOT_CMD_MKENT(apply, 2, 0, do_extension_apply, "", ""),
+};
+
+static int do_extensionops(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct cmd_tbl *cp;
+
+ /* Drop the extension command */
+ argc--;
+ argv++;
+
+ cp = find_cmd_tbl(argv[0], cmd_extension, ARRAY_SIZE(cmd_extension));
+ if (cp)
+ return cp->cmd(cmdtp, flag, argc, argv);
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(extension, 3, 1, do_extensionops,
+ "Extension board management sub system",
+ "scan - scan plugged extension(s) board(s)\n"
+ "extension list - lists available extension(s) board(s)\n"
+ "extension apply <extension number|all> - applies DT overlays corresponding to extension boards\n"
+);
diff --git a/cmd/fdt.c b/cmd/fdt.c
index 89ab572..f1e2fc2 100644
--- a/cmd/fdt.c
+++ b/cmd/fdt.c
@@ -27,7 +27,6 @@
*/
DECLARE_GLOBAL_DATA_PTR;
-static int fdt_valid(struct fdt_header **blobp);
static int fdt_parse_prop(char *const*newval, int count, char *data, int *len);
static int fdt_print(const char *pathp, char *prop, int depth);
static int is_printable_string(const void *data, int len);
@@ -732,54 +731,6 @@
/****************************************************************************/
-/**
- * fdt_valid() - Check if an FDT is valid. If not, change it to NULL
- *
- * @blobp: Pointer to FDT pointer
- * @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
- */
-static int fdt_valid(struct fdt_header **blobp)
-{
- const void *blob = *blobp;
- int err;
-
- if (blob == NULL) {
- printf ("The address of the fdt is invalid (NULL).\n");
- return 0;
- }
-
- err = fdt_check_header(blob);
- if (err == 0)
- return 1; /* valid */
-
- if (err < 0) {
- printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
- /*
- * Be more informative on bad version.
- */
- if (err == -FDT_ERR_BADVERSION) {
- if (fdt_version(blob) <
- FDT_FIRST_SUPPORTED_VERSION) {
- printf (" - too old, fdt %d < %d",
- fdt_version(blob),
- FDT_FIRST_SUPPORTED_VERSION);
- }
- if (fdt_last_comp_version(blob) >
- FDT_LAST_SUPPORTED_VERSION) {
- printf (" - too new, fdt %d > %d",
- fdt_version(blob),
- FDT_LAST_SUPPORTED_VERSION);
- }
- }
- printf("\n");
- *blobp = NULL;
- return 0;
- }
- return 1;
-}
-
-/****************************************************************************/
-
/*
* Parse the user's input, partially heuristic. Valid formats:
* <0x00112233 4 05> - an array of cells. Numbers follow standard
diff --git a/cmd/gpt.c b/cmd/gpt.c
index 76a95ad..17f2b83 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -350,17 +350,46 @@
}
/* a wrapper to test get_gpt_info */
-static int do_get_gpt_info(struct blk_desc *dev_desc)
+static int do_get_gpt_info(struct blk_desc *dev_desc, char * const namestr)
{
- int ret;
+ int numparts;
+
+ numparts = get_gpt_info(dev_desc);
+
+ if (numparts > 0) {
+ if (namestr) {
+ char disk_guid[UUID_STR_LEN + 1];
+ char *partitions_list;
+ int partlistlen;
+ int ret = -1;
+
+ ret = get_disk_guid(dev_desc, disk_guid);
+ if (ret < 0)
+ return ret;
+
+ partlistlen = calc_parts_list_len(numparts);
+ partitions_list = malloc(partlistlen);
+ if (!partitions_list) {
+ del_gpt_info();
+ return -ENOMEM;
+ }
+ memset(partitions_list, '\0', partlistlen);
+
+ ret = create_gpt_partitions_list(numparts, disk_guid,
+ partitions_list);
+ if (ret < 0)
+ printf("Error: Could not create partition list string!\n");
+ else
+ env_set(namestr, partitions_list);
- ret = get_gpt_info(dev_desc);
- if (ret > 0) {
- print_gpt_info();
+ free(partitions_list);
+ } else {
+ print_gpt_info();
+ }
del_gpt_info();
return 0;
}
- return ret;
+ return numparts;
}
#endif
@@ -982,7 +1011,7 @@
ret = do_disk_guid(blk_dev_desc, argv[4]);
#ifdef CONFIG_CMD_GPT_RENAME
} else if (strcmp(argv[1], "read") == 0) {
- ret = do_get_gpt_info(blk_dev_desc);
+ ret = do_get_gpt_info(blk_dev_desc, (argc == 5) ? argv[4] : NULL);
} else if ((strcmp(argv[1], "swap") == 0) ||
(strcmp(argv[1], "rename") == 0)) {
ret = do_rename_gpt_parts(blk_dev_desc, argv[1], argv[4], argv[5]);
@@ -1028,8 +1057,9 @@
" gpt guid mmc 0 varname\n"
#ifdef CONFIG_CMD_GPT_RENAME
"gpt partition renaming commands:\n"
- " gpt read <interface> <dev>\n"
+ " gpt read <interface> <dev> [<varname>]\n"
" - read GPT into a data structure for manipulation\n"
+ " - read GPT partitions into environment variable\n"
" gpt swap <interface> <dev> <name1> <name2>\n"
" - change all partitions named name1 to name2\n"
" and vice-versa\n"
diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig
index ad10a57..7c42c75 100644
--- a/cmd/mvebu/Kconfig
+++ b/cmd/mvebu/Kconfig
@@ -33,7 +33,7 @@
config MVEBU_MMC_BOOT
bool "eMMC flash boot"
- depends on MVEBU_MMC
+ depends on MVEBU_MMC || MMC_SDHCI_XENON
help
Enable boot from eMMC boot partition
Allow usage of eMMC/SD device as a target for "bubt" command
@@ -49,4 +49,10 @@
This option should contain a default file name to be used with
MVEBU "bubt" command if the source file name is omitted
+config CMD_MVEBU_COMPHY_RX_TRAINING
+ bool "mvebu_comphy_rx_training"
+ depends on ARMADA_8K
+ help
+ Perform COMPHY RX training sequence
+
endmenu
diff --git a/cmd/mvebu/Makefile b/cmd/mvebu/Makefile
index 96829c4..ca96ad0 100644
--- a/cmd/mvebu/Makefile
+++ b/cmd/mvebu/Makefile
@@ -4,5 +4,5 @@
#
# https://spdx.org/licenses
-
obj-$(CONFIG_CMD_MVEBU_BUBT) += bubt.o
+obj-$(CONFIG_CMD_MVEBU_COMPHY_RX_TRAINING) += comphy_rx_training.o
diff --git a/cmd/mvebu/bubt.c b/cmd/mvebu/bubt.c
index b649963..5cd520e 100644
--- a/cmd/mvebu/bubt.c
+++ b/cmd/mvebu/bubt.c
@@ -798,7 +798,7 @@
#define DEFAULT_BUBT_DST "nand"
#elif defined(CONFIG_MVEBU_MMC_BOOT)
#define DEFAULT_BUBT_DST "mmc"
-else
+#else
#define DEFAULT_BUBT_DST "error"
#endif
#endif /* DEFAULT_BUBT_DST */
diff --git a/cmd/mvebu/comphy_rx_training.c b/cmd/mvebu/comphy_rx_training.c
new file mode 100644
index 0000000..0798dec
--- /dev/null
+++ b/cmd/mvebu/comphy_rx_training.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 Marvell International Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <dm/device-internal.h>
+#include <mvebu/comphy.h>
+
+int mvebu_comphy_rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret, cp_index, comphy_index, i = 0;
+
+ if (argc != 3) {
+ printf("missing arguments\n");
+ return -1;
+ }
+
+ cp_index = simple_strtoul(argv[1], NULL, 16);
+ comphy_index = simple_strtoul(argv[2], NULL, 16);
+
+ ret = uclass_get(UCLASS_MISC, &uc);
+ if (ret) {
+ printf("Couldn't find UCLASS_MISC\n");
+ return ret;
+ }
+
+ uclass_foreach_dev(dev, uc) {
+ if (!(memcmp(dev->name, "comphy", 5))) {
+ if (i == cp_index) {
+ comphy_rx_training(dev, comphy_index);
+ return 0;
+ }
+
+ i++;
+ }
+ }
+
+ printf("Coudn't find comphy %d\n", cp_index);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ mvebu_comphy_rx_training, 3, 0, mvebu_comphy_rx_training_cmd,
+ "mvebu_comphy_rx_training <cp id> <comphy id>\n",
+ "\n\tRun COMPHY RX training sequence, the user must state CP index (0/1) and comphy ID (0/5)"
+);
diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c
index 9687cec..7a08061 100644
--- a/cmd/riscv/exception.c
+++ b/cmd/riscv/exception.c
@@ -8,6 +8,13 @@
#include <common.h>
#include <command.h>
+static int do_ebreak(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ asm volatile ("ebreak\n");
+ return CMD_RET_FAILURE;
+}
+
static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -28,6 +35,8 @@
}
static struct cmd_tbl cmd_sub[] = {
+ U_BOOT_CMD_MKENT(ebreak, CONFIG_SYS_MAXARGS, 1, do_ebreak,
+ "", ""),
U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned,
"", ""),
U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined,
@@ -37,6 +46,7 @@
static char exception_help_text[] =
"<ex>\n"
" The following exceptions are available:\n"
+ " ebreak - breakpoint\n"
" undefined - illegal instruction\n"
" unaligned - load address misaligned\n"
;
diff --git a/cmd/stackprot_test.c b/cmd/stackprot_test.c
index 36f5bac..1e26193 100644
--- a/cmd/stackprot_test.c
+++ b/cmd/stackprot_test.c
@@ -9,9 +9,16 @@
static int do_test_stackprot_fail(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
+ /*
+ * In order to avoid having the compiler optimize away the stack smashing
+ * we need to do a little something here.
+ */
char a[128];
memset(a, 0xa5, 512);
+
+ printf("We have smashed our stack as this should not exceed 128: sizeof(a) = %ld\n", strlen(a));
+
return 0;
}
diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
index efeff0d..db55744 100644
--- a/cmd/ti/Kconfig
+++ b/cmd/ti/Kconfig
@@ -7,4 +7,12 @@
supports memory verification, memory comapre and ecc
verification if supported.
+config CMD_PD
+ bool "command for verifying power domains"
+ depends on TI_POWER_DOMAIN
+ help
+ Debug command for K3 power domains. For this to work, the
+ K3 power domain driver must be enabled for the u-boot; by
+ default it is only enabled for SPL.
+
endmenu
diff --git a/cmd/ti/Makefile b/cmd/ti/Makefile
index 16fbade..0455933 100644
--- a/cmd/ti/Makefile
+++ b/cmd/ti/Makefile
@@ -5,4 +5,5 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_DDR3) += ddr3.o
+obj-$(CONFIG_CMD_PD) += pd.o
endif
diff --git a/cmd/ti/pd.c b/cmd/ti/pd.c
new file mode 100644
index 0000000..9e820b8
--- /dev/null
+++ b/cmd/ti/pd.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Power Domain test commands
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated, <www.ti.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <k3-dev.h>
+
+static const struct udevice_id ti_pd_of_match[] = {
+ { .compatible = "ti,sci-pm-domain" },
+ { /* sentinel */ }
+};
+
+static struct ti_k3_pd_platdata *ti_pd_find_data(void)
+{
+ struct udevice *dev;
+ int i = 0;
+
+ while (1) {
+ uclass_get_device(UCLASS_POWER_DOMAIN, i++, &dev);
+ if (!dev)
+ return NULL;
+
+ if (device_is_compatible(dev,
+ ti_pd_of_match[0].compatible))
+ return dev_get_priv(dev);
+ }
+
+ return NULL;
+}
+
+static void dump_lpsc(struct ti_k3_pd_platdata *data, struct ti_pd *pd)
+{
+ int i;
+ struct ti_lpsc *lpsc;
+ u8 state;
+ static const char * const lpsc_states[] = {
+ "swrstdis", "syncrst", "disable", "enable", "autosleep",
+ "autowake", "unknown",
+ };
+
+ for (i = 0; i < data->num_lpsc; i++) {
+ lpsc = &data->lpsc[i];
+ if (lpsc->pd != pd)
+ continue;
+ state = lpsc_get_state(lpsc);
+ if (state > ARRAY_SIZE(lpsc_states))
+ state = ARRAY_SIZE(lpsc_states) - 1;
+ printf(" LPSC%d: state=%s, usecount=%d\n",
+ lpsc->id, lpsc_states[state], lpsc->usecount);
+ }
+}
+
+static void dump_pd(struct ti_k3_pd_platdata *data, struct ti_psc *psc)
+{
+ int i;
+ struct ti_pd *pd;
+ u8 state;
+ static const char * const pd_states[] = {
+ "off", "on", "unknown"
+ };
+
+ for (i = 0; i < data->num_pd; i++) {
+ pd = &data->pd[i];
+ if (pd->psc != psc)
+ continue;
+ state = ti_pd_state(pd);
+ if (state > ARRAY_SIZE(pd_states))
+ state = ARRAY_SIZE(pd_states) - 1;
+ printf(" PD%d: state=%s, usecount=%d:\n",
+ pd->id, pd_states[state], pd->usecount);
+ dump_lpsc(data, pd);
+ }
+}
+
+static void dump_psc(struct ti_k3_pd_platdata *data)
+{
+ int i;
+ struct ti_psc *psc;
+
+ for (i = 0; i < data->num_psc; i++) {
+ psc = &data->psc[i];
+ printf("PSC%d [%p]:\n", psc->id, psc->base);
+ dump_pd(data, psc);
+ }
+}
+
+static int do_pd_dump(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ struct ti_k3_pd_platdata *data;
+
+ data = ti_pd_find_data();
+ if (!data)
+ return CMD_RET_FAILURE;
+
+ dump_psc(data);
+
+ return 0;
+}
+
+static int do_pd_endis(int argc, char *const argv[], u8 state)
+{
+ u32 psc_id;
+ u32 lpsc_id;
+ int i;
+ struct ti_k3_pd_platdata *data;
+ struct ti_lpsc *lpsc;
+ int ret;
+
+ if (argc < 3)
+ return CMD_RET_FAILURE;
+
+ data = ti_pd_find_data();
+ if (!data)
+ return CMD_RET_FAILURE;
+
+ psc_id = simple_strtoul(argv[1], NULL, 10);
+ lpsc_id = simple_strtoul(argv[2], NULL, 10);
+
+ for (i = 0; i < data->num_lpsc; i++) {
+ lpsc = &data->lpsc[i];
+ if (lpsc->pd->psc->id != psc_id)
+ continue;
+ if (lpsc->id != lpsc_id)
+ continue;
+ printf("%s pd [PSC:%d,LPSC:%d]...\n",
+ state == MDSTAT_STATE_ENABLE ? "Enabling" : "Disabling",
+ psc_id, lpsc_id);
+ ret = ti_lpsc_transition(lpsc, state);
+ if (ret)
+ return CMD_RET_FAILURE;
+ else
+ return 0;
+ }
+
+ printf("No matching psc/lpsc found.\n");
+
+ return CMD_RET_FAILURE;
+}
+
+static int do_pd_enable(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ return do_pd_endis(argc, argv, MDSTAT_STATE_ENABLE);
+}
+
+static int do_pd_disable(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ return do_pd_endis(argc, argv, MDSTAT_STATE_SWRSTDISABLE);
+}
+
+static struct cmd_tbl cmd_pd[] = {
+ U_BOOT_CMD_MKENT(dump, 1, 0, do_pd_dump, "", ""),
+ U_BOOT_CMD_MKENT(enable, 3, 0, do_pd_enable, "", ""),
+ U_BOOT_CMD_MKENT(disable, 3, 0, do_pd_disable, "", ""),
+};
+
+static int ti_do_pd(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct cmd_tbl *c;
+
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], cmd_pd, ARRAY_SIZE(cmd_pd));
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(pd, 4, 1, ti_do_pd,
+ "TI power domain control",
+#if CONFIG_IS_ENABLED(SYS_LONGHELP)
+ "dump - show power domain status\n"
+ "enable [psc] [lpsc] - enable power domain\n"
+ "disable [psc] [lpsc] - disable power domain\n"
+#endif
+);
diff --git a/cmd/x86/cbsysinfo.c b/cmd/x86/cbsysinfo.c
index a0db0ad..34fdaf5 100644
--- a/cmd/x86/cbsysinfo.c
+++ b/cmd/x86/cbsysinfo.c
@@ -205,7 +205,7 @@
print_hex(">type", ser->type);
print_addr(">base", ser->baseaddr);
print_dec(">baud", ser->baud);
- print_hex(">baud", ser->regwidth);
+ print_hex(">regwidth", ser->regwidth);
print_dec(">input_hz", ser->input_hertz);
print_addr(">PCI addr", ser->uart_pci_addr);
}
diff --git a/common/Kconfig.boot b/common/Kconfig.boot
index 5a18d62..89a3161 100644
--- a/common/Kconfig.boot
+++ b/common/Kconfig.boot
@@ -204,7 +204,7 @@
This path has the following limitations:
- 1. "loadables" images, other than FTDs, which do not have a "load"
+ 1. "loadables" images, other than FDTs, which do not have a "load"
property will not be loaded. This limitation also applies to FPGA
images with the correct "compatible" string.
2. For FPGA images, only the "compatible" = "u-boot,fpga-legacy"
@@ -273,14 +273,13 @@
config USE_SPL_FIT_GENERATOR
bool "Use a script to generate the .its script"
- default y if SPL_FIT && !ARCH_SUNXI
+ default y if SPL_FIT && (!ARCH_SUNXI && !RISCV)
config SPL_FIT_GENERATOR
string ".its file generator script for U-Boot FIT image"
depends on USE_SPL_FIT_GENERATOR
default "arch/arm/mach-rockchip/make_fit_atf.py" if SPL_LOAD_FIT && ARCH_ROCKCHIP
default "arch/arm/mach-zynqmp/mkimage_fit_atf.sh" if SPL_LOAD_FIT && ARCH_ZYNQMP
- default "arch/riscv/lib/mkimage_fit_opensbi.sh" if SPL_LOAD_FIT && RISCV
help
Specifies a (platform specific) script file to generate the FIT
source file used to build the U-Boot FIT image file. This gets
diff --git a/common/board_r.c b/common/board_r.c
index c835ff8e..3f82404 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -459,6 +459,8 @@
else
env_set_default(NULL, 0);
+ env_import_fdt();
+
if (IS_ENABLED(CONFIG_OF_CONTROL))
env_set_hex("fdtcontroladdr",
(unsigned long)map_to_sysmem(gd->fdt_blob));
diff --git a/common/cli_hush.c b/common/cli_hush.c
index 6cff3b1..1467ff8 100644
--- a/common/cli_hush.c
+++ b/common/cli_hush.c
@@ -3325,7 +3325,7 @@
void *p = NULL;
if (!(p = malloc(size))) {
- printf("ERROR : memory not allocated\n");
+ printf("ERROR : xmalloc failed\n");
for(;;);
}
return p;
@@ -3336,7 +3336,7 @@
void *p = NULL;
if (!(p = realloc(ptr, size))) {
- printf("ERROR : memory not allocated\n");
+ printf("ERROR : xrealloc failed\n");
for(;;);
}
return p;
diff --git a/common/console.c b/common/console.c
index 561cdf3..73edb28 100644
--- a/common/console.c
+++ b/common/console.c
@@ -95,16 +95,22 @@
{
if (!(gd->flags & GD_FLG_RECORD))
return;
- if (gd->console_out.start)
- membuff_putbyte((struct membuff *)&gd->console_out, c);
+ if (gd->console_out.start &&
+ !membuff_putbyte((struct membuff *)&gd->console_out, c))
+ gd->flags |= GD_FLG_RECORD_OVF;
}
static void console_record_puts(const char *s)
{
if (!(gd->flags & GD_FLG_RECORD))
return;
- if (gd->console_out.start)
- membuff_put((struct membuff *)&gd->console_out, s, strlen(s));
+ if (gd->console_out.start) {
+ int len = strlen(s);
+
+ if (membuff_put((struct membuff *)&gd->console_out, s, len) !=
+ len)
+ gd->flags |= GD_FLG_RECORD_OVF;
+ }
}
static int console_record_getc(void)
@@ -742,6 +748,7 @@
{
membuff_purge((struct membuff *)&gd->console_out);
membuff_purge((struct membuff *)&gd->console_in);
+ gd->flags &= ~GD_FLG_RECORD_OVF;
}
int console_record_reset_enable(void)
@@ -754,6 +761,9 @@
int console_record_readline(char *str, int maxlen)
{
+ if (gd->flags & GD_FLG_RECORD_OVF)
+ return -ENOSPC;
+
return membuff_readline((struct membuff *)&gd->console_out, str,
maxlen, ' ');
}
diff --git a/common/fdt_support.c b/common/fdt_support.c
index e624bbd..a9a32df 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -20,8 +20,6 @@
#include <exports.h>
#include <fdtdec.h>
-DECLARE_GLOBAL_DATA_PTR;
-
/**
* fdt_getprop_u32_default_node - Return a node's property or a default
*
@@ -269,6 +267,15 @@
return 0;
}
+/**
+ * board_fdt_chosen_bootargs - boards may override this function to use
+ * alternative kernel command line arguments
+ */
+__weak char *board_fdt_chosen_bootargs(void)
+{
+ return env_get("bootargs");
+}
+
int fdt_chosen(void *fdt)
{
int nodeoffset;
@@ -286,7 +293,8 @@
if (nodeoffset < 0)
return nodeoffset;
+ str = board_fdt_chosen_bootargs();
+
- str = env_get("bootargs");
if (str) {
err = fdt_setprop(fdt, nodeoffset, "bootargs", str,
strlen(str) + 1);
@@ -991,8 +999,8 @@
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_BAD_ADDR FDT_ADDR_T_NONE
-#define OF_CHECK_COUNTS(na, ns) (((na) > 0 && (na) <= OF_MAX_ADDR_CELLS) && \
- ((ns) > 0 || gd_size_cells_0()))
+#define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \
+ (ns) > 0)
/* Debug utility */
#ifdef DEBUG
@@ -1896,3 +1904,49 @@
return err;
}
#endif
+
+/**
+ * fdt_valid() - Check if an FDT is valid. If not, change it to NULL
+ *
+ * @blobp: Pointer to FDT pointer
+ * @return 1 if OK, 0 if bad (in which case *blobp is set to NULL)
+ */
+int fdt_valid(struct fdt_header **blobp)
+{
+ const void *blob = *blobp;
+ int err;
+
+ if (!blob) {
+ printf("The address of the fdt is invalid (NULL).\n");
+ return 0;
+ }
+
+ err = fdt_check_header(blob);
+ if (err == 0)
+ return 1; /* valid */
+
+ if (err < 0) {
+ printf("libfdt fdt_check_header(): %s", fdt_strerror(err));
+ /*
+ * Be more informative on bad version.
+ */
+ if (err == -FDT_ERR_BADVERSION) {
+ if (fdt_version(blob) <
+ FDT_FIRST_SUPPORTED_VERSION) {
+ printf(" - too old, fdt %d < %d",
+ fdt_version(blob),
+ FDT_FIRST_SUPPORTED_VERSION);
+ }
+ if (fdt_last_comp_version(blob) >
+ FDT_LAST_SUPPORTED_VERSION) {
+ printf(" - too new, fdt %d > %d",
+ fdt_version(blob),
+ FDT_LAST_SUPPORTED_VERSION);
+ }
+ }
+ printf("\n");
+ *blobp = NULL;
+ return 0;
+ }
+ return 1;
+}
diff --git a/common/hash.c b/common/hash.c
index 10dff7d..90cf46b 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -260,12 +260,12 @@
.name = "sha384",
.digest_size = SHA384_SUM_LEN,
.chunk_size = CHUNKSZ_SHA384,
-#ifdef CONFIG_SHA_HW_ACCEL
+#ifdef CONFIG_SHA512_HW_ACCEL
.hash_func_ws = hw_sha384,
#else
.hash_func_ws = sha384_csum_wd,
#endif
-#ifdef CONFIG_SHA_PROG_HW_ACCEL
+#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
@@ -281,12 +281,12 @@
.name = "sha512",
.digest_size = SHA512_SUM_LEN,
.chunk_size = CHUNKSZ_SHA512,
-#ifdef CONFIG_SHA_HW_ACCEL
+#ifdef CONFIG_SHA512_HW_ACCEL
.hash_func_ws = hw_sha512,
#else
.hash_func_ws = sha512_csum_wd,
#endif
-#ifdef CONFIG_SHA_PROG_HW_ACCEL
+#if defined(CONFIG_SHA512_HW_ACCEL) && defined(CONFIG_SHA_PROG_HW_ACCEL)
.hash_init = hw_sha_init,
.hash_update = hw_sha_update,
.hash_finish = hw_sha_finish,
diff --git a/common/image-fdt.c b/common/image-fdt.c
index d50e1ba..06dce92 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -75,18 +75,20 @@
#endif
static void boot_fdt_reserve_region(struct lmb *lmb, uint64_t addr,
- uint64_t size)
+ uint64_t size, enum lmb_flags flags)
{
long ret;
- ret = lmb_reserve(lmb, addr, size);
+ ret = lmb_reserve_flags(lmb, addr, size, flags);
if (ret >= 0) {
- debug(" reserving fdt memory region: addr=%llx size=%llx\n",
- (unsigned long long)addr, (unsigned long long)size);
+ debug(" reserving fdt memory region: addr=%llx size=%llx flags=%x\n",
+ (unsigned long long)addr,
+ (unsigned long long)size, flags);
} else {
puts("ERROR: reserving fdt memory region failed ");
- printf("(addr=%llx size=%llx)\n",
- (unsigned long long)addr, (unsigned long long)size);
+ printf("(addr=%llx size=%llx flags=%x)\n",
+ (unsigned long long)addr,
+ (unsigned long long)size, flags);
}
}
@@ -106,6 +108,7 @@
int i, total, ret;
int nodeoffset, subnode;
struct fdt_resource res;
+ enum lmb_flags flags;
if (fdt_check_header(fdt_blob) != 0)
return;
@@ -115,7 +118,7 @@
for (i = 0; i < total; i++) {
if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
continue;
- boot_fdt_reserve_region(lmb, addr, size);
+ boot_fdt_reserve_region(lmb, addr, size, LMB_NONE);
}
/* process reserved-memory */
@@ -127,9 +130,13 @@
ret = fdt_get_resource(fdt_blob, subnode, "reg", 0,
&res);
if (!ret && fdtdec_get_is_enabled(fdt_blob, subnode)) {
+ flags = LMB_NONE;
+ if (fdtdec_get_bool(fdt_blob, subnode,
+ "no-map"))
+ flags = LMB_NOMAP;
addr = res.start;
size = res.end - res.start + 1;
- boot_fdt_reserve_region(lmb, addr, size);
+ boot_fdt_reserve_region(lmb, addr, size, flags);
}
subnode = fdt_next_subnode(fdt_blob, subnode);
diff --git a/common/image-fit.c b/common/image-fit.c
index e614643..0c5a059 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -2143,7 +2143,7 @@
/* perform any post-processing on the image data */
if (!host_build() && IS_ENABLED(CONFIG_FIT_IMAGE_POST_PROCESS))
- board_fit_image_post_process(&buf, &size);
+ board_fit_image_post_process(fit, noffset, &buf, &size);
len = (ulong)size;
diff --git a/common/iomux.c b/common/iomux.c
index b9088aa..c428f71 100644
--- a/common/iomux.c
+++ b/common/iomux.c
@@ -158,8 +158,12 @@
return -ENOMEM;
}
- strcat(tmp, ",");
- strcat(tmp, name);
+ if (arg) {
+ strcat(tmp, ",");
+ strcat(tmp, name);
+ }
+ else
+ strcpy(tmp, name);
arg = tmp;
size = strlen(tmp) + 1;
diff --git a/common/log.c b/common/log.c
index ea407c6..1aaa6c1 100644
--- a/common/log.c
+++ b/common/log.c
@@ -284,6 +284,36 @@
return 0;
}
+#define MAX_LINE_LENGTH_BYTES 64
+#define DEFAULT_LINE_LENGTH_BYTES 16
+
+int _log_buffer(enum log_category_t cat, enum log_level_t level,
+ const char *file, int line, const char *func, ulong addr,
+ const void *data, uint width, uint count, uint linelen)
+{
+ if (linelen * width > MAX_LINE_LENGTH_BYTES)
+ linelen = MAX_LINE_LENGTH_BYTES / width;
+ if (linelen < 1)
+ linelen = DEFAULT_LINE_LENGTH_BYTES / width;
+
+ while (count) {
+ uint thislinelen;
+ char buf[HEXDUMP_MAX_BUF_LENGTH(width * linelen)];
+
+ thislinelen = hexdump_line(addr, data, width, count, linelen,
+ buf, sizeof(buf));
+ assert(thislinelen >= 0);
+ _log(cat, level, file, line, func, "%s\n", buf);
+
+ /* update references */
+ data += thislinelen * width;
+ addr += thislinelen * width;
+ count -= thislinelen;
+ }
+
+ return 0;
+}
+
int log_add_filter_flags(const char *drv_name, enum log_category_t cat_list[],
enum log_level_t level, const char *file_list,
int flags)
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index df5468f..fa80524 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -165,7 +165,7 @@
provided by the board.
config SPL_BOOTROM_SUPPORT
- bool "Support returning to the BOOTROM"
+ bool "Support returning to the BOOTROM"
help
Some platforms (e.g. the Rockchip RK3368) provide support in their
ROM for loading the next boot-stage after performing basic setup
@@ -322,7 +322,7 @@
ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP44XX || OMAP54XX || AM33XX || AM43XX || \
- TARGET_SIFIVE_UNLEASHED
+ TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
help
Use sector number for specifying U-Boot location on MMC/SD in
raw mode.
@@ -339,7 +339,7 @@
default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \
OMAP54XX || AM33XX || AM43XX || ARCH_K3
default 0x4000 if ARCH_ROCKCHIP
- default 0x822 if TARGET_SIFIVE_UNLEASHED
+ default 0x822 if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
help
Address on the MMC to load U-Boot from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
@@ -707,7 +707,7 @@
default 1
help
Partition on the MMC to load U-Boot from when the MMC is being
- used in fs mode
+ used in fs mode
config SPL_MMC_TINY
bool "Tiny MMC framework in SPL"
@@ -784,8 +784,8 @@
config SPL_NAND_BASE
depends on SPL_NAND_DRIVERS
bool "Use Base NAND Driver"
- help
- Include nand_base.c in the SPL.
+ help
+ Include nand_base.c in the SPL.
config SPL_NAND_IDENT
depends on SPL_NAND_BASE
@@ -1301,7 +1301,7 @@
method, say Y.
config SPL_ATF_NO_PLATFORM_PARAM
- bool "Pass no platform parameter"
+ bool "Pass no platform parameter"
depends on SPL_ATF
help
While we expect to call a pointer to a valid FDT (or NULL)
@@ -1395,7 +1395,7 @@
For example, it may be useful to choose the device to boot.
config TPL_LDSCRIPT
- string "Linker script for the TPL stage"
+ string "Linker script for the TPL stage"
depends on TPL
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
default "arch/\$(ARCH)/cpu/u-boot-spl.lds"
@@ -1409,7 +1409,7 @@
fall back to the linker-script used for the SPL stage.
config TPL_NEEDS_SEPARATE_TEXT_BASE
- bool "TPL needs a separate text-base"
+ bool "TPL needs a separate text-base"
default n
depends on TPL
help
@@ -1418,7 +1418,7 @@
.text sections of the TPL stage has to be set below.
config TPL_NEEDS_SEPARATE_STACK
- bool "TPL needs a separate initial stack-pointer"
+ bool "TPL needs a separate initial stack-pointer"
default n
depends on TPL
help
@@ -1426,20 +1426,20 @@
stack-pointer from the settings for the SPL stage.
config TPL_TEXT_BASE
- hex "Base address for the .text section of the TPL stage"
+ hex "Base address for the .text section of the TPL stage"
depends on TPL_NEEDS_SEPARATE_TEXT_BASE
help
The base address for the .text section of the TPL stage.
config TPL_MAX_SIZE
- int "Maximum size (in bytes) for the TPL stage"
+ int "Maximum size (in bytes) for the TPL stage"
default 0
depends on TPL
help
The maximum size (in bytes) of the TPL stage.
config TPL_STACK
- hex "Address of the initial stack-pointer for the TPL stage"
+ hex "Address of the initial stack-pointer for the TPL stage"
depends on TPL_NEEDS_SEPARATE_STACK
help
The address of the initial stack-pointer for the TPL stage.
@@ -1457,7 +1457,7 @@
device-private data.
config TPL_BOOTROM_SUPPORT
- bool "Support returning to the BOOTROM (from TPL)"
+ bool "Support returning to the BOOTROM (from TPL)"
help
Some platforms (e.g. the Rockchip RK3368) provide support in their
ROM for loading the next boot-stage after performing basic setup
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 4288f57..57d621d 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -110,6 +110,10 @@
* no string in the property for this index. Check if the
* sysinfo-level code can supply one.
*/
+ rc = sysinfo_detect(sysinfo);
+ if (rc)
+ return rc;
+
rc = sysinfo_get_fit_loadable(sysinfo, index - i - 1, type,
&str);
if (rc && rc != -ENOENT)
@@ -316,7 +320,7 @@
}
if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS))
- board_fit_image_post_process(&src, &length);
+ board_fit_image_post_process(fit, node, &src, &length);
load_ptr = map_sysmem(load_addr, length);
if (IS_ENABLED(CONFIG_SPL_GZIP) && image_comp == IH_COMP_GZIP) {
diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig
index a70ee31..88b0b02 100644
--- a/configs/CHIP_defconfig
+++ b/configs/CHIP_defconfig
@@ -5,6 +5,7 @@
CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y
CONFIG_USB0_VBUS_PIN="PB10"
CONFIG_VIDEO_COMPOSITE=y
+CONFIG_CHIP_DIP_SCAN=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-r8-chip"
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_CMD_DFU=y
diff --git a/configs/MPC8315ERDB_defconfig b/configs/MPC8315ERDB_defconfig
index f03fec9..fa22196 100644
--- a/configs/MPC8315ERDB_defconfig
+++ b/configs/MPC8315ERDB_defconfig
@@ -118,7 +118,6 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_NAND=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@@ -131,7 +130,6 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFE080000
-CONFIG_FSL_SATA=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/MPC837XERDB_SLAVE_defconfig b/configs/MPC837XERDB_SLAVE_defconfig
index ea84564..fa27cd0 100644
--- a/configs/MPC837XERDB_SLAVE_defconfig
+++ b/configs/MPC837XERDB_SLAVE_defconfig
@@ -111,7 +111,6 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
-CONFIG_CMD_SATA=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
@@ -121,7 +120,6 @@
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFE080000
-CONFIG_FSL_SATA=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 63ce36d..eba1aa9 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -166,7 +166,6 @@
CONFIG_ENV_ADDR=0xFE080000
CONFIG_DM=y
CONFIG_FSL_SATA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig
index f1bb2ab..269a445 100644
--- a/configs/P1010RDB-PA_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig
@@ -85,5 +85,4 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig
index ec99aaa..3ac1db0 100644
--- a/configs/P1010RDB-PA_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig
@@ -67,5 +67,4 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
index c8ce5e3..e44e91b 100644
--- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig
@@ -79,5 +79,4 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
index 68afbf0..bf61206 100644
--- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig
@@ -81,5 +81,4 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig
index feec8cd..5809b1c 100644
--- a/configs/P1010RDB-PA_NAND_defconfig
+++ b/configs/P1010RDB-PA_NAND_defconfig
@@ -84,4 +84,3 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig
index 72b889c..b8773e0 100644
--- a/configs/P1010RDB-PA_NOR_defconfig
+++ b/configs/P1010RDB-PA_NOR_defconfig
@@ -66,4 +66,3 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig
index 2c81934..e1e7daf 100644
--- a/configs/P1010RDB-PA_SDCARD_defconfig
+++ b/configs/P1010RDB-PA_SDCARD_defconfig
@@ -78,4 +78,3 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig
index c81b53d..4863d60 100644
--- a/configs/P1010RDB-PA_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PA_SPIFLASH_defconfig
@@ -80,4 +80,3 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig
index 8aa8add..1f3f475 100644
--- a/configs/P1010RDB-PB_36BIT_NAND_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig
@@ -85,5 +85,4 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig
index db2650e..db3ee24 100644
--- a/configs/P1010RDB-PB_36BIT_NOR_defconfig
+++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig
@@ -67,5 +67,4 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
index 179752a..329bd4b 100644
--- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig
@@ -79,5 +79,4 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
index d4155ea..d639f45 100644
--- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig
@@ -81,5 +81,4 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig
index 52c72aa..a2bc41c 100644
--- a/configs/P1010RDB-PB_NAND_defconfig
+++ b/configs/P1010RDB-PB_NAND_defconfig
@@ -84,4 +84,3 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig
index 59a2ffc..e8dd323 100644
--- a/configs/P1010RDB-PB_NOR_defconfig
+++ b/configs/P1010RDB-PB_NOR_defconfig
@@ -66,4 +66,3 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig
index 9963a37..709e4ac 100644
--- a/configs/P1010RDB-PB_SDCARD_defconfig
+++ b/configs/P1010RDB-PB_SDCARD_defconfig
@@ -78,4 +78,3 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig
index 422d9c4..e8abb67 100644
--- a/configs/P1010RDB-PB_SPIFLASH_defconfig
+++ b/configs/P1010RDB-PB_SPIFLASH_defconfig
@@ -80,4 +80,3 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 9826273..32efb87 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -49,7 +49,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 4fb28d1..c73c9db 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -45,7 +45,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index e00da7e..d02bd75 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -47,7 +47,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index fbb03e8..fb5285f 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -34,7 +34,6 @@
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index bd79617..5428057 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -48,7 +48,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index 72c9489..591c278 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -44,7 +44,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index a9a38e1..6bccd7c 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -46,7 +46,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index a9576ef..b591903 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -33,7 +33,6 @@
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index d26031d..8ec246d 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -51,7 +51,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index 7ec37fc..c9e2f59 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -47,7 +47,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index e3d7a76..2791eef 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -49,7 +49,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index dcc5a79..0e5ce38 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -36,7 +36,6 @@
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index 9d4540d..f977428 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -53,7 +53,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 84a4689..0e7be2b 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -49,7 +49,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index 00667c8..5c53a70 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -51,7 +51,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index bc84bf8..565a537 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -38,7 +38,6 @@
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 8927cc8..aca3e28 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -52,7 +52,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index f84f18b..3f317fd 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -48,7 +48,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 622b51c..755674d 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -50,7 +50,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index 900aa0d..e49bc11 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -37,7 +37,6 @@
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 8abbe00..c434ebd 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index fd775a7..e259780 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 781cdba..a9682df 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -35,7 +35,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 79e44cb..7b6c0ed 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -33,7 +33,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 54fb21d..9c9ab0d 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -33,7 +33,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index 83368ca..7a59d0d 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -33,7 +33,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index c0afe88..3ae8ea6 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index e60c9b3..8734186 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -32,7 +32,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 4b81467..6646e59 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -33,7 +33,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 8c32529..0290987 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index 5b2a2f1..16bc722 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -32,7 +32,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 2fdc904..86c14b6 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index cd19132..d8bab74 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -33,7 +33,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 7ed70f0..f2b5d74 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 708a8d4..331579a 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -32,7 +32,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T1023RDB_SECURE_BOOT_defconfig b/configs/T1023RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index 8fe44cb..0000000
--- a/configs/T1023RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_SYS_MEMTEST_START=0x00200000
-CONFIG_SYS_MEMTEST_END=0x00400000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1023RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_MEMTEST=y
-CONFIG_SYS_ALT_MEMTEST=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_AQUANTIA=y
-CONFIG_PHY_REALTEK=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig
index f9776ffe..a298779 100644
--- a/configs/T1024RDB_NAND_defconfig
+++ b/configs/T1024RDB_NAND_defconfig
@@ -56,7 +56,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig
index 529522a..e4ad738 100644
--- a/configs/T1024RDB_SDCARD_defconfig
+++ b/configs/T1024RDB_SDCARD_defconfig
@@ -54,7 +54,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T1024RDB_SECURE_BOOT_defconfig b/configs/T1024RDB_SECURE_BOOT_defconfig
index f33c002..df639b2 100644
--- a/configs/T1024RDB_SECURE_BOOT_defconfig
+++ b/configs/T1024RDB_SECURE_BOOT_defconfig
@@ -63,7 +63,6 @@
CONFIG_DM_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig
index fe01675..c2cda97 100644
--- a/configs/T1024RDB_SPIFLASH_defconfig
+++ b/configs/T1024RDB_SPIFLASH_defconfig
@@ -56,7 +56,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig
index 4b95136..05cd138 100644
--- a/configs/T1024RDB_defconfig
+++ b/configs/T1024RDB_defconfig
@@ -42,7 +42,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T1040D4RDB_SECURE_BOOT_defconfig b/configs/T1040D4RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index 88d54fc..0000000
--- a/configs/T1040D4RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040D4RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1040RDB_SECURE_BOOT_defconfig b/configs/T1040RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index ba660ea..0000000
--- a/configs/T1040RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1040RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_ETHSW=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig
index 54bcc2f..473b029 100644
--- a/configs/T1042D4RDB_NAND_defconfig
+++ b/configs/T1042D4RDB_NAND_defconfig
@@ -51,7 +51,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig
index 853a3d6..cf1f145 100644
--- a/configs/T1042D4RDB_SDCARD_defconfig
+++ b/configs/T1042D4RDB_SDCARD_defconfig
@@ -49,7 +49,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T1042D4RDB_SECURE_BOOT_defconfig b/configs/T1042D4RDB_SECURE_BOOT_defconfig
index bca800f..b36b36a 100644
--- a/configs/T1042D4RDB_SECURE_BOOT_defconfig
+++ b/configs/T1042D4RDB_SECURE_BOOT_defconfig
@@ -59,7 +59,6 @@
CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
CONFIG_ADDR_MAP=y
CONFIG_SYS_NUM_ADDR_MAP=64
CONFIG_RSA=y
diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig
index cef5295..15b97a9 100644
--- a/configs/T1042D4RDB_SPIFLASH_defconfig
+++ b/configs/T1042D4RDB_SPIFLASH_defconfig
@@ -51,7 +51,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig
index 85e2bea..50713e6 100644
--- a/configs/T1042D4RDB_defconfig
+++ b/configs/T1042D4RDB_defconfig
@@ -37,7 +37,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig b/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
deleted file mode 100644
index 701257c..0000000
--- a/configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,84 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0x30001000
-CONFIG_SPL_LIBCOMMON_SUPPORT=y
-CONFIG_SPL_LIBGENERIC_SUPPORT=y
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_SPL_TEXT_BASE=0xFFFD8000
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_SPL=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB_PI=y
-CONFIG_SYS_CUSTOM_LDSCRIPT=y
-CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL"
-CONFIG_BOOTDELAY=0
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-# CONFIG_SPL_FRAMEWORK is not set
-CONFIG_SPL_NAND_BOOT=y
-CONFIG_SPL_FSL_PBL=y
-CONFIG_SPL_CRYPTO_SUPPORT=y
-CONFIG_SPL_HASH_SUPPORT=y
-CONFIG_SPL_ENV_SUPPORT=y
-CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_SPL_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T1042RDB_SECURE_BOOT_defconfig b/configs/T1042RDB_SECURE_BOOT_defconfig
deleted file mode 100644
index eb03ba6..0000000
--- a/configs/T1042RDB_SECURE_BOOT_defconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xEFF40000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_NXP_ESBC=y
-CONFIG_MPC85xx=y
-CONFIG_TARGET_T1042RDB=y
-# CONFIG_SYS_MALLOC_F is not set
-CONFIG_FIT=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-CONFIG_SILENT_CONSOLE=y
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_BOARD_EARLY_INIT_F=y
-CONFIG_BOARD_EARLY_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_GREPENV=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-CONFIG_MP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
-CONFIG_ENV_OVERWRITE=y
-CONFIG_DM=y
-CONFIG_SYS_FSL_DDR3=y
-CONFIG_FSL_ESDHC=y
-CONFIG_MTD=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_FLASH_CFI_MTD=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_MODE=0
-CONFIG_SF_DEFAULT_SPEED=10000000
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_PHYLIB=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_FMAN_ENET=y
-CONFIG_MII=y
-CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
-CONFIG_SYS_NS16550=y
-CONFIG_SPI=y
-CONFIG_FSL_ESPI=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_ADDR_MAP=y
-CONFIG_SYS_NUM_ADDR_MAP=64
-CONFIG_RSA=y
-CONFIG_SPL_RSA=y
-CONFIG_RSA_SOFTWARE_EXP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig
index 8d3000e..ffd23fa 100644
--- a/configs/T2080QDS_NAND_defconfig
+++ b/configs/T2080QDS_NAND_defconfig
@@ -48,7 +48,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig
index 8427c3d..cb5d7ff 100644
--- a/configs/T2080QDS_SDCARD_defconfig
+++ b/configs/T2080QDS_SDCARD_defconfig
@@ -46,7 +46,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig
index d37408c..4d33dc6 100644
--- a/configs/T2080QDS_SECURE_BOOT_defconfig
+++ b/configs/T2080QDS_SECURE_BOOT_defconfig
@@ -33,7 +33,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig
index 0432f61..1029a8e 100644
--- a/configs/T2080QDS_SPIFLASH_defconfig
+++ b/configs/T2080QDS_SPIFLASH_defconfig
@@ -48,7 +48,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
index d476934..0677053 100644
--- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
+++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig
@@ -31,7 +31,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig
index c823eb5..c9d1fec 100644
--- a/configs/T2080QDS_defconfig
+++ b/configs/T2080QDS_defconfig
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig
index 3bb7433..2b95637 100644
--- a/configs/T2080RDB_NAND_defconfig
+++ b/configs/T2080RDB_NAND_defconfig
@@ -53,7 +53,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig
index bcd67a0..e47234d 100644
--- a/configs/T2080RDB_SDCARD_defconfig
+++ b/configs/T2080RDB_SDCARD_defconfig
@@ -51,7 +51,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig
index 198e926..d4431d6 100644
--- a/configs/T2080RDB_SPIFLASH_defconfig
+++ b/configs/T2080RDB_SPIFLASH_defconfig
@@ -53,7 +53,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig
index 12aaccd..39adbcf 100644
--- a/configs/T2080RDB_defconfig
+++ b/configs/T2080RDB_defconfig
@@ -39,7 +39,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig
index 2def901..73b90c2 100644
--- a/configs/T4240RDB_SDCARD_defconfig
+++ b/configs/T4240RDB_SDCARD_defconfig
@@ -44,7 +44,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig
index 8a0c122..b931eb0 100644
--- a/configs/T4240RDB_defconfig
+++ b/configs/T4240RDB_defconfig
@@ -32,7 +32,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/UCP1020_defconfig b/configs/UCP1020_defconfig
index 3666cee..a016a85 100644
--- a/configs/UCP1020_defconfig
+++ b/configs/UCP1020_defconfig
@@ -35,7 +35,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEC0C0000
-# CONFIG_SATA_SIL is not set
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/adp-ae3xx_defconfig b/configs/adp-ae3xx_defconfig
index bd531b1..9349583 100644
--- a/configs/adp-ae3xx_defconfig
+++ b/configs/adp-ae3xx_defconfig
@@ -29,7 +29,6 @@
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_FTSDC010=y
CONFIG_FTSDC010_SDIO=y
CONFIG_MTD=y
diff --git a/configs/adp-ag101p_defconfig b/configs/adp-ag101p_defconfig
index 989ff1a..3e898e5 100644
--- a/configs/adp-ag101p_defconfig
+++ b/configs/adp-ag101p_defconfig
@@ -26,7 +26,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_FTSDC010=y
CONFIG_FTSDC010_SDIO=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig
index 153266f..e8dc816 100644
--- a/configs/ae350_rv32_spl_defconfig
+++ b/configs/ae350_rv32_spl_defconfig
@@ -2,7 +2,9 @@
CONFIG_SYS_TEXT_BASE=0x01200000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig
index 651b1eb..494cb65 100644
--- a/configs/ae350_rv32_spl_xip_defconfig
+++ b/configs/ae350_rv32_spl_xip_defconfig
@@ -3,7 +3,9 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_TEXT_BASE=0x80000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_32"
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
diff --git a/configs/ae350_rv64_spl_defconfig b/configs/ae350_rv64_spl_defconfig
index f434091..d23b56c 100644
--- a/configs/ae350_rv64_spl_defconfig
+++ b/configs/ae350_rv64_spl_defconfig
@@ -2,7 +2,9 @@
CONFIG_SYS_TEXT_BASE=0x01200000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
diff --git a/configs/ae350_rv64_spl_xip_defconfig b/configs/ae350_rv64_spl_xip_defconfig
index b0afdb4..adc9d66 100644
--- a/configs/ae350_rv64_spl_xip_defconfig
+++ b/configs/ae350_rv64_spl_xip_defconfig
@@ -3,7 +3,9 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_TEXT_BASE=0x80000000
+CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="ae350_64"
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
diff --git a/configs/alt_defconfig b/configs/alt_defconfig
index db5e297..d833b20 100644
--- a/configs/alt_defconfig
+++ b/configs/alt_defconfig
@@ -66,7 +66,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index df01273..8d0e9f8 100644
--- a/configs/am335x_baltos_defconfig
+++ b/configs/am335x_baltos_defconfig
@@ -51,7 +51,6 @@
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_OMAP24_I2C_SPEED=1000
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP_HS_ADMA=y
CONFIG_MTD=y
diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig
index 6d55d83..e0d144e 100644
--- a/configs/am335x_boneblack_vboot_defconfig
+++ b/configs/am335x_boneblack_vboot_defconfig
@@ -46,7 +46,6 @@
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
# CONFIG_SPL_DM_MMC is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index c4d3bd0..edb5628 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -13,7 +13,6 @@
CONFIG_LOGLEVEL=3
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_MISC_INIT=y
-CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_FIT_IMAGE_TINY=y
CONFIG_SPL_ETH_SUPPORT=y
# CONFIG_SPL_FS_EXT4 is not set
@@ -58,7 +57,6 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig
index b1c80c1..24c5b34 100644
--- a/configs/am335x_evm_spiboot_defconfig
+++ b/configs/am335x_evm_spiboot_defconfig
@@ -54,7 +54,6 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
# CONFIG_SPL_DM_MMC is not set
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index f6cf80e..b4d3575 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -50,7 +50,6 @@
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index f06b10b..f0c75cd 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -52,7 +52,6 @@
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig
index efa0573..6ebf8f8 100644
--- a/configs/am335x_igep003x_defconfig
+++ b/configs/am335x_igep003x_defconfig
@@ -68,7 +68,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/am335x_pdu001_defconfig b/configs/am335x_pdu001_defconfig
index a2db4cf..81f211b 100644
--- a/configs/am335x_pdu001_defconfig
+++ b/configs/am335x_pdu001_defconfig
@@ -41,7 +41,6 @@
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_SDHCI=y
CONFIG_PINCTRL=y
diff --git a/configs/am335x_shc_defconfig b/configs/am335x_shc_defconfig
index dafd699..caabdf4 100644
--- a/configs/am335x_shc_defconfig
+++ b/configs/am335x_shc_defconfig
@@ -51,7 +51,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
diff --git a/configs/am335x_shc_ict_defconfig b/configs/am335x_shc_ict_defconfig
index 0325cd1..b1912ce 100644
--- a/configs/am335x_shc_ict_defconfig
+++ b/configs/am335x_shc_ict_defconfig
@@ -52,7 +52,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
diff --git a/configs/am335x_shc_netboot_defconfig b/configs/am335x_shc_netboot_defconfig
index e47e114..a533c39 100644
--- a/configs/am335x_shc_netboot_defconfig
+++ b/configs/am335x_shc_netboot_defconfig
@@ -52,7 +52,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
diff --git a/configs/am335x_shc_sdboot_defconfig b/configs/am335x_shc_sdboot_defconfig
index 3dc9460..fb81579 100644
--- a/configs/am335x_shc_sdboot_defconfig
+++ b/configs/am335x_shc_sdboot_defconfig
@@ -51,7 +51,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_SMSC=y
diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig
index 8ae7c1b..bc0f2dd 100644
--- a/configs/am335x_sl50_defconfig
+++ b/configs/am335x_sl50_defconfig
@@ -57,7 +57,6 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig
index 0bc7bf7..0b9bd0e 100644
--- a/configs/am3517_evm_defconfig
+++ b/configs/am3517_evm_defconfig
@@ -12,10 +12,10 @@
CONFIG_SPL_SYS_MALLOC_F_LEN=0x3000
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="am3517-evm"
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=10
# CONFIG_USE_BOOTCOMMAND is not set
-CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig
index 81d43cc..6782695 100644
--- a/configs/am43xx_evm_defconfig
+++ b/configs/am43xx_evm_defconfig
@@ -54,7 +54,6 @@
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/am43xx_evm_qspiboot_defconfig b/configs/am43xx_evm_qspiboot_defconfig
index 095c225..fb8c78d 100644
--- a/configs/am43xx_evm_qspiboot_defconfig
+++ b/configs/am43xx_evm_qspiboot_defconfig
@@ -43,7 +43,6 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SF_DEFAULT_SPEED=48000000
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig
index 623be72..7b2cb8e 100644
--- a/configs/am43xx_evm_rtconly_defconfig
+++ b/configs/am43xx_evm_rtconly_defconfig
@@ -41,7 +41,6 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 63f15e0..a8827e6 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -60,7 +60,6 @@
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 8357b81..8c9ba77 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -59,7 +59,6 @@
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/am57xx_evm_defconfig b/configs/am57xx_evm_defconfig
index 4da4aaa..6157bd1 100644
--- a/configs/am57xx_evm_defconfig
+++ b/configs/am57xx_evm_defconfig
@@ -78,7 +78,6 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index 65b9bdd..3de2208 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -74,7 +74,6 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 35f9027..20da3a0 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -81,7 +81,6 @@
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig
new file mode 100644
index 0000000..fbce9e9
--- /dev/null
+++ b/configs/am64x_evm_a53_defconfig
@@ -0,0 +1,143 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_SOC_K3_AM642=y
+CONFIG_K3_ATF_LOAD_ADDR=0x701a0000
+CONFIG_TARGET_AM642_A53_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x80080000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am642-evm"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run get_kern_${boot}; run get_fdt_${boot}; run run_kern"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_DMA=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_TIME=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="k3-am642-evm k3-am642-sk"
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DMA_CHANNELS=y
+CONFIG_TI_K3_NAVSS_UDMA=y
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHY_TI_DP83867=y
+CONFIG_PHY_FIXED=y
+CONFIG_DM_ETH=y
+CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_DM_SERIAL=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_SOC_TI=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_CMD_DFU=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_USB=y
+CONFIG_DFU=y
+CONFIG_DFU_OVER_USB=y
+# CONFIG_DFU_TFTP is not set
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+# CONFIG_DFU_VIRT is not set
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3_TI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_MASS_STORAGE=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
new file mode 100644
index 0000000..3e9b565
--- /dev/null
+++ b/configs/am64x_evm_r5_defconfig
@@ -0,0 +1,136 @@
+CONFIG_ARM=y
+CONFIG_ARCH_K3=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SOC_K3_AM642=y
+CONFIG_TARGET_AM642_R5_EVM=y
+CONFIG_ENV_SIZE=0x20000
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_TEXT_BASE=0x70000000
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL_SIZE_LIMIT=0x190000
+CONFIG_SPL_SIZE_LIMIT_PROVIDE_STACK=0x4000
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y
+CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y
+CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_EARLY_BSS=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_REMOTEPROC=y
+CONFIG_SPL_SPI_LOAD=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_STORAGE=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_REMOTEPROC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TIME=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-am642-r5-evm k3-am642-r5-sk"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_DM=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_TI_SCI=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
+CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OMAP24XX=y
+CONFIG_DM_MAILBOX=y
+CONFIG_K3_SEC_PROXY=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_SPL_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_AM654=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PINCTRL=y
+# CONFIG_PINCTRL_GENERIC is not set
+CONFIG_SPL_PINCTRL=y
+# CONFIG_SPL_PINCTRL_GENERIC is not set
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_SPL_DM_REGULATOR_GPIO=y
+CONFIG_K3_SYSTEM_CONTROLLER=y
+CONFIG_REMOTEPROC_TI_K3_ARM64=y
+CONFIG_DM_RESET=y
+CONFIG_RESET_TI_SCI=y
+CONFIG_SPECIFY_CONSOLE_INDEX=y
+CONFIG_DM_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_SPL_DM_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_HOST=y
+CONFIG_USB_CDNS3_TI=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 1f2d78d..7f2b825 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -90,6 +90,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
@@ -100,7 +102,6 @@
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
@@ -124,7 +125,6 @@
CONFIG_CMD_E1000=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PCI=y
-CONFIG_DM_PCI=y
CONFIG_PCI_KEYSTONE=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 57f3300..164c665 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -88,7 +88,6 @@
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_K3_AVS0=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index 1616342..b45a6d2 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -65,6 +65,8 @@
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_TI_SCI=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
index a9737d0..33526f0 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -85,6 +85,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
@@ -94,7 +96,6 @@
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
@@ -113,7 +114,6 @@
CONFIG_CMD_E1000=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PCI=y
-CONFIG_DM_PCI=y
CONFIG_PCI_KEYSTONE=y
CONFIG_PHY=y
CONFIG_AM654_PHY=y
diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig
index d54f209..5c1949f 100644
--- a/configs/am65x_hs_evm_r5_defconfig
+++ b/configs/am65x_hs_evm_r5_defconfig
@@ -85,7 +85,6 @@
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_K3_AVS0=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
diff --git a/configs/apalis-imx8_defconfig b/configs/apalis-imx8_defconfig
index 2450797..b03a0e2 100644
--- a/configs/apalis-imx8_defconfig
+++ b/configs/apalis-imx8_defconfig
@@ -37,13 +37,13 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_TFTP_TSIZE=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/apalis-imx8x_defconfig b/configs/apalis-imx8x_defconfig
index 777d3a9..0d225db 100644
--- a/configs/apalis-imx8x_defconfig
+++ b/configs/apalis-imx8x_defconfig
@@ -40,6 +40,7 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_TFTP_TSIZE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_CLK_IMX8=y
@@ -50,7 +51,6 @@
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig
index 5da83e9..7c67306 100644
--- a/configs/apalis-tk1_defconfig
+++ b/configs/apalis-tk1_defconfig
@@ -38,6 +38,7 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
+CONFIG_TFTP_TSIZE=y
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SUPPORT_EMMC_BOOT=y
diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig
index 1c791ab..e1817c3 100644
--- a/configs/apalis_imx6_defconfig
+++ b/configs/apalis_imx6_defconfig
@@ -70,7 +70,6 @@
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig
index 85f9ce9..d23f057 100644
--- a/configs/apalis_t30_defconfig
+++ b/configs/apalis_t30_defconfig
@@ -33,6 +33,7 @@
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
+CONFIG_TFTP_TSIZE=y
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_E1000=y
diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig
index df0b26d..4d9cb5b 100644
--- a/configs/aristainetos2c_defconfig
+++ b/configs/aristainetos2c_defconfig
@@ -77,7 +77,6 @@
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig
index 0156493..dd63e8f 100644
--- a/configs/aristainetos2ccslb_defconfig
+++ b/configs/aristainetos2ccslb_defconfig
@@ -77,7 +77,6 @@
CONFIG_LED_GPIO=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/at91sam9263ek_dataflash_cs0_defconfig b/configs/at91sam9263ek_dataflash_cs0_defconfig
index cee2b72..c417441 100644
--- a/configs/at91sam9263ek_dataflash_cs0_defconfig
+++ b/configs/at91sam9263ek_dataflash_cs0_defconfig
@@ -43,7 +43,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9263ek_dataflash_defconfig b/configs/at91sam9263ek_dataflash_defconfig
index cee2b72..c417441 100644
--- a/configs/at91sam9263ek_dataflash_defconfig
+++ b/configs/at91sam9263ek_dataflash_defconfig
@@ -43,7 +43,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9263ek_nandflash_defconfig b/configs/at91sam9263ek_nandflash_defconfig
index 4f5a9d4..d7f0238 100644
--- a/configs/at91sam9263ek_nandflash_defconfig
+++ b/configs/at91sam9263ek_nandflash_defconfig
@@ -40,7 +40,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig
index 7ee13e3..0547947 100644
--- a/configs/at91sam9263ek_norflash_boot_defconfig
+++ b/configs/at91sam9263ek_norflash_boot_defconfig
@@ -40,7 +40,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig
index 4eba692..a41ad60b 100644
--- a/configs/at91sam9263ek_norflash_defconfig
+++ b/configs/at91sam9263ek_norflash_defconfig
@@ -40,7 +40,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/at91sam9g20ek_2mmc_defconfig b/configs/at91sam9g20ek_2mmc_defconfig
index 67dbca0..25b4309 100644
--- a/configs/at91sam9g20ek_2mmc_defconfig
+++ b/configs/at91sam9g20ek_2mmc_defconfig
@@ -38,7 +38,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9g20ek_2mmc_nandflash_defconfig b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
index 6bba1ab..32cb46d 100644
--- a/configs/at91sam9g20ek_2mmc_nandflash_defconfig
+++ b/configs/at91sam9g20ek_2mmc_nandflash_defconfig
@@ -38,7 +38,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig
index 2c4bbd0..f8efca1 100644
--- a/configs/at91sam9m10g45ek_mmc_defconfig
+++ b/configs/at91sam9m10g45ek_mmc_defconfig
@@ -38,7 +38,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig
index 4494f8d..e5c270a 100644
--- a/configs/at91sam9m10g45ek_nandflash_defconfig
+++ b/configs/at91sam9m10g45ek_nandflash_defconfig
@@ -39,7 +39,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig
index ad6ab85..bc15efe 100644
--- a/configs/at91sam9n12ek_mmc_defconfig
+++ b/configs/at91sam9n12ek_mmc_defconfig
@@ -37,7 +37,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig
index 42d86fd..084376d 100644
--- a/configs/at91sam9n12ek_nandflash_defconfig
+++ b/configs/at91sam9n12ek_nandflash_defconfig
@@ -38,7 +38,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig
index c6ac366..44670fa 100644
--- a/configs/at91sam9n12ek_spiflash_defconfig
+++ b/configs/at91sam9n12ek_spiflash_defconfig
@@ -39,7 +39,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9rlek_dataflash_defconfig b/configs/at91sam9rlek_dataflash_defconfig
index 7e2b635..c7b3012 100644
--- a/configs/at91sam9rlek_dataflash_defconfig
+++ b/configs/at91sam9rlek_dataflash_defconfig
@@ -41,7 +41,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9rlek_mmc_defconfig b/configs/at91sam9rlek_mmc_defconfig
index f8fe961..71a4cb4 100644
--- a/configs/at91sam9rlek_mmc_defconfig
+++ b/configs/at91sam9rlek_mmc_defconfig
@@ -37,7 +37,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9rlek_nandflash_defconfig b/configs/at91sam9rlek_nandflash_defconfig
index 60715a0..9551aed 100644
--- a/configs/at91sam9rlek_nandflash_defconfig
+++ b/configs/at91sam9rlek_nandflash_defconfig
@@ -38,7 +38,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig
index b6d6a30..596b170 100644
--- a/configs/at91sam9x5ek_dataflash_defconfig
+++ b/configs/at91sam9x5ek_dataflash_defconfig
@@ -42,7 +42,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig
index 9acdbb8..27d5490 100644
--- a/configs/at91sam9x5ek_mmc_defconfig
+++ b/configs/at91sam9x5ek_mmc_defconfig
@@ -40,7 +40,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig
index 2b1256d..62da989 100644
--- a/configs/at91sam9x5ek_nandflash_defconfig
+++ b/configs/at91sam9x5ek_nandflash_defconfig
@@ -41,7 +41,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig
index 25de37f..1bb8cac 100644
--- a/configs/at91sam9x5ek_spiflash_defconfig
+++ b/configs/at91sam9x5ek_spiflash_defconfig
@@ -42,7 +42,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/axs101_defconfig b/configs/axs101_defconfig
index 9dbc594..4a403ee 100644
--- a/configs/axs101_defconfig
+++ b/configs/axs101_defconfig
@@ -33,7 +33,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MTD=y
diff --git a/configs/axs103_defconfig b/configs/axs103_defconfig
index 399ec9c..c04604e 100644
--- a/configs/axs103_defconfig
+++ b/configs/axs103_defconfig
@@ -33,7 +33,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MTD=y
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index 429de94..95a9135 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -47,6 +47,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/bcm7260_defconfig b/configs/bcm7260_defconfig
index d1b0530..a42a6ac 100644
--- a/configs/bcm7260_defconfig
+++ b/configs/bcm7260_defconfig
@@ -28,7 +28,6 @@
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_MTD=y
diff --git a/configs/bcm7445_defconfig b/configs/bcm7445_defconfig
index 1f9ab48..96e8da0 100644
--- a/configs/bcm7445_defconfig
+++ b/configs/bcm7445_defconfig
@@ -29,7 +29,6 @@
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCMSTB=y
CONFIG_MTD=y
diff --git a/configs/bcm_ns3_defconfig b/configs/bcm_ns3_defconfig
index 5fb82e9..f158b82 100644
--- a/configs/bcm_ns3_defconfig
+++ b/configs/bcm_ns3_defconfig
@@ -19,7 +19,7 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot> "
-CONFIG_SYS_XTRACE=n
+# CONFIG_SYS_XTRACE is not set
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_MMC=y
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_CLK=y
CONFIG_CLK_CCF=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_IPROC=y
diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig
index 4c89244..cf18fee 100644
--- a/configs/beaver_defconfig
+++ b/configs/beaver_defconfig
@@ -34,6 +34,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/beelink-gtking_defconfig b/configs/beelink-gtking_defconfig
index 12caa58..cb2f3e3 100644
--- a/configs/beelink-gtking_defconfig
+++ b/configs/beelink-gtking_defconfig
@@ -26,16 +26,15 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
diff --git a/configs/beelink-gtkingpro_defconfig b/configs/beelink-gtkingpro_defconfig
index 2b022e4..771d250 100644
--- a/configs/beelink-gtkingpro_defconfig
+++ b/configs/beelink-gtkingpro_defconfig
@@ -26,16 +26,15 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
diff --git a/configs/bk4r1_defconfig b/configs/bk4r1_defconfig
index 85e20610..e6583bc 100644
--- a/configs/bk4r1_defconfig
+++ b/configs/bk4r1_defconfig
@@ -62,7 +62,6 @@
CONFIG_SYS_EEPROM_SIZE=32768
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig
index 2d3c893..e6f0795 100644
--- a/configs/blanche_defconfig
+++ b/configs/blanche_defconfig
@@ -46,7 +46,6 @@
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
diff --git a/configs/brppt1_mmc_defconfig b/configs/brppt1_mmc_defconfig
index 5f96aa8..2c73ece 100644
--- a/configs/brppt1_mmc_defconfig
+++ b/configs/brppt1_mmc_defconfig
@@ -83,7 +83,6 @@
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_NATSEMI=y
CONFIG_DM_ETH=y
diff --git a/configs/brppt1_spi_defconfig b/configs/brppt1_spi_defconfig
index 437146e..37e7e3d 100644
--- a/configs/brppt1_spi_defconfig
+++ b/configs/brppt1_spi_defconfig
@@ -90,7 +90,6 @@
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/brsmarc1_defconfig b/configs/brsmarc1_defconfig
index 10997b8..c27dd92 100644
--- a/configs/brsmarc1_defconfig
+++ b/configs/brsmarc1_defconfig
@@ -89,7 +89,6 @@
# CONFIG_SPL_BLK is not set
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/brxre1_defconfig b/configs/brxre1_defconfig
index 2832ed1..c1014db 100644
--- a/configs/brxre1_defconfig
+++ b/configs/brxre1_defconfig
@@ -80,7 +80,6 @@
# CONFIG_OF_TRANSLATE is not set
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_ETH=y
CONFIG_DRIVER_TI_CPSW=y
@@ -93,8 +92,6 @@
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_SYS_WHITE_ON_BLACK=y
-CONFIG_AM335X_LCD=y
-CONFIG_LCD=y
CONFIG_SPL_TINY_MEMSET=y
# CONFIG_OF_LIBFDT_OVERLAY is not set
# CONFIG_EFI_LOADER is not set
diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig
index 987e3ac..c1ff9d7 100644
--- a/configs/cei-tk1-som_defconfig
+++ b/configs/cei-tk1-som_defconfig
@@ -34,6 +34,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig
index 01d15eb..24f992d 100644
--- a/configs/cherryhill_defconfig
+++ b/configs/cherryhill_defconfig
@@ -35,6 +35,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig
index 1d6075b..656f72a 100644
--- a/configs/chiliboard_defconfig
+++ b/configs/chiliboard_defconfig
@@ -48,7 +48,6 @@
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/chromebook_coral_defconfig b/configs/chromebook_coral_defconfig
index 4823913..d785c9b 100644
--- a/configs/chromebook_coral_defconfig
+++ b/configs/chromebook_coral_defconfig
@@ -32,8 +32,6 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS_SUBST=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_LOGF_FUNC=y
-CONFIG_SPL_LOG=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_BLOBLIST=y
@@ -75,6 +73,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_SPL_REMOVE_PROPS="clocks clock-names interrupt-parent interrupts linux-name acpi,name acpi,path u-boot,acpi-dsdt-order u-boot,acpi-ssdt-order"
CONFIG_ENV_OVERWRITE=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig
index 872e33d..e6c6c38 100644
--- a/configs/chromebook_link64_defconfig
+++ b/configs/chromebook_link64_defconfig
@@ -59,6 +59,7 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 60a7640..6a69938 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -50,6 +50,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig
index 71b5f8b..c839e20 100644
--- a/configs/chromebook_samus_defconfig
+++ b/configs/chromebook_samus_defconfig
@@ -52,6 +52,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 49461db..5f11c59 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -44,6 +44,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CROS_EC=y
diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig
index 56a479f..29efd26 100644
--- a/configs/ci20_mmc_defconfig
+++ b/configs/ci20_mmc_defconfig
@@ -36,7 +36,6 @@
CONFIG_JZ4780_EFUSE=y
CONFIG_MMC=y
CONFIG_MMC_BROKEN_CD=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig
index 4916d99..9af4e67 100644
--- a/configs/cl-som-imx7_defconfig
+++ b/configs/cl-som-imx7_defconfig
@@ -60,7 +60,6 @@
CONFIG_SPL_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_CMD_PCA953X=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index 232688b..53c2bdb 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -50,7 +50,6 @@
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
diff --git a/configs/clearfog_gt_8k_defconfig b/configs/clearfog_gt_8k_defconfig
index 9bb1f21..69694b5 100644
--- a/configs/clearfog_gt_8k_defconfig
+++ b/configs/clearfog_gt_8k_defconfig
@@ -45,7 +45,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index aed25b6..aefda70 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -63,7 +63,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
# CONFIG_DWC_AHSATA_AHCI is not set
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig
index 0bcc3c7..3548009 100644
--- a/configs/cm_t43_defconfig
+++ b/configs/cm_t43_defconfig
@@ -61,7 +61,6 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_DM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/colibri-imx6ull_defconfig b/configs/colibri-imx6ull_defconfig
index 5e18f66..bec5fd7 100644
--- a/configs/colibri-imx6ull_defconfig
+++ b/configs/colibri-imx6ull_defconfig
@@ -58,13 +58,14 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
+CONFIG_TFTP_TSIZE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/colibri-imx8x_defconfig b/configs/colibri-imx8x_defconfig
index dab8a92..eba334b 100644
--- a/configs/colibri-imx8x_defconfig
+++ b/configs/colibri-imx8x_defconfig
@@ -35,13 +35,13 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
+CONFIG_TFTP_TSIZE=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig
index 9e03ac0..956806e 100644
--- a/configs/colibri_imx6_defconfig
+++ b/configs/colibri_imx6_defconfig
@@ -69,7 +69,6 @@
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
diff --git a/configs/colibri_imx7_defconfig b/configs/colibri_imx7_defconfig
index 71e331e..24dd852 100644
--- a/configs/colibri_imx7_defconfig
+++ b/configs/colibri_imx7_defconfig
@@ -10,7 +10,6 @@
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_IMX_HAB=y
-# CONFIG_CMD_DEKBLOB is not set
CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-rawnand"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/toradex/colibri_imx7/imximage.cfg,MX7D"
@@ -63,7 +62,6 @@
CONFIG_FSL_CAAM=y
CONFIG_DFU_NAND=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/colibri_imx7_emmc_defconfig b/configs/colibri_imx7_emmc_defconfig
index c5a6c44..86eb3a4 100644
--- a/configs/colibri_imx7_emmc_defconfig
+++ b/configs/colibri_imx7_emmc_defconfig
@@ -11,7 +11,6 @@
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_IMX_HAB=y
-# CONFIG_CMD_DEKBLOB is not set
CONFIG_DEFAULT_DEVICE_TREE="imx7-colibri-emmc"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
@@ -63,7 +62,6 @@
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/colibri_pxa270_defconfig b/configs/colibri_pxa270_defconfig
index 2865730..ec62ec3 100644
--- a/configs/colibri_pxa270_defconfig
+++ b/configs/colibri_pxa270_defconfig
@@ -35,7 +35,6 @@
CONFIG_ENV_ADDR=0x80000
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-CONFIG_DM_MMC=y
CONFIG_PXA_MMC_GENERIC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig
index 02f40a8..cacd988 100644
--- a/configs/colibri_t20_defconfig
+++ b/configs/colibri_t20_defconfig
@@ -41,6 +41,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=1536
+CONFIG_TFTP_TSIZE=y
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_MTD=y
diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig
index d074058..3707e36 100644
--- a/configs/colibri_t30_defconfig
+++ b/configs/colibri_t30_defconfig
@@ -32,6 +32,7 @@
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=16352
+CONFIG_TFTP_TSIZE=y
CONFIG_SPL_DM=y
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SYS_NS16550=y
diff --git a/configs/colibri_vf_defconfig b/configs/colibri_vf_defconfig
index abac672..13399ca 100644
--- a/configs/colibri_vf_defconfig
+++ b/configs/colibri_vf_defconfig
@@ -62,8 +62,8 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_DM=y
CONFIG_DFU_NAND=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_VYBRID_GPIO=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index fd99d36..cc271bd 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -54,6 +54,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 32df445..203306d 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -50,6 +50,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/controlcenterdc_defconfig b/configs/controlcenterdc_defconfig
index 1bbd28c..ba0a87d 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -59,7 +59,6 @@
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SF_DEFAULT_BUS=1
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig
index e3cfdbc..84ff128 100644
--- a/configs/coreboot64_defconfig
+++ b/configs/coreboot64_defconfig
@@ -41,6 +41,7 @@
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_PCI_PNP is not set
diff --git a/configs/coreboot_defconfig b/configs/coreboot_defconfig
index 501a20e..992f662 100644
--- a/configs/coreboot_defconfig
+++ b/configs/coreboot_defconfig
@@ -36,6 +36,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_PCI_PNP is not set
diff --git a/configs/cortina_presidio-asic-emmc_defconfig b/configs/cortina_presidio-asic-emmc_defconfig
index eec9584..8fcb66f 100644
--- a/configs/cortina_presidio-asic-emmc_defconfig
+++ b/configs/cortina_presidio-asic-emmc_defconfig
@@ -26,7 +26,6 @@
CONFIG_CORTINA_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_CA=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_CORTINA=y
CONFIG_PHYLIB=y
diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig
index 491f563..8206c4c 100644
--- a/configs/corvus_defconfig
+++ b/configs/corvus_defconfig
@@ -51,6 +51,7 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig
index c1d4f9c..b771a2a 100644
--- a/configs/cougarcanyon2_defconfig
+++ b/configs/cougarcanyon2_defconfig
@@ -39,6 +39,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index 397c5a9..0258f31 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -42,6 +42,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig
index 26e76a2..42db153 100644
--- a/configs/da850evm_defconfig
+++ b/configs/da850evm_defconfig
@@ -19,6 +19,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
+CONFIG_LTO=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
@@ -63,7 +64,6 @@
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
-CONFIG_DM_MMC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig
index d3860a9..b595acf 100644
--- a/configs/da850evm_direct_nor_defconfig
+++ b/configs/da850evm_direct_nor_defconfig
@@ -11,6 +11,7 @@
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
+CONFIG_LTO=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="mem=32M console=ttyS2,115200n8 root=/dev/mtdblock2 rw noinitrd ip=dhcp"
@@ -26,7 +27,6 @@
CONFIG_CMD_MX_CYCLIC=y
CONFIG_CMD_DM=y
# CONFIG_CMD_GPT is not set
-# CONFIG_CMD_MMC is not set
CONFIG_CMD_MTD=y
# CONFIG_CMD_PART is not set
# CONFIG_CMD_SF is not set
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig
index 0d0e9a1..7e48293 100644
--- a/configs/da850evm_nand_defconfig
+++ b/configs/da850evm_nand_defconfig
@@ -16,6 +16,7 @@
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="da850-evm"
+CONFIG_LTO=y
CONFIG_SYS_EXTRA_OPTIONS="MAC_ADDR_IN_SPIFLASH"
CONFIG_BOOTDELAY=3
CONFIG_DEFAULT_FDT_FILE="da850-evm.dtb"
@@ -58,7 +59,6 @@
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig
index f2c1e84..fc15212 100644
--- a/configs/dalmore_defconfig
+++ b/configs/dalmore_defconfig
@@ -33,6 +33,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 30276d0..b39e213 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -51,7 +51,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_AHCI_MVEBU=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_MV=y
diff --git a/configs/deneb_defconfig b/configs/deneb_defconfig
index 3a433a8..3889ce0 100644
--- a/configs/deneb_defconfig
+++ b/configs/deneb_defconfig
@@ -76,7 +76,6 @@
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
index 530477c..268fbfe 100644
--- a/configs/dfi-bt700-q7x-151_defconfig
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -48,6 +48,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig
index b8c0f86..934798e 100644
--- a/configs/dh_imx6_defconfig
+++ b/configs/dh_imx6_defconfig
@@ -64,11 +64,11 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
CONFIG_BOOTCOUNT_LIMIT=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig
index becf744..30136d2 100644
--- a/configs/dra7xx_evm_defconfig
+++ b/configs/dra7xx_evm_defconfig
@@ -82,7 +82,6 @@
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig
index a49ae75..6be462d 100644
--- a/configs/dra7xx_hs_evm_defconfig
+++ b/configs/dra7xx_hs_evm_defconfig
@@ -85,7 +85,6 @@
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index bfe9ea1..53e1adf 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -81,7 +81,6 @@
CONFIG_PCF8575_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/draco_defconfig b/configs/draco_defconfig
index fb41d55..e3ccdea 100644
--- a/configs/draco_defconfig
+++ b/configs/draco_defconfig
@@ -62,7 +62,6 @@
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
-# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
@@ -72,9 +71,12 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
@@ -91,7 +93,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_USB_GADGET_VENDOR_NUM=0x0908
diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig
index f5db472..6831372 100644
--- a/configs/dragonboard410c_defconfig
+++ b/configs/dragonboard410c_defconfig
@@ -35,7 +35,6 @@
CONFIG_PM8916_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_PHY=y
diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig
index 13cffd9..d43fdf1 100644
--- a/configs/dragonboard820c_defconfig
+++ b/configs/dragonboard820c_defconfig
@@ -29,7 +29,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_CLK=y
CONFIG_PM8916_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MSM=y
CONFIG_PINCTRL=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index e1c0f69..d852284 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -21,7 +21,6 @@
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 ip=off initrd=0x8000040,8M root=/dev/md0 rw syno_hw_version=DS414r1 ihd_num=4 netif_num=2 flash_size=8 SataLedSpecial=1 HddHotplug=1"
-# CONFIG_USE_PREBOOT is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_R=y
diff --git a/configs/efi-x86_payload32_defconfig b/configs/efi-x86_payload32_defconfig
index 43e1df7..1c3724b 100644
--- a/configs/efi-x86_payload32_defconfig
+++ b/configs/efi-x86_payload32_defconfig
@@ -34,6 +34,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_PCI_PNP is not set
diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig
index a44e1e3..58a9a2e 100644
--- a/configs/efi-x86_payload64_defconfig
+++ b/configs/efi-x86_payload64_defconfig
@@ -34,6 +34,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_PCI_PNP is not set
diff --git a/configs/emsdp_defconfig b/configs/emsdp_defconfig
index 6a7893e..2b6498e 100644
--- a/configs/emsdp_defconfig
+++ b/configs/emsdp_defconfig
@@ -23,7 +23,6 @@
CONFIG_VERSION_VARIABLE=y
# CONFIG_NET is not set
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_DM_SERIAL=y
diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig
index 2849c60..10534d3 100644
--- a/configs/etamin_defconfig
+++ b/configs/etamin_defconfig
@@ -63,7 +63,6 @@
CONFIG_MTDIDS_DEFAULT="nand2=omap2-nand_concat"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand_concat:512k(spl),512k(spl.backup1),512k(spl.backup2),512k(spl.backup3),7680k(u-boot),2048k(u-boot.env0),2048k(u-boot.env1),2048k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
-# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
@@ -73,9 +72,12 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
@@ -92,7 +94,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_USB_GADGET_VENDOR_NUM=0x0908
diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig
index 9f57f34..5850241 100644
--- a/configs/ethernut5_defconfig
+++ b/configs/ethernut5_defconfig
@@ -72,4 +72,3 @@
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_USB=y
-CONFIG_USB_STORAGE=y
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 0370ef0..2d0a5ec 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -28,7 +28,6 @@
CONFIG_CLK=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_ASPEED=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ASPEED=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/evb-ast2600_defconfig b/configs/evb-ast2600_defconfig
index 003fedd..91518db 100644
--- a/configs/evb-ast2600_defconfig
+++ b/configs/evb-ast2600_defconfig
@@ -48,7 +48,6 @@
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_SPL_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ASPEED=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 75c7b66..60e3c56 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -40,6 +40,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index 899e61a..98c58b5 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -168,7 +168,6 @@
CONFIG_MPC83XX_SERDES=y
CONFIG_GDSYS_SOC=y
CONFIG_IHS_FPGA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_DM_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig
index 6840509..49c3a99 100644
--- a/configs/ge_b1x5v2_defconfig
+++ b/configs/ge_b1x5v2_defconfig
@@ -84,7 +84,6 @@
CONFIG_I2C_MUX_GPIO=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/ge_bx50v3_defconfig b/configs/ge_bx50v3_defconfig
index 9470a8d..a266ffd 100644
--- a/configs/ge_bx50v3_defconfig
+++ b/configs/ge_bx50v3_defconfig
@@ -4,8 +4,6 @@
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_OFFSET=0xC0000
-CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6Q=y
CONFIG_TARGET_GE_BX50V3=y
CONFIG_DM_GPIO=y
@@ -44,7 +42,6 @@
CONFIG_DTB_RESELECT=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
@@ -57,7 +54,6 @@
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
@@ -99,7 +95,7 @@
# CONFIG_VIDEO_BPP32 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_IPUV3=y
-CONFIG_WATCHDOG_TIMEOUT_MSECS=6000
+CONFIG_WATCHDOG_TIMEOUT_MSECS=8000
CONFIG_IMX_WATCHDOG=y
CONFIG_BCH=y
# CONFIG_EFI_LOADER is not set
diff --git a/configs/giedi_defconfig b/configs/giedi_defconfig
index ab0a70e..1c51943 100644
--- a/configs/giedi_defconfig
+++ b/configs/giedi_defconfig
@@ -76,7 +76,6 @@
CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/gose_defconfig b/configs/gose_defconfig
index 333a578..56d0808 100644
--- a/configs/gose_defconfig
+++ b/configs/gose_defconfig
@@ -65,7 +65,6 @@
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/gurnard_defconfig b/configs/gurnard_defconfig
index 7792d22..896a3b1 100644
--- a/configs/gurnard_defconfig
+++ b/configs/gurnard_defconfig
@@ -33,6 +33,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_AT91_GPIO=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
@@ -45,7 +46,6 @@
CONFIG_ATMEL_PIT_TIMER=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP32 is not set
CONFIG_CMD_DHRYSTONE=y
diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig
index d5270c5..97b39b6 100644
--- a/configs/gwventana_emmc_defconfig
+++ b/configs/gwventana_emmc_defconfig
@@ -80,7 +80,6 @@
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig
index 091bf30..ce40a4d 100644
--- a/configs/gwventana_gw5904_defconfig
+++ b/configs/gwventana_gw5904_defconfig
@@ -80,7 +80,6 @@
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig
index 0ccd3e9..a4d8595 100644
--- a/configs/gwventana_nand_defconfig
+++ b/configs/gwventana_nand_defconfig
@@ -82,7 +82,6 @@
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig
index bdc6f43..0c88486 100644
--- a/configs/helios4_defconfig
+++ b/configs/helios4_defconfig
@@ -50,7 +50,6 @@
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_I2C_EEPROM=y
CONFIG_SPL_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
index 5d65049..a6aed67 100644
--- a/configs/highbank_defconfig
+++ b/configs/highbank_defconfig
@@ -18,13 +18,11 @@
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_MISC_INIT_R=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_BOARD=y
CONFIG_ENV_IS_IN_NVRAM=y
CONFIG_ENV_ADDR=0xFFF88000
CONFIG_SCSI_AHCI=y
CONFIG_BOOTCOUNT_LIMIT=y
# CONFIG_MMC is not set
-CONFIG_SCSI=y
-CONFIG_CONS_INDEX=0
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_BOARD=y
CONFIG_CALXEDA_XGMAC=y
+CONFIG_SCSI=y
diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig
index 69eaab0..a42ac96 100644
--- a/configs/hihope_rzg2_defconfig
+++ b/configs/hihope_rzg2_defconfig
@@ -51,15 +51,12 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_RENESAS_SDHI=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_USE_4K_SECTORS=y
CONFIG_BITBANGMII=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
diff --git a/configs/hikey960_defconfig b/configs/hikey960_defconfig
index ca93d73..ca3b201 100644
--- a/configs/hikey960_defconfig
+++ b/configs/hikey960_defconfig
@@ -23,7 +23,6 @@
CONFIG_ENV_EXT4_INTERFACE="mmc"
CONFIG_ENV_EXT4_DEVICE_AND_PART="0:2"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
CONFIG_PINCTRL=y
diff --git a/configs/hikey_defconfig b/configs/hikey_defconfig
index d2bb196..222b79e 100644
--- a/configs/hikey_defconfig
+++ b/configs/hikey_defconfig
@@ -21,7 +21,6 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_PART=2
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
CONFIG_DM_ETH=y
diff --git a/configs/hsdk_4xd_defconfig b/configs/hsdk_4xd_defconfig
index 8ae05fe..b90bf7d 100644
--- a/configs/hsdk_4xd_defconfig
+++ b/configs/hsdk_4xd_defconfig
@@ -38,7 +38,6 @@
CONFIG_CLK_HSDK=y
CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MTD=y
diff --git a/configs/hsdk_defconfig b/configs/hsdk_defconfig
index aaf1270..1e51862 100644
--- a/configs/hsdk_defconfig
+++ b/configs/hsdk_defconfig
@@ -37,7 +37,6 @@
CONFIG_CLK_HSDK=y
CONFIG_HSDK_CREG_GPIO=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_MTD=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
index cfb8475..8aa7fb0 100644
--- a/configs/igep00x0_defconfig
+++ b/configs/igep00x0_defconfig
@@ -54,7 +54,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_SYS_MTDPARTS_RUNTIME=y
diff --git a/configs/imx28_xea_defconfig b/configs/imx28_xea_defconfig
index 2e1d060..135c38c 100644
--- a/configs/imx28_xea_defconfig
+++ b/configs/imx28_xea_defconfig
@@ -82,7 +82,6 @@
CONFIG_SPL_DM=y
CONFIG_DEVRES=y
CONFIG_MXS_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_MXS=y
CONFIG_MTD=y
diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig
index 36dc24d..64c20b8 100644
--- a/configs/imx6q_logic_defconfig
+++ b/configs/imx6q_logic_defconfig
@@ -19,6 +19,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_PAYLOAD="u-boot.img"
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig
new file mode 100644
index 0000000..3638243
--- /dev/null
+++ b/configs/imx7_cm_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX7=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_SYS_I2C_MXC_I2C4=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_IMX7_CM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
+CONFIG_IMX_RDC=y
+CONFIG_IMX_BOOTAUX=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7-cm"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_DEFAULT_FDT_FILE="ask"
+# CONFIG_BOARD_EARLY_INIT_F is not set
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_USB_HOST_SUPPORT=y
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_USB_SDP_SUPPORT=y
+# CONFIG_CMD_BOOTD is not set
+CONFIG_CMD_BOOTMENU=y
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_SPL=y
+CONFIG_CMD_SPL_WRITE_SIZE=0x20000
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_SDP=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_DFU_MMC=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x82000000
+CONFIG_FASTBOOT_BUF_SIZE=0x10000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_SPI_FLASH=y
+# CONFIG_SPI_FLASH_BAR is not set
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
+CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_FEC_MXC=y
+CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_PFUZE100=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+# CONFIG_FSL_QSPI_AHB_FULL_MAP is not set
+CONFIG_IMX_THERMAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_MXC_USB_OTG_HACTIVE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_DM_VIDEO=y
+CONFIG_SYS_WHITE_ON_BLACK=y
+CONFIG_SPLASH_SCREEN=y
+CONFIG_SPLASH_SCREEN_ALIGN=y
+CONFIG_VIDEO_BMP_RLE8=y
+CONFIG_BMP_16BPP=y
diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig
new file mode 100644
index 0000000..be98fa8
--- /dev/null
+++ b/configs/imx8mm-cl-iot-gate_defconfig
@@ -0,0 +1,148 @@
+CONFIG_ARM=y
+CONFIG_SPL_SYS_ICACHE_OFF=y
+CONFIG_SPL_SYS_DCACHE_OFF=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x4000
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_CL_IOT_GATE=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_BOOTEFI_SELFTEST=y
+CONFIG_CMD_NVEDIT_EFI=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_SHA1SUM=y
+CONFIG_CMD_BIND=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EFIDEBUG=y
+CONFIG_CMD_RTC=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_TPM=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_DFU_TFTP=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_UDP_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_BUF_ADDR=0x44000000
+CONFIG_FASTBOOT_BUF_SIZE=0x5000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=2
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_SUPPORT_EMMC_RPMB=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_ESDHC_IMX=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8M_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_SPL_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_BD71837=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_ABX80X=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_DM_THERMAL=y
+CONFIG_TPM2_TIS_SPI=y
+CONFIG_TPM2_FTPM_TEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_SDP_LOADADDR=0x40400000
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX88179=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_TPM=y
+CONFIG_LZO=y
+CONFIG_BZIP2=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_SECURE_BOOT=y
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
new file mode 100644
index 0000000..6053da4
--- /dev/null
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-ctouch2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
new file mode 100644
index 0000000..fadc6eb
--- /dev/null
+++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-edimm2.2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-edimm2.2.dtb"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig
index 045b19f..2248491 100644
--- a/configs/imx8mm_beacon_defconfig
+++ b/configs/imx8mm_beacon_defconfig
@@ -18,6 +18,7 @@
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-beacon-kit"
+CONFIG_LTO=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
@@ -69,7 +70,6 @@
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig
index 23741a1..200bf55 100644
--- a/configs/imx8mm_evk_defconfig
+++ b/configs/imx8mm_evk_defconfig
@@ -66,7 +66,6 @@
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig
index a15c364..07ddf37 100644
--- a/configs/imx8mm_venice_defconfig
+++ b/configs/imx8mm_venice_defconfig
@@ -21,6 +21,7 @@
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xff8000
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice"
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
@@ -75,7 +76,6 @@
CONFIG_LED=y
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_SPL_MMC_IO_VOLTAGE=y
diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig
index 58b8e49..ecd7fab 100644
--- a/configs/imx8mn_beacon_2g_defconfig
+++ b/configs/imx8mn_beacon_2g_defconfig
@@ -23,6 +23,7 @@
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
+CONFIG_LTO=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
@@ -84,7 +85,6 @@
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig
index 567a6e5..9a77f22 100644
--- a/configs/imx8mn_beacon_defconfig
+++ b/configs/imx8mn_beacon_defconfig
@@ -22,6 +22,7 @@
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-beacon-kit"
+CONFIG_LTO=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
@@ -84,7 +85,6 @@
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig
index b10cd13..a3e51ba 100644
--- a/configs/imx8mn_ddr4_evk_defconfig
+++ b/configs/imx8mn_ddr4_evk_defconfig
@@ -64,7 +64,6 @@
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig
index d0e5b58..86601eb 100644
--- a/configs/imx8mn_evk_defconfig
+++ b/configs/imx8mn_evk_defconfig
@@ -7,7 +7,6 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
-CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0x400000
CONFIG_SYS_I2C_MXC_I2C1=y
@@ -16,7 +15,6 @@
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_EVK=y
-CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
@@ -29,13 +27,14 @@
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8mn_evk/imximage-8mn-ddr4.cfg"
CONFIG_DEFAULT_FDT_FILE="imx8mn-evk.dtb"
+CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C_SUPPORT=y
-CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="u-boot=> "
# CONFIG_CMD_EXPORTENV is not set
@@ -67,7 +66,6 @@
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig
index 089ec26..11d6283 100644
--- a/configs/imx8mp_evk_defconfig
+++ b/configs/imx8mp_evk_defconfig
@@ -73,7 +73,6 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_LED=y
CONFIG_LED_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig
new file mode 100644
index 0000000..1f52f9b
--- /dev/null
+++ b/configs/imx8mq_cm_defconfig
@@ -0,0 +1,81 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MQ_CM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mq-cm"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_FIT_PRINT=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ronetix/imx8mq-cm/imximage-8mq-lpddr4.cfg"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SYS_PROMPT="u-boot=> "
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
+CONFIG_MXC_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS400_ES_SUPPORT=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_FSL_USDHC=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_PMIC=y
+CONFIG_DM_PMIC_BD71837=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_WATCHDOG=y
+CONFIG_WDT=y
diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig
index a149c1a..7116a90 100644
--- a/configs/imx8mq_evk_defconfig
+++ b/configs/imx8mq_evk_defconfig
@@ -38,7 +38,6 @@
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig
index 5fa89e9..f69b470 100644
--- a/configs/imx8mq_phanbell_defconfig
+++ b/configs/imx8mq_phanbell_defconfig
@@ -45,7 +45,6 @@
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
diff --git a/configs/imx8qm_mek_defconfig b/configs/imx8qm_mek_defconfig
index 0dc7f4b..8765c91 100644
--- a/configs/imx8qm_mek_defconfig
+++ b/configs/imx8qm_mek_defconfig
@@ -61,7 +61,6 @@
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/imx8qm_rom7720_a1_4G_defconfig b/configs/imx8qm_rom7720_a1_4G_defconfig
index b2b85d7..d363b1a 100644
--- a/configs/imx8qm_rom7720_a1_4G_defconfig
+++ b/configs/imx8qm_rom7720_a1_4G_defconfig
@@ -58,7 +58,6 @@
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
index e60eb80..5c78319 100644
--- a/configs/imx8qxp_mek_defconfig
+++ b/configs/imx8qxp_mek_defconfig
@@ -62,7 +62,6 @@
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
diff --git a/configs/imxrt1020-evk_defconfig b/configs/imxrt1020-evk_defconfig
index 9bddb69..ad408eb 100644
--- a/configs/imxrt1020-evk_defconfig
+++ b/configs/imxrt1020-evk_defconfig
@@ -50,7 +50,6 @@
# CONFIG_SPL_DM_GPIO is not set
CONFIG_MXC_GPIO=y
# CONFIG_INPUT is not set
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
index f639ea7..d03572e 100644
--- a/configs/imxrt1050-evk_defconfig
+++ b/configs/imxrt1050-evk_defconfig
@@ -53,7 +53,6 @@
# CONFIG_SPL_DM_GPIO is not set
CONFIG_MXC_GPIO=y
# CONFIG_INPUT is not set
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
CONFIG_PINCTRL=y
diff --git a/configs/iot_devkit_defconfig b/configs/iot_devkit_defconfig
index 5530440..98cdf47 100644
--- a/configs/iot_devkit_defconfig
+++ b/configs/iot_devkit_defconfig
@@ -27,7 +27,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_SNPS=y
CONFIG_DM_SERIAL=y
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 162bcc8..b204c7a 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -115,7 +115,6 @@
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index b20698f..5c51bd5 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -75,7 +75,7 @@
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
@@ -87,7 +87,6 @@
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
@@ -111,7 +110,7 @@
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_DM_RESET=y
@@ -143,3 +142,13 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_DEVICE_TI_K3=y
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index e14005c..f2a2934 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -112,7 +112,6 @@
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 7b4f0af..8a9b201 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -72,7 +72,7 @@
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+# CONFIG_CLK_TI_SCI is not set
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
@@ -87,7 +87,6 @@
CONFIG_ESM_K3=y
CONFIG_K3_AVS0=y
CONFIG_ESM_PMIC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
@@ -103,7 +102,7 @@
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+# CONFIG_TI_SCI_POWER_DOMAIN is not set
CONFIG_DM_PMIC=y
CONFIG_PMIC_TPS65941=y
CONFIG_DM_REGULATOR=y
@@ -141,3 +140,11 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_TI_POWER_DOMAIN=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_K3_DM_FW=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig
index 28bf56e..858e179 100644
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -102,7 +102,6 @@
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig
index f4faa74..cff45ff 100644
--- a/configs/j721e_hs_evm_r5_defconfig
+++ b/configs/j721e_hs_evm_r5_defconfig
@@ -83,7 +83,6 @@
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_K3_AVS0=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig
index 74d315d..0e72166 100644
--- a/configs/jetson-tk1_defconfig
+++ b/configs/jetson-tk1_defconfig
@@ -34,6 +34,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index d65f12e..74c45a3 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -34,7 +34,6 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
-# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index 9707624..6268916 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -21,7 +21,6 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
-# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index 6959074..ceb2f76 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -53,7 +53,6 @@
CONFIG_DFU_MMC=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index 7fee5f8..296afa4 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -36,11 +36,9 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_DM=y
-# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_SYS_I2C_DAVINCI=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index 4da3503..bb7d9a2 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -34,7 +34,6 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
-# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index d85e7d5..0665abd 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -21,7 +21,6 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
-# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 3c64028..99ed46e 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -34,7 +34,6 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
-# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index b364b0c..47275a2 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -20,7 +20,6 @@
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_GPIO is not set
# CONFIG_CMD_GPT is not set
-# CONFIG_CMD_MMC is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
diff --git a/configs/khadas-vim2_defconfig b/configs/khadas-vim2_defconfig
index 0aaa6c0..241da53 100644
--- a/configs/khadas-vim2_defconfig
+++ b/configs/khadas-vim2_defconfig
@@ -30,18 +30,17 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
diff --git a/configs/khadas-vim3_defconfig b/configs/khadas-vim3_defconfig
index bb41670..22951a9 100644
--- a/configs/khadas-vim3_defconfig
+++ b/configs/khadas-vim3_defconfig
@@ -20,6 +20,7 @@
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
@@ -35,18 +36,20 @@
CONFIG_BUTTON_ADC=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
@@ -88,8 +91,3 @@
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_PCI=y
-CONFIG_CMD_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_PCIE_DW_MESON=y
-CONFIG_NVME=y
diff --git a/configs/khadas-vim3l_defconfig b/configs/khadas-vim3l_defconfig
index 59541e7..a6fa432 100644
--- a/configs/khadas-vim3l_defconfig
+++ b/configs/khadas-vim3l_defconfig
@@ -20,6 +20,7 @@
CONFIG_CMD_I2C=y
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
@@ -35,18 +36,20 @@
CONFIG_BUTTON_ADC=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_MESON=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
@@ -88,8 +91,3 @@
CONFIG_BMP_24BPP=y
CONFIG_BMP_32BPP=y
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_PCI=y
-CONFIG_CMD_PCI=y
-CONFIG_DM_PCI=y
-CONFIG_PCIE_DW_MESON=y
-CONFIG_NVME=y
diff --git a/configs/khadas-vim_defconfig b/configs/khadas-vim_defconfig
index 60cdfff..53a8cbf 100644
--- a/configs/khadas-vim_defconfig
+++ b/configs/khadas-vim_defconfig
@@ -28,14 +28,13 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig
index a34bb08..0c09e2f 100644
--- a/configs/kmcent2_defconfig
+++ b/configs/kmcent2_defconfig
@@ -23,7 +23,6 @@
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_TRIMFFS=y
-# CONFIG_CMD_SATA is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_PING=y
CONFIG_CMD_ETHSW=y
@@ -43,7 +42,6 @@
CONFIG_ENV_ADDR=0xebf20000
CONFIG_ENV_ADDR_REDUND=0xebf00000
CONFIG_DM=y
-# CONFIG_FSL_SATA is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
@@ -51,7 +49,6 @@
CONFIG_SYS_I2C_FSL=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig
index 1aaa9c6..562259b 100644
--- a/configs/koelsch_defconfig
+++ b/configs/koelsch_defconfig
@@ -65,7 +65,6 @@
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/lager_defconfig b/configs/lager_defconfig
index 4a7e076..9d318e7 100644
--- a/configs/lager_defconfig
+++ b/configs/lager_defconfig
@@ -66,7 +66,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
diff --git a/configs/legoev3_defconfig b/configs/legoev3_defconfig
index 34bc72f..200d9ac 100644
--- a/configs/legoev3_defconfig
+++ b/configs/legoev3_defconfig
@@ -35,7 +35,6 @@
CONFIG_DM=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SYS_I2C_DAVINCI=y
-CONFIG_DM_MMC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=50000000
diff --git a/configs/libretech-ac_defconfig b/configs/libretech-ac_defconfig
index b383dfb..bfcd471 100644
--- a/configs/libretech-ac_defconfig
+++ b/configs/libretech-ac_defconfig
@@ -35,11 +35,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
@@ -47,7 +43,10 @@
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
diff --git a/configs/libretech-cc_defconfig b/configs/libretech-cc_defconfig
index ba59dee..11d620b 100644
--- a/configs/libretech-cc_defconfig
+++ b/configs/libretech-cc_defconfig
@@ -27,14 +27,13 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig
index 50ae3e1..48b3ffe 100644
--- a/configs/libretech-cc_v2_defconfig
+++ b/configs/libretech-cc_v2_defconfig
@@ -31,18 +31,17 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig
index 9ef6385..17ed47b 100644
--- a/configs/libretech-s905d-pc_defconfig
+++ b/configs/libretech-s905d-pc_defconfig
@@ -33,17 +33,16 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig
index a14ac20..df8be29 100644
--- a/configs/libretech-s912-pc_defconfig
+++ b/configs/libretech-s912-pc_defconfig
@@ -32,17 +32,16 @@
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
diff --git a/configs/lion-rk3368_defconfig b/configs/lion-rk3368_defconfig
index 6d6b73d..58c6f00 100644
--- a/configs/lion-rk3368_defconfig
+++ b/configs/lion-rk3368_defconfig
@@ -9,15 +9,13 @@
CONFIG_TPL_LIBCOMMON_SUPPORT=y
CONFIG_TPL_LIBGENERIC_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
-CONFIG_TARGET_LION_RK3368=y
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0xFF180000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion"
+CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion-haikou"
CONFIG_DEBUG_UART=y
-CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_LOAD_FIT=y
@@ -48,7 +46,6 @@
CONFIG_SPL_OF_CONTROL=y
CONFIG_TPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion-haikou"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent"
CONFIG_TPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig
index b258880..798a6e9 100644
--- a/configs/liteboard_defconfig
+++ b/configs/liteboard_defconfig
@@ -44,7 +44,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/ls1012a2g5rdb_qspi_defconfig b/configs/ls1012a2g5rdb_qspi_defconfig
index 6ddc973..7a188d2 100644
--- a/configs/ls1012a2g5rdb_qspi_defconfig
+++ b/configs/ls1012a2g5rdb_qspi_defconfig
@@ -41,7 +41,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012a2g5rdb_tfa_defconfig b/configs/ls1012a2g5rdb_tfa_defconfig
index 66aec34..9369046 100644
--- a/configs/ls1012a2g5rdb_tfa_defconfig
+++ b/configs/ls1012a2g5rdb_tfa_defconfig
@@ -41,7 +41,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
index 1593790..eea33d3 100644
--- a/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_qspi_SECURE_BOOT_defconfig
@@ -38,7 +38,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012afrwy_qspi_defconfig b/configs/ls1012afrwy_qspi_defconfig
index 8ad3cd8..2d0548b 100644
--- a/configs/ls1012afrwy_qspi_defconfig
+++ b/configs/ls1012afrwy_qspi_defconfig
@@ -43,7 +43,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
index ca20e37..1a8343e 100644
--- a/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012afrwy_tfa_SECURE_BOOT_defconfig
@@ -38,7 +38,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012afrwy_tfa_defconfig b/configs/ls1012afrwy_tfa_defconfig
index dff72e7..64200da 100644
--- a/configs/ls1012afrwy_tfa_defconfig
+++ b/configs/ls1012afrwy_tfa_defconfig
@@ -42,7 +42,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig
index 1771f1a..cafd0dc 100644
--- a/configs/ls1012aqds_qspi_defconfig
+++ b/configs/ls1012aqds_qspi_defconfig
@@ -54,7 +54,6 @@
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
index 214a2bb..7a0e800 100644
--- a/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012aqds_tfa_SECURE_BOOT_defconfig
@@ -42,7 +42,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012aqds_tfa_defconfig b/configs/ls1012aqds_tfa_defconfig
index fcd5319..ac03940 100644
--- a/configs/ls1012aqds_tfa_defconfig
+++ b/configs/ls1012aqds_tfa_defconfig
@@ -54,7 +54,6 @@
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
index 4d3dc20..349e4e9 100644
--- a/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_qspi_SECURE_BOOT_defconfig
@@ -42,7 +42,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig
index 79668a5..20b37ff 100644
--- a/configs/ls1012ardb_qspi_defconfig
+++ b/configs/ls1012ardb_qspi_defconfig
@@ -44,7 +44,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
index 6f66a51..c8902de 100644
--- a/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1012ardb_tfa_SECURE_BOOT_defconfig
@@ -41,7 +41,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1012ardb_tfa_defconfig b/configs/ls1012ardb_tfa_defconfig
index c52359e..c460e39 100644
--- a/configs/ls1012ardb_tfa_defconfig
+++ b/configs/ls1012ardb_tfa_defconfig
@@ -43,7 +43,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1021aiot_qspi_defconfig b/configs/ls1021aiot_qspi_defconfig
index 31209e4..01a870d 100644
--- a/configs/ls1021aiot_qspi_defconfig
+++ b/configs/ls1021aiot_qspi_defconfig
@@ -31,7 +31,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig
index e541c9c..cb65fd9 100644
--- a/configs/ls1021aiot_sdcard_defconfig
+++ b/configs/ls1021aiot_sdcard_defconfig
@@ -37,7 +37,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/ls1021aqds_ddr4_nor_defconfig b/configs/ls1021aqds_ddr4_nor_defconfig
index 8bfbac2..a02a9fd 100644
--- a/configs/ls1021aqds_ddr4_nor_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_defconfig
@@ -43,7 +43,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
index 433d3c6..d42e351 100644
--- a/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_ddr4_nor_lpuart_defconfig
@@ -44,7 +44,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig
index 6297379..93cb6bf 100644
--- a/configs/ls1021aqds_nand_defconfig
+++ b/configs/ls1021aqds_nand_defconfig
@@ -61,7 +61,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
index f145d15..d3b68b9 100644
--- a/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021aqds_nor_SECURE_BOOT_defconfig
@@ -42,7 +42,6 @@
CONFIG_SATA_CEVA=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021aqds_nor_defconfig b/configs/ls1021aqds_nor_defconfig
index e0e34e7..a67d040 100644
--- a/configs/ls1021aqds_nor_defconfig
+++ b/configs/ls1021aqds_nor_defconfig
@@ -44,7 +44,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021aqds_nor_lpuart_defconfig b/configs/ls1021aqds_nor_lpuart_defconfig
index 44d33e5..46625f1 100644
--- a/configs/ls1021aqds_nor_lpuart_defconfig
+++ b/configs/ls1021aqds_nor_lpuart_defconfig
@@ -45,7 +45,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021aqds_qspi_defconfig b/configs/ls1021aqds_qspi_defconfig
index 80d5ef8..17a7a60 100644
--- a/configs/ls1021aqds_qspi_defconfig
+++ b/configs/ls1021aqds_qspi_defconfig
@@ -45,7 +45,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig
index f4d2082..3442118 100644
--- a/configs/ls1021aqds_sdcard_ifc_defconfig
+++ b/configs/ls1021aqds_sdcard_ifc_defconfig
@@ -59,7 +59,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig
index d535ee6..c6d5c1e 100644
--- a/configs/ls1021aqds_sdcard_qspi_defconfig
+++ b/configs/ls1021aqds_sdcard_qspi_defconfig
@@ -57,7 +57,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig
index 17f7eea..5e0a51c 100644
--- a/configs/ls1021atsn_qspi_defconfig
+++ b/configs/ls1021atsn_qspi_defconfig
@@ -32,7 +32,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig
index a434530..47d8781 100644
--- a/configs/ls1021atsn_sdcard_defconfig
+++ b/configs/ls1021atsn_sdcard_defconfig
@@ -43,7 +43,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
index 4896c5b..38fe10b 100644
--- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig
@@ -36,7 +36,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig
index 1a9b3e1..e399499 100644
--- a/configs/ls1021atwr_nor_defconfig
+++ b/configs/ls1021atwr_nor_defconfig
@@ -38,7 +38,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig
index 5171c1b..22754f0 100644
--- a/configs/ls1021atwr_nor_lpuart_defconfig
+++ b/configs/ls1021atwr_nor_lpuart_defconfig
@@ -40,7 +40,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig
index 79ebf4c..f3877ed 100644
--- a/configs/ls1021atwr_qspi_defconfig
+++ b/configs/ls1021atwr_qspi_defconfig
@@ -41,7 +41,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
index d721729..11d33fd 100644
--- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
@@ -51,8 +51,10 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
+# CONFIG_SPL_DM_MMC is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig
index 430f89b..e08fa9c 100644
--- a/configs/ls1021atwr_sdcard_ifc_defconfig
+++ b/configs/ls1021atwr_sdcard_ifc_defconfig
@@ -53,7 +53,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig
index fe1caa2..80997a7 100644
--- a/configs/ls1021atwr_sdcard_qspi_defconfig
+++ b/configs/ls1021atwr_sdcard_qspi_defconfig
@@ -52,7 +52,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
index 17daef8..b576806 100644
--- a/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028aqds_tfa_SECURE_BOOT_defconfig
@@ -45,7 +45,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1028aqds_tfa_defconfig b/configs/ls1028aqds_tfa_defconfig
index cc38bd8..bcdb96d 100644
--- a/configs/ls1028aqds_tfa_defconfig
+++ b/configs/ls1028aqds_tfa_defconfig
@@ -51,7 +51,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1028aqds_tfa_lpuart_defconfig b/configs/ls1028aqds_tfa_lpuart_defconfig
index bc5f8f4..e310cfe 100644
--- a/configs/ls1028aqds_tfa_lpuart_defconfig
+++ b/configs/ls1028aqds_tfa_lpuart_defconfig
@@ -51,7 +51,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
index 794632a..34cd6fb 100644
--- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig
@@ -44,7 +44,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig
index 2ee57de..6ffc3bd 100644
--- a/configs/ls1028ardb_tfa_defconfig
+++ b/configs/ls1028ardb_tfa_defconfig
@@ -50,7 +50,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls1043aqds_defconfig b/configs/ls1043aqds_defconfig
index e55ad96..42fd350 100644
--- a/configs/ls1043aqds_defconfig
+++ b/configs/ls1043aqds_defconfig
@@ -40,7 +40,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043aqds_lpuart_defconfig b/configs/ls1043aqds_lpuart_defconfig
index 9388c24..1bafc2b 100644
--- a/configs/ls1043aqds_lpuart_defconfig
+++ b/configs/ls1043aqds_lpuart_defconfig
@@ -41,7 +41,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig
index 6440dbc..8fb23ac 100644
--- a/configs/ls1043aqds_nand_defconfig
+++ b/configs/ls1043aqds_nand_defconfig
@@ -57,7 +57,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043aqds_nor_ddr3_defconfig b/configs/ls1043aqds_nor_ddr3_defconfig
index f51d662..f87c9a7 100644
--- a/configs/ls1043aqds_nor_ddr3_defconfig
+++ b/configs/ls1043aqds_nor_ddr3_defconfig
@@ -41,7 +41,6 @@
CONFIG_FSL_CAAM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043aqds_qspi_defconfig b/configs/ls1043aqds_qspi_defconfig
index e803cdb..5de4e07 100644
--- a/configs/ls1043aqds_qspi_defconfig
+++ b/configs/ls1043aqds_qspi_defconfig
@@ -41,7 +41,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig
index bf5d1e5..6e3318b 100644
--- a/configs/ls1043aqds_sdcard_ifc_defconfig
+++ b/configs/ls1043aqds_sdcard_ifc_defconfig
@@ -57,7 +57,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig
index f9e9caf..cd20980 100644
--- a/configs/ls1043aqds_sdcard_qspi_defconfig
+++ b/configs/ls1043aqds_sdcard_qspi_defconfig
@@ -55,7 +55,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
index f1c6fb0..4caabca 100644
--- a/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043aqds_tfa_SECURE_BOOT_defconfig
@@ -39,7 +39,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043aqds_tfa_defconfig b/configs/ls1043aqds_tfa_defconfig
index 04b1cae..fb28072 100644
--- a/configs/ls1043aqds_tfa_defconfig
+++ b/configs/ls1043aqds_tfa_defconfig
@@ -48,7 +48,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig
index 2dcfd8b..5e1cfc6 100644
--- a/configs/ls1043ardb_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_SECURE_BOOT_defconfig
@@ -29,7 +29,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig
index 108d8e9..bd7b2db 100644
--- a/configs/ls1043ardb_defconfig
+++ b/configs/ls1043ardb_defconfig
@@ -32,7 +32,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
index 3ca7dac..04633bc 100644
--- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig
@@ -50,7 +50,6 @@
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
index fb53054..5c993f3 100644
--- a/configs/ls1043ardb_nand_defconfig
+++ b/configs/ls1043ardb_nand_defconfig
@@ -51,7 +51,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
index 06c1ce5..1f6087c 100644
--- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
@@ -49,7 +49,9 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_DM_I2C=y
+# CONFIG_SPL_DM_MMC is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index 87abc07..c66ec3b 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -50,7 +50,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
index 9796b84..44cbd76 100644
--- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig
@@ -31,7 +31,6 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig
index de3db3e..7e53bc4 100644
--- a/configs/ls1043ardb_tfa_defconfig
+++ b/configs/ls1043ardb_tfa_defconfig
@@ -37,7 +37,6 @@
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
index 5647fd5..f953106 100644
--- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig
@@ -32,7 +32,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig
index add3001..ea62d7f 100644
--- a/configs/ls1046afrwy_tfa_defconfig
+++ b/configs/ls1046afrwy_tfa_defconfig
@@ -38,7 +38,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1046aqds_SECURE_BOOT_defconfig b/configs/ls1046aqds_SECURE_BOOT_defconfig
index f75cca2..7e7ae34 100644
--- a/configs/ls1046aqds_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_SECURE_BOOT_defconfig
@@ -38,7 +38,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1046aqds_defconfig b/configs/ls1046aqds_defconfig
index 592916b..8905d45 100644
--- a/configs/ls1046aqds_defconfig
+++ b/configs/ls1046aqds_defconfig
@@ -41,7 +41,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1046aqds_lpuart_defconfig b/configs/ls1046aqds_lpuart_defconfig
index 38f285f..6627ac2 100644
--- a/configs/ls1046aqds_lpuart_defconfig
+++ b/configs/ls1046aqds_lpuart_defconfig
@@ -42,7 +42,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig
index 9194eff..9da564a 100644
--- a/configs/ls1046aqds_nand_defconfig
+++ b/configs/ls1046aqds_nand_defconfig
@@ -50,7 +50,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1046aqds_qspi_defconfig b/configs/ls1046aqds_qspi_defconfig
index 4753881..6cf46ff 100644
--- a/configs/ls1046aqds_qspi_defconfig
+++ b/configs/ls1046aqds_qspi_defconfig
@@ -42,7 +42,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig
index 0f2e9c0..165c272 100644
--- a/configs/ls1046aqds_sdcard_ifc_defconfig
+++ b/configs/ls1046aqds_sdcard_ifc_defconfig
@@ -59,7 +59,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig
index 0d6bea6..8e60a35 100644
--- a/configs/ls1046aqds_sdcard_qspi_defconfig
+++ b/configs/ls1046aqds_sdcard_qspi_defconfig
@@ -57,7 +57,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
# CONFIG_SPI_FLASH_BAR is not set
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
index 141857c..7e57b53 100644
--- a/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046aqds_tfa_SECURE_BOOT_defconfig
@@ -40,7 +40,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1046aqds_tfa_defconfig b/configs/ls1046aqds_tfa_defconfig
index 9d5c941..9366bc1 100644
--- a/configs/ls1046aqds_tfa_defconfig
+++ b/configs/ls1046aqds_tfa_defconfig
@@ -49,7 +49,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig
index 31b9771..68efb1b 100644
--- a/configs/ls1046ardb_emmc_defconfig
+++ b/configs/ls1046ardb_emmc_defconfig
@@ -53,7 +53,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
index 01858d0..3b43fd0 100644
--- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig
index 5bcc103..a9036dd 100644
--- a/configs/ls1046ardb_qspi_defconfig
+++ b/configs/ls1046ardb_qspi_defconfig
@@ -38,7 +38,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig
index 1b53704..a6e464b 100644
--- a/configs/ls1046ardb_qspi_spl_defconfig
+++ b/configs/ls1046ardb_qspi_spl_defconfig
@@ -57,7 +57,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
index 54f489d..3514f29 100644
--- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig
@@ -49,8 +49,10 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_DM_I2C=y
# CONFIG_SPL_DM_I2C is not set
+# CONFIG_SPL_DM_MMC is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 183cdd9..e5a8ad1 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -52,7 +52,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
index 0462567..faa08b2 100644
--- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig
@@ -34,7 +34,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig
index 2fbfa34..53f1314 100644
--- a/configs/ls1046ardb_tfa_defconfig
+++ b/configs/ls1046ardb_tfa_defconfig
@@ -40,7 +40,6 @@
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1088aqds_defconfig b/configs/ls1088aqds_defconfig
index b67901e..c0fb4c9 100644
--- a/configs/ls1088aqds_defconfig
+++ b/configs/ls1088aqds_defconfig
@@ -43,7 +43,6 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
index 52a3455..57c91c1 100644
--- a/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088aqds_qspi_SECURE_BOOT_defconfig
@@ -41,7 +41,6 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1088aqds_qspi_defconfig b/configs/ls1088aqds_qspi_defconfig
index c3af322..9abaead 100644
--- a/configs/ls1088aqds_qspi_defconfig
+++ b/configs/ls1088aqds_qspi_defconfig
@@ -44,7 +44,6 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig
index 2331e3e..44d4c13 100644
--- a/configs/ls1088aqds_sdcard_ifc_defconfig
+++ b/configs/ls1088aqds_sdcard_ifc_defconfig
@@ -54,7 +54,6 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig
index c94182b..dadea57 100644
--- a/configs/ls1088aqds_sdcard_qspi_defconfig
+++ b/configs/ls1088aqds_sdcard_qspi_defconfig
@@ -54,7 +54,6 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1088aqds_tfa_defconfig b/configs/ls1088aqds_tfa_defconfig
index cf8fb31..5229a35 100644
--- a/configs/ls1088aqds_tfa_defconfig
+++ b/configs/ls1088aqds_tfa_defconfig
@@ -57,7 +57,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
index db696f9..de37599 100644
--- a/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_qspi_SECURE_BOOT_defconfig
@@ -43,7 +43,6 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1088ardb_qspi_defconfig b/configs/ls1088ardb_qspi_defconfig
index 4bacce1..0e32aeb 100644
--- a/configs/ls1088ardb_qspi_defconfig
+++ b/configs/ls1088ardb_qspi_defconfig
@@ -46,7 +46,6 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
index 24e4ba7..7b85bf6 100644
--- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
@@ -56,6 +56,8 @@
CONFIG_DM=y
CONFIG_SPL_DM=y
CONFIG_SCSI_AHCI=y
+# CONFIG_SPL_BLK is not set
+# CONFIG_SPL_DM_MMC is not set
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig
index b38ef7b..59469d3 100644
--- a/configs/ls1088ardb_sdcard_qspi_defconfig
+++ b/configs/ls1088ardb_sdcard_qspi_defconfig
@@ -56,7 +56,6 @@
CONFIG_DM=y
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
index 4952d7c..84fbab0 100644
--- a/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls1088ardb_tfa_SECURE_BOOT_defconfig
@@ -49,7 +49,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls1088ardb_tfa_defconfig b/configs/ls1088ardb_tfa_defconfig
index 283c192..007a80c 100644
--- a/configs/ls1088ardb_tfa_defconfig
+++ b/configs/ls1088ardb_tfa_defconfig
@@ -54,7 +54,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig
index e6ff8b8..bfa697c 100644
--- a/configs/ls2080aqds_SECURE_BOOT_defconfig
+++ b/configs/ls2080aqds_SECURE_BOOT_defconfig
@@ -35,7 +35,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig
index 31d79cc..6f9cce5 100644
--- a/configs/ls2080aqds_defconfig
+++ b/configs/ls2080aqds_defconfig
@@ -38,7 +38,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig
index 2016606..cc0f2b1 100644
--- a/configs/ls2080aqds_nand_defconfig
+++ b/configs/ls2080aqds_nand_defconfig
@@ -49,7 +49,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig
index c1e49b5..cbdf733 100644
--- a/configs/ls2080aqds_qspi_defconfig
+++ b/configs/ls2080aqds_qspi_defconfig
@@ -40,7 +40,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig
index d866966..71174de 100644
--- a/configs/ls2080aqds_sdcard_defconfig
+++ b/configs/ls2080aqds_sdcard_defconfig
@@ -47,7 +47,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig
index be3b5ab..1175aaf 100644
--- a/configs/ls2080ardb_SECURE_BOOT_defconfig
+++ b/configs/ls2080ardb_SECURE_BOOT_defconfig
@@ -35,7 +35,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig
index dd77b4a..53abd06 100644
--- a/configs/ls2080ardb_defconfig
+++ b/configs/ls2080ardb_defconfig
@@ -38,7 +38,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig
index 50ac69b..93032ed 100644
--- a/configs/ls2080ardb_nand_defconfig
+++ b/configs/ls2080ardb_nand_defconfig
@@ -48,7 +48,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig
index 1bcfcde..ab1a9e2 100644
--- a/configs/ls2081ardb_defconfig
+++ b/configs/ls2081ardb_defconfig
@@ -38,7 +38,6 @@
CONFIG_SCSI_AHCI=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig
index 2929699..5620e8a 100644
--- a/configs/ls2088aqds_tfa_defconfig
+++ b/configs/ls2088aqds_tfa_defconfig
@@ -53,7 +53,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
index 41bab9b..10c139c 100644
--- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig
@@ -34,7 +34,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_SATA_CEVA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig
index 581ceb7..58fc6b2 100644
--- a/configs/ls2088ardb_qspi_defconfig
+++ b/configs/ls2088ardb_qspi_defconfig
@@ -41,7 +41,6 @@
CONFIG_DM=y
CONFIG_SATA_CEVA=y
CONFIG_FSL_CAAM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
index c5bfb18..eed26fa 100644
--- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig
@@ -44,7 +44,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig
index de57235..56cd024 100644
--- a/configs/ls2088ardb_tfa_defconfig
+++ b/configs/ls2088ardb_tfa_defconfig
@@ -51,7 +51,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
index 5a7ffe9..54d88c8 100644
--- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig
@@ -45,7 +45,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
index ed6f78b..d25d3e8 100644
--- a/configs/lx2160aqds_tfa_defconfig
+++ b/configs/lx2160aqds_tfa_defconfig
@@ -52,7 +52,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
index bb92fcb..1d61807 100644
--- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig
@@ -41,7 +41,6 @@
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
-CONFIG_DM_MMC=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig
index 1d3b59c..a160cfe 100644
--- a/configs/lx2160ardb_tfa_defconfig
+++ b/configs/lx2160ardb_tfa_defconfig
@@ -49,7 +49,6 @@
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig
index 1b06124..8b69a36 100644
--- a/configs/lx2160ardb_tfa_stmm_defconfig
+++ b/configs/lx2160ardb_tfa_stmm_defconfig
@@ -49,7 +49,6 @@
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
index 2ecd6b4..fcc78c6 100644
--- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
+++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig
@@ -47,7 +47,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig
index d0d3384..42a3a3a 100644
--- a/configs/lx2162aqds_tfa_defconfig
+++ b/configs/lx2162aqds_tfa_defconfig
@@ -54,7 +54,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig
index b926125..bf0ac38 100644
--- a/configs/lx2162aqds_tfa_verified_boot_defconfig
+++ b/configs/lx2162aqds_tfa_verified_boot_defconfig
@@ -55,7 +55,6 @@
CONFIG_I2C_DEFAULT_BUS_NUMBER=0
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC=y
diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig
index 251f1bc..0c1a307 100644
--- a/configs/m53menlo_defconfig
+++ b/configs/m53menlo_defconfig
@@ -66,7 +66,6 @@
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_BOOTCOUNT_MAGIC=0x0B01C041
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/marsboard_defconfig b/configs/marsboard_defconfig
index 551d09b..09f4a37 100644
--- a/configs/marsboard_defconfig
+++ b/configs/marsboard_defconfig
@@ -2,13 +2,13 @@
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_MX6Q=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
-CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-marsboard"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,DDR_MB=1024"
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
@@ -20,22 +20,17 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
-CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
-CONFIG_DM_GPIO=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_SST=y
@@ -44,6 +39,8 @@
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
@@ -67,4 +64,3 @@
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/mccmon6_nor_defconfig b/configs/mccmon6_nor_defconfig
index 442e603..f4a572d 100644
--- a/configs/mccmon6_nor_defconfig
+++ b/configs/mccmon6_nor_defconfig
@@ -53,7 +53,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig
index 9b4189c..fce6f4d 100644
--- a/configs/mccmon6_sd_defconfig
+++ b/configs/mccmon6_sd_defconfig
@@ -51,7 +51,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/meerkat96_defconfig b/configs/meerkat96_defconfig
index 08a9d4b..200a514 100644
--- a/configs/meerkat96_defconfig
+++ b/configs/meerkat96_defconfig
@@ -37,7 +37,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_MMC_BROKEN_CD=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PINCTRL=y
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 761cc65..245763b 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -40,6 +40,7 @@
CONFIG_CMD_JFFS2=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_DM=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 696a502..e3c3473 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -53,6 +53,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/mt7620_rfb_defconfig b/configs/mt7620_rfb_defconfig
index 9829371..3bea875 100644
--- a/configs/mt7620_rfb_defconfig
+++ b/configs/mt7620_rfb_defconfig
@@ -48,7 +48,6 @@
CONFIG_GPIO_HOG=y
# CONFIG_INPUT is not set
CONFIG_MMC=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_MTK=y
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
index c12ce5c..81a5a3b 100644
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -25,7 +25,6 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
-CONFIG_DM_MMC=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig
index 9286832..dd40d08 100644
--- a/configs/mt7623a_unielec_u7623_02_defconfig
+++ b/configs/mt7623a_unielec_u7623_02_defconfig
@@ -31,7 +31,6 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index fb20cb1..0a91752 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -32,7 +32,6 @@
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_HS400_SUPPORT=y
diff --git a/configs/mt8183_pumpkin_defconfig b/configs/mt8183_pumpkin_defconfig
index b0bdcb3..c74b812 100644
--- a/configs/mt8183_pumpkin_defconfig
+++ b/configs/mt8183_pumpkin_defconfig
@@ -54,9 +54,7 @@
CONFIG_FASTBOOT_BUF_SIZE=0x8000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_MMC_BOOT1_SUPPORT=y
# CONFIG_INPUT is not set
-CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
CONFIG_MMC_MTK=y
CONFIG_DM_ETH=y
diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig
index d8e0e86..2787f75 100644
--- a/configs/mt8512_bm1_emmc_defconfig
+++ b/configs/mt8512_bm1_emmc_defconfig
@@ -30,7 +30,6 @@
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
-CONFIG_DM_MMC=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_PHY=y
diff --git a/configs/mt8516_pumpkin_defconfig b/configs/mt8516_pumpkin_defconfig
index 5270ec2..7806600 100644
--- a/configs/mt8516_pumpkin_defconfig
+++ b/configs/mt8516_pumpkin_defconfig
@@ -55,7 +55,6 @@
CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
# CONFIG_INPUT is not set
-CONFIG_DM_MMC=y
# CONFIG_MMC_QUIRKS is not set
CONFIG_MMC_MTK=y
CONFIG_PINCTRL=y
diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig
index 2c760c1..5bf405e 100644
--- a/configs/mt8518_ap1_emmc_defconfig
+++ b/configs/mt8518_ap1_emmc_defconfig
@@ -26,7 +26,6 @@
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y
CONFIG_FASTBOOT_MMC_USER_SUPPORT=y
-CONFIG_DM_MMC=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_PINCTRL=y
diff --git a/configs/mvebu_crb_cn9130_defconfig b/configs/mvebu_crb_cn9130_defconfig
new file mode 100644
index 0000000..1afea4b
--- /dev/null
+++ b/configs/mvebu_crb_cn9130_defconfig
@@ -0,0 +1,83 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_OCTEONTX2_CN913x=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x3f0000
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEFAULT_DEVICE_TREE="cn9130-crb-A"
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="Marvell>> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_MVEBU_MMC_BOOT=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_AHCI_MVEBU=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_MMC_BROKEN_CD=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_MVPP2=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/mvebu_db-88f3720_defconfig b/configs/mvebu_db-88f3720_defconfig
index a6bbe1a..fbccc8e 100644
--- a/configs/mvebu_db-88f3720_defconfig
+++ b/configs/mvebu_db-88f3720_defconfig
@@ -6,7 +6,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_TARGET_MVEBU_ARMADA_37XX=y
CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_OFFSET=0x3f0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_DEBUG_UART_BASE=0xd0012000
@@ -46,7 +46,6 @@
# CONFIG_MVEBU_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_XENON=y
diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig
index 5d8a1b6..11d9069 100644
--- a/configs/mvebu_db_armada8k_defconfig
+++ b/configs/mvebu_db_armada8k_defconfig
@@ -6,7 +6,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_MVEBU_ARMADA_8K=y
CONFIG_ENV_SIZE=0x10000
-CONFIG_ENV_OFFSET=0x180000
+CONFIG_ENV_OFFSET=0x3f0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DEBUG_UART_BASE=0xf0512000
CONFIG_DEBUG_UART_CLOCK=200000000
@@ -41,7 +41,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mvebu_db_cn9130_defconfig b/configs/mvebu_db_cn9130_defconfig
new file mode 100644
index 0000000..2d8e8ef
--- /dev/null
+++ b/configs/mvebu_db_cn9130_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_TARGET_OCTEONTX2_CN913x=y
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x3f0000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEBUG_UART_BASE=0xf0512000
+CONFIG_DEBUG_UART_CLOCK=200000000
+CONFIG_DEFAULT_DEVICE_TREE="cn9130-db-A"
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_ARCH_EARLY_INIT_R=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_SYS_PROMPT="Marvell>> "
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_MVEBU_BUBT=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_MAC_PARTITION=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=1
+CONFIG_AHCI_MVEBU=y
+CONFIG_DM_GPIO_LOOKUP_LABEL=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MVTWSI=y
+CONFIG_MISC=y
+CONFIG_MMC_BROKEN_CD=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_XENON=y
+CONFIG_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_SYS_NAND_USE_FLASH_BBT=y
+CONFIG_NAND_PXA3XX=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_GIGE=y
+CONFIG_MVPP2=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCIE_DW_MVEBU=y
+CONFIG_MVEBU_COMPHY_SUPPORT=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_ARMADA_8K=y
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_SYS_NS16550=y
+CONFIG_KIRKWOOD_SPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_HOST_ETHER=y
+CONFIG_USB_ETHER_ASIX=y
+CONFIG_USB_ETHER_MCS7830=y
+CONFIG_USB_ETHER_RTL8152=y
+CONFIG_USB_ETHER_SMSC95XX=y
diff --git a/configs/mvebu_espressobin-88f3720_defconfig b/configs/mvebu_espressobin-88f3720_defconfig
index dd586c3..95a48b1 100644
--- a/configs/mvebu_espressobin-88f3720_defconfig
+++ b/configs/mvebu_espressobin-88f3720_defconfig
@@ -51,7 +51,6 @@
CONFIG_CLK_MVEBU=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_XENON=y
diff --git a/configs/mvebu_mcbin-88f8040_defconfig b/configs/mvebu_mcbin-88f8040_defconfig
index c5cb8bc..e9077c7 100644
--- a/configs/mvebu_mcbin-88f8040_defconfig
+++ b/configs/mvebu_mcbin-88f8040_defconfig
@@ -45,7 +45,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mvebu_puzzle-m801-88f8040_defconfig b/configs/mvebu_puzzle-m801-88f8040_defconfig
index 0778149..652ea64 100644
--- a/configs/mvebu_puzzle-m801-88f8040_defconfig
+++ b/configs/mvebu_puzzle-m801-88f8040_defconfig
@@ -51,7 +51,6 @@
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_XENON=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx23_olinuxino_defconfig b/configs/mx23_olinuxino_defconfig
index 680611c..0129381 100644
--- a/configs/mx23_olinuxino_defconfig
+++ b/configs/mx23_olinuxino_defconfig
@@ -41,7 +41,6 @@
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
CONFIG_LED_STATUS_CMD=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MXS=y
CONFIG_CONS_INDEX=0
CONFIG_USB=y
diff --git a/configs/mx23evk_defconfig b/configs/mx23evk_defconfig
index 99881f3..086d2bf 100644
--- a/configs/mx23evk_defconfig
+++ b/configs/mx23evk_defconfig
@@ -35,7 +35,6 @@
# CONFIG_NET is not set
CONFIG_DM=y
CONFIG_MXS_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MXS=y
CONFIG_PINCTRL=y
CONFIG_DM_REGULATOR=y
diff --git a/configs/mx28evk_auart_console_defconfig b/configs/mx28evk_auart_console_defconfig
index ec4fd65..4fc7648 100644
--- a/configs/mx28evk_auart_console_defconfig
+++ b/configs/mx28evk_auart_console_defconfig
@@ -12,7 +12,6 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE"
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
@@ -27,7 +26,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT4=y
@@ -56,8 +54,5 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_VIDEO=y
CONFIG_SPLASH_SCREEN=y
-CONFIG_VIDEO_BMP_GZIP=y
-CONFIG_VIDEO_BMP_RLE8=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_defconfig b/configs/mx28evk_defconfig
index 4f0ed83..ff1d0ed 100644
--- a/configs/mx28evk_defconfig
+++ b/configs/mx28evk_defconfig
@@ -12,7 +12,6 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_FIT=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
@@ -27,7 +26,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT4=y
@@ -56,8 +54,5 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_VIDEO=y
CONFIG_SPLASH_SCREEN=y
-CONFIG_VIDEO_BMP_GZIP=y
-CONFIG_VIDEO_BMP_RLE8=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_nand_defconfig b/configs/mx28evk_nand_defconfig
index 7d95b8f..94e4244 100644
--- a/configs/mx28evk_nand_defconfig
+++ b/configs/mx28evk_nand_defconfig
@@ -12,7 +12,6 @@
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x380000
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
@@ -27,7 +26,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT4=y
@@ -57,8 +55,5 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_VIDEO=y
CONFIG_SPLASH_SCREEN=y
-CONFIG_VIDEO_BMP_GZIP=y
-CONFIG_VIDEO_BMP_RLE8=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx28evk_spi_defconfig b/configs/mx28evk_spi_defconfig
index e969d50..2122bbe 100644
--- a/configs/mx28evk_spi_defconfig
+++ b/configs/mx28evk_spi_defconfig
@@ -10,7 +10,6 @@
CONFIG_TARGET_MX28EVK=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
@@ -25,7 +24,6 @@
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_DATE=y
CONFIG_CMD_EXT4=y
@@ -53,8 +51,5 @@
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_VIDEO=y
CONFIG_SPLASH_SCREEN=y
-CONFIG_VIDEO_BMP_GZIP=y
-CONFIG_VIDEO_BMP_RLE8=y
CONFIG_OF_LIBFDT=y
diff --git a/configs/mx51evk_defconfig b/configs/mx51evk_defconfig
index 557a1b5..c5843c5 100644
--- a/configs/mx51evk_defconfig
+++ b/configs/mx51evk_defconfig
@@ -31,7 +31,6 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
diff --git a/configs/mx53cx9020_defconfig b/configs/mx53cx9020_defconfig
index 6810780..883abee 100644
--- a/configs/mx53cx9020_defconfig
+++ b/configs/mx53cx9020_defconfig
@@ -21,7 +21,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_FPGA_ALTERA=y
CONFIG_FPGA_CYCLON2=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
diff --git a/configs/mx53loco_defconfig b/configs/mx53loco_defconfig
index 2828889..799ffd8 100644
--- a/configs/mx53loco_defconfig
+++ b/configs/mx53loco_defconfig
@@ -32,7 +32,6 @@
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
diff --git a/configs/mx53ppd_defconfig b/configs/mx53ppd_defconfig
index be06759..ceea322 100644
--- a/configs/mx53ppd_defconfig
+++ b/configs/mx53ppd_defconfig
@@ -4,7 +4,6 @@
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2800
-CONFIG_ENV_OFFSET=0xC0000
CONFIG_TARGET_MX53PPD=y
CONFIG_DM_GPIO=y
CONFIG_BOOTCOUNT_BOOTLIMIT=10
@@ -38,7 +37,6 @@
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
@@ -50,7 +48,6 @@
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig
index a373d52..3c90ab0 100644
--- a/configs/mx6cuboxi_defconfig
+++ b/configs/mx6cuboxi_defconfig
@@ -52,7 +52,6 @@
CONFIG_SPL_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DWC_AHSATA=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig
index c1f8085..3e66b33 100644
--- a/configs/mx6qsabrelite_defconfig
+++ b/configs/mx6qsabrelite_defconfig
@@ -48,7 +48,6 @@
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig
index 4f4e7ac..56283a1 100644
--- a/configs/mx6sabreauto_defconfig
+++ b/configs/mx6sabreauto_defconfig
@@ -68,7 +68,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
CONFIG_DFU_SF=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
index e527533..ba44543 100644
--- a/configs/mx6sabresd_defconfig
+++ b/configs/mx6sabresd_defconfig
@@ -77,7 +77,6 @@
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/mx6slevk_defconfig b/configs/mx6slevk_defconfig
index 5fd78c3..2abf48c 100644
--- a/configs/mx6slevk_defconfig
+++ b/configs/mx6slevk_defconfig
@@ -38,7 +38,6 @@
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6slevk_spinor_defconfig b/configs/mx6slevk_spinor_defconfig
index 9777166..a44a745 100644
--- a/configs/mx6slevk_spinor_defconfig
+++ b/configs/mx6slevk_spinor_defconfig
@@ -38,7 +38,6 @@
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig
index 4e44bc2..dac3bd7 100644
--- a/configs/mx6slevk_spl_defconfig
+++ b/configs/mx6slevk_spl_defconfig
@@ -47,7 +47,6 @@
CONFIG_DM=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6sllevk_defconfig b/configs/mx6sllevk_defconfig
index 1e446a3..d9606ca 100644
--- a/configs/mx6sllevk_defconfig
+++ b/configs/mx6sllevk_defconfig
@@ -36,7 +36,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PINCTRL=y
diff --git a/configs/mx6sllevk_plugin_defconfig b/configs/mx6sllevk_plugin_defconfig
index 3e0e100..3a4c2ba 100644
--- a/configs/mx6sllevk_plugin_defconfig
+++ b/configs/mx6sllevk_plugin_defconfig
@@ -37,7 +37,6 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PINCTRL=y
diff --git a/configs/mx6sxsabreauto_defconfig b/configs/mx6sxsabreauto_defconfig
index 0d8c07b..f4278c3 100644
--- a/configs/mx6sxsabreauto_defconfig
+++ b/configs/mx6sxsabreauto_defconfig
@@ -37,7 +37,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig
index af5acc1..ceccb6b 100644
--- a/configs/mx6sxsabresd_defconfig
+++ b/configs/mx6sxsabresd_defconfig
@@ -40,7 +40,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig
index f4a3a4a..a4fa393 100644
--- a/configs/mx6ul_14x14_evk_defconfig
+++ b/configs/mx6ul_14x14_evk_defconfig
@@ -57,7 +57,6 @@
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig
index 28a0806..02467c0 100644
--- a/configs/mx6ul_9x9_evk_defconfig
+++ b/configs/mx6ul_9x9_evk_defconfig
@@ -50,7 +50,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6ull_14x14_evk_defconfig b/configs/mx6ull_14x14_evk_defconfig
index 2696bd8..24e18c1 100644
--- a/configs/mx6ull_14x14_evk_defconfig
+++ b/configs/mx6ull_14x14_evk_defconfig
@@ -36,7 +36,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6ull_14x14_evk_plugin_defconfig b/configs/mx6ull_14x14_evk_plugin_defconfig
index 2e08c99..7ac7a2e 100644
--- a/configs/mx6ull_14x14_evk_plugin_defconfig
+++ b/configs/mx6ull_14x14_evk_plugin_defconfig
@@ -37,7 +37,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx6ulz_14x14_evk_defconfig b/configs/mx6ulz_14x14_evk_defconfig
index 7180120..23c8210 100644
--- a/configs/mx6ulz_14x14_evk_defconfig
+++ b/configs/mx6ulz_14x14_evk_defconfig
@@ -35,7 +35,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 3687a65..be4d7c8 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -44,7 +44,6 @@
CONFIG_DFU_RAM=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/mx7dsabresd_qspi_defconfig b/configs/mx7dsabresd_qspi_defconfig
index c216b8c..574a8b5 100644
--- a/configs/mx7dsabresd_qspi_defconfig
+++ b/configs/mx7dsabresd_qspi_defconfig
@@ -44,7 +44,6 @@
CONFIG_DFU_RAM=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/mx7ulp_com_defconfig b/configs/mx7ulp_com_defconfig
index 5b910d1..b490f9c 100644
--- a/configs/mx7ulp_com_defconfig
+++ b/configs/mx7ulp_com_defconfig
@@ -31,7 +31,6 @@
# CONFIG_MXC_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index e918634..b302440 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -32,7 +32,6 @@
# CONFIG_MXC_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index 8a80f89..f2bbad9 100644
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -30,7 +30,6 @@
# CONFIG_MXC_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/nanopi-k2_defconfig b/configs/nanopi-k2_defconfig
index 4332271..ccdb1de 100644
--- a/configs/nanopi-k2_defconfig
+++ b/configs/nanopi-k2_defconfig
@@ -25,7 +25,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
diff --git a/configs/nanopi-r4s-rk3399_defconfig b/configs/nanopi-r4s-rk3399_defconfig
index 0a3c28b..506f828 100644
--- a/configs/nanopi-r4s-rk3399_defconfig
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -1,12 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_TEXT_BASE=0x00200000
+CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_OFFSET=0x3F8000
CONFIG_ROCKCHIP_RK3399=y
CONFIG_TARGET_EVB_RK3399=y
-CONFIG_NR_DRAM_BANKS=1
CONFIG_DEBUG_UART_BASE=0xFF1A0000
CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
CONFIG_DEBUG_UART=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-r4s.dtb"
CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -21,7 +22,6 @@
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_TIME=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-r4s"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
diff --git a/configs/nitrogen6dl2g_defconfig b/configs/nitrogen6dl2g_defconfig
index 8817023..121bc09 100644
--- a/configs/nitrogen6dl2g_defconfig
+++ b/configs/nitrogen6dl2g_defconfig
@@ -51,7 +51,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/nitrogen6dl_defconfig b/configs/nitrogen6dl_defconfig
index bb07ece..b655e32 100644
--- a/configs/nitrogen6dl_defconfig
+++ b/configs/nitrogen6dl_defconfig
@@ -51,7 +51,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/nitrogen6q2g_defconfig b/configs/nitrogen6q2g_defconfig
index 0308db1..4d78df3 100644
--- a/configs/nitrogen6q2g_defconfig
+++ b/configs/nitrogen6q2g_defconfig
@@ -53,7 +53,6 @@
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/nitrogen6q_defconfig b/configs/nitrogen6q_defconfig
index 2dfdb9e..0c49721 100644
--- a/configs/nitrogen6q_defconfig
+++ b/configs/nitrogen6q_defconfig
@@ -53,7 +53,6 @@
CONFIG_DWC_AHSATA=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/nitrogen6s1g_defconfig b/configs/nitrogen6s1g_defconfig
index f30fbc5..7d865de 100644
--- a/configs/nitrogen6s1g_defconfig
+++ b/configs/nitrogen6s1g_defconfig
@@ -51,7 +51,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/nitrogen6s_defconfig b/configs/nitrogen6s_defconfig
index 3d85566..c47fb5e 100644
--- a/configs/nitrogen6s_defconfig
+++ b/configs/nitrogen6s_defconfig
@@ -51,7 +51,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 312ca3a..061f5c3 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -5,6 +5,7 @@
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_NOKIA_RX51=y
CONFIG_OPTIMIZE_INLINING=y
+CONFIG_LTO=y
# CONFIG_SYS_MALLOC_F is not set
# CONFIG_FIT is not set
CONFIG_BOOTDELAY=30
@@ -52,7 +53,6 @@
# CONFIG_DM_SEQ_ALIAS is not set
# CONFIG_BLOCK_CACHE is not set
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
# CONFIG_MMC_VERBOSE is not set
CONFIG_MMC_OMAP_HS=y
@@ -67,4 +67,6 @@
CONFIG_CFB_CONSOLE_ANSI=y
# CONFIG_VGA_AS_SINGLE_DEVICE is not set
CONFIG_SPLASH_SCREEN=y
+CONFIG_WATCHDOG_TIMEOUT_MSECS=31000
+CONFIG_WDT=y
# CONFIG_GZIP is not set
diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig
index 3a47c5a..349f918 100644
--- a/configs/nyan-big_defconfig
+++ b/configs/nyan-big_defconfig
@@ -51,6 +51,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_CROS_EC_KEYB=y
CONFIG_CROS_EC=y
diff --git a/configs/octeon_ebb7304_defconfig b/configs/octeon_ebb7304_defconfig
index f614e95..bf34ac8 100644
--- a/configs/octeon_ebb7304_defconfig
+++ b/configs/octeon_ebb7304_defconfig
@@ -3,7 +3,7 @@
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_ENV_SECT_SIZE=0x2000
CONFIG_DEBUG_UART_BASE=0x8001180000000800
CONFIG_DEBUG_UART_CLOCK=1200000000
CONFIG_ARCH_OCTEON=y
@@ -33,12 +33,11 @@
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0x1FBFE000
+CONFIG_ENV_ADDR=0x800000001FBFE000
CONFIG_CLK=y
# CONFIG_INPUT is not set
CONFIG_MISC=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
@@ -47,6 +46,7 @@
CONFIG_CFI_FLASH=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_ATMEL=y
diff --git a/configs/octeon_nic23_defconfig b/configs/octeon_nic23_defconfig
index f36af43..2dd160a 100644
--- a/configs/octeon_nic23_defconfig
+++ b/configs/octeon_nic23_defconfig
@@ -41,7 +41,6 @@
# CONFIG_INPUT is not set
CONFIG_MISC=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig
index 3f80bf4..2579191 100644
--- a/configs/octeontx2_95xx_defconfig
+++ b/configs/octeontx2_95xx_defconfig
@@ -72,9 +72,9 @@
CONFIG_ENV_SPI_MODE=0x0
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig
index 0a8888a..a1d4ecd 100644
--- a/configs/octeontx2_96xx_defconfig
+++ b/configs/octeontx2_96xx_defconfig
@@ -73,6 +73,7 @@
CONFIG_ENV_SPI_MODE=0x0
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
@@ -80,7 +81,6 @@
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig
index bcf03db..72394a7 100644
--- a/configs/octeontx_81xx_defconfig
+++ b/configs/octeontx_81xx_defconfig
@@ -75,11 +75,11 @@
CONFIG_ENV_SPI_MODE=0x0
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig
index 1fc7f0c..a82c405 100644
--- a/configs/octeontx_83xx_defconfig
+++ b/configs/octeontx_83xx_defconfig
@@ -72,11 +72,11 @@
CONFIG_ENV_SPI_MODE=0x0
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_SCSI_AHCI=y
CONFIG_AHCI_PCI=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OCTEONTX=y
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig
index 7ce65b1..8c489ef 100644
--- a/configs/odroid-c2_defconfig
+++ b/configs/odroid-c2_defconfig
@@ -28,7 +28,6 @@
CONFIG_SARADC_MESON=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
diff --git a/configs/odroid-c4_defconfig b/configs/odroid-c4_defconfig
index 48fb891..7b21c12 100644
--- a/configs/odroid-c4_defconfig
+++ b/configs/odroid-c4_defconfig
@@ -28,14 +28,13 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
diff --git a/configs/odroid-n2_defconfig b/configs/odroid-n2_defconfig
index d2a8c34..8a12148 100644
--- a/configs/odroid-n2_defconfig
+++ b/configs/odroid-n2_defconfig
@@ -28,14 +28,13 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_ADC=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
diff --git a/configs/odroid-xu3_defconfig b/configs/odroid-xu3_defconfig
index 755a2ca..bc71b45 100644
--- a/configs/odroid-xu3_defconfig
+++ b/configs/odroid-xu3_defconfig
@@ -41,6 +41,7 @@
CONFIG_ADC_EXYNOS=y
CONFIG_DFU_MMC=y
CONFIG_SET_DFU_ALT_INFO=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig
index 9f2b0b2..36719d9 100644
--- a/configs/odroid_defconfig
+++ b/configs/odroid_defconfig
@@ -42,6 +42,7 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
CONFIG_SET_DFU_ALT_INFO=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_SYS_I2C_S3C24X0=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig
index fa751e3..681a955 100644
--- a/configs/omap35_logic_defconfig
+++ b/configs/omap35_logic_defconfig
@@ -19,7 +19,6 @@
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-torpedo-35xx-devkit.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
@@ -54,7 +53,6 @@
CONFIG_SPL_DM=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig
index a8eab40..64fe9da 100644
--- a/configs/omap35_logic_somlv_defconfig
+++ b/configs/omap35_logic_somlv_defconfig
@@ -19,7 +19,6 @@
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-35xx-devkit.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
@@ -53,7 +52,6 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig
index 514bc01..83122af 100644
--- a/configs/omap3_beagle_defconfig
+++ b/configs/omap3_beagle_defconfig
@@ -69,7 +69,6 @@
CONFIG_LED_STATUS_GREEN=2
CONFIG_LED_STATUS_CMD=y
CONFIG_TWL4030_LED=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig
index 50d7020..7a26351 100644
--- a/configs/omap3_evm_defconfig
+++ b/configs/omap3_evm_defconfig
@@ -56,7 +56,6 @@
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_GPIO_HOG=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig
index 5414880..84f989d 100644
--- a/configs/omap3_logic_defconfig
+++ b/configs/omap3_logic_defconfig
@@ -12,13 +12,13 @@
# CONFIG_SPL_OMAP3_ID_NAND is not set
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="logicpd-torpedo-37xx-devkit"
+CONFIG_LTO=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
@@ -52,7 +52,6 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP36XX_PINS=y
CONFIG_MTD=y
diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig
index 3edd6d1..c825d0d 100644
--- a/configs/omap3_logic_somlv_defconfig
+++ b/configs/omap3_logic_somlv_defconfig
@@ -19,7 +19,6 @@
CONFIG_PREBOOT="setenv preboot;saveenv;"
CONFIG_DEFAULT_FDT_FILE="logicpd-som-lv-37xx-devkit.dtb"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_ALLOC_BD=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
@@ -53,7 +52,6 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_OMAP36XX_PINS=y
CONFIG_MTD=y
diff --git a/configs/omap4_panda_defconfig b/configs/omap4_panda_defconfig
index b86cfc1..60a451b 100644
--- a/configs/omap4_panda_defconfig
+++ b/configs/omap4_panda_defconfig
@@ -32,7 +32,6 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_ETH=y
CONFIG_CONS_INDEX=3
diff --git a/configs/omap4_sdp4430_defconfig b/configs/omap4_sdp4430_defconfig
index e6103c3..3592cfd 100644
--- a/configs/omap4_sdp4430_defconfig
+++ b/configs/omap4_sdp4430_defconfig
@@ -33,7 +33,6 @@
CONFIG_SYS_MMC_ENV_DEV=1
CONFIG_VERSION_VARIABLE=y
CONFIG_DM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_ETH=y
CONFIG_CONS_INDEX=3
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
index d370c40..a23058b 100644
--- a/configs/omap5_uevm_defconfig
+++ b/configs/omap5_uevm_defconfig
@@ -39,7 +39,6 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_CMD_TCA642X=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_DM_ETH=y
diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig
index 994d13b..6274f31 100644
--- a/configs/omapl138_lcdk_defconfig
+++ b/configs/omapl138_lcdk_defconfig
@@ -56,7 +56,6 @@
CONFIG_DA8XX_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DAVINCI=y
-CONFIG_DM_MMC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/openrd_base_defconfig b/configs/openrd_base_defconfig
index ebe22ab..3d83b2e 100644
--- a/configs/openrd_base_defconfig
+++ b/configs/openrd_base_defconfig
@@ -37,7 +37,6 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
-CONFIG_MVSATA_IDE=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/openrd_client_defconfig b/configs/openrd_client_defconfig
index 04fcea2..4e943b3 100644
--- a/configs/openrd_client_defconfig
+++ b/configs/openrd_client_defconfig
@@ -37,7 +37,6 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
-CONFIG_MVSATA_IDE=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/openrd_ultimate_defconfig b/configs/openrd_ultimate_defconfig
index de7526d..8c77f2a 100644
--- a/configs/openrd_ultimate_defconfig
+++ b/configs/openrd_ultimate_defconfig
@@ -37,7 +37,6 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NETCONSOLE=y
-CONFIG_MVSATA_IDE=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/origen_defconfig b/configs/origen_defconfig
index 4c4dc1a..650276e 100644
--- a/configs/origen_defconfig
+++ b/configs/origen_defconfig
@@ -31,6 +31,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
diff --git a/configs/p200_defconfig b/configs/p200_defconfig
index c61e974..0c85cdc 100644
--- a/configs/p200_defconfig
+++ b/configs/p200_defconfig
@@ -25,7 +25,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
diff --git a/configs/p201_defconfig b/configs/p201_defconfig
index 34dc154..f4b9a1a 100644
--- a/configs/p201_defconfig
+++ b/configs/p201_defconfig
@@ -26,7 +26,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
diff --git a/configs/p212_defconfig b/configs/p212_defconfig
index c36a674..51b8432 100644
--- a/configs/p212_defconfig
+++ b/configs/p212_defconfig
@@ -25,14 +25,13 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_MESON_GXL=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig
index 16f6b68..97232bb 100644
--- a/configs/p2371-0000_defconfig
+++ b/configs/p2371-0000_defconfig
@@ -5,7 +5,6 @@
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFE000
CONFIG_TEGRA210=y
-CONFIG_TARGET_P2371_0000=y
CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2371-0000"
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_CONSOLE_MUX=y
@@ -29,6 +28,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig
index c7f4404..af49089 100644
--- a/configs/p2371-2180_defconfig
+++ b/configs/p2371-2180_defconfig
@@ -32,6 +32,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig
index 9730340..68bfb8f 100644
--- a/configs/p2571_defconfig
+++ b/configs/p2571_defconfig
@@ -29,6 +29,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig
index 6e6a813..12c3f9b 100644
--- a/configs/p3450-0000_defconfig
+++ b/configs/p3450-0000_defconfig
@@ -33,6 +33,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/pcm052_defconfig b/configs/pcm052_defconfig
index 196bfc5..32f08a1 100644
--- a/configs/pcm052_defconfig
+++ b/configs/pcm052_defconfig
@@ -46,7 +46,6 @@
CONFIG_SYS_EEPROM_SIZE=32768
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=6
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig
index 49b895f..b027894 100644
--- a/configs/pcm058_defconfig
+++ b/configs/pcm058_defconfig
@@ -61,7 +61,6 @@
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig
index 7d1a28a..a61b826 100644
--- a/configs/pg_wcom_seli8_defconfig
+++ b/configs/pg_wcom_seli8_defconfig
@@ -9,6 +9,9 @@
CONFIG_SYS_MEMTEST_END=0x9fffffff
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
+CONFIG_SYS_I2C_MXC_I2C1=y
+CONFIG_SYS_I2C_MXC_I2C2=y
+CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SYS_BOOTCOUNT_ADDR=0x70000020
CONFIG_DEFAULT_DEVICE_TREE="ls1021a-pg-wcom-seli8"
@@ -22,8 +25,8 @@
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0"
CONFIG_SILENT_CONSOLE=y
-CONFIG_MISC_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
+CONFIG_MISC_INIT_R=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMINFO=y
@@ -38,19 +41,16 @@
CONFIG_MTDPARTS_DEFAULT="mtdparts=60000000.nor:128k(rcw),128k(qe),128k(envred),128k(env),512k(res),1m(u-boot),-(ubi0);68000000.flash:-(ubi1)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
-CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0x60060000
CONFIG_ENV_ADDR_REDUND=0x60040000
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SYS_FSL_DDR3=y
-# CONFIG_MMC is not set
CONFIG_SYS_I2C_MXC=y
-CONFIG_SYS_I2C_MXC_I2C1=y
-CONFIG_SYS_I2C_MXC_I2C2=y
-CONFIG_SYS_I2C_MXC_I2C3=y
+# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig
index 6d40497..8b3ad9d 100644
--- a/configs/phycore-am335x-r2-regor_defconfig
+++ b/configs/phycore-am335x-r2-regor_defconfig
@@ -62,7 +62,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig
index 882c954..cbf3b9f 100644
--- a/configs/phycore-am335x-r2-wega_defconfig
+++ b/configs/phycore-am335x-r2-wega_defconfig
@@ -62,7 +62,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig
index 86772f4..549a51d 100644
--- a/configs/phycore-imx8mm_defconfig
+++ b/configs/phycore-imx8mm_defconfig
@@ -75,7 +75,6 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig
index d09841a..f905c01 100644
--- a/configs/phycore-imx8mp_defconfig
+++ b/configs/phycore-imx8mp_defconfig
@@ -73,7 +73,6 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig
index cb363a7..b31209b 100644
--- a/configs/pic32mzdask_defconfig
+++ b/configs/pic32mzdask_defconfig
@@ -29,7 +29,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_CLK=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PIC32=y
CONFIG_PHY_SMSC=y
diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig
index de09847..3f3c4ef 100644
--- a/configs/pico-dwarf-imx6ul_defconfig
+++ b/configs/pico-dwarf-imx6ul_defconfig
@@ -43,13 +43,13 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
@@ -69,7 +69,5 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_VIDEO=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig
index dbfa2e0..589811a 100644
--- a/configs/pico-dwarf-imx7d_defconfig
+++ b/configs/pico-dwarf-imx7d_defconfig
@@ -53,7 +53,6 @@
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig
index e452f9c..88fdfec 100644
--- a/configs/pico-hobbit-imx6ul_defconfig
+++ b/configs/pico-hobbit-imx6ul_defconfig
@@ -44,13 +44,13 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
@@ -72,7 +72,5 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_VIDEO=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig
index f33a725..bb0f93f 100644
--- a/configs/pico-hobbit-imx7d_defconfig
+++ b/configs/pico-hobbit-imx7d_defconfig
@@ -53,7 +53,6 @@
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig
index b08fa5f..f010981 100644
--- a/configs/pico-imx6_defconfig
+++ b/configs/pico-imx6_defconfig
@@ -58,12 +58,12 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x12000000
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig
index 9cc5014..a54b22f 100644
--- a/configs/pico-imx6ul_defconfig
+++ b/configs/pico-imx6ul_defconfig
@@ -47,13 +47,13 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig
index 947dfcb..7265ec0 100644
--- a/configs/pico-imx7d_bl33_defconfig
+++ b/configs/pico-imx7d_bl33_defconfig
@@ -48,7 +48,6 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_PHYLIB=y
diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig
index cc49e6f..673e822 100644
--- a/configs/pico-imx7d_defconfig
+++ b/configs/pico-imx7d_defconfig
@@ -53,7 +53,6 @@
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig
index e2e3a15..61275e2 100644
--- a/configs/pico-imx8mq_defconfig
+++ b/configs/pico-imx8mq_defconfig
@@ -43,7 +43,6 @@
CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_DM_ETH=y
diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig
index dbfa2e0..589811a 100644
--- a/configs/pico-nymph-imx7d_defconfig
+++ b/configs/pico-nymph-imx7d_defconfig
@@ -53,7 +53,6 @@
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig
index d93f342..06fa449 100644
--- a/configs/pico-pi-imx6ul_defconfig
+++ b/configs/pico-pi-imx6ul_defconfig
@@ -44,13 +44,13 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
@@ -72,7 +72,5 @@
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
-CONFIG_VIDEO=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig
index ab630ca..345de8c 100644
--- a/configs/pico-pi-imx7d_defconfig
+++ b/configs/pico-pi-imx7d_defconfig
@@ -53,7 +53,6 @@
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig
index 8169bad..e031550 100644
--- a/configs/pm9g45_defconfig
+++ b/configs/pm9g45_defconfig
@@ -41,7 +41,6 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig
index 9ebfbdf..f0af88f 100644
--- a/configs/poplar_defconfig
+++ b/configs/poplar_defconfig
@@ -20,7 +20,6 @@
CONFIG_FASTBOOT_BUF_SIZE=0x10000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_K3=y
CONFIG_DM_ETH=y
diff --git a/configs/porter_defconfig b/configs/porter_defconfig
index 8463338..3d4037a 100644
--- a/configs/porter_defconfig
+++ b/configs/porter_defconfig
@@ -65,7 +65,6 @@
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig
index a547398..8c21890 100644
--- a/configs/pxm2_defconfig
+++ b/configs/pxm2_defconfig
@@ -27,7 +27,6 @@
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_USE_PREBOOT=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
@@ -55,7 +54,6 @@
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@@ -72,9 +70,12 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
@@ -92,7 +93,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_USB_GADGET_VENDOR_NUM=0x0908
@@ -100,10 +100,5 @@
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00"
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_SYS_CONSOLE_BG_COL=0xff
-CONFIG_SYS_CONSOLE_FG_COL=0x00
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
index 18dfe33..f30bd5f 100644
--- a/configs/qemu-riscv32_spl_defconfig
+++ b/configs/qemu-riscv32_spl_defconfig
@@ -2,6 +2,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
index 897adf6..ee91ece 100644
--- a/configs/qemu-riscv64_spl_defconfig
+++ b/configs/qemu-riscv64_spl_defconfig
@@ -2,6 +2,7 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
diff --git a/configs/qemu-x86_64_defconfig b/configs/qemu-x86_64_defconfig
index 4815d8a..6e42fb7 100644
--- a/configs/qemu-x86_64_defconfig
+++ b/configs/qemu-x86_64_defconfig
@@ -52,6 +52,7 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index 218026b..6be7ce0 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -35,6 +35,7 @@
CONFIG_MAC_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig
deleted file mode 100644
index 30d42ef..0000000
--- a/configs/qemu_mips64_defconfig
+++ /dev/null
@@ -1,29 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBFC00000
-CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_SECT_SIZE=0x8000
-CONFIG_TARGET_QEMU_MIPS=y
-CONFIG_CPU_MIPS64_R1=y
-CONFIG_BOOTDELAY=10
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="qemu-mips64 # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_RARP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBFFF8000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_NS16550=y
-CONFIG_LZMA=y
diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig
deleted file mode 100644
index 4a45d5e..0000000
--- a/configs/qemu_mips64el_defconfig
+++ /dev/null
@@ -1,30 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xFFFFFFFFBFC00000
-CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_SECT_SIZE=0x8000
-CONFIG_TARGET_QEMU_MIPS=y
-CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_CPU_MIPS64_R1=y
-CONFIG_BOOTDELAY=10
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="qemu-mips64el # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_RARP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFFFFFFFBFFF8000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_NS16550=y
-CONFIG_LZMA=y
diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig
deleted file mode 100644
index ebf7af0..0000000
--- a/configs/qemu_mips_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBFC00000
-CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_SECT_SIZE=0x8000
-CONFIG_TARGET_QEMU_MIPS=y
-CONFIG_BOOTDELAY=10
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="qemu-mips # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBFFF8000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_NS16550=y
-CONFIG_LZMA=y
diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig
deleted file mode 100644
index 03862f7..0000000
--- a/configs/qemu_mipsel_defconfig
+++ /dev/null
@@ -1,28 +0,0 @@
-CONFIG_MIPS=y
-CONFIG_SYS_TEXT_BASE=0xBFC00000
-CONFIG_ENV_SIZE=0x8000
-CONFIG_ENV_SECT_SIZE=0x8000
-CONFIG_TARGET_QEMU_MIPS=y
-CONFIG_SYS_LITTLE_ENDIAN=y
-CONFIG_BOOTDELAY=10
-CONFIG_MISC_INIT_R=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_PROMPT="qemu-mipsel # "
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_IDE=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-# CONFIG_ISO_PARTITION is not set
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xBFFF8000
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SYS_NS16550=y
-CONFIG_LZMA=y
diff --git a/configs/r8a774a1_beacon_defconfig b/configs/r8a774a1_beacon_defconfig
index 2f45edd..4a87a9a 100644
--- a/configs/r8a774a1_beacon_defconfig
+++ b/configs/r8a774a1_beacon_defconfig
@@ -8,6 +8,7 @@
CONFIG_TARGET_BEACON_RZG2M=y
# CONFIG_SPL is not set
CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit"
+CONFIG_LTO=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
@@ -42,7 +43,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
diff --git a/configs/r8a774b1_beacon_defconfig b/configs/r8a774b1_beacon_defconfig
index ca514bb..2c31222 100644
--- a/configs/r8a774b1_beacon_defconfig
+++ b/configs/r8a774b1_beacon_defconfig
@@ -8,6 +8,7 @@
CONFIG_TARGET_BEACON_RZG2N=y
# CONFIG_SPL is not set
CONFIG_DEFAULT_DEVICE_TREE="r8a774b1-beacon-rzg2n-kit"
+CONFIG_LTO=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
@@ -42,7 +43,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
diff --git a/configs/r8a774e1_beacon_defconfig b/configs/r8a774e1_beacon_defconfig
index b89729d..a814d6a 100644
--- a/configs/r8a774e1_beacon_defconfig
+++ b/configs/r8a774e1_beacon_defconfig
@@ -8,6 +8,7 @@
CONFIG_TARGET_BEACON_RZG2H=y
# CONFIG_SPL is not set
CONFIG_DEFAULT_DEVICE_TREE="r8a774e1-beacon-rzg2h-kit"
+CONFIG_LTO=y
CONFIG_FIT=y
CONFIG_SUPPORT_RAW_INITRD=y
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
@@ -42,7 +43,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig
index d579737..13c19f2 100644
--- a/configs/r8a77990_ebisu_defconfig
+++ b/configs/r8a77990_ebisu_defconfig
@@ -50,7 +50,6 @@
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig
index 46a7314..3175b94 100644
--- a/configs/r8a77995_draak_defconfig
+++ b/configs/r8a77995_draak_defconfig
@@ -48,7 +48,6 @@
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS200_SUPPORT=y
diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig
index a0d1ccd..29ade17 100644
--- a/configs/rastaban_defconfig
+++ b/configs/rastaban_defconfig
@@ -62,7 +62,6 @@
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),300m(rootfs),512k(mtdoops),-(configuration)"
CONFIG_CMD_UBI=y
-# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
@@ -72,9 +71,12 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
@@ -91,7 +93,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_USB_GADGET_VENDOR_NUM=0x0908
diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig
index c5215d6..b994e07 100644
--- a/configs/rcar3_salvator-x_defconfig
+++ b/configs/rcar3_salvator-x_defconfig
@@ -52,7 +52,6 @@
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig
index e345086..24e28ab 100644
--- a/configs/rcar3_ulcb_defconfig
+++ b/configs/rcar3_ulcb_defconfig
@@ -52,7 +52,6 @@
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
@@ -62,10 +61,10 @@
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_CFI_FLASH=y
-CONFIG_RENESAS_RPC_HF=y
CONFIG_FLASH_CFI_MTD=y
-CONFIG_DM_SPI_FLASH=y
CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_RENESAS_RPC_HF=y
+CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_BITBANGMII=y
CONFIG_PHY_MICREL=y
diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig
index d41b4ba..fc936ff 100644
--- a/configs/riotboard_defconfig
+++ b/configs/riotboard_defconfig
@@ -5,17 +5,17 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_MX6S=y
CONFIG_TARGET_EMBESTMX6BOARDS=y
-CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-riotboard"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,SPL,DDR_MB=1024"
CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd"
@@ -30,24 +30,19 @@
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_PINMUX is not set
-CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_DM=y
-CONFIG_DM_GPIO=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_SST=y
@@ -56,6 +51,8 @@
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
@@ -79,5 +76,4 @@
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_VIDEO_BMP_RLE8=y
CONFIG_BMP_16BPP=y
-CONFIG_OF_LIBFDT=y
CONFIG_SPL_OF_LIBFDT=y
diff --git a/configs/rock960-rk3399_defconfig b/configs/rock960-rk3399_defconfig
index 9f1aeaa..b7ef096 100644
--- a/configs/rock960-rk3399_defconfig
+++ b/configs/rock960-rk3399_defconfig
@@ -21,9 +21,9 @@
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
+# CONFIG_CMD_SF is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
-# CONFIG_CMD_SF is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
diff --git a/configs/rpi_0_w_defconfig b/configs/rpi_0_w_defconfig
index 0156599..ca92645 100644
--- a/configs/rpi_0_w_defconfig
+++ b/configs/rpi_0_w_defconfig
@@ -21,7 +21,7 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_MMC=y
+CONFIG_TFTP_TSIZE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_DM_ETH=y
diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig
index 1ad0626..b0aab1b 100644
--- a/configs/rpi_2_defconfig
+++ b/configs/rpi_2_defconfig
@@ -21,7 +21,7 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_MMC=y
+CONFIG_TFTP_TSIZE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_DM_ETH=y
@@ -41,4 +41,3 @@
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y
-# CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set
diff --git a/configs/rpi_3_32b_defconfig b/configs/rpi_3_32b_defconfig
index a14d7ee..7b1b08c 100644
--- a/configs/rpi_3_32b_defconfig
+++ b/configs/rpi_3_32b_defconfig
@@ -22,7 +22,7 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_MMC=y
+CONFIG_TFTP_TSIZE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_PHYLIB=y
diff --git a/configs/rpi_3_b_plus_defconfig b/configs/rpi_3_b_plus_defconfig
index ebab0b4..62ef2dd 100644
--- a/configs/rpi_3_b_plus_defconfig
+++ b/configs/rpi_3_b_plus_defconfig
@@ -22,7 +22,7 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_MMC=y
+CONFIG_TFTP_TSIZE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_PHYLIB=y
diff --git a/configs/rpi_3_defconfig b/configs/rpi_3_defconfig
index 4aedfb1..a19a428 100644
--- a/configs/rpi_3_defconfig
+++ b/configs/rpi_3_defconfig
@@ -22,7 +22,7 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_MMC=y
+CONFIG_TFTP_TSIZE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_PHYLIB=y
diff --git a/configs/rpi_4_32b_defconfig b/configs/rpi_4_32b_defconfig
index 0cbdd5f..e3ccdf7 100644
--- a/configs/rpi_4_32b_defconfig
+++ b/configs/rpi_4_32b_defconfig
@@ -22,9 +22,11 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_TFTP_TSIZE=y
CONFIG_DM_DMA=y
CONFIG_DFU_MMC=y
-CONFIG_DM_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_BCM2835=y
diff --git a/configs/rpi_4_defconfig b/configs/rpi_4_defconfig
index 3f21f99..b41d298 100644
--- a/configs/rpi_4_defconfig
+++ b/configs/rpi_4_defconfig
@@ -22,9 +22,11 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_TFTP_TSIZE=y
CONFIG_DM_DMA=y
CONFIG_DFU_MMC=y
-CONFIG_DM_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_BCM2835=y
diff --git a/configs/rpi_arm64_defconfig b/configs/rpi_arm64_defconfig
index d282d50..84e2237 100644
--- a/configs/rpi_arm64_defconfig
+++ b/configs/rpi_arm64_defconfig
@@ -20,8 +20,8 @@
CONFIG_OF_BOARD=y
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_TFTP_TSIZE=y
CONFIG_DM_DMA=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_BCM2835=y
diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig
index 7863810..1880f22 100644
--- a/configs/rpi_defconfig
+++ b/configs/rpi_defconfig
@@ -21,7 +21,7 @@
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_DM_MMC=y
+CONFIG_TFTP_TSIZE=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_BCM2835=y
CONFIG_DM_ETH=y
diff --git a/configs/rut_defconfig b/configs/rut_defconfig
index 4037c6a..0913388 100644
--- a/configs/rut_defconfig
+++ b/configs/rut_defconfig
@@ -27,11 +27,9 @@
CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
CONFIG_USE_PREBOOT=y
-# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_NAND_DRIVERS=y
@@ -56,7 +54,6 @@
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
-CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@@ -73,9 +70,12 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
@@ -93,17 +93,11 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_USB_GADGET_VENDOR_NUM=0x0908
CONFIG_USB_GADGET_PRODUCT_NUM=0x02d2
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y
-CONFIG_VIDEO=y
-# CONFIG_VIDEO_SW_CURSOR is not set
-CONFIG_SYS_CONSOLE_BG_COL=0xff
-CONFIG_SYS_CONSOLE_FG_COL=0x00
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
-CONFIG_VIDEO_BMP_RLE8=y
diff --git a/configs/s400_defconfig b/configs/s400_defconfig
index 39e44c0..af89fab 100644
--- a/configs/s400_defconfig
+++ b/configs/s400_defconfig
@@ -25,7 +25,6 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
diff --git a/configs/s5p4418_nanopi2_defconfig b/configs/s5p4418_nanopi2_defconfig
index c5537ba..36b8a15 100644
--- a/configs/s5p4418_nanopi2_defconfig
+++ b/configs/s5p4418_nanopi2_defconfig
@@ -40,7 +40,6 @@
# CONFIG_NET is not set
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_NEXELL=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig
index 28d8be6..72f9ce1 100644
--- a/configs/s5p_goni_defconfig
+++ b/configs/s5p_goni_defconfig
@@ -36,6 +36,7 @@
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
# CONFIG_NET is not set
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_S5P=y
diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig
index 759034a..734a99f 100644
--- a/configs/s5pc210_universal_defconfig
+++ b/configs/s5pc210_universal_defconfig
@@ -33,6 +33,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_SYS_I2C_S3C24X0=y
CONFIG_MMC_DW=y
CONFIG_MMC_SDHCI=y
diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig
index 8189997..e5b5226 100644
--- a/configs/sam9x60ek_mmc_defconfig
+++ b/configs/sam9x60ek_mmc_defconfig
@@ -49,7 +49,6 @@
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
CONFIG_MICROCHIP_FLEXCOM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig
index f4ba348..0cf940f 100644
--- a/configs/sam9x60ek_nandflash_defconfig
+++ b/configs/sam9x60ek_nandflash_defconfig
@@ -51,7 +51,6 @@
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
CONFIG_MICROCHIP_FLEXCOM=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
# CONFIG_SYS_NAND_USE_FLASH_BBT is not set
diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig
index 29071e8..57a87a6 100644
--- a/configs/sam9x60ek_qspiflash_defconfig
+++ b/configs/sam9x60ek_qspiflash_defconfig
@@ -59,7 +59,6 @@
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
CONFIG_MICROCHIP_FLEXCOM=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig
index fd5feb4..30697ad 100644
--- a/configs/sama5d27_giantboard_defconfig
+++ b/configs/sama5d27_giantboard_defconfig
@@ -61,7 +61,6 @@
CONFIG_ATMEL_PIO4=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_DM_SPI_FLASH=y
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig
index f867603..fbc0736 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -62,7 +62,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig
index 1a63f38..6be9cc1 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -62,7 +62,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig
index 69b4203..2467f40 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -70,7 +70,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig
index 06c6a16..8390198 100644
--- a/configs/sama5d27_wlsom1_ek_mmc_defconfig
+++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig
@@ -64,7 +64,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
index 6e88e34..3cb1ff6 100644
--- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig
@@ -76,7 +76,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig
index f4f4134..c9e82d0 100644
--- a/configs/sama5d2_icp_mmc_defconfig
+++ b/configs/sama5d2_icp_mmc_defconfig
@@ -63,7 +63,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_DM_ETH=y
diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig b/configs/sama5d2_ptc_ek_mmc_defconfig
index 978b4b2..b738e3f 100644
--- a/configs/sama5d2_ptc_ek_mmc_defconfig
+++ b/configs/sama5d2_ptc_ek_mmc_defconfig
@@ -49,7 +49,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig b/configs/sama5d2_ptc_ek_nandflash_defconfig
index 9017e9d..89ff40d 100644
--- a/configs/sama5d2_ptc_ek_nandflash_defconfig
+++ b/configs/sama5d2_ptc_ek_nandflash_defconfig
@@ -50,7 +50,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig
index 2750e24..1f3f728 100644
--- a/configs/sama5d2_xplained_emmc_defconfig
+++ b/configs/sama5d2_xplained_emmc_defconfig
@@ -61,7 +61,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig
index 5ac0996..8c637c4 100644
--- a/configs/sama5d2_xplained_mmc_defconfig
+++ b/configs/sama5d2_xplained_mmc_defconfig
@@ -63,7 +63,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig
index fa2e9b8..ea3e3b5 100644
--- a/configs/sama5d2_xplained_qspiflash_defconfig
+++ b/configs/sama5d2_xplained_qspiflash_defconfig
@@ -62,7 +62,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig
index 70209ef..5b6d1f4 100644
--- a/configs/sama5d2_xplained_spiflash_defconfig
+++ b/configs/sama5d2_xplained_spiflash_defconfig
@@ -66,7 +66,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_MTD=y
diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig
index 7b6cbb1..2893fb9 100644
--- a/configs/sama5d36ek_cmp_mmc_defconfig
+++ b/configs/sama5d36ek_cmp_mmc_defconfig
@@ -41,7 +41,6 @@
CONFIG_CLK_AT91=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig
index a3b2fac..3a3d9d2 100644
--- a/configs/sama5d36ek_cmp_nandflash_defconfig
+++ b/configs/sama5d36ek_cmp_nandflash_defconfig
@@ -42,7 +42,6 @@
CONFIG_CLK_AT91=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig
index 4d604a2..1500c02 100644
--- a/configs/sama5d36ek_cmp_spiflash_defconfig
+++ b/configs/sama5d36ek_cmp_spiflash_defconfig
@@ -43,7 +43,6 @@
CONFIG_CLK_AT91=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig
index dad7f39..162a59d 100644
--- a/configs/sama5d3_xplained_mmc_defconfig
+++ b/configs/sama5d3_xplained_mmc_defconfig
@@ -62,7 +62,6 @@
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig
index 9c82288..978b4ed 100644
--- a/configs/sama5d3_xplained_nandflash_defconfig
+++ b/configs/sama5d3_xplained_nandflash_defconfig
@@ -62,7 +62,6 @@
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig
index 5c0c5cb..35c9f5f 100644
--- a/configs/sama5d3xek_mmc_defconfig
+++ b/configs/sama5d3xek_mmc_defconfig
@@ -61,7 +61,6 @@
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig
index fe615c3..ad48f29 100644
--- a/configs/sama5d3xek_nandflash_defconfig
+++ b/configs/sama5d3xek_nandflash_defconfig
@@ -60,7 +60,6 @@
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig
index 109ac9f..7ae7b10 100644
--- a/configs/sama5d3xek_spiflash_defconfig
+++ b/configs/sama5d3xek_spiflash_defconfig
@@ -62,7 +62,6 @@
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig
index c5ca929..0754ead 100644
--- a/configs/sama5d4_xplained_mmc_defconfig
+++ b/configs/sama5d4_xplained_mmc_defconfig
@@ -58,7 +58,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig
index e264b9c..05e67c7 100644
--- a/configs/sama5d4_xplained_nandflash_defconfig
+++ b/configs/sama5d4_xplained_nandflash_defconfig
@@ -59,7 +59,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig
index b033e38..5828f37 100644
--- a/configs/sama5d4_xplained_spiflash_defconfig
+++ b/configs/sama5d4_xplained_spiflash_defconfig
@@ -64,7 +64,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig
index 3aa1fd4..5a46118 100644
--- a/configs/sama5d4ek_mmc_defconfig
+++ b/configs/sama5d4ek_mmc_defconfig
@@ -56,7 +56,6 @@
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig
index 00216f0..8f7858b 100644
--- a/configs/sama5d4ek_nandflash_defconfig
+++ b/configs/sama5d4ek_nandflash_defconfig
@@ -57,7 +57,6 @@
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_NAND_ATMEL=y
diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig
index e62619f..232d998 100644
--- a/configs/sama5d4ek_spiflash_defconfig
+++ b/configs/sama5d4ek_spiflash_defconfig
@@ -59,7 +59,6 @@
CONFIG_AT91_UTMI=y
CONFIG_AT91_H32MX=y
CONFIG_AT91_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_GENERIC_ATMEL_MCI=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/sama7g5ek_mmc1_defconfig b/configs/sama7g5ek_mmc1_defconfig
index 8acb5f2..337b58b 100644
--- a/configs/sama7g5ek_mmc1_defconfig
+++ b/configs/sama7g5ek_mmc1_defconfig
@@ -54,7 +54,6 @@
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
CONFIG_MICROCHIP_FLEXCOM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_PHY_MICREL=y
diff --git a/configs/sama7g5ek_mmc_defconfig b/configs/sama7g5ek_mmc_defconfig
index 2c7a81d..1dbf527 100644
--- a/configs/sama7g5ek_mmc_defconfig
+++ b/configs/sama7g5ek_mmc_defconfig
@@ -54,7 +54,6 @@
CONFIG_SYS_I2C_AT91=y
CONFIG_I2C_EEPROM=y
CONFIG_MICROCHIP_FLEXCOM=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_PHY_MICREL=y
diff --git a/configs/sandbox64_defconfig b/configs/sandbox64_defconfig
index 8a7e519..9cd7461 100644
--- a/configs/sandbox64_defconfig
+++ b/configs/sandbox64_defconfig
@@ -91,6 +91,7 @@
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_EXT4_INTERFACE="host"
CONFIG_ENV_EXT4_DEVICE_AND_PART="0:0"
+CONFIG_ENV_IMPORT_FDT=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
@@ -106,6 +107,8 @@
CONFIG_BUTTON=y
CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
+CONFIG_CLK_K210=y
+CONFIG_CLK_K210_SET_RATE=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
CONFIG_DM_DEMO_SIMPLE=y
@@ -204,6 +207,7 @@
CONFIG_SPMI_SANDBOX=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SANDBOX=y
+CONFIG_SYSINFO_GPIO=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index d3de9c3..0275dda 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -21,8 +21,7 @@
CONFIG_CONSOLE_RECORD=y
CONFIG_CONSOLE_RECORD_OUT_SIZE=0x1000
CONFIG_PRE_CONSOLE_BUFFER=y
-CONFIG_LOG_SYSLOG=y
-CONFIG_LOG_ERROR_RETURN=y
+CONFIG_LOG=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_F=y
CONFIG_STACKPROTECTOR=y
@@ -108,6 +107,7 @@
CONFIG_ENV_IS_IN_EXT4=y
CONFIG_ENV_EXT4_INTERFACE="host"
CONFIG_ENV_EXT4_DEVICE_AND_PART="0:0"
+CONFIG_ENV_IMPORT_FDT=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
@@ -131,6 +131,8 @@
CONFIG_CLK=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_CLK_SCMI=y
+CONFIG_CLK_K210=y
+CONFIG_CLK_K210_SET_RATE=y
CONFIG_SANDBOX_CLK_CCF=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
@@ -221,8 +223,8 @@
CONFIG_REGULATOR_RK8XX=y
CONFIG_REGULATOR_S5M8767=y
CONFIG_DM_REGULATOR_SANDBOX=y
-CONFIG_DM_REGULATOR_SCMI=y
CONFIG_REGULATOR_TPS65090=y
+CONFIG_DM_REGULATOR_SCMI=y
CONFIG_DM_PWM=y
CONFIG_PWM_SANDBOX=y
CONFIG_RAM=y
@@ -247,6 +249,7 @@
CONFIG_SPMI_SANDBOX=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SANDBOX=y
+CONFIG_SYSINFO_GPIO=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
diff --git a/configs/sandbox_flattree_defconfig b/configs/sandbox_flattree_defconfig
index 97ac46d..772230c 100644
--- a/configs/sandbox_flattree_defconfig
+++ b/configs/sandbox_flattree_defconfig
@@ -86,6 +86,8 @@
CONFIG_AXI_SANDBOX=y
CONFIG_CLK=y
CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_K210=y
+CONFIG_CLK_K210_SET_RATE=y
CONFIG_SANDBOX_CLK_CCF=y
CONFIG_CPU=y
CONFIG_DM_DEMO=y
@@ -178,6 +180,7 @@
CONFIG_SPMI_SANDBOX=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SANDBOX=y
+CONFIG_SYSINFO_GPIO=y
CONFIG_SYSRESET=y
CONFIG_TIMER=y
CONFIG_TIMER_EARLY=y
diff --git a/configs/sandbox_noinst_defconfig b/configs/sandbox_noinst_defconfig
index 0190590..c7fc98b 100644
--- a/configs/sandbox_noinst_defconfig
+++ b/configs/sandbox_noinst_defconfig
@@ -136,7 +136,6 @@
CONFIG_CROS_EC_LPC=y
CONFIG_CROS_EC_SANDBOX=y
CONFIG_CROS_EC_SPI=y
-CONFIG_IRQ=y
CONFIG_P2SB=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y
@@ -198,6 +197,7 @@
CONFIG_SPMI_SANDBOX=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SANDBOX=y
+CONFIG_SYSINFO_GPIO=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_TIMER=y
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index 0fac3ad..87223a5 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -11,7 +11,6 @@
CONFIG_SPL=y
CONFIG_BOOTSTAGE_STASH_ADDR=0x0
CONFIG_DEFAULT_DEVICE_TREE="sandbox"
-CONFIG_TARGET_SANDBOX_SPL=y
CONFIG_SANDBOX_SPL=y
CONFIG_DEBUG_UART=y
CONFIG_DISTRO_DEFAULTS=y
@@ -200,6 +199,7 @@
CONFIG_SPMI_SANDBOX=y
CONFIG_SYSINFO=y
CONFIG_SYSINFO_SANDBOX=y
+CONFIG_SYSINFO_GPIO=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_TIMER=y
diff --git a/configs/sei510_defconfig b/configs/sei510_defconfig
index 2c84abf..d400483 100644
--- a/configs/sei510_defconfig
+++ b/configs/sei510_defconfig
@@ -43,13 +43,12 @@
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
# CONFIG_INPUT is not set
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
diff --git a/configs/sei610_defconfig b/configs/sei610_defconfig
index 392ab64..aa2307e 100644
--- a/configs/sei610_defconfig
+++ b/configs/sei610_defconfig
@@ -43,13 +43,12 @@
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
# CONFIG_INPUT is not set
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
diff --git a/configs/sheevaplug_defconfig b/configs/sheevaplug_defconfig
index 65d8dff..242f97d 100644
--- a/configs/sheevaplug_defconfig
+++ b/configs/sheevaplug_defconfig
@@ -39,8 +39,6 @@
CONFIG_ENV_IS_IN_NAND=y
CONFIG_NETCONSOLE=y
CONFIG_DM=y
-CONFIG_MVSATA_IDE=y
-CONFIG_DM_MMC=y
CONFIG_MVEBU_MMC=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig
new file mode 100644
index 0000000..01ca2d8
--- /dev/null
+++ b/configs/sifive_unmatched_defconfig
@@ -0,0 +1,42 @@
+CONFIG_RISCV=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
+CONFIG_TARGET_SIFIVE_UNMATCHED=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+# CONFIG_SPL_USE_ARCH_MEMMOVE is not set
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_PWM=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OCORES=y
+CONFIG_E1000=y
+CONFIG_NVME=y
+CONFIG_PCI=y
+CONFIG_PCIE_DW_SIFIVE=y
+CONFIG_DM_RESET=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig
index dcd7560..7ef4599 100644
--- a/configs/silinux_ek874_defconfig
+++ b/configs/silinux_ek874_defconfig
@@ -2,32 +2,28 @@
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_RMOBILE=y
CONFIG_SYS_TEXT_BASE=0x50000000
-CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3F0000
CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0xe6318000
CONFIG_RCAR_GEN3=y
CONFIG_TARGET_SILINUX_EK874=y
-# CONFIG_BOARD_EARLY_INIT_F is not set
-CONFIG_SOC_DEVICE=y
-CONFIG_SOC_DEVICE_RENESAS=y
CONFIG_DEFAULT_DEVICE_TREE="r8a774c0-ek874-u-boot"
-CONFIG_SMBIOS_PRODUCT_NAME=""
CONFIG_FIT=y
+CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20"
-CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE="r8a774c0-ek874.dtb"
-CONFIG_VERSION_VARIABLE=y
+# CONFIG_BOARD_EARLY_INIT_F is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
+CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
@@ -41,28 +37,20 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
-CONFIG_BLK=y
CONFIG_CLK=y
CONFIG_CLK_RENESAS=y
-CONFIG_DM_GPIO=y
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_SPI_FLASH_USE_4K_SECTORS=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_RENESAS_RPC_SPI=y
-CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_RENESAS_SDHI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_WINBOND=y
CONFIG_BITBANGMII=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
@@ -71,6 +59,10 @@
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SCIF_CONSOLE=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_RENESAS_RPC_SPI=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_USB=y
@@ -80,4 +72,3 @@
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_SMBIOS_MANUFACTURER=""
diff --git a/configs/silk_defconfig b/configs/silk_defconfig
index 90b5781..00b91dd 100644
--- a/configs/silk_defconfig
+++ b/configs/silk_defconfig
@@ -66,7 +66,6 @@
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_SH_MMCIF=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
diff --git a/configs/sipeed_maix_bitm_defconfig b/configs/sipeed_maix_bitm_defconfig
index 210848c..33c67c0 100644
--- a/configs/sipeed_maix_bitm_defconfig
+++ b/configs/sipeed_maix_bitm_defconfig
@@ -7,10 +7,12 @@
CONFIG_STACK_SIZE=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run k210_bootcmd"
+CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"
# CONFIG_NET is not set
+CONFIG_CLK_K210_SET_RATE=y
# CONFIG_INPUT is not set
CONFIG_SF_DEFAULT_BUS=3
# CONFIG_DM_ETH is not set
diff --git a/configs/slimbootloader_defconfig b/configs/slimbootloader_defconfig
index e3c81a5..5cfbaa2 100644
--- a/configs/slimbootloader_defconfig
+++ b/configs/slimbootloader_defconfig
@@ -18,6 +18,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_PCI_PNP is not set
diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig
index 1f600d0..dc7b277 100644
--- a/configs/smartweb_defconfig
+++ b/configs/smartweb_defconfig
@@ -53,6 +53,7 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig
index a4437c1..95fd1ba 100644
--- a/configs/snapper9260_defconfig
+++ b/configs/snapper9260_defconfig
@@ -31,6 +31,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_AT91_GPIO=y
CONFIG_CMD_PCA953X=y
# CONFIG_MMC is not set
diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig
index 63fa8af..0e77080 100644
--- a/configs/snapper9g20_defconfig
+++ b/configs/snapper9g20_defconfig
@@ -30,6 +30,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_AT91_GPIO=y
CONFIG_CMD_PCA953X=y
# CONFIG_MMC is not set
diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig
index e5b7f4b..29e3fb8 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -14,10 +14,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000
CONFIG_SPL_FIT_SIGNATURE=y
-CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
@@ -26,6 +23,7 @@
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run mmcfitboot"
+CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
@@ -52,7 +50,6 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig
index 3d5d39f..0e5ef06 100644
--- a/configs/socfpga_agilex_defconfig
+++ b/configs/socfpga_agilex_defconfig
@@ -44,7 +44,6 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig
index fac9cf7..af726ba 100644
--- a/configs/socfpga_agilex_vab_defconfig
+++ b/configs/socfpga_agilex_vab_defconfig
@@ -15,19 +15,16 @@
CONFIG_SPL_FS_FAT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk"
CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000
CONFIG_SPL_FIT_SIGNATURE=y
-CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-# CONFIG_LEGACY_IMAGE_FORMAT is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
+CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
@@ -54,7 +51,6 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index fdad9bd..4687754 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -39,7 +39,6 @@
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
CONFIG_FS_LOADER=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index ff9c834..e6e6cb2 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -39,10 +39,10 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 5b75026..ff7aa1d 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -39,10 +39,10 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index 73549fe..70a891b 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -44,10 +44,10 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 6c49f28..35ad9a2 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -39,10 +39,10 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index 9075af6..92d9336 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -36,10 +36,10 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig
index d2f6799..c95d97e 100644
--- a/configs/socfpga_de1_soc_defconfig
+++ b/configs/socfpga_de1_soc_defconfig
@@ -37,7 +37,6 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_PHY_MICREL=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index 58700d9..2e7a9a2 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -37,10 +37,10 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MTD=y
diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig
index 710e97c..d9f4df4 100644
--- a/configs/socfpga_secu1_defconfig
+++ b/configs/socfpga_secu1_defconfig
@@ -63,7 +63,6 @@
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_EEPROM_SIZE=1024
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index 2c6135b..32f2031 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -39,10 +39,10 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 13a911f..756388e 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -40,10 +40,10 @@
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index bf864d0..734b5d2 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -49,7 +49,6 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_SPEED=100000000
diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig
index 7466025..9f2f220 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -14,10 +14,7 @@
CONFIG_SPL_FS_FAT=y
CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk"
CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_SIGNATURE_MAX_SIZE=0x10000000
CONFIG_SPL_FIT_SIGNATURE=y
-CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
@@ -26,6 +23,7 @@
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run mmcfitboot"
+CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
@@ -53,7 +51,6 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig
index 2d145e1..da8bf98 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -47,7 +47,6 @@
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x2003
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index 78f8948..174494c 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -53,6 +53,7 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_LED_STATUS=y
@@ -71,7 +72,6 @@
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
-CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD=y
CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/som-db5800-som-6867_defconfig b/configs/som-db5800-som-6867_defconfig
index 393882d..6cf91e0 100644
--- a/configs/som-db5800-som-6867_defconfig
+++ b/configs/som-db5800-som-6867_defconfig
@@ -48,6 +48,7 @@
CONFIG_EFI_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig
index 55505ea..c668447 100644
--- a/configs/stm32f429-evaluation_defconfig
+++ b/configs/stm32f429-evaluation_defconfig
@@ -24,6 +24,5 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-CONFIG_DM_MMC=y
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/stm32f469-discovery_defconfig b/configs/stm32f469-discovery_defconfig
index 3760397..d5d6dc6 100644
--- a/configs/stm32f469-discovery_defconfig
+++ b/configs/stm32f469-discovery_defconfig
@@ -24,7 +24,6 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-CONFIG_DM_MMC=y
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig
index e6585e5..7769026 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -37,7 +37,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
-CONFIG_DM_MMC=y
+# CONFIG_SPL_BLK is not set
# CONFIG_SPL_DM_MMC is not set
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig
index 6dc9668..4150091 100644
--- a/configs/stm32f769-disco_defconfig
+++ b/configs/stm32f769-disco_defconfig
@@ -36,7 +36,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
-CONFIG_DM_MMC=y
+# CONFIG_SPL_BLK is not set
# CONFIG_SPL_DM_MMC is not set
CONFIG_ARM_PL180_MMCI=y
CONFIG_MTD=y
diff --git a/configs/stm32h743-disco_defconfig b/configs/stm32h743-disco_defconfig
index 4f4144c..1712fe8 100644
--- a/configs/stm32h743-disco_defconfig
+++ b/configs/stm32h743-disco_defconfig
@@ -26,7 +26,6 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-CONFIG_DM_MMC=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32h743-eval_defconfig b/configs/stm32h743-eval_defconfig
index 1812485..cb7deda 100644
--- a/configs/stm32h743-eval_defconfig
+++ b/configs/stm32h743-eval_defconfig
@@ -26,7 +26,6 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-CONFIG_DM_MMC=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32h750-art-pi_defconfig b/configs/stm32h750-art-pi_defconfig
index 447af5b..78b937f 100644
--- a/configs/stm32h750-art-pi_defconfig
+++ b/configs/stm32h750-art-pi_defconfig
@@ -8,11 +8,14 @@
CONFIG_TARGET_STM32H750_ART_PI=y
CONFIG_DEFAULT_DEVICE_TREE="stm32h750i-art-pi"
CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
CONFIG_BOOTDELAY=3
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
CONFIG_AUTOBOOT_STOP_STR=" "
-# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttySTM0,2000000 root=/dev/ram loglevel=8"
+CONFIG_BOOTCOMMAND="bootm 90080000"
CONFIG_DEFAULT_FDT_FILE="stm32h750i-art-pi"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
@@ -28,24 +31,8 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
-CONFIG_DM_MMC=y
+CONFIG_DM_DMA=y
CONFIG_STM32_SDMMC2=y
# CONFIG_PINCTRL_FULL is not set
-CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_BAUDRATE=2000000
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySTM0,2000000 root=/dev/ram loglevel=8"
-CONFIG_BOOTCOMMAND="bootm 90080000"
-CONFIG_REQUIRE_SERIAL_CONSOLE=y
-CONFIG_SERIAL_PRESENT=y
-CONFIG_DM_SERIAL=y
-CONFIG_STM32_SERIAL=y
-CONFIG_FIT=y
-CONFIG_FIT_EXTERNAL_OFFSET=0x0
-CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
-CONFIG_FIT_FULL_CHECK=y
-CONFIG_FIT_PRINT=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_USE_BOOTCOMMAND=y
-CONFIG_DM_DMA=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
index 55f9fb9..24a7bdf 100644
--- a/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-ctouch2_defconfig
@@ -53,7 +53,6 @@
CONFIG_DM_MAILBOX=y
CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
index 2bfaf65..ab4819f 100644
--- a/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
+++ b/configs/stm32mp15-icore-stm32mp1-edimm2.2_defconfig
@@ -53,7 +53,6 @@
CONFIG_DM_MAILBOX=y
CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
index c0c7ff1..14bdf93 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2-of7_defconfig
@@ -53,7 +53,6 @@
CONFIG_DM_MAILBOX=y
CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
index 17aad82..55f919c 100644
--- a/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
+++ b/configs/stm32mp15-microgea-stm32mp1-microdev2_defconfig
@@ -53,7 +53,6 @@
CONFIG_DM_MAILBOX=y
CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_PHY_REALTEK=y
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index a60198f..3ff46f7 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -12,8 +12,8 @@
CONFIG_SPL=y
CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_CMD_STM32PROG=y
-CONFIG_TYPEC_STUSB160X=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
+CONFIG_TYPEC_STUSB160X=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
# CONFIG_ARMV7_VIRT is not set
@@ -38,6 +38,7 @@
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_ADC=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
@@ -101,7 +102,6 @@
CONFIG_DM_MAILBOX=y
CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig
index e36d34d..a127506 100644
--- a/configs/stm32mp15_dhcom_basic_defconfig
+++ b/configs/stm32mp15_dhcom_basic_defconfig
@@ -36,6 +36,7 @@
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_ADC=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
@@ -92,7 +93,6 @@
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=3
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig
index 4794b1a..40d06f4 100644
--- a/configs/stm32mp15_dhcor_basic_defconfig
+++ b/configs/stm32mp15_dhcor_basic_defconfig
@@ -34,6 +34,7 @@
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_ADC=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
@@ -88,7 +89,6 @@
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x53
CONFIG_SYS_I2C_EEPROM_BUS=2
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig
index 8c71ca6..afbf721 100644
--- a/configs/stm32mp15_trusted_defconfig
+++ b/configs/stm32mp15_trusted_defconfig
@@ -8,8 +8,8 @@
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_TARGET_ST_STM32MP15x=y
CONFIG_CMD_STM32PROG=y
-CONFIG_TYPEC_STUSB160X=y
CONFIG_ENV_OFFSET_REDUND=0x2C0000
+CONFIG_TYPEC_STUSB160X=y
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
@@ -21,6 +21,7 @@
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_UNZIP=y
CONFIG_CMD_ADC=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
@@ -81,7 +82,6 @@
CONFIG_DM_MAILBOX=y
CONFIG_STM32_IPCC=y
CONFIG_STM32_FMC2_EBI=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_STM32_SDMMC2=y
CONFIG_MTD=y
diff --git a/configs/stout_defconfig b/configs/stout_defconfig
index 9c64c33..4d57d71 100644
--- a/configs/stout_defconfig
+++ b/configs/stout_defconfig
@@ -65,7 +65,6 @@
CONFIG_RCAR_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_RCAR_IIC=y
-CONFIG_DM_MMC=y
CONFIG_RENESAS_SDHI=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
index 1f7e342..dbd6428 100644
--- a/configs/taurus_defconfig
+++ b/configs/taurus_defconfig
@@ -44,7 +44,7 @@
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="U-Boot> "
-CONFIG_SYS_XTRACE=n
+# CONFIG_SYS_XTRACE is not set
# CONFIG_CMD_BDI is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMI is not set
@@ -71,6 +71,7 @@
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_DFU_NAND=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_AT91_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
diff --git a/configs/tbs2910_defconfig b/configs/tbs2910_defconfig
index b71657a..e2e4db5 100644
--- a/configs/tbs2910_defconfig
+++ b/configs/tbs2910_defconfig
@@ -67,7 +67,6 @@
CONFIG_DWC_AHSATA=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
index 897d061..8c2af20 100644
--- a/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845-pcie-x4_defconfig
@@ -52,6 +52,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/theadorable-x86-conga-qa3-e3845_defconfig b/configs/theadorable-x86-conga-qa3-e3845_defconfig
index a8890eb..bbeea8d 100644
--- a/configs/theadorable-x86-conga-qa3-e3845_defconfig
+++ b/configs/theadorable-x86-conga-qa3-e3845_defconfig
@@ -51,6 +51,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
index 51aeaaf..f560d2b 100644
--- a/configs/theadorable-x86-dfi-bt700_defconfig
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -49,6 +49,7 @@
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_TFTP_TSIZE=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CPU=y
diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig
index c54b91e..247538a 100644
--- a/configs/thuban_defconfig
+++ b/configs/thuban_defconfig
@@ -62,7 +62,6 @@
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),512k(u-boot.env0),512k(u-boot.env1),512k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
-# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
@@ -72,9 +71,12 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_BOOTP_SEND_HOSTNAME=y
CONFIG_SPL_DM=y
+# CONFIG_SPL_BLK is not set
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
@@ -91,7 +93,6 @@
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Siemens AG"
CONFIG_USB_GADGET_VENDOR_NUM=0x0908
diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig
index 0ea078e..e38d409 100644
--- a/configs/ti816x_evm_defconfig
+++ b/configs/ti816x_evm_defconfig
@@ -54,7 +54,6 @@
CONFIG_DM=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OMAP24XX=y
-CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
diff --git a/configs/tools-only_defconfig b/configs/tools-only_defconfig
index e16f702..c6f287e 100644
--- a/configs/tools-only_defconfig
+++ b/configs/tools-only_defconfig
@@ -8,6 +8,7 @@
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_BOOTM is not set
# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_EXTENSION is not set
CONFIG_BOOTP_DNS2=y
# CONFIG_CMD_DATE is not set
CONFIG_OF_CONTROL=y
diff --git a/configs/topic_miami_defconfig b/configs/topic_miami_defconfig
index ec66bb0..3681919 100644
--- a/configs/topic_miami_defconfig
+++ b/configs/topic_miami_defconfig
@@ -38,6 +38,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_I2C=y
diff --git a/configs/topic_miamilite_defconfig b/configs/topic_miamilite_defconfig
index e414594..301a357 100644
--- a/configs/topic_miamilite_defconfig
+++ b/configs/topic_miamilite_defconfig
@@ -38,6 +38,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_I2C=y
diff --git a/configs/topic_miamiplus_defconfig b/configs/topic_miamiplus_defconfig
index 0041ee1..27cd913 100644
--- a/configs/topic_miamiplus_defconfig
+++ b/configs/topic_miamiplus_defconfig
@@ -37,6 +37,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_I2C=y
diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig
index 8439ddc..a3955e1 100644
--- a/configs/trats2_defconfig
+++ b/configs/trats2_defconfig
@@ -34,6 +34,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_S3C24X0=y
CONFIG_MMC_DW=y
diff --git a/configs/trats_defconfig b/configs/trats_defconfig
index 931c69b..64cd5dc 100644
--- a/configs/trats_defconfig
+++ b/configs/trats_defconfig
@@ -33,6 +33,7 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x2000000
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_S3C24X0=y
CONFIG_MMC_DW=y
diff --git a/configs/turris_mox_defconfig b/configs/turris_mox_defconfig
index f938fbb..75524ba 100644
--- a/configs/turris_mox_defconfig
+++ b/configs/turris_mox_defconfig
@@ -47,7 +47,6 @@
# CONFIG_MVEBU_GPIO is not set
CONFIG_DM_I2C=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_XENON=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index a8218da..79662ba 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -45,8 +45,8 @@
CONFIG_CMD_SATA=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_WDT=y
+CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_AES=y
@@ -63,7 +63,6 @@
CONFIG_AHCI_MVEBU=y
# CONFIG_MVEBU_GPIO is not set
CONFIG_DM_PCA953X=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
CONFIG_SPI_FLASH_MACRONIX=y
@@ -74,9 +73,9 @@
CONFIG_MII=y
CONFIG_PCI=y
CONFIG_PCI_MVEBU=y
-CONFIG_SCSI=y
CONFIG_DM_RTC=y
CONFIG_RTC_ARMADA38X=y
+CONFIG_SCSI=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/u200_defconfig b/configs/u200_defconfig
index 4da02f1..b018163 100644
--- a/configs/u200_defconfig
+++ b/configs/u200_defconfig
@@ -25,13 +25,12 @@
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MESON_G12A=y
-CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MESON_G12A=y
CONFIG_MESON_G12A_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_G12A=y
diff --git a/configs/uDPU_defconfig b/configs/uDPU_defconfig
index 9c41cf4..0c0757c 100644
--- a/configs/uDPU_defconfig
+++ b/configs/uDPU_defconfig
@@ -55,7 +55,6 @@
CONFIG_DM_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_MISC=y
-CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_XENON=y
diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig
index 064d545..a936937 100644
--- a/configs/udoo_defconfig
+++ b/configs/udoo_defconfig
@@ -5,18 +5,17 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="imx6q-udoo"
-CONFIG_OF_LIST="imx6q-udoo imx6dl-udoo"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_MX6QDL=y
CONFIG_TARGET_UDOO=y
-CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="imx6q-udoo"
CONFIG_AHCI=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
@@ -32,25 +31,23 @@
CONFIG_CMD_SATA=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_DM=y
-CONFIG_DM_GPIO=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_DM_MMC=y
CONFIG_DWC_AHSATA=y
CONFIG_FSL_USDHC=y
-CONFIG_DM_SCSI=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_DM_SCSI=y
CONFIG_MXC_UART=y
CONFIG_DM_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig
index a9b2e5b..6ab3815 100644
--- a/configs/udoo_neo_defconfig
+++ b/configs/udoo_neo_defconfig
@@ -5,19 +5,18 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic"
-CONFIG_OF_LIST="imx6sx-udoo-neo-basic imx6sx-udoo-neo-extended imx6sx-udoo-neo-full"
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x80000
CONFIG_MX6SX=y
CONFIG_TARGET_UDOO_NEO=y
-CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx6sx-udoo-neo-basic"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd"
@@ -27,28 +26,25 @@
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
+# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_CACHE=y
-# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_DM=y
-CONFIG_DM_ETH=y
-CONFIG_FEC_MXC=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
-CONFIG_PINCTRL=y
-CONFIG_PINCTRL_IMX6=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
-CONFIG_MII=y
+CONFIG_DM_ETH=y
+CONFIG_FEC_MXC=y
CONFIG_RGMII=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/usbarmory_defconfig b/configs/usbarmory_defconfig
index 39fe860..95bebdd 100644
--- a/configs/usbarmory_defconfig
+++ b/configs/usbarmory_defconfig
@@ -2,14 +2,14 @@
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x77800000
CONFIG_NR_DRAM_BANKS=1
-CONFIG_DEFAULT_DEVICE_TREE="imx53-usbarmory"
CONFIG_SYS_MEMTEST_START=0x70000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x60000
CONFIG_TARGET_USBARMORY=y
-CONFIG_OF_CONTROL=y
+CONFIG_DM_GPIO=y
# CONFIG_CMD_BMODE is not set
+CONFIG_DEFAULT_DEVICE_TREE="imx53-usbarmory"
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_CMD_MEMTEST=y
@@ -19,19 +19,18 @@
# CONFIG_CMD_PINMUX is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
+CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
-CONFIG_DM_GPIO=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
-CONFIG_MXC_UART=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_MX5=y
-CONFIG_OF_LIBFDT=y
diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig
index ca18677..9c14cef 100644
--- a/configs/venice2_defconfig
+++ b/configs/venice2_defconfig
@@ -32,6 +32,8 @@
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x2000000
CONFIG_SYS_I2C_TEGRA=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=24000000
diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig
index c8c3420..8d722b6 100644
--- a/configs/verdin-imx8mm_defconfig
+++ b/configs/verdin-imx8mm_defconfig
@@ -76,7 +76,6 @@
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_PHYLIB=y
diff --git a/configs/vinco_defconfig b/configs/vinco_defconfig
index df56e1b..be7aaa9 100644
--- a/configs/vinco_defconfig
+++ b/configs/vinco_defconfig
@@ -41,7 +41,6 @@
CONFIG_ATMEL_USART=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="L+G VInCo"
CONFIG_USB_GADGET_ATMEL_USBA=y
diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig
index 31e6cfb..8edd048 100644
--- a/configs/vining_2000_defconfig
+++ b/configs/vining_2000_defconfig
@@ -61,7 +61,6 @@
CONFIG_SYS_MMC_ENV_PART=1
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
diff --git a/configs/vocore2_defconfig b/configs/vocore2_defconfig
index e255829..5780af8 100644
--- a/configs/vocore2_defconfig
+++ b/configs/vocore2_defconfig
@@ -70,7 +70,6 @@
CONFIG_LED_BLINK=y
CONFIG_LED_GPIO=y
CONFIG_MMC=y
-CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_MTK=y
CONFIG_MTD=y
diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig
index 7c54999..c6e805a 100644
--- a/configs/wandboard_defconfig
+++ b/configs/wandboard_defconfig
@@ -58,7 +58,6 @@
CONFIG_DWC_AHSATA=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
-CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
diff --git a/configs/warp7_bl33_defconfig b/configs/warp7_bl33_defconfig
index 4b45fcd..5452a49 100644
--- a/configs/warp7_bl33_defconfig
+++ b/configs/warp7_bl33_defconfig
@@ -35,8 +35,8 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/warp7_defconfig b/configs/warp7_defconfig
index 3d111960..43471e7 100644
--- a/configs/warp7_defconfig
+++ b/configs/warp7_defconfig
@@ -41,8 +41,8 @@
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
diff --git a/configs/warp_defconfig b/configs/warp_defconfig
index 34acc9e..04f756a 100644
--- a/configs/warp_defconfig
+++ b/configs/warp_defconfig
@@ -33,6 +33,7 @@
# CONFIG_NET is not set
CONFIG_BOUNCE_BUFFER=y
CONFIG_DFU_MMC=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_USDHC=y
CONFIG_MXC_UART=y
diff --git a/configs/wetek-core2_defconfig b/configs/wetek-core2_defconfig
index 098e249..364c16c 100644
--- a/configs/wetek-core2_defconfig
+++ b/configs/wetek-core2_defconfig
@@ -27,16 +27,15 @@
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SARADC_MESON=y
-CONFIG_DM_MMC=y
CONFIG_MMC_MESON_GX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
-CONFIG_DM_MDIO=y
-CONFIG_DM_MDIO_MUX=y
-CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
+CONFIG_DM_MDIO=y
+CONFIG_DM_MDIO_MUX=y
CONFIG_ETH_DESIGNWARE_MESON8B=y
+CONFIG_MDIO_MUX_MMIOREG=y
CONFIG_MESON_GXL_USB_PHY=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_MESON_GXL=y
diff --git a/configs/x530_defconfig b/configs/x530_defconfig
index 890c94b..76574c4 100644
--- a/configs/x530_defconfig
+++ b/configs/x530_defconfig
@@ -62,7 +62,6 @@
CONFIG_NAND_PXA3XX=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_SPEED=50000000
-CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
@@ -84,3 +83,4 @@
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_WDT=y
CONFIG_WDT_ORION=y
+CONFIG_SPL_TINY_MEMSET=y
diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
index 2d639a1..121c3ae 100644
--- a/configs/xilinx_versal_virt_defconfig
+++ b/configs/xilinx_versal_virt_defconfig
@@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_POSITION_INDEPENDENT=y
+CONFIG_SYS_INIT_SP_BSS_OFFSET=1572864
CONFIG_ARCH_VERSAL=y
CONFIG_SYS_TEXT_BASE=0x8000000
CONFIG_SYS_MALLOC_F_LEN=0x100000
@@ -18,6 +19,7 @@
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_SYS_PROMPT="Versal> "
CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_CLK=y
@@ -38,14 +40,21 @@
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_OF_BOARD=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_IP_DEFRAG=y
CONFIG_TFTP_BLOCKSIZE=4096
CONFIG_CLK_VERSAL=y
+CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_VERSALPL=y
CONFIG_DM_I2C=y
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index 2fe5318..e53ef24 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -4,6 +4,7 @@
CONFIG_SYS_TEXT_BASE=0x4000000
CONFIG_SYS_MEMTEST_START=0x00000000
CONFIG_SYS_MEMTEST_END=0x00001000
+CONFIG_ENV_OFFSET=0xE00000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x100000
CONFIG_DM_GPIO=y
CONFIG_SPL_STACK_R_ADDR=0x200000
@@ -55,14 +56,19 @@
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_CMD_UBI=y
CONFIG_OF_LIST="zynq-zc702 zynq-zc706 zynq-zc770-xm010 zynq-zc770-xm011 zynq-zc770-xm011-x16 zynq-zc770-xm012 zynq-zc770-xm013 zynq-cc108 zynq-microzed zynq-minized zynq-picozed zynq-zed zynq-zturn zynq-zturn-v5 zynq-zybo zynq-zybo-z7 zynq-dlc20-rev1.0"
-CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DFU_TIMEOUT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
CONFIG_FPGA_XILINX=y
CONFIG_FPGA_ZYNQPL=y
CONFIG_DM_I2C=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index fbff215..b0cc9d9 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -33,6 +33,7 @@
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_BIND=y
@@ -58,6 +59,7 @@
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_TIME=y
+CONFIG_CMD_GETTIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
@@ -65,13 +67,15 @@
CONFIG_CMD_MTDPARTS_SPREAD=y
CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES=y
CONFIG_CMD_UBI=y
+CONFIG_PARTITION_TYPE_GUID=y
CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1"
+CONFIG_OF_LIST="avnet-ultra96-rev1 zynqmp-a2197-revA zynqmp-e-a2197-00-revA zynqmp-g-a2197-00-revA zynqmp-m-a2197-01-revA zynqmp-m-a2197-02-revA zynqmp-m-a2197-03-revA zynqmp-p-a2197-00-revA zynqmp-zc1232-revA zynqmp-zc1254-revA zynqmp-zc1751-xm015-dc1 zynqmp-zc1751-xm016-dc2 zynqmp-zc1751-xm017-dc3 zynqmp-zc1751-xm018-dc4 zynqmp-zc1751-xm019-dc5 zynqmp-zcu100-revC zynqmp-zcu102-rev1.1 zynqmp-zcu102-rev1.0 zynqmp-zcu102-revA zynqmp-zcu102-revB zynqmp-zcu104-revA zynqmp-zcu104-revC zynqmp-zcu106-revA zynqmp-zcu111-revA zynqmp-zcu1275-revA zynqmp-zcu1275-revB zynqmp-zcu1285-revA zynqmp-zcu208-revA zynqmp-zcu216-revA zynqmp-topic-miamimp-xilinx-xdp-v1r1 zynqmp-sm-k26-revA zynqmp-smk-k26-revA"
CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names interrupt-parent interrupts iommus power-domains"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETCONSOLE=y
@@ -80,7 +84,13 @@
CONFIG_SATA_CEVA=y
CONFIG_CLK_ZYNQMP=y
CONFIG_DFU_TFTP=y
+CONFIG_DFU_TIMEOUT=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_NAND=y
CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_DFU_MTD=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1800000
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
@@ -132,6 +142,8 @@
CONFIG_PHY_FIXED=y
CONFIG_XILINX_AXIEMAC=y
CONFIG_ZYNQ_GEM=y
+CONFIG_DM_RTC=y
+CONFIG_RTC_EMULATION=y
CONFIG_SCSI=y
CONFIG_DM_SCSI=y
CONFIG_ARM_DCC=y
@@ -171,4 +183,11 @@
CONFIG_PANIC_HANG=y
CONFIG_TPM=y
CONFIG_SPL_GZIP=y
+# CONFIG_SPL_HEXDUMP is not set
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_EFI_SET_TIME=y
+CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_CAPSULE_ON_DISK_EARLY=y
+CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
+CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y
diff --git a/disk/part.c b/disk/part.c
index 5e7e59c..086da84 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -714,7 +714,11 @@
int ret;
/* Separate device and partition name specification */
- part_str = strchr(dev_part_str, '#');
+ if (dev_part_str)
+ part_str = strchr(dev_part_str, '#');
+ else
+ part_str = NULL;
+
if (part_str) {
dup_str = strdup(dev_part_str);
dup_str[part_str - dev_part_str] = 0;
diff --git a/doc/README.gpt b/doc/README.gpt
index ac975f6..91e397d 100644
--- a/doc/README.gpt
+++ b/doc/README.gpt
@@ -237,6 +237,23 @@
=> gpt swap host 0 name othername
[ . . . ]
+Modifying GPT partition layout from U-Boot:
+===========================================
+
+The entire GPT partition layout can be exported to an environment
+variable and then modified enmasse. Users can change the partition
+numbers, offsets, names and sizes. The resulting variable can used to
+reformat the device. Here is an example of reading the GPT partitions
+into a variable and then modifying them:
+
+U-BOOT> gpt read mmc 0 current_partitions
+U-BOOT> env edit current_partitions
+edit: uuid_disk=[...];name=part1,start=0x4000,size=0x4000,uuid=[...];
+name=part2,start=0xc000,size=0xc000,uuid=[...];[ . . . ]
+
+U-BOOT> gpt write mmc 0 $current_partitions
+U-BOOT> gpt verify mmc 0 $current_partitions
+
Partition type GUID:
====================
diff --git a/doc/README.ne2000 b/doc/README.ne2000
deleted file mode 100644
index 0f6a2e0..0000000
--- a/doc/README.ne2000
+++ /dev/null
@@ -1,27 +0,0 @@
-This driver supports NE2000 compatible cards (those based on DP8390,
-DP83902 and similar). It can be used with PCMCIA/CF cards provided
-that the CCR is correctly initialized.
-
-The code is based on sources from the Linux kernel (pcnet_cs.c,
-8390.h) and eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2
-wonderful world are GPL, so this is, of course, GPL.
-
-I developed and tested this driver on a custom PXA255 based system and
-with a billionton CF network card connected to the PCMCIA interface of
-the micro (have a look at README.PXA_CF for the support of this port).
-
-The options you have to specify in the config file are (with the
-value for my board as an example):
-
-#define CONFIG_DRIVER_NE2000
-
-- Enables the driver
-
-#define CONFIG_DRIVER_NE2000_BASE (0x20000000+0x300)
-
-- Address where the board is mapped
-
-
-Enjoy!
-
-Christian Pellegrin <chri@ascensit.com>
diff --git a/doc/board/AndesTech/ax25-ae350.rst b/doc/board/AndesTech/ax25-ae350.rst
index f795476..9236492 100644
--- a/doc/board/AndesTech/ax25-ae350.rst
+++ b/doc/board/AndesTech/ax25-ae350.rst
@@ -343,7 +343,7 @@
cd opensbi
make PLATFORM=andes/ae350
-Copy OpenSBI FW_DYNAMIC image (build\platform\andes\ae350\firmware\fw_dynamic.bin)
+Copy OpenSBI FW_DYNAMIC image (build/platform/andes/ae350/firmware/fw_dynamic.bin)
into U-Boot root directory
@@ -532,4 +532,4 @@
Sat Apr 6 23:33:53 CST 2019
nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
-~ #
+ ~ #
diff --git a/doc/board/emulation/qemu-mips.rst b/doc/board/emulation/qemu-mips.rst
index d359251..5fd8a0a 100644
--- a/doc/board/emulation/qemu-mips.rst
+++ b/doc/board/emulation/qemu-mips.rst
@@ -1,246 +1,129 @@
.. SPDX-License-Identifier: GPL-2.0+
-.. sectionauthor:: Vlad Lungu <vlad.lungu@windriver.com>
+.. sectionauthor:: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
QEMU MIPS
=========
-Qemu is a full system emulator. See http://www.nongnu.org/qemu/
+Qemu for MIPS is based on the MIPS Malta board. The built Malta U-Boot
+images can be used for Qemu and on physical hardware. The Malta board
+supports all combinations of Little and Big Endian as well as 32 bit
+and 64 bit.
Limitations & comments
----------------------
-Supports the "-M mips" configuration of qemu: serial,NE2000,IDE.
-Supports little and big endian as well as 32 bit and 64 bit.
-Derived from au1x00 with a lot of things cut out.
-
-Supports emulated flash (patch Jean-Christophe PLAGNIOL-VILLARD) with
-recent qemu versions. When using emulated flash, launch with
--pflash <filename> and erase mips_bios.bin.
-
-
-Notes for the Qemu MIPS port
-----------------------------
+The memory size for Qemu is hard-coded to 256 MiB. For Malta Little Endian
+targets an extra endianness swapped image named *u-boot-swap.bin* is
+generated and required for Qemu.
Example usage
-^^^^^^^^^^^^^
-
-Using u-boot.bin as ROM (replaces Qemu monitor):
-
-32 bit, big endian
-
-.. code-block:: bash
-
- make qemu_mips_defconfig
- qemu-system-mips -M mips -bios u-boot.bin -nographic
-
-32 bit, little endian
-
-.. code-block:: bash
-
- make qemu_mipsel_defconfig
- qemu-system-mipsel -M mips -bios u-boot.bin -nographic
-
-64 bit, big endian
-
-.. code-block:: bash
-
- make qemu_mips64_defconfig
- qemu-system-mips64 -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
-
-64 bit, little endian
-
-.. code-block:: bash
-
- make qemu_mips64el_defconfig
- qemu-system-mips64el -cpu MIPS64R2-generic -M mips -bios u-boot.bin -nographic
-
-or using u-boot.bin from emulated flash:
+-------------
-if you use a QEMU version after commit 4224
+Build for 32 bit, big endian:
.. code-block:: bash
- # create image:
- dd of=flash bs=1k count=4k if=/dev/zero
- dd of=flash bs=1k conv=notrunc if=u-boot.bin
- # start it (see above):
- qemu-system-mips[64][el] [-cpu MIPS64R2-generic] -M mips -pflash flash -nographic
+ make malta_defconfig
+ make
+ UBOOT_BIN=u-boot.bin
+ QEMU_BIN=qemu-system-mips
+ QEMU_CPU=24Kc
-Download kernel + initrd
-^^^^^^^^^^^^^^^^^^^^^^^^
-
-On ftp://ftp.denx.de/pub/contrib/Jean-Christophe_Plagniol-Villard/qemu_mips/
-you can downland::
-
- #config to build the kernel
- qemu_mips_defconfig
- #patch to fix mips interrupt init on 2.6.24.y kernel
- qemu_mips_kernel.patch
- initrd.gz
- vmlinux
- vmlinux.bin
- System.map
-
-Generate uImage
-^^^^^^^^^^^^^^^
+Build for 32 bit, little endian:
.. code-block:: bash
- tools/mkimage -A mips -O linux -T kernel -C gzip -a 0x80010000 -e 0x80245650 -n "Linux 2.6.24.y" -d vmlinux.bin.gz uImage
+ make maltael_defconfig
+ make
+ UBOOT_BIN=u-boot-swap.bin
+ QEMU_BIN=qemu-system-mipsel
+ QEMU_CPU=24Kc
-Copy uImage to Flash
-^^^^^^^^^^^^^^^^^^^^
+Build for 64 bit, big endian:
.. code-block:: bash
- dd if=uImage bs=1k conv=notrunc seek=224 of=flash
+ make malta64_defconfig
+ make
+ UBOOT_BIN=u-boot.bin
+ QEMU_BIN=qemu-system-mips64
+ QEMU_CPU=MIPS64R2-generic
-Generate Ide Disk
-^^^^^^^^^^^^^^^^^
+Build for 64 bit, little endian:
.. code-block:: bash
- dd of=ide bs=1k count=100k if=/dev/zero
-
- # Create partion table
- sudo sfdisk ide << EOF
- label: dos
- label-id: 0x6fe3a999
- device: image
- unit: sectors
- image1 : start= 63, size= 32067, Id=83
- image2 : start= 32130, size= 32130, Id=83
- image3 : start= 64260, size= 4128705, Id=83
- EOF
+ make malta64el_defconfig
+ make
+ UBOOT_BIN=u-boot-swap.bin
+ QEMU_BIN=qemu-system-mips64el
+ QEMU_CPU=MIPS64R2-generic
-Copy to ide
-^^^^^^^^^^^
+Generate NOR flash image with U-Boot binary:
.. code-block:: bash
- dd if=uImage bs=512 conv=notrunc seek=63 of=ide
+ dd if=/dev/zero bs=1M count=4 | tr '\000' '\377' > pflash.img
+ dd if=${UBOOT_BIN} of=pflash.img conv=notrunc
-Generate ext2 on part 2 on Copy uImage and initrd.gz
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+Start Qemu:
.. code-block:: bash
- # Attached as loop device ide offset = 32130 * 512
- sudo losetup -o 16450560 /dev/loop0 ide
- # Format as ext2 ( arg2 : nb blocks)
- sudo mkfs.ext2 /dev/loop0 16065
- sudo losetup -d /dev/loop0
- # Mount and copy uImage and initrd.gz to it
- sudo mount -o loop,offset=16450560 -t ext2 ide /mnt
- sudo mkdir /mnt/boot
- cp {initrd.gz,uImage} /mnt/boot/
- # Umount it
- sudo umount /mnt
-
-Set Environment
-^^^^^^^^^^^^^^^
+ mkdir tftproot
+ ${QEMU_BIN} -nographic -cpu ${QEMU_CPU} -m 256 -drive if=pflash,file="$(pwd)/pflash.img",format=raw -netdev user,id=net0,tftp="$(pwd)/tftproot" -device pcnet,netdev=net0
.. code-block:: bash
- setenv rd_start 0x80800000
- setenv rd_size 2663940
- setenv kernel BFC38000
- setenv oad_addr 80500000
- setenv load_addr2 80F00000
- setenv kernel_flash BFC38000
- setenv load_addr_hello 80200000
- setenv bootargs 'root=/dev/ram0 init=/bin/sh'
- setenv load_rd_ext2 'ide res; ext2load ide 0:2 ${rd_start} /boot/initrd.gz'
- setenv load_rd_tftp 'tftp ${rd_start} /initrd.gz'
- setenv load_kernel_hda 'ide res; diskboot ${load_addr} 0:2'
- setenv load_kernel_ext2 'ide res; ext2load ide 0:2 ${load_addr} /boot/uImage'
- setenv load_kernel_tftp 'tftp ${load_addr} /qemu_mips/uImage'
- setenv boot_ext2_ext2 'run load_rd_ext2; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
- setenv boot_ext2_flash 'run load_rd_ext2; run addmisc; bootm ${kernel_flash}'
- setenv boot_ext2_hda 'run load_rd_ext2; run load_kernel_hda; run addmisc; bootm ${load_addr}'
- setenv boot_ext2_tftp 'run load_rd_ext2; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
- setenv boot_tftp_hda 'run load_rd_tftp; run load_kernel_hda; run addmisc; bootm ${load_addr}'
- setenv boot_tftp_ext2 'run load_rd_tftp; run load_kernel_ext2; run addmisc; bootm ${load_addr}'
- setenv boot_tftp_flash 'run load_rd_tftp; run addmisc; bootm ${kernel_flash}'
- setenv boot_tftp_tftp 'run load_rd_tftp; run load_kernel_tftp; run addmisc; bootm ${load_addr}'
- setenv load_hello_tftp 'tftp ${load_addr_hello} /examples/hello_world.bin'
- setenv go_tftp 'run load_hello_tftp; go ${load_addr_hello}'
- setenv addmisc 'setenv bootargs ${bootargs} console=ttyS0,${baudrate} rd_start=${rd_start} rd_size=${rd_size} ethaddr=${ethaddr}'
- setenv bootcmd 'run boot_tftp_flash'
-
-Now you can boot from flash, ide, ide+ext2 and tfp
+ U-Boot 2021.04-00963-g60279a2b1d (Apr 21 2021 - 19:54:32 +0200)
-.. code-block:: bash
-
- qemu-system-mips -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
+ Board: MIPS Malta CoreLV
+ DRAM: 256 MiB
+ Flash: 4 MiB
+ Loading Environment from Flash... *** Warning - bad CRC, using default environment
+ In: serial@3f8
+ Out: serial@3f8
+ Err: serial@3f8
+ Net: pcnet#0
+ IDE: Bus 0: not available
+ maltael #
How to debug U-Boot
-------------------
In order to debug U-Boot you need to start qemu with gdb server support (-s)
-and waiting the connection to start the CPU (-S)
+and waiting the connection to start the CPU (-S). Start Qemu in the first console:
.. code-block:: bash
- qemu-system-mips -S -s -M mips -pflash flash -monitor null -nographic -net nic -net user -tftp `pwd` -hda ide
-
-in an other console you start gdb
+ mkdir tftproot
+ ${QEMU_BIN} -s -S -nographic -cpu ${QEMU_CPU} -m 256 -drive if=pflash,file="$(pwd)/pflash.img",format=raw -netdev user,id=net0,tftp="$(pwd)/tftproot" -device pcnet,netdev=net0
-Debugging of U-Boot Before Relocation
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+In the second console start gdb:
-Before relocation, the addresses in the ELF file can be used without any problems
-by connecting to the gdb server localhost:1234
-
-.. code-block:: none
-
- $ mipsel-unknown-linux-gnu-gdb u-boot
- GNU gdb 6.6
- Copyright (C) 2006 Free Software Foundation, Inc.
- GDB is free software, covered by the GNU General Public License, and you are
- welcome to change it and/or distribute copies of it under certain conditions.
- Type "show copying" to see the conditions.
- There is absolutely no warranty for GDB. Type "show warranty" for details.
- This GDB was configured as "--host=i486-linux-gnu --target=mipsel-unknown-linux-gnu"...
- (gdb) target remote localhost:1234
- Remote debugging using localhost:1234
- _start () at start.S:64
- 64 RVECENT(reset,0) /* U-Boot entry point */
- Current language: auto; currently asm
- (gdb) b board.c:289
- Breakpoint 1 at 0xbfc00cc8: file board.c, line 289.
- (gdb) c
- Continuing.
-
- Breakpoint 1, board_init_f (bootflag=<value optimized out>) at board.c:290
- 290 relocate_code (addr_sp, id, addr);
- Current language: auto; currently c
- (gdb) p/x addr
- $1 = 0x87fa0000
-
-Debugging of U-Boot After Relocation
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+.. code-block:: bash
-For debugging U-Boot after relocation we need to know the address to which
-U-Boot relocates itself to 0x87fa0000 by default.
-And replace the symbol table to this offset.
+ gdb-multiarch --eval-command "target remote :1234" u-boot
-.. code-block:: none
+.. code-block:: bash
- (gdb) symbol-file
- Discard symbol table from `/private/u-boot-arm/u-boot'? (y or n) y
- Error in re-setting breakpoint 1:
- No symbol table is loaded. Use the "file" command.
- No symbol file now.
- (gdb) add-symbol-file u-boot 0x87fa0000
- add symbol table from file "u-boot" at
- .text_addr = 0x87fa0000
- (y or n) y
- Reading symbols from /private/u-boot-arm/u-boot...done.
- Breakpoint 1 at 0x87fa0cc8: file board.c, line 289.
- (gdb) c
- Continuing.
+ GNU gdb (Ubuntu 9.2-0ubuntu1~20.04) 9.2
+ Copyright (C) 2020 Free Software Foundation, Inc.
+ License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
+ This is free software: you are free to change and redistribute it.
+ There is NO WARRANTY, to the extent permitted by law.
+ Type "show copying" and "show warranty" for details.
+ This GDB was configured as "x86_64-linux-gnu".
+ Type "show configuration" for configuration details.
+ For bug reporting instructions, please see:
+ <http://www.gnu.org/software/gdb/bugs/>.
+ Find the GDB manual and other documentation resources online at:
+ <http://www.gnu.org/software/gdb/documentation/>.
- Program received signal SIGINT, Interrupt.
- 0xffffffff87fa0de4 in udelay (usec=<value optimized out>) at time.c:78
- 78 while ((tmo - read_c0_count()) < 0x7fffffff)
+ For help, type "help".
+ Type "apropos word" to search for commands related to "word"...
+ Reading symbols from u-boot...
+ Remote debugging using :1234
+ 0xbfc00000 in ?? ()
+ (gdb) c
+ Continuing.
diff --git a/doc/board/sifive/index.rst b/doc/board/sifive/index.rst
index ed7eacf..a43937a 100644
--- a/doc/board/sifive/index.rst
+++ b/doc/board/sifive/index.rst
@@ -7,3 +7,4 @@
:maxdepth: 2
unleashed
+ unmatched
diff --git a/doc/board/sifive/unmatched.rst b/doc/board/sifive/unmatched.rst
new file mode 100644
index 0000000..e65b0d3
--- /dev/null
+++ b/doc/board/sifive/unmatched.rst
@@ -0,0 +1,536 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+HiFive Unmatched
+================
+
+FU740-C000 RISC-V SoC
+---------------------
+The FU740-C000 is a 4+1 64-bit RISC-V core SoC from SiFive.
+
+The HiFive Unmatched development platform is based on FU740-C000 and capable
+of running Linux.
+
+Mainline support
+----------------
+The support for following drivers are already enabled:
+
+1. SiFive UART Driver.
+2. SiFive PRCI Driver for clock.
+3. Cadence MACB ethernet driver for networking support.
+4. SiFive SPI Driver.
+5. MMC SPI Driver for MMC/SD support.
+
+Booting from uSD using U-Boot SPL
+---------------------------------
+
+Building
+--------
+
+Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
+cloned and built for FU740 as below:
+
+.. code-block:: console
+
+ git clone https://github.com/riscv/opensbi.git
+ cd opensbi
+ make PLATFORM=generic
+ export OPENSBI=<path to opensbi/build/platform/generic/firmware/fw_dynamic.bin>
+
+Now build the U-Boot SPL and U-Boot proper
+
+.. code-block:: console
+
+ cd <U-Boot-dir>
+ make sifive_unmatched_defconfig
+ make
+
+This will generate spl/u-boot-spl.bin and u-boot.itb
+
+
+Flashing
+--------
+
+ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
+5B193300-FC78-40CD-8002-E86C45580B47
+
+U-Boot SPL expects u-boot.itb from a partition with GUID
+type 2E54B353-1271-4842-806F-E436D6AF6985
+
+u-boot.itb is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
+device tree blob (hifive-unmatched-a00.dtb)
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: none
+
+ # sudo sgdisk -g --clear -a 1 \
+ > --new=1:34:2081 --change-name=1:spl --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
+ > --new=2:2082:10273 --change-name=2:uboot --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
+ > --new=3:16384:282623 --change-name=3:boot --typecode=3:0x0700 \
+ > --new=4:286720:13918207 --change-name=4:root --typecode=4:0x8300 \
+ > /dev/sdb
+
+Copy linux Image.gz and hifive-unmatched-a00.dtb to boot partition
+
+.. code-block:: none
+
+ sudo mkfs.vfat /dev/sdb3
+ sudo mkfs.ext4 /dev/sdb4
+
+ sudo mount /dev/sdb3 /media/sdb3
+ sudo cp Image.gz hifive-unmatched-a00.dtb /media/sdb3/
+
+Program the SD card
+
+.. code-block:: none
+
+ sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
+ sudo dd if=u-boot.itb of=/dev/sda seek=2082
+
+Booting
+-------
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+
+Loading the kernel and dtb
+
+.. code-block:: none
+
+ fatload mmc 0:3 ${kernel_addr_r} Image.gz
+ fatload mmc 0:3 ${fdt_addr_r} hifive-unmatched-a00.dtb
+ booti ${kernel_addr_r} - ${fdt_addr_r}
+
+
+Sample boot log from HiFive Unmatched board
+-------------------------------------------
+
+.. code-block:: none
+
+ U-Boot SPL 2021.04-rc4-00009-g7d70643cc3-dirty (Mar 16 2021 - 18:03:14 +0800)
+ Trying to boot from MMC1
+
+ U-Boot 2021.04-rc4-00009-g7d70643cc3-dirty (Mar 16 2021 - 18:03:14 +0800)
+
+ CPU: rv64imafdc
+ Model: SiFive HiFive Unmatched A00
+ DRAM: 16 GiB
+ MMC: spi@10050000:mmc@0: 0
+ In: serial@10010000
+ Out: serial@10010000
+ Err: serial@10010000
+ Model: SiFive HiFive Unmatched A00
+ Net:
+ Error: ethernet@10090000 address not set.
+ No ethernet found.
+
+ Hit any key to stop autoboot: 0
+ PCIe Link up, Gen1
+
+ Device 0: Vendor: 0x126f Rev: S1111A0L Prod: AA000000000000001995
+ Type: Hard Disk
+ Capacity: 488386.3 MB = 476.9 GB (1000215216 x 512)
+ ... is now current device
+ Scanning nvme 0:1...
+ libfdt fdt_check_header(): FDT_ERR_BADMAGIC
+ Scanning disk mmc@0.blk...
+ ** Unrecognized filesystem type **
+ ** Unrecognized filesystem type **
+ Scanning disk nvme#0.blk#0...
+ Found 8 disks
+ No EFI system partition
+
+ Error: ethernet@10090000 address not set.
+ BootOrder not defined
+ EFI boot manager: Cannot load any image
+ starting USB...
+ Bus xhci_pci: Register 4000840 NbrPorts 4
+ Starting the controller
+ USB XHCI 1.00
+ scanning bus xhci_pci for devices... 3 USB Device(s) found
+ scanning usb for storage devices... 0 Storage Device(s) found
+
+ Device 0: unknown device
+ switch to partitions #0, OK
+ mmc0 is current device
+ Scanning mmc 0:3...
+ Found /extlinux/extlinux.conf
+ Retrieving file: /extlinux/extlinux.conf
+ 205 bytes read in 9 ms (21.5 KiB/s)
+ 1: OpenEmbedded-SiFive-HiFive-Unmatched
+ Retrieving file: /Image.gz
+ 7225919 bytes read in 4734 ms (1.5 MiB/s)
+ append: root=/dev/mmcblk0p4 rootfstype=ext4 rootwait console=ttySIF0,115200 earlycon=sbi
+ Retrieving file: /hifive-unmatched-a00.dtb
+ 10445 bytes read in 13 ms (784.2 KiB/s)
+ Uncompressing Kernel Image
+ Moving Image from 0x84000000 to 0x80200000, end=81629000
+ ## Flattened Device Tree blob at 88000000
+ Booting using the fdt blob at 0x88000000
+ Using Device Tree in place at 0000000088000000, end 00000000880058cc
+
+ Starting kernel ...
+
+ [ 0.000000] Linux version 5.10.15 (oe-user@oe-host) (riscv64-oe-linux-gcc (GCC) 10.2.0, GNU ld (GNU Binutils) 2.35.0.201
+ [ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+ [ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+ [ 0.000000] printk: bootconsole [sbi0] enabled
+ [ 0.000000] efi: UEFI not found.
+ [ 0.000000] Zone ranges:
+ [ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000ffffffff]
+ [ 0.000000] Normal [mem 0x0000000100000000-0x000000027fffffff]
+ [ 0.000000] Movable zone start for each node
+ [ 0.000000] Early memory node ranges
+ [ 0.000000] node 0: [mem 0x0000000080200000-0x000000027fffffff]
+ [ 0.000000] Zeroed struct page in unavailable ranges: 512 pages
+ [ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
+ [ 0.000000] software IO TLB: mapped [mem 0x00000000fbfff000-0x00000000fffff000] (64MB)
+ [ 0.000000] SBI specification v0.3 detected
+ [ 0.000000] SBI implementation ID=0x1 Version=0x9
+ [ 0.000000] SBI v0.2 TIME extension detected
+ [ 0.000000] SBI v0.2 IPI extension detected
+ [ 0.000000] SBI v0.2 RFENCE extension detected
+ [ 0.000000] SBI v0.2 HSM extension detected
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] riscv: ISA extensions acdfim
+ [ 0.000000] riscv: ELF capabilities acdfim
+ [ 0.000000] percpu: Embedded 26 pages/cpu s66904 r8192 d31400 u106496
+ [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2067975
+ [ 0.000000] Kernel command line: root=/dev/mmcblk0p4 rootfstype=ext4 rootwait console=ttySIF0,115200 earlycon=sbi
+ [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
+ [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
+ [ 0.000000] Sorting __ex_table...
+ [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+ [ 0.000000] Memory: 8155880K/8386560K available (8490K kernel code, 5515K rwdata, 4096K rodata, 285K init, 383K bss, 23)
+ [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+ [ 0.000000] rcu: Hierarchical RCU implementation.
+ [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+ [ 0.000000] Tracing variant of Tasks RCU enabled.
+ [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+ [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+ [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
+ [ 0.000000] CPU with hartid=0 is not available
+ [ 0.000000] riscv-intc: unable to find hart id for /cpus/cpu@0/interrupt-controller
+ [ 0.000000] riscv-intc: 64 local interrupts mapped
+ [ 0.000000] plic: interrupt-controller@c000000: mapped 69 interrupts with 4 handlers for 9 contexts.
+ [ 0.000000] random: get_random_bytes called from 0xffffffe000002a6a with crng_init=0
+ [ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
+ [ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 352636161696s
+ [ 0.000007] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
+ [ 0.008626] Console: colour dummy device 80x25
+ [ 0.013049] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000)
+ [ 0.023115] pid_max: default: 32768 minimum: 301
+ [ 0.028423] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+ [ 0.035919] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+ [ 0.045957] rcu: Hierarchical SRCU implementation.
+ [ 0.050393] EFI services will not be available.
+ [ 0.055132] smp: Bringing up secondary CPUs ...
+ [ 0.061824] smp: Brought up 1 node, 4 CPUs
+ [ 0.067458] devtmpfs: initialized
+ [ 0.072700] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+ [ 0.081789] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+ [ 0.089738] NET: Registered protocol family 16
+ [ 0.093999] thermal_sys: Registered thermal governor 'step_wise'
+ [ 0.109208] iommu: Default domain type: Translated
+ [ 0.119694] vgaarb: loaded
+ [ 0.122571] SCSI subsystem initialized
+ [ 0.126499] usbcore: registered new interface driver usbfs
+ [ 0.131686] usbcore: registered new interface driver hub
+ [ 0.137071] usbcore: registered new device driver usb
+ [ 0.142286] EDAC MC: Ver: 3.0.0
+ [ 0.145760] Advanced Linux Sound Architecture Driver Initialized.
+ [ 0.152205] clocksource: Switched to clocksource riscv_clocksource
+ [ 1.046286] VFS: Disk quotas dquot_6.6.0
+ [ 1.049651] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
+ [ 1.062844] NET: Registered protocol family 2
+ [ 1.067172] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
+ [ 1.075455] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
+ [ 1.085428] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
+ [ 1.096548] TCP: Hash tables configured (established 65536 bind 65536)
+ [ 1.103043] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
+ [ 1.109879] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
+ [ 1.117413] NET: Registered protocol family 1
+ [ 1.121881] RPC: Registered named UNIX socket transport module.
+ [ 1.127139] RPC: Registered udp transport module.
+ [ 1.131901] RPC: Registered tcp transport module.
+ [ 1.136677] RPC: Registered tcp NFSv4.1 backchannel transport module.
+ [ 1.143194] PCI: CLS 0 bytes, default 64
+ [ 1.148359] Initialise system trusted keyrings
+ [ 1.152364] workingset: timestamp_bits=62 max_order=21 bucket_order=0
+ [ 1.165382] NFS: Registering the id_resolver key type
+ [ 1.169781] Key type id_resolver registered
+ [ 1.174011] Key type id_legacy registered
+ [ 1.178179] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+ [ 1.184874] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
+ [ 1.192453] 9p: Installing v9fs 9p2000 file system support
+ [ 1.198116] NET: Registered protocol family 38
+ [ 1.201886] Key type asymmetric registered
+ [ 1.206046] Asymmetric key parser 'x509' registered
+ [ 1.211029] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
+ [ 1.218468] io scheduler mq-deadline registered
+ [ 1.223072] io scheduler kyber registered
+ [ 1.228803] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
+ [ 1.235017] fu740-pcie e00000000.pcie: FPGA PCIE PROBE
+ [ 1.281706] fu740-pcie e00000000.pcie: PCIE-PERSTN is GPIO 504
+ [ 1.286922] fu740-pcie e00000000.pcie: PWREN is GPIO 501
+ [ 1.292377] fu740-pcie e00000000.pcie: host bridge /soc/pcie@e00000000 ranges:
+ [ 1.299603] fu740-pcie e00000000.pcie: IO 0x0060080000..0x006008ffff -> 0x0060080000
+ [ 1.307922] fu740-pcie e00000000.pcie: MEM 0x0060090000..0x0070ffffff -> 0x0060090000
+ [ 1.316244] fu740-pcie e00000000.pcie: MEM 0x2000000000..0x3fffffffff -> 0x2000000000
+ [ 1.432223] fu740-pcie e00000000.pcie: PWREN enabling
+ [ 1.436607] fu740-pcie e00000000.pcie: PWREN valid
+ [ 1.560226] fu740-pcie e00000000.pcie: invalid resource
+ [ 1.664802] fu740-pcie e00000000.pcie: Link up
+ [ 1.768582] fu740-pcie e00000000.pcie: Link up
+ [ 1.872369] fu740-pcie e00000000.pcie: Link up
+ [ 1.876116] fu740-pcie e00000000.pcie: Link up, Gen3
+ [ 1.881352] fu740-pcie e00000000.pcie: PCI host bridge to bus 0000:00
+ [ 1.887700] pci_bus 0000:00: root bus resource [bus 00-ff]
+ [ 1.893247] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] (bus address [0x60080000-0x6008ffff])
+ [ 1.902807] pci_bus 0000:00: root bus resource [mem 0x60090000-0x70ffffff]
+ [ 1.909748] pci_bus 0000:00: root bus resource [mem 0x2000000000-0x3fffffffff pref]
+ [ 1.917517] pci 0000:00:00.0: [f15e:0000] type 01 class 0x060400
+ [ 1.923569] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff]
+ [ 1.929902] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref]
+ [ 1.936723] pci 0000:00:00.0: supports D1
+ [ 1.940755] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
+ [ 1.947619] pci 0000:01:00.0: [1b21:2824] type 01 class 0x060400
+ [ 1.953052] pci 0000:01:00.0: enabling Extended Tags
+ [ 1.958165] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
+ [ 1.976890] pci 0000:01:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+ [ 1.984425] pci 0000:02:00.0: [1b21:2824] type 01 class 0x060400
+ [ 1.990396] pci 0000:02:00.0: enabling Extended Tags
+ [ 1.995509] pci 0000:02:00.0: PME# supported from D0 D3hot D3cold
+ [ 2.001938] pci 0000:02:02.0: [1b21:2824] type 01 class 0x060400
+ [ 2.007682] pci 0000:02:02.0: enabling Extended Tags
+ [ 2.012793] pci 0000:02:02.0: PME# supported from D0 D3hot D3cold
+ [ 2.019167] pci 0000:02:03.0: [1b21:2824] type 01 class 0x060400
+ [ 2.024966] pci 0000:02:03.0: enabling Extended Tags
+ [ 2.030075] pci 0000:02:03.0: PME# supported from D0 D3hot D3cold
+ [ 2.036468] pci 0000:02:04.0: [1b21:2824] type 01 class 0x060400
+ [ 2.042250] pci 0000:02:04.0: enabling Extended Tags
+ [ 2.047359] pci 0000:02:04.0: PME# supported from D0 D3hot D3cold
+ [ 2.053811] pci 0000:02:08.0: [1b21:2824] type 01 class 0x060400
+ [ 2.059534] pci 0000:02:08.0: enabling Extended Tags
+ [ 2.064647] pci 0000:02:08.0: PME# supported from D0 D3hot D3cold
+ [ 2.071499] pci 0000:02:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+ [ 2.078837] pci 0000:02:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+ [ 2.086911] pci 0000:02:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+ [ 2.094987] pci 0000:02:04.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+ [ 2.103075] pci 0000:02:08.0: bridge configuration invalid ([bus 00-00]), reconfiguring
+ [ 2.111901] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
+ [ 2.118031] pci 0000:04:00.0: [1b21:1142] type 00 class 0x0c0330
+ [ 2.123968] pci 0000:04:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]
+ [ 2.131038] pci 0000:04:00.0: PME# supported from D3cold
+ [ 2.148888] pci_bus 0000:04: busn_res: [bus 04-ff] end is updated to 04
+ [ 2.155588] pci_bus 0000:05: busn_res: [bus 05-ff] end is updated to 05
+ [ 2.162286] pci_bus 0000:06: busn_res: [bus 06-ff] end is updated to 06
+ [ 2.168408] pci 0000:07:00.0: [126f:2263] type 00 class 0x010802
+ [ 2.174351] pci 0000:07:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit]
+ [ 2.192890] pci_bus 0000:07: busn_res: [bus 07-ff] end is updated to 07
+ [ 2.198837] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 07
+ [ 2.205522] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 07
+ [ 2.212241] pci 0000:00:00.0: BAR 0: assigned [mem 0x60100000-0x601fffff]
+ [ 2.219067] pci 0000:00:00.0: BAR 14: assigned [mem 0x60200000-0x603fffff]
+ [ 2.226010] pci 0000:00:00.0: BAR 6: assigned [mem 0x60090000-0x6009ffff pref]
+ [ 2.233308] pci 0000:01:00.0: BAR 14: assigned [mem 0x60200000-0x603fffff]
+ [ 2.240259] pci 0000:02:02.0: BAR 14: assigned [mem 0x60200000-0x602fffff]
+ [ 2.247203] pci 0000:02:08.0: BAR 14: assigned [mem 0x60300000-0x603fffff]
+ [ 2.254150] pci 0000:02:00.0: PCI bridge to [bus 03]
+ [ 2.259217] pci 0000:04:00.0: BAR 0: assigned [mem 0x60200000-0x60207fff 64bit]
+ [ 2.266594] pci 0000:02:02.0: PCI bridge to [bus 04]
+ [ 2.271615] pci 0000:02:02.0: bridge window [mem 0x60200000-0x602fffff]
+ [ 2.278485] pci 0000:02:03.0: PCI bridge to [bus 05]
+ [ 2.283529] pci 0000:02:04.0: PCI bridge to [bus 06]
+ [ 2.288572] pci 0000:07:00.0: BAR 0: assigned [mem 0x60300000-0x60303fff 64bit]
+ [ 2.295952] pci 0000:02:08.0: PCI bridge to [bus 07]
+ [ 2.300973] pci 0000:02:08.0: bridge window [mem 0x60300000-0x603fffff]
+ [ 2.307842] pci 0000:01:00.0: PCI bridge to [bus 02-07]
+ [ 2.313133] pci 0000:01:00.0: bridge window [mem 0x60200000-0x603fffff]
+ [ 2.320009] pci 0000:00:00.0: PCI bridge to [bus 01-07]
+ [ 2.325288] pci 0000:00:00.0: bridge window [mem 0x60200000-0x603fffff]
+ [ 2.332808] pcieport 0000:00:00.0: AER: enabled with IRQ 51
+ [ 2.337946] pcieport 0000:01:00.0: enabling device (0000 -> 0002)
+ [ 2.344786] pcieport 0000:02:02.0: enabling device (0000 -> 0002)
+ [ 2.351328] pcieport 0000:02:08.0: enabling device (0000 -> 0002)
+ [ 2.357091] pci 0000:04:00.0: enabling device (0000 -> 0002)
+ [ 2.362751] switchtec: loaded.
+ [ 2.365933] L2CACHE: DataError @ 0x00000003.00964470
+ [ 2.365992] L2CACHE: No. of Banks in the cache: 4
+ [ 2.375414] L2CACHE: No. of ways per bank: 16
+ [ 2.379846] L2CACHE: Sets per bank: 512
+ [ 2.383751] L2CACHE: Bytes per cache block: 64
+ [ 2.388267] L2CACHE: Index of the largest way enabled: 15
+ [ 2.434865] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+ [ 2.441695] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 1, base_baud = 115200) is a SiFive UART v0
+ [ 2.450625] printk: console [ttySIF0] enabled
+ [ 2.450625] printk: console [ttySIF0] enabled
+ [ 2.459360] printk: bootconsole [sbi0] disabled
+ [ 2.459360] printk: bootconsole [sbi0] disabled
+ [ 2.468824] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 2, base_baud = 115200) is a SiFive UART v0
+ [ 2.493853] loop: module loaded
+ [ 2.526475] nvme nvme0: pci function 0000:07:00.0
+ [ 2.530852] nvme 0000:07:00.0: enabling device (0000 -> 0002)
+ [ 2.537716] Rounding down aligned max_sectors from 4294967295 to 4294967288
+ [ 2.544470] db_root: cannot open: /etc/target
+ [ 2.545926] nvme nvme0: allocated 64 MiB host memory buffer.
+ [ 2.549020] sifive_spi 10040000.spi: mapped; irq=4, cs=1
+ [ 2.559941] spi-nor spi0.0: is25wp256 (32768 Kbytes)
+ [ 2.566431] sifive_spi 10050000.spi: mapped; irq=6, cs=1
+ [ 2.566707] nvme nvme0: 4/0/0 default/read/poll queues
+ [ 2.571935] libphy: Fixed MDIO Bus: probed
+ [ 2.580950] macb 10090000.ethernet: Registered clk switch 'sifive-gemgxl-mgmt'
+ [ 2.587536] macb 10090000.ethernet: invalid hw address, using random
+ [ 2.588100] nvme0n1: p1 p2
+ [ 2.593875] BEU: Load or Store TILINK BUS ERR occurred
+ [ 2.594342] libphy: MACB_mii_bus: probed
+ [ 2.599312] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 7 (5e:57:b8:ab:24:4a)
+ [ 2.615501] e1000e: Intel(R) PRO/1000 Network Driver
+ [ 2.620251] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
+ [ 2.626463] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+ [ 2.632684] ehci-pci: EHCI PCI platform driver
+ [ 2.637144] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
+ [ 2.643273] ohci-pci: OHCI PCI platform driver
+ [ 2.647731] uhci_hcd: USB Universal Host Controller Interface driver
+ [ 2.654315] xhci_hcd 0000:04:00.0: xHCI Host Controller
+ [ 2.659450] xhci_hcd 0000:04:00.0: new USB bus registered, assigned bus number 1
+ [ 2.807373] xhci_hcd 0000:04:00.0: hcc params 0x0200e081 hci version 0x100 quirks 0x0000000010000410
+ [ 2.816609] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10
+ [ 2.824115] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+ [ 2.831312] usb usb1: Product: xHCI Host Controller
+ [ 2.836174] usb usb1: Manufacturer: Linux 5.10.15 xhci-hcd
+ [ 2.841652] usb usb1: SerialNumber: 0000:04:00.0
+ [ 2.846639] hub 1-0:1.0: USB hub found
+ [ 2.850037] hub 1-0:1.0: 2 ports detected
+ [ 2.854306] xhci_hcd 0000:04:00.0: xHCI Host Controller
+ [ 2.859335] xhci_hcd 0000:04:00.0: new USB bus registered, assigned bus number 2
+ [ 2.866599] xhci_hcd 0000:04:00.0: Host supports USB 3.0 SuperSpeed
+ [ 2.873638] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
+ [ 2.881074] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.10
+ [ 2.889212] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+ [ 2.896422] usb usb2: Product: xHCI Host Controller
+ [ 2.901282] usb usb2: Manufacturer: Linux 5.10.15 xhci-hcd
+ [ 2.906752] usb usb2: SerialNumber: 0000:04:00.0
+ [ 2.911671] hub 2-0:1.0: USB hub found
+ [ 2.915130] hub 2-0:1.0: 2 ports detected
+ [ 2.919486] usbcore: registered new interface driver usb-storage
+ [ 2.925212] usbcore: registered new interface driver usbserial_generic
+ [ 2.931620] usbserial: USB Serial support registered for generic
+ [ 2.937771] mousedev: PS/2 mouse device common for all mice
+ [ 2.943220] usbcore: registered new interface driver usbtouchscreen
+ [ 2.949466] i2c /dev entries driver
+ [ 2.954218] lm90 0-004c: supply vcc not found, using dummy regulator
+ [ 2.961629] EDAC DEVICE0: Giving out device to module Sifive ECC Manager controller sifive_edac.0: DEV sifive_edac.0 (I)
+ [ 2.997874] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
+ [ 3.005138] ledtrig-cpu: registered to indicate activity on CPUs
+ [ 3.010980] usbcore: registered new interface driver usbhid
+ [ 3.016407] usbhid: USB HID core driver
+ [ 3.020540] usbcore: registered new interface driver snd-usb-audio
+ [ 3.027209] NET: Registered protocol family 10
+ [ 3.031878] Segment Routing with IPv6
+ [ 3.034864] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+ [ 3.041232] NET: Registered protocol family 17
+ [ 3.045324] 9pnet: Installing 9P2000 support
+ [ 3.049397] Key type dns_resolver registered
+ [ 3.053786] Loading compiled-in X.509 certificates
+ [ 3.059729] ALSA device list:
+ [ 3.061943] No soundcards found.
+ [ 3.066057] Waiting for root device /dev/mmcblk0p4...
+ [ 3.077319] mmc0: host does not support reading read-only switch, assuming write-enable
+ [ 3.084564] mmc0: new SDHC card on SPI
+ [ 3.089699] mmcblk0: mmc0:0000 SD32G 29.7 GiB
+ [ 3.126488] GPT:Primary header thinks Alt. header is not at the end of the disk.
+ [ 3.133144] GPT:13918241 != 62333951
+ [ 3.136679] GPT:Alternate GPT header not at the end of the disk.
+ [ 3.142673] GPT:13918241 != 62333951
+ [ 3.146231] GPT: Use GNU Parted to correct GPT errors.
+ [ 3.151398] mmcblk0: p1 p2 p3 p4
+ [ 3.212226] usb 1-2: new high-speed USB device number 2 using xhci_hcd
+ [ 3.258310] EXT4-fs (mmcblk0p4): INFO: recovery required on readonly filesystem
+ [ 3.264855] EXT4-fs (mmcblk0p4): write access will be enabled during recovery
+ [ 3.458247] usb 1-2: New USB device found, idVendor=174c, idProduct=2074, bcdDevice= 0.01
+ [ 3.465662] usb 1-2: New USB device strings: Mfr=2, Product=3, SerialNumber=1
+ [ 3.472775] usb 1-2: Product: AS2107
+ [ 3.476336] usb 1-2: Manufacturer: ASMedia
+ [ 3.480419] usb 1-2: SerialNumber: USB2.0 Hub
+ [ 3.533583] EXT4-fs (mmcblk0p4): recovery complete
+ [ 3.543756] EXT4-fs (mmcblk0p4): mounted filesystem with ordered data mode. Opts: (null)
+ [ 3.551132] VFS: Mounted root (ext4 filesystem) readonly on device 179:4.
+ [ 3.554682] hub 1-2:1.0: USB hub found
+ [ 3.561105] devtmpfs: mounted
+ [ 3.561778] hub 1-2:1.0: 4 ports detected
+ [ 3.565546] Freeing unused kernel memory: 284K
+ [ 3.572964] Kernel memory protection not selected by kernel config.
+ [ 3.579225] Run /sbin/init as init process
+ [ 3.613136] usb 2-2: new SuperSpeed Gen 1 USB device number 2 using xhci_hcd
+ [ 3.643539] usb 2-2: New USB device found, idVendor=174c, idProduct=3074, bcdDevice= 0.01
+ [ 3.650948] usb 2-2: New USB device strings: Mfr=2, Product=3, SerialNumber=1
+ [ 3.658072] usb 2-2: Product: AS2107
+ [ 3.661630] usb 2-2: Manufacturer: ASMedia
+ [ 3.665709] usb 2-2: SerialNumber: USB2.0 Hub
+ [ 3.762380] hub 2-2:1.0: USB hub found
+ [ 3.766074] hub 2-2:1.0: 4 ports detected
+ [ 7.487226] systemd[1]: System time before build time, advancing clock.
+ [ 7.788093] systemd[1]: systemd 247.2+ running in system mode. (+PAM -AUDIT -SELINUX +IMA -APPARMOR -SMACK +SYSVINIT +U)
+ [ 7.809694] systemd[1]: Detected architecture riscv64.
+
+ Welcome to OpenEmbedded nodistro.0!
+
+ [ 7.832648] systemd[1]: Set hostname to <unmatched>.
+ [ 9.397499] systemd[1]: Queued start job for default target Multi-User System.
+ [ 9.408518] random: systemd: uninitialized urandom read (16 bytes read)
+ [ 9.429329] systemd[1]: Created slice system-getty.slice.
+ [ OK ] Created slice system-getty.slice.
+ [ 9.440400] random: systemd: uninitialized urandom read (16 bytes read)
+ [ 9.447086] systemd[1]: Created slice system-modprobe.slice.
+ [ OK ] Created slice system-modprobe.slice.
+ [ 9.458480] random: systemd: uninitialized urandom read (16 bytes read)
+ [ 9.465436] systemd[1]: Created slice system-serial\x2dgetty.slice.
+ [ OK ] Created slice system-serial\x2dgetty.slice.
+ [ 9.478594] systemd[1]: Created slice User and Session Slice.
+ [ OK ] Created slice User and Session Slice.
+ [ 9.490225] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
+ [ OK ] Started Dispatch Password ��…ts to Console Directory Watch.
+ [ 9.506407] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
+ [ OK ] Started Forward Password R��…uests to Wall Directory Watch.
+ [ 9.522312] systemd[1]: Reached target Paths.
+ [ OK ] Reached target Paths.
+ [ 9.531078] systemd[1]: Reached target Remote File Systems.
+ [ OK ] Reached target Remote File Systems.
+ [ 9.542855] systemd[1]: Reached target Slices.
+ [ OK ] Reached target Slices.
+ [ 9.552712] systemd[1]: Reached target Swap.
+ [ OK ] Reached target Swap.
+ [ 9.561566] systemd[1]: Listening on initctl Compatibility Named Pipe.
+ [ OK ] Listening on initctl Compatibility Named Pipe.
+ [ 9.578686] systemd[1]: Condition check resulted in Journal Audit Socket being skipped.
+ [ 9.586545] systemd[1]: Listening on Journal Socket (/dev/log).
+ [ OK ] Listening on Journal Socket (/dev/log).
+
+ [snip]
+
+ [ OK ] Reached target System Time Synchronized.
+ [ OK ] Reached target Timers.
+ [ OK ] Listening on D-Bus System Message Bus Socket.
+ [ OK ] Reached target Sockets.
+ [ OK ] Reached target Basic System.
+ [ OK ] Started D-Bus System Message Bus.
+ Starting User Login Management...
+ Starting Permit User Sessions...
+ [ OK ] Started Xinetd A Powerful Replacement For Inetd.
+ [ OK ] Finished Permit User Sessions.
+ [ OK ] Started Getty on tty1.
+ [ OK ] Started Serial Getty on hvc0.
+ [ OK ] Started Serial Getty on ttySIF0.
+ [ OK ] Reached target Login Prompts.
+ [ OK ] Started User Login Management.
+ [ OK ] Reached target Multi-User System.
+ Starting Update UTMP about System Runlevel Changes...
+ [ OK ] Finished Update UTMP about System Runlevel Changes.
+
+ OpenEmbedded nodistro.0 unmatched hvc0
+
+ unmatched login:
+ OpenEmbedded nodistro.0 unmatched ttySIF0
+
+ unmatched login:
diff --git a/doc/develop/driver-model/index.rst b/doc/develop/driver-model/index.rst
index fd4575d..10a7625 100644
--- a/doc/develop/driver-model/index.rst
+++ b/doc/develop/driver-model/index.rst
@@ -27,3 +27,4 @@
soc-framework
spi-howto
usb-info
+ virtio
diff --git a/doc/README.virtio b/doc/develop/driver-model/virtio.rst
similarity index 85%
rename from doc/README.virtio
rename to doc/develop/driver-model/virtio.rst
index d3652f2..8ac9c94 100644
--- a/doc/README.virtio
+++ b/doc/develop/driver-model/virtio.rst
@@ -1,11 +1,10 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bin Meng <bmeng.cn@gmail.com>
VirtIO Support
==============
-This document describes the information about U-Boot support for VirtIO [1]
+This document describes the information about U-Boot support for VirtIO_
devices, including supported boards, build instructions, driver details etc.
What's VirtIO?
@@ -15,7 +14,7 @@
and cooperates with the hypervisor. This enables guests to get high performance
network and disk operations, and gives most of the performance benefits of
paravirtualization. In the U-Boot case, the guest is U-Boot itself, while the
-virtual environment are normally QEMU [2] targets like ARM, RISC-V and x86.
+virtual environment are normally QEMU_ targets like ARM, RISC-V and x86.
Status
------
@@ -49,6 +48,8 @@
For example, we can do the following with the CROSS_COMPILE environment
variable being properly set to a working toolchain for ARM:
+.. code-block:: bash
+
$ make qemu_arm_defconfig
$ make
@@ -56,11 +57,13 @@
MMIO and PCI buses. In this case, you can enable the PCI transport driver
from 'make menuconfig':
-Device Drivers --->
- ...
- VirtIO Drivers --->
- ...
- [*] PCI driver for virtio devices
+.. code-block:: none
+
+ Device Drivers --->
+ ...
+ VirtIO Drivers --->
+ ...
+ [*] PCI driver for virtio devices
Other drivers are at the same location and can be tuned to suit the needs.
@@ -74,6 +77,8 @@
The following QEMU command line is used to get U-Boot up and running with
VirtIO net and block devices on ARM.
+.. code-block:: bash
+
$ qemu-system-arm -nographic -machine virt -bios u-boot.bin \
-netdev tap,ifname=tap0,id=net0 \
-device virtio-net-device,netdev=net0 \
@@ -82,6 +87,8 @@
On x86, command is slightly different to create PCI VirtIO devices.
+.. code-block:: bash
+
$ qemu-system-i386 -nographic -bios u-boot.rom \
-netdev tap,ifname=tap0,id=net0 \
-device virtio-net-pci,netdev=net0 \
@@ -93,6 +100,8 @@
For example, the following commnad creates 3 VirtIO devices, with 1 on MMIO
and 2 on PCI bus.
+.. code-block:: bash
+
$ qemu-system-arm -nographic -machine virt -bios u-boot.bin \
-netdev tap,ifname=tap0,id=net0 \
-device virtio-net-pci,netdev=net0 \
@@ -104,6 +113,8 @@
By default QEMU creates VirtIO legacy devices by default. To create non-legacy
(aka modern) devices, pass additional device property/value pairs like below:
+.. code-block:: bash
+
$ qemu-system-i386 -nographic -bios u-boot.rom \
-netdev tap,ifname=tap0,id=net0 \
-device virtio-net-pci,netdev=net0,disable-legacy=true,disable-modern=false \
@@ -112,6 +123,8 @@
A 'virtio' command is provided in U-Boot shell.
+.. code-block:: none
+
=> virtio
virtio - virtio block devices sub-system
@@ -127,10 +140,14 @@
To probe all the VirtIO devices, type:
+.. code-block:: none
+
=> virtio scan
Then we can show the connected block device details by:
+.. code-block:: none
+
=> virtio info
Device 0: QEMU VirtIO Block Device
Type: Hard Disk
@@ -138,6 +155,8 @@
And list the directories and files on the disk by:
+.. code-block:: none
+
=> ls virtio 0 /
<DIR> 4096 .
<DIR> 4096 ..
@@ -167,6 +186,8 @@
----------------
There are 3 level of drivers in the VirtIO driver family.
+.. code-block:: none
+
+---------------------------------------+
| virtio device drivers |
| +-------------+ +------------+ |
@@ -199,20 +220,26 @@
virtio device driver to call. These ops APIs's parameter is designed to remind
the caller to pass the correct 'struct udevice' id of the virtio device, eg:
-int virtio_get_status(struct udevice *vdev, u8 *status)
+.. code-block:: C
+
+ int virtio_get_status(struct udevice *vdev, u8 *status)
So the parameter 'vdev' indicates the device should be the real virtio device.
But we also have an API like:
-struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num,
- unsigned int vring_align,
- struct udevice *udev)
+.. code-block:: C
+
+ struct virtqueue *vring_create_virtqueue(unsigned int index, unsigned int num,
+ unsigned int vring_align,
+ struct udevice *udev)
Here the parameter 'udev' indicates the device should be the transport device.
Similar naming is applied in other functions that are even not APIs, eg:
-static int virtio_uclass_post_probe(struct udevice *udev)
-static int virtio_uclass_child_pre_probe(struct udevice *vdev)
+.. code-block:: C
+
+ static int virtio_uclass_post_probe(struct udevice *udev)
+ static int virtio_uclass_child_pre_probe(struct udevice *vdev)
So it's easy to tell which device these functions are operating on.
@@ -223,20 +250,29 @@
please follow the guideline below.
1. add new device ID in virtio.h
-#define VIRTIO_ID_XXX X
+
+.. code-block:: C
+
+ #define VIRTIO_ID_XXX X
2. update VIRTIO_ID_MAX_NUM to be the largest device ID plus 1
3. add new driver name string in virtio.h
-#define VIRTIO_XXX_DRV_NAME "virtio-xxx"
+
+.. code-block:: C
+
+ #define VIRTIO_XXX_DRV_NAME "virtio-xxx"
4. create a new driver with name set to the name string above
-U_BOOT_DRIVER(virtio_xxx) = {
- .name = VIRTIO_XXX_DRV_NAME,
- ...
- .remove = virtio_reset,
- .flags = DM_FLAG_ACTIVE_DMA,
-}
+
+.. code-block:: C
+
+ U_BOOT_DRIVER(virtio_xxx) = {
+ .name = VIRTIO_XXX_DRV_NAME,
+ ...
+ .remove = virtio_reset,
+ .flags = DM_FLAG_ACTIVE_DMA,
+ }
Note the driver needs to provide the remove method and normally this can be
hooked to virtio_reset(). The driver flags should contain DM_FLAG_ACTIVE_DMA
@@ -247,7 +283,5 @@
6. do funny stuff with the driver
-References
-----------
-[1] http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf
-[2] https://www.qemu.org
+.. _VirtIO: http://docs.oasis-open.org/virtio/virtio/v1.0/virtio-v1.0.pdf
+.. _QEMU: https://www.qemu.org
diff --git a/doc/develop/logging.rst b/doc/develop/logging.rst
index f4e9250..51095b0 100644
--- a/doc/develop/logging.rst
+++ b/doc/develop/logging.rst
@@ -52,6 +52,10 @@
The above have SPL and TPL versions also, e.g. CONFIG_SPL_LOG_MAX_LEVEL and
CONFIG_TPL_LOG_MAX_LEVEL.
+If logging is disabled, the default behaviour is to output any message at
+level LOGL_INFO and below. If logging is disabled and DEBUG is defined (at
+the very top of a C file) then any message at LOGL_DEBUG will be written.
+
Temporary logging within a single file
--------------------------------------
@@ -291,8 +295,6 @@
Convert debug() statements in the code to log() statements
-Support making printf() emit log statements at L_INFO level
-
Convert error() statements in the code to log() statements
Figure out what to do with BUG(), BUG_ON() and warn_non_spl()
diff --git a/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt
new file mode 100644
index 0000000..0217341
--- /dev/null
+++ b/doc/device-tree-bindings/firmware/ti,j721e-dm-sci.txt
@@ -0,0 +1,32 @@
+Bindings for Texas Instruments System Control Interface (TI-SCI) Message
+Protocol for Device Manager(DM) to TI Foundational Security(TIFS)
+Firmware communication
+
+Required properties:
+--------------------
+- compatible: should be "ti,j721e-dm-sci"
+- mbox-names:
+ "rx" - Mailbox corresponding to receive path
+ "tx" - Mailbox corresponding to transmit path
+
+- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes
+ property should contain a phandle to the mailbox controller device
+ node and an args specifier that will be the phandle to the intended
+ sub-mailbox child node to be used for communication.
+
+- ti,host-id: Host ID to use for communication.
+
+Optional Properties:
+--------------------
+- ti,secure-host: If the host is defined as secure.
+
+Example:
+--------
+ dm_tifs: dm-tifs {
+ compatible = "ti,j721e-dm-sci";
+ ti,host-id = <3>;
+ ti,secure-host;
+ mbox-names = "rx", "tx";
+ mboxes= <&mcu_secproxy 21>,
+ <&mcu_secproxy 23>;
+ };
diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
index 873a0e7..c4cf26e 100644
--- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
+++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
@@ -9,7 +9,8 @@
==================
Required properties:
--------------------
-- compatible: Shall be: "ti,j721e-ddrss"
+- compatible: Shall be: "ti,j721e-ddrss" for j721e, j7200
+ "ti,am64-ddrss" for am642
- reg-names cfg - Map the controller configuration region
ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
- reg: Contains the register map per reg-names.
diff --git a/doc/device-tree-bindings/phy/mvebu_comphy.txt b/doc/device-tree-bindings/phy/mvebu_comphy.txt
new file mode 100644
index 0000000..65b8384
--- /dev/null
+++ b/doc/device-tree-bindings/phy/mvebu_comphy.txt
@@ -0,0 +1,68 @@
+Marvell COMPHY SerDes lane bindings
+=====================================
+
+The COMPHY node includes a description of the COMPHY SerDes lane configuration.
+The COMPHY driver initializes the MUX of the SerDes lanes, and powers up the SerDes
+by dependencies on the FDT blob configurations
+
+Mandatory properties:
+SoC specific:
+ - compatible:
+ The compatible should include "marvell,mvebu-comphy"
+ and the COMPHY per chip compatible:
+ "marvell,comphy-cp110" for CP110 available in Aramda70x0/80x0.
+ The COMPHY per chip used to set which MUX configuration to use, and COMPHY power-up revision.
+ - reg: Base address and size of the COMPHY and hpipe units.
+ - max-lanes: Maximum number of comphy lanes.
+ - mux-bitcount: Number of bits that are allocated for every MUX in the COMPHY-selector register.
+Board specific:
+ - PHY: Entry that include the configuration of the PHY.
+ Every PHY should have the below parameters:
+ - phy-type: the mode of the PHY
+ Possible modes located in include/dt-bindings/comphy/comphy_data.h
+ Optional properties:
+ - phy-speed: the speed of the PHY
+ Possible speeds values located in include/dt-bindings/comphy/comphy_data.h
+ - phy-invert: Polarity invert (COMPHY_POLARITY_TXD_INVERT/COMPHY_POLARITY_RXD_INVERT)
+ the possible bits under include/dt-bindings/comphy/comphy_data.h
+ - clk-src: Set the clock source of PCIe, if configured to PCIe clock output
+ This relevant for SerDes lane 5 only (by default, lane 4 is the clock source)
+ for Armada-7040 boards.
+ - endpoint: Optional boolean specifying this SerDes should be configured as PCIe endpoint.
+
+Example:
+ cpm_comphy: comphy@441000 {
+ compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110";
+ reg = <0x441000 0x8>, <0x120000 0x8>;
+ mux-bitcount = <4>;
+ max-lanes = <6>;
+
+ /*
+ * CP110 Serdes Configuration:
+ * Lane 0: SGMII1
+ * Lane 1: SATA 0
+ * Lane 2: USB HOST 0
+ * Lane 3: SATA1
+ * Lane 4: SFI (10G)
+ * Lane 5: SGMII2
+ */
+ phy0 {
+ phy-type = <COMPHY_TYPE_SGMII1>;
+ phy-speed = <COMPHY_SPEED_1_25G>;
+ };
+ phy1 {
+ phy-type = <COMPHY_TYPE_SATA0>;
+ };
+ phy2 {
+ phy-type = <COMPHY_TYPE_USB3_HOST0>;
+ };
+ phy3 {
+ phy-type = <COMPHY_TYPE_SATA1>;
+ };
+ phy4 {
+ phy-type = <COMPHY_TYPE_SFI>;
+ };
+ phy5 {
+ phy-type = <COMPHY_TYPE_SGMII2>;
+ };
+ };
diff --git a/doc/device-tree-bindings/sysinfo/gpio-sysinfo.txt b/doc/device-tree-bindings/sysinfo/gpio-sysinfo.txt
new file mode 100644
index 0000000..b5739d9
--- /dev/null
+++ b/doc/device-tree-bindings/sysinfo/gpio-sysinfo.txt
@@ -0,0 +1,37 @@
+GPIO-based Sysinfo device
+
+This binding describes several GPIOs which specify a board revision. Each GPIO
+forms a digit in a ternary revision number. This revision is then mapped to a
+name using the revisions and names properties.
+
+Each GPIO may be floating, pulled-up, or pulled-down, mapping to digits 2, 1,
+and 0, respectively. The first GPIO forms the least-significant digit of the
+revision. For example, consider the property
+
+ gpios = <&gpio 0>, <&gpio 1>, <&gpio 2>;
+
+If GPIO 0 is pulled-up, GPIO 1 is pulled-down, and GPIO 2 is floating, then the
+revision would be
+
+ 0t201 = 2*9 + 0*3 + 1*3 = 19
+
+If instead GPIO 0 is floating, GPIO 1 is pulled-up, and GPIO 2 is pulled-down,
+then the revision would be
+
+ 0t012 = 0*9 + 1*3 + 2*1 = 5
+
+Required properties:
+- compatible: should be "gpio-sysinfo".
+- gpios: should be a list of gpios forming the revision number,
+ least-significant-digit first
+- revisions: a list of known revisions; any revisions not present will have the
+ name "unknown"
+- names: the name of each revision in revisions
+
+Example:
+sysinfo {
+ compatible = "gpio-sysinfo";
+ gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
+ revisions = <19>, <5>;
+ names = "rev_a", "foo";
+};
diff --git a/doc/git-mailrc b/doc/git-mailrc
index f520ff8..34f936f 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -29,7 +29,7 @@
alias jagan Jagan Teki <jagan@amarulasolutions.com>
alias jhersh Joe Hershberger <joe.hershberger@ni.com>
alias kevery Kever Yang <kever.yang@rock-chips.com>
-alias leyfoon Ley Foon Tan <ley.foon.tan@intel.com>
+alias leyfoon Ley Foon Tan <lftan.linux@gmail.com>
alias lokeshvutla Lokesh Vutla <lokeshvutla@ti.com>
alias lukma Lukasz Majewski <lukma@denx.de>
alias macpaul Macpaul Lin <macpaul@andestech.com>
diff --git a/doc/usage/exception.rst b/doc/usage/exception.rst
index db1490f..27df88b 100644
--- a/doc/usage/exception.rst
+++ b/doc/usage/exception.rst
@@ -31,6 +31,9 @@
**RISC-V:**
+ ebreak
+ breakpoint exception
+
unaligned
load address misaligned
diff --git a/doc/usage/extension.rst b/doc/usage/extension.rst
new file mode 100644
index 0000000..2b88398
--- /dev/null
+++ b/doc/usage/extension.rst
@@ -0,0 +1,111 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright 2021, Kory Maincent <kory.maincent@bootlin.com>
+
+U-Boot extension board usage (CONFIG_EXTENSION)
+===============================================
+
+Synopsis
+--------
+
+::
+
+ extension scan
+ extension list
+ extension apply <extension number|all>
+
+Description
+-----------
+
+The "extension" command proposes a generic U-Boot mechanism to detect
+extension boards connected to the HW platform, and apply the appropriate
+Device Tree overlays depending on the detected extension boards.
+
+The "extension" command comes with three sub-commands:
+
+ - "extension scan" makes the generic code call the board-specific
+ extension_board_scan() function to retrieve the list of detected
+ extension boards.
+
+ - "extension list" allows to list the detected extension boards.
+
+ - "extension apply <number>|all" allows to apply the Device Tree
+ overlay(s) corresponding to one, or all, extension boards
+
+The latter requires two environment variables to exist:
+
+ - extension_overlay_addr: the RAM address where to load the Device
+ Tree overlays
+
+ - extension_overlay_cmd: the U-Boot command to load one overlay.
+ Indeed, the location and mechanism to load DT overlays is very setup
+ specific.
+
+In order to enable this mechanism, board-specific code must implement
+the extension_board_scan() function that fills in a linked list of
+"struct extension", each describing one extension board. In addition,
+the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig
+boolean.
+
+Usage example
+-------------
+
+1. Make sure your devicetree is loaded and set as the working fdt tree.
+
+::
+
+ => run loadfdt
+ => fdt addr $fdtaddr
+
+2. Prepare the environment variables
+
+::
+
+ => setenv extension_overlay_addr 0x88080000
+ => setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}'
+
+3. Detect the plugged extension board
+
+::
+
+ => extension scan
+
+4. List the plugged extension board information and the devicetree
+ overlay name
+
+::
+
+ => extension list
+
+5. Apply the appropriate devicetree overlay
+
+For apply the selected overlay:
+
+::
+
+ => extension apply 0
+
+For apply all the overlays:
+
+::
+
+ => extension apply all
+
+Simple extension_board_scan function example
+--------------------------------------------
+
+.. code-block:: c
+
+ int extension_board_scan(struct list_head *extension_list)
+ {
+ struct extension *extension;
+
+ extension = calloc(1, sizeof(struct extension));
+ snprintf(extension->overlay, sizeof(extension->overlay), "overlay.dtbo");
+ snprintf(extension->name, sizeof(extension->name), "extension board");
+ snprintf(extension->owner, sizeof(extension->owner), "sandbox");
+ snprintf(extension->version, sizeof(extension->version), "1.1");
+ snprintf(extension->other, sizeof(extension->other), "Extension board information");
+ list_add_tail(&extension->list, extension_list);
+
+ return 1;
+ }
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 528b3c7..c1f9b6a 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -26,6 +26,7 @@
conitrace
echo
exception
+ extension
exit
false
fatinfo
@@ -38,6 +39,7 @@
pstore
qfw
sbi
+ size
true
scp03
reset
diff --git a/doc/usage/mmc.rst b/doc/usage/mmc.rst
index 57284ed..458c764 100644
--- a/doc/usage/mmc.rst
+++ b/doc/usage/mmc.rst
@@ -40,7 +40,7 @@
cnt
block count
-The 'mmc erase' command erases MMC device from block offset until count.
+The 'mmc erase' command erases *cnt* blocks on the MMC device starting at block *blk#*.
blk#
start block offset
@@ -110,6 +110,7 @@
partitions to access
The 'mmc bootpart-resize' command changes sizes of boot and RPMB partitions.
+
dev
device number
boot part size MB
diff --git a/doc/usage/size.rst b/doc/usage/size.rst
new file mode 100644
index 0000000..f0c35e4
--- /dev/null
+++ b/doc/usage/size.rst
@@ -0,0 +1,40 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+size command
+============
+
+Synopsis
+--------
+
+::
+
+ size <interface> <dev[:part]> <filename>
+
+Description
+-----------
+
+The size command determines the size of a file and sets the environment variable
+filesize to this value. If filename points to a directory, the value is set to
+zero.
+
+If the command fails, the filesize environment variable is not changed.
+
+dev
+ device number
+
+part
+ partition number, defaults to 1
+
+filename
+ path to file
+
+Configuration
+-------------
+
+The size command is only available if CONFIG_CMD_FS_GENERIC=y.
+
+Return value
+------------
+
+The return value $? is set to 0 (true) if the command succeded and to 1 (false)
+otherwise.
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index b5a2798..6f0b772 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -77,8 +77,9 @@
config FSL_SATA
bool "Enable Freescale SATA controller driver support"
+ select AHCI
select LIBATA
- select AHCI if BLK
+ depends on BLK
help
Enable this driver to support the SATA controller found in
some Freescale PowerPC SoCs.
@@ -94,8 +95,9 @@
config SATA_SIL
bool "Enable Silicon Image SIL3131 / SIL3132 / SIL3124 SATA driver support"
+ select AHCI
select LIBATA
- select AHCI if BLK
+ depends on BLK
help
Enable this driver to support the SIL3131, SIL3132 and SIL3124
SATA controllers.
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 57c4e15..d4047c0 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -110,7 +110,7 @@
return (i < timeout_msec) ? 0 : -1;
}
-int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
+int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, int port)
{
u32 tmp;
int j = 0;
diff --git a/drivers/bios_emulator/biosemu.c b/drivers/bios_emulator/biosemu.c
index 9d4f07c..82befba 100644
--- a/drivers/bios_emulator/biosemu.c
+++ b/drivers/bios_emulator/biosemu.c
@@ -50,7 +50,7 @@
#include "biosemui.h"
BE_sysEnv _BE_env = {{0}};
-static X86EMU_memFuncs _BE_mem __attribute__((section(GOT2_TYPE))) = {
+static X86EMU_memFuncs _BE_mem __section(GOT2_TYPE) = {
BE_rdb,
BE_rdw,
BE_rdl,
@@ -59,7 +59,7 @@
BE_wrl,
};
-static X86EMU_pioFuncs _BE_pio __attribute__((section(GOT2_TYPE))) = {
+static X86EMU_pioFuncs _BE_pio __section(GOT2_TYPE) = {
BE_inb,
BE_inw,
BE_inl,
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 4aeaa0c..4bc6680 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -125,7 +125,7 @@
depends on CLK && ARCH_ZYNQ
default y
help
- This clock driver adds support for clock realted settings for
+ This clock driver adds support for clock related settings for
Zynq platform.
config CLK_ZYNQMP
@@ -159,11 +159,23 @@
by a SCMI agent based on SCMI clock protocol communication
with a SCMI server.
+config CLK_K210
+ bool "Clock support for Kendryte K210"
+ depends on CLK
+ help
+ This enables support clock driver for Kendryte K210 platforms.
+
+config CLK_K210_SET_RATE
+ bool "Enable setting the Kendryte K210 PLL rate"
+ depends on CLK_K210
+ help
+ Add functionality to calculate new rates for K210 PLLs. Enabling this
+ feature adds around 1K to U-Boot's final size.
+
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/imx/Kconfig"
-source "drivers/clk/kendryte/Kconfig"
source "drivers/clk/meson/Kconfig"
source "drivers/clk/microchip/Kconfig"
source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 645709b..f06164b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,7 +28,7 @@
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_$(SPL_TPL_)CLK_INTEL) += intel/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
-obj-$(CONFIG_CLK_K210) += kendryte/
+obj-$(CONFIG_CLK_K210) += clk_kendryte.o
obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
obj-$(CONFIG_CLK_MPFS) += microchip/
obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 4ab3c40..cac0f6a 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -14,6 +14,7 @@
#include <errno.h>
#include <log.h>
#include <malloc.h>
+#include <dm/device_compat.h>
#include <dm/device-internal.h>
#include <dm/devres.h>
#include <dm/read.h>
@@ -206,7 +207,8 @@
return c;
}
-static int clk_set_default_parents(struct udevice *dev, int stage)
+static int clk_set_default_parents(struct udevice *dev,
+ enum clk_defaults_stage stage)
{
struct clk clk, parent_clk, *c, *p;
int index;
@@ -240,6 +242,15 @@
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
+ /*
+ * If the clock provider is not ready yet, let it handle
+ * the re-programming later.
+ */
+ if (ret == -EPROBE_DEFER) {
+ ret = 0;
+ continue;
+ }
+
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
__func__, index, dev_read_name(dev));
@@ -250,10 +261,10 @@
* It cannot be done right now but need to wait after the
* device is probed
*/
- if (stage == 0 && clk.dev == dev)
+ if (stage == CLK_DEFAULTS_PRE && clk.dev == dev)
continue;
- if (stage > 0 && clk.dev != dev)
+ if (stage != CLK_DEFAULTS_PRE && clk.dev != dev)
/* do not setup twice the parent clocks */
continue;
@@ -279,7 +290,8 @@
return 0;
}
-static int clk_set_default_rates(struct udevice *dev, int stage)
+static int clk_set_default_rates(struct udevice *dev,
+ enum clk_defaults_stage stage)
{
struct clk clk, *c;
int index;
@@ -308,9 +320,19 @@
ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
index, &clk);
+ /*
+ * If the clock provider is not ready yet, let it handle
+ * the re-programming later.
+ */
+ if (ret == -EPROBE_DEFER) {
+ ret = 0;
+ continue;
+ }
+
if (ret) {
- debug("%s: could not get assigned clock %d for %s\n",
- __func__, index, dev_read_name(dev));
+ dev_dbg(dev,
+ "could not get assigned clock %d (err = %d)\n",
+ index, ret);
continue;
}
@@ -318,10 +340,10 @@
* It cannot be done right now but need to wait after the
* device is probed
*/
- if (stage == 0 && clk.dev == dev)
+ if (stage == CLK_DEFAULTS_PRE && clk.dev == dev)
continue;
- if (stage > 0 && clk.dev != dev)
+ if (stage != CLK_DEFAULTS_PRE && clk.dev != dev)
/* do not setup twice the parent clocks */
continue;
@@ -332,8 +354,9 @@
ret = clk_set_rate(c, rates[index]);
if (ret < 0) {
- debug("%s: failed to set rate on clock index %d (%ld) for %s\n",
- __func__, index, clk.id, dev_read_name(dev));
+ dev_warn(dev,
+ "failed to set rate on clock index %d (%ld) (error = %d)\n",
+ index, clk.id, ret);
break;
}
}
@@ -343,16 +366,21 @@
return ret;
}
-int clk_set_defaults(struct udevice *dev, int stage)
+int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage)
{
int ret;
if (!dev_has_ofnode(dev))
return 0;
- /* If this not in SPL and pre-reloc state, don't take any action. */
+ /*
+ * To avoid setting defaults twice, don't set them before relocation.
+ * However, still set them for SPL. And still set them if explicitly
+ * asked.
+ */
if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
- return 0;
+ if (stage != CLK_DEFAULTS_POST_FORCE)
+ return 0;
debug("%s(%s)\n", __func__, dev_read_name(dev));
@@ -499,6 +527,8 @@
return NULL;
pdev = dev_get_parent(clk->dev);
+ if (!pdev)
+ return ERR_PTR(-ENODEV);
pclk = dev_get_clk_ptr(pdev);
if (!pclk)
return ERR_PTR(-ENODEV);
@@ -545,6 +575,22 @@
return ops->round_rate(clk, rate);
}
+static void clk_clean_rate_cache(struct clk *clk)
+{
+ struct udevice *child_dev;
+ struct clk *clkp;
+
+ if (!clk)
+ return;
+
+ clk->rate = 0;
+
+ list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) {
+ clkp = dev_get_clk_ptr(child_dev);
+ clk_clean_rate_cache(clkp);
+ }
+}
+
ulong clk_set_rate(struct clk *clk, ulong rate)
{
const struct clk_ops *ops;
@@ -557,6 +603,9 @@
if (!ops->set_rate)
return -ENOSYS;
+ /* Clean up cached rates for us and all child clocks */
+ clk_clean_rate_cache(clk);
+
return ops->set_rate(clk, rate);
}
@@ -802,7 +851,7 @@
* where the DT is used to setup default parents and rates
* using assigned-clocks
*/
- clk_set_defaults(dev, 1);
+ clk_set_defaults(dev, CLK_DEFAULTS_POST);
return 0;
}
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c
index 09f9ef2..325a9b2 100644
--- a/drivers/clk/clk_fixed_rate.c
+++ b/drivers/clk/clk_fixed_rate.c
@@ -9,6 +9,9 @@
#include <dm/device-internal.h>
#include <linux/clk-provider.h>
+#define UBOOT_DM_CLK_FIXED_RATE "fixed_rate_clock"
+#define UBOOT_DM_CLK_FIXED_RATE_RAW "fixed_rate_raw_clock"
+
static ulong clk_fixed_rate_get_rate(struct clk *clk)
{
return to_clk_fixed_rate(clk->dev)->fixed_rate;
@@ -40,12 +43,47 @@
clk->enable_count = 0;
}
+static ulong clk_fixed_rate_raw_get_rate(struct clk *clk)
+{
+ return container_of(clk, struct clk_fixed_rate, clk)->fixed_rate;
+}
+
+const struct clk_ops clk_fixed_rate_raw_ops = {
+ .get_rate = clk_fixed_rate_raw_get_rate,
+};
+
static int clk_fixed_rate_of_to_plat(struct udevice *dev)
{
clk_fixed_rate_ofdata_to_plat_(dev, to_clk_fixed_rate(dev));
return 0;
}
+
+#if CONFIG_IS_ENABLED(CLK_CCF)
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+ ulong rate)
+{
+ struct clk *clk;
+ struct clk_fixed_rate *fixed;
+ int ret;
+
+ fixed = kzalloc(sizeof(*fixed), GFP_KERNEL);
+ if (!fixed)
+ return ERR_PTR(-ENOMEM);
+
+ fixed->fixed_rate = rate;
+
+ clk = &fixed->clk;
+
+ ret = clk_register(clk, UBOOT_DM_CLK_FIXED_RATE_RAW, name, NULL);
+ if (ret) {
+ kfree(fixed);
+ return ERR_PTR(ret);
+ }
+
+ return clk;
+}
+#endif
static const struct udevice_id clk_fixed_rate_match[] = {
{
@@ -63,3 +101,10 @@
.ops = &clk_fixed_rate_ops,
.flags = DM_FLAG_PRE_RELOC,
};
+
+U_BOOT_DRIVER(clk_fixed_rate_raw) = {
+ .name = UBOOT_DM_CLK_FIXED_RATE_RAW,
+ .id = UCLASS_CLK,
+ .ops = &clk_fixed_rate_raw_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/clk_kendryte.c b/drivers/clk/clk_kendryte.c
new file mode 100644
index 0000000..3148756
--- /dev/null
+++ b/drivers/clk/clk_kendryte.c
@@ -0,0 +1,1320 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ */
+#define LOG_CATEGORY UCLASS_CLK
+
+#include <common.h>
+#include <clk.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <log.h>
+#include <mapmem.h>
+#include <serial.h>
+#include <dt-bindings/clock/k210-sysctl.h>
+#include <dt-bindings/mfd/k210-sysctl.h>
+#include <kendryte/pll.h>
+#include <linux/bitfield.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+ * struct k210_clk_priv - K210 clock driver private data
+ * @base: The base address of the sysctl device
+ * @in0: The "in0" external oscillator
+ */
+struct k210_clk_priv {
+ void __iomem *base;
+ struct clk in0;
+};
+
+/*
+ * All parameters for different sub-clocks are collected into parameter arrays.
+ * These parameters are then initialized by the clock which uses them during
+ * probe. To save space, ids are automatically generated for each sub-clock by
+ * using an enum. Instead of storing a parameter struct for each clock, even for
+ * those clocks which don't use a particular type of sub-clock, we can just
+ * store the parameters for the clocks which need them.
+ *
+ * So why do it like this? Arranging all the sub-clocks together makes it very
+ * easy to find bugs in the code.
+ */
+
+/**
+ * enum k210_clk_div_type - The type of divider
+ * @K210_DIV_ONE: freq = parent / (reg + 1)
+ * @K210_DIV_EVEN: freq = parent / 2 / (reg + 1)
+ * @K210_DIV_POWER: freq = parent / (2 << reg)
+ * @K210_DIV_FIXED: freq = parent / factor
+ */
+enum k210_clk_div_type {
+ K210_DIV_ONE,
+ K210_DIV_EVEN,
+ K210_DIV_POWER,
+ K210_DIV_FIXED,
+};
+
+/**
+ * struct k210_div_params - Parameters for dividing clocks
+ * @type: An &enum k210_clk_div_type specifying the dividing formula
+ * @off: The offset of the divider from the sysctl base address
+ * @shift: The offset of the LSB of the divider
+ * @width: The number of bits in the divider
+ * @div: The fixed divisor for this divider
+ */
+struct k210_div_params {
+ u8 type;
+ union {
+ struct {
+ u8 off;
+ u8 shift;
+ u8 width;
+ };
+ u8 div;
+ };
+};
+
+#define DIV_LIST \
+ DIV(K210_CLK_ACLK, K210_SYSCTL_SEL0, 1, 2, K210_DIV_POWER) \
+ DIV(K210_CLK_APB0, K210_SYSCTL_SEL0, 3, 3, K210_DIV_ONE) \
+ DIV(K210_CLK_APB1, K210_SYSCTL_SEL0, 6, 3, K210_DIV_ONE) \
+ DIV(K210_CLK_APB2, K210_SYSCTL_SEL0, 9, 3, K210_DIV_ONE) \
+ DIV(K210_CLK_SRAM0, K210_SYSCTL_THR0, 0, 4, K210_DIV_ONE) \
+ DIV(K210_CLK_SRAM1, K210_SYSCTL_THR0, 4, 4, K210_DIV_ONE) \
+ DIV(K210_CLK_AI, K210_SYSCTL_THR0, 8, 4, K210_DIV_ONE) \
+ DIV(K210_CLK_DVP, K210_SYSCTL_THR0, 12, 4, K210_DIV_ONE) \
+ DIV(K210_CLK_ROM, K210_SYSCTL_THR0, 16, 4, K210_DIV_ONE) \
+ DIV(K210_CLK_SPI0, K210_SYSCTL_THR1, 0, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_SPI1, K210_SYSCTL_THR1, 8, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_SPI2, K210_SYSCTL_THR1, 16, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_SPI3, K210_SYSCTL_THR1, 24, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_TIMER0, K210_SYSCTL_THR2, 0, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_TIMER1, K210_SYSCTL_THR2, 8, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_TIMER2, K210_SYSCTL_THR2, 16, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_I2S0, K210_SYSCTL_THR3, 0, 16, K210_DIV_EVEN) \
+ DIV(K210_CLK_I2S1, K210_SYSCTL_THR3, 16, 16, K210_DIV_EVEN) \
+ DIV(K210_CLK_I2S2, K210_SYSCTL_THR4, 0, 16, K210_DIV_EVEN) \
+ DIV(K210_CLK_I2S0_M, K210_SYSCTL_THR4, 16, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_I2S1_M, K210_SYSCTL_THR4, 24, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_I2S2_M, K210_SYSCTL_THR4, 0, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_I2C0, K210_SYSCTL_THR5, 8, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_I2C1, K210_SYSCTL_THR5, 16, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_I2C2, K210_SYSCTL_THR5, 24, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_WDT0, K210_SYSCTL_THR6, 0, 8, K210_DIV_EVEN) \
+ DIV(K210_CLK_WDT1, K210_SYSCTL_THR6, 8, 8, K210_DIV_EVEN) \
+ DIV_FIXED(K210_CLK_CLINT, 50) \
+
+#define _DIVIFY(id) K210_CLK_DIV_##id
+#define DIVIFY(id) _DIVIFY(id)
+
+enum k210_div_id {
+#define DIV(id, ...) DIVIFY(id),
+#define DIV_FIXED DIV
+ DIV_LIST
+#undef DIV
+#undef DIV_FIXED
+ K210_CLK_DIV_NONE,
+};
+
+static const struct k210_div_params k210_divs[] = {
+#define DIV(id, _off, _shift, _width, _type) \
+ [DIVIFY(id)] = { \
+ .type = (_type), \
+ .off = (_off), \
+ .shift = (_shift), \
+ .width = (_width), \
+ },
+#define DIV_FIXED(id, _div) \
+ [DIVIFY(id)] = { \
+ .type = K210_DIV_FIXED, \
+ .div = (_div) \
+ },
+ DIV_LIST
+#undef DIV
+#undef DIV_FIXED
+};
+
+#undef DIV
+#undef DIV_LIST
+
+/**
+ * struct k210_gate_params - Parameters for gated clocks
+ * @off: The offset of the gate from the sysctl base address
+ * @bit_idx: The index of the bit within the register
+ */
+struct k210_gate_params {
+ u8 off;
+ u8 bit_idx;
+};
+
+#define GATE_LIST \
+ GATE(K210_CLK_CPU, K210_SYSCTL_EN_CENT, 0) \
+ GATE(K210_CLK_SRAM0, K210_SYSCTL_EN_CENT, 1) \
+ GATE(K210_CLK_SRAM1, K210_SYSCTL_EN_CENT, 2) \
+ GATE(K210_CLK_APB0, K210_SYSCTL_EN_CENT, 3) \
+ GATE(K210_CLK_APB1, K210_SYSCTL_EN_CENT, 4) \
+ GATE(K210_CLK_APB2, K210_SYSCTL_EN_CENT, 5) \
+ GATE(K210_CLK_ROM, K210_SYSCTL_EN_PERI, 0) \
+ GATE(K210_CLK_DMA, K210_SYSCTL_EN_PERI, 1) \
+ GATE(K210_CLK_AI, K210_SYSCTL_EN_PERI, 2) \
+ GATE(K210_CLK_DVP, K210_SYSCTL_EN_PERI, 3) \
+ GATE(K210_CLK_FFT, K210_SYSCTL_EN_PERI, 4) \
+ GATE(K210_CLK_GPIO, K210_SYSCTL_EN_PERI, 5) \
+ GATE(K210_CLK_SPI0, K210_SYSCTL_EN_PERI, 6) \
+ GATE(K210_CLK_SPI1, K210_SYSCTL_EN_PERI, 7) \
+ GATE(K210_CLK_SPI2, K210_SYSCTL_EN_PERI, 8) \
+ GATE(K210_CLK_SPI3, K210_SYSCTL_EN_PERI, 9) \
+ GATE(K210_CLK_I2S0, K210_SYSCTL_EN_PERI, 10) \
+ GATE(K210_CLK_I2S1, K210_SYSCTL_EN_PERI, 11) \
+ GATE(K210_CLK_I2S2, K210_SYSCTL_EN_PERI, 12) \
+ GATE(K210_CLK_I2C0, K210_SYSCTL_EN_PERI, 13) \
+ GATE(K210_CLK_I2C1, K210_SYSCTL_EN_PERI, 14) \
+ GATE(K210_CLK_I2C2, K210_SYSCTL_EN_PERI, 15) \
+ GATE(K210_CLK_UART1, K210_SYSCTL_EN_PERI, 16) \
+ GATE(K210_CLK_UART2, K210_SYSCTL_EN_PERI, 17) \
+ GATE(K210_CLK_UART3, K210_SYSCTL_EN_PERI, 18) \
+ GATE(K210_CLK_AES, K210_SYSCTL_EN_PERI, 19) \
+ GATE(K210_CLK_FPIOA, K210_SYSCTL_EN_PERI, 20) \
+ GATE(K210_CLK_TIMER0, K210_SYSCTL_EN_PERI, 21) \
+ GATE(K210_CLK_TIMER1, K210_SYSCTL_EN_PERI, 22) \
+ GATE(K210_CLK_TIMER2, K210_SYSCTL_EN_PERI, 23) \
+ GATE(K210_CLK_WDT0, K210_SYSCTL_EN_PERI, 24) \
+ GATE(K210_CLK_WDT1, K210_SYSCTL_EN_PERI, 25) \
+ GATE(K210_CLK_SHA, K210_SYSCTL_EN_PERI, 26) \
+ GATE(K210_CLK_OTP, K210_SYSCTL_EN_PERI, 27) \
+ GATE(K210_CLK_RTC, K210_SYSCTL_EN_PERI, 29)
+
+#define _GATEIFY(id) K210_CLK_GATE_##id
+#define GATEIFY(id) _GATEIFY(id)
+
+enum k210_gate_id {
+#define GATE(id, ...) GATEIFY(id),
+ GATE_LIST
+#undef GATE
+ K210_CLK_GATE_NONE,
+};
+
+static const struct k210_gate_params k210_gates[] = {
+#define GATE(id, _off, _idx) \
+ [GATEIFY(id)] = { \
+ .off = (_off), \
+ .bit_idx = (_idx), \
+ },
+ GATE_LIST
+#undef GATE
+};
+
+#undef GATE_LIST
+
+/* The most parents is PLL2 */
+#define K210_CLK_MAX_PARENTS 3
+
+/**
+ * struct k210_mux_params - Parameters for muxed clocks
+ * @parents: A list of parent clock ids
+ * @num_parents: The number of parent clocks
+ * @off: The offset of the mux from the base sysctl address
+ * @shift: The offset of the LSB of the mux selector
+ * @width: The number of bits in the mux selector
+ */
+struct k210_mux_params {
+ u8 parents[K210_CLK_MAX_PARENTS];
+ u8 num_parents;
+ u8 off;
+ u8 shift;
+ u8 width;
+};
+
+#define MUX(id, reg, shift, width) \
+ MUX_PARENTS(id, reg, shift, width, K210_CLK_IN0, K210_CLK_PLL0)
+#define MUX_LIST \
+ MUX_PARENTS(K210_CLK_PLL2, K210_SYSCTL_PLL2, 26, 2, \
+ K210_CLK_IN0, K210_CLK_PLL0, K210_CLK_PLL1) \
+ MUX(K210_CLK_ACLK, K210_SYSCTL_SEL0, 0, 1) \
+ MUX(K210_CLK_SPI3, K210_SYSCTL_SEL0, 12, 1) \
+ MUX(K210_CLK_TIMER0, K210_SYSCTL_SEL0, 13, 1) \
+ MUX(K210_CLK_TIMER1, K210_SYSCTL_SEL0, 14, 1) \
+ MUX(K210_CLK_TIMER2, K210_SYSCTL_SEL0, 15, 1)
+
+#define _MUXIFY(id) K210_CLK_MUX_##id
+#define MUXIFY(id) _MUXIFY(id)
+
+enum k210_mux_id {
+#define MUX_PARENTS(id, ...) MUXIFY(id),
+ MUX_LIST
+#undef MUX_PARENTS
+ K210_CLK_MUX_NONE,
+};
+
+static const struct k210_mux_params k210_muxes[] = {
+#define MUX_PARENTS(id, _off, _shift, _width, ...) \
+ [MUXIFY(id)] = { \
+ .parents = { __VA_ARGS__ }, \
+ .num_parents = __count_args(__VA_ARGS__), \
+ .off = (_off), \
+ .shift = (_shift), \
+ .width = (_width), \
+ },
+ MUX_LIST
+#undef MUX_PARENTS
+};
+
+#undef MUX
+#undef MUX_LIST
+
+/**
+ * struct k210_pll_params - K210 PLL parameters
+ * @off: The offset of the PLL from the base sysctl address
+ * @shift: The offset of the LSB of the lock status
+ * @width: The number of bits in the lock status
+ */
+struct k210_pll_params {
+ u8 off;
+ u8 shift;
+ u8 width;
+};
+
+static const struct k210_pll_params k210_plls[] = {
+#define PLL(_off, _shift, _width) { \
+ .off = (_off), \
+ .shift = (_shift), \
+ .width = (_width), \
+}
+ [0] = PLL(K210_SYSCTL_PLL0, 0, 2),
+ [1] = PLL(K210_SYSCTL_PLL1, 8, 1),
+ [2] = PLL(K210_SYSCTL_PLL2, 16, 1),
+#undef PLL
+};
+
+/**
+ * enum k210_clk_flags - The type of a K210 clock
+ * @K210_CLKF_MUX: This clock has a mux and not a static parent
+ * @K210_CLKF_PLL: This clock is a PLL
+ */
+enum k210_clk_flags {
+ K210_CLKF_MUX = BIT(0),
+ K210_CLKF_PLL = BIT(1),
+};
+
+/**
+ * struct k210_clk_params - The parameters defining a K210 clock
+ * @name: The name of the clock
+ * @flags: A set of &enum k210_clk_flags defining which fields are valid
+ * @mux: An &enum k210_mux_id of this clock's mux
+ * @parent: The clock id of this clock's parent
+ * @pll: The id of the PLL (if this clock is a PLL)
+ * @div: An &enum k210_div_id of this clock's divider
+ * @gate: An &enum k210_gate_id of this clock's gate
+ */
+struct k210_clk_params {
+#if CONFIG_IS_ENABLED(CMD_CLK)
+ const char *name;
+#endif
+ u8 flags;
+ union {
+ u8 parent;
+ u8 mux;
+ };
+ union {
+ u8 pll;
+ struct {
+ u8 div;
+ u8 gate;
+ };
+ };
+};
+
+static const struct k210_clk_params k210_clks[] = {
+#if CONFIG_IS_ENABLED(CMD_CLK)
+#define NAME(_name) .name = (_name),
+#else
+#define NAME(name)
+#endif
+#define CLK(id, _name, _parent, _div, _gate) \
+ [id] = { \
+ NAME(_name) \
+ .parent = (_parent), \
+ .div = (_div), \
+ .gate = (_gate), \
+ }
+#define CLK_MUX(id, _name, _mux, _div, _gate) \
+ [id] = { \
+ NAME(_name) \
+ .flags = K210_CLKF_MUX, \
+ .mux = (_mux), \
+ .div = (_div), \
+ .gate = (_gate), \
+ }
+#define CLK_PLL(id, _pll, _parent) \
+ [id] = { \
+ NAME("pll" #_pll) \
+ .flags = K210_CLKF_PLL, \
+ .parent = (_parent), \
+ .pll = (_pll), \
+ }
+#define CLK_FULL(id, name) \
+ CLK_MUX(id, name, MUXIFY(id), DIVIFY(id), GATEIFY(id))
+#define CLK_NOMUX(id, name, parent) \
+ CLK(id, name, parent, DIVIFY(id), GATEIFY(id))
+#define CLK_DIV(id, name, parent) \
+ CLK(id, name, parent, DIVIFY(id), K210_CLK_GATE_NONE)
+#define CLK_GATE(id, name, parent) \
+ CLK(id, name, parent, K210_CLK_DIV_NONE, GATEIFY(id))
+ CLK_PLL(K210_CLK_PLL0, 0, K210_CLK_IN0),
+ CLK_PLL(K210_CLK_PLL1, 1, K210_CLK_IN0),
+ [K210_CLK_PLL2] = {
+ NAME("pll2")
+ .flags = K210_CLKF_MUX | K210_CLKF_PLL,
+ .mux = MUXIFY(K210_CLK_PLL2),
+ .pll = 2,
+ },
+ CLK_MUX(K210_CLK_ACLK, "aclk", MUXIFY(K210_CLK_ACLK),
+ DIVIFY(K210_CLK_ACLK), K210_CLK_GATE_NONE),
+ CLK_FULL(K210_CLK_SPI3, "spi3"),
+ CLK_FULL(K210_CLK_TIMER0, "timer0"),
+ CLK_FULL(K210_CLK_TIMER1, "timer1"),
+ CLK_FULL(K210_CLK_TIMER2, "timer2"),
+ CLK_NOMUX(K210_CLK_SRAM0, "sram0", K210_CLK_ACLK),
+ CLK_NOMUX(K210_CLK_SRAM1, "sram1", K210_CLK_ACLK),
+ CLK_NOMUX(K210_CLK_ROM, "rom", K210_CLK_ACLK),
+ CLK_NOMUX(K210_CLK_DVP, "dvp", K210_CLK_ACLK),
+ CLK_NOMUX(K210_CLK_APB0, "apb0", K210_CLK_ACLK),
+ CLK_NOMUX(K210_CLK_APB1, "apb1", K210_CLK_ACLK),
+ CLK_NOMUX(K210_CLK_APB2, "apb2", K210_CLK_ACLK),
+ CLK_NOMUX(K210_CLK_AI, "ai", K210_CLK_PLL1),
+ CLK_NOMUX(K210_CLK_I2S0, "i2s0", K210_CLK_PLL2),
+ CLK_NOMUX(K210_CLK_I2S1, "i2s1", K210_CLK_PLL2),
+ CLK_NOMUX(K210_CLK_I2S2, "i2s2", K210_CLK_PLL2),
+ CLK_NOMUX(K210_CLK_WDT0, "wdt0", K210_CLK_IN0),
+ CLK_NOMUX(K210_CLK_WDT1, "wdt1", K210_CLK_IN0),
+ CLK_NOMUX(K210_CLK_SPI0, "spi0", K210_CLK_PLL0),
+ CLK_NOMUX(K210_CLK_SPI1, "spi1", K210_CLK_PLL0),
+ CLK_NOMUX(K210_CLK_SPI2, "spi2", K210_CLK_PLL0),
+ CLK_NOMUX(K210_CLK_I2C0, "i2c0", K210_CLK_PLL0),
+ CLK_NOMUX(K210_CLK_I2C1, "i2c1", K210_CLK_PLL0),
+ CLK_NOMUX(K210_CLK_I2C2, "i2c2", K210_CLK_PLL0),
+ CLK_DIV(K210_CLK_I2S0_M, "i2s0_m", K210_CLK_PLL2),
+ CLK_DIV(K210_CLK_I2S1_M, "i2s1_m", K210_CLK_PLL2),
+ CLK_DIV(K210_CLK_I2S2_M, "i2s2_m", K210_CLK_PLL2),
+ CLK_DIV(K210_CLK_CLINT, "clint", K210_CLK_ACLK),
+ CLK_GATE(K210_CLK_CPU, "cpu", K210_CLK_ACLK),
+ CLK_GATE(K210_CLK_DMA, "dma", K210_CLK_ACLK),
+ CLK_GATE(K210_CLK_FFT, "fft", K210_CLK_ACLK),
+ CLK_GATE(K210_CLK_GPIO, "gpio", K210_CLK_APB0),
+ CLK_GATE(K210_CLK_UART1, "uart1", K210_CLK_APB0),
+ CLK_GATE(K210_CLK_UART2, "uart2", K210_CLK_APB0),
+ CLK_GATE(K210_CLK_UART3, "uart3", K210_CLK_APB0),
+ CLK_GATE(K210_CLK_FPIOA, "fpioa", K210_CLK_APB0),
+ CLK_GATE(K210_CLK_SHA, "sha", K210_CLK_APB0),
+ CLK_GATE(K210_CLK_AES, "aes", K210_CLK_APB1),
+ CLK_GATE(K210_CLK_OTP, "otp", K210_CLK_APB1),
+ CLK_GATE(K210_CLK_RTC, "rtc", K210_CLK_IN0),
+#undef NAME
+#undef CLK_PLL
+#undef CLK
+#undef CLK_FULL
+#undef CLK_NOMUX
+#undef CLK_DIV
+#undef CLK_GATE
+#undef CLK_LIST
+};
+
+#define K210_PLL_CLKR GENMASK(3, 0)
+#define K210_PLL_CLKF GENMASK(9, 4)
+#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */
+#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */
+#define K210_PLL_RESET BIT(20)
+#define K210_PLL_PWRD BIT(21) /* PoWeReD */
+#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */
+#define K210_PLL_BYPASS BIT(23)
+#define K210_PLL_TEST BIT(24)
+#define K210_PLL_EN BIT(25)
+#define K210_PLL_TEST_EN BIT(26)
+
+#define K210_PLL_LOCK 0
+#define K210_PLL_CLEAR_SLIP 2
+#define K210_PLL_TEST_OUT 3
+
+#ifdef CONFIG_CLK_K210_SET_RATE
+static int k210_pll_enable(struct k210_clk_priv *priv, int id);
+static int k210_pll_disable(struct k210_clk_priv *priv, int id);
+static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id, ulong rate_in);
+
+/*
+ * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
+ * General-Purpose PLL. The logical layout of the PLL with internal feedback is
+ * approximately the following:
+ *
+ * +---------------+
+ * |reference clock|
+ * +---------------+
+ * |
+ * v
+ * +--+
+ * |/r|
+ * +--+
+ * |
+ * v
+ * +-------------+
+ * |divided clock|
+ * +-------------+
+ * |
+ * v
+ * +--------------+
+ * |phase detector|<---+
+ * +--------------+ |
+ * | |
+ * v +--------------+
+ * +---+ |feedback clock|
+ * |VCO| +--------------+
+ * +---+ ^
+ * | +--+ |
+ * +--->|/f|---+
+ * | +--+
+ * v
+ * +---+
+ * |/od|
+ * +---+
+ * |
+ * v
+ * +------+
+ * |output|
+ * +------+
+ *
+ * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
+ * the effect of the division by f is to multiply the input frequency. The
+ * equation for the output rate is
+ * rate = (rate_in * f) / (r * od).
+ * Moving knowns to one side of the equation, we get
+ * rate / rate_in = f / (r * od)
+ * Rearranging slightly,
+ * abs_error = abs((rate / rate_in) - (f / (r * od))).
+ * To get relative, error, we divide by the expected ratio
+ * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
+ * Simplifying,
+ * error = abs(1 - f / (r * od)) / (rate / rate_in)
+ * error = abs(1 - (f * rate_in) / (r * od * rate))
+ * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
+ * error = abs((f * inv_ratio) / (r * od) - 1)
+ * This is the error used in evaluating parameters.
+ *
+ * r and od are four bits each, while f is six bits. Because r and od are
+ * multiplied together, instead of the full 256 values possible if both bits
+ * were used fully, there are only 97 distinct products. Combined with f, there
+ * are 6208 theoretical settings for the PLL. However, most of these settings
+ * can be ruled out immediately because they do not have the correct ratio.
+ *
+ * In addition to the constraint of approximating the desired ratio, parameters
+ * must also keep internal pll frequencies within acceptable ranges. The divided
+ * clock's minimum and maximum frequencies have a ratio of around 128. This
+ * leaves fairly substantial room to work with, especially since the only
+ * affected parameter is r. The VCO's minimum and maximum frequency have a ratio
+ * of 5, which is considerably more restrictive.
+ *
+ * The r and od factors are stored in a table. This is to make it easy to find
+ * the next-largest product. Some products have multiple factorizations, but
+ * only when one factor has at least a 2.5x ratio to the factors of the other
+ * factorization. This is because any smaller ratio would not make a difference
+ * when ensuring the VCO's frequency is within spec.
+ *
+ * Throughout the calculation function, fixed point arithmetic is used. Because
+ * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
+ * 32.32 fixed-point numbers are used to represent ratios. In general, to
+ * implement division, the numerator is first multiplied by 2^32. This gives a
+ * result where the whole number part is in the upper 32 bits, and the fraction
+ * is in the lower 32 bits.
+ *
+ * In general, rounding is done to the closest integer. This helps find the best
+ * approximation for the ratio. Rounding in one direction (e.g down) could cause
+ * the function to miss a better ratio with one of the parameters increased by
+ * one.
+ */
+
+/*
+ * The factors table was generated with the following python code:
+ *
+ * def p(x, y):
+ * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
+ *
+ * factors = {}
+ * for i in range(1, 17):
+ * for j in range(1, 17):
+ * fs = factors.get(i*j) or []
+ * if fs == [] or all([
+ * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
+ * for (x, y) in fs]):
+ * fs.append((i, j))
+ * factors[i*j] = fs
+ *
+ * for k, l in sorted(factors.items()):
+ * for v in l:
+ * print("PACK(%s, %s)," % v)
+ */
+#define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
+#define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
+#define UNPACK_OD(val) (((val) & 0xF) + 1)
+static const u8 factors[] = {
+ PACK(1, 1),
+ PACK(1, 2),
+ PACK(1, 3),
+ PACK(1, 4),
+ PACK(1, 5),
+ PACK(1, 6),
+ PACK(1, 7),
+ PACK(1, 8),
+ PACK(1, 9),
+ PACK(3, 3),
+ PACK(1, 10),
+ PACK(1, 11),
+ PACK(1, 12),
+ PACK(3, 4),
+ PACK(1, 13),
+ PACK(1, 14),
+ PACK(1, 15),
+ PACK(3, 5),
+ PACK(1, 16),
+ PACK(4, 4),
+ PACK(2, 9),
+ PACK(2, 10),
+ PACK(3, 7),
+ PACK(2, 11),
+ PACK(2, 12),
+ PACK(5, 5),
+ PACK(2, 13),
+ PACK(3, 9),
+ PACK(2, 14),
+ PACK(2, 15),
+ PACK(2, 16),
+ PACK(3, 11),
+ PACK(5, 7),
+ PACK(3, 12),
+ PACK(3, 13),
+ PACK(4, 10),
+ PACK(3, 14),
+ PACK(4, 11),
+ PACK(3, 15),
+ PACK(3, 16),
+ PACK(7, 7),
+ PACK(5, 10),
+ PACK(4, 13),
+ PACK(6, 9),
+ PACK(5, 11),
+ PACK(4, 14),
+ PACK(4, 15),
+ PACK(7, 9),
+ PACK(4, 16),
+ PACK(5, 13),
+ PACK(6, 11),
+ PACK(5, 14),
+ PACK(6, 12),
+ PACK(5, 15),
+ PACK(7, 11),
+ PACK(6, 13),
+ PACK(5, 16),
+ PACK(9, 9),
+ PACK(6, 14),
+ PACK(8, 11),
+ PACK(6, 15),
+ PACK(7, 13),
+ PACK(6, 16),
+ PACK(7, 14),
+ PACK(9, 11),
+ PACK(10, 10),
+ PACK(8, 13),
+ PACK(7, 15),
+ PACK(9, 12),
+ PACK(10, 11),
+ PACK(7, 16),
+ PACK(9, 13),
+ PACK(8, 15),
+ PACK(11, 11),
+ PACK(9, 14),
+ PACK(8, 16),
+ PACK(10, 13),
+ PACK(11, 12),
+ PACK(9, 15),
+ PACK(10, 14),
+ PACK(11, 13),
+ PACK(9, 16),
+ PACK(10, 15),
+ PACK(11, 14),
+ PACK(12, 13),
+ PACK(10, 16),
+ PACK(11, 15),
+ PACK(12, 14),
+ PACK(13, 13),
+ PACK(11, 16),
+ PACK(12, 15),
+ PACK(13, 14),
+ PACK(12, 16),
+ PACK(13, 15),
+ PACK(14, 14),
+ PACK(13, 16),
+ PACK(14, 15),
+ PACK(14, 16),
+ PACK(15, 15),
+ PACK(15, 16),
+ PACK(16, 16),
+};
+
+TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
+ struct k210_pll_config *best)
+{
+ int i;
+ s64 error, best_error;
+ u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
+ u64 max_r;
+ u64 r, f, od;
+
+ /*
+ * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
+ * VCO frequency. These are not the same limits as below because od can
+ * reduce the output frequency by 16.
+ */
+ if (rate > 1750000000 || rate < 21250000)
+ return -EINVAL;
+
+ /* Similar restrictions on the input rate */
+ if (rate_in > 1750000000 || rate_in < 13300000)
+ return -EINVAL;
+
+ ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
+ inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
+ /* Can't increase by more than 64 or reduce by more than 256 */
+ if (rate > rate_in && ratio > (64ULL << 32))
+ return -EINVAL;
+ else if (rate <= rate_in && inv_ratio > (256ULL << 32))
+ return -EINVAL;
+
+ /*
+ * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
+ * MHz. There is no minimum, since the only way to get a higher input
+ * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
+ * cannot output frequencies greater than 1.75 GHz, the minimum would
+ * never be greater than one.
+ */
+ max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
+
+ /* Variables get immediately incremented, so start at -1th iteration */
+ i = -1;
+ f = 0;
+ r = 0;
+ od = 0;
+ best_error = S64_MAX;
+ error = best_error;
+ /* do-while here so we always try at least one ratio */
+ do {
+ /*
+ * Whether we swapped r and od while enforcing frequency limits
+ */
+ bool swapped = false;
+ u64 last_od = od;
+ u64 last_r = r;
+
+ /*
+ * Try the next largest value for f (or r and od) and
+ * recalculate the other parameters based on that
+ */
+ if (rate > rate_in) {
+ /*
+ * Skip factors of the same product if we already tried
+ * out that product
+ */
+ do {
+ i++;
+ r = UNPACK_R(factors[i]);
+ od = UNPACK_OD(factors[i]);
+ } while (i + 1 < ARRAY_SIZE(factors) &&
+ r * od == last_r * last_od);
+
+ /* Round close */
+ f = (r * od * ratio + BIT(31)) >> 32;
+ if (f > 64)
+ f = 64;
+ } else {
+ u64 tmp = ++f * inv_ratio;
+ bool round_up = !!(tmp & BIT(31));
+ u32 goal = (tmp >> 32) + round_up;
+ u32 err, last_err;
+
+ /* Get the next r/od pair in factors */
+ while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
+ i++;
+ r = UNPACK_R(factors[i]);
+ od = UNPACK_OD(factors[i]);
+ }
+
+ /*
+ * This is a case of double rounding. If we rounded up
+ * above, we need to round down (in cases of ties) here.
+ * This prevents off-by-one errors resulting from
+ * choosing X+2 over X when X.Y rounds up to X+1 and
+ * there is no r * od = X+1. For the converse, when X.Y
+ * is rounded down to X, we should choose X+1 over X-1.
+ */
+ err = abs(r * od - goal);
+ last_err = abs(last_r * last_od - goal);
+ if (last_err < err || (round_up && last_err == err)) {
+ i--;
+ r = last_r;
+ od = last_od;
+ }
+ }
+
+ /*
+ * Enforce limits on internal clock frequencies. If we
+ * aren't in spec, try swapping r and od. If everything is
+ * in-spec, calculate the relative error.
+ */
+ while (true) {
+ /*
+ * Whether the intermediate frequencies are out-of-spec
+ */
+ bool out_of_spec = false;
+
+ if (r > max_r) {
+ out_of_spec = true;
+ } else {
+ /*
+ * There is no way to only divide once; we need
+ * to examine the frequency with and without the
+ * effect of od.
+ */
+ u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
+
+ if (vco > 1750000000 || vco < 340000000)
+ out_of_spec = true;
+ }
+
+ if (out_of_spec) {
+ if (!swapped) {
+ u64 tmp = r;
+
+ r = od;
+ od = tmp;
+ swapped = true;
+ continue;
+ } else {
+ /*
+ * Try looking ahead to see if there are
+ * additional factors for the same
+ * product.
+ */
+ if (i + 1 < ARRAY_SIZE(factors)) {
+ u64 new_r, new_od;
+
+ i++;
+ new_r = UNPACK_R(factors[i]);
+ new_od = UNPACK_OD(factors[i]);
+ if (r * od == new_r * new_od) {
+ r = new_r;
+ od = new_od;
+ swapped = false;
+ continue;
+ }
+ i--;
+ }
+ break;
+ }
+ }
+
+ error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
+ /* The lower 16 bits are spurious */
+ error = abs((error - BIT(32))) >> 16;
+
+ if (error < best_error) {
+ best->r = r;
+ best->f = f;
+ best->od = od;
+ best_error = error;
+ }
+ break;
+ }
+ } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
+
+ if (best_error == S64_MAX)
+ return -EINVAL;
+
+ log_debug("best error %lld\n", best_error);
+ return 0;
+}
+
+static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
+ ulong rate_in)
+{
+ int err;
+ const struct k210_pll_params *pll = &k210_plls[id];
+ struct k210_pll_config config = {};
+ u32 reg;
+ ulong calc_rate;
+
+ if (rate_in < 0)
+ return rate_in;
+
+ err = k210_pll_calc_config(rate, rate_in, &config);
+ if (err)
+ return err;
+ log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
+
+ /* Don't bother setting the rate if we're already at that rate */
+ calc_rate = DIV_ROUND_DOWN_ULL(((u64)rate_in) * config.f,
+ config.r * config.od);
+ if (calc_rate == k210_pll_get_rate(priv, id, rate))
+ return calc_rate;
+
+ k210_pll_disable(priv, id);
+
+ reg = readl(priv->base + pll->off);
+ reg &= ~K210_PLL_CLKR
+ & ~K210_PLL_CLKF
+ & ~K210_PLL_CLKOD
+ & ~K210_PLL_BWADJ;
+ reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1)
+ | FIELD_PREP(K210_PLL_CLKF, config.f - 1)
+ | FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
+ | FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
+ writel(reg, priv->base + pll->off);
+
+ k210_pll_enable(priv, id);
+
+ serial_setbrg();
+ return k210_pll_get_rate(priv, id, rate);
+}
+#else
+static ulong k210_pll_set_rate(struct k210_clk_priv *priv, int id, ulong rate,
+ ulong rate_in)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_CLK_K210_SET_RATE */
+
+static ulong k210_pll_get_rate(struct k210_clk_priv *priv, int id,
+ ulong rate_in)
+{
+ u64 r, f, od;
+ u32 reg = readl(priv->base + k210_plls[id].off);
+
+ if (rate_in < 0 || (reg & K210_PLL_BYPASS))
+ return rate_in;
+
+ if (!(reg & K210_PLL_PWRD))
+ return 0;
+
+ r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
+ f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
+ od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
+
+ return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
+}
+
+/*
+ * Wait for the PLL to be locked. If the PLL is not locked, try clearing the
+ * slip before retrying
+ */
+static void k210_pll_waitfor_lock(struct k210_clk_priv *priv, int id)
+{
+ const struct k210_pll_params *pll = &k210_plls[id];
+ u32 mask = (BIT(pll->width) - 1) << pll->shift;
+
+ while (true) {
+ u32 reg = readl(priv->base + K210_SYSCTL_PLL_LOCK);
+
+ if ((reg & mask) == mask)
+ break;
+
+ reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
+ writel(reg, priv->base + K210_SYSCTL_PLL_LOCK);
+ }
+}
+
+static bool k210_pll_enabled(u32 reg)
+{
+ return (reg & K210_PLL_PWRD) && (reg & K210_PLL_EN) &&
+ !(reg & K210_PLL_RESET);
+}
+
+/* Adapted from sysctl_pll_enable */
+static int k210_pll_enable(struct k210_clk_priv *priv, int id)
+{
+ const struct k210_pll_params *pll = &k210_plls[id];
+ u32 reg = readl(priv->base + pll->off);
+
+ if (k210_pll_enabled(reg))
+ return 0;
+
+ reg |= K210_PLL_PWRD;
+ writel(reg, priv->base + pll->off);
+
+ /* Ensure reset is low before asserting it */
+ reg &= ~K210_PLL_RESET;
+ writel(reg, priv->base + pll->off);
+ reg |= K210_PLL_RESET;
+ writel(reg, priv->base + pll->off);
+ nop();
+ nop();
+ reg &= ~K210_PLL_RESET;
+ writel(reg, priv->base + pll->off);
+
+ k210_pll_waitfor_lock(priv, id);
+
+ reg &= ~K210_PLL_BYPASS;
+ reg |= K210_PLL_EN;
+ writel(reg, priv->base + pll->off);
+
+ return 0;
+}
+
+static int k210_pll_disable(struct k210_clk_priv *priv, int id)
+{
+ const struct k210_pll_params *pll = &k210_plls[id];
+ u32 reg = readl(priv->base + pll->off);
+
+ /*
+ * Bypassing before powering off is important so child clocks don't stop
+ * working. This is especially important for pll0, the indirect parent
+ * of the cpu clock.
+ */
+ reg |= K210_PLL_BYPASS;
+ writel(reg, priv->base + pll->off);
+
+ reg &= ~K210_PLL_PWRD;
+ reg &= ~K210_PLL_EN;
+ writel(reg, priv->base + pll->off);
+ return 0;
+}
+
+static u32 k210_clk_readl(struct k210_clk_priv *priv, u8 off, u8 shift,
+ u8 width)
+{
+ u32 reg = readl(priv->base + off);
+
+ return (reg >> shift) & (BIT(width) - 1);
+}
+
+static void k210_clk_writel(struct k210_clk_priv *priv, u8 off, u8 shift,
+ u8 width, u32 val)
+{
+ u32 reg = readl(priv->base + off);
+ u32 mask = (BIT(width) - 1) << shift;
+
+ reg &= ~mask;
+ reg |= mask & (val << shift);
+ writel(reg, priv->base + off);
+}
+
+static int k210_clk_get_parent(struct k210_clk_priv *priv, int id)
+{
+ u32 sel;
+ const struct k210_mux_params *mux;
+
+ if (!(k210_clks[id].flags & K210_CLKF_MUX))
+ return k210_clks[id].parent;
+ mux = &k210_muxes[k210_clks[id].mux];
+
+ sel = k210_clk_readl(priv, mux->off, mux->shift, mux->width);
+ assert(sel < mux->num_parents);
+ return mux->parents[sel];
+}
+
+static ulong do_k210_clk_get_rate(struct k210_clk_priv *priv, int id)
+{
+ int parent;
+ u32 val;
+ ulong parent_rate;
+ const struct k210_div_params *div;
+
+ if (id == K210_CLK_IN0)
+ return clk_get_rate(&priv->in0);
+
+ parent = k210_clk_get_parent(priv, id);
+ parent_rate = do_k210_clk_get_rate(priv, parent);
+
+ if (k210_clks[id].flags & K210_CLKF_PLL)
+ return k210_pll_get_rate(priv, k210_clks[id].pll, parent_rate);
+
+ if (k210_clks[id].div == K210_CLK_DIV_NONE)
+ return parent_rate;
+ div = &k210_divs[k210_clks[id].div];
+
+ if (div->type == K210_DIV_FIXED)
+ return parent_rate / div->div;
+
+ val = k210_clk_readl(priv, div->off, div->shift, div->width);
+ switch (div->type) {
+ case K210_DIV_ONE:
+ return parent_rate / (val + 1);
+ case K210_DIV_EVEN:
+ return parent_rate / 2 / (val + 1);
+ case K210_DIV_POWER:
+ /* This is ACLK, which has no divider on IN0 */
+ if (parent == K210_CLK_IN0)
+ return parent_rate;
+ return parent_rate / (2 << val);
+ default:
+ assert(false);
+ return -EINVAL;
+ };
+}
+
+static ulong k210_clk_get_rate(struct clk *clk)
+{
+ return do_k210_clk_get_rate(dev_get_priv(clk->dev), clk->id);
+}
+
+static int do_k210_clk_set_parent(struct k210_clk_priv *priv, int id, int new)
+{
+ int i;
+ const struct k210_mux_params *mux;
+
+ if (!(k210_clks[id].flags & K210_CLKF_MUX))
+ return -ENOSYS;
+ mux = &k210_muxes[k210_clks[id].mux];
+
+ for (i = 0; i < mux->num_parents; i++) {
+ if (mux->parents[i] == new) {
+ k210_clk_writel(priv, mux->off, mux->shift, mux->width,
+ i);
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static int k210_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ return do_k210_clk_set_parent(dev_get_priv(clk->dev), clk->id,
+ parent->id);
+}
+
+static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ int parent, ret, err;
+ ulong rate_in, val;
+ const struct k210_div_params *div;
+ struct k210_clk_priv *priv = dev_get_priv(clk->dev);
+
+ if (clk->id == K210_CLK_IN0)
+ return clk_set_rate(&priv->in0, rate);
+
+ parent = k210_clk_get_parent(priv, clk->id);
+ rate_in = do_k210_clk_get_rate(priv, parent);
+
+ log_debug("id=%ld rate=%lu rate_in=%lu\n", clk->id, rate, rate_in);
+
+ if (clk->id == K210_CLK_PLL0) {
+ /* Bypass ACLK so the CPU keeps going */
+ ret = do_k210_clk_set_parent(priv, K210_CLK_ACLK, K210_CLK_IN0);
+ if (ret)
+ return ret;
+ } else if (clk->id == K210_CLK_PLL1 && gd->flags & GD_FLG_RELOC) {
+ /*
+ * We can't bypass the AI clock like we can ACLK, and after
+ * relocation we are using the AI ram.
+ */
+ return -EPERM;
+ }
+
+ if (k210_clks[clk->id].flags & K210_CLKF_PLL) {
+ ret = k210_pll_set_rate(priv, k210_clks[clk->id].pll, rate,
+ rate_in);
+ if (!IS_ERR_VALUE(ret) && clk->id == K210_CLK_PLL0) {
+ /*
+ * This may have the side effect of reparenting ACLK,
+ * but I don't really want to keep track of what the old
+ * parent was.
+ */
+ err = do_k210_clk_set_parent(priv, K210_CLK_ACLK,
+ K210_CLK_PLL0);
+ if (err)
+ return err;
+ }
+ return ret;
+ }
+
+ if (k210_clks[clk->id].div == K210_CLK_DIV_NONE)
+ return -ENOSYS;
+ div = &k210_divs[k210_clks[clk->id].div];
+
+ switch (div->type) {
+ case K210_DIV_ONE:
+ val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, rate);
+ val = val ? val - 1 : 0;
+ break;
+ case K210_DIV_EVEN:
+ val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, 2 * rate);
+ break;
+ case K210_DIV_POWER:
+ /* This is ACLK, which has no divider on IN0 */
+ if (parent == K210_CLK_IN0)
+ return -ENOSYS;
+
+ val = DIV_ROUND_CLOSEST_ULL((u64)rate_in, rate);
+ val = __ffs(val);
+ break;
+ default:
+ assert(false);
+ return -EINVAL;
+ };
+
+ val = val ? val - 1 : 0;
+ k210_clk_writel(priv, div->off, div->shift, div->width, val);
+ return do_k210_clk_get_rate(priv, clk->id);
+}
+
+static int k210_clk_endisable(struct k210_clk_priv *priv, int id, bool enable)
+{
+ int parent = k210_clk_get_parent(priv, id);
+ const struct k210_gate_params *gate;
+
+ if (id == K210_CLK_IN0) {
+ if (enable)
+ return clk_enable(&priv->in0);
+ else
+ return clk_disable(&priv->in0);
+ }
+
+ /* Only recursively enable clocks since we don't track refcounts */
+ if (enable) {
+ int ret = k210_clk_endisable(priv, parent, true);
+
+ if (ret && ret != -ENOSYS)
+ return ret;
+ }
+
+ if (k210_clks[id].flags & K210_CLKF_PLL) {
+ if (enable)
+ return k210_pll_enable(priv, k210_clks[id].pll);
+ else
+ return k210_pll_disable(priv, k210_clks[id].pll);
+ }
+
+ if (k210_clks[id].gate == K210_CLK_GATE_NONE)
+ return -ENOSYS;
+ gate = &k210_gates[k210_clks[id].gate];
+
+ k210_clk_writel(priv, gate->off, gate->bit_idx, 1, enable);
+ return 0;
+}
+
+static int k210_clk_enable(struct clk *clk)
+{
+ return k210_clk_endisable(dev_get_priv(clk->dev), clk->id, true);
+}
+
+static int k210_clk_disable(struct clk *clk)
+{
+ return k210_clk_endisable(dev_get_priv(clk->dev), clk->id, false);
+}
+
+static int k210_clk_request(struct clk *clk)
+{
+ if (clk->id >= ARRAY_SIZE(k210_clks))
+ return -EINVAL;
+ return 0;
+}
+
+static const struct clk_ops k210_clk_ops = {
+ .request = k210_clk_request,
+ .set_rate = k210_clk_set_rate,
+ .get_rate = k210_clk_get_rate,
+ .set_parent = k210_clk_set_parent,
+ .enable = k210_clk_enable,
+ .disable = k210_clk_disable,
+};
+
+static int k210_clk_probe(struct udevice *dev)
+{
+ int ret;
+ struct k210_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr_ptr(dev_get_parent(dev));
+ if (!priv->base)
+ return -EINVAL;
+
+ ret = clk_get_by_index(dev, 0, &priv->in0);
+ if (ret)
+ return ret;
+
+ /*
+ * Force setting defaults, even before relocation. This is so we can
+ * set the clock rate for PLL1 before we relocate into aisram.
+ */
+ if (!(gd->flags & GD_FLG_RELOC))
+ clk_set_defaults(dev, CLK_DEFAULTS_POST_FORCE);
+
+ return 0;
+}
+
+static const struct udevice_id k210_clk_ids[] = {
+ { .compatible = "kendryte,k210-clk" },
+ { },
+};
+
+U_BOOT_DRIVER(k210_clk) = {
+ .name = "k210_clk",
+ .id = UCLASS_CLK,
+ .of_match = k210_clk_ids,
+ .ops = &k210_clk_ops,
+ .probe = k210_clk_probe,
+ .priv_auto = sizeof(struct k210_clk_priv),
+};
+
+#if CONFIG_IS_ENABLED(CMD_CLK)
+static char show_enabled(struct k210_clk_priv *priv, int id)
+{
+ bool enabled;
+
+ if (k210_clks[id].flags & K210_CLKF_PLL) {
+ const struct k210_pll_params *pll =
+ &k210_plls[k210_clks[id].pll];
+
+ enabled = k210_pll_enabled(readl(priv->base + pll->off));
+ } else if (k210_clks[id].gate == K210_CLK_GATE_NONE) {
+ return '-';
+ } else {
+ const struct k210_gate_params *gate =
+ &k210_gates[k210_clks[id].gate];
+
+ enabled = k210_clk_readl(priv, gate->off, gate->bit_idx, 1);
+ }
+
+ return enabled ? 'y' : 'n';
+}
+
+static void show_clks(struct k210_clk_priv *priv, int id, int depth)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(k210_clks); i++) {
+ if (k210_clk_get_parent(priv, i) != id)
+ continue;
+
+ printf(" %-9lu %-7c %*s%s\n", do_k210_clk_get_rate(priv, i),
+ show_enabled(priv, i), depth * 4, "",
+ k210_clks[i].name);
+
+ show_clks(priv, i, depth + 1);
+ }
+}
+
+int soc_clk_dump(void)
+{
+ int ret;
+ struct udevice *dev;
+ struct k210_clk_priv *priv;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK, DM_DRIVER_GET(k210_clk),
+ &dev);
+ if (ret)
+ return ret;
+ priv = dev_get_priv(dev);
+
+ puts(" Rate Enabled Name\n");
+ puts("------------------------\n");
+ printf(" %-9lu %-7c %*s%s\n", clk_get_rate(&priv->in0), 'y', 0, "",
+ priv->in0.dev->name);
+ show_clks(priv, K210_CLK_IN0, 1);
+ return 0;
+}
+#endif
diff --git a/drivers/clk/kendryte/Kconfig b/drivers/clk/kendryte/Kconfig
deleted file mode 100644
index 073fca0..0000000
--- a/drivers/clk/kendryte/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-config CLK_K210
- bool "Clock support for Kendryte K210"
- depends on CLK && CLK_CCF && CLK_COMPOSITE_CCF
- help
- This enables support clock driver for Kendryte K210 platforms.
-
-config CLK_K210_SET_RATE
- bool "Enable setting the Kendryte K210 PLL rate"
- depends on CLK_K210
- help
- Add functionality to calculate new rates for K210 PLLs. Enabling this
- feature adds around 1K to U-Boot's final size.
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
deleted file mode 100644
index 6fb6825..0000000
--- a/drivers/clk/kendryte/Makefile
+++ /dev/null
@@ -1 +0,0 @@
-obj-y += bypass.o clk.o pll.o
diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
deleted file mode 100644
index bbdbd9a..0000000
--- a/drivers/clk/kendryte/bypass.c
+++ /dev/null
@@ -1,273 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
- */
-
-#define LOG_CATEGORY UCLASS_CLK
-
-#include <common.h>
-#include <clk.h>
-#include <clk-uclass.h>
-#include <dm.h>
-#include <log.h>
-#include <kendryte/bypass.h>
-#include <linux/clk-provider.h>
-#include <linux/err.h>
-
-#define CLK_K210_BYPASS "k210_clk_bypass"
-
-/*
- * This is a small driver to do a software bypass of a clock if hardware bypass
- * is not working. I have tried to write this in a generic fashion, so that it
- * could be potentially broken out of the kendryte code at some future date.
- *
- * Say you have the following clock configuration
- *
- * +---+ +---+
- * |osc| |pll|
- * +---+ +---+
- * ^
- * /|
- * / |
- * / |
- * / |
- * / |
- * +---+ +---+
- * |clk| |clk|
- * +---+ +---+
- *
- * But the pll does not have a bypass, so when you configure the pll, the
- * configuration needs to change to look like
- *
- * +---+ +---+
- * |osc| |pll|
- * +---+ +---+
- * ^
- * |\
- * | \
- * | \
- * | \
- * | \
- * +---+ +---+
- * |clk| |clk|
- * +---+ +---+
- *
- * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
- * creating the child clocks, set their parent to the bypass clock. After
- * creating all the children, call k210_bypass_setchildren().
- */
-
-static int k210_bypass_dobypass(struct k210_bypass *bypass)
-{
- int ret, i;
-
- /*
- * If we already have saved parents, then the children are already
- * bypassed
- */
- if (bypass->child_count && bypass->saved_parents[0])
- return 0;
-
- for (i = 0; i < bypass->child_count; i++) {
- struct clk *child = bypass->children[i];
- struct clk *parent = clk_get_parent(child);
-
- if (IS_ERR(parent)) {
- for (; i; i--)
- bypass->saved_parents[i] = NULL;
- return PTR_ERR(parent);
- }
- bypass->saved_parents[i] = parent;
- }
-
- for (i = 0; i < bypass->child_count; i++) {
- struct clk *child = bypass->children[i];
-
- ret = clk_set_parent(child, bypass->alt);
- if (ret) {
- for (; i; i--)
- clk_set_parent(bypass->children[i],
- bypass->saved_parents[i]);
- for (i = 0; i < bypass->child_count; i++)
- bypass->saved_parents[i] = NULL;
- return ret;
- }
- }
-
- return 0;
-}
-
-static int k210_bypass_unbypass(struct k210_bypass *bypass)
-{
- int err, ret, i;
-
- if (!bypass->child_count && !bypass->saved_parents[0]) {
- log_warning("Cannot unbypass children; dobypass not called first\n");
- return 0;
- }
-
- ret = 0;
- for (i = 0; i < bypass->child_count; i++) {
- err = clk_set_parent(bypass->children[i],
- bypass->saved_parents[i]);
- if (err)
- ret = err;
- bypass->saved_parents[i] = NULL;
- }
- return ret;
-}
-
-static ulong k210_bypass_get_rate(struct clk *clk)
-{
- struct k210_bypass *bypass = to_k210_bypass(clk);
- const struct clk_ops *ops = bypass->bypassee_ops;
-
- if (ops->get_rate)
- return ops->get_rate(bypass->bypassee);
- else
- return clk_get_parent_rate(bypass->bypassee);
-}
-
-static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret;
- struct k210_bypass *bypass = to_k210_bypass(clk);
- const struct clk_ops *ops = bypass->bypassee_ops;
-
- /* Don't bother bypassing if we aren't going to set the rate */
- if (!ops->set_rate)
- return k210_bypass_get_rate(clk);
-
- ret = k210_bypass_dobypass(bypass);
- if (ret)
- return ret;
-
- ret = ops->set_rate(bypass->bypassee, rate);
- if (ret < 0)
- return ret;
-
- return k210_bypass_unbypass(bypass);
-}
-
-static int k210_bypass_set_parent(struct clk *clk, struct clk *parent)
-{
- struct k210_bypass *bypass = to_k210_bypass(clk);
- const struct clk_ops *ops = bypass->bypassee_ops;
-
- if (ops->set_parent)
- return ops->set_parent(bypass->bypassee, parent);
- else
- return -EINVAL;
-}
-
-/*
- * For these next two functions, do the bypassing even if there is no
- * en-/-disable function, since the bypassing itself can be observed in between
- * calls.
- */
-static int k210_bypass_enable(struct clk *clk)
-{
- int ret;
- struct k210_bypass *bypass = to_k210_bypass(clk);
- const struct clk_ops *ops = bypass->bypassee_ops;
-
- ret = k210_bypass_dobypass(bypass);
- if (ret)
- return ret;
-
- if (ops->enable)
- ret = ops->enable(bypass->bypassee);
- else
- ret = 0;
- if (ret)
- return ret;
-
- return k210_bypass_unbypass(bypass);
-}
-
-static int k210_bypass_disable(struct clk *clk)
-{
- int ret;
- struct k210_bypass *bypass = to_k210_bypass(clk);
- const struct clk_ops *ops = bypass->bypassee_ops;
-
- ret = k210_bypass_dobypass(bypass);
- if (ret)
- return ret;
-
- if (ops->disable)
- return ops->disable(bypass->bypassee);
- else
- return 0;
-}
-
-static const struct clk_ops k210_bypass_ops = {
- .get_rate = k210_bypass_get_rate,
- .set_rate = k210_bypass_set_rate,
- .set_parent = k210_bypass_set_parent,
- .enable = k210_bypass_enable,
- .disable = k210_bypass_disable,
-};
-
-int k210_bypass_set_children(struct clk *clk, struct clk **children,
- size_t child_count)
-{
- struct k210_bypass *bypass = to_k210_bypass(clk);
-
- kfree(bypass->saved_parents);
- if (child_count) {
- bypass->saved_parents =
- kcalloc(child_count, sizeof(struct clk *), GFP_KERNEL);
- if (!bypass->saved_parents)
- return -ENOMEM;
- }
- bypass->child_count = child_count;
- bypass->children = children;
-
- return 0;
-}
-
-struct clk *k210_register_bypass_struct(const char *name,
- const char *parent_name,
- struct k210_bypass *bypass)
-{
- int ret;
- struct clk *clk;
-
- clk = &bypass->clk;
-
- ret = clk_register(clk, CLK_K210_BYPASS, name, parent_name);
- if (ret)
- return ERR_PTR(ret);
-
- bypass->bypassee->dev = clk->dev;
- return clk;
-}
-
-struct clk *k210_register_bypass(const char *name, const char *parent_name,
- struct clk *bypassee,
- const struct clk_ops *bypassee_ops,
- struct clk *alt)
-{
- struct clk *clk;
- struct k210_bypass *bypass;
-
- bypass = kzalloc(sizeof(*bypass), GFP_KERNEL);
- if (!bypass)
- return ERR_PTR(-ENOMEM);
-
- bypass->bypassee = bypassee;
- bypass->bypassee_ops = bypassee_ops;
- bypass->alt = alt;
-
- clk = k210_register_bypass_struct(name, parent_name, bypass);
- if (IS_ERR(clk))
- kfree(bypass);
- return clk;
-}
-
-U_BOOT_DRIVER(k210_bypass) = {
- .name = CLK_K210_BYPASS,
- .id = UCLASS_CLK,
- .ops = &k210_bypass_ops,
-};
diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c
deleted file mode 100644
index 3b674a9..0000000
--- a/drivers/clk/kendryte/clk.c
+++ /dev/null
@@ -1,666 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
- */
-#include <kendryte/clk.h>
-
-#include <asm/io.h>
-#include <dt-bindings/clock/k210-sysctl.h>
-#include <dt-bindings/mfd/k210-sysctl.h>
-#include <dm.h>
-#include <log.h>
-#include <mapmem.h>
-
-#include <kendryte/bypass.h>
-#include <kendryte/pll.h>
-
-/* All methods are delegated to CCF clocks */
-
-static ulong k210_clk_get_rate(struct clk *clk)
-{
- struct clk *c;
- int err = clk_get_by_id(clk->id, &c);
-
- if (err)
- return err;
- return clk_get_rate(c);
-}
-
-static ulong k210_clk_set_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *c;
- int err = clk_get_by_id(clk->id, &c);
-
- if (err)
- return err;
- return clk_set_rate(c, rate);
-}
-
-static int k210_clk_set_parent(struct clk *clk, struct clk *parent)
-{
- struct clk *c, *p;
- int err = clk_get_by_id(clk->id, &c);
-
- if (err)
- return err;
-
- err = clk_get_by_id(parent->id, &p);
- if (err)
- return err;
-
- return clk_set_parent(c, p);
-}
-
-static int k210_clk_endisable(struct clk *clk, bool enable)
-{
- struct clk *c;
- int err = clk_get_by_id(clk->id, &c);
-
- if (err)
- return err;
- return enable ? clk_enable(c) : clk_disable(c);
-}
-
-static int k210_clk_enable(struct clk *clk)
-{
- return k210_clk_endisable(clk, true);
-}
-
-static int k210_clk_disable(struct clk *clk)
-{
- return k210_clk_endisable(clk, false);
-}
-
-static const struct clk_ops k210_clk_ops = {
- .set_rate = k210_clk_set_rate,
- .get_rate = k210_clk_get_rate,
- .set_parent = k210_clk_set_parent,
- .enable = k210_clk_enable,
- .disable = k210_clk_disable,
-};
-
-/* Parents for muxed clocks */
-static const char * const generic_sels[] = { "in0_half", "pll0_half" };
-/* The first clock is in0, which is filled in by k210_clk_probe */
-static const char *aclk_sels[] = { NULL, "pll0_half" };
-static const char *pll2_sels[] = { NULL, "pll0", "pll1" };
-
-/*
- * All parameters for different sub-clocks are collected into parameter arrays.
- * These parameters are then initialized by the clock which uses them during
- * probe. To save space, ids are automatically generated for each sub-clock by
- * using an enum. Instead of storing a parameter struct for each clock, even for
- * those clocks which don't use a particular type of sub-clock, we can just
- * store the parameters for the clocks which need them.
- *
- * So why do it like this? Arranging all the sub-clocks together makes it very
- * easy to find bugs in the code.
- */
-
-#define DIV(id, off, shift, width) DIV_FLAGS(id, off, shift, width, 0)
-#define DIV_LIST \
- DIV_FLAGS(K210_CLK_ACLK, K210_SYSCTL_SEL0, 1, 2, \
- CLK_DIVIDER_POWER_OF_TWO) \
- DIV(K210_CLK_APB0, K210_SYSCTL_SEL0, 3, 3) \
- DIV(K210_CLK_APB1, K210_SYSCTL_SEL0, 6, 3) \
- DIV(K210_CLK_APB2, K210_SYSCTL_SEL0, 9, 3) \
- DIV(K210_CLK_SRAM0, K210_SYSCTL_THR0, 0, 4) \
- DIV(K210_CLK_SRAM1, K210_SYSCTL_THR0, 4, 4) \
- DIV(K210_CLK_AI, K210_SYSCTL_THR0, 8, 4) \
- DIV(K210_CLK_DVP, K210_SYSCTL_THR0, 12, 4) \
- DIV(K210_CLK_ROM, K210_SYSCTL_THR0, 16, 4) \
- DIV(K210_CLK_SPI0, K210_SYSCTL_THR1, 0, 8) \
- DIV(K210_CLK_SPI1, K210_SYSCTL_THR1, 8, 8) \
- DIV(K210_CLK_SPI2, K210_SYSCTL_THR1, 16, 8) \
- DIV(K210_CLK_SPI3, K210_SYSCTL_THR1, 24, 8) \
- DIV(K210_CLK_TIMER0, K210_SYSCTL_THR2, 0, 8) \
- DIV(K210_CLK_TIMER1, K210_SYSCTL_THR2, 8, 8) \
- DIV(K210_CLK_TIMER2, K210_SYSCTL_THR2, 16, 8) \
- DIV(K210_CLK_I2S0, K210_SYSCTL_THR3, 0, 16) \
- DIV(K210_CLK_I2S1, K210_SYSCTL_THR3, 16, 16) \
- DIV(K210_CLK_I2S2, K210_SYSCTL_THR4, 0, 16) \
- DIV(K210_CLK_I2S0_M, K210_SYSCTL_THR4, 16, 8) \
- DIV(K210_CLK_I2S1_M, K210_SYSCTL_THR4, 24, 8) \
- DIV(K210_CLK_I2S2_M, K210_SYSCTL_THR4, 0, 8) \
- DIV(K210_CLK_I2C0, K210_SYSCTL_THR5, 8, 8) \
- DIV(K210_CLK_I2C1, K210_SYSCTL_THR5, 16, 8) \
- DIV(K210_CLK_I2C2, K210_SYSCTL_THR5, 24, 8) \
- DIV(K210_CLK_WDT0, K210_SYSCTL_THR6, 0, 8) \
- DIV(K210_CLK_WDT1, K210_SYSCTL_THR6, 8, 8)
-
-#define _DIVIFY(id) K210_CLK_DIV_##id
-#define DIVIFY(id) _DIVIFY(id)
-
-enum k210_div_ids {
-#define DIV_FLAGS(id, ...) DIVIFY(id),
- DIV_LIST
-#undef DIV_FLAGS
-};
-
-struct k210_div_params {
- u8 off;
- u8 shift;
- u8 width;
- u8 flags;
-};
-
-static const struct k210_div_params k210_divs[] = {
-#define DIV_FLAGS(id, _off, _shift, _width, _flags) \
- [DIVIFY(id)] = { \
- .off = (_off), \
- .shift = (_shift), \
- .width = (_width), \
- .flags = (_flags), \
- },
- DIV_LIST
-#undef DIV_FLAGS
-};
-
-#undef DIV
-#undef DIV_LIST
-
-#define GATE_LIST \
- GATE(K210_CLK_CPU, K210_SYSCTL_EN_CENT, 0) \
- GATE(K210_CLK_SRAM0, K210_SYSCTL_EN_CENT, 1) \
- GATE(K210_CLK_SRAM1, K210_SYSCTL_EN_CENT, 2) \
- GATE(K210_CLK_APB0, K210_SYSCTL_EN_CENT, 3) \
- GATE(K210_CLK_APB1, K210_SYSCTL_EN_CENT, 4) \
- GATE(K210_CLK_APB2, K210_SYSCTL_EN_CENT, 5) \
- GATE(K210_CLK_ROM, K210_SYSCTL_EN_PERI, 0) \
- GATE(K210_CLK_DMA, K210_SYSCTL_EN_PERI, 1) \
- GATE(K210_CLK_AI, K210_SYSCTL_EN_PERI, 2) \
- GATE(K210_CLK_DVP, K210_SYSCTL_EN_PERI, 3) \
- GATE(K210_CLK_FFT, K210_SYSCTL_EN_PERI, 4) \
- GATE(K210_CLK_GPIO, K210_SYSCTL_EN_PERI, 5) \
- GATE(K210_CLK_SPI0, K210_SYSCTL_EN_PERI, 6) \
- GATE(K210_CLK_SPI1, K210_SYSCTL_EN_PERI, 7) \
- GATE(K210_CLK_SPI2, K210_SYSCTL_EN_PERI, 8) \
- GATE(K210_CLK_SPI3, K210_SYSCTL_EN_PERI, 9) \
- GATE(K210_CLK_I2S0, K210_SYSCTL_EN_PERI, 10) \
- GATE(K210_CLK_I2S1, K210_SYSCTL_EN_PERI, 11) \
- GATE(K210_CLK_I2S2, K210_SYSCTL_EN_PERI, 12) \
- GATE(K210_CLK_I2C0, K210_SYSCTL_EN_PERI, 13) \
- GATE(K210_CLK_I2C1, K210_SYSCTL_EN_PERI, 14) \
- GATE(K210_CLK_I2C2, K210_SYSCTL_EN_PERI, 15) \
- GATE(K210_CLK_UART1, K210_SYSCTL_EN_PERI, 16) \
- GATE(K210_CLK_UART2, K210_SYSCTL_EN_PERI, 17) \
- GATE(K210_CLK_UART3, K210_SYSCTL_EN_PERI, 18) \
- GATE(K210_CLK_AES, K210_SYSCTL_EN_PERI, 19) \
- GATE(K210_CLK_FPIOA, K210_SYSCTL_EN_PERI, 20) \
- GATE(K210_CLK_TIMER0, K210_SYSCTL_EN_PERI, 21) \
- GATE(K210_CLK_TIMER1, K210_SYSCTL_EN_PERI, 22) \
- GATE(K210_CLK_TIMER2, K210_SYSCTL_EN_PERI, 23) \
- GATE(K210_CLK_WDT0, K210_SYSCTL_EN_PERI, 24) \
- GATE(K210_CLK_WDT1, K210_SYSCTL_EN_PERI, 25) \
- GATE(K210_CLK_SHA, K210_SYSCTL_EN_PERI, 26) \
- GATE(K210_CLK_OTP, K210_SYSCTL_EN_PERI, 27) \
- GATE(K210_CLK_RTC, K210_SYSCTL_EN_PERI, 29)
-
-#define _GATEIFY(id) K210_CLK_GATE_##id
-#define GATEIFY(id) _GATEIFY(id)
-
-enum k210_gate_ids {
-#define GATE(id, ...) GATEIFY(id),
- GATE_LIST
-#undef GATE
-};
-
-struct k210_gate_params {
- u8 off;
- u8 bit_idx;
-};
-
-static const struct k210_gate_params k210_gates[] = {
-#define GATE(id, _off, _idx) \
- [GATEIFY(id)] = { \
- .off = (_off), \
- .bit_idx = (_idx), \
- },
- GATE_LIST
-#undef GATE
-};
-
-#undef GATE_LIST
-
-#define MUX(id, reg, shift, width) \
- MUX_PARENTS(id, generic_sels, reg, shift, width)
-#define MUX_LIST \
- MUX_PARENTS(K210_CLK_PLL2, pll2_sels, K210_SYSCTL_PLL2, 26, 2) \
- MUX_PARENTS(K210_CLK_ACLK, aclk_sels, K210_SYSCTL_SEL0, 0, 1) \
- MUX(K210_CLK_SPI3, K210_SYSCTL_SEL0, 12, 1) \
- MUX(K210_CLK_TIMER0, K210_SYSCTL_SEL0, 13, 1) \
- MUX(K210_CLK_TIMER1, K210_SYSCTL_SEL0, 14, 1) \
- MUX(K210_CLK_TIMER2, K210_SYSCTL_SEL0, 15, 1)
-
-#define _MUXIFY(id) K210_CLK_MUX_##id
-#define MUXIFY(id) _MUXIFY(id)
-
-enum k210_mux_ids {
-#define MUX_PARENTS(id, ...) MUXIFY(id),
- MUX_LIST
-#undef MUX_PARENTS
- K210_CLK_MUX_NONE,
-};
-
-struct k210_mux_params {
- const char *const *parent_names;
- u8 num_parents;
- u8 off;
- u8 shift;
- u8 width;
-};
-
-static const struct k210_mux_params k210_muxes[] = {
-#define MUX_PARENTS(id, parents, _off, _shift, _width) \
- [MUXIFY(id)] = { \
- .parent_names = (const char * const *)(parents), \
- .num_parents = ARRAY_SIZE(parents), \
- .off = (_off), \
- .shift = (_shift), \
- .width = (_width), \
- },
- MUX_LIST
-#undef MUX_PARENTS
-};
-
-#undef MUX
-#undef MUX_LIST
-
-struct k210_pll_params {
- u8 off;
- u8 lock_off;
- u8 shift;
- u8 width;
-};
-
-static const struct k210_pll_params k210_plls[] = {
-#define PLL(_off, _shift, _width) { \
- .off = (_off), \
- .lock_off = K210_SYSCTL_PLL_LOCK, \
- .shift = (_shift), \
- .width = (_width), \
-}
- [0] = PLL(K210_SYSCTL_PLL0, 0, 2),
- [1] = PLL(K210_SYSCTL_PLL1, 8, 1),
- [2] = PLL(K210_SYSCTL_PLL2, 16, 1),
-#undef PLL
-};
-
-#define COMP(id) \
- COMP_FULL(id, MUXIFY(id), DIVIFY(id), GATEIFY(id))
-#define COMP_NOMUX(id) \
- COMP_FULL(id, K210_CLK_MUX_NONE, DIVIFY(id), GATEIFY(id))
-#define COMP_LIST \
- COMP(K210_CLK_SPI3) \
- COMP(K210_CLK_TIMER0) \
- COMP(K210_CLK_TIMER1) \
- COMP(K210_CLK_TIMER2) \
- COMP_NOMUX(K210_CLK_SRAM0) \
- COMP_NOMUX(K210_CLK_SRAM1) \
- COMP_NOMUX(K210_CLK_ROM) \
- COMP_NOMUX(K210_CLK_DVP) \
- COMP_NOMUX(K210_CLK_APB0) \
- COMP_NOMUX(K210_CLK_APB1) \
- COMP_NOMUX(K210_CLK_APB2) \
- COMP_NOMUX(K210_CLK_AI) \
- COMP_NOMUX(K210_CLK_I2S0) \
- COMP_NOMUX(K210_CLK_I2S1) \
- COMP_NOMUX(K210_CLK_I2S2) \
- COMP_NOMUX(K210_CLK_WDT0) \
- COMP_NOMUX(K210_CLK_WDT1) \
- COMP_NOMUX(K210_CLK_SPI0) \
- COMP_NOMUX(K210_CLK_SPI1) \
- COMP_NOMUX(K210_CLK_SPI2) \
- COMP_NOMUX(K210_CLK_I2C0) \
- COMP_NOMUX(K210_CLK_I2C1) \
- COMP_NOMUX(K210_CLK_I2C2)
-
-#define _COMPIFY(id) K210_CLK_COMP_##id
-#define COMPIFY(id) _COMPIFY(id)
-
-enum k210_comp_ids {
-#define COMP_FULL(id, ...) COMPIFY(id),
- COMP_LIST
-#undef COMP_FULL
-};
-
-struct k210_comp_params {
- u8 mux;
- u8 div;
- u8 gate;
-};
-
-static const struct k210_comp_params k210_comps[] = {
-#define COMP_FULL(id, _mux, _div, _gate) \
- [COMPIFY(id)] = { \
- .mux = (_mux), \
- .div = (_div), \
- .gate = (_gate), \
- },
- COMP_LIST
-#undef COMP_FULL
-};
-
-#undef COMP
-#undef COMP_ID
-#undef COMP_NOMUX
-#undef COMP_NOMUX_ID
-#undef COMP_LIST
-
-static struct clk *k210_bypass_children = {
- NULL,
-};
-
-/* Helper functions to create sub-clocks */
-static struct clk_mux *k210_create_mux(const struct k210_mux_params *params,
- void *base)
-{
- struct clk_mux *mux = kzalloc(sizeof(*mux), GFP_KERNEL);
-
- if (!mux)
- return mux;
-
- mux->reg = base + params->off;
- mux->mask = BIT(params->width) - 1;
- mux->shift = params->shift;
- mux->parent_names = params->parent_names;
- mux->num_parents = params->num_parents;
-
- return mux;
-}
-
-static struct clk_divider *k210_create_div(const struct k210_div_params *params,
- void *base)
-{
- struct clk_divider *div = kzalloc(sizeof(*div), GFP_KERNEL);
-
- if (!div)
- return div;
-
- div->reg = base + params->off;
- div->shift = params->shift;
- div->width = params->width;
- div->flags = params->flags;
-
- return div;
-}
-
-static struct clk_gate *k210_create_gate(const struct k210_gate_params *params,
- void *base)
-{
- struct clk_gate *gate = kzalloc(sizeof(*gate), GFP_KERNEL);
-
- if (!gate)
- return gate;
-
- gate->reg = base + params->off;
- gate->bit_idx = params->bit_idx;
-
- return gate;
-}
-
-static struct k210_pll *k210_create_pll(const struct k210_pll_params *params,
- void *base)
-{
- struct k210_pll *pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-
- if (!pll)
- return pll;
-
- pll->reg = base + params->off;
- pll->lock = base + params->lock_off;
- pll->shift = params->shift;
- pll->width = params->width;
-
- return pll;
-}
-
-/* Create all sub-clocks, and then register the composite clock */
-static struct clk *k210_register_comp(const struct k210_comp_params *params,
- void *base, const char *name,
- const char *parent)
-{
- const char *const *parent_names;
- int num_parents;
- struct clk *comp;
- const struct clk_ops *mux_ops;
- struct clk_mux *mux;
- struct clk_divider *div;
- struct clk_gate *gate;
-
- if (params->mux == K210_CLK_MUX_NONE) {
- if (!parent)
- return ERR_PTR(-EINVAL);
-
- mux_ops = NULL;
- mux = NULL;
- parent_names = &parent;
- num_parents = 1;
- } else {
- mux_ops = &clk_mux_ops;
- mux = k210_create_mux(&k210_muxes[params->mux], base);
- if (!mux)
- return ERR_PTR(-ENOMEM);
-
- parent_names = mux->parent_names;
- num_parents = mux->num_parents;
- }
-
- div = k210_create_div(&k210_divs[params->div], base);
- if (!div) {
- comp = ERR_PTR(-ENOMEM);
- goto cleanup_mux;
- }
-
- gate = k210_create_gate(&k210_gates[params->gate], base);
- if (!gate) {
- comp = ERR_PTR(-ENOMEM);
- goto cleanup_div;
- }
-
- comp = clk_register_composite(NULL, name, parent_names, num_parents,
- &mux->clk, mux_ops,
- &div->clk, &clk_divider_ops,
- &gate->clk, &clk_gate_ops, 0);
- if (IS_ERR(comp))
- goto cleanup_gate;
- return comp;
-
-cleanup_gate:
- free(gate);
-cleanup_div:
- free(div);
-cleanup_mux:
- free(mux);
- return comp;
-}
-
-static bool probed;
-
-static int k210_clk_probe(struct udevice *dev)
-{
- int ret;
- const char *in0;
- struct clk *in0_clk, *bypass;
- struct clk_mux *mux;
- struct clk_divider *div;
- struct k210_pll *pll;
- void *base;
-
- /*
- * Only one instance of this driver allowed. This prevents weird bugs
- * when the driver fails part-way through probing. Some clocks will
- * already have been registered, and re-probing will register them
- * again, creating a bunch of duplicates. Better error-handling/cleanup
- * could fix this, but it's Probably Not Worth It (TM).
- */
- if (probed)
- return -EINVAL;
-
- base = dev_read_addr_ptr(dev_get_parent(dev));
- if (!base)
- return -EINVAL;
-
- in0_clk = kzalloc(sizeof(*in0_clk), GFP_KERNEL);
- if (!in0_clk)
- return -ENOMEM;
-
- ret = clk_get_by_index(dev, 0, in0_clk);
- if (ret)
- return ret;
- in0 = in0_clk->dev->name;
-
- probed = true;
-
- aclk_sels[0] = in0;
- pll2_sels[0] = in0;
-
- /*
- * All PLLs have a broken bypass, but pll0 has the CPU downstream, so we
- * need to manually reparent it whenever we configure pll0
- */
- pll = k210_create_pll(&k210_plls[0], base);
- if (pll) {
- bypass = k210_register_bypass("pll0", in0, &pll->clk,
- &k210_pll_ops, in0_clk);
- clk_dm(K210_CLK_PLL0, bypass);
- } else {
- return -ENOMEM;
- }
-
- {
- const struct k210_pll_params *params = &k210_plls[1];
-
- clk_dm(K210_CLK_PLL1,
- k210_register_pll("pll1", in0, base + params->off,
- base + params->lock_off, params->shift,
- params->width));
- }
-
- /* PLL2 is muxed, so set up a composite clock */
- mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_PLL2)], base);
- pll = k210_create_pll(&k210_plls[2], base);
- if (!mux || !pll) {
- free(mux);
- free(pll);
- } else {
- clk_dm(K210_CLK_PLL2,
- clk_register_composite(NULL, "pll2", pll2_sels,
- ARRAY_SIZE(pll2_sels),
- &mux->clk, &clk_mux_ops,
- &pll->clk, &k210_pll_ops,
- &pll->clk, &k210_pll_ops, 0));
- }
-
- /* Half-frequency clocks for "even" dividers */
- clk_dm(K210_CLK_IN0_H, k210_clk_half("in0_half", in0));
- clk_dm(K210_CLK_PLL0_H, k210_clk_half("pll0_half", "pll0"));
- clk_dm(K210_CLK_PLL2_H, k210_clk_half("pll2_half", "pll2"));
-
- /* ACLK has no gate */
- mux = k210_create_mux(&k210_muxes[MUXIFY(K210_CLK_ACLK)], base);
- div = k210_create_div(&k210_divs[DIVIFY(K210_CLK_ACLK)], base);
- if (!mux || !div) {
- free(mux);
- free(div);
- } else {
- struct clk *aclk =
- clk_register_composite(NULL, "aclk", aclk_sels,
- ARRAY_SIZE(aclk_sels),
- &mux->clk, &clk_mux_ops,
- &div->clk, &clk_divider_ops,
- NULL, NULL, 0);
- clk_dm(K210_CLK_ACLK, aclk);
- if (!IS_ERR(aclk)) {
- k210_bypass_children = aclk;
- k210_bypass_set_children(bypass,
- &k210_bypass_children, 1);
- }
- }
-
-#define REGISTER_COMP(id, name) \
- clk_dm(id, \
- k210_register_comp(&k210_comps[COMPIFY(id)], base, name, NULL))
- REGISTER_COMP(K210_CLK_SPI3, "spi3");
- REGISTER_COMP(K210_CLK_TIMER0, "timer0");
- REGISTER_COMP(K210_CLK_TIMER1, "timer1");
- REGISTER_COMP(K210_CLK_TIMER2, "timer2");
-#undef REGISTER_COMP
-
- /* Dividing clocks, no mux */
-#define REGISTER_COMP_NOMUX(id, name, parent) \
- clk_dm(id, \
- k210_register_comp(&k210_comps[COMPIFY(id)], base, name, parent))
- REGISTER_COMP_NOMUX(K210_CLK_SRAM0, "sram0", "aclk");
- REGISTER_COMP_NOMUX(K210_CLK_SRAM1, "sram1", "aclk");
- REGISTER_COMP_NOMUX(K210_CLK_ROM, "rom", "aclk");
- REGISTER_COMP_NOMUX(K210_CLK_DVP, "dvp", "aclk");
- REGISTER_COMP_NOMUX(K210_CLK_APB0, "apb0", "aclk");
- REGISTER_COMP_NOMUX(K210_CLK_APB1, "apb1", "aclk");
- REGISTER_COMP_NOMUX(K210_CLK_APB2, "apb2", "aclk");
- REGISTER_COMP_NOMUX(K210_CLK_AI, "ai", "pll1");
- REGISTER_COMP_NOMUX(K210_CLK_I2S0, "i2s0", "pll2_half");
- REGISTER_COMP_NOMUX(K210_CLK_I2S1, "i2s1", "pll2_half");
- REGISTER_COMP_NOMUX(K210_CLK_I2S2, "i2s2", "pll2_half");
- REGISTER_COMP_NOMUX(K210_CLK_WDT0, "wdt0", "in0_half");
- REGISTER_COMP_NOMUX(K210_CLK_WDT1, "wdt1", "in0_half");
- REGISTER_COMP_NOMUX(K210_CLK_SPI0, "spi0", "pll0_half");
- REGISTER_COMP_NOMUX(K210_CLK_SPI1, "spi1", "pll0_half");
- REGISTER_COMP_NOMUX(K210_CLK_SPI2, "spi2", "pll0_half");
- REGISTER_COMP_NOMUX(K210_CLK_I2C0, "i2c0", "pll0_half");
- REGISTER_COMP_NOMUX(K210_CLK_I2C1, "i2c1", "pll0_half");
- REGISTER_COMP_NOMUX(K210_CLK_I2C2, "i2c2", "pll0_half");
-#undef REGISTER_COMP_NOMUX
-
- /* Dividing clocks */
-#define REGISTER_DIV(id, name, parent) do {\
- const struct k210_div_params *params = &k210_divs[DIVIFY(id)]; \
- clk_dm(id, \
- clk_register_divider(NULL, name, parent, 0, base + params->off, \
- params->shift, params->width, 0)); \
-} while (false)
- REGISTER_DIV(K210_CLK_I2S0_M, "i2s0_m", "pll2_half");
- REGISTER_DIV(K210_CLK_I2S1_M, "i2s1_m", "pll2_half");
- REGISTER_DIV(K210_CLK_I2S2_M, "i2s2_m", "pll2_half");
-#undef REGISTER_DIV
-
- /* Gated clocks */
-#define REGISTER_GATE(id, name, parent) do { \
- const struct k210_gate_params *params = &k210_gates[GATEIFY(id)]; \
- clk_dm(id, \
- clk_register_gate(NULL, name, parent, 0, base + params->off, \
- params->bit_idx, 0, NULL)); \
-} while (false)
- REGISTER_GATE(K210_CLK_CPU, "cpu", "aclk");
- REGISTER_GATE(K210_CLK_DMA, "dma", "aclk");
- REGISTER_GATE(K210_CLK_FFT, "fft", "aclk");
- REGISTER_GATE(K210_CLK_GPIO, "gpio", "apb0");
- REGISTER_GATE(K210_CLK_UART1, "uart1", "apb0");
- REGISTER_GATE(K210_CLK_UART2, "uart2", "apb0");
- REGISTER_GATE(K210_CLK_UART3, "uart3", "apb0");
- REGISTER_GATE(K210_CLK_FPIOA, "fpioa", "apb0");
- REGISTER_GATE(K210_CLK_SHA, "sha", "apb0");
- REGISTER_GATE(K210_CLK_AES, "aes", "apb1");
- REGISTER_GATE(K210_CLK_OTP, "otp", "apb1");
- REGISTER_GATE(K210_CLK_RTC, "rtc", in0);
-#undef REGISTER_GATE
-
- /* The MTIME register in CLINT runs at one 50th the CPU clock speed */
- clk_dm(K210_CLK_CLINT,
- clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50));
-
- return 0;
-}
-
-static const struct udevice_id k210_clk_ids[] = {
- { .compatible = "kendryte,k210-clk" },
- { },
-};
-
-U_BOOT_DRIVER(k210_clk) = {
- .name = "k210_clk",
- .id = UCLASS_CLK,
- .of_match = k210_clk_ids,
- .ops = &k210_clk_ops,
- .probe = k210_clk_probe,
-};
diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c
deleted file mode 100644
index ab6d75d..0000000
--- a/drivers/clk/kendryte/pll.c
+++ /dev/null
@@ -1,603 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
- */
-#define LOG_CATEGORY UCLASS_CLK
-
-#include <common.h>
-#include <dm.h>
-/* For DIV_ROUND_DOWN_ULL, defined in linux/kernel.h */
-#include <div64.h>
-#include <log.h>
-#include <serial.h>
-#include <asm/io.h>
-#include <dt-bindings/clock/k210-sysctl.h>
-#include <kendryte/pll.h>
-#include <linux/bitfield.h>
-#include <linux/clk-provider.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-
-#define CLK_K210_PLL "k210_clk_pll"
-
-#ifdef CONFIG_CLK_K210_SET_RATE
-static int k210_pll_enable(struct clk *clk);
-static int k210_pll_disable(struct clk *clk);
-
-/*
- * The PLL included with the Kendryte K210 appears to be a True Circuits, Inc.
- * General-Purpose PLL. The logical layout of the PLL with internal feedback is
- * approximately the following:
- *
- * +---------------+
- * |reference clock|
- * +---------------+
- * |
- * v
- * +--+
- * |/r|
- * +--+
- * |
- * v
- * +-------------+
- * |divided clock|
- * +-------------+
- * |
- * v
- * +--------------+
- * |phase detector|<---+
- * +--------------+ |
- * | |
- * v +--------------+
- * +---+ |feedback clock|
- * |VCO| +--------------+
- * +---+ ^
- * | +--+ |
- * +--->|/f|---+
- * | +--+
- * v
- * +---+
- * |/od|
- * +---+
- * |
- * v
- * +------+
- * |output|
- * +------+
- *
- * The k210 PLLs have three factors: r, f, and od. Because of the feedback mode,
- * the effect of the division by f is to multiply the input frequency. The
- * equation for the output rate is
- * rate = (rate_in * f) / (r * od).
- * Moving knowns to one side of the equation, we get
- * rate / rate_in = f / (r * od)
- * Rearranging slightly,
- * abs_error = abs((rate / rate_in) - (f / (r * od))).
- * To get relative, error, we divide by the expected ratio
- * error = abs((rate / rate_in) - (f / (r * od))) / (rate / rate_in).
- * Simplifying,
- * error = abs(1 - f / (r * od)) / (rate / rate_in)
- * error = abs(1 - (f * rate_in) / (r * od * rate))
- * Using the constants ratio = rate / rate_in and inv_ratio = rate_in / rate,
- * error = abs((f * inv_ratio) / (r * od) - 1)
- * This is the error used in evaluating parameters.
- *
- * r and od are four bits each, while f is six bits. Because r and od are
- * multiplied together, instead of the full 256 values possible if both bits
- * were used fully, there are only 97 distinct products. Combined with f, there
- * are 6208 theoretical settings for the PLL. However, most of these settings
- * can be ruled out immediately because they do not have the correct ratio.
- *
- * In addition to the constraint of approximating the desired ratio, parameters
- * must also keep internal pll frequencies within acceptable ranges. The divided
- * clock's minimum and maximum frequencies have a ratio of around 128. This
- * leaves fairly substantial room to work with, especially since the only
- * affected parameter is r. The VCO's minimum and maximum frequency have a ratio
- * of 5, which is considerably more restrictive.
- *
- * The r and od factors are stored in a table. This is to make it easy to find
- * the next-largest product. Some products have multiple factorizations, but
- * only when one factor has at least a 2.5x ratio to the factors of the other
- * factorization. This is because any smaller ratio would not make a difference
- * when ensuring the VCO's frequency is within spec.
- *
- * Throughout the calculation function, fixed point arithmetic is used. Because
- * the range of rate and rate_in may be up to 1.75 GHz, or around 2^30, 64-bit
- * 32.32 fixed-point numbers are used to represent ratios. In general, to
- * implement division, the numerator is first multiplied by 2^32. This gives a
- * result where the whole number part is in the upper 32 bits, and the fraction
- * is in the lower 32 bits.
- *
- * In general, rounding is done to the closest integer. This helps find the best
- * approximation for the ratio. Rounding in one direction (e.g down) could cause
- * the function to miss a better ratio with one of the parameters increased by
- * one.
- */
-
-/*
- * The factors table was generated with the following python code:
- *
- * def p(x, y):
- * return (1.0*x/y > 2.5) or (1.0*y/x > 2.5)
- *
- * factors = {}
- * for i in range(1, 17):
- * for j in range(1, 17):
- * fs = factors.get(i*j) or []
- * if fs == [] or all([
- * (p(i, x) and p(i, y)) or (p(j, x) and p(j, y))
- * for (x, y) in fs]):
- * fs.append((i, j))
- * factors[i*j] = fs
- *
- * for k, l in sorted(factors.items()):
- * for v in l:
- * print("PACK(%s, %s)," % v)
- */
-#define PACK(r, od) (((((r) - 1) & 0xF) << 4) | (((od) - 1) & 0xF))
-#define UNPACK_R(val) ((((val) >> 4) & 0xF) + 1)
-#define UNPACK_OD(val) (((val) & 0xF) + 1)
-static const u8 factors[] = {
- PACK(1, 1),
- PACK(1, 2),
- PACK(1, 3),
- PACK(1, 4),
- PACK(1, 5),
- PACK(1, 6),
- PACK(1, 7),
- PACK(1, 8),
- PACK(1, 9),
- PACK(3, 3),
- PACK(1, 10),
- PACK(1, 11),
- PACK(1, 12),
- PACK(3, 4),
- PACK(1, 13),
- PACK(1, 14),
- PACK(1, 15),
- PACK(3, 5),
- PACK(1, 16),
- PACK(4, 4),
- PACK(2, 9),
- PACK(2, 10),
- PACK(3, 7),
- PACK(2, 11),
- PACK(2, 12),
- PACK(5, 5),
- PACK(2, 13),
- PACK(3, 9),
- PACK(2, 14),
- PACK(2, 15),
- PACK(2, 16),
- PACK(3, 11),
- PACK(5, 7),
- PACK(3, 12),
- PACK(3, 13),
- PACK(4, 10),
- PACK(3, 14),
- PACK(4, 11),
- PACK(3, 15),
- PACK(3, 16),
- PACK(7, 7),
- PACK(5, 10),
- PACK(4, 13),
- PACK(6, 9),
- PACK(5, 11),
- PACK(4, 14),
- PACK(4, 15),
- PACK(7, 9),
- PACK(4, 16),
- PACK(5, 13),
- PACK(6, 11),
- PACK(5, 14),
- PACK(6, 12),
- PACK(5, 15),
- PACK(7, 11),
- PACK(6, 13),
- PACK(5, 16),
- PACK(9, 9),
- PACK(6, 14),
- PACK(8, 11),
- PACK(6, 15),
- PACK(7, 13),
- PACK(6, 16),
- PACK(7, 14),
- PACK(9, 11),
- PACK(10, 10),
- PACK(8, 13),
- PACK(7, 15),
- PACK(9, 12),
- PACK(10, 11),
- PACK(7, 16),
- PACK(9, 13),
- PACK(8, 15),
- PACK(11, 11),
- PACK(9, 14),
- PACK(8, 16),
- PACK(10, 13),
- PACK(11, 12),
- PACK(9, 15),
- PACK(10, 14),
- PACK(11, 13),
- PACK(9, 16),
- PACK(10, 15),
- PACK(11, 14),
- PACK(12, 13),
- PACK(10, 16),
- PACK(11, 15),
- PACK(12, 14),
- PACK(13, 13),
- PACK(11, 16),
- PACK(12, 15),
- PACK(13, 14),
- PACK(12, 16),
- PACK(13, 15),
- PACK(14, 14),
- PACK(13, 16),
- PACK(14, 15),
- PACK(14, 16),
- PACK(15, 15),
- PACK(15, 16),
- PACK(16, 16),
-};
-
-TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
- struct k210_pll_config *best)
-{
- int i;
- s64 error, best_error;
- u64 ratio, inv_ratio; /* fixed point 32.32 ratio of the rates */
- u64 max_r;
- u64 r, f, od;
-
- /*
- * Can't go over 1.75 GHz or under 21.25 MHz due to limitations on the
- * VCO frequency. These are not the same limits as below because od can
- * reduce the output frequency by 16.
- */
- if (rate > 1750000000 || rate < 21250000)
- return -EINVAL;
-
- /* Similar restrictions on the input rate */
- if (rate_in > 1750000000 || rate_in < 13300000)
- return -EINVAL;
-
- ratio = DIV_ROUND_CLOSEST_ULL((u64)rate << 32, rate_in);
- inv_ratio = DIV_ROUND_CLOSEST_ULL((u64)rate_in << 32, rate);
- /* Can't increase by more than 64 or reduce by more than 256 */
- if (rate > rate_in && ratio > (64ULL << 32))
- return -EINVAL;
- else if (rate <= rate_in && inv_ratio > (256ULL << 32))
- return -EINVAL;
-
- /*
- * The divided clock (rate_in / r) must stay between 1.75 GHz and 13.3
- * MHz. There is no minimum, since the only way to get a higher input
- * clock than 26 MHz is to use a clock generated by a PLL. Because PLLs
- * cannot output frequencies greater than 1.75 GHz, the minimum would
- * never be greater than one.
- */
- max_r = DIV_ROUND_DOWN_ULL(rate_in, 13300000);
-
- /* Variables get immediately incremented, so start at -1th iteration */
- i = -1;
- f = 0;
- r = 0;
- od = 0;
- best_error = S64_MAX;
- error = best_error;
- /* do-while here so we always try at least one ratio */
- do {
- /*
- * Whether we swapped r and od while enforcing frequency limits
- */
- bool swapped = false;
- u64 last_od = od;
- u64 last_r = r;
-
- /*
- * Try the next largest value for f (or r and od) and
- * recalculate the other parameters based on that
- */
- if (rate > rate_in) {
- /*
- * Skip factors of the same product if we already tried
- * out that product
- */
- do {
- i++;
- r = UNPACK_R(factors[i]);
- od = UNPACK_OD(factors[i]);
- } while (i + 1 < ARRAY_SIZE(factors) &&
- r * od == last_r * last_od);
-
- /* Round close */
- f = (r * od * ratio + BIT(31)) >> 32;
- if (f > 64)
- f = 64;
- } else {
- u64 tmp = ++f * inv_ratio;
- bool round_up = !!(tmp & BIT(31));
- u32 goal = (tmp >> 32) + round_up;
- u32 err, last_err;
-
- /* Get the next r/od pair in factors */
- while (r * od < goal && i + 1 < ARRAY_SIZE(factors)) {
- i++;
- r = UNPACK_R(factors[i]);
- od = UNPACK_OD(factors[i]);
- }
-
- /*
- * This is a case of double rounding. If we rounded up
- * above, we need to round down (in cases of ties) here.
- * This prevents off-by-one errors resulting from
- * choosing X+2 over X when X.Y rounds up to X+1 and
- * there is no r * od = X+1. For the converse, when X.Y
- * is rounded down to X, we should choose X+1 over X-1.
- */
- err = abs(r * od - goal);
- last_err = abs(last_r * last_od - goal);
- if (last_err < err || (round_up && last_err == err)) {
- i--;
- r = last_r;
- od = last_od;
- }
- }
-
- /*
- * Enforce limits on internal clock frequencies. If we
- * aren't in spec, try swapping r and od. If everything is
- * in-spec, calculate the relative error.
- */
- while (true) {
- /*
- * Whether the intermediate frequencies are out-of-spec
- */
- bool out_of_spec = false;
-
- if (r > max_r) {
- out_of_spec = true;
- } else {
- /*
- * There is no way to only divide once; we need
- * to examine the frequency with and without the
- * effect of od.
- */
- u64 vco = DIV_ROUND_CLOSEST_ULL(rate_in * f, r);
-
- if (vco > 1750000000 || vco < 340000000)
- out_of_spec = true;
- }
-
- if (out_of_spec) {
- if (!swapped) {
- u64 tmp = r;
-
- r = od;
- od = tmp;
- swapped = true;
- continue;
- } else {
- /*
- * Try looking ahead to see if there are
- * additional factors for the same
- * product.
- */
- if (i + 1 < ARRAY_SIZE(factors)) {
- u64 new_r, new_od;
-
- i++;
- new_r = UNPACK_R(factors[i]);
- new_od = UNPACK_OD(factors[i]);
- if (r * od == new_r * new_od) {
- r = new_r;
- od = new_od;
- swapped = false;
- continue;
- }
- i--;
- }
- break;
- }
- }
-
- error = DIV_ROUND_CLOSEST_ULL(f * inv_ratio, r * od);
- /* The lower 16 bits are spurious */
- error = abs((error - BIT(32))) >> 16;
-
- if (error < best_error) {
- best->r = r;
- best->f = f;
- best->od = od;
- best_error = error;
- }
- break;
- }
- } while (f < 64 && i + 1 < ARRAY_SIZE(factors) && error != 0);
-
- if (best_error == S64_MAX)
- return -EINVAL;
-
- log_debug("best error %lld\n", best_error);
- return 0;
-}
-
-static ulong k210_pll_set_rate(struct clk *clk, ulong rate)
-{
- int err;
- long long rate_in = clk_get_parent_rate(clk);
- struct k210_pll_config config = {};
- struct k210_pll *pll = to_k210_pll(clk);
- u32 reg;
-
- if (rate_in < 0)
- return rate_in;
-
- log_debug("Calculating parameters with rate=%lu and rate_in=%lld\n",
- rate, rate_in);
- err = k210_pll_calc_config(rate, rate_in, &config);
- if (err)
- return err;
- log_debug("Got r=%u f=%u od=%u\n", config.r, config.f, config.od);
-
- /*
- * Don't use clk_disable as it might not actually disable the pll due to
- * refcounting
- */
- k210_pll_disable(clk);
-
- reg = readl(pll->reg);
- reg &= ~K210_PLL_CLKR
- & ~K210_PLL_CLKF
- & ~K210_PLL_CLKOD
- & ~K210_PLL_BWADJ;
- reg |= FIELD_PREP(K210_PLL_CLKR, config.r - 1)
- | FIELD_PREP(K210_PLL_CLKF, config.f - 1)
- | FIELD_PREP(K210_PLL_CLKOD, config.od - 1)
- | FIELD_PREP(K210_PLL_BWADJ, config.f - 1);
- writel(reg, pll->reg);
-
- err = k210_pll_enable(clk);
- if (err)
- return err;
-
- serial_setbrg();
- return clk_get_rate(clk);
-}
-#endif /* CONFIG_CLK_K210_SET_RATE */
-
-static ulong k210_pll_get_rate(struct clk *clk)
-{
- long long rate_in = clk_get_parent_rate(clk);
- struct k210_pll *pll = to_k210_pll(clk);
- u64 r, f, od;
- u32 reg = readl(pll->reg);
-
- if (rate_in < 0 || (reg & K210_PLL_BYPASS))
- return rate_in;
-
- if (!(reg & K210_PLL_PWRD))
- return 0;
-
- r = FIELD_GET(K210_PLL_CLKR, reg) + 1;
- f = FIELD_GET(K210_PLL_CLKF, reg) + 1;
- od = FIELD_GET(K210_PLL_CLKOD, reg) + 1;
-
- return DIV_ROUND_DOWN_ULL(((u64)rate_in) * f, r * od);
-}
-
-/*
- * Wait for the PLL to be locked. If the PLL is not locked, try clearing the
- * slip before retrying
- */
-static void k210_pll_waitfor_lock(struct k210_pll *pll)
-{
- u32 mask = GENMASK(pll->width - 1, 0) << pll->shift;
-
- while (true) {
- u32 reg = readl(pll->lock);
-
- if ((reg & mask) == mask)
- break;
-
- reg |= BIT(pll->shift + K210_PLL_CLEAR_SLIP);
- writel(reg, pll->lock);
- }
-}
-
-/* Adapted from sysctl_pll_enable */
-static int k210_pll_enable(struct clk *clk)
-{
- struct k210_pll *pll = to_k210_pll(clk);
- u32 reg = readl(pll->reg);
-
- if ((reg | K210_PLL_PWRD) && !(reg | K210_PLL_RESET))
- return 0;
-
- reg |= K210_PLL_PWRD;
- writel(reg, pll->reg);
-
- /* Ensure reset is low before asserting it */
- reg &= ~K210_PLL_RESET;
- writel(reg, pll->reg);
- reg |= K210_PLL_RESET;
- writel(reg, pll->reg);
- nop();
- nop();
- reg &= ~K210_PLL_RESET;
- writel(reg, pll->reg);
-
- k210_pll_waitfor_lock(pll);
-
- reg &= ~K210_PLL_BYPASS;
- writel(reg, pll->reg);
-
- return 0;
-}
-
-static int k210_pll_disable(struct clk *clk)
-{
- struct k210_pll *pll = to_k210_pll(clk);
- u32 reg = readl(pll->reg);
-
- /*
- * Bypassing before powering off is important so child clocks don't stop
- * working. This is especially important for pll0, the indirect parent
- * of the cpu clock.
- */
- reg |= K210_PLL_BYPASS;
- writel(reg, pll->reg);
-
- reg &= ~K210_PLL_PWRD;
- writel(reg, pll->reg);
- return 0;
-}
-
-const struct clk_ops k210_pll_ops = {
- .get_rate = k210_pll_get_rate,
-#ifdef CONFIG_CLK_K210_SET_RATE
- .set_rate = k210_pll_set_rate,
-#endif
- .enable = k210_pll_enable,
- .disable = k210_pll_disable,
-};
-
-struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
- struct k210_pll *pll)
-{
- int ret;
- struct clk *clk = &pll->clk;
-
- ret = clk_register(clk, CLK_K210_PLL, name, parent_name);
- if (ret)
- return ERR_PTR(ret);
- return clk;
-}
-
-struct clk *k210_register_pll(const char *name, const char *parent_name,
- void __iomem *reg, void __iomem *lock, u8 shift,
- u8 width)
-{
- struct clk *clk;
- struct k210_pll *pll;
-
- pll = kzalloc(sizeof(*pll), GFP_KERNEL);
- if (!pll)
- return ERR_PTR(-ENOMEM);
- pll->reg = reg;
- pll->lock = lock;
- pll->shift = shift;
- pll->width = width;
-
- clk = k210_register_pll_struct(name, parent_name, pll);
- if (IS_ERR(clk))
- kfree(pll);
- return clk;
-}
-
-U_BOOT_DRIVER(k210_pll) = {
- .name = CLK_K210_PLL,
- .id = UCLASS_CLK,
- .ops = &k210_pll_ops,
-};
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index b423c94..d2d0169 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -23,8 +23,6 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen2-cpg.h"
-#define CPG_RST_MODEMR 0x0060
-
#define CPG_PLL0CR 0x00d8
#define CPG_SDCKCR 0x0074
@@ -63,14 +61,14 @@
{
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, true);
+ return renesas_clk_endisable(clk, priv->base, priv->info, true);
}
static int gen2_clk_disable(struct clk *clk)
{
struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, false);
+ return renesas_clk_endisable(clk, priv->base, priv->info, false);
}
static ulong gen2_clk_get_rate(struct clk *clk)
diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 3223bec..7b42e28 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -25,8 +25,6 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
-#define CPG_RST_MODEMR 0x0060
-
#define CPG_PLL0CR 0x00d8
#define CPG_PLL2CR 0x002c
#define CPG_PLL4CR 0x01f4
@@ -145,16 +143,40 @@
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, true);
+ return renesas_clk_endisable(clk, priv->base, priv->info, true);
}
static int gen3_clk_disable(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
- return renesas_clk_endisable(clk, priv->base, false);
+ return renesas_clk_endisable(clk, priv->base, priv->info, false);
}
+static u64 gen3_clk_get_rate64(struct clk *clk);
+
+static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
+ struct clk *parent,
+ const struct cpg_core_clk *core,
+ u32 mul_reg, u32 mult, u32 div,
+ char *name)
+{
+ u32 value;
+ u64 rate;
+
+ if (mul_reg) {
+ value = readl(priv->base + mul_reg);
+ mult = (((value >> 24) & 0x7f) + 1) * 2;
+ div = 1;
+ }
+
+ rate = (gen3_clk_get_rate64(parent) * mult) / div;
+
+ debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",
+ __func__, __LINE__, name, core->parent, mult, div, rate);
+ return rate;
+}
+
static u64 gen3_clk_get_rate64(struct clk *clk)
{
struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
@@ -163,7 +185,7 @@
const struct cpg_core_clk *core;
const struct rcar_gen3_cpg_pll_config *pll_config =
priv->cpg_pll_config;
- u32 value, mult, div, prediv, postdiv;
+ u32 value, div, prediv, postdiv;
u64 rate = 0;
int i, ret;
@@ -205,60 +227,36 @@
return -EINVAL;
case CLK_TYPE_GEN3_MAIN:
- rate = gen3_clk_get_rate64(&parent) / pll_config->extal_div;
- debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%llu\n",
- __func__, __LINE__,
- core->parent, pll_config->extal_div, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ 0, 1, pll_config->extal_div,
+ "MAIN");
case CLK_TYPE_GEN3_PLL0:
- value = readl(priv->base + CPG_PLL0CR);
- mult = (((value >> 24) & 0x7f) + 1) * 2;
- rate = gen3_clk_get_rate64(&parent) * mult;
- debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%llu\n",
- __func__, __LINE__, core->parent, mult, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ CPG_PLL0CR, 0, 0, "PLL0");
case CLK_TYPE_GEN3_PLL1:
- rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult;
- rate /= pll_config->pll1_div;
- debug("%s[%i] PLL1 clk: parent=%i mul=%i div=%i => rate=%llu\n",
- __func__, __LINE__,
- core->parent, pll_config->pll1_mult,
- pll_config->pll1_div, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ 0, pll_config->pll1_mult,
+ pll_config->pll1_div, "PLL1");
case CLK_TYPE_GEN3_PLL2:
- value = readl(priv->base + CPG_PLL2CR);
- mult = (((value >> 24) & 0x7f) + 1) * 2;
- rate = gen3_clk_get_rate64(&parent) * mult;
- debug("%s[%i] PLL2 clk: parent=%i mult=%u => rate=%llu\n",
- __func__, __LINE__, core->parent, mult, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ CPG_PLL2CR, 0, 0, "PLL2");
case CLK_TYPE_GEN3_PLL3:
- rate = gen3_clk_get_rate64(&parent) * pll_config->pll3_mult;
- rate /= pll_config->pll3_div;
- debug("%s[%i] PLL3 clk: parent=%i mul=%i div=%i => rate=%llu\n",
- __func__, __LINE__,
- core->parent, pll_config->pll3_mult,
- pll_config->pll3_div, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ 0, pll_config->pll3_mult,
+ pll_config->pll3_div, "PLL3");
case CLK_TYPE_GEN3_PLL4:
- value = readl(priv->base + CPG_PLL4CR);
- mult = (((value >> 24) & 0x7f) + 1) * 2;
- rate = gen3_clk_get_rate64(&parent) * mult;
- debug("%s[%i] PLL4 clk: parent=%i mult=%u => rate=%llu\n",
- __func__, __LINE__, core->parent, mult, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ CPG_PLL4CR, 0, 0, "PLL4");
case CLK_TYPE_FF:
- rate = (gen3_clk_get_rate64(&parent) * core->mult) / core->div;
- debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%llu\n",
- __func__, __LINE__,
- core->parent, core->mult, core->div, rate);
- return rate;
+ return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+ 0, core->mult, core->div,
+ "FIXED");
case CLK_TYPE_GEN3_MDSEL:
div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
@@ -289,6 +287,7 @@
return -EINVAL;
case CLK_TYPE_GEN3_RPC:
+ case CLK_TYPE_GEN3_RPCD2:
rate = gen3_clk_get_rate64(&parent);
value = readl(priv->base + core->offset);
@@ -304,11 +303,19 @@
postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
CPG_RPC_POSTDIV_MASK;
- rate /= postdiv + 1;
- debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
- __func__, __LINE__,
- core->parent, prediv, postdiv, rate);
+ if (postdiv % 2 != 0) {
+ rate /= postdiv + 1;
+
+ if (core->type == CLK_TYPE_GEN3_RPCD2)
+ rate /= 2;
+
+ debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
+ __func__, __LINE__,
+ core->parent, prediv, postdiv, rate);
+
+ return rate;
+ }
return -EINVAL;
@@ -373,7 +380,7 @@
if (rst_base == FDT_ADDR_T_NONE)
return -EINVAL;
- cpg_mode = readl(rst_base + CPG_RST_MODEMR);
+ cpg_mode = readl(rst_base + info->reset_modemr_offset);
priv->cpg_pll_config =
(struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
@@ -382,6 +389,15 @@
priv->sscg = !(cpg_mode & BIT(12));
+ if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
+ priv->info->status_regs = mstpsr;
+ priv->info->control_regs = smstpcr;
+ priv->info->reset_regs = srcr;
+ priv->info->reset_clear_regs = srstclr;
+ } else {
+ return -EINVAL;
+ }
+
ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
if (ret < 0)
return ret;
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 1c54eca..48da65c 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -68,13 +68,18 @@
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774A1_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774A1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A774A1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
- DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
- DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
+ DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
+ DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -99,7 +104,6 @@
DEF_GEN3_SD("sd1", R8A774A1_CLK_SD1, CLK_SDSRC, 0x078),
DEF_GEN3_SD("sd2", R8A774A1_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A774A1_CLK_SD3, CLK_SDSRC, 0x26c),
- DEF_GEN3_RPC("rpc", R8A774A1_CLK_RPC, CLK_RPCSRC, 0x238),
DEF_FIXED("cl", R8A774A1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cp", R8A774A1_CLK_CP, CLK_EXTAL, 2, 1),
@@ -203,7 +207,7 @@
DEF_MOD("can-fd", 914, R8A774A1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774A1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774A1_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A774A1_CLK_RPC),
+ DEF_MOD("rpc-if", 917, R8A774A1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774A1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774A1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774A1_CLK_CP),
@@ -317,6 +321,7 @@
.mstp_table = r8a774a1_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a774a1_mstp_table),
.reset_node = "renesas,r8a774a1-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index 03851d0..418c393 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -39,6 +39,7 @@
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -64,6 +65,12 @@
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A774B1_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
@@ -195,6 +202,7 @@
DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
+ DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
@@ -310,6 +318,7 @@
.mstp_table = r8a774b1_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a774b1_mstp_table),
.reset_node = "renesas,r8a774b1-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 37a7123..c1283d2 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -44,6 +44,7 @@
CLK_S2,
CLK_S3,
CLK_SDSRC,
+ CLK_RPCSRC,
CLK_RINT,
CLK_OCO,
@@ -74,6 +75,13 @@
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A774C0_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A774C0_CLK_RPC),
+
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
@@ -199,6 +207,7 @@
DEF_MOD("can-fd", 914, R8A774C0_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A774C0_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A774C0_CLK_S3D4),
+ DEF_MOD("rpc-if", 917, R8A774C0_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A774C0_CLK_S3D2),
DEF_MOD("i2c5", 919, R8A774C0_CLK_S3D2),
DEF_MOD("i2c-dvfs", 926, R8A774C0_CLK_CP),
@@ -283,6 +292,7 @@
.mstp_table = r8a774c0_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a774c0_mstp_table),
.reset_node = "renesas,r8a774c0-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = ~0,
diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index c969ec6..0cacd8d 100644
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -332,6 +332,7 @@
.mstp_table = r8a774e1_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a774e1_mstp_table),
.reset_node = "renesas,r8a774e1-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index d5079da..1f3477f 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -108,8 +108,8 @@
DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
- DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
- DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
+ DEF_MOD("vspr", 130, R8A7790_CLK_ZS),
+ DEF_MOD("vsps", 131, R8A7790_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
DEF_MOD("scifa0", 204, R8A7790_CLK_MP),
@@ -263,6 +263,7 @@
.mstp_table = r8a7790_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7790_mstp_table),
.reset_node = "renesas,r8a7790-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extal_usb_node = "usb_extal",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index fa0e275..fcca7be 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -106,7 +106,7 @@
DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
- DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
+ DEF_MOD("vsps", 131, R8A7791_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
@@ -265,6 +265,7 @@
.mstp_table = r8a7791_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table),
.reset_node = "renesas,r8a7791-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extal_usb_node = "usb_extal",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index d2225a3..5b33363 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -88,7 +88,7 @@
DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
- DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
+ DEF_MOD("vsps", 131, R8A7792_CLK_ZS),
DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
@@ -213,6 +213,7 @@
.mstp_table = r8a7792_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table),
.reset_node = "renesas,r8a7792-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.pll0_div = 2,
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index d05f89d..b9dd88d 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -97,7 +97,7 @@
DEF_MOD("cmt0", 124, R8A7794_CLK_R),
DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
- DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
+ DEF_MOD("vsps", 131, R8A7794_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
DEF_MOD("scifa0", 204, R8A7794_CLK_MP),
@@ -240,6 +240,7 @@
.mstp_table = r8a7794_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7794_mstp_table),
.reset_node = "renesas,r8a7794-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extal_usb_node = "usb_extal",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index b137564..6ba796b 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -41,8 +41,8 @@
CLK_S2,
CLK_S3,
CLK_SDSRC,
- CLK_RPCSRC,
CLK_SSPSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -69,13 +69,18 @@
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A7795_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A7795_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
- DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
- DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
+ DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
+ DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -102,8 +107,6 @@
DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_SDSRC, 0x26c),
- DEF_GEN3_RPC("rpc", R8A7795_CLK_RPC, CLK_RPCSRC, 0x238),
-
DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
DEF_FIXED("cr", R8A7795_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
@@ -132,14 +135,15 @@
DEF_MOD("msiof2", 209, R8A7795_CLK_MSO),
DEF_MOD("msiof1", 210, R8A7795_CLK_MSO),
DEF_MOD("msiof0", 211, R8A7795_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S0D3),
+ DEF_MOD("sys-dmac2", 217, R8A7795_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A7795_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A7795_CLK_S0D3),
DEF_MOD("sceg-pub", 229, R8A7795_CLK_CR),
DEF_MOD("cmt3", 300, R8A7795_CLK_R),
DEF_MOD("cmt2", 301, R8A7795_CLK_R),
DEF_MOD("cmt1", 302, R8A7795_CLK_R),
DEF_MOD("cmt0", 303, R8A7795_CLK_R),
+ DEF_MOD("tpu0", 304, R8A7795_CLK_S3D4),
DEF_MOD("scif2", 310, R8A7795_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A7795_CLK_SD3),
DEF_MOD("sdif2", 312, R8A7795_CLK_SD2),
@@ -156,16 +160,16 @@
DEF_MOD("rwdt", 402, R8A7795_CLK_R),
DEF_MOD("intc-ex", 407, R8A7795_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7795_CLK_S0D3),
- DEF_MOD("audmac1", 501, R8A7795_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A7795_CLK_S0D3),
- DEF_MOD("drif7", 508, R8A7795_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A7795_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A7795_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A7795_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A7795_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A7795_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A7795_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A7795_CLK_S3D2),
+ DEF_MOD("audmac1", 501, R8A7795_CLK_S1D2),
+ DEF_MOD("audmac0", 502, R8A7795_CLK_S1D2),
+ DEF_MOD("drif31", 508, R8A7795_CLK_S3D2),
+ DEF_MOD("drif30", 509, R8A7795_CLK_S3D2),
+ DEF_MOD("drif21", 510, R8A7795_CLK_S3D2),
+ DEF_MOD("drif20", 511, R8A7795_CLK_S3D2),
+ DEF_MOD("drif11", 512, R8A7795_CLK_S3D2),
+ DEF_MOD("drif10", 513, R8A7795_CLK_S3D2),
+ DEF_MOD("drif01", 514, R8A7795_CLK_S3D2),
+ DEF_MOD("drif00", 515, R8A7795_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7795_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7795_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7795_CLK_S3D1),
@@ -197,12 +201,16 @@
DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
- DEF_MOD("ehci3", 700, R8A7795_CLK_S3D4),
- DEF_MOD("ehci2", 701, R8A7795_CLK_S3D4),
- DEF_MOD("ehci1", 702, R8A7795_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A7795_CLK_S3D4),
- DEF_MOD("hsusb", 704, R8A7795_CLK_S3D4),
- DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D4),
+ DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
+ DEF_MOD("ehci2", 701, R8A7795_CLK_S3D2),
+ DEF_MOD("ehci1", 702, R8A7795_CLK_S3D2),
+ DEF_MOD("ehci0", 703, R8A7795_CLK_S3D2),
+ DEF_MOD("hsusb", 704, R8A7795_CLK_S3D2),
+ DEF_MOD("hsusb3", 705, R8A7795_CLK_S3D2),
+ DEF_MOD("cmm3", 708, R8A7795_CLK_S2D1),
+ DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
+ DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
+ DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
@@ -239,7 +247,7 @@
DEF_MOD("can-fd", 914, R8A7795_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7795_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A7795_CLK_RPC),
+ DEF_MOD("rpc-if", 917, R8A7795_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
@@ -354,6 +362,7 @@
.mstp_table = r8a7795_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7795_mstp_table),
.reset_node = "renesas,r8a7795-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 6745305..e318719 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -47,8 +47,8 @@
CLK_S2,
CLK_S3,
CLK_SDSRC,
- CLK_RPCSRC,
CLK_SSPSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -75,13 +75,18 @@
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A7796_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A7796_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A7796_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
- DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
- DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2),
+ DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
+ DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL2, 2, 0),
DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -108,9 +113,8 @@
DEF_GEN3_SD("sd2", R8A7796_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A7796_CLK_SD3, CLK_SDSRC, 0x26c),
- DEF_GEN3_RPC("rpc", R8A7796_CLK_RPC, CLK_RPCSRC, 0x238),
-
DEF_FIXED("cl", R8A7796_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cr", R8A7796_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A7796_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A7796_CLK_CPEX, CLK_EXTAL, 2, 1),
@@ -126,6 +130,11 @@
static const struct mssr_mod_clk r8a7796_mod_clks[] = {
DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
+ DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
+ DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
+ DEF_MOD("tmu2", 123, R8A7796_CLK_S3D2),
+ DEF_MOD("tmu1", 124, R8A7796_CLK_S3D2),
+ DEF_MOD("tmu0", 125, R8A7796_CLK_CP),
DEF_MOD("scif5", 202, R8A7796_CLK_S3D4),
DEF_MOD("scif4", 203, R8A7796_CLK_S3D4),
DEF_MOD("scif3", 204, R8A7796_CLK_S3D4),
@@ -135,13 +144,15 @@
DEF_MOD("msiof2", 209, R8A7796_CLK_MSO),
DEF_MOD("msiof1", 210, R8A7796_CLK_MSO),
DEF_MOD("msiof0", 211, R8A7796_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S0D3),
+ DEF_MOD("sys-dmac2", 217, R8A7796_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A7796_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A7796_CLK_S0D3),
+ DEF_MOD("sceg-pub", 229, R8A7796_CLK_CR),
DEF_MOD("cmt3", 300, R8A7796_CLK_R),
DEF_MOD("cmt2", 301, R8A7796_CLK_R),
DEF_MOD("cmt1", 302, R8A7796_CLK_R),
DEF_MOD("cmt0", 303, R8A7796_CLK_R),
+ DEF_MOD("tpu0", 304, R8A7796_CLK_S3D4),
DEF_MOD("scif2", 310, R8A7796_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A7796_CLK_SD3),
DEF_MOD("sdif2", 312, R8A7796_CLK_SD2),
@@ -155,16 +166,16 @@
DEF_MOD("rwdt", 402, R8A7796_CLK_R),
DEF_MOD("intc-ex", 407, R8A7796_CLK_CP),
DEF_MOD("intc-ap", 408, R8A7796_CLK_S0D3),
- DEF_MOD("audmac1", 501, R8A7796_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A7796_CLK_S0D3),
- DEF_MOD("drif7", 508, R8A7796_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A7796_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A7796_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A7796_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A7796_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A7796_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A7796_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A7796_CLK_S3D2),
+ DEF_MOD("audmac1", 501, R8A7796_CLK_S1D2),
+ DEF_MOD("audmac0", 502, R8A7796_CLK_S1D2),
+ DEF_MOD("drif31", 508, R8A7796_CLK_S3D2),
+ DEF_MOD("drif30", 509, R8A7796_CLK_S3D2),
+ DEF_MOD("drif21", 510, R8A7796_CLK_S3D2),
+ DEF_MOD("drif20", 511, R8A7796_CLK_S3D2),
+ DEF_MOD("drif11", 512, R8A7796_CLK_S3D2),
+ DEF_MOD("drif10", 513, R8A7796_CLK_S3D2),
+ DEF_MOD("drif01", 514, R8A7796_CLK_S3D2),
+ DEF_MOD("drif00", 515, R8A7796_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A7796_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A7796_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A7796_CLK_S3D1),
@@ -185,9 +196,12 @@
DEF_MOD("vspd0", 623, R8A7796_CLK_S0D2),
DEF_MOD("vspb", 626, R8A7796_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7796_CLK_S0D1),
- DEF_MOD("ehci1", 702, R8A7796_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A7796_CLK_S3D4),
- DEF_MOD("hsusb", 704, R8A7796_CLK_S3D4),
+ DEF_MOD("ehci1", 702, R8A7796_CLK_S3D2),
+ DEF_MOD("ehci0", 703, R8A7796_CLK_S3D2),
+ DEF_MOD("hsusb", 704, R8A7796_CLK_S3D2),
+ DEF_MOD("cmm2", 709, R8A7796_CLK_S2D1),
+ DEF_MOD("cmm1", 710, R8A7796_CLK_S2D1),
+ DEF_MOD("cmm0", 711, R8A7796_CLK_S2D1),
DEF_MOD("csi20", 714, R8A7796_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7796_CLK_CSI0),
DEF_MOD("du2", 722, R8A7796_CLK_S2D1),
@@ -217,7 +231,7 @@
DEF_MOD("can-fd", 914, R8A7796_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A7796_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A7796_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A7796_CLK_RPC),
+ DEF_MOD("rpc-if", 917, R8A7796_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A7796_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7796_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A7796_CLK_CP),
@@ -332,6 +346,7 @@
.mstp_table = r8a7796_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a7796_mstp_table),
.reset_node = "renesas,r8a7796-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 8d792bc..0a15617 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -41,8 +41,8 @@
CLK_S2,
CLK_S3,
CLK_SDSRC,
- CLK_RPCSRC,
CLK_SSPSRC,
+ CLK_RPCSRC,
CLK_RINT,
/* Module Clocks */
@@ -68,12 +68,17 @@
DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+ DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A77965_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77965_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A77965_CLK_RPC),
DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
/* Core Clock Outputs */
- DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0),
+ DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
@@ -100,9 +105,8 @@
DEF_GEN3_SD("sd2", R8A77965_CLK_SD2, CLK_SDSRC, 0x268),
DEF_GEN3_SD("sd3", R8A77965_CLK_SD3, CLK_SDSRC, 0x26c),
- DEF_GEN3_RPC("rpc", R8A77965_CLK_RPC, CLK_RPCSRC, 0x238),
-
- DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cl", R8A77965_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cr", R8A77965_CLK_CR, CLK_PLL1_DIV4, 2, 1),
DEF_FIXED("cp", R8A77965_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77965_CLK_CPEX, CLK_EXTAL, 2, 1),
@@ -118,6 +122,11 @@
static const struct mssr_mod_clk r8a77965_mod_clks[] = {
DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
+ DEF_MOD("tmu4", 121, R8A77965_CLK_S0D6),
+ DEF_MOD("tmu3", 122, R8A77965_CLK_S3D2),
+ DEF_MOD("tmu2", 123, R8A77965_CLK_S3D2),
+ DEF_MOD("tmu1", 124, R8A77965_CLK_S3D2),
+ DEF_MOD("tmu0", 125, R8A77965_CLK_CP),
DEF_MOD("scif5", 202, R8A77965_CLK_S3D4),
DEF_MOD("scif4", 203, R8A77965_CLK_S3D4),
DEF_MOD("scif3", 204, R8A77965_CLK_S3D4),
@@ -127,14 +136,16 @@
DEF_MOD("msiof2", 209, R8A77965_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77965_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77965_CLK_MSO),
- DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S0D3),
- DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S0D3),
+ DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
+ DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
+ DEF_MOD("sceg-pub", 229, R8A77965_CLK_CR),
DEF_MOD("cmt3", 300, R8A77965_CLK_R),
DEF_MOD("cmt2", 301, R8A77965_CLK_R),
DEF_MOD("cmt1", 302, R8A77965_CLK_R),
DEF_MOD("cmt0", 303, R8A77965_CLK_R),
+ DEF_MOD("tpu0", 304, R8A77965_CLK_S3D4),
DEF_MOD("scif2", 310, R8A77965_CLK_S3D4),
DEF_MOD("sdif3", 311, R8A77965_CLK_SD3),
DEF_MOD("sdif2", 312, R8A77965_CLK_SD2),
@@ -150,16 +161,16 @@
DEF_MOD("intc-ex", 407, R8A77965_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77965_CLK_S0D3),
- DEF_MOD("audmac1", 501, R8A77965_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A77965_CLK_S0D3),
- DEF_MOD("drif7", 508, R8A77965_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A77965_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A77965_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A77965_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A77965_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A77965_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A77965_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A77965_CLK_S3D2),
+ DEF_MOD("audmac1", 501, R8A77965_CLK_S1D2),
+ DEF_MOD("audmac0", 502, R8A77965_CLK_S1D2),
+ DEF_MOD("drif31", 508, R8A77965_CLK_S3D2),
+ DEF_MOD("drif30", 509, R8A77965_CLK_S3D2),
+ DEF_MOD("drif21", 510, R8A77965_CLK_S3D2),
+ DEF_MOD("drif20", 511, R8A77965_CLK_S3D2),
+ DEF_MOD("drif11", 512, R8A77965_CLK_S3D2),
+ DEF_MOD("drif10", 513, R8A77965_CLK_S3D2),
+ DEF_MOD("drif01", 514, R8A77965_CLK_S3D2),
+ DEF_MOD("drif00", 515, R8A77965_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77965_CLK_S3D1),
DEF_MOD("hscif3", 517, R8A77965_CLK_S3D1),
DEF_MOD("hscif2", 518, R8A77965_CLK_S3D1),
@@ -179,9 +190,12 @@
DEF_MOD("vspb", 626, R8A77965_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A77965_CLK_S0D1),
- DEF_MOD("ehci1", 702, R8A77965_CLK_S3D4),
- DEF_MOD("ehci0", 703, R8A77965_CLK_S3D4),
- DEF_MOD("hsusb", 704, R8A77965_CLK_S3D4),
+ DEF_MOD("ehci1", 702, R8A77965_CLK_S3D2),
+ DEF_MOD("ehci0", 703, R8A77965_CLK_S3D2),
+ DEF_MOD("hsusb", 704, R8A77965_CLK_S3D2),
+ DEF_MOD("cmm3", 708, R8A77965_CLK_S2D1),
+ DEF_MOD("cmm1", 710, R8A77965_CLK_S2D1),
+ DEF_MOD("cmm0", 711, R8A77965_CLK_S2D1),
DEF_MOD("csi20", 714, R8A77965_CLK_CSI0),
DEF_MOD("csi40", 716, R8A77965_CLK_CSI0),
DEF_MOD("du3", 721, R8A77965_CLK_S2D1),
@@ -214,7 +228,7 @@
DEF_MOD("can-fd", 914, R8A77965_CLK_S3D2),
DEF_MOD("can-if1", 915, R8A77965_CLK_S3D4),
DEF_MOD("can-if0", 916, R8A77965_CLK_S3D4),
- DEF_MOD("rpc", 917, R8A77965_CLK_RPC),
+ DEF_MOD("rpc-if", 917, R8A77965_CLK_RPCD2),
DEF_MOD("i2c6", 918, R8A77965_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A77965_CLK_S0D6),
DEF_MOD("i2c-dvfs", 926, R8A77965_CLK_CP),
@@ -330,6 +344,7 @@
.mstp_table = r8a77965_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77965_mstp_table),
.reset_node = "renesas,r8a77965-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index b2b32be..a85bed6 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -20,6 +20,13 @@
#include "renesas-cpg-mssr.h"
#include "rcar-gen3-cpg.h"
+#define CPG_SD0CKCR 0x0074
+
+enum r8a77970_clk_types {
+ CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
+ CLK_TYPE_R8A77970_SD0,
+};
+
enum clk_ids {
/* Core Clock Outputs exported to DT */
LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
@@ -32,24 +39,9 @@
CLK_MAIN,
CLK_PLL0,
CLK_PLL1,
- CLK_PLL2,
CLK_PLL3,
- CLK_PLL4,
CLK_PLL1_DIV2,
CLK_PLL1_DIV4,
- CLK_PLL0D2,
- CLK_PLL0D3,
- CLK_PLL0D5,
- CLK_PLL1D2,
- CLK_PE,
- CLK_S0,
- CLK_S1,
- CLK_S2,
- CLK_S3,
- CLK_SDSRC,
- CLK_RPCSRC,
- CLK_SSPSRC,
- CLK_RINT,
/* Module Clocks */
MOD_CLK_BASE
@@ -57,67 +49,80 @@
static const struct cpg_core_clk r8a77970_core_clks[] = {
/* External Clock Inputs */
- DEF_INPUT("extal", CLK_EXTAL),
- DEF_INPUT("extalr", CLK_EXTALR),
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
/* Internal Core Clocks */
- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
- DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
- DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
- DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
- DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */
- DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
- DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
- DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
- DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
- DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
- DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
- DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
- DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
- DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
- DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
- DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
+ DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
+ DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
+ DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
- DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
+ DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
+ CLK_PLL1_DIV2),
+ DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
- DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
+ DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
+ DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
- DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
- DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
+ DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
+ DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1),
- /* NOTE: HDMI, CSI, CAN etc. clock are missing */
+ DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
+ DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
+ DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
- DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
+ DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
+ DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
};
static const struct mssr_mod_clk r8a77970_mod_clks[] = {
+ DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
+ DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
+ DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
+ DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
+ DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
- DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
- DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
+ DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
+ DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
+ DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
+ DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
- DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
- DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
- DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
+ DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
+ DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
+ DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
+ DEF_MOD("cmt3", 300, R8A77970_CLK_R),
+ DEF_MOD("cmt2", 301, R8A77970_CLK_R),
+ DEF_MOD("cmt1", 302, R8A77970_CLK_R),
+ DEF_MOD("cmt0", 303, R8A77970_CLK_R),
+ DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
+ DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
+ DEF_MOD("rwdt", 402, R8A77970_CLK_R),
DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
- DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
- DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
+ DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
+ DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
+ DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
+ DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
+ DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
DEF_MOD("thermal", 522, R8A77970_CLK_CP),
DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
@@ -130,7 +135,6 @@
DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
- DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
@@ -138,7 +142,7 @@
DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
- DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
+ DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
@@ -207,6 +211,7 @@
.mstp_table = r8a77970_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
.reset_node = "renesas,r8a77970-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index cf96309..bd9d7c9 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -230,6 +230,7 @@
.mstp_table = r8a77980_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77980_mstp_table),
.reset_node = "renesas,r8a77980-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.extalr_node = "extalr",
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index e983296..67a1f58 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -74,7 +74,13 @@
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77990_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A77990_CLK_RPC),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@@ -83,6 +89,7 @@
/* Core Clock Outputs */
DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1),
DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1),
+ DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z, CLK_PLL0, 4, 8),
DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1),
DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1),
DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1),
@@ -105,9 +112,8 @@
DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078),
DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c),
- DEF_GEN3_RPC("rpc", R8A77990_CLK_RPC, CLK_RPCSRC, 0x238),
-
DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1),
DEF_FIXED("cp", R8A77990_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77990_CLK_CPEX, CLK_EXTAL, 4, 1),
@@ -126,6 +132,11 @@
};
static const struct mssr_mod_clk r8a77990_mod_clks[] = {
+ DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C),
+ DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C),
+ DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C),
+ DEF_MOD("tmu1", 124, R8A77990_CLK_S3D2C),
+ DEF_MOD("tmu0", 125, R8A77990_CLK_CP),
DEF_MOD("scif5", 202, R8A77990_CLK_S3D4C),
DEF_MOD("scif4", 203, R8A77990_CLK_S3D4C),
DEF_MOD("scif3", 204, R8A77990_CLK_S3D4C),
@@ -138,6 +149,7 @@
DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
+ DEF_MOD("sceg-pub", 229, R8A77990_CLK_CR),
DEF_MOD("cmt3", 300, R8A77990_CLK_R),
DEF_MOD("cmt2", 301, R8A77990_CLK_R),
@@ -156,15 +168,15 @@
DEF_MOD("intc-ex", 407, R8A77990_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77990_CLK_S0D3),
- DEF_MOD("audmac0", 502, R8A77990_CLK_S3D4),
- DEF_MOD("drif7", 508, R8A77990_CLK_S3D2),
- DEF_MOD("drif6", 509, R8A77990_CLK_S3D2),
- DEF_MOD("drif5", 510, R8A77990_CLK_S3D2),
- DEF_MOD("drif4", 511, R8A77990_CLK_S3D2),
- DEF_MOD("drif3", 512, R8A77990_CLK_S3D2),
- DEF_MOD("drif2", 513, R8A77990_CLK_S3D2),
- DEF_MOD("drif1", 514, R8A77990_CLK_S3D2),
- DEF_MOD("drif0", 515, R8A77990_CLK_S3D2),
+ DEF_MOD("audmac0", 502, R8A77990_CLK_S1D2),
+ DEF_MOD("drif31", 508, R8A77990_CLK_S3D2),
+ DEF_MOD("drif30", 509, R8A77990_CLK_S3D2),
+ DEF_MOD("drif21", 510, R8A77990_CLK_S3D2),
+ DEF_MOD("drif20", 511, R8A77990_CLK_S3D2),
+ DEF_MOD("drif11", 512, R8A77990_CLK_S3D2),
+ DEF_MOD("drif10", 513, R8A77990_CLK_S3D2),
+ DEF_MOD("drif01", 514, R8A77990_CLK_S3D2),
+ DEF_MOD("drif00", 515, R8A77990_CLK_S3D2),
DEF_MOD("hscif4", 516, R8A77990_CLK_S3D1C),
DEF_MOD("hscif3", 517, R8A77990_CLK_S3D1C),
DEF_MOD("hscif2", 518, R8A77990_CLK_S3D1C),
@@ -184,8 +196,10 @@
DEF_MOD("vspb", 626, R8A77990_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A77990_CLK_S0D1),
- DEF_MOD("ehci0", 703, R8A77990_CLK_S3D4),
- DEF_MOD("hsusb", 704, R8A77990_CLK_S3D4),
+ DEF_MOD("ehci0", 703, R8A77990_CLK_S3D2),
+ DEF_MOD("hsusb", 704, R8A77990_CLK_S3D2),
+ DEF_MOD("cmm1", 710, R8A77990_CLK_S1D1),
+ DEF_MOD("cmm0", 711, R8A77990_CLK_S1D1),
DEF_MOD("csi40", 716, R8A77990_CLK_CSI0),
DEF_MOD("du1", 723, R8A77990_CLK_S1D1),
DEF_MOD("du0", 724, R8A77990_CLK_S1D1),
@@ -290,6 +304,7 @@
.mstp_table = r8a77990_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77990_mstp_table),
.reset_node = "renesas,r8a77990-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = ~0,
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index fb1df6d..83e8e9b 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -70,7 +70,13 @@
DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
+
+ DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
+
+ DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
+ CLK_RPCSRC),
+ DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
+ R8A77995_CLK_RPC),
DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
@@ -93,13 +99,12 @@
DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
+ DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1),
DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
- DEF_GEN3_RPC("rpc", R8A77995_CLK_RPC, CLK_RPCSRC, 0x238),
-
DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
@@ -114,6 +119,11 @@
};
static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+ DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
+ DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
+ DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
+ DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C),
+ DEF_MOD("tmu0", 125, R8A77995_CLK_CP),
DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
@@ -126,6 +136,7 @@
DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
+ DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
DEF_MOD("cmt3", 300, R8A77995_CLK_R),
DEF_MOD("cmt2", 301, R8A77995_CLK_R),
DEF_MOD("cmt1", 302, R8A77995_CLK_R),
@@ -137,7 +148,7 @@
DEF_MOD("rwdt", 402, R8A77995_CLK_R),
DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
- DEF_MOD("audmac0", 502, R8A77995_CLK_S3D1),
+ DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
DEF_MOD("thermal", 522, R8A77995_CLK_CP),
@@ -150,6 +161,8 @@
DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
+ DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1),
+ DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1),
DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
@@ -229,6 +242,7 @@
.mstp_table = r8a77995_mstp_table,
.mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
.reset_node = "renesas,r8a77995-rst",
+ .reset_modemr_offset = CPG_RST_MODEMR,
.mod_clk_base = MOD_CLK_BASE,
.clk_extal_id = CLK_EXTAL,
.clk_extalr_id = ~0,
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.h b/drivers/clk/renesas/rcar-gen2-cpg.h
index 913c932..ca7c3ed 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.h
+++ b/drivers/clk/renesas/rcar-gen2-cpg.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* R-Car Gen2 Clock Pulse Generator
*
* Copyright (C) 2016 Cogent Embedded Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation; version 2 of the License.
*/
#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__
@@ -33,6 +30,8 @@
unsigned int pll0_mult; /* leave as zero if PLL0CR exists */
};
+#define CPG_RST_MODEMR 0x060
+
struct gen2_clk_priv {
void __iomem *base;
struct cpg_mssr_info *info;
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 3beae7d..4fce0a9 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -1,11 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* R-Car Gen3 Clock Pulse Generator
*
- * Copyright (C) 2015-2016 Glider bvba
+ * Copyright (C) 2015-2018 Glider bvba
+ * Copyright (C) 2018 Renesas Electronics Corp.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
*/
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
@@ -22,10 +21,10 @@
CLK_TYPE_GEN3_R,
CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
CLK_TYPE_GEN3_Z,
- CLK_TYPE_GEN3_Z2,
CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
CLK_TYPE_GEN3_RPCSRC,
+ CLK_TYPE_GEN3_E3_RPCSRC,
CLK_TYPE_GEN3_RPC,
CLK_TYPE_GEN3_RPCD2,
@@ -36,8 +35,8 @@
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
-#define DEF_GEN3_RPC(_name, _id, _parent, _offset) \
- DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPC, _parent, .offset = _offset)
+#define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset)
#define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
@@ -59,6 +58,10 @@
#define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
+#define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
+ DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
+ (_parent0) << 16 | (_parent1), .div = 8)
+
struct rcar_gen3_cpg_pll_config {
u8 extal_div;
u8 pll1_mult;
@@ -68,6 +71,8 @@
u8 osc_prediv;
};
+#define CPG_RST_MODEMR 0x060
+
#define CPG_RPCCKCR 0x238
#define CPG_RCKCR 0x240
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 7c1222f..b1cf7f5 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -22,47 +22,6 @@
#include "renesas-cpg-mssr.h"
-/*
- * Module Standby and Software Reset register offets.
- *
- * If the registers exist, these are valid for SH-Mobile, R-Mobile,
- * R-Car Gen2, R-Car Gen3, and RZ/G1.
- * These are NOT valid for R-Car Gen1 and RZ/A1!
- */
-
-/*
- * Module Stop Status Register offsets
- */
-
-static const u16 mstpsr[] = {
- 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
- 0x9A0, 0x9A4, 0x9A8, 0x9AC,
-};
-
-#define MSTPSR(i) mstpsr[i]
-
-
-/*
- * System Module Stop Control Register offsets
- */
-
-static const u16 smstpcr[] = {
- 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
- 0x990, 0x994, 0x998, 0x99C,
-};
-
-#define SMSTPCR(i) smstpcr[i]
-
-
-/* Realtime Module Stop Control Register offsets */
-#define RMSTPCR(i) (smstpcr[i] - 0x20)
-
-/* Modem Module Stop Control Register offsets (r8a73a4) */
-#define MMSTPCR(i) (smstpcr[i] + 0x20)
-
-/* Software Reset Clearing Register offsets */
-#define SRSTCLR(i) (0x940 + (i) * 4)
-
bool renesas_clk_is_mod(struct clk *clk)
{
return (clk->id >> 16) == CPG_MOD;
@@ -132,7 +91,8 @@
return 0;
}
-int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable)
+int renesas_clk_endisable(struct clk *clk, void __iomem *base,
+ struct cpg_mssr_info *info, bool enable)
{
const unsigned long clkid = clk->id & 0xffff;
const unsigned int reg = clkid / 100;
@@ -146,11 +106,11 @@
clkid, reg, bit, enable ? "ON" : "OFF");
if (enable) {
- clrbits_le32(base + SMSTPCR(reg), bitmask);
- return wait_for_bit_le32(base + MSTPSR(reg),
+ clrbits_le32(base + info->control_regs[reg], bitmask);
+ return wait_for_bit_le32(base + info->status_regs[reg],
bitmask, 0, 100, 0);
} else {
- setbits_le32(base + SMSTPCR(reg), bitmask);
+ setbits_le32(base + info->control_regs[reg], bitmask);
return 0;
}
}
@@ -164,7 +124,7 @@
/* Stop module clock */
for (i = 0; i < info->mstp_table_size; i++) {
- clrsetbits_le32(base + SMSTPCR(i),
+ clrsetbits_le32(base + info->control_regs[i],
info->mstp_table[i].sdis,
info->mstp_table[i].sen);
clrsetbits_le32(base + RMSTPCR(i),
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index b669dec..92421b1 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -14,14 +14,21 @@
#define __DRIVERS_CLK_RENESAS_CPG_MSSR__
#include <linux/bitops.h>
+
+enum clk_reg_layout {
+ CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
+};
+
struct cpg_mssr_info {
const struct cpg_core_clk *core_clk;
unsigned int core_clk_size;
+ enum clk_reg_layout reg_layout;
const struct mssr_mod_clk *mod_clk;
unsigned int mod_clk_size;
const struct mstp_stop_table *mstp_table;
unsigned int mstp_table_size;
const char *reset_node;
+ unsigned int reset_modemr_offset;
const char *extalr_node;
const char *extal_usb_node;
unsigned int mod_clk_base;
@@ -30,6 +37,10 @@
unsigned int clk_extal_usb_id;
unsigned int pll0_div;
const void *(*get_pll_config)(const u32 cpg_mode);
+ const u16 *status_regs;
+ const u16 *control_regs;
+ const u16 *reset_regs;
+ const u16 *reset_clear_regs;
};
/*
@@ -114,7 +125,56 @@
const struct cpg_core_clk **core);
int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
struct clk *parent);
-int renesas_clk_endisable(struct clk *clk, void __iomem *base, bool enable);
+int renesas_clk_endisable(struct clk *clk, void __iomem *base,
+ struct cpg_mssr_info *info, bool enable);
int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
+/*
+ * Module Standby and Software Reset register offets.
+ *
+ * If the registers exist, these are valid for SH-Mobile, R-Mobile,
+ * R-Car Gen2, R-Car Gen3, and RZ/G1.
+ * These are NOT valid for R-Car Gen1 and RZ/A1!
+ */
+
+/*
+ * Module Stop Status Register offsets
+ */
+
+static const u16 mstpsr[] = {
+ 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
+ 0x9A0, 0x9A4, 0x9A8, 0x9AC,
+};
+
+/*
+ * System Module Stop Control Register offsets
+ */
+
+static const u16 smstpcr[] = {
+ 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
+ 0x990, 0x994, 0x998, 0x99C,
+};
+
+/*
+ * Software Reset Register offsets
+ */
+
+static const u16 srcr[] = {
+ 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
+ 0x920, 0x924, 0x928, 0x92C,
+};
+
+/* Realtime Module Stop Control Register offsets */
+#define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
+
+/* Modem Module Stop Control Register offsets (r8a73a4) */
+#define MMSTPCR(i) (smstpcr[i] + 0x20)
+
+/* Software Reset Clearing Register offsets */
+
+static const u16 srstclr[] = {
+ 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
+ 0x960, 0x964, 0x968, 0x96C,
+};
+
#endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index 5a838b9..5248e59 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -1014,7 +1014,7 @@
rk3308_clk_init(dev);
/* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
- ret = clk_set_defaults(dev, 1);
+ ret = clk_set_defaults(dev, CLK_DEFAULTS_POST);
if (ret)
debug("%s clk_set_defaults failed %d\n", __func__, ret);
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
index c4d0a1f..20fc004 100644
--- a/drivers/clk/sifive/Kconfig
+++ b/drivers/clk/sifive/Kconfig
@@ -6,11 +6,11 @@
help
SoC drivers for SiFive Linux-capable SoCs.
-config CLK_SIFIVE_FU540_PRCI
- bool "PRCI driver for SiFive FU540 SoCs"
+config CLK_SIFIVE_PRCI
+ bool "PRCI driver for SiFive SoCs"
depends on CLK_SIFIVE
select CLK_ANALOGBITS_WRPLL_CLN28HPC
help
Supports the Power Reset Clock interface (PRCI) IP block found in
- FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC,
- enable this driver.
+ FU540/FU740 SoCs. If this kernel is meant to run on a SiFive FU540/
+ FU740 SoCs, enable this driver.
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
index b224279..51348b1 100644
--- a/drivers/clk/sifive/Makefile
+++ b/drivers/clk/sifive/Makefile
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-2.0+
-obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI) += fu540-prci.o
+obj-y += sifive-prci.o
+
+obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index b3882d0..ceb2c6f 100644
--- a/drivers/clk/sifive/fu540-prci.c
+++ b/drivers/clk/sifive/fu540-prci.c
@@ -5,6 +5,8 @@
* Copyright (C) 2018 SiFive, Inc.
* Wesley Terpstra
* Paul Walmsley
+ * Zong Li
+ * Pragnesh Patel
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -15,632 +17,48 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
- * The FU540 PRCI implements clock and reset control for the SiFive
- * FU540-C000 chip. This driver assumes that it has sole control
- * over all PRCI resources.
- *
- * This driver is based on the PRCI driver written by Wesley Terpstra.
- *
- * Refer, commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
- * https://github.com/riscv/riscv-linux
- *
* References:
* - SiFive FU540-C000 manual v1p0, Chapter 7 "Clocking and Reset"
*/
-#include <common.h>
-#include <clk-uclass.h>
-#include <clk.h>
-#include <div64.h>
-#include <dm.h>
-#include <dm/device.h>
-#include <dm/device_compat.h>
-#include <dm/uclass.h>
#include <dt-bindings/clock/sifive-fu540-prci.h>
-#include <dt-bindings/reset/sifive-fu540-prci.h>
-#include <errno.h>
-#include <reset-uclass.h>
-#include <asm/io.h>
-#include <asm/arch/reset.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/math64.h>
-#include <linux/clk/analogbits-wrpll-cln28hpc.h>
-
-/*
- * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
- * hfclk and rtcclk
- */
-#define EXPECTED_CLK_PARENT_COUNT 2
-
-/*
- * Register offsets and bitmasks
- */
-
-/* COREPLLCFG0 */
-#define PRCI_COREPLLCFG0_OFFSET 0x4
-#define PRCI_COREPLLCFG0_DIVR_SHIFT 0
-#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
-#define PRCI_COREPLLCFG0_DIVF_SHIFT 6
-#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
-#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
-#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
-#define PRCI_COREPLLCFG0_RANGE_SHIFT 18
-#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
-#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
-#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
-#define PRCI_COREPLLCFG0_FSE_SHIFT 25
-#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
-#define PRCI_COREPLLCFG0_LOCK_SHIFT 31
-#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
-
-/* COREPLLCFG1 */
-#define PRCI_COREPLLCFG1_OFFSET 0x8
-#define PRCI_COREPLLCFG1_CKE_SHIFT 31
-#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
-
-/* DDRPLLCFG0 */
-#define PRCI_DDRPLLCFG0_OFFSET 0xc
-#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
-#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
-#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
-#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
-#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
-#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
-#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
-#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
-#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
-#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
-#define PRCI_DDRPLLCFG0_FSE_SHIFT 25
-#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
-#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
-#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
-
-/* DDRPLLCFG1 */
-#define PRCI_DDRPLLCFG1_OFFSET 0x10
-#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
-#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
-
-/* GEMGXLPLLCFG0 */
-#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
-#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
-#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \
- (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
-#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
-#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \
- (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
-#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
-#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
-#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
-#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \
- (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
-#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
-#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \
- (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
-#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
-#define PRCI_GEMGXLPLLCFG0_FSE_MASK \
- (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
-#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
-#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
-
-/* GEMGXLPLLCFG1 */
-#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
-#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
-#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
-
-/* CORECLKSEL */
-#define PRCI_CORECLKSEL_OFFSET 0x24
-#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
-#define PRCI_CORECLKSEL_CORECLKSEL_MASK \
- (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
-
-/* DEVICESRESETREG */
-#define PRCI_DEVICESRESETREG_OFFSET 0x28
-#define PRCI_DEVICERESETCNT 5
-
-#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \
- (0x1 << PRCI_RST_DDR_CTRL_N)
-#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \
- (0x1 << PRCI_RST_DDR_AXI_N)
-#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \
- (0x1 << PRCI_RST_DDR_AHB_N)
-#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \
- (0x1 << PRCI_RST_DDR_PHY_N)
-#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \
- (0x1 << PRCI_RST_GEMGXL_N)
-
-/* CLKMUXSTATUSREG */
-#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
-#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
-#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
- (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
-
-/* PROCMONCFG */
-#define PRCI_PROCMONCFG_OFFSET 0xF0
-#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
-#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
- (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
-
-/*
- * Private structures
- */
-
-/**
- * struct __prci_data - per-device-instance data
- * @va: base virtual address of the PRCI IP block
- * @parent: parent clk instance
- *
- * PRCI per-device instance data
- */
-struct __prci_data {
- void *va;
- struct clk parent_hfclk;
- struct clk parent_rtcclk;
-};
-
-/**
- * struct __prci_wrpll_data - WRPLL configuration and integration data
- * @c: WRPLL current configuration record
- * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
- * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
- * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
- * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
- * @release_reset: fn ptr to code to release clock reset
- *
- * @enable_bypass and @disable_bypass are used for WRPLL instances
- * that contain a separate external glitchless clock mux downstream
- * from the PLL. The WRPLL internal bypass mux is not glitchless.
- */
-struct __prci_wrpll_data {
- struct wrpll_cfg c;
- void (*enable_bypass)(struct __prci_data *pd);
- void (*disable_bypass)(struct __prci_data *pd);
- u8 cfg0_offs;
- u8 cfg1_offs;
- void (*release_reset)(struct __prci_data *pd);
-};
-
-struct __prci_clock;
-
-/* struct __prci_clock_ops - clock operations */
-struct __prci_clock_ops {
- int (*set_rate)(struct __prci_clock *pc,
- unsigned long rate,
- unsigned long parent_rate);
- unsigned long (*round_rate)(struct __prci_clock *pc,
- unsigned long rate,
- unsigned long *parent_rate);
- unsigned long (*recalc_rate)(struct __prci_clock *pc,
- unsigned long parent_rate);
- int (*enable_clk)(struct __prci_clock *pc, bool enable);
-};
-
-/**
- * struct __prci_clock - describes a clock device managed by PRCI
- * @name: user-readable clock name string - should match the manual
- * @parent_name: parent name for this clock
- * @ops: struct __prci_clock_ops for control
- * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
- * @pd: PRCI-specific data associated with this clock (if not NULL)
- *
- * PRCI clock data. Used by the PRCI driver to register PRCI-provided
- * clocks to the Linux clock infrastructure.
- */
-struct __prci_clock {
- const char *name;
- const char *parent_name;
- const struct __prci_clock_ops *ops;
- struct __prci_wrpll_data *pwd;
- struct __prci_data *pd;
-};
-
-/*
- * Private functions
- */
-
-/**
- * __prci_readl() - read from a PRCI register
- * @pd: PRCI context
- * @offs: register offset to read from (in bytes, from PRCI base address)
- *
- * Read the register located at offset @offs from the base virtual
- * address of the PRCI register target described by @pd, and return
- * the value to the caller.
- *
- * Context: Any context.
- *
- * Return: the contents of the register described by @pd and @offs.
- */
-static u32 __prci_readl(struct __prci_data *pd, u32 offs)
-{
- return readl(pd->va + offs);
-}
-
-static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
-{
- writel(v, pd->va + offs);
-}
-
-/* WRPLL-related private functions */
-
-/**
- * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
- * @c: ptr to a struct wrpll_cfg record to write config into
- * @r: value read from the PRCI PLL configuration register
- *
- * Given a value @r read from an FU540 PRCI PLL configuration register,
- * split it into fields and populate it into the WRPLL configuration record
- * pointed to by @c.
- *
- * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
- * have the same register layout.
- *
- * Context: Any context.
- */
-static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
-{
- u32 v;
-
- v = r & PRCI_COREPLLCFG0_DIVR_MASK;
- v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
- c->divr = v;
-
- v = r & PRCI_COREPLLCFG0_DIVF_MASK;
- v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
- c->divf = v;
-
- v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
- v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
- c->divq = v;
-
- v = r & PRCI_COREPLLCFG0_RANGE_MASK;
- v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
- c->range = v;
-
- c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
- WRPLL_FLAGS_EXT_FEEDBACK_MASK);
-
- /* external feedback mode not supported */
- c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
-}
-
-/**
- * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
- * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
- *
- * Using a set of WRPLL configuration values pointed to by @c,
- * assemble a PRCI PLL configuration register value, and return it to
- * the caller.
- *
- * Context: Any context. Caller must ensure that the contents of the
- * record pointed to by @c do not change during the execution
- * of this function.
- *
- * Returns: a value suitable for writing into a PRCI PLL configuration
- * register
- */
-static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
-{
- u32 r = 0;
-
- r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
- r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
- r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
- r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
-
- /* external feedback mode not supported */
- r |= PRCI_COREPLLCFG0_FSE_MASK;
-
- return r;
-}
-
-/**
- * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
- * @pd: PRCI context
- * @pwd: PRCI WRPLL metadata
- *
- * Read the current configuration of the PLL identified by @pwd from
- * the PRCI identified by @pd, and store it into the local configuration
- * cache in @pwd.
- *
- * Context: Any context. Caller must prevent the records pointed to by
- * @pd and @pwd from changing during execution.
- */
-static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd)
-{
- __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
-}
-
-/**
- * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
- * @pd: PRCI context
- * @pwd: PRCI WRPLL metadata
- * @c: WRPLL configuration record to write
- *
- * Write the WRPLL configuration described by @c into the WRPLL
- * configuration register identified by @pwd in the PRCI instance
- * described by @c. Make a cached copy of the WRPLL's current
- * configuration so it can be used by other code.
- *
- * Context: Any context. Caller must prevent the records pointed to by
- * @pd and @pwd from changing during execution.
- */
-static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd,
- struct wrpll_cfg *c)
-{
- __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
-
- memcpy(&pwd->c, c, sizeof(*c));
-}
-
-/**
- * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
- * into the PRCI
- * @pd: PRCI context
- * @pwd: PRCI WRPLL metadata
- * @enable: Clock enable or disable value
- */
-static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
- struct __prci_wrpll_data *pwd,
- u32 enable)
-{
- __prci_writel(enable, pwd->cfg1_offs, pd);
-}
-
-/* Core clock mux control */
-
-/**
- * __prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
- * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
- *
- * Switch the CORECLK mux to the HFCLK input source; return once complete.
- *
- * Context: Any context. Caller must prevent concurrent changes to the
- * PRCI_CORECLKSEL_OFFSET register.
- */
-static void __prci_coreclksel_use_hfclk(struct __prci_data *pd)
-{
- u32 r;
-
- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
- r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
- __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
-
- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
-}
-
-/**
- * __prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
- * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
- *
- * Switch the CORECLK mux to the PLL output clock; return once complete.
- *
- * Context: Any context. Caller must prevent concurrent changes to the
- * PRCI_CORECLKSEL_OFFSET register.
- */
-static void __prci_coreclksel_use_corepll(struct __prci_data *pd)
-{
- u32 r;
-
- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
- r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
- __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
-
- r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
-}
-
-static unsigned long sifive_fu540_prci_wrpll_recalc_rate(
- struct __prci_clock *pc,
- unsigned long parent_rate)
-{
- struct __prci_wrpll_data *pwd = pc->pwd;
-
- return wrpll_calc_output_rate(&pwd->c, parent_rate);
-}
-static unsigned long sifive_fu540_prci_wrpll_round_rate(
- struct __prci_clock *pc,
- unsigned long rate,
- unsigned long *parent_rate)
-{
- struct __prci_wrpll_data *pwd = pc->pwd;
- struct wrpll_cfg c;
+#include "sifive-prci.h"
- memcpy(&c, &pwd->c, sizeof(c));
-
- wrpll_configure_for_rate(&c, rate, *parent_rate);
-
- return wrpll_calc_output_rate(&c, *parent_rate);
-}
-
-static int sifive_fu540_prci_wrpll_set_rate(struct __prci_clock *pc,
- unsigned long rate,
- unsigned long parent_rate)
-{
- struct __prci_wrpll_data *pwd = pc->pwd;
- struct __prci_data *pd = pc->pd;
- int r;
-
- r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
- if (r)
- return r;
-
- if (pwd->enable_bypass)
- pwd->enable_bypass(pd);
-
- __prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
-
- udelay(wrpll_calc_max_lock_us(&pwd->c));
-
- if (pwd->disable_bypass)
- pwd->disable_bypass(pd);
-
- return 0;
-}
-
-static int sifive_fu540_prci_clock_enable(struct __prci_clock *pc, bool enable)
-{
- struct __prci_wrpll_data *pwd = pc->pwd;
- struct __prci_data *pd = pc->pd;
-
- if (enable) {
- __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
-
- if (pwd->release_reset)
- pwd->release_reset(pd);
- } else {
- u32 r;
-
- r = __prci_readl(pd, pwd->cfg1_offs);
- r &= ~PRCI_COREPLLCFG1_CKE_MASK;
-
- __prci_wrpll_write_cfg1(pd, pwd, r);
- }
-
- return 0;
-}
-
-static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
- .set_rate = sifive_fu540_prci_wrpll_set_rate,
- .round_rate = sifive_fu540_prci_wrpll_round_rate,
- .recalc_rate = sifive_fu540_prci_wrpll_recalc_rate,
- .enable_clk = sifive_fu540_prci_clock_enable,
-};
-
-/* TLCLKSEL clock integration */
-
-static unsigned long sifive_fu540_prci_tlclksel_recalc_rate(
- struct __prci_clock *pc,
- unsigned long parent_rate)
-{
- struct __prci_data *pd = pc->pd;
- u32 v;
- u8 div;
-
- v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
- v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
- div = v ? 1 : 2;
-
- return div_u64(parent_rate, div);
-}
-
-static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
- .recalc_rate = sifive_fu540_prci_tlclksel_recalc_rate,
-};
-
-static int __prci_consumer_reset(const char *rst_name, bool trigger)
-{
- struct udevice *dev;
- struct reset_ctl rst_sig;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_RESET,
- DM_DRIVER_GET(sifive_reset),
- &dev);
- if (ret) {
- dev_err(dev, "Reset driver not found: %d\n", ret);
- return ret;
- }
-
- ret = reset_get_by_name(dev, rst_name, &rst_sig);
- if (ret) {
- dev_err(dev, "failed to get %s reset\n", rst_name);
- return ret;
- }
-
- if (reset_valid(&rst_sig)) {
- if (trigger)
- ret = reset_deassert(&rst_sig);
- else
- ret = reset_assert(&rst_sig);
- if (ret) {
- dev_err(dev, "failed to trigger reset id = %ld\n",
- rst_sig.id);
- return ret;
- }
- }
-
- return ret;
-}
-
-/**
- * __prci_ddr_release_reset() - Release DDR reset
- * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
- *
- */
-static void __prci_ddr_release_reset(struct __prci_data *pd)
-{
- /* Release DDR ctrl reset */
- __prci_consumer_reset("ddr_ctrl", true);
-
- /* HACK to get the '1 full controller clock cycle'. */
- asm volatile ("fence");
-
- /* Release DDR AXI reset */
- __prci_consumer_reset("ddr_axi", true);
-
- /* Release DDR AHB reset */
- __prci_consumer_reset("ddr_ahb", true);
-
- /* Release DDR PHY reset */
- __prci_consumer_reset("ddr_phy", true);
-
- /* HACK to get the '1 full controller clock cycle'. */
- asm volatile ("fence");
-
- /*
- * These take like 16 cycles to actually propagate. We can't go sending
- * stuff before they come out of reset. So wait.
- */
- for (int i = 0; i < 256; i++)
- asm volatile ("nop");
-}
-
-/**
- * __prci_ethernet_release_reset() - Release ethernet reset
- * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
- *
- */
-static void __prci_ethernet_release_reset(struct __prci_data *pd)
-{
- /* Release GEMGXL reset */
- __prci_consumer_reset("gemgxl_reset", true);
-
- /* Procmon => core clock */
- __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
- pd);
-}
-
-/*
- * PRCI integration data for each WRPLL instance
- */
-
+/* PRCI integration data for each WRPLL instance */
static struct __prci_wrpll_data __prci_corepll_data = {
.cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
.cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
- .enable_bypass = __prci_coreclksel_use_hfclk,
- .disable_bypass = __prci_coreclksel_use_corepll,
+ .enable_bypass = sifive_prci_coreclksel_use_hfclk,
+ .disable_bypass = sifive_prci_coreclksel_use_corepll,
};
static struct __prci_wrpll_data __prci_ddrpll_data = {
.cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
.cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
- .release_reset = __prci_ddr_release_reset,
+ .release_reset = sifive_prci_ddr_release_reset,
};
static struct __prci_wrpll_data __prci_gemgxlpll_data = {
.cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
.cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
- .release_reset = __prci_ethernet_release_reset,
+ .release_reset = sifive_prci_ethernet_release_reset,
};
-/*
- * List of clock controls provided by the PRCI
- */
+/* Linux clock framework integration */
+static const struct __prci_clock_ops sifive_fu540_prci_wrpll_clk_ops = {
+ .set_rate = sifive_prci_wrpll_set_rate,
+ .round_rate = sifive_prci_wrpll_round_rate,
+ .recalc_rate = sifive_prci_wrpll_recalc_rate,
+ .enable_clk = sifive_prci_clock_enable,
+};
-static struct __prci_clock __prci_init_clocks[] = {
+static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = {
+ .recalc_rate = sifive_prci_tlclksel_recalc_rate,
+};
+
+/* List of clock controls provided by the PRCI */
+struct __prci_clock __prci_init_clocks_fu540[] = {
[PRCI_CLK_COREPLL] = {
.name = "corepll",
.parent_name = "hfclk",
@@ -665,148 +83,3 @@
.ops = &sifive_fu540_prci_tlclksel_clk_ops,
},
};
-
-static ulong sifive_fu540_prci_parent_rate(struct __prci_clock *pc)
-{
- ulong parent_rate;
- struct __prci_clock *p;
-
- if (strcmp(pc->parent_name, "corepll") == 0) {
- p = &__prci_init_clocks[PRCI_CLK_COREPLL];
- if (!p->pd || !p->ops->recalc_rate)
- return -ENXIO;
-
- return p->ops->recalc_rate(p, sifive_fu540_prci_parent_rate(p));
- }
-
- if (strcmp(pc->parent_name, "rtcclk") == 0)
- parent_rate = clk_get_rate(&pc->pd->parent_rtcclk);
- else
- parent_rate = clk_get_rate(&pc->pd->parent_hfclk);
-
- return parent_rate;
-}
-
-static ulong sifive_fu540_prci_get_rate(struct clk *clk)
-{
- struct __prci_clock *pc;
-
- if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
- return -ENXIO;
-
- pc = &__prci_init_clocks[clk->id];
- if (!pc->pd || !pc->ops->recalc_rate)
- return -ENXIO;
-
- return pc->ops->recalc_rate(pc, sifive_fu540_prci_parent_rate(pc));
-}
-
-static ulong sifive_fu540_prci_set_rate(struct clk *clk, ulong rate)
-{
- int err;
- struct __prci_clock *pc;
-
- if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
- return -ENXIO;
-
- pc = &__prci_init_clocks[clk->id];
- if (!pc->pd || !pc->ops->set_rate)
- return -ENXIO;
-
- err = pc->ops->set_rate(pc, rate, sifive_fu540_prci_parent_rate(pc));
- if (err)
- return err;
-
- return rate;
-}
-
-static int sifive_fu540_prci_enable(struct clk *clk)
-{
- struct __prci_clock *pc;
- int ret = 0;
-
- if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
- return -ENXIO;
-
- pc = &__prci_init_clocks[clk->id];
- if (!pc->pd)
- return -ENXIO;
-
- if (pc->ops->enable_clk)
- ret = pc->ops->enable_clk(pc, 1);
-
- return ret;
-}
-
-static int sifive_fu540_prci_disable(struct clk *clk)
-{
- struct __prci_clock *pc;
- int ret = 0;
-
- if (ARRAY_SIZE(__prci_init_clocks) <= clk->id)
- return -ENXIO;
-
- pc = &__prci_init_clocks[clk->id];
- if (!pc->pd)
- return -ENXIO;
-
- if (pc->ops->enable_clk)
- ret = pc->ops->enable_clk(pc, 0);
-
- return ret;
-}
-
-static int sifive_fu540_prci_probe(struct udevice *dev)
-{
- int i, err;
- struct __prci_clock *pc;
- struct __prci_data *pd = dev_get_priv(dev);
-
- pd->va = (void *)dev_read_addr(dev);
- if (IS_ERR(pd->va))
- return PTR_ERR(pd->va);
-
- err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
- if (err)
- return err;
-
- err = clk_get_by_index(dev, 1, &pd->parent_rtcclk);
- if (err)
- return err;
-
- for (i = 0; i < ARRAY_SIZE(__prci_init_clocks); ++i) {
- pc = &__prci_init_clocks[i];
- pc->pd = pd;
- if (pc->pwd)
- __prci_wrpll_read_cfg0(pd, pc->pwd);
- }
-
- return 0;
-}
-
-static struct clk_ops sifive_fu540_prci_ops = {
- .set_rate = sifive_fu540_prci_set_rate,
- .get_rate = sifive_fu540_prci_get_rate,
- .enable = sifive_fu540_prci_enable,
- .disable = sifive_fu540_prci_disable,
-};
-
-static int sifive_fu540_clk_bind(struct udevice *dev)
-{
- return sifive_reset_bind(dev, PRCI_DEVICERESETCNT);
-}
-
-static const struct udevice_id sifive_fu540_prci_ids[] = {
- { .compatible = "sifive,fu540-c000-prci" },
- { }
-};
-
-U_BOOT_DRIVER(sifive_fu540_prci) = {
- .name = "sifive-fu540-prci",
- .id = UCLASS_CLK,
- .of_match = sifive_fu540_prci_ids,
- .probe = sifive_fu540_prci_probe,
- .ops = &sifive_fu540_prci_ops,
- .priv_auto = sizeof(struct __prci_data),
- .bind = sifive_fu540_clk_bind,
-};
diff --git a/drivers/clk/sifive/fu540-prci.h b/drivers/clk/sifive/fu540-prci.h
new file mode 100644
index 0000000..1133011
--- /dev/null
+++ b/drivers/clk/sifive/fu540-prci.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ * Zong Li
+ * Pragnesh Patel
+ */
+
+#ifndef __SIFIVE_CLK_FU540_PRCI_H
+#define __SIFIVE_CLK_FU540_PRCI_H
+
+#include "sifive-prci.h"
+
+#define NUM_CLOCK_FU540 4
+
+extern struct __prci_clock __prci_init_clocks_fu540[NUM_CLOCK_FU540];
+
+static const struct prci_clk_desc prci_clk_fu540 = {
+ .clks = __prci_init_clocks_fu540,
+ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu540),
+};
+
+#endif /* __SIFIVE_CLK_FU540_PRCI_H */
diff --git a/drivers/clk/sifive/fu740-prci.c b/drivers/clk/sifive/fu740-prci.c
new file mode 100644
index 0000000..9a642c1
--- /dev/null
+++ b/drivers/clk/sifive/fu740-prci.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2021 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ * Zong Li
+ * Pragnesh Patel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/clock/sifive-fu740-prci.h>
+#include "sifive-prci.h"
+#include <asm/io.h>
+
+int sifive_prci_fu740_pciauxclk_enable(struct __prci_clock *pc, bool enable)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+ struct __prci_data *pd = pc->pd;
+ u32 v;
+
+ if (pwd->cfg1_offs != PRCI_PCIEAUXCFG1_OFFSET)
+ return -EINVAL;
+
+ v = readl(pd->va + pwd->cfg1_offs);
+ v = enable ? (v | PRCI_PCIEAUXCFG1_MASK) : (v & ~PRCI_PCIEAUXCFG1_MASK);
+ writel(v, pd->va + pwd->cfg1_offs);
+
+ return 0;
+}
+
+/* PRCI integration data for each WRPLL instance */
+static struct __prci_wrpll_data __prci_corepll_data = {
+ .cfg0_offs = PRCI_COREPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_COREPLLCFG1_OFFSET,
+ .enable_bypass = sifive_prci_coreclksel_use_hfclk,
+ .disable_bypass = sifive_prci_coreclksel_use_final_corepll,
+};
+
+static struct __prci_wrpll_data __prci_ddrpll_data = {
+ .cfg0_offs = PRCI_DDRPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_DDRPLLCFG1_OFFSET,
+ .release_reset = sifive_prci_ddr_release_reset,
+};
+
+static struct __prci_wrpll_data __prci_gemgxlpll_data = {
+ .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET,
+ .release_reset = sifive_prci_ethernet_release_reset,
+};
+
+static struct __prci_wrpll_data __prci_dvfscorepll_data = {
+ .cfg0_offs = PRCI_DVFSCOREPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_DVFSCOREPLLCFG1_OFFSET,
+ .enable_bypass = sifive_prci_corepllsel_use_corepll,
+ .disable_bypass = sifive_prci_corepllsel_use_dvfscorepll,
+};
+
+static struct __prci_wrpll_data __prci_hfpclkpll_data = {
+ .cfg0_offs = PRCI_HFPCLKPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_HFPCLKPLLCFG1_OFFSET,
+ .enable_bypass = sifive_prci_hfpclkpllsel_use_hfclk,
+ .disable_bypass = sifive_prci_hfpclkpllsel_use_hfpclkpll,
+};
+
+static struct __prci_wrpll_data __prci_cltxpll_data = {
+ .cfg0_offs = PRCI_CLTXPLLCFG0_OFFSET,
+ .cfg1_offs = PRCI_CLTXPLLCFG1_OFFSET,
+ .release_reset = sifive_prci_cltx_release_reset,
+};
+
+static struct __prci_wrpll_data __prci_pcieaux_data = {
+ .cfg1_offs = PRCI_PCIEAUXCFG1_OFFSET,
+};
+
+/* Linux clock framework integration */
+
+static const struct __prci_clock_ops sifive_fu740_prci_wrpll_clk_ops = {
+ .set_rate = sifive_prci_wrpll_set_rate,
+ .round_rate = sifive_prci_wrpll_round_rate,
+ .recalc_rate = sifive_prci_wrpll_recalc_rate,
+ .enable_clk = sifive_prci_clock_enable,
+};
+
+static const struct __prci_clock_ops sifive_fu740_prci_tlclksel_clk_ops = {
+ .recalc_rate = sifive_prci_tlclksel_recalc_rate,
+};
+
+static const struct __prci_clock_ops sifive_fu740_prci_hfpclkplldiv_clk_ops = {
+ .recalc_rate = sifive_prci_hfpclkplldiv_recalc_rate,
+};
+
+static const struct __prci_clock_ops sifive_fu740_prci_pcieaux_clk_ops = {
+ .enable_clk = sifive_prci_fu740_pciauxclk_enable,
+};
+
+/* List of clock controls provided by the PRCI */
+struct __prci_clock __prci_init_clocks_fu740[] = {
+ [PRCI_CLK_COREPLL] = {
+ .name = "corepll",
+ .parent_name = "hfclk",
+ .ops = &sifive_fu740_prci_wrpll_clk_ops,
+ .pwd = &__prci_corepll_data,
+ },
+ [PRCI_CLK_DDRPLL] = {
+ .name = "ddrpll",
+ .parent_name = "hfclk",
+ .ops = &sifive_fu740_prci_wrpll_clk_ops,
+ .pwd = &__prci_ddrpll_data,
+ },
+ [PRCI_CLK_GEMGXLPLL] = {
+ .name = "gemgxlpll",
+ .parent_name = "hfclk",
+ .ops = &sifive_fu740_prci_wrpll_clk_ops,
+ .pwd = &__prci_gemgxlpll_data,
+ },
+ [PRCI_CLK_DVFSCOREPLL] = {
+ .name = "dvfscorepll",
+ .parent_name = "hfclk",
+ .ops = &sifive_fu740_prci_wrpll_clk_ops,
+ .pwd = &__prci_dvfscorepll_data,
+ },
+ [PRCI_CLK_HFPCLKPLL] = {
+ .name = "hfpclkpll",
+ .parent_name = "hfclk",
+ .ops = &sifive_fu740_prci_wrpll_clk_ops,
+ .pwd = &__prci_hfpclkpll_data,
+ },
+ [PRCI_CLK_CLTXPLL] = {
+ .name = "cltxpll",
+ .parent_name = "hfclk",
+ .ops = &sifive_fu740_prci_wrpll_clk_ops,
+ .pwd = &__prci_cltxpll_data,
+ },
+ [PRCI_CLK_TLCLK] = {
+ .name = "tlclk",
+ .parent_name = "corepll",
+ .ops = &sifive_fu740_prci_tlclksel_clk_ops,
+ },
+ [PRCI_CLK_PCLK] = {
+ .name = "pclk",
+ .parent_name = "hfpclkpll",
+ .ops = &sifive_fu740_prci_hfpclkplldiv_clk_ops,
+ },
+ [PRCI_CLK_PCIEAUX] {
+ .name = "pciaux",
+ .parent_name = "",
+ .ops = &sifive_fu740_prci_pcieaux_clk_ops,
+ .pwd = &__prci_pcieaux_data,
+ }
+};
diff --git a/drivers/clk/sifive/fu740-prci.h b/drivers/clk/sifive/fu740-prci.h
new file mode 100644
index 0000000..b74f078
--- /dev/null
+++ b/drivers/clk/sifive/fu740-prci.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ * Zong Li
+ * Pragnesh Patel
+ */
+
+#ifndef __SIFIVE_CLK_FU740_PRCI_H
+#define __SIFIVE_CLK_FU740_PRCI_H
+
+#include "sifive-prci.h"
+
+#define NUM_CLOCK_FU740 9
+
+extern struct __prci_clock __prci_init_clocks_fu740[NUM_CLOCK_FU740];
+
+static const struct prci_clk_desc prci_clk_fu740 = {
+ .clks = __prci_init_clocks_fu740,
+ .num_clks = ARRAY_SIZE(__prci_init_clocks_fu740),
+};
+
+#endif /* __SIFIVE_CLK_FU740_PRCI_H */
diff --git a/drivers/clk/sifive/sifive-prci.c b/drivers/clk/sifive/sifive-prci.c
new file mode 100644
index 0000000..cd1acb9
--- /dev/null
+++ b/drivers/clk/sifive/sifive-prci.c
@@ -0,0 +1,733 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018-2021 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ * Zong Li
+ * Pragnesh Patel
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * The PRCI implements clock and reset control for the SiFive chip.
+ * This driver assumes that it has sole control over all PRCI resources.
+ *
+ * This driver is based on the PRCI driver written by Wesley Terpstra:
+ * https://github.com/riscv/riscv-linux/commit/999529edf517ed75b56659d456d221b2ee56bb60
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <reset.h>
+#include <asm/io.h>
+#include <asm/arch/reset.h>
+#include <linux/delay.h>
+#include <linux/math64.h>
+#include <dt-bindings/clock/sifive-fu740-prci.h>
+
+#include "fu540-prci.h"
+#include "fu740-prci.h"
+
+/*
+ * Private functions
+ */
+
+/**
+ * __prci_readl() - read from a PRCI register
+ * @pd: PRCI context
+ * @offs: register offset to read from (in bytes, from PRCI base address)
+ *
+ * Read the register located at offset @offs from the base virtual
+ * address of the PRCI register target described by @pd, and return
+ * the value to the caller.
+ *
+ * Context: Any context.
+ *
+ * Return: the contents of the register described by @pd and @offs.
+ */
+static u32 __prci_readl(struct __prci_data *pd, u32 offs)
+{
+ return readl(pd->va + offs);
+}
+
+static void __prci_writel(u32 v, u32 offs, struct __prci_data *pd)
+{
+ writel(v, pd->va + offs);
+}
+
+/* WRPLL-related private functions */
+
+/**
+ * __prci_wrpll_unpack() - unpack WRPLL configuration registers into parameters
+ * @c: ptr to a struct wrpll_cfg record to write config into
+ * @r: value read from the PRCI PLL configuration register
+ *
+ * Given a value @r read from an FU540 PRCI PLL configuration register,
+ * split it into fields and populate it into the WRPLL configuration record
+ * pointed to by @c.
+ *
+ * The COREPLLCFG0 macros are used below, but the other *PLLCFG0 macros
+ * have the same register layout.
+ *
+ * Context: Any context.
+ */
+static void __prci_wrpll_unpack(struct wrpll_cfg *c, u32 r)
+{
+ u32 v;
+
+ v = r & PRCI_COREPLLCFG0_DIVR_MASK;
+ v >>= PRCI_COREPLLCFG0_DIVR_SHIFT;
+ c->divr = v;
+
+ v = r & PRCI_COREPLLCFG0_DIVF_MASK;
+ v >>= PRCI_COREPLLCFG0_DIVF_SHIFT;
+ c->divf = v;
+
+ v = r & PRCI_COREPLLCFG0_DIVQ_MASK;
+ v >>= PRCI_COREPLLCFG0_DIVQ_SHIFT;
+ c->divq = v;
+
+ v = r & PRCI_COREPLLCFG0_RANGE_MASK;
+ v >>= PRCI_COREPLLCFG0_RANGE_SHIFT;
+ c->range = v;
+
+ c->flags &= (WRPLL_FLAGS_INT_FEEDBACK_MASK |
+ WRPLL_FLAGS_EXT_FEEDBACK_MASK);
+
+ /* external feedback mode not supported */
+ c->flags |= WRPLL_FLAGS_INT_FEEDBACK_MASK;
+}
+
+/**
+ * __prci_wrpll_pack() - pack PLL configuration parameters into a register value
+ * @c: pointer to a struct wrpll_cfg record containing the PLL's cfg
+ *
+ * Using a set of WRPLL configuration values pointed to by @c,
+ * assemble a PRCI PLL configuration register value, and return it to
+ * the caller.
+ *
+ * Context: Any context. Caller must ensure that the contents of the
+ * record pointed to by @c do not change during the execution
+ * of this function.
+ *
+ * Returns: a value suitable for writing into a PRCI PLL configuration
+ * register
+ */
+static u32 __prci_wrpll_pack(const struct wrpll_cfg *c)
+{
+ u32 r = 0;
+
+ r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT;
+ r |= c->divf << PRCI_COREPLLCFG0_DIVF_SHIFT;
+ r |= c->divq << PRCI_COREPLLCFG0_DIVQ_SHIFT;
+ r |= c->range << PRCI_COREPLLCFG0_RANGE_SHIFT;
+
+ /* external feedback mode not supported */
+ r |= PRCI_COREPLLCFG0_FSE_MASK;
+
+ return r;
+}
+
+/**
+ * __prci_wrpll_read_cfg0() - read the WRPLL configuration from the PRCI
+ * @pd: PRCI context
+ * @pwd: PRCI WRPLL metadata
+ *
+ * Read the current configuration of the PLL identified by @pwd from
+ * the PRCI identified by @pd, and store it into the local configuration
+ * cache in @pwd.
+ *
+ * Context: Any context. Caller must prevent the records pointed to by
+ * @pd and @pwd from changing during execution.
+ */
+static void __prci_wrpll_read_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd)
+{
+ __prci_wrpll_unpack(&pwd->c, __prci_readl(pd, pwd->cfg0_offs));
+}
+
+/**
+ * __prci_wrpll_write_cfg0() - write WRPLL configuration into the PRCI
+ * @pd: PRCI context
+ * @pwd: PRCI WRPLL metadata
+ * @c: WRPLL configuration record to write
+ *
+ * Write the WRPLL configuration described by @c into the WRPLL
+ * configuration register identified by @pwd in the PRCI instance
+ * described by @c. Make a cached copy of the WRPLL's current
+ * configuration so it can be used by other code.
+ *
+ * Context: Any context. Caller must prevent the records pointed to by
+ * @pd and @pwd from changing during execution.
+ */
+static void __prci_wrpll_write_cfg0(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ struct wrpll_cfg *c)
+{
+ __prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
+
+ memcpy(&pwd->c, c, sizeof(*c));
+}
+
+/**
+ * __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
+ * into the PRCI
+ * @pd: PRCI context
+ * @pwd: PRCI WRPLL metadata
+ * @enable: Clock enable or disable value
+ */
+static void __prci_wrpll_write_cfg1(struct __prci_data *pd,
+ struct __prci_wrpll_data *pwd,
+ u32 enable)
+{
+ __prci_writel(enable, pwd->cfg1_offs, pd);
+}
+
+unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc,
+ unsigned long parent_rate)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+
+ return wrpll_calc_output_rate(&pwd->c, parent_rate);
+}
+
+unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+ struct wrpll_cfg c;
+
+ memcpy(&c, &pwd->c, sizeof(c));
+
+ wrpll_configure_for_rate(&c, rate, *parent_rate);
+
+ return wrpll_calc_output_rate(&c, *parent_rate);
+}
+
+int sifive_prci_wrpll_set_rate(struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+ struct __prci_data *pd = pc->pd;
+ int r;
+
+ r = wrpll_configure_for_rate(&pwd->c, rate, parent_rate);
+ if (r)
+ return r;
+
+ if (pwd->enable_bypass)
+ pwd->enable_bypass(pd);
+
+ __prci_wrpll_write_cfg0(pd, pwd, &pwd->c);
+
+ udelay(wrpll_calc_max_lock_us(&pwd->c));
+
+ return 0;
+}
+
+int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable)
+{
+ struct __prci_wrpll_data *pwd = pc->pwd;
+ struct __prci_data *pd = pc->pd;
+
+ if (enable) {
+ __prci_wrpll_write_cfg1(pd, pwd, PRCI_COREPLLCFG1_CKE_MASK);
+
+ if (pwd->disable_bypass)
+ pwd->disable_bypass(pd);
+
+ if (pwd->release_reset)
+ pwd->release_reset(pd);
+ } else {
+ u32 r;
+
+ if (pwd->enable_bypass)
+ pwd->enable_bypass(pd);
+
+ r = __prci_readl(pd, pwd->cfg1_offs);
+ r &= ~PRCI_COREPLLCFG1_CKE_MASK;
+
+ __prci_wrpll_write_cfg1(pd, pwd, r);
+ }
+
+ return 0;
+}
+
+/* TLCLKSEL clock integration */
+
+unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc,
+ unsigned long parent_rate)
+{
+ struct __prci_data *pd = pc->pd;
+ u32 v;
+ u8 div;
+
+ v = __prci_readl(pd, PRCI_CLKMUXSTATUSREG_OFFSET);
+ v &= PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK;
+ div = v ? 1 : 2;
+
+ return div_u64(parent_rate, div);
+}
+
+/* HFPCLK clock integration */
+
+unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc,
+ unsigned long parent_rate)
+{
+ struct __prci_data *pd = pc->pd;
+ u32 div = __prci_readl(pd, PRCI_HFPCLKPLLDIV_OFFSET);
+
+ return div_u64(parent_rate, div + 2);
+}
+
+/**
+ * sifive_prci_coreclksel_use_final_corepll() - switch the CORECLK mux to output
+ * FINAL_COREPLL
+ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
+ *
+ * Switch the CORECLK mux to the final COREPLL output clock; return once
+ * complete.
+ *
+ * Context: Any context. Caller must prevent concurrent changes to the
+ * PRCI_CORECLKSEL_OFFSET register.
+ */
+void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd)
+{
+ u32 r;
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
+ r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
+ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
+}
+
+/**
+ * sifive_prci_corepllsel_use_dvfscorepll() - switch the COREPLL mux to
+ * output DVFS_COREPLL
+ * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
+ *
+ * Switch the COREPLL mux to the DVFSCOREPLL output clock; return once complete.
+ *
+ * Context: Any context. Caller must prevent concurrent changes to the
+ * PRCI_COREPLLSEL_OFFSET register.
+ */
+void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd)
+{
+ u32 r;
+
+ r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
+ r |= PRCI_COREPLLSEL_COREPLLSEL_MASK;
+ __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
+
+ r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
+}
+
+/**
+ * sifive_prci_corepllsel_use_corepll() - switch the COREPLL mux to
+ * output COREPLL
+ * @pd: struct __prci_data * for the PRCI containing the COREPLL mux reg
+ *
+ * Switch the COREPLL mux to the COREPLL output clock; return once complete.
+ *
+ * Context: Any context. Caller must prevent concurrent changes to the
+ * PRCI_COREPLLSEL_OFFSET register.
+ */
+void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd)
+{
+ u32 r;
+
+ r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET);
+ r &= ~PRCI_COREPLLSEL_COREPLLSEL_MASK;
+ __prci_writel(r, PRCI_COREPLLSEL_OFFSET, pd);
+
+ r = __prci_readl(pd, PRCI_COREPLLSEL_OFFSET); /* barrier */
+}
+
+/**
+ * sifive_prci_hfpclkpllsel_use_hfclk() - switch the HFPCLKPLL mux to
+ * output HFCLK
+ * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
+ *
+ * Switch the HFPCLKPLL mux to the HFCLK input source; return once complete.
+ *
+ * Context: Any context. Caller must prevent concurrent changes to the
+ * PRCI_HFPCLKPLLSEL_OFFSET register.
+ */
+void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd)
+{
+ u32 r;
+
+ r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
+ r |= PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
+ __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
+
+ r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
+}
+
+/**
+ * sifive_prci_hfpclkpllsel_use_hfpclkpll() - switch the HFPCLKPLL mux to
+ * output HFPCLKPLL
+ * @pd: struct __prci_data * for the PRCI containing the HFPCLKPLL mux reg
+ *
+ * Switch the HFPCLKPLL mux to the HFPCLKPLL output clock; return once complete.
+ *
+ * Context: Any context. Caller must prevent concurrent changes to the
+ * PRCI_HFPCLKPLLSEL_OFFSET register.
+ */
+void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd)
+{
+ u32 r;
+
+ r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET);
+ r &= ~PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK;
+ __prci_writel(r, PRCI_HFPCLKPLLSEL_OFFSET, pd);
+
+ r = __prci_readl(pd, PRCI_HFPCLKPLLSEL_OFFSET); /* barrier */
+}
+
+static int __prci_consumer_reset(const char *rst_name, bool trigger)
+{
+ struct udevice *dev;
+ struct reset_ctl rst_sig;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_RESET,
+ DM_DRIVER_GET(sifive_reset),
+ &dev);
+ if (ret) {
+ dev_err(dev, "Reset driver not found: %d\n", ret);
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, rst_name, &rst_sig);
+ if (ret) {
+ dev_err(dev, "failed to get %s reset\n", rst_name);
+ return ret;
+ }
+
+ if (reset_valid(&rst_sig)) {
+ if (trigger)
+ ret = reset_deassert(&rst_sig);
+ else
+ ret = reset_assert(&rst_sig);
+ if (ret) {
+ dev_err(dev, "failed to trigger reset id = %ld\n",
+ rst_sig.id);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * sifive_prci_ddr_release_reset() - Release DDR reset
+ * @pd: struct __prci_data * for the PRCI containing the DDRCLK mux reg
+ *
+ */
+void sifive_prci_ddr_release_reset(struct __prci_data *pd)
+{
+ /* Release DDR ctrl reset */
+ __prci_consumer_reset("ddr_ctrl", true);
+
+ /* HACK to get the '1 full controller clock cycle'. */
+ asm volatile ("fence");
+
+ /* Release DDR AXI reset */
+ __prci_consumer_reset("ddr_axi", true);
+
+ /* Release DDR AHB reset */
+ __prci_consumer_reset("ddr_ahb", true);
+
+ /* Release DDR PHY reset */
+ __prci_consumer_reset("ddr_phy", true);
+
+ /* HACK to get the '1 full controller clock cycle'. */
+ asm volatile ("fence");
+
+ /*
+ * These take like 16 cycles to actually propagate. We can't go sending
+ * stuff before they come out of reset. So wait.
+ */
+ for (int i = 0; i < 256; i++)
+ asm volatile ("nop");
+}
+
+/**
+ * sifive_prci_ethernet_release_reset() - Release ethernet reset
+ * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
+ *
+ */
+void sifive_prci_ethernet_release_reset(struct __prci_data *pd)
+{
+ /* Release GEMGXL reset */
+ __prci_consumer_reset("gemgxl_reset", true);
+
+ /* Procmon => core clock */
+ __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET,
+ pd);
+
+ /* Release Chiplink reset */
+ __prci_consumer_reset("cltx_reset", true);
+}
+
+/**
+ * sifive_prci_cltx_release_reset() - Release cltx reset
+ * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg
+ *
+ */
+void sifive_prci_cltx_release_reset(struct __prci_data *pd)
+{
+ /* Release CLTX reset */
+ __prci_consumer_reset("cltx_reset", true);
+}
+
+/* Core clock mux control */
+
+/**
+ * sifive_prci_coreclksel_use_hfclk() - switch the CORECLK mux to output HFCLK
+ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
+ *
+ * Switch the CORECLK mux to the HFCLK input source; return once complete.
+ *
+ * Context: Any context. Caller must prevent concurrent changes to the
+ * PRCI_CORECLKSEL_OFFSET register.
+ */
+void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd)
+{
+ u32 r;
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
+ r |= PRCI_CORECLKSEL_CORECLKSEL_MASK;
+ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
+}
+
+/**
+ * sifive_prci_coreclksel_use_corepll() - switch the CORECLK mux to output COREPLL
+ * @pd: struct __prci_data * for the PRCI containing the CORECLK mux reg
+ *
+ * Switch the CORECLK mux to the PLL output clock; return once complete.
+ *
+ * Context: Any context. Caller must prevent concurrent changes to the
+ * PRCI_CORECLKSEL_OFFSET register.
+ */
+void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd)
+{
+ u32 r;
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET);
+ r &= ~PRCI_CORECLKSEL_CORECLKSEL_MASK;
+ __prci_writel(r, PRCI_CORECLKSEL_OFFSET, pd);
+
+ r = __prci_readl(pd, PRCI_CORECLKSEL_OFFSET); /* barrier */
+}
+
+static ulong sifive_prci_parent_rate(struct __prci_clock *pc, struct prci_clk_desc *data)
+{
+ ulong parent_rate;
+ ulong i;
+ struct __prci_clock *p;
+
+ if (strcmp(pc->parent_name, "corepll") == 0 ||
+ strcmp(pc->parent_name, "hfpclkpll") == 0) {
+ for (i = 0; i < data->num_clks; i++) {
+ if (strcmp(pc->parent_name, data->clks[i].name) == 0)
+ break;
+ }
+
+ if (i >= data->num_clks)
+ return -ENXIO;
+
+ p = &data->clks[i];
+ if (!p->pd || !p->ops->recalc_rate)
+ return -ENXIO;
+
+ return p->ops->recalc_rate(p, sifive_prci_parent_rate(p, data));
+ }
+
+ if (strcmp(pc->parent_name, "rtcclk") == 0)
+ parent_rate = clk_get_rate(&pc->pd->parent_rtcclk);
+ else
+ parent_rate = clk_get_rate(&pc->pd->parent_hfclk);
+
+ return parent_rate;
+}
+
+static ulong sifive_prci_get_rate(struct clk *clk)
+{
+ struct __prci_clock *pc;
+ struct prci_clk_desc *data =
+ (struct prci_clk_desc *)dev_get_driver_data(clk->dev);
+
+ if (data->num_clks <= clk->id)
+ return -ENXIO;
+
+ pc = &data->clks[clk->id];
+ if (!pc->pd || !pc->ops->recalc_rate)
+ return -ENXIO;
+
+ return pc->ops->recalc_rate(pc, sifive_prci_parent_rate(pc, data));
+}
+
+static ulong sifive_prci_set_rate(struct clk *clk, ulong rate)
+{
+ int err;
+ struct __prci_clock *pc;
+ struct prci_clk_desc *data =
+ (struct prci_clk_desc *)dev_get_driver_data(clk->dev);
+
+ if (data->num_clks <= clk->id)
+ return -ENXIO;
+
+ pc = &data->clks[clk->id];
+ if (!pc->pd || !pc->ops->set_rate)
+ return -ENXIO;
+
+ err = pc->ops->set_rate(pc, rate, sifive_prci_parent_rate(pc, data));
+ if (err)
+ return err;
+
+ return rate;
+}
+
+static int sifive_prci_enable(struct clk *clk)
+{
+ struct __prci_clock *pc;
+ int ret = 0;
+ struct prci_clk_desc *data =
+ (struct prci_clk_desc *)dev_get_driver_data(clk->dev);
+
+ if (data->num_clks <= clk->id)
+ return -ENXIO;
+
+ pc = &data->clks[clk->id];
+ if (!pc->pd)
+ return -ENXIO;
+
+ if (pc->ops->enable_clk)
+ ret = pc->ops->enable_clk(pc, 1);
+
+ return ret;
+}
+
+static int sifive_prci_disable(struct clk *clk)
+{
+ struct __prci_clock *pc;
+ int ret = 0;
+ struct prci_clk_desc *data =
+ (struct prci_clk_desc *)dev_get_driver_data(clk->dev);
+
+ if (data->num_clks <= clk->id)
+ return -ENXIO;
+
+ pc = &data->clks[clk->id];
+ if (!pc->pd)
+ return -ENXIO;
+
+ if (pc->ops->enable_clk)
+ ret = pc->ops->enable_clk(pc, 0);
+
+ return ret;
+}
+
+static int sifive_prci_probe(struct udevice *dev)
+{
+ int i, err;
+ struct __prci_clock *pc;
+ struct __prci_data *pd = dev_get_priv(dev);
+
+ struct prci_clk_desc *data =
+ (struct prci_clk_desc *)dev_get_driver_data(dev);
+
+ pd->va = (void *)dev_read_addr(dev);
+ if (IS_ERR(pd->va))
+ return PTR_ERR(pd->va);
+
+ err = clk_get_by_index(dev, 0, &pd->parent_hfclk);
+ if (err)
+ return err;
+
+ err = clk_get_by_index(dev, 1, &pd->parent_rtcclk);
+ if (err)
+ return err;
+
+ for (i = 0; i < data->num_clks; ++i) {
+ pc = &data->clks[i];
+ pc->pd = pd;
+ if (pc->pwd)
+ __prci_wrpll_read_cfg0(pd, pc->pwd);
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_BUILD)) {
+ if (device_is_compatible(dev, "sifive,fu740-c000-prci")) {
+ u32 prci_pll_reg;
+ unsigned long parent_rate;
+
+ prci_pll_reg = readl(pd->va + PRCI_PRCIPLL_OFFSET);
+
+ if (prci_pll_reg & PRCI_PRCIPLL_HFPCLKPLL) {
+ /*
+ * Only initialize the HFPCLK PLL. In this
+ * case the design uses hfpclk to drive
+ * Chiplink
+ */
+ pc = &data->clks[PRCI_CLK_HFPCLKPLL];
+ parent_rate = sifive_prci_parent_rate(pc, data);
+ sifive_prci_wrpll_set_rate(pc, 260000000,
+ parent_rate);
+ pc->ops->enable_clk(pc, 1);
+ } else if (prci_pll_reg & PRCI_PRCIPLL_CLTXPLL) {
+ /* CLTX pll init */
+ pc = &data->clks[PRCI_CLK_CLTXPLL];
+ parent_rate = sifive_prci_parent_rate(pc, data);
+ sifive_prci_wrpll_set_rate(pc, 260000000,
+ parent_rate);
+ pc->ops->enable_clk(pc, 1);
+ }
+ }
+ }
+
+ return 0;
+}
+
+static struct clk_ops sifive_prci_ops = {
+ .set_rate = sifive_prci_set_rate,
+ .get_rate = sifive_prci_get_rate,
+ .enable = sifive_prci_enable,
+ .disable = sifive_prci_disable,
+};
+
+static int sifive_clk_bind(struct udevice *dev)
+{
+ return sifive_reset_bind(dev, PRCI_DEVICERESETCNT);
+}
+
+static const struct udevice_id sifive_prci_ids[] = {
+ { .compatible = "sifive,fu540-c000-prci", .data = (ulong)&prci_clk_fu540 },
+ { .compatible = "sifive,fu740-c000-prci", .data = (ulong)&prci_clk_fu740 },
+ { }
+};
+
+U_BOOT_DRIVER(sifive_prci) = {
+ .name = "sifive-prci",
+ .id = UCLASS_CLK,
+ .of_match = sifive_prci_ids,
+ .probe = sifive_prci_probe,
+ .ops = &sifive_prci_ops,
+ .priv_auto = sizeof(struct __prci_data),
+ .bind = sifive_clk_bind,
+};
diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
new file mode 100644
index 0000000..5ce33d6
--- /dev/null
+++ b/drivers/clk/sifive/sifive-prci.h
@@ -0,0 +1,323 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ * Zong Li
+ * Pragnesh Patel
+ */
+
+#ifndef __SIFIVE_CLK_SIFIVE_PRCI_H
+#define __SIFIVE_CLK_SIFIVE_PRCI_H
+
+#include <clk.h>
+#include <linux/clk/analogbits-wrpll-cln28hpc.h>
+
+/*
+ * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects:
+ * hfclk and rtcclk
+ */
+#define EXPECTED_CLK_PARENT_COUNT 2
+
+/*
+ * Register offsets and bitmasks
+ */
+
+/* COREPLLCFG0 */
+#define PRCI_COREPLLCFG0_OFFSET 0x4
+#define PRCI_COREPLLCFG0_DIVR_SHIFT 0
+#define PRCI_COREPLLCFG0_DIVR_MASK (0x3f << PRCI_COREPLLCFG0_DIVR_SHIFT)
+#define PRCI_COREPLLCFG0_DIVF_SHIFT 6
+#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT)
+#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15
+#define PRCI_COREPLLCFG0_DIVQ_MASK (0x7 << PRCI_COREPLLCFG0_DIVQ_SHIFT)
+#define PRCI_COREPLLCFG0_RANGE_SHIFT 18
+#define PRCI_COREPLLCFG0_RANGE_MASK (0x7 << PRCI_COREPLLCFG0_RANGE_SHIFT)
+#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24
+#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT)
+#define PRCI_COREPLLCFG0_FSE_SHIFT 25
+#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT)
+#define PRCI_COREPLLCFG0_LOCK_SHIFT 31
+#define PRCI_COREPLLCFG0_LOCK_MASK (0x1 << PRCI_COREPLLCFG0_LOCK_SHIFT)
+
+/* COREPLLCFG1 */
+#define PRCI_COREPLLCFG1_OFFSET 0x8
+#define PRCI_COREPLLCFG1_CKE_SHIFT 31
+#define PRCI_COREPLLCFG1_CKE_MASK (0x1 << PRCI_COREPLLCFG1_CKE_SHIFT)
+
+/* DDRPLLCFG0 */
+#define PRCI_DDRPLLCFG0_OFFSET 0xc
+#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0
+#define PRCI_DDRPLLCFG0_DIVR_MASK (0x3f << PRCI_DDRPLLCFG0_DIVR_SHIFT)
+#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6
+#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT)
+#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15
+#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x7 << PRCI_DDRPLLCFG0_DIVQ_SHIFT)
+#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18
+#define PRCI_DDRPLLCFG0_RANGE_MASK (0x7 << PRCI_DDRPLLCFG0_RANGE_SHIFT)
+#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24
+#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT)
+#define PRCI_DDRPLLCFG0_FSE_SHIFT 25
+#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT)
+#define PRCI_DDRPLLCFG0_LOCK_SHIFT 31
+#define PRCI_DDRPLLCFG0_LOCK_MASK (0x1 << PRCI_DDRPLLCFG0_LOCK_SHIFT)
+
+/* DDRPLLCFG1 */
+#define PRCI_DDRPLLCFG1_OFFSET 0x10
+#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
+#define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
+
+/* PCIEAUXCFG1 */
+#define PRCI_PCIEAUXCFG1_OFFSET 0x14
+#define PRCI_PCIEAUXCFG1_SHIFT 0
+#define PRCI_PCIEAUXCFG1_MASK (0x1 << PRCI_PCIEAUXCFG1_SHIFT)
+
+/* GEMGXLPLLCFG0 */
+#define PRCI_GEMGXLPLLCFG0_OFFSET 0x1c
+#define PRCI_GEMGXLPLLCFG0_DIVR_SHIFT 0
+#define PRCI_GEMGXLPLLCFG0_DIVR_MASK \
+ (0x3f << PRCI_GEMGXLPLLCFG0_DIVR_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_DIVF_SHIFT 6
+#define PRCI_GEMGXLPLLCFG0_DIVF_MASK \
+ (0x1ff << PRCI_GEMGXLPLLCFG0_DIVF_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT 15
+#define PRCI_GEMGXLPLLCFG0_DIVQ_MASK (0x7 << PRCI_GEMGXLPLLCFG0_DIVQ_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_RANGE_SHIFT 18
+#define PRCI_GEMGXLPLLCFG0_RANGE_MASK \
+ (0x7 << PRCI_GEMGXLPLLCFG0_RANGE_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT 24
+#define PRCI_GEMGXLPLLCFG0_BYPASS_MASK \
+ (0x1 << PRCI_GEMGXLPLLCFG0_BYPASS_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_FSE_SHIFT 25
+#define PRCI_GEMGXLPLLCFG0_FSE_MASK \
+ (0x1 << PRCI_GEMGXLPLLCFG0_FSE_SHIFT)
+#define PRCI_GEMGXLPLLCFG0_LOCK_SHIFT 31
+#define PRCI_GEMGXLPLLCFG0_LOCK_MASK (0x1 << PRCI_GEMGXLPLLCFG0_LOCK_SHIFT)
+
+/* GEMGXLPLLCFG1 */
+#define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
+#define PRCI_GEMGXLPLLCFG1_CKE_SHIFT 31
+#define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
+
+/* CORECLKSEL */
+#define PRCI_CORECLKSEL_OFFSET 0x24
+#define PRCI_CORECLKSEL_CORECLKSEL_SHIFT 0
+#define PRCI_CORECLKSEL_CORECLKSEL_MASK \
+ (0x1 << PRCI_CORECLKSEL_CORECLKSEL_SHIFT)
+
+/* DEVICESRESETREG */
+#define PRCI_DEVICESRESETREG_OFFSET 0x28
+#define PRCI_DEVICERESETCNT 6
+
+/* CLKMUXSTATUSREG */
+#define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
+#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT 1
+#define PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_MASK \
+ (0x1 << PRCI_CLKMUXSTATUSREG_TLCLKSEL_STATUS_SHIFT)
+
+/* CLTXPLLCFG0 */
+#define PRCI_CLTXPLLCFG0_OFFSET 0x30
+#define PRCI_CLTXPLLCFG0_DIVR_SHIFT 0
+#define PRCI_CLTXPLLCFG0_DIVR_MASK (0x3f << PRCI_CLTXPLLCFG0_DIVR_SHIFT)
+#define PRCI_CLTXPLLCFG0_DIVF_SHIFT 6
+#define PRCI_CLTXPLLCFG0_DIVF_MASK (0x1ff << PRCI_CLTXPLLCFG0_DIVF_SHIFT)
+#define PRCI_CLTXPLLCFG0_DIVQ_SHIFT 15
+#define PRCI_CLTXPLLCFG0_DIVQ_MASK (0x7 << PRCI_CLTXPLLCFG0_DIVQ_SHIFT)
+#define PRCI_CLTXPLLCFG0_RANGE_SHIFT 18
+#define PRCI_CLTXPLLCFG0_RANGE_MASK (0x7 << PRCI_CLTXPLLCFG0_RANGE_SHIFT)
+#define PRCI_CLTXPLLCFG0_BYPASS_SHIFT 24
+#define PRCI_CLTXPLLCFG0_BYPASS_MASK (0x1 << PRCI_CLTXPLLCFG0_BYPASS_SHIFT)
+#define PRCI_CLTXPLLCFG0_FSE_SHIFT 25
+#define PRCI_CLTXPLLCFG0_FSE_MASK (0x1 << PRCI_CLTXPLLCFG0_FSE_SHIFT)
+#define PRCI_CLTXPLLCFG0_LOCK_SHIFT 31
+#define PRCI_CLTXPLLCFG0_LOCK_MASK (0x1 << PRCI_CLTXPLLCFG0_LOCK_SHIFT)
+
+/* CLTXPLLCFG1 */
+#define PRCI_CLTXPLLCFG1_OFFSET 0x34
+#define PRCI_CLTXPLLCFG1_CKE_SHIFT 24
+#define PRCI_CLTXPLLCFG1_CKE_MASK (0x1 << PRCI_CLTXPLLCFG1_CKE_SHIFT)
+
+/* DVFSCOREPLLCFG0 */
+#define PRCI_DVFSCOREPLLCFG0_OFFSET 0x38
+
+/* DVFSCOREPLLCFG1 */
+#define PRCI_DVFSCOREPLLCFG1_OFFSET 0x3c
+#define PRCI_DVFSCOREPLLCFG1_CKE_SHIFT 24
+#define PRCI_DVFSCOREPLLCFG1_CKE_MASK (0x1 << PRCI_DVFSCOREPLLCFG1_CKE_SHIFT)
+
+/* COREPLLSEL */
+#define PRCI_COREPLLSEL_OFFSET 0x40
+#define PRCI_COREPLLSEL_COREPLLSEL_SHIFT 0
+#define PRCI_COREPLLSEL_COREPLLSEL_MASK \
+ (0x1 << PRCI_COREPLLSEL_COREPLLSEL_SHIFT)
+
+/* HFPCLKPLLCFG0 */
+#define PRCI_HFPCLKPLLCFG0_OFFSET 0x50
+#define PRCI_HFPCLKPLL_CFG0_DIVR_SHIFT 0
+#define PRCI_HFPCLKPLL_CFG0_DIVR_MASK \
+ (0x3f << PRCI_HFPCLKPLLCFG0_DIVR_SHIFT)
+#define PRCI_HFPCLKPLL_CFG0_DIVF_SHIFT 6
+#define PRCI_HFPCLKPLL_CFG0_DIVF_MASK \
+ (0x1ff << PRCI_HFPCLKPLLCFG0_DIVF_SHIFT)
+#define PRCI_HFPCLKPLL_CFG0_DIVQ_SHIFT 15
+#define PRCI_HFPCLKPLL_CFG0_DIVQ_MASK \
+ (0x7 << PRCI_HFPCLKPLLCFG0_DIVQ_SHIFT)
+#define PRCI_HFPCLKPLL_CFG0_RANGE_SHIFT 18
+#define PRCI_HFPCLKPLL_CFG0_RANGE_MASK \
+ (0x7 << PRCI_HFPCLKPLLCFG0_RANGE_SHIFT)
+#define PRCI_HFPCLKPLL_CFG0_BYPASS_SHIFT 24
+#define PRCI_HFPCLKPLL_CFG0_BYPASS_MASK \
+ (0x1 << PRCI_HFPCLKPLLCFG0_BYPASS_SHIFT)
+#define PRCI_HFPCLKPLL_CFG0_FSE_SHIFT 25
+#define PRCI_HFPCLKPLL_CFG0_FSE_MASK \
+ (0x1 << PRCI_HFPCLKPLLCFG0_FSE_SHIFT)
+#define PRCI_HFPCLKPLL_CFG0_LOCK_SHIFT 31
+#define PRCI_HFPCLKPLL_CFG0_LOCK_MASK \
+ (0x1 << PRCI_HFPCLKPLLCFG0_LOCK_SHIFT)
+
+/* HFPCLKPLLCFG1 */
+#define PRCI_HFPCLKPLLCFG1_OFFSET 0x54
+#define PRCI_HFPCLKPLLCFG1_CKE_SHIFT 24
+#define PRCI_HFPCLKPLLCFG1_CKE_MASK \
+ (0x1 << PRCI_HFPCLKPLLCFG1_CKE_SHIFT)
+
+/* HFPCLKPLLSEL */
+#define PRCI_HFPCLKPLLSEL_OFFSET 0x58
+#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT 0
+#define PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_MASK \
+ (0x1 << PRCI_HFPCLKPLLSEL_HFPCLKPLLSEL_SHIFT)
+
+/* HFPCLKPLLDIV */
+#define PRCI_HFPCLKPLLDIV_OFFSET 0x5c
+
+/* PRCIPLL */
+#define PRCI_PRCIPLL_OFFSET 0xe0
+
+#define PRCI_PRCIPLL_CLTXPLL (0x1 << 0)
+#define PRCI_PRCIPLL_GEMGXLPLL (0x1 << 1)
+#define PRCI_PRCIPLL_DDRPLL (0x1 << 2)
+#define PRCI_PRCIPLL_HFPCLKPLL (0x1 << 3)
+#define PRCI_PRCIPLL_DVFSCOREPLL (0x1 << 4)
+#define PRCI_PRCIPLL_COREPLL (0x1 << 5)
+
+/* PROCMONCFG */
+#define PRCI_PROCMONCFG_OFFSET 0xF0
+#define PRCI_PROCMONCFG_CORE_CLOCK_SHIFT 24
+#define PRCI_PROCMONCFG_CORE_CLOCK_MASK \
+ (0x1 << PRCI_PROCMONCFG_CORE_CLOCK_SHIFT)
+
+/*
+ * Private structures
+ */
+
+/**
+ * struct __prci_data - per-device-instance data
+ * @va: base virtual address of the PRCI IP block
+ * @parent: parent clk instance
+ *
+ * PRCI per-device instance data
+ */
+struct __prci_data {
+ void *va;
+ struct clk parent_hfclk;
+ struct clk parent_rtcclk;
+};
+
+/**
+ * struct __prci_wrpll_data - WRPLL configuration and integration data
+ * @c: WRPLL current configuration record
+ * @enable_bypass: fn ptr to code to bypass the WRPLL (if applicable; else NULL)
+ * @disable_bypass: fn ptr to code to not bypass the WRPLL (or NULL)
+ * @cfg0_offs: WRPLL CFG0 register offset (in bytes) from the PRCI base address
+ * @cfg1_offs: WRPLL CFG1 register offset (in bytes) from the PRCI base address
+ * @release_reset: fn ptr to code to release clock reset
+ *
+ * @enable_bypass and @disable_bypass are used for WRPLL instances
+ * that contain a separate external glitchless clock mux downstream
+ * from the PLL. The WRPLL internal bypass mux is not glitchless.
+ */
+struct __prci_wrpll_data {
+ struct wrpll_cfg c;
+ void (*enable_bypass)(struct __prci_data *pd);
+ void (*disable_bypass)(struct __prci_data *pd);
+ u8 cfg0_offs;
+ u8 cfg1_offs;
+ void (*release_reset)(struct __prci_data *pd);
+};
+
+/**
+ * struct __prci_clock - describes a clock device managed by PRCI
+ * @name: user-readable clock name string - should match the manual
+ * @parent_name: parent name for this clock
+ * @ops: struct __prci_clock_ops for control
+ * @pwd: WRPLL-specific data, associated with this clock (if not NULL)
+ * @pd: PRCI-specific data associated with this clock (if not NULL)
+ *
+ * PRCI clock data. Used by the PRCI driver to register PRCI-provided
+ * clocks to the Linux clock infrastructure.
+ */
+struct __prci_clock {
+ const char *name;
+ const char *parent_name;
+ const struct __prci_clock_ops *ops;
+ struct __prci_wrpll_data *pwd;
+ struct __prci_data *pd;
+};
+
+/* struct __prci_clock_ops - clock operations */
+struct __prci_clock_ops {
+ int (*set_rate)(struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long parent_rate);
+ unsigned long (*round_rate)(struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long *parent_rate);
+ unsigned long (*recalc_rate)(struct __prci_clock *pc,
+ unsigned long parent_rate);
+ int (*enable_clk)(struct __prci_clock *pc, bool enable);
+};
+
+/*
+ * struct prci_clk_desc - describes the information of clocks of each SoCs
+ * @clks: point to a array of __prci_clock
+ * @num_clks: the number of element of clks
+ */
+struct prci_clk_desc {
+ struct __prci_clock *clks;
+ size_t num_clks;
+};
+
+void sifive_prci_ethernet_release_reset(struct __prci_data *pd);
+void sifive_prci_ddr_release_reset(struct __prci_data *pd);
+void sifive_prci_cltx_release_reset(struct __prci_data *pd);
+
+/* Core clock mux control */
+void sifive_prci_coreclksel_use_hfclk(struct __prci_data *pd);
+void sifive_prci_coreclksel_use_corepll(struct __prci_data *pd);
+void sifive_prci_coreclksel_use_final_corepll(struct __prci_data *pd);
+void sifive_prci_corepllsel_use_dvfscorepll(struct __prci_data *pd);
+void sifive_prci_corepllsel_use_corepll(struct __prci_data *pd);
+void sifive_prci_hfpclkpllsel_use_hfclk(struct __prci_data *pd);
+void sifive_prci_hfpclkpllsel_use_hfpclkpll(struct __prci_data *pd);
+
+unsigned long sifive_prci_wrpll_round_rate(struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long *parent_rate);
+
+/* Linux clock framework integration */
+int sifive_prci_wrpll_set_rate(struct __prci_clock *pc,
+ unsigned long rate,
+ unsigned long parent_rate);
+
+unsigned long sifive_prci_wrpll_recalc_rate(struct __prci_clock *pc,
+ unsigned long parent_rate);
+
+unsigned long sifive_prci_tlclksel_recalc_rate(struct __prci_clock *pc,
+ unsigned long parent_rate);
+
+unsigned long sifive_prci_hfpclkplldiv_recalc_rate(struct __prci_clock *pc,
+ unsigned long parent_rate);
+
+int sifive_prci_clock_enable(struct __prci_clock *pc, bool enable);
+
+#endif /* __SIFIVE_CLK_SIFIVE_PRCI_H */
diff --git a/drivers/clk/ti/Kconfig b/drivers/clk/ti/Kconfig
index 2dc86d4..fbcdefd 100644
--- a/drivers/clk/ti/Kconfig
+++ b/drivers/clk/ti/Kconfig
@@ -41,3 +41,27 @@
This enables the clock driver support over TI System Control Interface
available on some new TI's SoCs. If you wish to use clock resources
managed by the TI System Controller, say Y here. Otherwise, say N.
+
+config CLK_K3_PLL
+ bool "PLL clock support for K3 SoC family of devices"
+ depends on CLK && LIB_RATIONAL
+ help
+ Enables PLL clock support for K3 SoC family of devices.
+
+config SPL_CLK_K3_PLL
+ bool "PLL clock support for K3 SoC family of devices"
+ depends on CLK && LIB_RATIONAL && SPL
+ help
+ Enables PLL clock support for K3 SoC family of devices.
+
+config CLK_K3
+ bool "Clock support for K3 SoC family of devices"
+ depends on CLK
+ help
+ Enables the clock translation layer from DT to device clocks.
+
+config SPL_CLK_K3
+ bool "Clock support for K3 SoC family of devices"
+ depends on CLK && SPL
+ help
+ Enables the clock translation layer from DT to device clocks.
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index 9f56b47..07aa9a5 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -11,3 +11,5 @@
obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
+obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk-k3.o
diff --git a/drivers/clk/ti/clk-am3-dpll.c b/drivers/clk/ti/clk-am3-dpll.c
index 90b4cc6..916d308 100644
--- a/drivers/clk/ti/clk-am3-dpll.c
+++ b/drivers/clk/ti/clk-am3-dpll.c
@@ -17,15 +17,16 @@
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include "clk.h"
struct clk_ti_am3_dpll_drv_data {
ulong max_rate;
};
struct clk_ti_am3_dpll_priv {
- fdt_addr_t clkmode_reg;
- fdt_addr_t idlest_reg;
- fdt_addr_t clksel_reg;
+ struct clk_ti_reg clkmode_reg;
+ struct clk_ti_reg idlest_reg;
+ struct clk_ti_reg clksel_reg;
struct clk clk_bypass;
struct clk clk_ref;
u16 last_rounded_mult;
@@ -75,6 +76,37 @@
return ret;
}
+static void clk_ti_am3_dpll_clken(struct clk_ti_am3_dpll_priv *priv,
+ u8 clken_bits)
+{
+ u32 v;
+
+ v = clk_ti_readl(&priv->clkmode_reg);
+ v &= ~CM_CLKMODE_DPLL_DPLL_EN_MASK;
+ v |= clken_bits << CM_CLKMODE_DPLL_EN_SHIFT;
+ clk_ti_writel(v, &priv->clkmode_reg);
+}
+
+static int clk_ti_am3_dpll_state(struct clk *clk, u8 state)
+{
+ struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
+ u32 i = 0, v;
+
+ do {
+ v = clk_ti_readl(&priv->idlest_reg) & ST_DPLL_CLK_MASK;
+ if (v == state) {
+ dev_dbg(clk->dev, "transition to '%s' in %d loops\n",
+ state ? "locked" : "bypassed", i);
+ return 1;
+ }
+
+ } while (++i < LDELAY);
+
+ dev_err(clk->dev, "failed transition to '%s'\n",
+ state ? "locked" : "bypassed");
+ return 0;
+}
+
static ulong clk_ti_am3_dpll_set_rate(struct clk *clk, ulong rate)
{
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(clk->dev);
@@ -85,16 +117,13 @@
if (IS_ERR_VALUE(round_rate))
return round_rate;
- v = readl(priv->clksel_reg);
+ v = clk_ti_readl(&priv->clksel_reg);
/* enter bypass mode */
- clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
+ clk_ti_am3_dpll_clken(priv, DPLL_EN_MN_BYPASS);
/* wait for bypass mode */
- if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
- (void *)priv->idlest_reg, LDELAY))
- dev_err(clk->dev, "failed bypassing dpll\n");
+ clk_ti_am3_dpll_state(clk, 0);
/* set M & N */
v &= ~CM_CLKSEL_DPLL_M_MASK;
@@ -105,18 +134,14 @@
v |= ((priv->last_rounded_div - 1) << CM_CLKSEL_DPLL_N_SHIFT) &
CM_CLKSEL_DPLL_N_MASK;
- writel(v, priv->clksel_reg);
+ clk_ti_writel(v, &priv->clksel_reg);
/* lock dpll */
- clrsetbits_le32(priv->clkmode_reg, CM_CLKMODE_DPLL_DPLL_EN_MASK,
- DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
+ clk_ti_am3_dpll_clken(priv, DPLL_EN_LOCK);
/* wait till the dpll locks */
- if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
- (void *)priv->idlest_reg, LDELAY)) {
- dev_err(clk->dev, "failed locking dpll\n");
+ if (!clk_ti_am3_dpll_state(clk, ST_DPLL_CLK_MASK))
hang();
- }
return round_rate;
}
@@ -128,7 +153,7 @@
u32 m, n, v;
/* Return bypass rate if DPLL is bypassed */
- v = readl(priv->clkmode_reg);
+ v = clk_ti_readl(&priv->clkmode_reg);
v &= CM_CLKMODE_DPLL_EN_MASK;
v >>= CM_CLKMODE_DPLL_EN_SHIFT;
@@ -141,7 +166,7 @@
return rate;
}
- v = readl(priv->clksel_reg);
+ v = clk_ti_readl(&priv->clksel_reg);
m = v & CM_CLKSEL_DPLL_M_MASK;
m >>= CM_CLKSEL_DPLL_M_SHIFT;
n = v & CM_CLKSEL_DPLL_N_MASK;
@@ -204,33 +229,28 @@
struct clk_ti_am3_dpll_priv *priv = dev_get_priv(dev);
struct clk_ti_am3_dpll_drv_data *data =
(struct clk_ti_am3_dpll_drv_data *)dev_get_driver_data(dev);
+ int err;
priv->max_rate = data->max_rate;
- priv->clkmode_reg = dev_read_addr_index(dev, 0);
- if (priv->clkmode_reg == FDT_ADDR_T_NONE) {
- dev_err(dev, "failed to get clkmode register\n");
- return -EINVAL;
+ err = clk_ti_get_reg_addr(dev, 0, &priv->clkmode_reg);
+ if (err) {
+ dev_err(dev, "failed to get clkmode register address\n");
+ return err;
}
- dev_dbg(dev, "clkmode_reg=0x%08lx\n", priv->clkmode_reg);
-
- priv->idlest_reg = dev_read_addr_index(dev, 1);
- if (priv->idlest_reg == FDT_ADDR_T_NONE) {
+ err = clk_ti_get_reg_addr(dev, 1, &priv->idlest_reg);
+ if (err) {
dev_err(dev, "failed to get idlest register\n");
return -EINVAL;
}
- dev_dbg(dev, "idlest_reg=0x%08lx\n", priv->idlest_reg);
-
- priv->clksel_reg = dev_read_addr_index(dev, 2);
- if (priv->clksel_reg == FDT_ADDR_T_NONE) {
+ err = clk_ti_get_reg_addr(dev, 2, &priv->clksel_reg);
+ if (err) {
dev_err(dev, "failed to get clksel register\n");
- return -EINVAL;
+ return err;
}
- dev_dbg(dev, "clksel_reg=0x%08lx\n", priv->clksel_reg);
-
return 0;
}
diff --git a/drivers/clk/ti/clk-divider.c b/drivers/clk/ti/clk-divider.c
index 270f2fb..15941f1 100644
--- a/drivers/clk/ti/clk-divider.c
+++ b/drivers/clk/ti/clk-divider.c
@@ -27,7 +27,7 @@
struct clk_ti_divider_priv {
struct clk parent;
- fdt_addr_t reg;
+ struct clk_ti_reg reg;
const struct clk_div_table *table;
u8 shift;
u8 flags;
@@ -200,11 +200,11 @@
val = _get_val(priv->table, priv->div_flags, div);
- v = readl(priv->reg);
+ v = clk_ti_readl(&priv->reg);
v &= ~(priv->mask << priv->shift);
v |= val << priv->shift;
- writel(v, priv->reg);
- clk_ti_latch(priv->reg, priv->latch);
+ clk_ti_writel(v, &priv->reg);
+ clk_ti_latch(&priv->reg, priv->latch);
return clk_get_rate(clk);
}
@@ -220,7 +220,7 @@
if (IS_ERR_VALUE(parent_rate))
return parent_rate;
- v = readl(priv->reg) >> priv->shift;
+ v = clk_ti_readl(&priv->reg) >> priv->shift;
v &= priv->mask;
div = _get_div(priv->table, priv->div_flags, v);
@@ -287,10 +287,14 @@
u32 min_div = 0;
u32 max_val, max_div = 0;
u16 mask;
- int i, div_num;
+ int i, div_num, err;
+
+ err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
+ if (err) {
+ dev_err(dev, "failed to get register address\n");
+ return err;
+ }
- priv->reg = dev_read_addr(dev);
- dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
if (dev_read_bool(dev, "ti,index-starts-at-one"))
diff --git a/drivers/clk/ti/clk-gate.c b/drivers/clk/ti/clk-gate.c
index 0ca453c..eb15f62 100644
--- a/drivers/clk/ti/clk-gate.c
+++ b/drivers/clk/ti/clk-gate.c
@@ -13,9 +13,10 @@
#include <clk-uclass.h>
#include <asm/io.h>
#include <linux/clk-provider.h>
+#include "clk.h"
struct clk_ti_gate_priv {
- fdt_addr_t reg;
+ struct clk_ti_reg reg;
u8 enable_bit;
u32 flags;
bool invert_enable;
@@ -26,13 +27,13 @@
struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
u32 v;
- v = readl(priv->reg);
+ v = clk_ti_readl(&priv->reg);
if (priv->invert_enable)
v |= (1 << priv->enable_bit);
else
v &= ~(1 << priv->enable_bit);
- writel(v, priv->reg);
+ clk_ti_writel(v, &priv->reg);
/* No OCP barrier needed here since it is a disable operation */
return 0;
}
@@ -42,29 +43,29 @@
struct clk_ti_gate_priv *priv = dev_get_priv(clk->dev);
u32 v;
- v = readl(priv->reg);
+ v = clk_ti_readl(&priv->reg);
if (priv->invert_enable)
v &= ~(1 << priv->enable_bit);
else
v |= (1 << priv->enable_bit);
- writel(v, priv->reg);
+ clk_ti_writel(v, &priv->reg);
/* OCP barrier */
- v = readl(priv->reg);
+ v = clk_ti_readl(&priv->reg);
return 0;
}
static int clk_ti_gate_of_to_plat(struct udevice *dev)
{
struct clk_ti_gate_priv *priv = dev_get_priv(dev);
+ int err;
- priv->reg = dev_read_addr(dev);
- if (priv->reg == FDT_ADDR_T_NONE) {
- dev_err(dev, "failed to get control register\n");
- return -EINVAL;
+ err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
+ if (err) {
+ dev_err(dev, "failed to get control register address\n");
+ return err;
}
- dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
priv->enable_bit = dev_read_u32_default(dev, "ti,bit-shift", 0);
if (dev_read_bool(dev, "ti,set-rate-parent"))
priv->flags |= CLK_SET_RATE_PARENT;
diff --git a/drivers/clk/ti/clk-k3-pll.c b/drivers/clk/ti/clk-k3-pll.c
new file mode 100644
index 0000000..bf2407a
--- /dev/null
+++ b/drivers/clk/ti/clk-k3-pll.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 SoC PLL clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <div64.h>
+#include <errno.h>
+#include <clk-uclass.h>
+#include <linux/clk-provider.h>
+#include "k3-clk.h"
+#include <linux/rational.h>
+
+/* 16FFT register offsets */
+#define PLL_16FFT_CFG 0x08
+#define PLL_KICK0 0x10
+#define PLL_KICK1 0x14
+#define PLL_16FFT_CTRL 0x20
+#define PLL_16FFT_STAT 0x24
+#define PLL_16FFT_FREQ_CTRL0 0x30
+#define PLL_16FFT_FREQ_CTRL1 0x34
+#define PLL_16FFT_DIV_CTRL 0x38
+
+/* CTRL register bits */
+#define PLL_16FFT_CTRL_BYPASS_EN BIT(31)
+#define PLL_16FFT_CTRL_PLL_EN BIT(15)
+#define PLL_16FFT_CTRL_DSM_EN BIT(1)
+
+/* STAT register bits */
+#define PLL_16FFT_STAT_LOCK BIT(0)
+
+/* FREQ_CTRL0 bits */
+#define PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK 0xfff
+
+/* DIV CTRL register bits */
+#define PLL_16FFT_DIV_CTRL_REF_DIV_MASK 0x3f
+
+#define PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS 24
+#define PLL_16FFT_HSDIV_CTRL_CLKOUT_EN BIT(15)
+
+/* KICK register magic values */
+#define PLL_KICK0_VALUE 0x68ef3490
+#define PLL_KICK1_VALUE 0xd172bc5a
+
+/**
+ * struct ti_pll_clk - TI PLL clock data info structure
+ * @clk: core clock structure
+ * @reg: memory address of the PLL controller
+ */
+struct ti_pll_clk {
+ struct clk clk;
+ void __iomem *reg;
+};
+
+#define to_clk_pll(_clk) container_of(_clk, struct ti_pll_clk, clk)
+
+static int ti_pll_wait_for_lock(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u32 stat;
+ int i;
+
+ for (i = 0; i < 100000; i++) {
+ stat = readl(pll->reg + PLL_16FFT_STAT);
+ if (stat & PLL_16FFT_STAT_LOCK)
+ return 0;
+ }
+
+ printf("%s: pll (%s) failed to lock\n", __func__,
+ clk->dev->name);
+
+ return -EBUSY;
+}
+
+static ulong ti_pll_clk_get_rate(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u64 current_freq;
+ u64 parent_freq = clk_get_parent_rate(clk);
+ u32 pllm;
+ u32 plld;
+ u32 pllfm;
+ u32 ctrl;
+
+ /* Check if we are in bypass */
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ if (ctrl & PLL_16FFT_CTRL_BYPASS_EN)
+ return parent_freq;
+
+ pllm = readl(pll->reg + PLL_16FFT_FREQ_CTRL0);
+ pllfm = readl(pll->reg + PLL_16FFT_FREQ_CTRL1);
+
+ plld = readl(pll->reg + PLL_16FFT_DIV_CTRL) &
+ PLL_16FFT_DIV_CTRL_REF_DIV_MASK;
+
+ current_freq = parent_freq * pllm / plld;
+
+ if (pllfm) {
+ u64 tmp;
+
+ tmp = parent_freq * pllfm;
+ do_div(tmp, plld);
+ tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+ current_freq += tmp;
+ }
+
+ return current_freq;
+}
+
+static ulong ti_pll_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u64 current_freq;
+ u64 parent_freq = clk_get_parent_rate(clk);
+ int ret;
+ u32 ctrl;
+ unsigned long pllm;
+ u32 pllfm = 0;
+ unsigned long plld;
+ u32 rem;
+ int shift;
+
+ debug("%s(clk=%p, rate=%u)\n", __func__, clk, (u32)rate);
+
+ if (ti_pll_clk_get_rate(clk) == rate)
+ return rate;
+
+ if (rate != parent_freq)
+ /*
+ * Attempt with higher max multiplier value first to give
+ * some space for fractional divider to kick in.
+ */
+ for (shift = 8; shift >= 0; shift -= 8) {
+ rational_best_approximation(rate, parent_freq,
+ ((PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK + 1) << shift) - 1,
+ PLL_16FFT_DIV_CTRL_REF_DIV_MASK, &pllm, &plld);
+ if (pllm / plld <= PLL_16FFT_FREQ_CTRL0_FB_DIV_INT_MASK)
+ break;
+ }
+
+ /* Put PLL to bypass mode */
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ if (rate == parent_freq) {
+ debug("%s: put %s to bypass\n", __func__, clk->dev->name);
+ return rate;
+ }
+
+ debug("%s: pre-frac-calc: rate=%u, parent_freq=%u, plld=%u, pllm=%u\n",
+ __func__, (u32)rate, (u32)parent_freq, (u32)plld, (u32)pllm);
+
+ /* Check if we need fractional config */
+ if (plld > 1) {
+ pllfm = pllm % plld;
+ pllfm <<= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+ rem = pllfm % plld;
+ pllfm /= plld;
+ if (rem)
+ pllfm++;
+ pllm /= plld;
+ plld = 1;
+ }
+
+ if (pllfm)
+ ctrl |= PLL_16FFT_CTRL_DSM_EN;
+ else
+ ctrl &= ~PLL_16FFT_CTRL_DSM_EN;
+
+ writel(pllm, pll->reg + PLL_16FFT_FREQ_CTRL0);
+ writel(pllfm, pll->reg + PLL_16FFT_FREQ_CTRL1);
+ writel(plld, pll->reg + PLL_16FFT_DIV_CTRL);
+
+ ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+ ctrl |= PLL_16FFT_CTRL_PLL_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ ret = ti_pll_wait_for_lock(clk);
+ if (ret)
+ return ret;
+
+ debug("%s: pllm=%u, plld=%u, pllfm=%u, parent_freq=%u\n",
+ __func__, (u32)pllm, (u32)plld, (u32)pllfm, (u32)parent_freq);
+
+ current_freq = parent_freq * pllm / plld;
+
+ if (pllfm) {
+ u64 tmp;
+
+ tmp = parent_freq * pllfm;
+ do_div(tmp, plld);
+ tmp >>= PLL_16FFT_FREQ_CTRL1_FB_DIV_FRAC_BITS;
+ current_freq += tmp;
+ }
+
+ return current_freq;
+}
+
+static int ti_pll_clk_enable(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u32 ctrl;
+
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl &= ~PLL_16FFT_CTRL_BYPASS_EN;
+ ctrl |= PLL_16FFT_CTRL_PLL_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ return ti_pll_wait_for_lock(clk);
+}
+
+static int ti_pll_clk_disable(struct clk *clk)
+{
+ struct ti_pll_clk *pll = to_clk_pll(clk);
+ u32 ctrl;
+
+ ctrl = readl(pll->reg + PLL_16FFT_CTRL);
+ ctrl |= PLL_16FFT_CTRL_BYPASS_EN;
+ writel(ctrl, pll->reg + PLL_16FFT_CTRL);
+
+ return 0;
+}
+
+static const struct clk_ops ti_pll_clk_ops = {
+ .get_rate = ti_pll_clk_get_rate,
+ .set_rate = ti_pll_clk_set_rate,
+ .enable = ti_pll_clk_enable,
+ .disable = ti_pll_clk_disable,
+};
+
+struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
+ void __iomem *reg)
+{
+ struct ti_pll_clk *pll;
+ int ret;
+ int i;
+ u32 cfg, ctrl, hsdiv_presence_bit, hsdiv_ctrl_offs;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->reg = reg;
+
+ ret = clk_register(&pll->clk, "ti-pll-clk", name, parent_name);
+ if (ret) {
+ printf("%s: failed to register: %d\n", __func__, ret);
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ /* Unlock the PLL registers */
+ writel(PLL_KICK0_VALUE, pll->reg + PLL_KICK0);
+ writel(PLL_KICK1_VALUE, pll->reg + PLL_KICK1);
+
+ /* Enable all HSDIV outputs */
+ cfg = readl(pll->reg + PLL_16FFT_CFG);
+ for (i = 0; i < 16; i++) {
+ hsdiv_presence_bit = BIT(16 + i);
+ hsdiv_ctrl_offs = 0x80 + (i * 4);
+ /* Enable HSDIV output if present */
+ if ((hsdiv_presence_bit & cfg) != 0UL) {
+ ctrl = readl(pll->reg + hsdiv_ctrl_offs);
+ ctrl |= PLL_16FFT_HSDIV_CTRL_CLKOUT_EN;
+ writel(ctrl, pll->reg + hsdiv_ctrl_offs);
+ }
+ }
+
+ return &pll->clk;
+}
+
+U_BOOT_DRIVER(ti_pll_clk) = {
+ .name = "ti-pll-clk",
+ .id = UCLASS_CLK,
+ .ops = &ti_pll_clk_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/ti/clk-k3.c b/drivers/clk/ti/clk-k3.c
new file mode 100644
index 0000000..e921894
--- /dev/null
+++ b/drivers/clk/ti/clk-k3.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments K3 clock driver
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <soc.h>
+#include <clk-uclass.h>
+#include "k3-clk.h"
+
+#define PLL_MIN_FREQ 800000000
+#define PLL_MAX_FREQ 3200000000UL
+#define PLL_MAX_DIV 127
+
+/**
+ * struct clk_map - mapping from dev/clk id tuples towards physical clocks
+ * @dev_id: device ID for the clock
+ * @clk_id: clock ID for the clock
+ * @clk: pointer to the registered clock entry for the mapping
+ */
+struct clk_map {
+ u16 dev_id;
+ u32 clk_id;
+ struct clk *clk;
+};
+
+/**
+ * struct ti_clk_data - clock controller information structure
+ * @map: mapping from dev/clk id tuples to physical clock entries
+ * @size: number of entries in the map
+ */
+struct ti_clk_data {
+ struct clk_map *map;
+ int size;
+};
+
+static ulong osc_freq;
+
+static void clk_add_map(struct ti_clk_data *data, struct clk *clk,
+ u32 dev_id, u32 clk_id)
+{
+ struct clk_map *map;
+
+ debug("%s: added clk=%p, data=%p, dev=%d, clk=%d\n", __func__,
+ clk, data, dev_id, clk_id);
+ if (!clk)
+ return;
+
+ map = data->map + data->size++;
+
+ map->dev_id = dev_id;
+ map->clk_id = clk_id;
+ map->clk = clk;
+}
+
+static const struct soc_attr ti_k3_soc_clk_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+ {
+ .family = "J721E",
+ .data = &j721e_clk_platdata,
+ },
+ {
+ .family = "J7200",
+ .data = &j7200_clk_platdata,
+ },
+#endif
+ { /* sentinel */ }
+};
+
+static int ti_clk_probe(struct udevice *dev)
+{
+ struct ti_clk_data *data = dev_get_priv(dev);
+ struct clk *clk;
+ const char *name;
+ const struct clk_data *ti_clk_data;
+ int i, j;
+ const struct soc_attr *soc_match_data;
+ const struct ti_k3_clk_platdata *pdata;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ soc_match_data = soc_device_match(ti_k3_soc_clk_data);
+ if (!soc_match_data)
+ return -ENODEV;
+
+ pdata = (const struct ti_k3_clk_platdata *)soc_match_data->data;
+
+ data->map = kcalloc(pdata->soc_dev_clk_data_cnt, sizeof(*data->map),
+ GFP_KERNEL);
+ data->size = 0;
+
+ for (i = 0; i < pdata->clk_list_cnt; i++) {
+ ti_clk_data = &pdata->clk_list[i];
+
+ switch (ti_clk_data->type) {
+ case CLK_TYPE_FIXED_RATE:
+ name = ti_clk_data->clk.fixed_rate.name;
+ clk = clk_register_fixed_rate(NULL,
+ name,
+ ti_clk_data->clk.fixed_rate.rate);
+ break;
+ case CLK_TYPE_DIV:
+ name = ti_clk_data->clk.div.name;
+ clk = clk_register_divider(NULL, name,
+ ti_clk_data->clk.div.parent,
+ ti_clk_data->clk.div.flags,
+ map_physmem(ti_clk_data->clk.div.reg, 0, MAP_NOCACHE),
+ ti_clk_data->clk.div.shift,
+ ti_clk_data->clk.div.width,
+ 0);
+ break;
+ case CLK_TYPE_MUX:
+ name = ti_clk_data->clk.mux.name;
+ clk = clk_register_mux(NULL, name,
+ ti_clk_data->clk.mux.parents,
+ ti_clk_data->clk.mux.num_parents,
+ ti_clk_data->clk.mux.flags,
+ map_physmem(ti_clk_data->clk.mux.reg, 0, MAP_NOCACHE),
+ ti_clk_data->clk.mux.shift,
+ ti_clk_data->clk.mux.width,
+ 0);
+ break;
+ case CLK_TYPE_PLL:
+ name = ti_clk_data->clk.pll.name;
+ clk = clk_register_ti_pll(name,
+ ti_clk_data->clk.pll.parent,
+ map_physmem(ti_clk_data->clk.pll.reg, 0, MAP_NOCACHE));
+
+ if (!osc_freq)
+ osc_freq = clk_get_rate(clk_get_parent(clk));
+ break;
+ default:
+ name = NULL;
+ clk = NULL;
+ printf("WARNING: %s has encountered unknown clk type %d\n",
+ __func__, ti_clk_data->type);
+ }
+
+ if (clk && ti_clk_data->default_freq)
+ clk_set_rate(clk, ti_clk_data->default_freq);
+
+ if (clk && name) {
+ for (j = 0; j < pdata->soc_dev_clk_data_cnt; j++) {
+ if (!strcmp(name, pdata->soc_dev_clk_data[j].clk_name)) {
+ clk_add_map(data, clk, pdata->soc_dev_clk_data[j].dev_id,
+ pdata->soc_dev_clk_data[j].clk_id);
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int _clk_cmp(u32 dev_id, u32 clk_id, const struct clk_map *map)
+{
+ if (map->dev_id == dev_id && map->clk_id == clk_id)
+ return 0;
+ if (map->dev_id > dev_id ||
+ (map->dev_id == dev_id && map->clk_id > clk_id))
+ return -1;
+ return 1;
+}
+
+static int bsearch(u32 dev_id, u32 clk_id, struct clk_map *map, int num)
+{
+ int result;
+ int idx;
+
+ for (idx = 0; idx < num; idx++) {
+ result = _clk_cmp(dev_id, clk_id, &map[idx]);
+
+ if (result == 0)
+ return idx;
+ }
+
+ return -ENOENT;
+}
+
+static int ti_clk_of_xlate(struct clk *clk,
+ struct ofnode_phandle_args *args)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ int idx;
+
+ debug("%s(clk=%p, args_count=%d [0]=%d [1]=%d)\n", __func__, clk,
+ args->args_count, args->args[0], args->args[1]);
+
+ if (args->args_count != 2) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ if (!data->size)
+ return -EPROBE_DEFER;
+
+ idx = bsearch(args->args[0], args->args[1], data->map, data->size);
+ if (idx < 0)
+ return idx;
+
+ clk->id = idx;
+
+ return 0;
+}
+
+static ulong ti_clk_get_rate(struct clk *clk)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+
+ return clk_get_rate(clkp);
+}
+
+static ulong ti_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+ int div = 1;
+ ulong child_rate;
+ const struct clk_ops *ops;
+ ulong new_rate, rem;
+ ulong diff, new_diff;
+
+ /*
+ * We must propagate rate change to parent if current clock type
+ * does not allow setting it.
+ */
+ while (clkp) {
+ ops = clkp->dev->driver->ops;
+ if (ops->set_rate)
+ break;
+
+ /*
+ * Store child rate so we can calculate the clock rate
+ * that must be passed to parent
+ */
+ child_rate = clk_get_rate(clkp);
+ clkp = clk_get_parent(clkp);
+ if (clkp) {
+ debug("%s: propagating rate change to parent %s, rate=%u.\n",
+ __func__, clkp->dev->name, (u32)rate / div);
+ div *= clk_get_rate(clkp) / child_rate;
+ }
+ }
+
+ if (!clkp)
+ return -ENOSYS;
+
+ child_rate = clk_get_rate(clkp);
+
+ new_rate = clk_set_rate(clkp, rate / div);
+
+ diff = abs(new_rate - rate / div);
+
+ debug("%s: clk=%s, div=%d, rate=%u, new_rate=%u, diff=%u\n", __func__,
+ clkp->dev->name, div, (u32)rate, (u32)new_rate, (u32)diff);
+
+ /*
+ * If the new rate differs by 50% of the target,
+ * modify parent. This handles typical cases where we have a hsdiv
+ * following directly a PLL
+ */
+
+ if (diff > rate / div / 2) {
+ ulong pll_tgt;
+ int pll_div = 0;
+
+ clk = clkp;
+
+ debug("%s: propagating rate change to parent, rate=%u.\n",
+ __func__, (u32)rate / div);
+
+ clkp = clk_get_parent(clkp);
+
+ if (rate > osc_freq) {
+ if (rate > PLL_MAX_FREQ / 2 && rate < PLL_MAX_FREQ) {
+ pll_tgt = rate;
+ pll_div = 1;
+ } else {
+ for (pll_div = 2; pll_div < PLL_MAX_DIV; pll_div++) {
+ pll_tgt = rate / div * pll_div;
+ if (pll_tgt >= PLL_MIN_FREQ && pll_tgt <= PLL_MAX_FREQ)
+ break;
+ }
+ }
+ } else {
+ pll_tgt = osc_freq;
+ pll_div = rate / div / osc_freq;
+ }
+
+ debug("%s: pll_tgt=%u, rate=%u, div=%u\n", __func__,
+ (u32)pll_tgt, (u32)rate, pll_div);
+
+ clk_set_rate(clkp, pll_tgt);
+
+ return clk_set_rate(clk, rate / div) * div;
+ }
+
+ /*
+ * If the new rate differs by at least 5% of the target,
+ * we must check for rounding error in a divider, so try
+ * set rate with rate + (parent_freq % rate).
+ */
+
+ if (diff > rate / div / 20) {
+ u64 parent_freq = clk_get_parent_rate(clkp);
+
+ rem = parent_freq % rate;
+ new_rate = clk_set_rate(clkp, (rate / div) + rem);
+ new_diff = abs(new_rate - rate / div);
+
+ if (new_diff > diff) {
+ new_rate = clk_set_rate(clkp, rate / div);
+ } else {
+ debug("%s: Using better rate %lu that gives diff %lu\n",
+ __func__, new_rate, new_diff);
+ }
+ }
+
+ return new_rate;
+}
+
+static int ti_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+ struct clk *parentp = data->map[parent->id].clk;
+
+ return clk_set_parent(clkp, parentp);
+}
+
+static int ti_clk_enable(struct clk *clk)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+
+ return clk_enable(clkp);
+}
+
+static int ti_clk_disable(struct clk *clk)
+{
+ struct ti_clk_data *data = dev_get_priv(clk->dev);
+ struct clk *clkp = data->map[clk->id].clk;
+
+ return clk_disable(clkp);
+}
+
+static const struct udevice_id ti_clk_of_match[] = {
+ { .compatible = "ti,k2g-sci-clk" },
+ { /* sentinel */ },
+};
+
+static const struct clk_ops ti_clk_ops = {
+ .of_xlate = ti_clk_of_xlate,
+ .set_rate = ti_clk_set_rate,
+ .get_rate = ti_clk_get_rate,
+ .enable = ti_clk_enable,
+ .disable = ti_clk_disable,
+ .set_parent = ti_clk_set_parent,
+};
+
+U_BOOT_DRIVER(ti_clk) = {
+ .name = "ti-clk",
+ .id = UCLASS_CLK,
+ .of_match = ti_clk_of_match,
+ .probe = ti_clk_probe,
+ .priv_auto = sizeof(struct ti_clk_data),
+ .ops = &ti_clk_ops,
+};
diff --git a/drivers/clk/ti/clk-mux.c b/drivers/clk/ti/clk-mux.c
index bb5e49e..215241b 100644
--- a/drivers/clk/ti/clk-mux.c
+++ b/drivers/clk/ti/clk-mux.c
@@ -17,7 +17,7 @@
struct clk_ti_mux_priv {
struct clk_bulk parents;
- fdt_addr_t reg;
+ struct clk_ti_reg reg;
u32 flags;
u32 mux_flags;
u32 mask;
@@ -58,7 +58,7 @@
struct clk_ti_mux_priv *priv = dev_get_priv(clk->dev);
u32 val;
- val = readl(priv->reg);
+ val = clk_ti_readl(&priv->reg);
val >>= priv->shift;
val &= priv->mask;
@@ -91,13 +91,13 @@
if (priv->flags & CLK_MUX_HIWORD_MASK) {
val = priv->mask << (priv->shift + 16);
} else {
- val = readl(priv->reg);
+ val = clk_ti_readl(&priv->reg);
val &= ~(priv->mask << priv->shift);
}
val |= index << priv->shift;
- writel(val, priv->reg);
- clk_ti_latch(priv->reg, priv->latch);
+ clk_ti_writel(val, &priv->reg);
+ clk_ti_latch(&priv->reg, priv->latch);
return 0;
}
@@ -215,14 +215,14 @@
static int clk_ti_mux_of_to_plat(struct udevice *dev)
{
struct clk_ti_mux_priv *priv = dev_get_priv(dev);
+ int err;
- priv->reg = dev_read_addr(dev);
- if (priv->reg == FDT_ADDR_T_NONE) {
- dev_err(dev, "failed to get register\n");
- return -EINVAL;
+ err = clk_ti_get_reg_addr(dev, 0, &priv->reg);
+ if (err) {
+ dev_err(dev, "failed to get register address\n");
+ return err;
}
- dev_dbg(dev, "reg=0x%08lx\n", priv->reg);
priv->shift = dev_read_u32_default(dev, "ti,bit-shift", 0);
priv->latch = dev_read_s32_default(dev, "ti,latch-bit", -EINVAL);
diff --git a/drivers/clk/ti/clk-sci.c b/drivers/clk/ti/clk-sci.c
index 6f0fdaa..acb9ead 100644
--- a/drivers/clk/ti/clk-sci.c
+++ b/drivers/clk/ti/clk-sci.c
@@ -111,10 +111,12 @@
#endif
ret = cops->set_freq(sci, clk->id, clk->data, 0, rate, ULONG_MAX);
- if (ret)
+ if (ret) {
dev_err(clk->dev, "%s: set_freq failed (%d)\n", __func__, ret);
+ return ret;
+ }
- return ret;
+ return rate;
}
static int ti_sci_clk_set_parent(struct clk *clk, struct clk *parent)
diff --git a/drivers/clk/ti/clk.c b/drivers/clk/ti/clk.c
index c999df2..6e5cc90 100644
--- a/drivers/clk/ti/clk.c
+++ b/drivers/clk/ti/clk.c
@@ -6,21 +6,34 @@
*/
#include <common.h>
+#include <dm.h>
#include <fdtdec.h>
+#include <regmap.h>
#include <asm/io.h>
+#include <dm/device_compat.h>
#include "clk.h"
-static void clk_ti_rmw(u32 val, u32 mask, fdt_addr_t reg)
+#define CLK_MAX_MEMMAPS 10
+
+struct clk_iomap {
+ struct regmap *regmap;
+ ofnode node;
+};
+
+static unsigned int clk_memmaps_num;
+static struct clk_iomap clk_memmaps[CLK_MAX_MEMMAPS];
+
+static void clk_ti_rmw(u32 val, u32 mask, struct clk_ti_reg *reg)
{
u32 v;
- v = readl(reg);
+ v = clk_ti_readl(reg);
v &= ~mask;
v |= val;
- writel(v, reg);
+ clk_ti_writel(v, reg);
}
-void clk_ti_latch(fdt_addr_t reg, s8 shift)
+void clk_ti_latch(struct clk_ti_reg *reg, s8 shift)
{
u32 latch;
@@ -31,5 +44,77 @@
clk_ti_rmw(latch, latch, reg);
clk_ti_rmw(0, latch, reg);
- readl(reg); /* OCP barrier */
+ clk_ti_readl(reg); /* OCP barrier */
+}
+
+void clk_ti_writel(u32 val, struct clk_ti_reg *reg)
+{
+ struct clk_iomap *io = &clk_memmaps[reg->index];
+
+ regmap_write(io->regmap, reg->offset, val);
+}
+
+u32 clk_ti_readl(struct clk_ti_reg *reg)
+{
+ struct clk_iomap *io = &clk_memmaps[reg->index];
+ u32 val;
+
+ regmap_read(io->regmap, reg->offset, &val);
+ return val;
+}
+
+static ofnode clk_ti_get_regmap_node(struct udevice *dev)
+{
+ ofnode node = dev_ofnode(dev), parent;
+
+ if (!ofnode_valid(node))
+ return ofnode_null();
+
+ parent = ofnode_get_parent(node);
+ if (strcmp(ofnode_get_name(parent), "clocks"))
+ return ofnode_null();
+
+ return ofnode_get_parent(parent);
+}
+
+int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg)
+{
+ ofnode node;
+ int i, ret;
+ u32 val;
+
+ ret = ofnode_read_u32_index(dev_ofnode(dev), "reg", index, &val);
+ if (ret) {
+ dev_err(dev, "%s must have reg[%d]\n", ofnode_get_name(node),
+ index);
+ return ret;
+ }
+
+ /* parent = ofnode_get_parent(parent); */
+ node = clk_ti_get_regmap_node(dev);
+ if (!ofnode_valid(node)) {
+ dev_err(dev, "failed to get regmap node\n");
+ return -EFAULT;
+ }
+
+ for (i = 0; i < clk_memmaps_num; i++) {
+ if (ofnode_equal(clk_memmaps[i].node, node))
+ break;
+ }
+
+ if (i == clk_memmaps_num) {
+ if (i == CLK_MAX_MEMMAPS)
+ return -ENOMEM;
+
+ ret = regmap_init_mem(node, &clk_memmaps[i].regmap);
+ if (ret)
+ return ret;
+
+ clk_memmaps[i].node = node;
+ clk_memmaps_num++;
+ }
+
+ reg->index = i;
+ reg->offset = val;
+ return 0;
}
diff --git a/drivers/clk/ti/clk.h b/drivers/clk/ti/clk.h
index 601c382..96859f9 100644
--- a/drivers/clk/ti/clk.h
+++ b/drivers/clk/ti/clk.h
@@ -8,6 +8,19 @@
#ifndef _CLK_TI_H
#define _CLK_TI_H
-void clk_ti_latch(fdt_addr_t reg, s8 shift);
+/**
+ * struct clk_ti_reg - TI register declaration
+ * @offset: offset from the master IP module base address
+ * @index: index of the master IP module
+ */
+struct clk_ti_reg {
+ u16 offset;
+ u8 index;
+};
+
+void clk_ti_latch(struct clk_ti_reg *reg, s8 shift);
+void clk_ti_writel(u32 val, struct clk_ti_reg *reg);
+u32 clk_ti_readl(struct clk_ti_reg *reg);
+int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg);
#endif /* #ifndef _CLK_TI_H */
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index a7c3120..d618e16 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -271,18 +271,6 @@
used for the address translation. This function is faster and
smaller in size than fdt_translate_address().
-config OF_TRANSLATE_ZERO_SIZE_CELLS
- bool "Enable translation for zero size cells"
- depends on OF_TRANSLATE
- default n
- help
- The routine used to translate an FDT address into a physical CPU
- address was developed by IBM. It considers that crossing any level
- with #size-cells = <0> makes translation impossible, even if it is
- not the way it was specified.
- Enabling this option makes translation possible even in the case
- of crossing levels with #size-cells = <0>.
-
config SPL_OF_TRANSLATE
bool "Translate addresses using fdt_translate_address in SPL"
depends on SPL_DM && SPL_OF_CONTROL
diff --git a/drivers/core/device.c b/drivers/core/device.c
index cb960f8..9f14007 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -561,7 +561,7 @@
* Process 'assigned-{clocks/clock-parents/clock-rates}'
* properties
*/
- ret = clk_set_defaults(dev, 0);
+ ret = clk_set_defaults(dev, CLK_DEFAULTS_PRE);
if (ret)
goto fail;
}
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index 83a50b6..b9874c7 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -50,7 +50,7 @@
reg += index * (na + ns);
- if (ns || gd_size_cells_0()) {
+ if (ns) {
/*
* Use the full-fledged translate function for complex
* bus setups.
diff --git a/drivers/core/of_addr.c b/drivers/core/of_addr.c
index b3e384d..3fbc0a7 100644
--- a/drivers/core/of_addr.c
+++ b/drivers/core/of_addr.c
@@ -18,8 +18,7 @@
/* Max address size we deal with */
#define OF_MAX_ADDR_CELLS 4
#define OF_CHECK_ADDR_COUNT(na) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS)
-#define OF_CHECK_COUNTS(na, ns) (OF_CHECK_ADDR_COUNT(na) && \
- ((ns) > 0 || gd_size_cells_0()))
+#define OF_CHECK_COUNTS(na, ns) (OF_CHECK_ADDR_COUNT(na) && (ns) > 0)
static struct of_bus *of_match_bus(struct device_node *np);
@@ -119,11 +118,6 @@
return NULL;
}
-static void dev_count_cells(const struct device_node *np, int *nap, int *nsp)
-{
- of_bus_default_count_cells(np, nap, nsp);
-}
-
const __be32 *of_get_address(const struct device_node *dev, int index,
u64 *size, unsigned int *flags)
{
@@ -137,7 +131,6 @@
parent = of_get_parent(dev);
if (parent == NULL)
return NULL;
- dev_count_cells(dev, &na, &ns);
bus = of_match_bus(parent);
bus->count_cells(dev, &na, &ns);
of_node_put(parent);
@@ -163,6 +156,11 @@
}
EXPORT_SYMBOL(of_get_address);
+static int of_empty_ranges_quirk(const struct device_node *np)
+{
+ return false;
+}
+
static int of_translate_one(const struct device_node *parent,
struct of_bus *bus, struct of_bus *pbus,
__be32 *addr, int na, int ns, int pna,
@@ -188,9 +186,16 @@
*
* As far as we know, this damage only exists on Apple machines, so
* This code is only enabled on powerpc. --gcl
+ *
+ * This quirk also applies for 'dma-ranges' which frequently exist in
+ * child nodes without 'dma-ranges' in the parent nodes. --RobH
*/
-
ranges = of_get_property(parent, rprop, &rlen);
+ if (ranges == NULL && !of_empty_ranges_quirk(parent) &&
+ strcmp(rprop, "dma-ranges")) {
+ debug("no ranges; cannot translate\n");
+ return 1;
+ }
if (ranges == NULL || rlen == 0) {
offset = of_read_number(addr, na);
memset(addr, 0, pna * 4);
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index fa0bd2a..6c771e3 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -303,6 +303,8 @@
{
int na, ns;
+ *size = FDT_SIZE_T_NONE;
+
if (ofnode_is_np(node)) {
const __be32 *prop_val;
u64 size64;
@@ -317,8 +319,7 @@
ns = of_n_size_cells(ofnode_to_np(node));
- if (IS_ENABLED(CONFIG_OF_TRANSLATE) &&
- (ns > 0 || gd_size_cells_0())) {
+ if (IS_ENABLED(CONFIG_OF_TRANSLATE) && ns > 0) {
return of_translate_address(ofnode_to_np(node), prop_val);
} else {
na = of_n_addr_cells(ofnode_to_np(node));
@@ -347,6 +348,15 @@
return ofnode_get_addr_index(node, 0);
}
+fdt_size_t ofnode_get_size(ofnode node)
+{
+ fdt_size_t size;
+
+ ofnode_get_addr_size_index(node, 0, &size);
+
+ return size;
+}
+
int ofnode_stringlist_search(ofnode node, const char *property,
const char *string)
{
@@ -692,10 +702,8 @@
ns = of_n_size_cells(np);
*sizep = of_read_number(prop + na, ns);
- if (CONFIG_IS_ENABLED(OF_TRANSLATE) &&
- (ns > 0 || gd_size_cells_0())) {
+ if (CONFIG_IS_ENABLED(OF_TRANSLATE) && ns > 0)
return of_translate_address(np, prop);
- }
else
return of_read_number(prop, na);
} else {
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
index b51ce10..3206f3d 100644
--- a/drivers/core/regmap.c
+++ b/drivers/core/regmap.c
@@ -435,7 +435,36 @@
int regmap_read(struct regmap *map, uint offset, uint *valp)
{
- return regmap_raw_read(map, offset, valp, map->width);
+ union {
+ u8 v8;
+ u16 v16;
+ u32 v32;
+ u64 v64;
+ } u;
+ int res;
+
+ res = regmap_raw_read(map, offset, &u, map->width);
+ if (res)
+ return res;
+
+ switch (map->width) {
+ case REGMAP_SIZE_8:
+ *valp = u.v8;
+ break;
+ case REGMAP_SIZE_16:
+ *valp = u.v16;
+ break;
+ case REGMAP_SIZE_32:
+ *valp = u.v32;
+ break;
+ case REGMAP_SIZE_64:
+ *valp = u.v64;
+ break;
+ default:
+ unreachable();
+ }
+
+ return 0;
}
static inline void __write_8(u8 *addr, const u8 *val,
@@ -546,7 +575,33 @@
int regmap_write(struct regmap *map, uint offset, uint val)
{
- return regmap_raw_write(map, offset, &val, map->width);
+ union {
+ u8 v8;
+ u16 v16;
+ u32 v32;
+ u64 v64;
+ } u;
+
+ switch (map->width) {
+ case REGMAP_SIZE_8:
+ u.v8 = val;
+ break;
+ case REGMAP_SIZE_16:
+ u.v16 = val;
+ break;
+ case REGMAP_SIZE_32:
+ u.v32 = val;
+ break;
+ case REGMAP_SIZE_64:
+ u.v64 = val;
+ break;
+ default:
+ debug("%s: regmap size %zu unknown\n", __func__,
+ (size_t)map->width);
+ return -EINVAL;
+ }
+
+ return regmap_raw_write(map, offset, &u, map->width);
}
int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val)
diff --git a/drivers/core/root.c b/drivers/core/root.c
index d9a19c5..fe0562c 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -164,9 +164,6 @@
{
int ret;
- if (IS_ENABLED(CONFIG_OF_TRANSLATE_ZERO_SIZE_CELLS))
- gd->dm_flags |= GD_DM_FLG_SIZE_CELLS_0;
-
if (gd->dm_root) {
dm_warn("Virtual root driver already exists!\n");
return -EINVAL;
@@ -265,7 +262,7 @@
static int dm_scan_fdt_node(struct udevice *parent, ofnode parent_node,
bool pre_reloc_only)
{
- int ret = 0, err;
+ int ret = 0, err = 0;
ofnode node;
if (!ofnode_valid(parent_node))
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index 121dc54..b505474 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -92,5 +92,25 @@
help
This option allows to call the function set_dfu_alt_info to
dynamically build dfu_alt_info in board.
+
+config SYS_DFU_DATA_BUF_SIZE
+ hex "Size of buffer to be allocated for transfer to raw storage device"
+ default 0x800000
+ help
+ DFU transfer uses a buffer before writing data to the
+ raw storage device. This value can be used for setting the
+ size of this buffer. The size of the buffer is also configurable
+ through the "dfu_bufsiz" environment variable. If both are
+ given the size of the buffer is set to "dfu_bufsize".
+
+config SYS_DFU_MAX_FILE_SIZE
+ hex "Size of the buffer to be allocated for transferring files"
+ default SYS_DFU_DATA_BUF_SIZE
+ help
+ When updating files rather than the raw storage device,
+ we use a static buffer to copy the file into and then write
+ the buffer once we've been given the whole file. Define
+ this to the maximum filesize (in bytes) for the buffer.
+ If undefined it defaults to the CONFIG_SYS_DFU_DATA_BUF_SIZE.
endif
endmenu
diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c
index ca67585..ec40b8f 100644
--- a/drivers/dfu/dfu_mtd.c
+++ b/drivers/dfu/dfu_mtd.c
@@ -150,7 +150,9 @@
/* Write done, lock again */
debug("Locking the mtd device\n");
ret = mtd_lock(mtd, lock_ofs, lock_len);
- if (ret && ret != -EOPNOTSUPP)
+ if (ret == -EOPNOTSUPP)
+ ret = 0;
+ else if (ret)
printf("MTD device lock failed\n");
}
return ret;
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 4ea9c62..0391cd3 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -5,3 +5,4 @@
k3-psil-data-y += k3-psil.o
k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
+k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
diff --git a/drivers/dma/ti/k3-psil-am64.c b/drivers/dma/ti/k3-psil-am64.c
new file mode 100644
index 0000000..15742c3
--- /dev/null
+++ b/drivers/dma/ti/k3-psil-am64.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ */
+
+#include <linux/kernel.h>
+
+#include "k3-psil-priv.h"
+
+#define PSIL_PDMA_XY_TR(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1, \
+ }, \
+ }
+
+#define PSIL_PDMA_XY_PKT(x) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_PDMA_XY, \
+ .mapped_channel_id = -1, \
+ .pkt_mode = 1, \
+ }, \
+ }
+
+#define PSIL_ETHERNET(x, ch, flow_base, flow_cnt) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 16, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = flow_base, \
+ }, \
+ }
+
+#define PSIL_SAUL(x, ch, flow_base, flow_cnt, default_flow, tx) \
+ { \
+ .thread_id = x, \
+ .ep_config = { \
+ .ep_type = PSIL_EP_NATIVE, \
+ .pkt_mode = 1, \
+ .needs_epib = 1, \
+ .psd_size = 64, \
+ .mapped_channel_id = ch, \
+ .flow_start = flow_base, \
+ .flow_num = flow_cnt, \
+ .default_flow_id = default_flow, \
+ .notdpkt = tx, \
+ }, \
+ }
+
+/* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */
+static struct psil_ep am64_src_ep_map[] = {
+ /* SAUL */
+ PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
+ PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
+ PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
+ PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
+ /* ICSS_G0 */
+ PSIL_ETHERNET(0x4100, 21, 48, 16),
+ PSIL_ETHERNET(0x4101, 22, 64, 16),
+ PSIL_ETHERNET(0x4102, 23, 80, 16),
+ PSIL_ETHERNET(0x4103, 24, 96, 16),
+ /* ICSS_G1 */
+ PSIL_ETHERNET(0x4200, 25, 112, 16),
+ PSIL_ETHERNET(0x4201, 26, 128, 16),
+ PSIL_ETHERNET(0x4202, 27, 144, 16),
+ PSIL_ETHERNET(0x4203, 28, 160, 16),
+ /* PDMA_MAIN0 - SPI0-3 */
+ PSIL_PDMA_XY_PKT(0x4300),
+ PSIL_PDMA_XY_PKT(0x4301),
+ PSIL_PDMA_XY_PKT(0x4302),
+ PSIL_PDMA_XY_PKT(0x4303),
+ PSIL_PDMA_XY_PKT(0x4304),
+ PSIL_PDMA_XY_PKT(0x4305),
+ PSIL_PDMA_XY_PKT(0x4306),
+ PSIL_PDMA_XY_PKT(0x4307),
+ PSIL_PDMA_XY_PKT(0x4308),
+ PSIL_PDMA_XY_PKT(0x4309),
+ PSIL_PDMA_XY_PKT(0x430a),
+ PSIL_PDMA_XY_PKT(0x430b),
+ PSIL_PDMA_XY_PKT(0x430c),
+ PSIL_PDMA_XY_PKT(0x430d),
+ PSIL_PDMA_XY_PKT(0x430e),
+ PSIL_PDMA_XY_PKT(0x430f),
+ /* PDMA_MAIN0 - USART0-1 */
+ PSIL_PDMA_XY_PKT(0x4310),
+ PSIL_PDMA_XY_PKT(0x4311),
+ /* PDMA_MAIN1 - SPI4 */
+ PSIL_PDMA_XY_PKT(0x4400),
+ PSIL_PDMA_XY_PKT(0x4401),
+ PSIL_PDMA_XY_PKT(0x4402),
+ PSIL_PDMA_XY_PKT(0x4403),
+ /* PDMA_MAIN1 - USART2-6 */
+ PSIL_PDMA_XY_PKT(0x4404),
+ PSIL_PDMA_XY_PKT(0x4405),
+ PSIL_PDMA_XY_PKT(0x4406),
+ PSIL_PDMA_XY_PKT(0x4407),
+ PSIL_PDMA_XY_PKT(0x4408),
+ /* PDMA_MAIN1 - ADCs */
+ PSIL_PDMA_XY_TR(0x440f),
+ PSIL_PDMA_XY_TR(0x4410),
+ /* CPSW2 */
+ PSIL_ETHERNET(0x4500, 16, 16, 16),
+};
+
+/* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */
+static struct psil_ep am64_dst_ep_map[] = {
+ /* SAUL */
+ PSIL_SAUL(0xc000, 24, 80, 8, 80, 1),
+ PSIL_SAUL(0xc001, 25, 88, 8, 88, 1),
+ /* ICSS_G0 */
+ PSIL_ETHERNET(0xc100, 26, 96, 1),
+ PSIL_ETHERNET(0xc101, 27, 97, 1),
+ PSIL_ETHERNET(0xc102, 28, 98, 1),
+ PSIL_ETHERNET(0xc103, 29, 99, 1),
+ PSIL_ETHERNET(0xc104, 30, 100, 1),
+ PSIL_ETHERNET(0xc105, 31, 101, 1),
+ PSIL_ETHERNET(0xc106, 32, 102, 1),
+ PSIL_ETHERNET(0xc107, 33, 103, 1),
+ /* ICSS_G1 */
+ PSIL_ETHERNET(0xc200, 34, 104, 1),
+ PSIL_ETHERNET(0xc201, 35, 105, 1),
+ PSIL_ETHERNET(0xc202, 36, 106, 1),
+ PSIL_ETHERNET(0xc203, 37, 107, 1),
+ PSIL_ETHERNET(0xc204, 38, 108, 1),
+ PSIL_ETHERNET(0xc205, 39, 109, 1),
+ PSIL_ETHERNET(0xc206, 40, 110, 1),
+ PSIL_ETHERNET(0xc207, 41, 111, 1),
+ /* CPSW2 */
+ PSIL_ETHERNET(0xc500, 16, 16, 8),
+ PSIL_ETHERNET(0xc501, 17, 24, 8),
+ PSIL_ETHERNET(0xc502, 18, 32, 8),
+ PSIL_ETHERNET(0xc503, 19, 40, 8),
+ PSIL_ETHERNET(0xc504, 20, 48, 8),
+ PSIL_ETHERNET(0xc505, 21, 56, 8),
+ PSIL_ETHERNET(0xc506, 22, 64, 8),
+ PSIL_ETHERNET(0xc507, 23, 72, 8),
+};
+
+struct psil_ep_map am64_ep_map = {
+ .name = "am64",
+ .src = am64_src_ep_map,
+ .src_count = ARRAY_SIZE(am64_src_ep_map),
+ .dst = am64_dst_ep_map,
+ .dst_count = ARRAY_SIZE(am64_dst_ep_map),
+};
diff --git a/drivers/dma/ti/k3-psil-am654.c b/drivers/dma/ti/k3-psil-am654.c
index f95d99c..d16c075 100644
--- a/drivers/dma/ti/k3-psil-am654.c
+++ b/drivers/dma/ti/k3-psil-am654.c
@@ -44,40 +44,22 @@
static struct psil_ep am654_dst_ep_map[] = {
/* PRU_ICSSG0 */
PSIL_ETHERNET(0xc100),
- PSIL_ETHERNET(0xc101),
- PSIL_ETHERNET(0xc102),
- PSIL_ETHERNET(0xc103),
+ /* PSIL: 0xc101 - 0xc103 unused */
PSIL_ETHERNET(0xc104),
- PSIL_ETHERNET(0xc105),
- PSIL_ETHERNET(0xc106),
- PSIL_ETHERNET(0xc107),
+ /* PSIL: 0xc105 - 0xc107 unused */
/* PRU_ICSSG1 */
PSIL_ETHERNET(0xc200),
- PSIL_ETHERNET(0xc201),
- PSIL_ETHERNET(0xc202),
- PSIL_ETHERNET(0xc203),
+ /* PSIL: 0xc201 - 0xc203 unused */
PSIL_ETHERNET(0xc204),
- PSIL_ETHERNET(0xc205),
- PSIL_ETHERNET(0xc206),
- PSIL_ETHERNET(0xc207),
+ /* PSIL: 0xc205 - 0xc207 unused */
/* PRU_ICSSG2 */
PSIL_ETHERNET(0xc300),
- PSIL_ETHERNET(0xc301),
- PSIL_ETHERNET(0xc302),
- PSIL_ETHERNET(0xc303),
+ /* PSIL: 0xc301 - 0xc303 unused */
PSIL_ETHERNET(0xc304),
- PSIL_ETHERNET(0xc305),
- PSIL_ETHERNET(0xc306),
- PSIL_ETHERNET(0xc307),
+ /* PSIL: 0xc305 - 0xc307 unused */
/* CPSW0 */
PSIL_ETHERNET(0xf000),
- PSIL_ETHERNET(0xf001),
- PSIL_ETHERNET(0xf002),
- PSIL_ETHERNET(0xf003),
- PSIL_ETHERNET(0xf004),
- PSIL_ETHERNET(0xf005),
- PSIL_ETHERNET(0xf006),
- PSIL_ETHERNET(0xf007),
+ /* PSIL: 0xf001 - 0xf007 unused */
};
struct psil_ep_map am654_ep_map = {
diff --git a/drivers/dma/ti/k3-psil-priv.h b/drivers/dma/ti/k3-psil-priv.h
index d3a3832..02d1c20 100644
--- a/drivers/dma/ti/k3-psil-priv.h
+++ b/drivers/dma/ti/k3-psil-priv.h
@@ -39,5 +39,6 @@
/* SoC PSI-L endpoint maps */
extern struct psil_ep_map am654_ep_map;
extern struct psil_ep_map j721e_ep_map;
+extern struct psil_ep_map am64_ep_map;
#endif /* K3_PSIL_PRIV_H_ */
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index b5c92b2..e82f807 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -20,6 +20,8 @@
soc_ep_map = &am654_ep_map;
else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
soc_ep_map = &j721e_ep_map;
+ else if (IS_ENABLED(CONFIG_SOC_K3_AM642))
+ soc_ep_map = &am64_ep_map;
}
if (thread_id & K3_PSIL_DST_THREAD_ID_OFFSET && soc_ep_map->dst) {
diff --git a/drivers/dma/ti/k3-psil.h b/drivers/dma/ti/k3-psil.h
index 53c61b4..1e0fe06 100644
--- a/drivers/dma/ti/k3-psil.h
+++ b/drivers/dma/ti/k3-psil.h
@@ -50,6 +50,15 @@
* @channel_tpl: Desired throughput level for the channel
* @pdma_acc32: ACC32 must be enabled on the PDMA side
* @pdma_burst: BURST must be enabled on the PDMA side
+ * @mapped_channel_id: PKTDMA thread to channel mapping for mapped
+ * channels. The thread must be serviced by the specified
+ * channel if mapped_channel_id is >= 0 in case of PKTDMA
+ * @flow_start: PKTDMA flow range start of mapped channel. Unmapped
+ * channels use flow_id == chan_id
+ * @flow_num: PKTDMA flow count of mapped channel. Unmapped
+ * channels use flow_id == chan_id
+ * @default_flow_id: PKTDMA default (r)flow index of mapped channel.
+ * Must be within the flow range of the mapped channel.
*/
struct psil_endpoint_config {
enum psil_endpoint_type ep_type;
@@ -63,5 +72,12 @@
/* PDMA properties, valid for PSIL_EP_PDMA_* */
unsigned pdma_acc32:1;
unsigned pdma_burst:1;
+
+ /* PKTDMA mapped channel */
+ int mapped_channel_id;
+ /* PKTDMA tflow and rflow ranges for mapped channel */
+ u16 flow_start;
+ u16 flow_num;
+ u16 default_flow_id;
};
#endif /* K3_PSIL_H_ */
diff --git a/drivers/dma/ti/k3-udma-u-boot.c b/drivers/dma/ti/k3-udma-u-boot.c
new file mode 100644
index 0000000..3e04f55
--- /dev/null
+++ b/drivers/dma/ti/k3-udma-u-boot.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+#define UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT (16)
+
+/* How SRC/DST tag should be updated by UDMA in the descriptor's Word 3 */
+#define UDMA_RFLOW_SRCTAG_NONE 0
+#define UDMA_RFLOW_SRCTAG_CFG_TAG 1
+#define UDMA_RFLOW_SRCTAG_FLOW_ID 2
+#define UDMA_RFLOW_SRCTAG_SRC_TAG 4
+
+#define UDMA_RFLOW_DSTTAG_NONE 0
+#define UDMA_RFLOW_DSTTAG_CFG_TAG 1
+#define UDMA_RFLOW_DSTTAG_FLOW_ID 2
+#define UDMA_RFLOW_DSTTAG_DST_TAG_LO 4
+#define UDMA_RFLOW_DSTTAG_DST_TAG_HI 5
+
+#define UDMA_RFLOW_RFC_DEFAULT \
+ ((UDMA_RFLOW_SRCTAG_NONE << UDMA_RFLOW_RFC_SRC_TAG_HI_SEL_SHIFT) | \
+ (UDMA_RFLOW_SRCTAG_SRC_TAG << UDMA_RFLOW_RFC_SRC_TAG_LO_SEL_SHIFT) | \
+ (UDMA_RFLOW_DSTTAG_DST_TAG_HI << UDMA_RFLOW_RFC_DST_TAG_HI_SEL_SHIFT) | \
+ (UDMA_RFLOW_DSTTAG_DST_TAG_LO << UDMA_RFLOW_RFC_DST_TAG_LO_SE_SHIFT))
+
+#define UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT (16)
+
+/* TCHAN */
+static inline u32 udma_tchan_read(struct udma_tchan *tchan, int reg)
+{
+ if (!tchan)
+ return 0;
+ return udma_read(tchan->reg_chan, reg);
+}
+
+static inline void udma_tchan_write(struct udma_tchan *tchan, int reg, u32 val)
+{
+ if (!tchan)
+ return;
+ udma_write(tchan->reg_chan, reg, val);
+}
+
+static inline void udma_tchan_update_bits(struct udma_tchan *tchan, int reg,
+ u32 mask, u32 val)
+{
+ if (!tchan)
+ return;
+ udma_update_bits(tchan->reg_chan, reg, mask, val);
+}
+
+/* RCHAN */
+static inline u32 udma_rchan_read(struct udma_rchan *rchan, int reg)
+{
+ if (!rchan)
+ return 0;
+ return udma_read(rchan->reg_chan, reg);
+}
+
+static inline void udma_rchan_write(struct udma_rchan *rchan, int reg, u32 val)
+{
+ if (!rchan)
+ return;
+ udma_write(rchan->reg_chan, reg, val);
+}
+
+static inline void udma_rchan_update_bits(struct udma_rchan *rchan, int reg,
+ u32 mask, u32 val)
+{
+ if (!rchan)
+ return;
+ udma_update_bits(rchan->reg_chan, reg, mask, val);
+}
+
+/* RFLOW */
+static inline u32 udma_rflow_read(struct udma_rflow *rflow, int reg)
+{
+ if (!rflow)
+ return 0;
+ return udma_read(rflow->reg_rflow, reg);
+}
+
+static inline void udma_rflow_write(struct udma_rflow *rflow, int reg, u32 val)
+{
+ if (!rflow)
+ return;
+ udma_write(rflow->reg_rflow, reg, val);
+}
+
+static inline void udma_rflow_update_bits(struct udma_rflow *rflow, int reg,
+ u32 mask, u32 val)
+{
+ if (!rflow)
+ return;
+ udma_update_bits(rflow->reg_rflow, reg, mask, val);
+}
+
+static void udma_alloc_tchan_raw(struct udma_chan *uc)
+{
+ u32 mode, fetch_size;
+
+ if (uc->config.pkt_mode)
+ mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR;
+ else
+ mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR;
+
+ udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG,
+ UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode);
+
+ if (uc->config.dir == DMA_MEM_TO_MEM)
+ fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
+ else
+ fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
+ uc->config.psd_size, 0) >> 2;
+
+ udma_tchan_update_bits(uc->tchan, UDMA_TCHAN_TCFG_REG,
+ UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size);
+ udma_tchan_write(uc->tchan, UDMA_TCHAN_TCQ_REG,
+ k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring));
+}
+
+static void udma_alloc_rchan_raw(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ int fd_ring = k3_nav_ringacc_get_ring_id(uc->rflow->fd_ring);
+ int rx_ring = k3_nav_ringacc_get_ring_id(uc->rflow->r_ring);
+ int tc_ring = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
+ u32 rx_einfo_present = 0, rx_psinfo_present = 0;
+ u32 mode, fetch_size, rxcq_num;
+
+ if (uc->config.pkt_mode)
+ mode = UDMA_CHAN_CFG_CHAN_TYPE_PACKET_PBRR;
+ else
+ mode = UDMA_CHAN_CFG_CHAN_TYPE_3RDP_BC_PBRR;
+
+ udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG,
+ UDMA_CHAN_CFG_CHAN_TYPE_MASK, mode);
+
+ if (uc->config.dir == DMA_MEM_TO_MEM) {
+ fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
+ rxcq_num = tc_ring;
+ } else {
+ fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
+ uc->config.psd_size, 0) >> 2;
+ rxcq_num = rx_ring;
+ }
+
+ udma_rchan_update_bits(uc->rchan, UDMA_RCHAN_RCFG_REG,
+ UDMA_CHAN_CFG_FETCH_SIZE_MASK, fetch_size);
+ udma_rchan_write(uc->rchan, UDMA_RCHAN_RCQ_REG, rxcq_num);
+
+ if (uc->config.dir == DMA_MEM_TO_MEM)
+ return;
+
+ if (ud->match_data->type == DMA_TYPE_UDMA &&
+ uc->rflow->id != uc->rchan->id &&
+ uc->config.dir != DMA_MEM_TO_MEM)
+ udma_rchan_write(uc->rchan, UDMA_RCHAN_RFLOW_RNG_REG, uc->rflow->id |
+ 1 << UDMA_RCHAN_RFLOW_RNG_FLOWID_CNT_SHIFT);
+
+ if (uc->config.needs_epib)
+ rx_einfo_present = UDMA_RFLOW_RFA_EINFO;
+
+ if (uc->config.psd_size)
+ rx_psinfo_present = UDMA_RFLOW_RFA_PSINFO;
+
+ udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(A),
+ rx_einfo_present | rx_psinfo_present | rxcq_num);
+
+ udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(C), UDMA_RFLOW_RFC_DEFAULT);
+ udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(D),
+ fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT);
+ udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(E),
+ fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT);
+ udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(G), fd_ring);
+ udma_rflow_write(uc->rflow, UDMA_RFLOW_REG(H),
+ fd_ring | fd_ring << UDMA_RFLOW_RFx_REG_FDQ_SIZE_SHIFT);
+}
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index f3ec827..411edef 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -28,6 +28,7 @@
#include <linux/soc/ti/cppi5.h>
#include <linux/soc/ti/ti-udma.h>
#include <linux/soc/ti/ti_sci_protocol.h>
+#include <linux/soc/ti/cppi5.h>
#include "k3-udma-hwdef.h"
#include "k3-psil-priv.h"
@@ -36,57 +37,99 @@
struct udma_chan;
+enum k3_dma_type {
+ DMA_TYPE_UDMA = 0,
+ DMA_TYPE_BCDMA,
+ DMA_TYPE_PKTDMA,
+};
+
enum udma_mmr {
MMR_GCFG = 0,
+ MMR_BCHANRT,
MMR_RCHANRT,
MMR_TCHANRT,
+ MMR_RCHAN,
+ MMR_TCHAN,
+ MMR_RFLOW,
MMR_LAST,
};
static const char * const mmr_names[] = {
- "gcfg", "rchanrt", "tchanrt"
+ [MMR_GCFG] = "gcfg",
+ [MMR_BCHANRT] = "bchanrt",
+ [MMR_RCHANRT] = "rchanrt",
+ [MMR_TCHANRT] = "tchanrt",
+ [MMR_RCHAN] = "rchan",
+ [MMR_TCHAN] = "tchan",
+ [MMR_RFLOW] = "rflow",
};
struct udma_tchan {
+ void __iomem *reg_chan;
void __iomem *reg_rt;
int id;
struct k3_nav_ring *t_ring; /* Transmit ring */
struct k3_nav_ring *tc_ring; /* Transmit Completion ring */
+ int tflow_id; /* applicable only for PKTDMA */
+
+};
+
+#define udma_bchan udma_tchan
+
+struct udma_rflow {
+ void __iomem *reg_rflow;
+ int id;
+ struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
+ struct k3_nav_ring *r_ring; /* Receive ring */
};
struct udma_rchan {
+ void __iomem *reg_chan;
void __iomem *reg_rt;
int id;
};
+struct udma_oes_offsets {
+ /* K3 UDMA Output Event Offset */
+ u32 udma_rchan;
+
+ /* BCDMA Output Event Offsets */
+ u32 bcdma_bchan_data;
+ u32 bcdma_bchan_ring;
+ u32 bcdma_tchan_data;
+ u32 bcdma_tchan_ring;
+ u32 bcdma_rchan_data;
+ u32 bcdma_rchan_ring;
+
+ /* PKTDMA Output Event Offsets */
+ u32 pktdma_tchan_flow;
+ u32 pktdma_rchan_flow;
+};
+
#define UDMA_FLAG_PDMA_ACC32 BIT(0)
#define UDMA_FLAG_PDMA_BURST BIT(1)
#define UDMA_FLAG_TDTYPE BIT(2)
struct udma_match_data {
+ enum k3_dma_type type;
u32 psil_base;
bool enable_memcpy_support;
u32 flags;
u32 statictr_z_mask;
- u32 rchan_oes_offset;
+ struct udma_oes_offsets oes;
u8 tpl_levels;
u32 level_start_idx[];
};
-struct udma_rflow {
- int id;
-
- struct k3_nav_ring *fd_ring; /* Free Descriptor ring */
- struct k3_nav_ring *r_ring; /* Receive ring*/
-};
-
enum udma_rm_range {
- RM_RANGE_TCHAN = 0,
+ RM_RANGE_BCHAN = 0,
+ RM_RANGE_TCHAN,
RM_RANGE_RCHAN,
RM_RANGE_RFLOW,
+ RM_RANGE_TFLOW,
RM_RANGE_LAST,
};
@@ -111,15 +154,21 @@
u32 features;
+ int bchan_cnt;
int tchan_cnt;
int echan_cnt;
int rchan_cnt;
int rflow_cnt;
+ int tflow_cnt;
+ unsigned long *bchan_map;
unsigned long *tchan_map;
unsigned long *rchan_map;
unsigned long *rflow_map;
unsigned long *rflow_map_reserved;
+ unsigned long *rflow_in_use;
+ unsigned long *tflow_map;
+ struct udma_bchan *bchans;
struct udma_tchan *tchans;
struct udma_rchan *rchans;
struct udma_rflow *rflows;
@@ -143,6 +192,11 @@
enum psil_endpoint_type ep_type;
enum udma_tp_level channel_tpl; /* Channel Throughput Level */
+ /* PKTDMA mapped channel */
+ int mapped_channel_id;
+ /* PKTDMA default tflow or rflow for mapped channel */
+ int default_flow_id;
+
enum dma_direction dir;
unsigned int pkt_mode:1; /* TR or packet */
@@ -156,6 +210,7 @@
struct udma_dev *ud;
char name[20];
+ struct udma_bchan *bchan;
struct udma_tchan *tchan;
struct udma_rchan *rchan;
struct udma_rflow *rflow;
@@ -289,6 +344,16 @@
return "invalid";
}
+#include "k3-udma-u-boot.c"
+
+static void udma_reset_uchan(struct udma_chan *uc)
+{
+ memset(&uc->config, 0, sizeof(uc->config));
+ uc->config.remote_thread_id = -1;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
+}
+
static inline bool udma_is_chan_running(struct udma_chan *uc)
{
u32 trt_ctl = 0;
@@ -371,7 +436,7 @@
}
if (ring1)
- k3_nav_ringacc_ring_reset_dma(ring1, 0);
+ k3_nav_ringacc_ring_reset_dma(ring1, k3_nav_ringacc_ring_get_occ(ring1));
if (ring2)
k3_nav_ringacc_ring_reset(ring2);
}
@@ -390,8 +455,10 @@
val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PCNT_REG);
udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PCNT_REG, val);
- val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
- udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
+ if (!uc->bchan) {
+ val = udma_tchanrt_read(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG);
+ udma_tchanrt_write(uc->tchan, UDMA_TCHAN_RT_PEER_BCNT_REG, val);
+ }
}
if (uc->rchan) {
@@ -640,10 +707,32 @@
return 0;
}
- uc->tchan = __udma_reserve_tchan(ud, -1);
+ uc->tchan = __udma_reserve_tchan(ud, uc->config.mapped_channel_id);
if (IS_ERR(uc->tchan))
return PTR_ERR(uc->tchan);
+ if (ud->tflow_cnt) {
+ int tflow_id;
+
+ /* Only PKTDMA have support for tx flows */
+ if (uc->config.default_flow_id >= 0)
+ tflow_id = uc->config.default_flow_id;
+ else
+ tflow_id = uc->tchan->id;
+
+ if (test_bit(tflow_id, ud->tflow_map)) {
+ dev_err(ud->dev, "tflow%d is in use\n", tflow_id);
+ __clear_bit(uc->tchan->id, ud->tchan_map);
+ uc->tchan = NULL;
+ return -ENOENT;
+ }
+
+ uc->tchan->tflow_id = tflow_id;
+ __set_bit(tflow_id, ud->tflow_map);
+ } else {
+ uc->tchan->tflow_id = -1;
+ }
+
pr_debug("chan%d: got tchan%d\n", uc->id, uc->tchan->id);
return 0;
@@ -659,7 +748,7 @@
return 0;
}
- uc->rchan = __udma_reserve_rchan(ud, -1);
+ uc->rchan = __udma_reserve_rchan(ud, uc->config.mapped_channel_id);
if (IS_ERR(uc->rchan))
return PTR_ERR(uc->rchan);
@@ -751,6 +840,8 @@
dev_dbg(ud->dev, "chan%d: put tchan%d\n", uc->id,
uc->tchan->id);
__clear_bit(uc->tchan->id, ud->tchan_map);
+ if (uc->tchan->tflow_id >= 0)
+ __clear_bit(uc->tchan->tflow_id, ud->tflow_map);
uc->tchan = NULL;
}
}
@@ -855,15 +946,24 @@
if (uc->config.dir == DMA_MEM_TO_MEM)
return 0;
+ if (uc->config.default_flow_id >= 0)
+ ret = udma_get_rflow(uc, uc->config.default_flow_id);
+ else
+ ret = udma_get_rflow(uc, uc->rchan->id);
+
- ret = udma_get_rflow(uc, uc->rchan->id);
if (ret) {
ret = -EBUSY;
goto err_rflow;
}
- fd_ring_id = ud->tchan_cnt + ud->echan_cnt + uc->rchan->id;
-
rflow = uc->rflow;
+ if (ud->tflow_cnt) {
+ fd_ring_id = ud->tflow_cnt + rflow->id;
+ } else {
+ fd_ring_id = ud->bchan_cnt + ud->tchan_cnt + ud->echan_cnt +
+ uc->rchan->id;
+ }
+
ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, fd_ring_id, -1,
&rflow->fd_ring, &rflow->r_ring);
if (ret) {
@@ -925,10 +1025,20 @@
req.txcq_qnum = tc_ring;
ret = tisci_rm->tisci_udmap_ops->tx_ch_cfg(tisci_rm->tisci, &req);
- if (ret)
+ if (ret) {
dev_err(ud->dev, "tisci tx alloc failed %d\n", ret);
+ return ret;
+ }
- return ret;
+ /*
+ * Above TI SCI call handles firewall configuration, cfg
+ * register configuration still has to be done locally in
+ * absence of RM services.
+ */
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ udma_alloc_tchan_raw(uc);
+
+ return 0;
}
static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
@@ -950,9 +1060,7 @@
req.valid_params = TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
- TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID;
req.nav_id = tisci_rm->tisci_dev_id;
req.index = uc->rchan->id;
req.rx_chan_type = mode;
@@ -965,9 +1073,13 @@
0) >> 2;
req.rxcq_qnum = rx_ring;
}
- if (uc->rflow->id != uc->rchan->id && uc->config.dir != DMA_MEM_TO_MEM) {
+ if (ud->match_data->type == DMA_TYPE_UDMA &&
+ uc->rflow->id != uc->rchan->id &&
+ uc->config.dir != DMA_MEM_TO_MEM) {
req.flowid_start = uc->rflow->id;
req.flowid_cnt = 1;
+ req.valid_params |= TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID |
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID;
}
ret = tisci_rm->tisci_udmap_ops->rx_ch_cfg(tisci_rm->tisci, &req);
@@ -1023,11 +1135,21 @@
ret = tisci_rm->tisci_udmap_ops->rx_flow_cfg(tisci_rm->tisci,
&flow_req);
- if (ret)
+ if (ret) {
dev_err(ud->dev, "tisci rx %u flow %u cfg failed %d\n",
uc->rchan->id, uc->rflow->id, ret);
+ return ret;
+ }
- return ret;
+ /*
+ * Above TI SCI call handles firewall configuration, cfg
+ * register configuration still has to be done locally in
+ * absence of RM services.
+ */
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ udma_alloc_rchan_raw(uc);
+
+ return 0;
}
static int udma_alloc_chan_resources(struct udma_chan *uc)
@@ -1150,12 +1272,58 @@
uc->config.dir = DMA_MEM_TO_MEM;
}
+static const char * const range_names[] = {
+ [RM_RANGE_BCHAN] = "ti,sci-rm-range-bchan",
+ [RM_RANGE_TCHAN] = "ti,sci-rm-range-tchan",
+ [RM_RANGE_RCHAN] = "ti,sci-rm-range-rchan",
+ [RM_RANGE_RFLOW] = "ti,sci-rm-range-rflow",
+ [RM_RANGE_TFLOW] = "ti,sci-rm-range-tflow",
+};
+
static int udma_get_mmrs(struct udevice *dev)
{
struct udma_dev *ud = dev_get_priv(dev);
+ u32 cap2, cap3, cap4;
int i;
+ ud->mmrs[MMR_GCFG] = (uint32_t *)devfdt_get_addr_name(dev, mmr_names[MMR_GCFG]);
+ if (!ud->mmrs[MMR_GCFG])
+ return -EINVAL;
+
+ cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
+ cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
+
- for (i = 0; i < MMR_LAST; i++) {
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ud->rflow_cnt = cap3 & 0x3fff;
+ ud->tchan_cnt = cap2 & 0x1ff;
+ ud->echan_cnt = (cap2 >> 9) & 0x1ff;
+ ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+ break;
+ case DMA_TYPE_BCDMA:
+ ud->bchan_cnt = cap2 & 0x1ff;
+ ud->tchan_cnt = (cap2 >> 9) & 0x1ff;
+ ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+ break;
+ case DMA_TYPE_PKTDMA:
+ cap4 = udma_read(ud->mmrs[MMR_GCFG], 0x30);
+ ud->tchan_cnt = cap2 & 0x1ff;
+ ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+ ud->rflow_cnt = cap3 & 0x3fff;
+ ud->tflow_cnt = cap4 & 0x3fff;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ for (i = 1; i < MMR_LAST; i++) {
+ if (i == MMR_BCHANRT && ud->bchan_cnt == 0)
+ continue;
+ if (i == MMR_TCHANRT && ud->tchan_cnt == 0)
+ continue;
+ if (i == MMR_RCHANRT && ud->rchan_cnt == 0)
+ continue;
+
ud->mmrs[i] = (uint32_t *)devfdt_get_addr_name(dev,
mmr_names[i]);
if (!ud->mmrs[i])
@@ -1168,23 +1336,10 @@
static int udma_setup_resources(struct udma_dev *ud)
{
struct udevice *dev = ud->dev;
- int ch_count, i;
- u32 cap2, cap3;
+ int i;
struct ti_sci_resource_desc *rm_desc;
struct ti_sci_resource *rm_res;
struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
- static const char * const range_names[] = { "ti,sci-rm-range-tchan",
- "ti,sci-rm-range-rchan",
- "ti,sci-rm-range-rflow" };
-
- cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
- cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
-
- ud->rflow_cnt = cap3 & 0x3fff;
- ud->tchan_cnt = cap2 & 0x1ff;
- ud->echan_cnt = (cap2 >> 9) & 0x1ff;
- ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
- ch_count = ud->tchan_cnt + ud->rchan_cnt;
ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
sizeof(unsigned long), GFP_KERNEL);
@@ -1215,11 +1370,15 @@
bitmap_set(ud->rflow_map_reserved, 0, ud->rchan_cnt);
/* Get resource ranges from tisci */
- for (i = 0; i < RM_RANGE_LAST; i++)
+ for (i = 0; i < RM_RANGE_LAST; i++) {
+ if (i == RM_RANGE_BCHAN || i == RM_RANGE_TFLOW)
+ continue;
+
tisci_rm->rm_ranges[i] =
devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
tisci_rm->tisci_dev_id,
(char *)range_names[i]);
+ }
/* tchan ranges */
rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
@@ -1263,9 +1422,232 @@
rm_desc = &rm_res->desc[i];
bitmap_clear(ud->rflow_map, rm_desc->start,
rm_desc->num);
+ }
+ }
+
+ return 0;
+}
+
+static int bcdma_setup_resources(struct udma_dev *ud)
+{
+ int i;
+ struct udevice *dev = ud->dev;
+ struct ti_sci_resource_desc *rm_desc;
+ struct ti_sci_resource *rm_res;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
+ ud->bchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->bchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->bchans = devm_kcalloc(dev, ud->bchan_cnt, sizeof(*ud->bchans),
+ GFP_KERNEL);
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ GFP_KERNEL);
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ /* BCDMA do not really have flows, but the driver expect it */
+ ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long),
+ GFP_KERNEL);
+ ud->rflows = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rflows),
+ GFP_KERNEL);
+
+ if (!ud->bchan_map || !ud->tchan_map || !ud->rchan_map ||
+ !ud->rflow_in_use || !ud->bchans || !ud->tchans || !ud->rchans ||
+ !ud->rflows)
+ return -ENOMEM;
+
+ /* Get resource ranges from tisci */
+ for (i = 0; i < RM_RANGE_LAST; i++) {
+ if (i == RM_RANGE_RFLOW || i == RM_RANGE_TFLOW)
+ continue;
+
+ tisci_rm->rm_ranges[i] =
+ devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
+ tisci_rm->tisci_dev_id,
+ (char *)range_names[i]);
+ }
+
+ /* bchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_BCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->bchan_map, ud->bchan_cnt);
+ } else {
+ bitmap_fill(ud->bchan_map, ud->bchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->bchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: bchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* tchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
+ } else {
+ bitmap_fill(ud->tchan_map, ud->tchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->tchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: tchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* rchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+ } else {
+ bitmap_fill(ud->rchan_map, ud->rchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->rchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: rchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ return 0;
+}
+
+static int pktdma_setup_resources(struct udma_dev *ud)
+{
+ int i;
+ struct udevice *dev = ud->dev;
+ struct ti_sci_resource *rm_res;
+ struct ti_sci_resource_desc *rm_desc;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+
+ ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
+ GFP_KERNEL);
+ ud->rchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->rchan_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+ ud->rchans = devm_kcalloc(dev, ud->rchan_cnt, sizeof(*ud->rchans),
+ GFP_KERNEL);
+ ud->rflow_in_use = devm_kcalloc(dev, BITS_TO_LONGS(ud->rflow_cnt),
+ sizeof(unsigned long),
+ GFP_KERNEL);
+ ud->rflows = devm_kcalloc(dev, ud->rflow_cnt, sizeof(*ud->rflows),
+ GFP_KERNEL);
+ ud->tflow_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tflow_cnt),
+ sizeof(unsigned long), GFP_KERNEL);
+
+ if (!ud->tchan_map || !ud->rchan_map || !ud->tflow_map || !ud->tchans ||
+ !ud->rchans || !ud->rflows || !ud->rflow_in_use)
+ return -ENOMEM;
+
+ /* Get resource ranges from tisci */
+ for (i = 0; i < RM_RANGE_LAST; i++) {
+ if (i == RM_RANGE_BCHAN)
+ continue;
+
+ tisci_rm->rm_ranges[i] =
+ devm_ti_sci_get_of_resource(tisci_rm->tisci, dev,
+ tisci_rm->tisci_dev_id,
+ (char *)range_names[i]);
+ }
+
+ /* tchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_TCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->tchan_map, ud->tchan_cnt);
+ } else {
+ bitmap_fill(ud->tchan_map, ud->tchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->tchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: tchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* rchan ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_RCHAN];
+ if (IS_ERR(rm_res)) {
+ bitmap_zero(ud->rchan_map, ud->rchan_cnt);
+ } else {
+ bitmap_fill(ud->rchan_map, ud->rchan_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->rchan_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: rchan: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* rflow ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_RFLOW];
+ if (IS_ERR(rm_res)) {
+ /* all rflows are assigned exclusively to Linux */
+ bitmap_zero(ud->rflow_in_use, ud->rflow_cnt);
+ } else {
+ bitmap_fill(ud->rflow_in_use, ud->rflow_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->rflow_in_use, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: rflow: %d:%d\n",
+ rm_desc->start, rm_desc->num);
+ }
+ }
+
+ /* tflow ranges */
+ rm_res = tisci_rm->rm_ranges[RM_RANGE_TFLOW];
+ if (IS_ERR(rm_res)) {
+ /* all tflows are assigned exclusively to Linux */
+ bitmap_zero(ud->tflow_map, ud->tflow_cnt);
+ } else {
+ bitmap_fill(ud->tflow_map, ud->tflow_cnt);
+ for (i = 0; i < rm_res->sets; i++) {
+ rm_desc = &rm_res->desc[i];
+ bitmap_clear(ud->tflow_map, rm_desc->start,
+ rm_desc->num);
+ dev_dbg(dev, "ti-sci-res: tflow: %d:%d\n",
+ rm_desc->start, rm_desc->num);
}
}
+ return 0;
+}
+
+static int setup_resources(struct udma_dev *ud)
+{
+ struct udevice *dev = ud->dev;
+ int ch_count, ret;
+
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ret = udma_setup_resources(ud);
+ break;
+ case DMA_TYPE_BCDMA:
+ ret = bcdma_setup_resources(ud);
+ break;
+ case DMA_TYPE_PKTDMA:
+ ret = pktdma_setup_resources(ud);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (ret)
+ return ret;
+
+ ch_count = ud->bchan_cnt + ud->tchan_cnt + ud->rchan_cnt;
+ if (ud->bchan_cnt)
+ ch_count -= bitmap_weight(ud->bchan_map, ud->bchan_cnt);
ch_count -= bitmap_weight(ud->tchan_map, ud->tchan_cnt);
ch_count -= bitmap_weight(ud->rchan_map, ud->rchan_cnt);
if (!ch_count)
@@ -1276,13 +1658,45 @@
if (!ud->channels)
return -ENOMEM;
- dev_info(dev,
- "Channels: %d (tchan: %u, echan: %u, rchan: %u, rflow: %u)\n",
- ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
- ud->rflow_cnt);
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ dev_dbg(dev,
+ "Channels: %d (tchan: %u, rchan: %u, gp-rflow: %u)\n",
+ ch_count,
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt),
+ ud->rflow_cnt - bitmap_weight(ud->rflow_map,
+ ud->rflow_cnt));
+ break;
+ case DMA_TYPE_BCDMA:
+ dev_dbg(dev,
+ "Channels: %d (bchan: %u, tchan: %u, rchan: %u)\n",
+ ch_count,
+ ud->bchan_cnt - bitmap_weight(ud->bchan_map,
+ ud->bchan_cnt),
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt));
+ break;
+ case DMA_TYPE_PKTDMA:
+ dev_dbg(dev,
+ "Channels: %d (tchan: %u, rchan: %u)\n",
+ ch_count,
+ ud->tchan_cnt - bitmap_weight(ud->tchan_map,
+ ud->tchan_cnt),
+ ud->rchan_cnt - bitmap_weight(ud->rchan_map,
+ ud->rchan_cnt));
+ break;
+ default:
+ break;
+ }
return ch_count;
}
+
static int udma_probe(struct udevice *dev)
{
struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
@@ -1294,17 +1708,11 @@
ofnode navss_ofnode = ofnode_get_parent(dev_ofnode(dev));
+ ud->match_data = (void *)dev_get_driver_data(dev);
ret = udma_get_mmrs(dev);
if (ret)
return ret;
- ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
- "ti,ringacc", &tmp);
- ud->ringacc = dev_get_priv(tmp);
- if (IS_ERR(ud->ringacc))
- return PTR_ERR(ud->ringacc);
-
- ud->match_data = (void *)dev_get_driver_data(dev);
ud->psil_base = ud->match_data->psil_base;
ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
@@ -1335,21 +1743,46 @@
tisci_rm->tisci_udmap_ops = &tisci_rm->tisci->ops.rm_udmap_ops;
tisci_rm->tisci_psil_ops = &tisci_rm->tisci->ops.rm_psil_ops;
+ if (ud->match_data->type == DMA_TYPE_UDMA) {
+ ret = uclass_get_device_by_phandle(UCLASS_MISC, dev,
+ "ti,ringacc", &tmp);
+ ud->ringacc = dev_get_priv(tmp);
+ } else {
+ struct k3_ringacc_init_data ring_init_data;
+
+ ring_init_data.tisci = ud->tisci_rm.tisci;
+ ring_init_data.tisci_dev_id = ud->tisci_rm.tisci_dev_id;
+ if (ud->match_data->type == DMA_TYPE_BCDMA) {
+ ring_init_data.num_rings = ud->bchan_cnt +
+ ud->tchan_cnt +
+ ud->rchan_cnt;
+ } else {
+ ring_init_data.num_rings = ud->rflow_cnt +
+ ud->tflow_cnt;
+ }
+
+ ud->ringacc = k3_ringacc_dmarings_init(dev, &ring_init_data);
+ }
+ if (IS_ERR(ud->ringacc))
+ return PTR_ERR(ud->ringacc);
+
ud->dev = dev;
- ud->ch_count = udma_setup_resources(ud);
+ ud->ch_count = setup_resources(ud);
if (ud->ch_count <= 0)
return ud->ch_count;
- dev_info(dev,
- "Number of channels: %u (tchan: %u, echan: %u, rchan: %u dev-id %u)\n",
- ud->ch_count, ud->tchan_cnt, ud->echan_cnt, ud->rchan_cnt,
- tisci_rm->tisci_dev_id);
- dev_info(dev, "Number of rflows: %u\n", ud->rflow_cnt);
+ for (i = 0; i < ud->bchan_cnt; i++) {
+ struct udma_bchan *bchan = &ud->bchans[i];
+
+ bchan->id = i;
+ bchan->reg_rt = ud->mmrs[MMR_BCHANRT] + i * 0x1000;
+ }
for (i = 0; i < ud->tchan_cnt; i++) {
struct udma_tchan *tchan = &ud->tchans[i];
tchan->id = i;
+ tchan->reg_chan = ud->mmrs[MMR_TCHAN] + UDMA_CH_100(i);
tchan->reg_rt = ud->mmrs[MMR_TCHANRT] + UDMA_CH_1000(i);
}
@@ -1357,6 +1790,7 @@
struct udma_rchan *rchan = &ud->rchans[i];
rchan->id = i;
+ rchan->reg_chan = ud->mmrs[MMR_RCHAN] + UDMA_CH_100(i);
rchan->reg_rt = ud->mmrs[MMR_RCHANRT] + UDMA_CH_1000(i);
}
@@ -1364,6 +1798,7 @@
struct udma_rflow *rflow = &ud->rflows[i];
rflow->id = i;
+ rflow->reg_rflow = ud->mmrs[MMR_RFLOW] + UDMA_CH_40(i);
}
for (i = 0; i < ud->ch_count; i++) {
@@ -1372,15 +1807,19 @@
uc->ud = ud;
uc->id = i;
uc->config.remote_thread_id = -1;
+ uc->bchan = NULL;
uc->tchan = NULL;
uc->rchan = NULL;
+ uc->config.mapped_channel_id = -1;
+ uc->config.default_flow_id = -1;
uc->config.dir = DMA_MEM_TO_MEM;
sprintf(uc->name, "UDMA chan%d\n", i);
if (!i)
uc->in_use = true;
}
- pr_debug("UDMA(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+ pr_debug("%s(rev: 0x%08x) CAP0-3: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+ dev->name,
udma_read(ud->mmrs[MMR_GCFG], 0),
udma_read(ud->mmrs[MMR_GCFG], 0x20),
udma_read(ud->mmrs[MMR_GCFG], 0x24),
@@ -1494,8 +1933,381 @@
udma_push_to_ring(uc->tchan->t_ring, tr_desc);
return 0;
+}
+
+#define TISCI_BCDMA_BCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID)
+
+#define TISCI_BCDMA_TCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID)
+
+#define TISCI_BCDMA_RCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID)
+
+#define TISCI_UDMA_TCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
+
+#define TISCI_UDMA_RCHAN_VALID_PARAMS ( \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID | \
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID)
+
+static int bcdma_tisci_m2m_channel_config(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
+ struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
+ struct udma_bchan *bchan = uc->bchan;
+ int ret = 0;
+
+ req_tx.valid_params = TISCI_BCDMA_BCHAN_VALID_PARAMS;
+ req_tx.nav_id = tisci_rm->tisci_dev_id;
+ req_tx.extended_ch_type = TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN;
+ req_tx.index = bchan->id;
+
+ ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
+ if (ret)
+ dev_err(ud->dev, "bchan%d cfg failed %d\n", bchan->id, ret);
+
+ return ret;
+}
+
+static struct udma_bchan *__bcdma_reserve_bchan(struct udma_dev *ud, int id)
+{
+ if (id >= 0) {
+ if (test_bit(id, ud->bchan_map)) {
+ dev_err(ud->dev, "bchan%d is in use\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+ } else {
+ id = find_next_zero_bit(ud->bchan_map, ud->bchan_cnt, 0);
+ if (id == ud->bchan_cnt)
+ return ERR_PTR(-ENOENT);
+ }
+ __set_bit(id, ud->bchan_map);
+ return &ud->bchans[id];
+}
+
+static int bcdma_get_bchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->bchan) {
+ dev_err(ud->dev, "chan%d: already have bchan%d allocated\n",
+ uc->id, uc->bchan->id);
+ return 0;
+ }
+
+ uc->bchan = __bcdma_reserve_bchan(ud, -1);
+ if (IS_ERR(uc->bchan))
+ return PTR_ERR(uc->bchan);
+
+ uc->tchan = uc->bchan;
+
+ return 0;
+}
+
+static void bcdma_put_bchan(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+
+ if (uc->bchan) {
+ dev_dbg(ud->dev, "chan%d: put bchan%d\n", uc->id,
+ uc->bchan->id);
+ __clear_bit(uc->bchan->id, ud->bchan_map);
+ uc->bchan = NULL;
+ uc->tchan = NULL;
+ }
+}
+
+static void bcdma_free_bchan_resources(struct udma_chan *uc)
+{
+ if (!uc->bchan)
+ return;
+
+ k3_nav_ringacc_ring_free(uc->bchan->tc_ring);
+ k3_nav_ringacc_ring_free(uc->bchan->t_ring);
+ uc->bchan->tc_ring = NULL;
+ uc->bchan->t_ring = NULL;
+
+ bcdma_put_bchan(uc);
+}
+
+static int bcdma_alloc_bchan_resources(struct udma_chan *uc)
+{
+ struct k3_nav_ring_cfg ring_cfg;
+ struct udma_dev *ud = uc->ud;
+ int ret;
+
+ ret = bcdma_get_bchan(uc);
+ if (ret)
+ return ret;
+
+ ret = k3_nav_ringacc_request_rings_pair(ud->ringacc, uc->bchan->id, -1,
+ &uc->bchan->t_ring,
+ &uc->bchan->tc_ring);
+ if (ret) {
+ ret = -EBUSY;
+ goto err_ring;
+ }
+
+ memset(&ring_cfg, 0, sizeof(ring_cfg));
+ ring_cfg.size = 16;
+ ring_cfg.elm_size = K3_NAV_RINGACC_RING_ELSIZE_8;
+ ring_cfg.mode = K3_NAV_RINGACC_RING_MODE_RING;
+
+ ret = k3_nav_ringacc_ring_cfg(uc->bchan->t_ring, &ring_cfg);
+ if (ret)
+ goto err_ringcfg;
+
+ return 0;
+
+err_ringcfg:
+ k3_nav_ringacc_ring_free(uc->bchan->tc_ring);
+ uc->bchan->tc_ring = NULL;
+ k3_nav_ringacc_ring_free(uc->bchan->t_ring);
+ uc->bchan->t_ring = NULL;
+err_ring:
+ bcdma_put_bchan(uc);
+
+ return ret;
+}
+
+static int bcdma_tisci_tx_channel_config(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
+ struct udma_tchan *tchan = uc->tchan;
+ struct ti_sci_msg_rm_udmap_tx_ch_cfg req_tx = { 0 };
+ int ret = 0;
+
+ req_tx.valid_params = TISCI_BCDMA_TCHAN_VALID_PARAMS;
+ req_tx.nav_id = tisci_rm->tisci_dev_id;
+ req_tx.index = tchan->id;
+ req_tx.tx_supr_tdpkt = uc->config.notdpkt;
+ if (uc->config.ep_type == PSIL_EP_PDMA_XY &&
+ ud->match_data->flags & UDMA_FLAG_TDTYPE) {
+ /* wait for peer to complete the teardown for PDMAs */
+ req_tx.valid_params |=
+ TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID;
+ req_tx.tx_tdtype = 1;
+ }
+
+ ret = tisci_ops->tx_ch_cfg(tisci_rm->tisci, &req_tx);
+ if (ret)
+ dev_err(ud->dev, "tchan%d cfg failed %d\n", tchan->id, ret);
+
+ return ret;
+}
+
+#define pktdma_tisci_tx_channel_config bcdma_tisci_tx_channel_config
+
+static int pktdma_tisci_rx_channel_config(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ struct udma_tisci_rm *tisci_rm = &ud->tisci_rm;
+ const struct ti_sci_rm_udmap_ops *tisci_ops = tisci_rm->tisci_udmap_ops;
+ struct ti_sci_msg_rm_udmap_rx_ch_cfg req_rx = { 0 };
+ struct ti_sci_msg_rm_udmap_flow_cfg flow_req = { 0 };
+ int ret = 0;
+
+ req_rx.valid_params = TISCI_BCDMA_RCHAN_VALID_PARAMS;
+ req_rx.nav_id = tisci_rm->tisci_dev_id;
+ req_rx.index = uc->rchan->id;
+
+ ret = tisci_ops->rx_ch_cfg(tisci_rm->tisci, &req_rx);
+ if (ret) {
+ dev_err(ud->dev, "rchan%d cfg failed %d\n", uc->rchan->id, ret);
+ return ret;
+ }
+
+ flow_req.valid_params =
+ TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID |
+ TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID |
+ TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID;
+
+ flow_req.nav_id = tisci_rm->tisci_dev_id;
+ flow_req.flow_index = uc->rflow->id;
+
+ if (uc->config.needs_epib)
+ flow_req.rx_einfo_present = 1;
+ else
+ flow_req.rx_einfo_present = 0;
+ if (uc->config.psd_size)
+ flow_req.rx_psinfo_present = 1;
+ else
+ flow_req.rx_psinfo_present = 0;
+ flow_req.rx_error_handling = 1;
+
+ ret = tisci_ops->rx_flow_cfg(tisci_rm->tisci, &flow_req);
+
+ if (ret)
+ dev_err(ud->dev, "flow%d config failed: %d\n", uc->rflow->id,
+ ret);
+
+ return ret;
+}
+
+static int bcdma_alloc_chan_resources(struct udma_chan *uc)
+{
+ int ret;
+
+ uc->config.pkt_mode = false;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_MEM:
+ /* Non synchronized - mem to mem type of transfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-MEM\n", __func__,
+ uc->id);
+
+ ret = bcdma_alloc_bchan_resources(uc);
+ if (ret)
+ return ret;
+
+ ret = bcdma_tisci_m2m_channel_config(uc);
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(uc->ud->dev, "chan%d: is running!\n", uc->id);
+ udma_stop(uc);
+ if (udma_is_chan_running(uc)) {
+ dev_err(uc->ud->dev, "chan%d: won't stop!\n", uc->id);
+ goto err_res_free;
+ }
+ }
+
+ udma_reset_rings(uc);
+
+ return 0;
+
+err_res_free:
+ bcdma_free_bchan_resources(uc);
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ return ret;
}
+static int pktdma_alloc_chan_resources(struct udma_chan *uc)
+{
+ struct udma_dev *ud = uc->ud;
+ int ret;
+
+ switch (uc->config.dir) {
+ case DMA_MEM_TO_DEV:
+ /* Slave transfer synchronized - mem to dev (TX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as MEM-to-DEV\n", __func__,
+ uc->id);
+
+ ret = udma_alloc_tx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = ud->psil_base + uc->tchan->id;
+ uc->config.dst_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread |= K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ ret = pktdma_tisci_tx_channel_config(uc);
+ break;
+ case DMA_DEV_TO_MEM:
+ /* Slave transfer synchronized - dev to mem (RX) trasnfer */
+ dev_dbg(uc->ud->dev, "%s: chan%d as DEV-to-MEM\n", __func__,
+ uc->id);
+
+ ret = udma_alloc_rx_resources(uc);
+ if (ret) {
+ uc->config.remote_thread_id = -1;
+ return ret;
+ }
+
+ uc->config.src_thread = uc->config.remote_thread_id;
+ uc->config.dst_thread = (ud->psil_base + uc->rchan->id) |
+ K3_PSIL_DST_THREAD_ID_OFFSET;
+
+ ret = pktdma_tisci_rx_channel_config(uc);
+ break;
+ default:
+ /* Can not happen */
+ dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
+ __func__, uc->id, uc->config.dir);
+ return -EINVAL;
+ }
+
+ /* check if the channel configuration was successful */
+ if (ret)
+ goto err_res_free;
+
+ /* PSI-L pairing */
+ ret = udma_navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
+ if (ret) {
+ dev_err(ud->dev, "PSI-L pairing failed: 0x%04x -> 0x%04x\n",
+ uc->config.src_thread, uc->config.dst_thread);
+ goto err_res_free;
+ }
+
+ if (udma_is_chan_running(uc)) {
+ dev_warn(ud->dev, "chan%d: is running!\n", uc->id);
+ udma_stop(uc);
+ if (udma_is_chan_running(uc)) {
+ dev_err(ud->dev, "chan%d: won't stop!\n", uc->id);
+ goto err_res_free;
+ }
+ }
+
+ udma_reset_rings(uc);
+
+ if (uc->tchan)
+ dev_dbg(ud->dev,
+ "chan%d: tchan%d, tflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->tchan->id, uc->tchan->tflow_id,
+ uc->config.remote_thread_id);
+ else if (uc->rchan)
+ dev_dbg(ud->dev,
+ "chan%d: rchan%d, rflow%d, Remote thread: 0x%04x\n",
+ uc->id, uc->rchan->id, uc->rflow->id,
+ uc->config.remote_thread_id);
+ return 0;
+
+err_res_free:
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+
+ udma_reset_uchan(uc);
+
+ return ret;
+}
+
static int udma_transfer(struct udevice *dev, int direction,
void *dst, void *src, size_t len)
{
@@ -1505,7 +2317,16 @@
dma_addr_t paddr = 0;
int ret;
- ret = udma_alloc_chan_resources(uc);
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ret = udma_alloc_chan_resources(uc);
+ break;
+ case DMA_TYPE_BCDMA:
+ ret = bcdma_alloc_chan_resources(uc);
+ break;
+ default:
+ return -EINVAL;
+ };
if (ret)
return ret;
@@ -1514,7 +2335,17 @@
udma_poll_completion(uc, &paddr);
udma_stop(uc);
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ udma_free_chan_resources(uc);
+ break;
+ case DMA_TYPE_BCDMA:
+ bcdma_free_bchan_resources(uc);
+ break;
+ default:
+ return -EINVAL;
+ };
+
- udma_free_chan_resources(uc);
return 0;
}
@@ -1533,7 +2364,19 @@
uc = &ud->channels[dma->id];
ucc = &uc->config;
- ret = udma_alloc_chan_resources(uc);
+ switch (ud->match_data->type) {
+ case DMA_TYPE_UDMA:
+ ret = udma_alloc_chan_resources(uc);
+ break;
+ case DMA_TYPE_BCDMA:
+ ret = bcdma_alloc_chan_resources(uc);
+ break;
+ case DMA_TYPE_PKTDMA:
+ ret = pktdma_alloc_chan_resources(uc);
+ break;
+ default:
+ return -EINVAL;
+ }
if (ret) {
dev_err(dma->dev, "alloc dma res failed %d\n", ret);
return -EINVAL;
@@ -1573,7 +2416,14 @@
if (udma_is_chan_running(uc))
udma_stop(uc);
- udma_free_chan_resources(uc);
+
+ udma_navss_psil_unpair(ud, uc->config.src_thread,
+ uc->config.dst_thread);
+
+ bcdma_free_bchan_resources(uc);
+ udma_free_tx_resources(uc);
+ udma_free_rx_resources(uc);
+ udma_reset_uchan(uc);
uc->in_use = false;
@@ -1764,6 +2614,15 @@
ucc->notdpkt = ep_config->notdpkt;
ucc->ep_type = ep_config->ep_type;
+ if (ud->match_data->type == DMA_TYPE_PKTDMA &&
+ ep_config->mapped_channel_id >= 0) {
+ ucc->mapped_channel_id = ep_config->mapped_channel_id;
+ ucc->default_flow_id = ep_config->default_flow_id;
+ } else {
+ ucc->mapped_channel_id = -1;
+ ucc->default_flow_id = -1;
+ }
+
ucc->needs_epib = ep_config->needs_epib;
ucc->psd_size = ep_config->psd_size;
ucc->metadata_size = (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + ucc->psd_size;
@@ -1859,10 +2718,13 @@
};
static struct udma_match_data am654_main_data = {
+ .type = DMA_TYPE_UDMA,
.psil_base = 0x1000,
.enable_memcpy_support = true,
.statictr_z_mask = GENMASK(11, 0),
- .rchan_oes_offset = 0x200,
+ .oes = {
+ .udma_rchan = 0x200,
+ },
.tpl_levels = 2,
.level_start_idx = {
[0] = 8, /* Normal channels */
@@ -1871,10 +2733,13 @@
};
static struct udma_match_data am654_mcu_data = {
+ .type = DMA_TYPE_UDMA,
.psil_base = 0x6000,
.enable_memcpy_support = true,
.statictr_z_mask = GENMASK(11, 0),
- .rchan_oes_offset = 0x200,
+ .oes = {
+ .udma_rchan = 0x200,
+ },
.tpl_levels = 2,
.level_start_idx = {
[0] = 2, /* Normal channels */
@@ -1883,11 +2748,14 @@
};
static struct udma_match_data j721e_main_data = {
+ .type = DMA_TYPE_UDMA,
.psil_base = 0x1000,
.enable_memcpy_support = true,
.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
.statictr_z_mask = GENMASK(23, 0),
- .rchan_oes_offset = 0x400,
+ .oes = {
+ .udma_rchan = 0x400,
+ },
.tpl_levels = 3,
.level_start_idx = {
[0] = 16, /* Normal channels */
@@ -1897,16 +2765,49 @@
};
static struct udma_match_data j721e_mcu_data = {
+ .type = DMA_TYPE_UDMA,
.psil_base = 0x6000,
.enable_memcpy_support = true,
.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
.statictr_z_mask = GENMASK(23, 0),
- .rchan_oes_offset = 0x400,
+ .oes = {
+ .udma_rchan = 0x400,
+ },
.tpl_levels = 2,
.level_start_idx = {
[0] = 2, /* Normal channels */
[1] = 0, /* High Throughput channels */
},
+};
+
+static struct udma_match_data am64_bcdma_data = {
+ .type = DMA_TYPE_BCDMA,
+ .psil_base = 0x2000, /* for tchan and rchan, not applicable to bchan */
+ .enable_memcpy_support = true, /* Supported via bchan */
+ .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
+ .statictr_z_mask = GENMASK(23, 0),
+ .oes = {
+ .bcdma_bchan_data = 0x2200,
+ .bcdma_bchan_ring = 0x2400,
+ .bcdma_tchan_data = 0x2800,
+ .bcdma_tchan_ring = 0x2a00,
+ .bcdma_rchan_data = 0x2e00,
+ .bcdma_rchan_ring = 0x3000,
+ },
+ /* No throughput levels */
+};
+
+static struct udma_match_data am64_pktdma_data = {
+ .type = DMA_TYPE_PKTDMA,
+ .psil_base = 0x1000,
+ .enable_memcpy_support = false,
+ .flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST | UDMA_FLAG_TDTYPE,
+ .statictr_z_mask = GENMASK(23, 0),
+ .oes = {
+ .pktdma_tchan_flow = 0x1200,
+ .pktdma_rchan_flow = 0x1600,
+ },
+ /* No throughput levels */
};
static const struct udevice_id udma_ids[] = {
@@ -1924,6 +2825,14 @@
.compatible = "ti,j721e-navss-mcu-udmap",
.data = (ulong)&j721e_mcu_data,
},
+ {
+ .compatible = "ti,am64-dmss-bcdma",
+ .data = (ulong)&am64_bcdma_data,
+ },
+ {
+ .compatible = "ti,am64-dmss-pktdma",
+ .data = (ulong)&am64_pktdma_data,
+ },
{ /* Sentinel */ },
};
diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c
index be57552..89cb7d8 100644
--- a/drivers/firmware/psci.c
+++ b/drivers/firmware/psci.c
@@ -42,7 +42,7 @@
#if CONFIG_IS_ENABLED(EFI_LOADER)
int __efi_runtime_data psci_method;
#else
-int psci_method __attribute__ ((section(".data")));
+int psci_method __section(".data");
#endif
unsigned long __efi_runtime invoke_psci_fn
@@ -66,7 +66,7 @@
return res.a0;
}
-static int psci_features(u32 psci_func_id)
+static int request_psci_features(u32 psci_func_id)
{
return invoke_psci_fn(PSCI_1_0_FN_PSCI_FEATURES,
psci_func_id, 0, 0);
@@ -85,7 +85,8 @@
ver = psci_0_2_get_version();
if (PSCI_VERSION_MAJOR(ver) >= 1) {
- ret = psci_features(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2));
+ ret = request_psci_features(PSCI_FN_NATIVE(1_1,
+ SYSTEM_RESET2));
if (ret != PSCI_RET_NOT_SUPPORTED)
return true;
diff --git a/drivers/firmware/scmi/smt.c b/drivers/firmware/scmi/smt.c
index f1915c0..e60c2ae 100644
--- a/drivers/firmware/scmi/smt.c
+++ b/drivers/firmware/scmi/smt.c
@@ -30,8 +30,6 @@
int ret;
struct ofnode_phandle_args args;
struct resource resource;
- fdt32_t faddr;
- phys_addr_t paddr;
ret = dev_read_phandle_with_args(dev, "shmem", NULL, 0, 0, &args);
if (ret)
@@ -41,21 +39,13 @@
if (ret)
return ret;
- /* TEMP workaround for ofnode_read_resource translation issue */
- if (of_live_active()) {
- paddr = resource.start;
- } else {
- faddr = cpu_to_fdt32(resource.start);
- paddr = ofnode_translate_address(args.node, &faddr);
- }
-
smt->size = resource_size(&resource);
if (smt->size < sizeof(struct scmi_smt_header)) {
dev_err(dev, "Shared memory buffer too small\n");
return -EINVAL;
}
- smt->buf = devm_ioremap(dev, paddr, smt->size);
+ smt->buf = devm_ioremap(dev, resource.start, smt->size);
if (!smt->buf)
return -ENOMEM;
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index 0cdfb0e..0b6ba35 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -23,6 +23,7 @@
#include <linux/soc/ti/ti_sci_protocol.h>
#include "ti_sci.h"
+#include "ti_sci_static_data.h"
/* List of all TI SCI devices active in system */
static LIST_HEAD(ti_sci_list);
@@ -1588,6 +1589,7 @@
dev_err(info->dev, "Message alloc failed(%d)\n", ret);
return ret;
}
+ req.domain = 0;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
@@ -1667,6 +1669,34 @@
return ret;
}
+static int __maybe_unused
+ti_sci_cmd_get_resource_range_static(const struct ti_sci_handle *handle,
+ u32 dev_id, u8 subtype,
+ u16 *range_start, u16 *range_num)
+{
+ struct ti_sci_resource_static_data *data;
+ int i = 0;
+
+ while (1) {
+ data = &rm_static_data[i];
+
+ if (!data->dev_id)
+ return -EINVAL;
+
+ if (data->dev_id != dev_id || data->subtype != subtype) {
+ i++;
+ continue;
+ }
+
+ *range_start = data->range_start;
+ *range_num = data->range_num;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
/**
* ti_sci_cmd_get_resource_range - Get a range of resources assigned to host
* that is same as ti sci interface host.
@@ -2466,6 +2496,9 @@
req.tx_orderid = params->tx_orderid;
req.fdepth = params->fdepth;
req.tx_sched_priority = params->tx_sched_priority;
+ req.tx_burst_size = params->tx_burst_size;
+ req.tx_tdtype = params->tx_tdtype;
+ req.extended_ch_type = params->extended_ch_type;
ret = ti_sci_do_xfer(info, xfer);
if (ret) {
@@ -3012,6 +3045,58 @@
return ret;
}
+/**
+ * ti_sci_dm_probe() - Basic probe for DM to TIFS SCI
+ * @dev: corresponding system controller interface device
+ *
+ * Return: 0 if all goes good, else appropriate error message.
+ */
+static __maybe_unused int ti_sci_dm_probe(struct udevice *dev)
+{
+ struct ti_sci_rm_core_ops *rm_core_ops;
+ struct ti_sci_rm_udmap_ops *udmap_ops;
+ struct ti_sci_rm_ringacc_ops *rops;
+ struct ti_sci_rm_psil_ops *psilops;
+ struct ti_sci_ops *ops;
+ struct ti_sci_info *info;
+ int ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ info = dev_get_priv(dev);
+ info->desc = (void *)dev_get_driver_data(dev);
+
+ ret = ti_sci_of_to_info(dev, info);
+ if (ret) {
+ dev_err(dev, "%s: Probe failed with error %d\n", __func__, ret);
+ return ret;
+ }
+
+ info->dev = dev;
+ info->seq = 0xA;
+
+ list_add_tail(&info->list, &ti_sci_list);
+
+ ops = &info->handle.ops;
+
+ rm_core_ops = &ops->rm_core_ops;
+ rm_core_ops->get_range = ti_sci_cmd_get_resource_range_static;
+
+ rops = &ops->rm_ring_ops;
+ rops->config = ti_sci_cmd_ring_config;
+
+ psilops = &ops->rm_psil_ops;
+ psilops->pair = ti_sci_cmd_rm_psil_pair;
+ psilops->unpair = ti_sci_cmd_rm_psil_unpair;
+
+ udmap_ops = &ops->rm_udmap_ops;
+ udmap_ops->tx_ch_cfg = ti_sci_cmd_rm_udmap_tx_ch_cfg;
+ udmap_ops->rx_ch_cfg = ti_sci_cmd_rm_udmap_rx_ch_cfg;
+ udmap_ops->rx_flow_cfg = ti_sci_cmd_rm_udmap_rx_flow_cfg;
+
+ return ret;
+}
+
/*
* ti_sci_get_free_resource() - Get a free resource from TISCI resource.
* @res: Pointer to the TISCI resource
@@ -3149,6 +3234,14 @@
.max_msg_size = 60,
};
+/* Description for J721e DM to DMSC communication */
+static const struct ti_sci_desc ti_sci_dm_j721e_desc = {
+ .default_host_id = 3,
+ .max_rx_timeout_ms = 10000,
+ .max_msgs = 20,
+ .max_msg_size = 60,
+};
+
static const struct udevice_id ti_sci_ids[] = {
{
.compatible = "ti,k2g-sci",
@@ -3161,6 +3254,14 @@
{ /* Sentinel */ },
};
+static __maybe_unused const struct udevice_id ti_sci_dm_ids[] = {
+ {
+ .compatible = "ti,j721e-dm-sci",
+ .data = (ulong)&ti_sci_dm_j721e_desc
+ },
+ { /* Sentinel */ },
+};
+
U_BOOT_DRIVER(ti_sci) = {
.name = "ti_sci",
.id = UCLASS_FIRMWARE,
@@ -3168,3 +3269,13 @@
.probe = ti_sci_probe,
.priv_auto = sizeof(struct ti_sci_info),
};
+
+#if IS_ENABLED(CONFIG_K3_DM_FW)
+U_BOOT_DRIVER(ti_sci_dm) = {
+ .name = "ti_sci_dm",
+ .id = UCLASS_FIRMWARE,
+ .of_match = ti_sci_dm_ids,
+ .probe = ti_sci_dm_probe,
+ .priv_auto = sizeof(struct ti_sci_info),
+};
+#endif
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 327bb82..e4a087c 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -137,12 +137,14 @@
/**
* struct ti_sci_msg_req_reboot - Reboot the SoC
* @hdr: Generic Header
+ * @domain: Domain to be reset, 0 for full SoC reboot.
*
* Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
* ACK/NACK message.
*/
struct ti_sci_msg_req_reboot {
struct ti_sci_msg_hdr hdr;
+ u8 domain;
} __packed;
/**
@@ -998,6 +1000,9 @@
* 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
* 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
* 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
+ * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
+ * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
+ * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
*
* @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
*
@@ -1058,6 +1063,18 @@
* @tx_sched_priority: UDMAP transmit channel tx scheduling priority
* configuration to be programmed into the priority field of the channel's
* TCHAN_TST_SCHED register.
+ *
+ * @tx_burst_size: UDMAP transmit channel burst size configuration to be
+ * programmed into the tx_burst_size field of the TCHAN_TCFG register.
+ *
+ * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
+ * programmed into the tdtype field of the TCHAN_TCFG register:
+ * 0 - Return immediately
+ * 1 - Wait for completion message from remote peer
+ *
+ * @extended_ch_type: Valid for BCDMA.
+ * 0 - the channel is split tx channel (tchan)
+ * 1 - the channel is block copy channel (bchan)
*/
struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
struct ti_sci_msg_hdr hdr;
@@ -1078,6 +1095,9 @@
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
+ u8 tx_burst_size;
+ u8 tx_tdtype;
+ u8 extended_ch_type;
} __packed;
/**
diff --git a/drivers/firmware/ti_sci_static_data.h b/drivers/firmware/ti_sci_static_data.h
new file mode 100644
index 0000000..3c506e6
--- /dev/null
+++ b/drivers/firmware/ti_sci_static_data.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ */
+
+#ifndef __TI_SCI_STATIC_DATA_H
+#define __TI_SCI_STATIC_DATA_H
+
+struct ti_sci_resource_static_data {
+ u32 dev_id;
+ u16 range_start;
+ u16 range_num;
+ u8 subtype;
+};
+
+#if IS_ENABLED(CONFIG_K3_DM_FW)
+
+#if IS_ENABLED(CONFIG_TARGET_J721E_R5_EVM)
+static struct ti_sci_resource_static_data rm_static_data[] = {
+ /* Free rings */
+ {
+ .dev_id = 235,
+ .subtype = 1,
+ .range_start = 124,
+ .range_num = 32,
+ },
+ /* TX channels */
+ {
+ .dev_id = 236,
+ .subtype = 13,
+ .range_start = 6,
+ .range_num = 2,
+ },
+ /* RX channels */
+ {
+ .dev_id = 236,
+ .subtype = 10,
+ .range_start = 6,
+ .range_num = 2,
+ },
+ /* RX Free flows */
+ {
+ .dev_id = 236,
+ .subtype = 0,
+ .range_start = 60,
+ .range_num = 8,
+ },
+ { },
+};
+#endif /* CONFIG_TARGET_J721E_R5_EVM */
+
+#if IS_ENABLED(CONFIG_TARGET_J7200_R5_EVM)
+static struct ti_sci_resource_static_data rm_static_data[] = {
+ /* Free rings */
+ {
+ .dev_id = 235,
+ .subtype = 1,
+ .range_start = 144,
+ .range_num = 32,
+ },
+ /* TX channels */
+ {
+ .dev_id = 236,
+ .subtype = 13,
+ .range_start = 7,
+ .range_num = 2,
+ },
+ /* RX channels */
+ {
+ .dev_id = 236,
+ .subtype = 10,
+ .range_start = 7,
+ .range_num = 2,
+ },
+ /* RX Free flows */
+ {
+ .dev_id = 236,
+ .subtype = 0,
+ .range_start = 60,
+ .range_num = 8,
+ },
+ { },
+};
+#endif /* CONFIG_TARGET_J7200_R5_EVM */
+
+#else
+static struct ti_sci_resource_static_data rm_static_data[] = {
+ { },
+};
+#endif /* CONFIG_K3_DM_FW */
+#endif /* __TI_SCI_STATIC_DATA_H */
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index daaac5e..5f1ec39 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -66,9 +66,12 @@
return 0;
}
-static void rcar_gpio_set_direction(void __iomem *regs, unsigned offset,
+static void rcar_gpio_set_direction(struct udevice *dev, unsigned offset,
bool output)
{
+ struct rcar_gpio_priv *priv = dev_get_priv(dev);
+ void __iomem *regs = priv->regs;
+
/*
* follow steps in the GPIO documentation for
* "Setting General Output Mode" and
@@ -90,9 +93,7 @@
static int rcar_gpio_direction_input(struct udevice *dev, unsigned offset)
{
- struct rcar_gpio_priv *priv = dev_get_priv(dev);
-
- rcar_gpio_set_direction(priv->regs, offset, false);
+ rcar_gpio_set_direction(dev, offset, false);
return 0;
}
@@ -100,11 +101,9 @@
static int rcar_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
- struct rcar_gpio_priv *priv = dev_get_priv(dev);
-
/* write GPIO value to output before selecting output mode of pin */
rcar_gpio_set_value(dev, offset, value);
- rcar_gpio_set_direction(priv->regs, offset, true);
+ rcar_gpio_set_direction(dev, offset, true);
return 0;
}
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index e4e7f58..131099c 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -1215,9 +1215,9 @@
{
int ret;
- ret = dev_read_phandle_with_args(dev, list_name, "#gpio-cells", 0, -1,
- NULL);
- if (ret) {
+ ret = dev_count_phandle_with_args(dev, list_name, "#gpio-cells",
+ -ENOENT);
+ if (ret < 0) {
debug("%s: Node '%s', property '%s', GPIO count failed: %d\n",
__func__, dev->name, list_name, ret);
}
diff --git a/drivers/mailbox/k3-sec-proxy.c b/drivers/mailbox/k3-sec-proxy.c
index ff21a08..20fdb09 100644
--- a/drivers/mailbox/k3-sec-proxy.c
+++ b/drivers/mailbox/k3-sec-proxy.c
@@ -409,15 +409,7 @@
return 0;
}
-/*
- * Thread ID #4: ROM request
- * Thread ID #5: ROM response, SYSFW notify
- * Thread ID #6: SYSFW request response
- * Thread ID #7: SYSFW request high priority
- * Thread ID #8: SYSFW request low priority
- * Thread ID #9: SYSFW notify response
- */
-static const u32 am6x_valid_threads[] = { 4, 5, 6, 7, 8, 9, 11, 13 };
+static const u32 am6x_valid_threads[] = { 0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 13, 20, 21, 22, 23 };
static const struct k3_sec_proxy_desc am654_desc = {
.thread_count = 90,
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index f4ad1db..8901456 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -4,6 +4,7 @@
bool "MMC/SD/SDIO card support"
default ARM || PPC || SANDBOX
select HAVE_BLOCK_DEVICE
+ select DM_MMC if DM
help
This selects MultiMediaCard, Secure Digital and Secure
Digital I/O support.
@@ -33,6 +34,7 @@
config DM_MMC
bool "Enable MMC controllers using Driver Model"
depends on DM
+ select BLK
help
This enables the MultiMediaCard (MMC) uclass which supports MMC and
Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 11dcde1..a86d96a 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -470,6 +470,16 @@
.flags = IOMUX_PRESENT,
};
+static const struct am654_driver_data sdhci_am64_8bit_drvdata = {
+ .ops = &am654_sdhci_ops,
+ .flags = DLL_PRESENT | DLL_CALIB,
+};
+
+static const struct am654_driver_data sdhci_am64_4bit_drvdata = {
+ .ops = &j721e_4bit_sdhci_ops,
+ .flags = IOMUX_PRESENT,
+};
+
const struct soc_attr am654_sdhci_soc_attr[] = {
{ .family = "AM65X", .revision = "SR1.0", .data = &am654_sr1_drv_data},
{/* sentinel */}
@@ -651,6 +661,14 @@
.compatible = "ti,j721e-sdhci-4bit",
.data = (ulong)&j721e_4bit_drv_data,
},
+ {
+ .compatible = "ti,am64-sdhci-8bit",
+ .data = (ulong)&sdhci_am64_8bit_drvdata,
+ },
+ {
+ .compatible = "ti,am64-sdhci-4bit",
+ .data = (ulong)&sdhci_am64_4bit_drvdata,
+ },
{ }
};
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 9642d7c..9c27fea 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -2276,12 +2276,12 @@
flash_unlock_seq(info, 0);
flash_write_cmd(info, 0,
info->addr_unlock1,
- FLASH_CMD_READ_ID);
+ AMD_CMD_SET_PPB_ENTRY);
info->protect[sect_cnt] =
- flash_isset(
- info, sect_cnt,
- FLASH_OFFSET_PROTECT,
- FLASH_STATUS_PROTECT);
+ !flash_isset(info, sect_cnt,
+ 0, 0x01);
+ flash_write_cmd(info, 0, 0,
+ info->cmd_reset);
break;
default:
/* default: not protected */
diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c
index e1e5425..2f054b6 100644
--- a/drivers/mtd/nand/raw/mxc_nand_spl.c
+++ b/drivers/mtd/nand/raw/mxc_nand_spl.c
@@ -326,7 +326,7 @@
* configured and available since this code loads the main U-Boot image
* from NAND into SDRAM and starts it from there.
*/
-void nand_boot(void)
+__used void nand_boot(void)
{
__attribute__((noreturn)) void (*uboot)(void);
diff --git a/drivers/net/8390.h b/drivers/net/8390.h
deleted file mode 100644
index f087217..0000000
--- a/drivers/net/8390.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
-
-Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
-
-Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
-eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
-are GPL, so this is, of course, GPL.
-
-*/
-
-/* Generic NS8390 register definitions. */
-/* This file is part of Donald Becker's 8390 drivers, and is distributed
- under the same license. Auto-loading of 8390.o only in v2.2 - Paul G.
- Some of these names and comments originated from the Crynwr
- packet drivers, which are distributed under the GPL. */
-
-#ifndef _8390_h
-#define _8390_h
-
-/* Some generic ethernet register configurations. */
-#define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */
-#define E8390_RX_IRQ_MASK 0x5
-#define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */
-#define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */
-#define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */
-#define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */
-
-/* Register accessed at EN_CMD, the 8390 base addr. */
-#define E8390_STOP 0x01 /* Stop and reset the chip */
-#define E8390_START 0x02 /* Start the chip, clear reset */
-#define E8390_TRANS 0x04 /* Transmit a frame */
-#define E8390_RREAD 0x08 /* Remote read */
-#define E8390_RWRITE 0x10 /* Remote write */
-#define E8390_NODMA 0x20 /* Remote DMA */
-#define E8390_PAGE0 0x00 /* Select page chip registers */
-#define E8390_PAGE1 0x40 /* using the two high-order bits */
-#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
-
-/*
- * Only generate indirect loads given a machine that needs them.
- * - removed AMIGA_PCMCIA from this list, handled as ISA io now
- */
-
-#define n2k_inb(port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)))
-#define n2k_outb(val,port) (*((volatile unsigned char *)(port+CONFIG_DRIVER_NE2000_BASE)) = val)
-
-#define EI_SHIFT(x) (x)
-
-#define E8390_CMD EI_SHIFT(0x00) /* The command register (for all pages) */
-/* Page 0 register offsets. */
-#define EN0_CLDALO EI_SHIFT(0x01) /* Low byte of current local dma addr RD */
-#define EN0_STARTPG EI_SHIFT(0x01) /* Starting page of ring bfr WR */
-#define EN0_CLDAHI EI_SHIFT(0x02) /* High byte of current local dma addr RD */
-#define EN0_STOPPG EI_SHIFT(0x02) /* Ending page +1 of ring bfr WR */
-#define EN0_BOUNDARY EI_SHIFT(0x03) /* Boundary page of ring bfr RD WR */
-#define EN0_TSR EI_SHIFT(0x04) /* Transmit status reg RD */
-#define EN0_TPSR EI_SHIFT(0x04) /* Transmit starting page WR */
-#define EN0_NCR EI_SHIFT(0x05) /* Number of collision reg RD */
-#define EN0_TCNTLO EI_SHIFT(0x05) /* Low byte of tx byte count WR */
-#define EN0_FIFO EI_SHIFT(0x06) /* FIFO RD */
-#define EN0_TCNTHI EI_SHIFT(0x06) /* High byte of tx byte count WR */
-#define EN0_ISR EI_SHIFT(0x07) /* Interrupt status reg RD WR */
-#define EN0_CRDALO EI_SHIFT(0x08) /* low byte of current remote dma address RD */
-#define EN0_RSARLO EI_SHIFT(0x08) /* Remote start address reg 0 */
-#define EN0_CRDAHI EI_SHIFT(0x09) /* high byte, current remote dma address RD */
-#define EN0_RSARHI EI_SHIFT(0x09) /* Remote start address reg 1 */
-#define EN0_RCNTLO EI_SHIFT(0x0a) /* Remote byte count reg WR */
-#define EN0_RCNTHI EI_SHIFT(0x0b) /* Remote byte count reg WR */
-#define EN0_RSR EI_SHIFT(0x0c) /* rx status reg RD */
-#define EN0_RXCR EI_SHIFT(0x0c) /* RX configuration reg WR */
-#define EN0_TXCR EI_SHIFT(0x0d) /* TX configuration reg WR */
-#define EN0_COUNTER0 EI_SHIFT(0x0d) /* Rcv alignment error counter RD */
-#define EN0_DCFG EI_SHIFT(0x0e) /* Data configuration reg WR */
-#define EN0_COUNTER1 EI_SHIFT(0x0e) /* Rcv CRC error counter RD */
-#define EN0_IMR EI_SHIFT(0x0f) /* Interrupt mask reg WR */
-#define EN0_COUNTER2 EI_SHIFT(0x0f) /* Rcv missed frame error counter RD */
-
-/* Bits in EN0_ISR - Interrupt status register */
-#define ENISR_RX 0x01 /* Receiver, no error */
-#define ENISR_TX 0x02 /* Transmitter, no error */
-#define ENISR_RX_ERR 0x04 /* Receiver, with error */
-#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
-#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
-#define ENISR_COUNTERS 0x20 /* Counters need emptying */
-#define ENISR_RDC 0x40 /* remote dma complete */
-#define ENISR_RESET 0x80 /* Reset completed */
-#define ENISR_ALL 0x3f /* Interrupts we will enable */
-
-/* Bits in EN0_DCFG - Data config register */
-#define ENDCFG_WTS 0x01 /* word transfer mode selection */
-#define ENDCFG_BOS 0x02 /* byte order selection */
-#define ENDCFG_AUTO_INIT 0x10 /* Auto-init to remove packets from ring */
-#define ENDCFG_FIFO 0x40 /* 8 bytes */
-
-/* Page 1 register offsets. */
-#define EN1_PHYS EI_SHIFT(0x01) /* This board's physical enet addr RD WR */
-#define EN1_PHYS_SHIFT(i) EI_SHIFT(i+1) /* Get and set mac address */
-#define EN1_CURPAG EI_SHIFT(0x07) /* Current memory page RD WR */
-#define EN1_MULT EI_SHIFT(0x08) /* Multicast filter mask array (8 bytes) RD WR */
-#define EN1_MULT_SHIFT(i) EI_SHIFT(8+i) /* Get and set multicast filter */
-
-/* Bits in received packet status byte and EN0_RSR*/
-#define ENRSR_RXOK 0x01 /* Received a good packet */
-#define ENRSR_CRC 0x02 /* CRC error */
-#define ENRSR_FAE 0x04 /* frame alignment error */
-#define ENRSR_FO 0x08 /* FIFO overrun */
-#define ENRSR_MPA 0x10 /* missed pkt */
-#define ENRSR_PHY 0x20 /* physical/multicast address */
-#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
-#define ENRSR_DEF 0x80 /* deferring */
-
-/* Transmitted packet status, EN0_TSR. */
-#define ENTSR_PTX 0x01 /* Packet transmitted without error */
-#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
-#define ENTSR_COL 0x04 /* The transmit collided at least once. */
-#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
-#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
-#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
-#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
-#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
-
-#define NIC_RECEIVE_MONITOR_MODE 0x20
-
-#endif /* _8390_h */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 2ce89f7..a44a7d3 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -56,7 +56,6 @@
obj-$(CONFIG_MVNETA) += mvneta.o
obj-$(CONFIG_MVPP2) += mvpp2.o
obj-$(CONFIG_NATSEMI) += natsemi.o
-obj-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
obj-$(CONFIG_NETCONSOLE) += netconsole.o
obj-$(CONFIG_NS8382X) += ns8382x.o
obj-$(CONFIG_PCH_GBE) += pch_gbe.o
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index b8ba00b..5d92257 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -91,9 +91,8 @@
}
#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
-static int dw_mdio_reset(struct mii_dev *bus)
+static int __dw_mdio_reset(struct udevice *dev)
{
- struct udevice *dev = bus->priv;
struct dw_eth_dev *priv = dev_get_priv(dev);
struct dw_eth_pdata *pdata = dev_get_plat(dev);
int ret;
@@ -122,6 +121,13 @@
return 0;
}
+
+static int dw_mdio_reset(struct mii_dev *bus)
+{
+ struct udevice *dev = bus->priv;
+
+ return __dw_mdio_reset(dev);
+}
#endif
#if IS_ENABLED(CONFIG_DM_MDIO)
@@ -142,9 +148,10 @@
#if CONFIG_IS_ENABLED(DM_GPIO)
int designware_eth_mdio_reset(struct udevice *mdio_dev)
{
- struct mdio_perdev_priv *pdata = dev_get_uclass_priv(mdio_dev);
+ struct mdio_perdev_priv *mdio_pdata = dev_get_uclass_priv(mdio_dev);
+ struct udevice *dev = mdio_pdata->mii_bus->priv;
- return dw_mdio_reset(pdata->mii_bus);
+ return __dw_mdio_reset(dev->parent);
}
#endif
diff --git a/drivers/net/dwmac_meson8b.c b/drivers/net/dwmac_meson8b.c
index c0b6ef4..ddbaa87 100644
--- a/drivers/net/dwmac_meson8b.c
+++ b/drivers/net/dwmac_meson8b.c
@@ -59,8 +59,6 @@
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set RGMII mode */
setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
AXG_ETH_REG_0_TX_PHASE(1) |
@@ -69,6 +67,15 @@
AXG_ETH_REG_0_CLK_EN);
break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
+ setbits_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
+ AXG_ETH_REG_0_TX_RATIO(4) |
+ AXG_ETH_REG_0_PHY_CLK_EN |
+ AXG_ETH_REG_0_CLK_EN);
+ break;
+
case PHY_INTERFACE_MODE_RMII:
/* Set RMII mode */
out_le32(plat->regs + ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
@@ -90,8 +97,6 @@
switch (edata->phy_interface) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
- case PHY_INTERFACE_MODE_RGMII_RXID:
- case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set RGMII mode */
setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
GX_ETH_REG_0_TX_PHASE(1) |
@@ -101,6 +106,16 @@
break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ /* TOFIX: handle amlogic,tx-delay-ns & rx-internal-delay-ps from DT */
+ setbits_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
+ GX_ETH_REG_0_TX_RATIO(4) |
+ GX_ETH_REG_0_PHY_CLK_EN |
+ GX_ETH_REG_0_CLK_EN);
+
+ break;
+
case PHY_INTERFACE_MODE_RMII:
/* Set RMII mode */
out_le32(plat->regs + ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
@@ -133,6 +148,7 @@
static const struct udevice_id dwmac_meson8b_ids[] = {
{ .compatible = "amlogic,meson-gxbb-dwmac", .data = (ulong)dwmac_setup_gx },
+ { .compatible = "amlogic,meson-g12a-dwmac", .data = (ulong)dwmac_setup_axg },
{ .compatible = "amlogic,meson-axg-dwmac", .data = (ulong)dwmac_setup_axg },
{ }
};
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index ec21157..4fd5c01 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1299,16 +1299,19 @@
static int device_get_phy_addr(struct fec_priv *priv, struct udevice *dev)
{
struct ofnode_phandle_args phandle_args;
- int reg;
+ int reg, ret;
- if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
- &phandle_args)) {
- debug("Failed to find phy-handle");
- return -ENODEV;
+ ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
+ &phandle_args);
+ if (ret) {
+ debug("Failed to find phy-handle (err = %d\n)", ret);
+ return ret;
}
- priv->phy_of_node = phandle_args.node;
+ if (!ofnode_is_available(phandle_args.node))
+ return -ENOENT;
+ priv->phy_of_node = phandle_args.node;
reg = ofnode_read_u32_default(phandle_args.node, "reg", 0);
return reg;
@@ -1352,6 +1355,7 @@
static int fecmxc_probe(struct udevice *dev)
{
+ bool dm_mii_bus = true;
struct eth_pdata *pdata = dev_get_plat(dev);
struct fec_priv *priv = dev_get_priv(dev);
struct mii_dev *bus = NULL;
@@ -1459,6 +1463,7 @@
#endif
if (!bus) {
+ dm_mii_bus = false;
#ifdef CONFIG_FEC_MXC_MDIO_BASE
bus = fec_get_miibus((ulong)CONFIG_FEC_MXC_MDIO_BASE,
dev_seq(dev));
@@ -1504,8 +1509,10 @@
return 0;
err_phy:
- mdio_unregister(bus);
- free(bus);
+ if (!dm_mii_bus) {
+ mdio_unregister(bus);
+ free(bus);
+ }
err_mii:
err_timeout:
fec_free_descs(priv);
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index f909660..04008d2 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -565,7 +565,7 @@
ulong rate;
int ret;
- ret = clk_set_defaults(dev, 0);
+ ret = clk_set_defaults(dev, CLK_DEFAULTS_PRE);
if (ret)
debug("%s clk_set_defaults failed %d\n", __func__, ret);
diff --git a/drivers/net/mscc_eswitch/jr2_switch.c b/drivers/net/mscc_eswitch/jr2_switch.c
index 570d5a5..d1e5b61 100644
--- a/drivers/net/mscc_eswitch/jr2_switch.c
+++ b/drivers/net/mscc_eswitch/jr2_switch.c
@@ -863,7 +863,6 @@
int i;
int ret;
struct resource res;
- fdt32_t faddr;
phys_addr_t addr_base;
unsigned long addr_size;
ofnode eth_node, node, mdio_node;
@@ -926,9 +925,8 @@
if (ofnode_read_resource(mdio_node, 0, &res))
return -ENOMEM;
- faddr = cpu_to_fdt32(res.start);
- addr_base = ofnode_translate_address(mdio_node, &faddr);
+ addr_base = res.start;
addr_size = res.end - res.start;
/* If the bus is new then create a new bus */
diff --git a/drivers/net/mscc_eswitch/luton_switch.c b/drivers/net/mscc_eswitch/luton_switch.c
index 54afa14..73c950d 100644
--- a/drivers/net/mscc_eswitch/luton_switch.c
+++ b/drivers/net/mscc_eswitch/luton_switch.c
@@ -588,7 +588,6 @@
struct luton_private *priv = dev_get_priv(dev);
int i, ret;
struct resource res;
- fdt32_t faddr;
phys_addr_t addr_base;
unsigned long addr_size;
ofnode eth_node, node, mdio_node;
@@ -658,9 +657,7 @@
if (ofnode_read_resource(mdio_node, 0, &res))
return -ENOMEM;
- faddr = cpu_to_fdt32(res.start);
-
- addr_base = ofnode_translate_address(mdio_node, &faddr);
+ addr_base = res.start;
addr_size = res.end - res.start;
/* If the bus is new then create a new bus */
diff --git a/drivers/net/mscc_eswitch/ocelot_switch.c b/drivers/net/mscc_eswitch/ocelot_switch.c
index 19e725c..d1d0a48 100644
--- a/drivers/net/mscc_eswitch/ocelot_switch.c
+++ b/drivers/net/mscc_eswitch/ocelot_switch.c
@@ -530,7 +530,6 @@
struct ocelot_private *priv = dev_get_priv(dev);
int i, ret;
struct resource res;
- fdt32_t faddr;
phys_addr_t addr_base;
unsigned long addr_size;
ofnode eth_node, node, mdio_node;
@@ -578,9 +577,8 @@
if (ofnode_read_resource(mdio_node, 0, &res))
return -ENOMEM;
- faddr = cpu_to_fdt32(res.start);
- addr_base = ofnode_translate_address(mdio_node, &faddr);
+ addr_base = res.start;
addr_size = res.end - res.start;
/* If the bus is new then create a new bus */
diff --git a/drivers/net/mscc_eswitch/serval_switch.c b/drivers/net/mscc_eswitch/serval_switch.c
index 09ce334..c4b81f7 100644
--- a/drivers/net/mscc_eswitch/serval_switch.c
+++ b/drivers/net/mscc_eswitch/serval_switch.c
@@ -482,7 +482,6 @@
struct serval_private *priv = dev_get_priv(dev);
int i, ret;
struct resource res;
- fdt32_t faddr;
phys_addr_t addr_base;
unsigned long addr_size;
ofnode eth_node, node, mdio_node;
@@ -533,9 +532,8 @@
if (ofnode_read_resource(mdio_node, 0, &res))
return -ENOMEM;
- faddr = cpu_to_fdt32(res.start);
- addr_base = ofnode_translate_address(mdio_node, &faddr);
+ addr_base = res.start;
addr_size = res.end - res.start;
/* If the bus is new then create a new bus */
diff --git a/drivers/net/mscc_eswitch/servalt_switch.c b/drivers/net/mscc_eswitch/servalt_switch.c
index 4a4e9e4..f114086 100644
--- a/drivers/net/mscc_eswitch/servalt_switch.c
+++ b/drivers/net/mscc_eswitch/servalt_switch.c
@@ -412,7 +412,6 @@
struct servalt_private *priv = dev_get_priv(dev);
int i;
struct resource res;
- fdt32_t faddr;
phys_addr_t addr_base;
unsigned long addr_size;
ofnode eth_node, node, mdio_node;
@@ -461,9 +460,8 @@
if (ofnode_read_resource(mdio_node, 0, &res))
return -ENOMEM;
- faddr = cpu_to_fdt32(res.start);
- addr_base = ofnode_translate_address(mdio_node, &faddr);
+ addr_base = res.start;
addr_size = res.end - res.start;
/* If the bus is new then create a new bus */
diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 1cf522b..4c0a7b0 100644
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -490,9 +490,6 @@
#define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
#define MVPP22_SMI_POLLING_EN BIT(10)
-#define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
- (0x4 * (port)))
-
#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
/* Descriptor ring Macros */
@@ -520,8 +517,9 @@
/* Net Complex */
enum mv_netc_topology {
MV_NETC_GE_MAC2_SGMII = BIT(0),
- MV_NETC_GE_MAC3_SGMII = BIT(1),
- MV_NETC_GE_MAC3_RGMII = BIT(2),
+ MV_NETC_GE_MAC2_RGMII = BIT(1),
+ MV_NETC_GE_MAC3_SGMII = BIT(2),
+ MV_NETC_GE_MAC3_RGMII = BIT(3),
};
enum mv_netc_phase {
@@ -978,8 +976,6 @@
unsigned int duplex;
unsigned int speed;
- unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
-
struct mvpp2_bm_pool *pool_long;
struct mvpp2_bm_pool *pool_short;
@@ -2877,8 +2873,13 @@
switch (port->phy_interface) {
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
val |= MVPP2_GMAC_INBAND_AN_MASK;
break;
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ val &= ~MVPP2_GMAC_INBAND_AN_MASK;
+ break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
val |= MVPP2_GMAC_PORT_RGMII_MASK;
@@ -2939,7 +2940,10 @@
else
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
else
val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -3050,10 +3054,10 @@
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
/*
- * Configure GIG MAC to 1000Base-X mode connected to a fiber
+ * Configure GIG MAC to SGMII mode connected to a fiber
* transceiver
*/
- val |= MVPP2_GMAC_PORT_TYPE_MASK;
+ val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
/* configure AN 0x9268 */
@@ -3105,6 +3109,91 @@
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
}
+static void gop_gmac_2500basex_cfg(struct mvpp2_port *port)
+{
+ u32 val, thresh;
+
+ /*
+ * Configure minimal level of the Tx FIFO before the lower part
+ * starts to read a packet
+ */
+ thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
+ val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+ val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+ val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
+ writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+ /* Disable bypass of sync module */
+ val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+ val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+ /* configure DP clock select according to mode */
+ val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+ /* configure QSGMII bypass according to mode */
+ val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+ writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+ val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+ /*
+ * Configure GIG MAC to 2500Base-X mode connected to a fiber
+ * transceiver
+ */
+ val |= MVPP2_GMAC_PORT_TYPE_MASK;
+ writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+ /* In 2500BaseX mode, we can't negotiate speed
+ * and we do not want InBand autoneg
+ * bypass enabled (link interrupt storm risk
+ * otherwise).
+ */
+ val = MVPP2_GMAC_AN_BYPASS_EN |
+ MVPP2_GMAC_EN_PCS_AN |
+ MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_CONFIG_FULL_DUPLEX |
+ MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
+static void gop_gmac_1000basex_cfg(struct mvpp2_port *port)
+{
+ u32 val, thresh;
+
+ /*
+ * Configure minimal level of the Tx FIFO before the lower part
+ * starts to read a packet
+ */
+ thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
+ val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+ val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
+ val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
+ writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
+
+ /* Disable bypass of sync module */
+ val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
+ val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
+ /* configure DP clock select according to mode */
+ val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
+ /* configure QSGMII bypass according to mode */
+ val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
+ writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
+
+ val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
+ /* configure GIG MAC to 1000BASEX mode */
+ val |= MVPP2_GMAC_PORT_TYPE_MASK;
+ writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
+
+ /* In 1000BaseX mode, we can't negotiate speed (it's
+ * only 1000), and we do not want InBand autoneg
+ * bypass enabled (link interrupt storm risk
+ * otherwise).
+ */
+ val = MVPP2_GMAC_AN_BYPASS_EN |
+ MVPP2_GMAC_EN_PCS_AN |
+ MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_CONFIG_FULL_DUPLEX |
+ MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
+}
+
static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
{
u32 val, thresh;
@@ -3150,10 +3239,17 @@
/* Set TX FIFO thresholds */
switch (port->phy_interface) {
case PHY_INTERFACE_MODE_SGMII:
- if (port->phy_speed == 2500)
- gop_gmac_sgmii2_5_cfg(port);
- else
- gop_gmac_sgmii_cfg(port);
+ gop_gmac_sgmii_cfg(port);
+ break;
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ gop_gmac_sgmii2_5_cfg(port);
+ break;
+ case PHY_INTERFACE_MODE_1000BASEX:
+ gop_gmac_1000basex_cfg(port);
+ break;
+
+ case PHY_INTERFACE_MODE_2500BASEX:
+ gop_gmac_2500basex_cfg(port);
break;
case PHY_INTERFACE_MODE_RGMII:
@@ -3208,56 +3304,31 @@
return 0;
}
-/* Set the internal mux's to the required PCS in the PI */
-static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
-{
- u32 val;
- int lane;
-
- switch (num_of_lanes) {
- case 1:
- lane = 0;
- break;
- case 2:
- lane = 1;
- break;
- case 4:
- lane = 2;
- break;
- default:
- return -1;
- }
-
- /* configure XG MAC mode */
- val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
- val &= ~MVPP22_XPCS_PCSMODE_MASK;
- val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
- val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
- writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
-
- return 0;
-}
-
static int gop_mpcs_mode(struct mvpp2_port *port)
{
u32 val;
/* configure PCS40G COMMON CONTROL */
- val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+ val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+ PCS40G_COMMON_CONTROL);
val &= ~FORWARD_ERROR_CORRECTION_MASK;
- writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
+ writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+ PCS40G_COMMON_CONTROL);
/* configure PCS CLOCK RESET */
- val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
+ val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+ PCS_CLOCK_RESET);
val &= ~CLK_DIVISION_RATIO_MASK;
val |= 1 << CLK_DIVISION_RATIO_OFFS;
- writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+ writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+ PCS_CLOCK_RESET);
val &= ~CLK_DIV_PHASE_SET_MASK;
val |= MAC_CLK_RESET_MASK;
val |= RX_SD_CLK_RESET_MASK;
val |= TX_SD_CLK_RESET_MASK;
- writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
+ writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
+ PCS_CLOCK_RESET);
return 0;
}
@@ -3300,22 +3371,6 @@
return 0;
}
-/* Set PCS to reset or exit from reset */
-static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
-{
- u32 val;
-
- /* read - modify - write */
- val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
- if (reset)
- val &= ~MVPP22_XPCS_PCSRESET;
- else
- val |= MVPP22_XPCS_PCSRESET;
- writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
-
- return 0;
-}
-
/* Set the MAC to reset or exit from reset */
static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
{
@@ -3369,6 +3424,9 @@
break;
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
/* configure PCS */
gop_gpcs_mode_cfg(port, 1);
@@ -3387,14 +3445,10 @@
num_of_act_lanes = 2;
mac_num = 0;
/* configure PCS */
- gop_xpcs_mode(port, num_of_act_lanes);
gop_mpcs_mode(port);
/* configure MAC */
gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
- /* pcs unreset */
- gop_xpcs_reset(port, 0);
-
/* mac unreset */
gop_xlg_mac_reset(port, 0);
break;
@@ -3430,6 +3484,9 @@
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
if (enable)
mvpp2_port_enable(port);
else
@@ -3463,12 +3520,21 @@
u32 val = 0;
if (gop_id == 2) {
- if (phy_type == PHY_INTERFACE_MODE_SGMII)
+ if (phy_type == PHY_INTERFACE_MODE_SGMII ||
+ phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
+ phy_type == PHY_INTERFACE_MODE_1000BASEX ||
+ phy_type == PHY_INTERFACE_MODE_2500BASEX)
val |= MV_NETC_GE_MAC2_SGMII;
+ else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
+ phy_type == PHY_INTERFACE_MODE_RGMII_ID)
+ val |= MV_NETC_GE_MAC2_RGMII;
}
if (gop_id == 3) {
- if (phy_type == PHY_INTERFACE_MODE_SGMII)
+ if (phy_type == PHY_INTERFACE_MODE_SGMII ||
+ phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
+ phy_type == PHY_INTERFACE_MODE_1000BASEX ||
+ phy_type == PHY_INTERFACE_MODE_2500BASEX)
val |= MV_NETC_GE_MAC3_SGMII;
else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
phy_type == PHY_INTERFACE_MODE_RGMII_ID)
@@ -3656,7 +3722,7 @@
if (c & MV_NETC_GE_MAC2_SGMII)
gop_netc_mac_to_sgmii(priv, 2, phase);
- else
+ else if (c & MV_NETC_GE_MAC2_RGMII)
gop_netc_mac_to_xgmii(priv, 2, phase);
if (c & MV_NETC_GE_MAC3_SGMII) {
@@ -4383,7 +4449,8 @@
if (phydev->duplex)
val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
- if (phydev->speed == SPEED_1000)
+ if (phydev->speed == SPEED_1000 ||
+ phydev->speed == 2500)
val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
else if (phydev->speed == SPEED_100)
val |= MVPP2_GMAC_CONFIG_MII_SPEED;
@@ -4464,6 +4531,9 @@
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
mvpp2_gmac_max_rx_size_set(port);
default:
break;
@@ -4721,16 +4791,25 @@
u32 id;
u32 phyaddr = 0;
int phy_mode = -1;
+ int fixed_link = 0;
int ret;
phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
+ fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node, "fixed-link");
if (phy_node > 0) {
int parent;
- phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
- if (phyaddr < 0) {
- dev_err(dev, "could not find phy address\n");
- return -1;
+
+ if (fixed_link != -FDT_ERR_NOTFOUND) {
+ /* phy_addr is set to invalid value for fixed links */
+ phyaddr = PHY_MAX_ADDR;
+ } else {
+ phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node,
+ "reg", 0);
+ if (phyaddr < 0) {
+ dev_err(dev, "could not find phy address\n");
+ return -1;
+ }
}
parent = fdt_parent_offset(gd->fdt_blob, phy_node);
ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
@@ -4763,15 +4842,6 @@
&port->phy_tx_disable_gpio, GPIOD_IS_OUT);
#endif
- /*
- * ToDo:
- * Not sure if this DT property "phy-speed" will get accepted, so
- * this might change later
- */
- /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
- port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
- "phy-speed", 1000);
-
port->id = id;
if (port->priv->hw_version == MVPP21)
port->first_rxq = port->id * rxq_number;
@@ -5200,6 +5270,9 @@
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_SGMII_2500:
+ case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
mvpp2_port_power_up(port);
default:
break;
@@ -5226,14 +5299,6 @@
return mvpp2_prs_update_mac_da(port, port->dev_addr);
}
-static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
-{
- writel(port->phyaddr, port->priv->iface_base +
- MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
-
- return 0;
-}
-
static int mvpp2_base_probe(struct udevice *dev)
{
struct mvpp2 *priv = dev_get_priv(dev);
@@ -5356,10 +5421,6 @@
port->base = priv->iface_base + MVPP22_PORT_BASE +
port->gop_id * MVPP22_PORT_OFFSET;
- /* Set phy address of the port */
- if (port->phyaddr < PHY_MAX_ADDR)
- mvpp22_smi_phy_addr_cfg(port);
-
/* GoP Init */
gop_port_init(port);
}
diff --git a/drivers/net/ne2000.c b/drivers/net/ne2000.c
deleted file mode 100644
index 28a99bb..0000000
--- a/drivers/net/ne2000.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
-Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
-
-Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
-eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
-are GPL, so this is, of course, GPL.
-
-==========================================================================
-
-dev/if_dp83902a.c
-
-Ethernet device driver for NS DP83902a ethernet controller
-
-==========================================================================
-####ECOSGPLCOPYRIGHTBEGIN####
--------------------------------------------
-This file is part of eCos, the Embedded Configurable Operating System.
-Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-
-eCos is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2 or (at your option) any later version.
-
-eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-for more details.
-
-You should have received a copy of the GNU General Public License along
-with eCos; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-
-As a special exception, if other files instantiate templates or use macros
-or inline functions from this file, or you compile this file and link it
-with other works to produce a work based on this file, this file does not
-by itself cause the resulting work to be covered by the GNU General Public
-License. However the source code for this file must still be made available
-in accordance with section (3) of the GNU General Public License.
-
-This exception does not invalidate any other reasons why a work based on
-this file might be covered by the GNU General Public License.
-
-Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-at http://sources.redhat.com/ecos/ecos-license/
--------------------------------------------
-####ECOSGPLCOPYRIGHTEND####
-####BSDCOPYRIGHTBEGIN####
-
--------------------------------------------
-
-Portions of this software may have been derived from OpenBSD or other sources,
-and are covered by the appropriate copyright disclaimers included herein.
-
--------------------------------------------
-
-####BSDCOPYRIGHTEND####
-==========================================================================
-#####DESCRIPTIONBEGIN####
-
-Author(s): gthomas
-Contributors: gthomas, jskov, rsandifo
-Date: 2001-06-13
-Purpose:
-Description:
-
-FIXME: Will fail if pinged with large packets (1520 bytes)
-Add promisc config
-Add SNMP
-
-####DESCRIPTIONEND####
-
-==========================================================================
-*/
-
-#include <common.h>
-#include <command.h>
-#include <linux/delay.h>
-
-/* NE2000 base header file */
-#include "ne2000_base.h"
-
-/* find prom (taken from pc_net_cs.c from Linux) */
-
-#include "8390.h"
-/*
-typedef struct hw_info_t {
- u_int offset;
- u_char a0, a1, a2;
- u_int flags;
-} hw_info_t;
-*/
-#define DELAY_OUTPUT 0x01
-#define HAS_MISC_REG 0x02
-#define USE_BIG_BUF 0x04
-#define HAS_IBM_MISC 0x08
-#define IS_DL10019 0x10
-#define IS_DL10022 0x20
-#define HAS_MII 0x40
-#define USE_SHMEM 0x80 /* autodetected */
-
-#define AM79C9XX_HOME_PHY 0x00006B90 /* HomePNA PHY */
-#define AM79C9XX_ETH_PHY 0x00006B70 /* 10baseT PHY */
-#define MII_PHYID_REV_MASK 0xfffffff0
-#define MII_PHYID_REG1 0x02
-#define MII_PHYID_REG2 0x03
-
-static hw_info_t hw_info[] = {
- { /* Accton EN2212 */ 0x0ff0, 0x00, 0x00, 0xe8, DELAY_OUTPUT },
- { /* Allied Telesis LA-PCM */ 0x0ff0, 0x00, 0x00, 0xf4, 0 },
- { /* APEX MultiCard */ 0x03f4, 0x00, 0x20, 0xe5, 0 },
- { /* ASANTE FriendlyNet */ 0x4910, 0x00, 0x00, 0x94,
- DELAY_OUTPUT | HAS_IBM_MISC },
- { /* Danpex EN-6200P2 */ 0x0110, 0x00, 0x40, 0xc7, 0 },
- { /* DataTrek NetCard */ 0x0ff0, 0x00, 0x20, 0xe8, 0 },
- { /* Dayna CommuniCard E */ 0x0110, 0x00, 0x80, 0x19, 0 },
- { /* D-Link DE-650 */ 0x0040, 0x00, 0x80, 0xc8, 0 },
- { /* EP-210 Ethernet */ 0x0110, 0x00, 0x40, 0x33, 0 },
- { /* EP4000 Ethernet */ 0x01c0, 0x00, 0x00, 0xb4, 0 },
- { /* Epson EEN10B */ 0x0ff0, 0x00, 0x00, 0x48,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* ELECOM Laneed LD-CDWA */ 0xb8, 0x08, 0x00, 0x42, 0 },
- { /* Hypertec Ethernet */ 0x01c0, 0x00, 0x40, 0x4c, 0 },
- { /* IBM CCAE */ 0x0ff0, 0x08, 0x00, 0x5a,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* IBM CCAE */ 0x0ff0, 0x00, 0x04, 0xac,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* IBM CCAE */ 0x0ff0, 0x00, 0x06, 0x29,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* IBM FME */ 0x0374, 0x08, 0x00, 0x5a,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* IBM FME */ 0x0374, 0x00, 0x04, 0xac,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* Kansai KLA-PCM/T */ 0x0ff0, 0x00, 0x60, 0x87,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* NSC DP83903 */ 0x0374, 0x08, 0x00, 0x17,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* NSC DP83903 */ 0x0374, 0x00, 0xc0, 0xa8,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* NSC DP83903 */ 0x0374, 0x00, 0xa0, 0xb0,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* NSC DP83903 */ 0x0198, 0x00, 0x20, 0xe0,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* I-O DATA PCLA/T */ 0x0ff0, 0x00, 0xa0, 0xb0, 0 },
- { /* Katron PE-520 */ 0x0110, 0x00, 0x40, 0xf6, 0 },
- { /* Kingston KNE-PCM/x */ 0x0ff0, 0x00, 0xc0, 0xf0,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* Kingston KNE-PCM/x */ 0x0ff0, 0xe2, 0x0c, 0x0f,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* Kingston KNE-PC2 */ 0x0180, 0x00, 0xc0, 0xf0, 0 },
- { /* Maxtech PCN2000 */ 0x5000, 0x00, 0x00, 0xe8, 0 },
- { /* NDC Instant-Link */ 0x003a, 0x00, 0x80, 0xc6, 0 },
- { /* NE2000 Compatible */ 0x0ff0, 0x00, 0xa0, 0x0c, 0 },
- { /* Network General Sniffer */ 0x0ff0, 0x00, 0x00, 0x65,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* Panasonic VEL211 */ 0x0ff0, 0x00, 0x80, 0x45,
- HAS_MISC_REG | HAS_IBM_MISC },
- { /* PreMax PE-200 */ 0x07f0, 0x00, 0x20, 0xe0, 0 },
- { /* RPTI EP400 */ 0x0110, 0x00, 0x40, 0x95, 0 },
- { /* SCM Ethernet */ 0x0ff0, 0x00, 0x20, 0xcb, 0 },
- { /* Socket EA */ 0x4000, 0x00, 0xc0, 0x1b,
- DELAY_OUTPUT | HAS_MISC_REG | USE_BIG_BUF },
- { /* Socket LP-E CF+ */ 0x01c0, 0x00, 0xc0, 0x1b, 0 },
- { /* SuperSocket RE450T */ 0x0110, 0x00, 0xe0, 0x98, 0 },
- { /* Volktek NPL-402CT */ 0x0060, 0x00, 0x40, 0x05, 0 },
- { /* NEC PC-9801N-J12 */ 0x0ff0, 0x00, 0x00, 0x4c, 0 },
- { /* PCMCIA Technology OEM */ 0x01c8, 0x00, 0xa0, 0x0c, 0 },
- { /* Qemu */ 0x0, 0x52, 0x54, 0x00, 0 },
- { /* RTL8019AS */ 0x0, 0x0, 0x18, 0x5f, 0 }
-};
-
-#define NR_INFO (sizeof(hw_info)/sizeof(hw_info_t))
-
-#define PCNET_CMD 0x00
-#define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */
-#define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */
-#define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */
-
-static void pcnet_reset_8390(u8* addr)
-{
- int i, r;
-
- n2k_outb(E8390_NODMA + E8390_PAGE0+E8390_STOP, E8390_CMD);
- PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
- n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
- PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
- n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
- PRINTK("cmd (at %lx) is %x\n", addr + E8390_CMD, n2k_inb(E8390_CMD));
- n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
-
- n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
-
- for (i = 0; i < 100; i++) {
- if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
- break;
- PRINTK("got %x in reset\n", r);
- udelay(100);
- }
- n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
-
- if (i == 100)
- printf("pcnet_reset_8390() did not complete.\n");
-} /* pcnet_reset_8390 */
-
-int get_prom(u8* mac_addr, u8* base_addr)
-{
- u8 prom[32];
- int i, j;
- struct {
- u_char value, offset;
- } program_seq[] = {
- {E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
- {0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */
- {0x00, EN0_RCNTLO}, /* Clear the count regs. */
- {0x00, EN0_RCNTHI},
- {0x00, EN0_IMR}, /* Mask completion irq. */
- {0xFF, EN0_ISR},
- {E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */
- {E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */
- {32, EN0_RCNTLO},
- {0x00, EN0_RCNTHI},
- {0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */
- {0x00, EN0_RSARHI},
- {E8390_RREAD+E8390_START, E8390_CMD},
- };
-
- PRINTK ("trying to get MAC via prom reading\n");
-
- pcnet_reset_8390 (base_addr);
-
- mdelay (10);
-
- for (i = 0; i < ARRAY_SIZE(program_seq); i++)
- n2k_outb (program_seq[i].value, program_seq[i].offset);
-
- PRINTK ("PROM:");
- for (i = 0; i < 32; i++) {
- prom[i] = n2k_inb (PCNET_DATAPORT);
- PRINTK (" %02x", prom[i]);
- }
- PRINTK ("\n");
- for (i = 0; i < NR_INFO; i++) {
- if ((prom[0] == hw_info[i].a0) &&
- (prom[2] == hw_info[i].a1) &&
- (prom[4] == hw_info[i].a2)) {
- PRINTK ("matched board %d\n", i);
- break;
- }
- }
- if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
- PRINTK ("on exit i is %d/%ld\n", i, NR_INFO);
- PRINTK ("MAC address is ");
- for (j = 0; j < 6; j++) {
- mac_addr[j] = prom[j << 1];
- PRINTK ("%02x:", mac_addr[i]);
- }
- PRINTK ("\n");
- return (i < NR_INFO) ? i : 0;
- }
- return 0;
-}
diff --git a/drivers/net/ne2000.h b/drivers/net/ne2000.h
deleted file mode 100644
index 2cde6be..0000000
--- a/drivers/net/ne2000.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
-Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
-
-Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
-eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
-are GPL, so this is, of course, GPL.
-
-==========================================================================
-
- dev/dp83902a.h
-
- National Semiconductor DP83902a ethernet chip
-
-==========================================================================
-####ECOSGPLCOPYRIGHTBEGIN####
- -------------------------------------------
- This file is part of eCos, the Embedded Configurable Operating System.
- Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-
- eCos is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2 or (at your option) any later version.
-
- eCos is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License along
- with eCos; if not, write to the Free Software Foundation, Inc.,
- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-
- As a special exception, if other files instantiate templates or use macros
- or inline functions from this file, or you compile this file and link it
- with other works to produce a work based on this file, this file does not
- by itself cause the resulting work to be covered by the GNU General Public
- License. However the source code for this file must still be made available
- in accordance with section (3) of the GNU General Public License.
-
- This exception does not invalidate any other reasons why a work based on
- this file might be covered by the GNU General Public License.
-
- Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
- at http://sources.redhat.com/ecos/ecos-license/
- -------------------------------------------
-####ECOSGPLCOPYRIGHTEND####
-####BSDCOPYRIGHTBEGIN####
-
- -------------------------------------------
-
- Portions of this software may have been derived from OpenBSD or other sources,
- and are covered by the appropriate copyright disclaimers included herein.
-
- -------------------------------------------
-
-####BSDCOPYRIGHTEND####
-==========================================================================
-#####DESCRIPTIONBEGIN####
-
- Author(s): gthomas
- Contributors: gthomas, jskov
- Date: 2001-06-13
- Purpose:
- Description:
-
-####DESCRIPTIONEND####
-
-==========================================================================
-*/
-
-/*
- * NE2000 support header file.
- * Created by Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- */
-
-#ifndef __DRIVERS_NE2000_H__
-#define __DRIVERS_NE2000_H__
-
-/* Enable NE2000 basic init function */
-#define NE2000_BASIC_INIT
-
-#define DP_DATA 0x10
-#define START_PG 0x50 /* First page of TX buffer */
-#define START_PG2 0x48
-#define STOP_PG 0x80 /* Last page +1 of RX ring */
-
-#define RX_START 0x50
-#define RX_END 0x80
-
-#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_)))
-#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_)
-#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_)))
-#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_)
-#endif /* __DRIVERS_NE2000_H__ */
diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c
deleted file mode 100644
index f6673f5..0000000
--- a/drivers/net/ne2000_base.c
+++ /dev/null
@@ -1,792 +0,0 @@
-/*
-Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
-
-Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
-eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
-are GPL, so this is, of course, GPL.
-
-==========================================================================
-
-dev/if_dp83902a.c
-
-Ethernet device driver for NS DP83902a ethernet controller
-
-==========================================================================
-####ECOSGPLCOPYRIGHTBEGIN####
--------------------------------------------
-This file is part of eCos, the Embedded Configurable Operating System.
-Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-
-eCos is free software; you can redistribute it and/or modify it under
-the terms of the GNU General Public License as published by the Free
-Software Foundation; either version 2 or (at your option) any later version.
-
-eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-WARRANTY; without even the implied warranty of MERCHANTABILITY or
-FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-for more details.
-
-You should have received a copy of the GNU General Public License along
-with eCos; if not, write to the Free Software Foundation, Inc.,
-59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-
-As a special exception, if other files instantiate templates or use macros
-or inline functions from this file, or you compile this file and link it
-with other works to produce a work based on this file, this file does not
-by itself cause the resulting work to be covered by the GNU General Public
-License. However the source code for this file must still be made available
-in accordance with section (3) of the GNU General Public License.
-
-This exception does not invalidate any other reasons why a work based on
-this file might be covered by the GNU General Public License.
-
-Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-at http://sources.redhat.com/ecos/ecos-license/
--------------------------------------------
-####ECOSGPLCOPYRIGHTEND####
-####BSDCOPYRIGHTBEGIN####
-
--------------------------------------------
-
-Portions of this software may have been derived from OpenBSD or other sources,
-and are covered by the appropriate copyright disclaimers included herein.
-
--------------------------------------------
-
-####BSDCOPYRIGHTEND####
-==========================================================================
-#####DESCRIPTIONBEGIN####
-
-Author(s): gthomas
-Contributors: gthomas, jskov, rsandifo
-Date: 2001-06-13
-Purpose:
-Description:
-
-FIXME: Will fail if pinged with large packets (1520 bytes)
-Add promisc config
-Add SNMP
-
-####DESCRIPTIONEND####
-
-==========================================================================
-*/
-
-#include <common.h>
-#include <command.h>
-#include <env.h>
-#include <log.h>
-#include <net.h>
-#include <malloc.h>
-#include <linux/compiler.h>
-
-/* forward definition of function used for the uboot interface */
-void uboot_push_packet_len(int len);
-void uboot_push_tx_done(int key, int val);
-
-/* NE2000 base header file */
-#include "ne2000_base.h"
-
-#if defined(CONFIG_DRIVER_AX88796L)
-/* AX88796L support */
-#include "ax88796.h"
-#else
-/* Basic NE2000 chip support */
-#include "ne2000.h"
-#endif
-
-static dp83902a_priv_data_t nic; /* just one instance of the card supported */
-
-/**
- * This function reads the MAC address from the serial EEPROM,
- * used if PROM read fails. Does nothing for ax88796 chips (sh boards)
- */
-static bool
-dp83902a_init(unsigned char *enetaddr)
-{
- dp83902a_priv_data_t *dp = &nic;
- u8* base;
-#if defined(NE2000_BASIC_INIT)
- int i;
-#endif
-
- DEBUG_FUNCTION();
-
- base = dp->base;
- if (!base)
- return false; /* No device found */
-
- DEBUG_LINE();
-
-#if defined(NE2000_BASIC_INIT)
- /* AX88796L doesn't need */
- /* Prepare ESA */
- DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */
- /* Use the address from the serial EEPROM */
- for (i = 0; i < 6; i++)
- DP_IN(base, DP_P1_PAR0+i, dp->esa[i]);
- DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */
-
- printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n",
- "eeprom",
- dp->esa[0],
- dp->esa[1],
- dp->esa[2],
- dp->esa[3],
- dp->esa[4],
- dp->esa[5] );
-
- memcpy(enetaddr, dp->esa, 6); /* Use MAC from serial EEPROM */
-#endif /* NE2000_BASIC_INIT */
- return true;
-}
-
-static void
-dp83902a_stop(void)
-{
- dp83902a_priv_data_t *dp = &nic;
- u8 *base = dp->base;
-
- DEBUG_FUNCTION();
-
- DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
- DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */
- DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */
-
- dp->running = false;
-}
-
-/*
- * This function is called to "start up" the interface. It may be called
- * multiple times, even when the hardware is already running. It will be
- * called whenever something "hardware oriented" changes and should leave
- * the hardware ready to send/receive packets.
- */
-static void
-dp83902a_start(u8 * enaddr)
-{
- dp83902a_priv_data_t *dp = &nic;
- u8 *base = dp->base;
- int i;
-
- debug("The MAC is %pM\n", enaddr);
-
- DEBUG_FUNCTION();
-
- DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */
- DP_OUT(base, DP_DCR, DP_DCR_INIT);
- DP_OUT(base, DP_RBCH, 0); /* Remote byte count */
- DP_OUT(base, DP_RBCL, 0);
- DP_OUT(base, DP_RCR, DP_RCR_MON); /* Accept no packets */
- DP_OUT(base, DP_TCR, DP_TCR_LOCAL); /* Transmitter [virtually] off */
- DP_OUT(base, DP_TPSR, dp->tx_buf1); /* Transmitter start page */
- dp->tx1 = dp->tx2 = 0;
- dp->tx_next = dp->tx_buf1;
- dp->tx_started = false;
- dp->running = true;
- DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
- DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */
- DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */
- dp->rx_next = dp->rx_buf_start - 1;
- dp->running = true;
- DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */
- DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */
- DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */
- DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */
- dp->running = true;
- for (i = 0; i < ETHER_ADDR_LEN; i++) {
- /* FIXME */
- /*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) +
- * 0x1400)) = enaddr[i];*/
- DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
- }
- /* Enable and start device */
- DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
- DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
- DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */
- dp->running = true;
-}
-
-/*
- * This routine is called to start the transmitter. It is split out from the
- * data handling routine so it may be called either when data becomes first
- * available or when an Tx interrupt occurs
- */
-
-static void
-dp83902a_start_xmit(int start_page, int len)
-{
- dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
- u8 *base = dp->base;
-
- DEBUG_FUNCTION();
-
-#if DEBUG & 1
- printf("Tx pkt %d len %d\n", start_page, len);
- if (dp->tx_started)
- printf("TX already started?!?\n");
-#endif
-
- DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE));
- DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
- DP_OUT(base, DP_TBCL, len & 0xFF);
- DP_OUT(base, DP_TBCH, len >> 8);
- DP_OUT(base, DP_TPSR, start_page);
- DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
-
- dp->tx_started = true;
-}
-
-/*
- * This routine is called to send data to the hardware. It is known a-priori
- * that there is free buffer space (dp->tx_next).
- */
-static void
-dp83902a_send(u8 *data, int total_len, u32 key)
-{
- struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- u8 *base = dp->base;
- int len, start_page, pkt_len, i, isr;
-#if DEBUG & 4
- int dx;
-#endif
-
- DEBUG_FUNCTION();
-
- len = pkt_len = total_len;
- if (pkt_len < IEEE_8023_MIN_FRAME)
- pkt_len = IEEE_8023_MIN_FRAME;
-
- start_page = dp->tx_next;
- if (dp->tx_next == dp->tx_buf1) {
- dp->tx1 = start_page;
- dp->tx1_len = pkt_len;
- dp->tx1_key = key;
- dp->tx_next = dp->tx_buf2;
- } else {
- dp->tx2 = start_page;
- dp->tx2_len = pkt_len;
- dp->tx2_key = key;
- dp->tx_next = dp->tx_buf1;
- }
-
-#if DEBUG & 5
- printf("TX prep page %d len %d\n", start_page, pkt_len);
-#endif
-
- DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
- {
- /*
- * Dummy read. The manual sez something slightly different,
- * but the code is extended a bit to do what Hitachi's monitor
- * does (i.e., also read data).
- */
-
- __maybe_unused u16 tmp;
- int len = 1;
-
- DP_OUT(base, DP_RSAL, 0x100 - len);
- DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff);
- DP_OUT(base, DP_RBCL, len);
- DP_OUT(base, DP_RBCH, 0);
- DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START);
- DP_IN_DATA(dp->data, tmp);
- }
-
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
- /*
- * Stall for a bit before continuing to work around random data
- * corruption problems on some platforms.
- */
- CYGACC_CALL_IF_DELAY_US(1);
-#endif
-
- /* Send data to device buffer(s) */
- DP_OUT(base, DP_RSAL, 0);
- DP_OUT(base, DP_RSAH, start_page);
- DP_OUT(base, DP_RBCL, pkt_len & 0xFF);
- DP_OUT(base, DP_RBCH, pkt_len >> 8);
- DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START);
-
- /* Put data into buffer */
-#if DEBUG & 4
- printf(" sg buf %08lx len %08x\n ", (u32)data, len);
- dx = 0;
-#endif
- while (len > 0) {
-#if DEBUG & 4
- printf(" %02x", *data);
- if (0 == (++dx % 16)) printf("\n ");
-#endif
-
- DP_OUT_DATA(dp->data, *data++);
- len--;
- }
-#if DEBUG & 4
- printf("\n");
-#endif
- if (total_len < pkt_len) {
-#if DEBUG & 4
- printf(" + %d bytes of padding\n", pkt_len - total_len);
-#endif
- /* Padding to 802.3 length was required */
- for (i = total_len; i < pkt_len;) {
- i++;
- DP_OUT_DATA(dp->data, 0);
- }
- }
-
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA
- /*
- * After last data write, delay for a bit before accessing the
- * device again, or we may get random data corruption in the last
- * datum (on some platforms).
- */
- CYGACC_CALL_IF_DELAY_US(1);
-#endif
-
- /* Wait for DMA to complete */
- do {
- DP_IN(base, DP_ISR, isr);
- } while ((isr & DP_ISR_RDC) == 0);
-
- /* Then disable DMA */
- DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
-
- /* Start transmit if not already going */
- if (!dp->tx_started) {
- if (start_page == dp->tx1) {
- dp->tx_int = 1; /* Expecting interrupt from BUF1 */
- } else {
- dp->tx_int = 2; /* Expecting interrupt from BUF2 */
- }
- dp83902a_start_xmit(start_page, pkt_len);
- }
-}
-
-/*
- * This function is called when a packet has been received. It's job is
- * to prepare to unload the packet from the hardware. Once the length of
- * the packet is known, the upper layer of the driver can be told. When
- * the upper layer is ready to unload the packet, the internal function
- * 'dp83902a_recv' will be called to actually fetch it from the hardware.
- */
-static void
-dp83902a_RxEvent(void)
-{
- struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- u8 *base = dp->base;
- __maybe_unused u8 rsr;
- u8 rcv_hdr[4];
- int i, len, pkt, cur;
-
- DEBUG_FUNCTION();
-
- DP_IN(base, DP_RSR, rsr);
- while (true) {
- /* Read incoming packet header */
- DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START);
- DP_IN(base, DP_P1_CURP, cur);
- DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
- DP_IN(base, DP_BNDRY, pkt);
-
- pkt += 1;
- if (pkt == dp->rx_buf_end)
- pkt = dp->rx_buf_start;
-
- if (pkt == cur) {
- break;
- }
- DP_OUT(base, DP_RBCL, sizeof(rcv_hdr));
- DP_OUT(base, DP_RBCH, 0);
- DP_OUT(base, DP_RSAL, 0);
- DP_OUT(base, DP_RSAH, pkt);
- if (dp->rx_next == pkt) {
- if (cur == dp->rx_buf_start)
- DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
- else
- DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */
- return;
- }
- dp->rx_next = pkt;
- DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
- DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
- CYGACC_CALL_IF_DELAY_US(10);
-#endif
-
- /* read header (get data size)*/
- for (i = 0; i < sizeof(rcv_hdr);) {
- DP_IN_DATA(dp->data, rcv_hdr[i++]);
- }
-
-#if DEBUG & 5
- printf("rx hdr %02x %02x %02x %02x\n",
- rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
-#endif
- len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
-
- /* data read */
- uboot_push_packet_len(len);
-
- if (rcv_hdr[1] == dp->rx_buf_start)
- DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1);
- else
- DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */
- }
-}
-
-/*
- * This function is called as a result of the "eth_drv_recv()" call above.
- * It's job is to actually fetch data for a packet from the hardware once
- * memory buffers have been allocated for the packet. Note that the buffers
- * may come in pieces, using a scatter-gather list. This allows for more
- * efficient processing in the upper layers of the stack.
- */
-static void
-dp83902a_recv(u8 *data, int len)
-{
- struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- u8 *base = dp->base;
- int i, mlen;
- u8 saved_char = 0;
- bool saved;
-#if DEBUG & 4
- int dx;
-#endif
-
- DEBUG_FUNCTION();
-
-#if DEBUG & 5
- printf("Rx packet %d length %d\n", dp->rx_next, len);
-#endif
-
- /* Read incoming packet data */
- DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
- DP_OUT(base, DP_RBCL, len & 0xFF);
- DP_OUT(base, DP_RBCH, len >> 8);
- DP_OUT(base, DP_RSAL, 4); /* Past header */
- DP_OUT(base, DP_RSAH, dp->rx_next);
- DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */
- DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START);
-#ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA
- CYGACC_CALL_IF_DELAY_US(10);
-#endif
-
- saved = false;
- for (i = 0; i < 1; i++) {
- if (data) {
- mlen = len;
-#if DEBUG & 4
- printf(" sg buf %08lx len %08x \n", (u32) data, mlen);
- dx = 0;
-#endif
- while (0 < mlen) {
- /* Saved byte from previous loop? */
- if (saved) {
- *data++ = saved_char;
- mlen--;
- saved = false;
- continue;
- }
-
- {
- u8 tmp;
- DP_IN_DATA(dp->data, tmp);
-#if DEBUG & 4
- printf(" %02x", tmp);
- if (0 == (++dx % 16)) printf("\n ");
-#endif
- *data++ = tmp;
- mlen--;
- }
- }
-#if DEBUG & 4
- printf("\n");
-#endif
- }
- }
-}
-
-static void
-dp83902a_TxEvent(void)
-{
- struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- u8 *base = dp->base;
- __maybe_unused u8 tsr;
- u32 key;
-
- DEBUG_FUNCTION();
-
- DP_IN(base, DP_TSR, tsr);
- if (dp->tx_int == 1) {
- key = dp->tx1_key;
- dp->tx1 = 0;
- } else {
- key = dp->tx2_key;
- dp->tx2 = 0;
- }
- /* Start next packet if one is ready */
- dp->tx_started = false;
- if (dp->tx1) {
- dp83902a_start_xmit(dp->tx1, dp->tx1_len);
- dp->tx_int = 1;
- } else if (dp->tx2) {
- dp83902a_start_xmit(dp->tx2, dp->tx2_len);
- dp->tx_int = 2;
- } else {
- dp->tx_int = 0;
- }
- /* Tell higher level we sent this packet */
- uboot_push_tx_done(key, 0);
-}
-
-/*
- * Read the tally counters to clear them. Called in response to a CNT
- * interrupt.
- */
-static void
-dp83902a_ClearCounters(void)
-{
- struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- u8 *base = dp->base;
- __maybe_unused u8 cnt1, cnt2, cnt3;
-
- DP_IN(base, DP_FER, cnt1);
- DP_IN(base, DP_CER, cnt2);
- DP_IN(base, DP_MISSED, cnt3);
- DP_OUT(base, DP_ISR, DP_ISR_CNT);
-}
-
-/*
- * Deal with an overflow condition. This code follows the procedure set
- * out in section 7.0 of the datasheet.
- */
-static void
-dp83902a_Overflow(void)
-{
- struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
- u8 *base = dp->base;
- u8 isr;
-
- /* Issue a stop command and wait 1.6ms for it to complete. */
- DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
- CYGACC_CALL_IF_DELAY_US(1600);
-
- /* Clear the remote byte counter registers. */
- DP_OUT(base, DP_RBCL, 0);
- DP_OUT(base, DP_RBCH, 0);
-
- /* Enter loopback mode while we clear the buffer. */
- DP_OUT(base, DP_TCR, DP_TCR_LOCAL);
- DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA);
-
- /*
- * Read in as many packets as we can and acknowledge any and receive
- * interrupts. Since the buffer has overflowed, a receive event of
- * some kind will have occurred.
- */
- dp83902a_RxEvent();
- DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE);
-
- /* Clear the overflow condition and leave loopback mode. */
- DP_OUT(base, DP_ISR, DP_ISR_OFLW);
- DP_OUT(base, DP_TCR, DP_TCR_NORMAL);
-
- /*
- * If a transmit command was issued, but no transmit event has occurred,
- * restart it here.
- */
- DP_IN(base, DP_ISR, isr);
- if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) {
- DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START);
- }
-}
-
-static void
-dp83902a_poll(void)
-{
- struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
- u8 *base = dp->base;
- u8 isr;
-
- DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
- DP_IN(base, DP_ISR, isr);
- while (0 != isr) {
- /*
- * The CNT interrupt triggers when the MSB of one of the error
- * counters is set. We don't much care about these counters, but
- * we should read their values to reset them.
- */
- if (isr & DP_ISR_CNT) {
- dp83902a_ClearCounters();
- }
- /*
- * Check for overflow. It's a special case, since there's a
- * particular procedure that must be followed to get back into
- * a running state.a
- */
- if (isr & DP_ISR_OFLW) {
- dp83902a_Overflow();
- } else {
- /*
- * Other kinds of interrupts can be acknowledged simply by
- * clearing the relevant bits of the ISR. Do that now, then
- * handle the interrupts we care about.
- */
- DP_OUT(base, DP_ISR, isr); /* Clear set bits */
- if (!dp->running) break; /* Is this necessary? */
- /*
- * Check for tx_started on TX event since these may happen
- * spuriously it seems.
- */
- if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) {
- dp83902a_TxEvent();
- }
- if (isr & (DP_ISR_RxP|DP_ISR_RxE)) {
- dp83902a_RxEvent();
- }
- }
- DP_IN(base, DP_ISR, isr);
- }
-}
-
-
-/* U-Boot specific routines */
-static u8 *pbuf = NULL;
-
-static int pkey = -1;
-static int initialized = 0;
-
-void uboot_push_packet_len(int len) {
- PRINTK("pushed len = %d\n", len);
- if (len >= 2000) {
- printf("NE2000: packet too big\n");
- return;
- }
- dp83902a_recv(&pbuf[0], len);
-
- /*Just pass it to the upper layer*/
- net_process_received_packet(&pbuf[0], len);
-}
-
-void uboot_push_tx_done(int key, int val) {
- PRINTK("pushed key = %d\n", key);
- pkey = key;
-}
-
-/**
- * Setup the driver and init MAC address according to doc/README.enetaddr
- * Called by ne2k_register() before registering the driver @eth layer
- *
- * @param struct ethdevice of this instance of the driver for dev->enetaddr
- * @return 0 on success, -1 on error (causing caller to print error msg)
- */
-static int ne2k_setup_driver(struct eth_device *dev)
-{
- PRINTK("### ne2k_setup_driver\n");
-
- if (!pbuf) {
- pbuf = malloc(2000);
- if (!pbuf) {
- printf("Cannot allocate rx buffer\n");
- return -1;
- }
- }
-
- nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
-
- nic.data = nic.base + DP_DATA;
- nic.tx_buf1 = START_PG;
- nic.tx_buf2 = START_PG2;
- nic.rx_buf_start = RX_START;
- nic.rx_buf_end = RX_END;
-
- /*
- * According to doc/README.enetaddr, drivers shall give priority
- * to the MAC address value in the environment, so we do not read
- * it from the prom or eeprom if it is specified in the environment.
- */
- if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr)) {
- /* If the MAC address is not in the environment, get it: */
- if (!get_prom(dev->enetaddr, nic.base)) /* get MAC from prom */
- dp83902a_init(dev->enetaddr); /* fallback: seeprom */
- /* And write it into the environment otherwise eth_write_hwaddr
- * returns -1 due to eth_env_get_enetaddr_by_index() failing,
- * and this causes "Warning: failed to set MAC address", and
- * cmd_bdinfo has no ethaddr value which it can show: */
- eth_env_set_enetaddr("ethaddr", dev->enetaddr);
- }
- return 0;
-}
-
-static int ne2k_init(struct eth_device *dev, struct bd_info *bd)
-{
- dp83902a_start(dev->enetaddr);
- initialized = 1;
- return 0;
-}
-
-static void ne2k_halt(struct eth_device *dev)
-{
- debug("### ne2k_halt\n");
- if(initialized)
- dp83902a_stop();
- initialized = 0;
-}
-
-static int ne2k_recv(struct eth_device *dev)
-{
- dp83902a_poll();
- return 1;
-}
-
-static int ne2k_send(struct eth_device *dev, void *packet, int length)
-{
- int tmo;
-
- debug("### ne2k_send\n");
-
- pkey = -1;
-
- dp83902a_send((u8 *) packet, length, 666);
- tmo = get_timer (0) + TOUT * CONFIG_SYS_HZ;
- while(1) {
- dp83902a_poll();
- if (pkey != -1) {
- PRINTK("Packet sucesfully sent\n");
- return 0;
- }
- if (get_timer (0) >= tmo) {
- printf("transmission error (timoeut)\n");
- return 0;
- }
-
- }
- return 0;
-}
-
-/**
- * Setup the driver for use and register it with the eth layer
- * @return 0 on success, -1 on error (causing caller to print error msg)
- */
-int ne2k_register(void)
-{
- struct eth_device *dev;
-
- dev = calloc(sizeof(*dev), 1);
- if (dev == NULL)
- return -1;
-
- if (ne2k_setup_driver(dev))
- return -1;
-
- dev->init = ne2k_init;
- dev->halt = ne2k_halt;
- dev->send = ne2k_send;
- dev->recv = ne2k_recv;
-
- strcpy(dev->name, "NE2000");
-
- return eth_register(dev);
-}
diff --git a/drivers/net/ne2000_base.h b/drivers/net/ne2000_base.h
deleted file mode 100644
index 2493608..0000000
--- a/drivers/net/ne2000_base.h
+++ /dev/null
@@ -1,305 +0,0 @@
-/*
-Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
-
-Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
-eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
-are GPL, so this is, of course, GPL.
-
-
-==========================================================================
-
- dev/dp83902a.h
-
- National Semiconductor DP83902a ethernet chip
-
-==========================================================================
-####ECOSGPLCOPYRIGHTBEGIN####
- -------------------------------------------
- This file is part of eCos, the Embedded Configurable Operating System.
- Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-
- eCos is free software; you can redistribute it and/or modify it under
- the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 2 or (at your option) any later version.
-
- eCos is distributed in the hope that it will be useful, but WITHOUT ANY
- WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- for more details.
-
- You should have received a copy of the GNU General Public License along
- with eCos; if not, write to the Free Software Foundation, Inc.,
- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-
- As a special exception, if other files instantiate templates or use macros
- or inline functions from this file, or you compile this file and link it
- with other works to produce a work based on this file, this file does not
- by itself cause the resulting work to be covered by the GNU General Public
- License. However the source code for this file must still be made available
- in accordance with section (3) of the GNU General Public License.
-
- This exception does not invalidate any other reasons why a work based on
- this file might be covered by the GNU General Public License.
-
- Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
- at http://sources.redhat.com/ecos/ecos-license/
- -------------------------------------------
-####ECOSGPLCOPYRIGHTEND####
-####BSDCOPYRIGHTBEGIN####
-
- -------------------------------------------
-
- Portions of this software may have been derived from OpenBSD or other sources,
- and are covered by the appropriate copyright disclaimers included herein.
-
- -------------------------------------------
-
-####BSDCOPYRIGHTEND####
-==========================================================================
-#####DESCRIPTIONBEGIN####
-
- Author(s): gthomas
- Contributors: gthomas, jskov
- Date: 2001-06-13
- Purpose:
- Description:
-
-####DESCRIPTIONEND####
-
-==========================================================================
-
-*/
-
-/*
- ------------------------------------------------------------------------
- Macros for accessing DP registers
- These can be overridden by the platform header
-*/
-
-#ifndef __NE2000_BASE_H__
-#define __NE2000_BASE_H__
-
-/*
- * Debugging details
- *
- * Set to perms of:
- * 0 disables all debug output
- * 1 for process debug output
- * 2 for added data IO output: get_reg, put_reg
- * 4 for packet allocation/free output
- * 8 for only startup status, so we can tell we're installed OK
- */
-#if 0
-#define DEBUG 0xf
-#else
-#define DEBUG 0
-#endif
-
-#if DEBUG & 1
-#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
-#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
-#define PRINTK(args...) printf(args)
-#else
-#define DEBUG_FUNCTION() do {} while(0)
-#define DEBUG_LINE() do {} while(0)
-#define PRINTK(args...)
-#endif
-
-/* timeout for tx/rx in s */
-#include <linux/delay.h>
-#define TOUT 5
-/* Ether MAC address size */
-#define ETHER_ADDR_LEN 6
-
-
-#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
-#define CYGACC_CALL_IF_DELAY_US(X) udelay(X)
-
-/* H/W infomation struct */
-typedef struct hw_info_t {
- u32 offset;
- u8 a0, a1, a2;
- u32 flags;
-} hw_info_t;
-
-typedef struct dp83902a_priv_data {
- u8* base;
- u8* data;
- u8* reset;
- int tx_next; /* First free Tx page */
- int tx_int; /* Expecting interrupt from this buffer */
- int rx_next; /* First free Rx page */
- int tx1, tx2; /* Page numbers for Tx buffers */
- u32 tx1_key, tx2_key; /* Used to ack when packet sent */
- int tx1_len, tx2_len;
- bool tx_started, running, hardwired_esa;
- u8 esa[6];
- void* plf_priv;
-
- /* Buffer allocation */
- int tx_buf1, tx_buf2;
- int rx_buf_start, rx_buf_end;
-} dp83902a_priv_data_t;
-
-/* ------------------------------------------------------------------------ */
-/* Register offsets */
-
-#define DP_CR 0x00
-#define DP_CLDA0 0x01
-#define DP_PSTART 0x01 /* write */
-#define DP_CLDA1 0x02
-#define DP_PSTOP 0x02 /* write */
-#define DP_BNDRY 0x03
-#define DP_TSR 0x04
-#define DP_TPSR 0x04 /* write */
-#define DP_NCR 0x05
-#define DP_TBCL 0x05 /* write */
-#define DP_FIFO 0x06
-#define DP_TBCH 0x06 /* write */
-#define DP_ISR 0x07
-#define DP_CRDA0 0x08
-#define DP_RSAL 0x08 /* write */
-#define DP_CRDA1 0x09
-#define DP_RSAH 0x09 /* write */
-#define DP_RBCL 0x0a /* write */
-#define DP_RBCH 0x0b /* write */
-#define DP_RSR 0x0c
-#define DP_RCR 0x0c /* write */
-#define DP_FER 0x0d
-#define DP_TCR 0x0d /* write */
-#define DP_CER 0x0e
-#define DP_DCR 0x0e /* write */
-#define DP_MISSED 0x0f
-#define DP_IMR 0x0f /* write */
-#define DP_DATAPORT 0x10 /* "eprom" data port */
-
-#define DP_P1_CR 0x00
-#define DP_P1_PAR0 0x01
-#define DP_P1_PAR1 0x02
-#define DP_P1_PAR2 0x03
-#define DP_P1_PAR3 0x04
-#define DP_P1_PAR4 0x05
-#define DP_P1_PAR5 0x06
-#define DP_P1_CURP 0x07
-#define DP_P1_MAR0 0x08
-#define DP_P1_MAR1 0x09
-#define DP_P1_MAR2 0x0a
-#define DP_P1_MAR3 0x0b
-#define DP_P1_MAR4 0x0c
-#define DP_P1_MAR5 0x0d
-#define DP_P1_MAR6 0x0e
-#define DP_P1_MAR7 0x0f
-
-#define DP_P2_CR 0x00
-#define DP_P2_PSTART 0x01
-#define DP_P2_CLDA0 0x01 /* write */
-#define DP_P2_PSTOP 0x02
-#define DP_P2_CLDA1 0x02 /* write */
-#define DP_P2_RNPP 0x03
-#define DP_P2_TPSR 0x04
-#define DP_P2_LNPP 0x05
-#define DP_P2_ACH 0x06
-#define DP_P2_ACL 0x07
-#define DP_P2_RCR 0x0c
-#define DP_P2_TCR 0x0d
-#define DP_P2_DCR 0x0e
-#define DP_P2_IMR 0x0f
-
-/* Command register - common to all pages */
-
-#define DP_CR_STOP 0x01 /* Stop: software reset */
-#define DP_CR_START 0x02 /* Start: initialize device */
-#define DP_CR_TXPKT 0x04 /* Transmit packet */
-#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */
-#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */
-#define DP_CR_SEND 0x18 /* Send packet */
-#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */
-#define DP_CR_PAGE0 0x00 /* Page select */
-#define DP_CR_PAGE1 0x40
-#define DP_CR_PAGE2 0x80
-#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */
-
-/* Data configuration register */
-
-#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */
-#define DP_DCR_BOS 0x02 /* 1=Little Endian */
-#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */
-#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */
-#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */
-#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */
-#define DP_DCR_FIFO_2 0x20
-#define DP_DCR_FIFO_4 0x40
-#define DP_DCR_FIFO_6 0x60
-
-#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4)
-
-/* Interrupt status register */
-
-#define DP_ISR_RxP 0x01 /* Packet received */
-#define DP_ISR_TxP 0x02 /* Packet transmitted */
-#define DP_ISR_RxE 0x04 /* Receive error */
-#define DP_ISR_TxE 0x08 /* Transmit error */
-#define DP_ISR_OFLW 0x10 /* Receive overflow */
-#define DP_ISR_CNT 0x20 /* Tally counters need emptying */
-#define DP_ISR_RDC 0x40 /* Remote DMA complete */
-#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */
-
-/* Interrupt mask register */
-
-#define DP_IMR_RxP 0x01 /* Packet received */
-#define DP_IMR_TxP 0x02 /* Packet transmitted */
-#define DP_IMR_RxE 0x04 /* Receive error */
-#define DP_IMR_TxE 0x08 /* Transmit error */
-#define DP_IMR_OFLW 0x10 /* Receive overflow */
-#define DP_IMR_CNT 0x20 /* Tall counters need emptying */
-#define DP_IMR_RDC 0x40 /* Remote DMA complete */
-
-#define DP_IMR_All 0x3F /* Everything but remote DMA */
-
-/* Receiver control register */
-
-#define DP_RCR_SEP 0x01 /* Save bad(error) packets */
-#define DP_RCR_AR 0x02 /* Accept runt packets */
-#define DP_RCR_AB 0x04 /* Accept broadcast packets */
-#define DP_RCR_AM 0x08 /* Accept multicast packets */
-#define DP_RCR_PROM 0x10 /* Promiscuous mode */
-#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */
-
-/* Receiver status register */
-
-#define DP_RSR_RxP 0x01 /* Packet received */
-#define DP_RSR_CRC 0x02 /* CRC error */
-#define DP_RSR_FRAME 0x04 /* Framing error */
-#define DP_RSR_FO 0x08 /* FIFO overrun */
-#define DP_RSR_MISS 0x10 /* Missed packet */
-#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */
-#define DP_RSR_DIS 0x40 /* Receiver disabled */
-#define DP_RSR_DFR 0x80 /* Receiver processing deferred */
-
-/* Transmitter control register */
-
-#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */
-#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */
-#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */
-#define DP_TCR_INLOOP 0x04 /* Full internal loopback */
-#define DP_TCR_OUTLOOP 0x08 /* External loopback */
-#define DP_TCR_ATD 0x10 /* Auto transmit disable */
-#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */
-
-/* Transmit status register */
-
-#define DP_TSR_TxP 0x01 /* Packet transmitted */
-#define DP_TSR_COL 0x04 /* Collision (at least one) */
-#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */
-#define DP_TSR_CRS 0x10 /* Lost carrier */
-#define DP_TSR_FU 0x20 /* FIFO underrun */
-#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */
-#define DP_TSR_OWC 0x80 /* Collision outside normal window */
-
-#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */
-#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */
-
-/* Functions */
-int get_prom(u8* mac_addr, u8* base_addr);
-
-#endif /* __NE2000_BASE_H__ */
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index dcdef9e..ed197fa 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -948,9 +948,9 @@
phy_interface_t interface)
{
struct phy_device *phydev = NULL;
- ofnode node = dev_ofnode(dev);
+ ofnode node;
- while (ofnode_valid(node)) {
+ ofnode_for_each_subnode(node, dev_ofnode(dev)) {
node = ofnode_by_compatible(node, "xlnx,gmii-to-rgmii-1.0");
if (ofnode_valid(node)) {
phydev = phy_device_create(bus, 0,
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c
index e6954b6..3ab6a30 100644
--- a/drivers/net/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ti/am65-cpsw-nuss.c
@@ -26,7 +26,7 @@
#include "cpsw_mdio.h"
-#define AM65_CPSW_CPSWNU_MAX_PORTS 2
+#define AM65_CPSW_CPSWNU_MAX_PORTS 9
#define AM65_CPSW_SS_BASE 0x0
#define AM65_CPSW_SGMII_BASE 0x100
@@ -719,11 +719,11 @@
if (!port_id)
continue;
- priv->port_id = port_id;
cpsw_common->ports[port_id].disabled = disabled;
if (disabled)
continue;
+ priv->port_id = port_id;
ret = am65_cpsw_ofdata_parse_phy(dev, node);
if (ret)
goto out;
@@ -782,6 +782,7 @@
static const struct udevice_id am65_cpsw_nuss_ids[] = {
{ .compatible = "ti,am654-cpsw-nuss" },
{ .compatible = "ti,j721e-cpsw-nuss" },
+ { .compatible = "ti,am642-cpsw-nuss" },
{ }
};
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index d5b6018..b2b7b25 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -97,6 +97,16 @@
Armada-8K SoCs. The PCIe controller on Armada-8K is based on
DesignWare hardware.
+config PCIE_DW_SIFIVE
+ bool "Enable SiFive FU740 PCIe"
+ depends on CLK_SIFIVE_PRCI
+ depends on RESET_SIFIVE
+ depends on SIFIVE_GPIO
+ select PCIE_DW_COMMON
+ help
+ Say Y here if you want to enable PCIe controller support on
+ FU740.
+
config PCIE_FSL
bool "FSL PowerPC PCIe support"
depends on DM_PCI
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 1f74178..c742bb2 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -54,3 +54,4 @@
obj-$(CONFIG_PCI_BRCMSTB) += pcie_brcmstb.o
obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
+obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 3b9309f..96aa039 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -99,6 +99,46 @@
#define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
#define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
+/* PCIe window configuration */
+#define OB_WIN_BASE_ADDR 0x4c00
+#define OB_WIN_BLOCK_SIZE 0x20
+#define OB_WIN_COUNT 8
+#define OB_WIN_REG_ADDR(win, offset) (OB_WIN_BASE_ADDR + \
+ OB_WIN_BLOCK_SIZE * (win) + \
+ (offset))
+#define OB_WIN_MATCH_LS(win) OB_WIN_REG_ADDR(win, 0x00)
+#define OB_WIN_ENABLE BIT(0)
+#define OB_WIN_MATCH_MS(win) OB_WIN_REG_ADDR(win, 0x04)
+#define OB_WIN_REMAP_LS(win) OB_WIN_REG_ADDR(win, 0x08)
+#define OB_WIN_REMAP_MS(win) OB_WIN_REG_ADDR(win, 0x0c)
+#define OB_WIN_MASK_LS(win) OB_WIN_REG_ADDR(win, 0x10)
+#define OB_WIN_MASK_MS(win) OB_WIN_REG_ADDR(win, 0x14)
+#define OB_WIN_ACTIONS(win) OB_WIN_REG_ADDR(win, 0x18)
+#define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
+#define OB_WIN_FUNC_NUM_MASK GENMASK(31, 24)
+#define OB_WIN_FUNC_NUM_SHIFT 24
+#define OB_WIN_FUNC_NUM_ENABLE BIT(23)
+#define OB_WIN_BUS_NUM_BITS_MASK GENMASK(22, 20)
+#define OB_WIN_BUS_NUM_BITS_SHIFT 20
+#define OB_WIN_MSG_CODE_ENABLE BIT(22)
+#define OB_WIN_MSG_CODE_MASK GENMASK(21, 14)
+#define OB_WIN_MSG_CODE_SHIFT 14
+#define OB_WIN_MSG_PAYLOAD_LEN BIT(12)
+#define OB_WIN_ATTR_ENABLE BIT(11)
+#define OB_WIN_ATTR_TC_MASK GENMASK(10, 8)
+#define OB_WIN_ATTR_TC_SHIFT 8
+#define OB_WIN_ATTR_RELAXED BIT(7)
+#define OB_WIN_ATTR_NOSNOOP BIT(6)
+#define OB_WIN_ATTR_POISON BIT(5)
+#define OB_WIN_ATTR_IDO BIT(4)
+#define OB_WIN_TYPE_MASK GENMASK(3, 0)
+#define OB_WIN_TYPE_SHIFT 0
+#define OB_WIN_TYPE_MEM 0x0
+#define OB_WIN_TYPE_IO 0x4
+#define OB_WIN_TYPE_CONFIG_TYPE0 0x8
+#define OB_WIN_TYPE_CONFIG_TYPE1 0x9
+#define OB_WIN_TYPE_MSG 0xc
+
/* LMI registers base address and register offsets */
#define LMI_BASE_ADDR 0x6000
#define CFG_REG (LMI_BASE_ADDR + 0x0)
@@ -132,8 +172,9 @@
PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
/* PCIe Retries & Timeout definitions */
-#define MAX_RETRIES 10
-#define PIO_WAIT_TIMEOUT 100
+#define PIO_MAX_RETRIES 1500
+#define PIO_WAIT_TIMEOUT 1000
+#define LINK_MAX_RETRIES 10
#define LINK_WAIT_TIMEOUT 100000
#define CFG_RD_UR_VAL 0xFFFFFFFF
@@ -192,7 +233,7 @@
*
* @pcie: The PCI device to access
*
- * Wait up to 1 micro second for PIO access to be accomplished.
+ * Wait up to 1.5 seconds for PIO access to be accomplished.
*
* Return 1 (true) if PIO access is accomplished.
* Return 0 (false) if PIO access is timed out.
@@ -202,7 +243,7 @@
uint start, isr;
uint count;
- for (count = 0; count < MAX_RETRIES; count++) {
+ for (count = 0; count < PIO_MAX_RETRIES; count++) {
start = advk_readl(pcie, PIO_START);
isr = advk_readl(pcie, PIO_ISR);
if (!start && isr)
@@ -214,7 +255,7 @@
udelay(PIO_WAIT_TIMEOUT);
}
- dev_err(pcie->dev, "config read/write timed out\n");
+ dev_err(pcie->dev, "PIO read/write transfer time out\n");
return 0;
}
@@ -323,9 +364,14 @@
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
@@ -342,10 +388,15 @@
advk_writel(pcie, 0, PIO_ADDR_MS);
/* Start the transfer */
+ advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
- if (!pcie_advk_wait_pio(pcie))
- return -EINVAL;
+ if (!pcie_advk_wait_pio(pcie)) {
+ if (offset != PCI_VENDOR_ID)
+ return -EINVAL;
+ *valuep = CFG_RD_CRS_VAL;
+ return 0;
+ }
/* Check PIO status and get the read result */
ret = pcie_advk_check_pio_status(pcie, true, ®);
@@ -420,9 +471,11 @@
return 0;
}
- /* Start PIO */
- advk_writel(pcie, 0, PIO_START);
- advk_writel(pcie, 1, PIO_ISR);
+ if (advk_readl(pcie, PIO_START)) {
+ dev_err(pcie->dev,
+ "Previous PIO read/write transfer is still running\n");
+ return -EINVAL;
+ }
/* Program the control register */
reg = advk_readl(pcie, PIO_CTRL);
@@ -450,6 +503,7 @@
dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
/* Start the transfer */
+ advk_writel(pcie, 1, PIO_ISR);
advk_writel(pcie, 1, PIO_START);
if (!pcie_advk_wait_pio(pcie)) {
@@ -494,7 +548,7 @@
int retries;
/* check if the link is up or not */
- for (retries = 0; retries < MAX_RETRIES; retries++) {
+ for (retries = 0; retries < LINK_MAX_RETRIES; retries++) {
if (pcie_advk_link_up(pcie)) {
printf("PCIE-%d: Link up\n", pcie->first_busno);
return 0;
@@ -508,6 +562,86 @@
return -ETIMEDOUT;
}
+/*
+ * Set PCIe address window register which could be used for memory
+ * mapping.
+ */
+static void pcie_advk_set_ob_win(struct pcie_advk *pcie, u8 win_num,
+ phys_addr_t match, phys_addr_t remap,
+ phys_addr_t mask, u32 actions)
+{
+ advk_writel(pcie, OB_WIN_ENABLE |
+ lower_32_bits(match), OB_WIN_MATCH_LS(win_num));
+ advk_writel(pcie, upper_32_bits(match), OB_WIN_MATCH_MS(win_num));
+ advk_writel(pcie, lower_32_bits(remap), OB_WIN_REMAP_LS(win_num));
+ advk_writel(pcie, upper_32_bits(remap), OB_WIN_REMAP_MS(win_num));
+ advk_writel(pcie, lower_32_bits(mask), OB_WIN_MASK_LS(win_num));
+ advk_writel(pcie, upper_32_bits(mask), OB_WIN_MASK_MS(win_num));
+ advk_writel(pcie, actions, OB_WIN_ACTIONS(win_num));
+}
+
+static void pcie_advk_disable_ob_win(struct pcie_advk *pcie, u8 win_num)
+{
+ advk_writel(pcie, 0, OB_WIN_MATCH_LS(win_num));
+ advk_writel(pcie, 0, OB_WIN_MATCH_MS(win_num));
+ advk_writel(pcie, 0, OB_WIN_REMAP_LS(win_num));
+ advk_writel(pcie, 0, OB_WIN_REMAP_MS(win_num));
+ advk_writel(pcie, 0, OB_WIN_MASK_LS(win_num));
+ advk_writel(pcie, 0, OB_WIN_MASK_MS(win_num));
+ advk_writel(pcie, 0, OB_WIN_ACTIONS(win_num));
+}
+
+static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
+ struct pci_region *region, u32 actions)
+{
+ phys_addr_t phys_start = region->phys_start;
+ pci_addr_t bus_start = region->bus_start;
+ pci_size_t size = region->size;
+ phys_addr_t win_mask;
+ u64 win_size;
+
+ if (*wins == -1)
+ return;
+
+ /*
+ * The n-th PCIe window is configured by tuple (match, remap, mask)
+ * and an access to address A uses this window it if A matches the
+ * match with given mask.
+ * So every PCIe window size must be a power of two and every start
+ * address must be aligned to window size. Minimal size is 64 KiB
+ * because lower 16 bits of mask must be zero.
+ */
+ while (*wins < OB_WIN_COUNT && size > 0) {
+ /* Calculate the largest aligned window size */
+ win_size = (1ULL << (fls64(size) - 1)) |
+ (phys_start ? (1ULL << __ffs64(phys_start)) : 0);
+ win_size = 1ULL << __ffs64(win_size);
+ if (win_size < 0x10000)
+ break;
+
+ dev_dbg(pcie->dev,
+ "Configuring PCIe window %d: [0x%llx-0x%llx] as 0x%x\n",
+ *wins, (u64)phys_start, (u64)phys_start + win_size,
+ actions);
+ win_mask = ~(win_size - 1) & ~0xffff;
+ pcie_advk_set_ob_win(pcie, *wins, phys_start, bus_start,
+ win_mask, actions);
+
+ phys_start += win_size;
+ bus_start += win_size;
+ size -= win_size;
+ (*wins)++;
+ }
+
+ if (size > 0) {
+ *wins = -1;
+ dev_err(pcie->dev,
+ "Invalid PCIe region [0x%llx-0x%llx]\n",
+ (u64)region->phys_start,
+ (u64)region->phys_start + region->size);
+ }
+}
+
/**
* pcie_advk_setup_hw() - PCIe initailzation
*
@@ -517,6 +651,8 @@
*/
static int pcie_advk_setup_hw(struct pcie_advk *pcie)
{
+ struct pci_region *io, *mem, *pref;
+ int i, wins;
u32 reg;
/* Set to Direct mode */
@@ -583,7 +719,9 @@
* configurations (Default User Field: 0xD0074CFC)
* are used to transparent address translation for
* the outbound transactions. Thus, PCIe address
- * windows are not required.
+ * windows are not required for transparent memory
+ * access when default outbound window configuration
+ * is set for memory access.
*/
reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
@@ -599,10 +737,33 @@
reg |= PIO_CTRL_ADDR_WIN_DISABLE;
advk_writel(pcie, reg, PIO_CTRL);
+ /*
+ * Set memory access in Default User Field so it
+ * is not required to configure PCIe address for
+ * transparent memory access.
+ */
+ advk_writel(pcie, OB_WIN_TYPE_MEM, OB_WIN_DEFAULT_ACTIONS);
+
+ /*
+ * Configure PCIe address windows for non-memory or
+ * non-transparent access as by default PCIe uses
+ * transparent memory access.
+ */
+ wins = 0;
+ pci_get_regions(pcie->dev, &io, &mem, &pref);
+ if (io)
+ pcie_advk_set_ob_region(pcie, &wins, io, OB_WIN_TYPE_IO);
+ if (mem && mem->phys_start != mem->bus_start)
+ pcie_advk_set_ob_region(pcie, &wins, mem, OB_WIN_TYPE_MEM);
+ if (pref && pref->phys_start != pref->bus_start)
+ pcie_advk_set_ob_region(pcie, &wins, pref, OB_WIN_TYPE_MEM);
+
- /* Start link training */
- reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
- reg |= PCIE_CORE_LINK_TRAINING;
- advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
+ /* Disable remaining PCIe outbound windows */
+ for (i = ((wins >= 0) ? wins : 0); i < OB_WIN_COUNT; i++)
+ pcie_advk_disable_ob_win(pcie, i);
+
+ if (wins == -1)
+ return -EINVAL;
/* Wait for PCIe link up */
if (pcie_advk_wait_for_link(pcie))
@@ -665,6 +826,16 @@
{
struct pcie_advk *pcie = dev_get_priv(dev);
u32 reg;
+ int i;
+
+ for (i = 0; i < OB_WIN_COUNT; i++)
+ pcie_advk_disable_ob_win(pcie, i);
+
+ reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
+ reg &= ~(PCIE_CORE_CMD_MEM_ACCESS_EN |
+ PCIE_CORE_CMD_IO_ACCESS_EN |
+ PCIE_CORE_CMD_MEM_IO_REQ_EN);
+ advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
reg &= ~LINK_TRAINING_EN;
@@ -702,7 +873,7 @@
};
static const struct udevice_id pcie_advk_ids[] = {
- { .compatible = "marvell,armada-37xx-pcie" },
+ { .compatible = "marvell,armada-3700-pcie" },
{ }
};
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index dfd54b3..22a033e 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -646,6 +646,9 @@
return log_msg_ret("probe", ret);
}
+ if (!ea_pos)
+ sub_bus = pci_get_bus_max();
+
dm_pciauto_postscan_setup_bridge(bus, sub_bus);
return sub_bus;
@@ -787,6 +790,10 @@
return ret;
}
+__weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
+{
+}
+
int pci_bind_bus_devices(struct udevice *bus)
{
ulong vendor, device;
@@ -892,6 +899,8 @@
}
}
}
+
+ board_pci_fixup_dev(bus, dev);
}
return 0;
diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
index 785fd3a..e66fb14 100644
--- a/drivers/pci/pcie_dw_common.c
+++ b/drivers/pci/pcie_dw_common.c
@@ -213,7 +213,7 @@
va_address = set_cfg_address(pcie, bdf, offset);
- value = readl(va_address);
+ value = readl((void __iomem *)va_address);
debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
*valuep = pci_conv_32_to_size(value, offset, size);
@@ -257,9 +257,9 @@
va_address = set_cfg_address(pcie, bdf, offset);
- old = readl(va_address);
+ old = readl((void __iomem *)va_address);
value = pci_conv_size_to_32(old, value, offset, size);
- writel(value, va_address);
+ writel(value, (void __iomem *)va_address);
return pcie_dw_prog_outbound_atu_unroll(pcie, PCIE_ATU_REGION_INDEX1,
PCIE_ATU_TYPE_IO, pcie->io.phys_start,
@@ -333,33 +333,37 @@
}
}
- dev_dbg(pci->dev, "Config space: [0x%p - 0x%p, size 0x%llx]\n",
- pci->cfg_base, pci->cfg_base + pci->cfg_size,
- pci->cfg_size);
+ dev_dbg(pci->dev, "Config space: [0x%llx - 0x%llx, size 0x%llx]\n",
+ (u64)pci->cfg_base, (u64)pci->cfg_base + pci->cfg_size,
+ (u64)pci->cfg_size);
- dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%lx]\n",
- pci->io.phys_start, pci->io.phys_start + pci->io.size,
- pci->io.size);
+ dev_dbg(pci->dev, "IO space: [0x%llx - 0x%llx, size 0x%llx]\n",
+ (u64)pci->io.phys_start, (u64)pci->io.phys_start + pci->io.size,
+ (u64)pci->io.size);
- dev_dbg(pci->dev, "IO bus: [0x%lx - 0x%lx, size 0x%lx]\n",
- pci->io.bus_start, pci->io.bus_start + pci->io.size,
- pci->io.size);
+ dev_dbg(pci->dev, "IO bus: [0x%llx - 0x%llx, size 0x%llx]\n",
+ (u64)pci->io.bus_start, (u64)pci->io.bus_start + pci->io.size,
+ (u64)pci->io.size);
- dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%lx]\n",
- pci->mem.phys_start, pci->mem.phys_start + pci->mem.size,
- pci->mem.size);
+ dev_dbg(pci->dev, "MEM space: [0x%llx - 0x%llx, size 0x%llx]\n",
+ (u64)pci->mem.phys_start,
+ (u64)pci->mem.phys_start + pci->mem.size,
+ (u64)pci->mem.size);
- dev_dbg(pci->dev, "MEM bus: [0x%lx - 0x%lx, size 0x%lx]\n",
- pci->mem.bus_start, pci->mem.bus_start + pci->mem.size,
- pci->mem.size);
+ dev_dbg(pci->dev, "MEM bus: [0x%llx - 0x%llx, size 0x%llx]\n",
+ (u64)pci->mem.bus_start,
+ (u64)pci->mem.bus_start + pci->mem.size,
+ (u64)pci->mem.size);
if (pci->prefetch.size) {
- dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size 0x%lx]\n",
- pci->prefetch.phys_start, pci->prefetch.phys_start + pci->prefetch.size,
- pci->prefetch.size);
+ dev_dbg(pci->dev, "PREFETCH space: [0x%llx - 0x%llx, size 0x%llx]\n",
+ (u64)pci->prefetch.phys_start,
+ (u64)pci->prefetch.phys_start + pci->prefetch.size,
+ (u64)pci->prefetch.size);
- dev_dbg(pci->dev, "PREFETCH bus: [0x%lx - 0x%lx, size 0x%lx]\n",
- pci->prefetch.bus_start, pci->prefetch.bus_start + pci->prefetch.size,
- pci->prefetch.size);
+ dev_dbg(pci->dev, "PREFETCH bus: [0x%llx - 0x%llx, size 0x%llx]\n",
+ (u64)pci->prefetch.bus_start,
+ (u64)pci->prefetch.bus_start + pci->prefetch.size,
+ (u64)pci->prefetch.size);
}
}
diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c
index 93e57cf..0490fd3 100644
--- a/drivers/pci/pcie_dw_mvebu.c
+++ b/drivers/pci/pcie_dw_mvebu.c
@@ -115,6 +115,7 @@
int first_busno;
/* IO and MEM PCI regions */
+ int region_count;
struct pci_region io;
struct pci_region mem;
};
@@ -267,9 +268,10 @@
debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
*valuep = pci_conv_32_to_size(value, offset, size);
- pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_IO, pcie->io.phys_start,
- pcie->io.bus_start, pcie->io.size);
+ if (pcie->region_count > 1)
+ pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_IO, pcie->io.phys_start,
+ pcie->io.bus_start, pcie->io.size);
return 0;
}
@@ -312,9 +314,10 @@
value = pci_conv_size_to_32(old, value, offset, size);
writel(value, va_address);
- pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
- PCIE_ATU_TYPE_IO, pcie->io.phys_start,
- pcie->io.bus_start, pcie->io.size);
+ if (pcie->region_count > 1)
+ pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_IO, pcie->io.phys_start,
+ pcie->io.bus_start, pcie->io.size);
return 0;
}
@@ -513,14 +516,24 @@
hose->first_busno);
}
+ pcie->region_count = hose->region_count - CONFIG_NR_DRAM_BANKS;
+
/* Store the IO and MEM windows settings for future use by the ATU */
- pcie->io.phys_start = hose->regions[0].phys_start; /* IO base */
- pcie->io.bus_start = hose->regions[0].bus_start; /* IO_bus_addr */
- pcie->io.size = hose->regions[0].size; /* IO size */
+ if (pcie->region_count > 1) {
+ /* IO base */
+ pcie->io.phys_start = hose->regions[0].phys_start;
+ /* IO_bus_addr */
+ pcie->io.bus_start = hose->regions[0].bus_start;
+ /* IO size */
+ pcie->io.size = hose->regions[0].size;
+ }
- pcie->mem.phys_start = hose->regions[1].phys_start; /* MEM base */
- pcie->mem.bus_start = hose->regions[1].bus_start; /* MEM_bus_addr */
- pcie->mem.size = hose->regions[1].size; /* MEM size */
+ /* MEM base */
+ pcie->mem.phys_start = hose->regions[pcie->region_count - 1].phys_start;
+ /* MEM_bus_addr */
+ pcie->mem.bus_start = hose->regions[pcie->region_count - 1].bus_start;
+ /* MEM size */
+ pcie->mem.size = hose->regions[pcie->region_count - 1].size;
pcie_dw_prog_outbound_atu(pcie, PCIE_ATU_REGION_INDEX1,
PCIE_ATU_TYPE_MEM, pcie->mem.phys_start,
diff --git a/drivers/pci/pcie_dw_sifive.c b/drivers/pci/pcie_dw_sifive.c
new file mode 100644
index 0000000..fac3f18
--- /dev/null
+++ b/drivers/pci/pcie_dw_sifive.c
@@ -0,0 +1,507 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * SiFive FU740 DesignWare PCIe Controller
+ *
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ *
+ * Based in early part on the i.MX6 PCIe host controller shim which is:
+ *
+ * Copyright (C) 2013 Kosagi
+ * http://www.kosagi.com
+ *
+ * Based on driver from author: Alan Mikhak <amikhak@wirelessfabric.com>
+ */
+#include <asm/io.h>
+#include <asm-generic/gpio.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <generic-phy.h>
+#include <linux/bitops.h>
+#include <linux/log2.h>
+#include <pci.h>
+#include <pci_ep.h>
+#include <pci_ids.h>
+#include <regmap.h>
+#include <reset.h>
+#include <syscon.h>
+
+#include "pcie_dw_common.h"
+
+struct pcie_sifive {
+ /* Must be first member of the struct */
+ struct pcie_dw dw;
+
+ /* private control regs */
+ void __iomem *priv_base;
+
+ /* reset, power, clock resources */
+ int sys_int_pin;
+ struct gpio_desc pwren_gpio;
+ struct gpio_desc reset_gpio;
+ struct clk aux_ck;
+ struct reset_ctl reset;
+};
+
+enum pcie_sifive_devtype {
+ SV_PCIE_UNKNOWN_TYPE = 0,
+ SV_PCIE_ENDPOINT_TYPE = 1,
+ SV_PCIE_HOST_TYPE = 3
+};
+
+#define ASSERTION_DELAY 100
+#define PCIE_PERST_ASSERT 0x0
+#define PCIE_PERST_DEASSERT 0x1
+#define PCIE_PHY_RESET 0x1
+#define PCIE_PHY_RESET_DEASSERT 0x0
+#define GPIO_LOW 0x0
+#define GPIO_HIGH 0x1
+#define PCIE_PHY_SEL 0x1
+
+#define sv_info(sv, fmt, arg...) printf(fmt, ## arg)
+#define sv_warn(sv, fmt, arg...) printf(fmt, ## arg)
+#define sv_debug(sv, fmt, arg...) debug(fmt, ## arg)
+#define sv_err(sv, fmt, arg...) printf(fmt, ## arg)
+
+/* Doorbell Interface */
+#define DBI_OFFSET 0x0
+#define DBI_SIZE 0x1000
+
+#define PL_OFFSET 0x700
+
+#define PHY_DEBUG_R0 (PL_OFFSET + 0x28)
+
+#define PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
+#define PHY_DEBUG_R1_LINK_UP (0x1 << 4)
+#define PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
+
+#define PCIE_MISC_CONTROL_1 0x8bc
+#define DBI_RO_WR_EN BIT(0)
+
+/* pcie reset */
+#define PCIEX8MGMT_PERST_N 0x0
+
+/* LTSSM */
+#define PCIEX8MGMT_APP_LTSSM_ENABLE 0x10
+#define LTSSM_ENABLE_BIT BIT(0)
+
+/* phy reset */
+#define PCIEX8MGMT_APP_HOLD_PHY_RST 0x18
+
+/* device type */
+#define PCIEX8MGMT_DEVICE_TYPE 0x708
+#define DEVICE_TYPE_EP 0x0
+#define DEVICE_TYPE_RC 0x4
+
+/* phy control registers*/
+#define PCIEX8MGMT_PHY0_CR_PARA_ADDR 0x860
+#define PCIEX8MGMT_PHY0_CR_PARA_RD_EN 0x870
+#define PCIEX8MGMT_PHY0_CR_PARA_RD_DATA 0x878
+#define PCIEX8MGMT_PHY0_CR_PARA_SEL 0x880
+#define PCIEX8MGMT_PHY0_CR_PARA_WR_DATA 0x888
+#define PCIEX8MGMT_PHY0_CR_PARA_WR_EN 0x890
+#define PCIEX8MGMT_PHY0_CR_PARA_ACK 0x898
+#define PCIEX8MGMT_PHY1_CR_PARA_ADDR 0x8a0
+#define PCIEX8MGMT_PHY1_CR_PARA_RD_EN 0x8b0
+#define PCIEX8MGMT_PHY1_CR_PARA_RD_DATA 0x8b8
+#define PCIEX8MGMT_PHY1_CR_PARA_SEL 0x8c0
+#define PCIEX8MGMT_PHY1_CR_PARA_WR_DATA 0x8c8
+#define PCIEX8MGMT_PHY1_CR_PARA_WR_EN 0x8d0
+#define PCIEX8MGMT_PHY1_CR_PARA_ACK 0x8d8
+
+#define PCIEX8MGMT_LANE_NUM 8
+#define PCIEX8MGMT_LANE 0x1008
+#define PCIEX8MGMT_LANE_OFF 0x100
+#define PCIEX8MGMT_TERM_MODE 0x0e21
+
+#define PCIE_CAP_BASE 0x70
+#define PCI_CONFIG(r) (DBI_OFFSET + (r))
+#define PCIE_CAPABILITIES(r) PCI_CONFIG(PCIE_CAP_BASE + (r))
+
+/* Link capability */
+#define PF0_PCIE_CAP_LINK_CAP PCIE_CAPABILITIES(0xc)
+#define PCIE_LINK_CAP_MAX_SPEED_MASK 0xf
+#define PCIE_LINK_CAP_MAX_SPEED_GEN1 BIT(0)
+#define PCIE_LINK_CAP_MAX_SPEED_GEN2 BIT(1)
+#define PCIE_LINK_CAP_MAX_SPEED_GEN3 BIT(2)
+#define PCIE_LINK_CAP_MAX_SPEED_GEN4 BIT(3)
+
+static enum pcie_sifive_devtype pcie_sifive_get_devtype(struct pcie_sifive *sv)
+{
+ u32 val;
+
+ val = readl(sv->priv_base + PCIEX8MGMT_DEVICE_TYPE);
+ switch (val) {
+ case DEVICE_TYPE_RC:
+ return SV_PCIE_HOST_TYPE;
+ case DEVICE_TYPE_EP:
+ return SV_PCIE_ENDPOINT_TYPE;
+ default:
+ return SV_PCIE_UNKNOWN_TYPE;
+ }
+}
+
+static void pcie_sifive_priv_set_state(struct pcie_sifive *sv, u32 reg,
+ u32 bits, int state)
+{
+ u32 val;
+
+ val = readl(sv->priv_base + reg);
+ val = state ? (val | bits) : (val & !bits);
+ writel(val, sv->priv_base + reg);
+}
+
+static void pcie_sifive_assert_reset(struct pcie_sifive *sv)
+{
+ dm_gpio_set_value(&sv->reset_gpio, GPIO_LOW);
+ writel(PCIE_PERST_ASSERT, sv->priv_base + PCIEX8MGMT_PERST_N);
+ mdelay(ASSERTION_DELAY);
+}
+
+static void pcie_sifive_power_on(struct pcie_sifive *sv)
+{
+ dm_gpio_set_value(&sv->pwren_gpio, GPIO_HIGH);
+ mdelay(ASSERTION_DELAY);
+}
+
+static void pcie_sifive_deassert_reset(struct pcie_sifive *sv)
+{
+ writel(PCIE_PERST_DEASSERT, sv->priv_base + PCIEX8MGMT_PERST_N);
+ dm_gpio_set_value(&sv->reset_gpio, GPIO_HIGH);
+ mdelay(ASSERTION_DELAY);
+}
+
+static int pcie_sifive_setphy(const u8 phy, const u8 write,
+ const u16 addr, const u16 wrdata,
+ u16 *rddata, struct pcie_sifive *sv)
+{
+ unsigned char ack = 0;
+
+ if (!(phy == 0 || phy == 1))
+ return -2;
+
+ /* setup phy para */
+ writel(addr, sv->priv_base +
+ (phy ? PCIEX8MGMT_PHY1_CR_PARA_ADDR :
+ PCIEX8MGMT_PHY0_CR_PARA_ADDR));
+
+ if (write)
+ writel(wrdata, sv->priv_base +
+ (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_DATA :
+ PCIEX8MGMT_PHY0_CR_PARA_WR_DATA));
+
+ /* enable access if write */
+ if (write)
+ writel(1, sv->priv_base +
+ (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN :
+ PCIEX8MGMT_PHY0_CR_PARA_WR_EN));
+ else
+ writel(1, sv->priv_base +
+ (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN :
+ PCIEX8MGMT_PHY0_CR_PARA_RD_EN));
+
+ /* wait for wait_idle */
+ do {
+ u32 val;
+
+ val = readl(sv->priv_base +
+ (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK :
+ PCIEX8MGMT_PHY0_CR_PARA_ACK));
+ if (val) {
+ ack = 1;
+ if (!write)
+ readl(sv->priv_base +
+ (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_DATA :
+ PCIEX8MGMT_PHY0_CR_PARA_RD_DATA));
+ mdelay(1);
+ }
+ } while (!ack);
+
+ /* clear */
+ if (write)
+ writel(0, sv->priv_base +
+ (phy ? PCIEX8MGMT_PHY1_CR_PARA_WR_EN :
+ PCIEX8MGMT_PHY0_CR_PARA_WR_EN));
+ else
+ writel(0, sv->priv_base +
+ (phy ? PCIEX8MGMT_PHY1_CR_PARA_RD_EN :
+ PCIEX8MGMT_PHY0_CR_PARA_RD_EN));
+
+ while (readl(sv->priv_base +
+ (phy ? PCIEX8MGMT_PHY1_CR_PARA_ACK :
+ PCIEX8MGMT_PHY0_CR_PARA_ACK))) {
+ /* wait for ~wait_idle */
+ }
+
+ return 0;
+}
+
+static void pcie_sifive_init_phy(struct pcie_sifive *sv)
+{
+ int lane;
+
+ /* enable phy cr_para_sel interfaces */
+ writel(PCIE_PHY_SEL, sv->priv_base + PCIEX8MGMT_PHY0_CR_PARA_SEL);
+ writel(PCIE_PHY_SEL, sv->priv_base + PCIEX8MGMT_PHY1_CR_PARA_SEL);
+ mdelay(1);
+
+ /* set PHY AC termination mode */
+ for (lane = 0; lane < PCIEX8MGMT_LANE_NUM; lane++) {
+ pcie_sifive_setphy(0, 1,
+ PCIEX8MGMT_LANE +
+ (PCIEX8MGMT_LANE_OFF * lane),
+ PCIEX8MGMT_TERM_MODE, NULL, sv);
+ pcie_sifive_setphy(1, 1,
+ PCIEX8MGMT_LANE +
+ (PCIEX8MGMT_LANE_OFF * lane),
+ PCIEX8MGMT_TERM_MODE, NULL, sv);
+ }
+}
+
+static int pcie_sifive_check_link(struct pcie_sifive *sv)
+{
+ u32 val;
+
+ val = readl(sv->dw.dbi_base + PHY_DEBUG_R1);
+ return (val & PHY_DEBUG_R1_LINK_UP) &&
+ !(val & PHY_DEBUG_R1_LINK_IN_TRAINING);
+}
+
+static void pcie_sifive_force_gen1(struct pcie_sifive *sv)
+{
+ u32 val, linkcap;
+
+ /*
+ * Force Gen1 operation when starting the link. In case the link is
+ * started in Gen2 mode, there is a possibility the devices on the
+ * bus will not be detected at all. This happens with PCIe switches.
+ */
+
+ /* ctrl_ro_wr_enable */
+ val = readl(sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
+ val |= DBI_RO_WR_EN;
+ writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
+
+ /* configure link cap */
+ linkcap = readl(sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
+ linkcap |= PCIE_LINK_CAP_MAX_SPEED_MASK;
+ writel(linkcap, sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
+
+ /* ctrl_ro_wr_disable */
+ val &= ~DBI_RO_WR_EN;
+ writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
+}
+
+static void pcie_sifive_print_phy_debug(struct pcie_sifive *sv)
+{
+ sv_err(sv, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
+ readl(sv->dw.dbi_base + PHY_DEBUG_R0),
+ readl(sv->dw.dbi_base + PHY_DEBUG_R1));
+}
+
+static int pcie_sifive_wait_for_link(struct pcie_sifive *sv)
+{
+ u32 val;
+ int timeout;
+
+ /* Wait for the link to train */
+ mdelay(20);
+ timeout = 20;
+
+ do {
+ mdelay(1);
+ } while (--timeout && !pcie_sifive_check_link(sv));
+
+ val = readl(sv->dw.dbi_base + PHY_DEBUG_R1);
+ if (!(val & PHY_DEBUG_R1_LINK_UP) ||
+ (val & PHY_DEBUG_R1_LINK_IN_TRAINING)) {
+ sv_info(sv, "Failed to negotiate PCIe link!\n");
+ pcie_sifive_print_phy_debug(sv);
+ writel(PCIE_PHY_RESET,
+ sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int pcie_sifive_start_link(struct pcie_sifive *sv)
+{
+ if (pcie_sifive_check_link(sv))
+ return -EALREADY;
+
+ pcie_sifive_force_gen1(sv);
+
+ /* set ltssm */
+ pcie_sifive_priv_set_state(sv, PCIEX8MGMT_APP_LTSSM_ENABLE,
+ LTSSM_ENABLE_BIT, 1);
+ return 0;
+}
+
+static int pcie_sifive_init_port(struct udevice *dev,
+ enum pcie_sifive_devtype mode)
+{
+ struct pcie_sifive *sv = dev_get_priv(dev);
+ int ret;
+
+ /* Power on reset */
+ pcie_sifive_assert_reset(sv);
+ pcie_sifive_power_on(sv);
+ pcie_sifive_deassert_reset(sv);
+
+ /* Enable pcieauxclk */
+ ret = clk_enable(&sv->aux_ck);
+ if (ret)
+ dev_err(dev, "unable to enable pcie_aux clock\n");
+
+ /*
+ * assert hold_phy_rst (hold the controller LTSSM in reset
+ * after power_up_rst_n for register programming with cr_para)
+ */
+ writel(PCIE_PHY_RESET, sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
+
+ /* deassert power_up_rst_n */
+ ret = reset_deassert(&sv->reset);
+ if (ret < 0) {
+ dev_err(dev, "failed to deassert reset");
+ return -EINVAL;
+ }
+
+ pcie_sifive_init_phy(sv);
+
+ /* disable pcieauxclk */
+ clk_disable(&sv->aux_ck);
+
+ /* deassert hold_phy_rst */
+ writel(PCIE_PHY_RESET_DEASSERT,
+ sv->priv_base + PCIEX8MGMT_APP_HOLD_PHY_RST);
+
+ /* enable pcieauxclk */
+ clk_enable(&sv->aux_ck);
+
+ /* Set desired mode while core is not operational */
+ if (mode == SV_PCIE_HOST_TYPE)
+ writel(DEVICE_TYPE_RC,
+ sv->priv_base + PCIEX8MGMT_DEVICE_TYPE);
+ else
+ writel(DEVICE_TYPE_EP,
+ sv->priv_base + PCIEX8MGMT_DEVICE_TYPE);
+
+ /* Confirm desired mode from operational core */
+ if (pcie_sifive_get_devtype(sv) != mode)
+ return -EINVAL;
+
+ pcie_dw_setup_host(&sv->dw);
+
+ if (pcie_sifive_start_link(sv) == -EALREADY)
+ sv_info(sv, "PCIe link is already up\n");
+ else if (pcie_sifive_wait_for_link(sv) == -ETIMEDOUT)
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+static int pcie_sifive_probe(struct udevice *dev)
+{
+ struct pcie_sifive *sv = dev_get_priv(dev);
+ struct udevice *parent = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(parent);
+ int err;
+
+ sv->dw.first_busno = dev_seq(dev);
+ sv->dw.dev = dev;
+
+ err = pcie_sifive_init_port(dev, SV_PCIE_HOST_TYPE);
+ if (err) {
+ sv_info(sv, "Failed to init port.\n");
+ return err;
+ }
+
+ printf("PCIE-%d: Link up (Gen%d-x%d, Bus%d)\n",
+ dev_seq(dev), pcie_dw_get_link_speed(&sv->dw),
+ pcie_dw_get_link_width(&sv->dw),
+ hose->first_busno);
+
+ return pcie_dw_prog_outbound_atu_unroll(&sv->dw,
+ PCIE_ATU_REGION_INDEX0,
+ PCIE_ATU_TYPE_MEM,
+ sv->dw.mem.phys_start,
+ sv->dw.mem.bus_start,
+ sv->dw.mem.size);
+}
+
+static void __iomem *get_fdt_addr(struct udevice *dev, const char *name)
+{
+ fdt_addr_t addr;
+
+ addr = dev_read_addr_name(dev, name);
+
+ return (addr == FDT_ADDR_T_NONE) ? NULL : (void __iomem *)addr;
+}
+
+static int pcie_sifive_of_to_plat(struct udevice *dev)
+{
+ struct pcie_sifive *sv = dev_get_priv(dev);
+ int err;
+
+ /* get designware DBI base addr */
+ sv->dw.dbi_base = get_fdt_addr(dev, "dbi");
+ if (!sv->dw.dbi_base)
+ return -EINVAL;
+
+ /* get private control base addr */
+ sv->priv_base = get_fdt_addr(dev, "mgmt");
+ if (!sv->priv_base)
+ return -EINVAL;
+
+ gpio_request_by_name(dev, "pwren-gpios", 0, &sv->pwren_gpio,
+ GPIOD_IS_OUT);
+
+ if (!dm_gpio_is_valid(&sv->pwren_gpio)) {
+ sv_info(sv, "pwren_gpio is invalid\n");
+ return -EINVAL;
+ }
+
+ gpio_request_by_name(dev, "reset-gpios", 0, &sv->reset_gpio,
+ GPIOD_IS_OUT);
+
+ if (!dm_gpio_is_valid(&sv->reset_gpio)) {
+ sv_info(sv, "reset_gpio is invalid\n");
+ return -EINVAL;
+ }
+
+ err = clk_get_by_index(dev, 0, &sv->aux_ck);
+ if (err) {
+ sv_info(sv, "clk_get_by_index(aux_ck) failed: %d\n", err);
+ return err;
+ }
+
+ err = reset_get_by_index(dev, 0, &sv->reset);
+ if (err) {
+ sv_info(sv, "reset_get_by_index(reset) failed: %d\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+static const struct dm_pci_ops pcie_sifive_ops = {
+ .read_config = pcie_dw_read_config,
+ .write_config = pcie_dw_write_config,
+};
+
+static const struct udevice_id pcie_sifive_ids[] = {
+ { .compatible = "sifive,fu740-pcie" },
+ {}
+};
+
+U_BOOT_DRIVER(pcie_sifive) = {
+ .name = "pcie_sifive",
+ .id = UCLASS_PCI,
+ .of_match = pcie_sifive_ids,
+ .ops = &pcie_sifive_ops,
+ .of_to_plat = pcie_sifive_of_to_plat,
+ .probe = pcie_sifive_probe,
+ .priv_auto = sizeof(struct pcie_sifive),
+};
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index d9c2325..73875e0 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -473,7 +473,7 @@
* If both LTSSM_ENABLE and REF_SSP_ENABLE are active we have a strong
* indication that the bootloader activated the link.
*/
- if (is_mx6dq() && prepare_for_boot) {
+ if ((is_mx6dq() || is_mx6sdl()) && prepare_for_boot) {
u32 val, gpr1, gpr12;
gpr1 = readl(&iomuxc_regs->gpr[1]);
diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
index 12523d1..06822d1 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -17,33 +17,33 @@
DECLARE_GLOBAL_DATA_PTR;
struct comphy_mux_data a3700_comphy_mux_data[] = {
-/* Lane 0 */
+ /* Lane 0 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0 },
- { PHY_TYPE_SGMII1, 0x0 },
- { PHY_TYPE_USB3_HOST0, 0x1 },
- { PHY_TYPE_USB3_DEVICE, 0x1 }
+ { COMPHY_TYPE_UNCONNECTED, 0x0 },
+ { COMPHY_TYPE_SGMII1, 0x0 },
+ { COMPHY_TYPE_USB3_HOST0, 0x1 },
+ { COMPHY_TYPE_USB3_DEVICE, 0x1 }
}
},
-/* Lane 1 */
+ /* Lane 1 */
{
3,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SGMII0, 0x0},
- { PHY_TYPE_PEX0, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SGMII0, 0x0},
+ { COMPHY_TYPE_PEX0, 0x1}
}
},
-/* Lane 2 */
+ /* Lane 2 */
{
4,
{
- { PHY_TYPE_UNCONNECTED, 0x0},
- { PHY_TYPE_SATA0, 0x0},
- { PHY_TYPE_USB3_HOST0, 0x1},
- { PHY_TYPE_USB3_DEVICE, 0x1}
+ { COMPHY_TYPE_UNCONNECTED, 0x0},
+ { COMPHY_TYPE_SATA0, 0x0},
+ { COMPHY_TYPE_USB3_HOST0, 0x1},
+ { COMPHY_TYPE_USB3_DEVICE, 0x1}
}
},
};
@@ -228,10 +228,10 @@
/*
* 10. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -284,10 +284,10 @@
/*
* 0. Check the Polarity invert bits
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
data |= bs_txd_inv;
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
data |= bs_rxd_inv;
reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv);
@@ -465,10 +465,10 @@
/*
* 9. Check the Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
/*
@@ -513,7 +513,7 @@
* Set Soft ID for Host mode (Device mode works with Hard ID
* detection)
*/
- if (type == PHY_TYPE_USB3_HOST0) {
+ if (type == COMPHY_TYPE_USB3_HOST0) {
/*
* set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
* clear BIT1: set SOFT_ID = Host
@@ -685,8 +685,8 @@
* comparison to 3.125 Gbps values. These register values are
* stored in "sgmii_phy_init_fix" array.
*/
- if ((speed != PHY_SPEED_1_25G) &&
- (sgmii_phy_init_fix[fix_idx].addr == addr)) {
+ if (speed != COMPHY_SPEED_1_25G &&
+ sgmii_phy_init_fix[fix_idx].addr == addr) {
/* Use new value */
val = sgmii_phy_init_fix[fix_idx].value;
if (fix_idx < fix_arr_sz)
@@ -737,13 +737,13 @@
* 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
* COMPHY bit rate
*/
- if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */
+ if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x8 << rf_gen_rx_sel_shift) |
(0x8 << rf_gen_tx_sel_shift),
rf_gen_rx_select | rf_gen_tx_select);
- } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */
+ } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */
reg_set(COMPHY_PHY_CFG1_ADDR(lane),
(0x6 << rf_gen_rx_sel_shift) |
(0x6 << rf_gen_tx_sel_shift),
@@ -819,7 +819,7 @@
* registers are OK.
*/
debug("Running C-DPI phy init %s mode\n",
- speed == PHY_SPEED_3_125G ? "2G5" : "1G");
+ speed == COMPHY_SPEED_3_125G ? "2G5" : "1G");
if (get_ref_clk() == 40)
comphy_sgmii_phy_init(lane, speed);
@@ -837,10 +837,10 @@
/*
* 18. Check the PHY Polarity invert bit
*/
- if (invert & PHY_POLARITY_TXD_INVERT)
+ if (invert & COMPHY_POLARITY_TXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
- if (invert & PHY_POLARITY_RXD_INVERT)
+ if (invert & COMPHY_POLARITY_RXD_INVERT)
reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
/*
@@ -976,30 +976,30 @@
comphy_map->type, comphy_map->invert);
switch (comphy_map->type) {
- case PHY_TYPE_UNCONNECTED:
+ case COMPHY_TYPE_UNCONNECTED:
continue;
break;
- case PHY_TYPE_PEX0:
+ case COMPHY_TYPE_PEX0:
ret = comphy_pcie_power_up(comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_USB3_HOST0:
- case PHY_TYPE_USB3_DEVICE:
+ case COMPHY_TYPE_USB3_HOST0:
+ case COMPHY_TYPE_USB3_DEVICE:
ret = comphy_usb3_power_up(lane,
comphy_map->type,
comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SGMII0:
- case PHY_TYPE_SGMII1:
+ case COMPHY_TYPE_SGMII0:
+ case COMPHY_TYPE_SGMII1:
ret = comphy_sgmii_power_up(lane, comphy_map->speed,
comphy_map->invert);
break;
- case PHY_TYPE_SATA0:
+ case COMPHY_TYPE_SATA0:
ret = comphy_sata_power_up(comphy_map->invert);
break;
diff --git a/drivers/phy/marvell/comphy_a3700.h b/drivers/phy/marvell/comphy_a3700.h
index b0941ff..8748c6c 100644
--- a/drivers/phy/marvell/comphy_a3700.h
+++ b/drivers/phy/marvell/comphy_a3700.h
@@ -7,7 +7,6 @@
#define _COMPHY_A3700_H_
#include "comphy_core.h"
-#include "comphy_hpipe.h"
#define MVEBU_REG(offs) \
((void __iomem *)(ulong)MVEBU_REGISTER(offs))
diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c
index cd54e7f..2c9d7b2 100644
--- a/drivers/phy/marvell/comphy_core.c
+++ b/drivers/phy/marvell/comphy_core.c
@@ -24,12 +24,12 @@
static const char *get_speed_string(u32 speed)
{
static const char * const speed_strings[] = {
- "1.25 Gbps", "1.5 Gbps", "2.5 Gbps",
- "3.0 Gbps", "3.125 Gbps", "5 Gbps", "6 Gbps",
- "6.25 Gbps", "10.31 Gbps"
+ "1.25 Gbps", "2.5 Gbps", "3.125 Gbps",
+ "5 Gbps", "5.125 Gpbs", "6 Gbps",
+ "10.3125 Gbps"
};
- if (speed < 0 || speed > PHY_SPEED_MAX)
+ if (speed < 0 || speed > COMPHY_SPEED_MAX)
return "invalid";
return speed_strings[speed];
@@ -39,14 +39,13 @@
{
static const char * const type_strings[] = {
"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
- "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0",
- "SGMII1", "SGMII2", "SGMII3", "QSGMII",
- "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE",
- "XAUI0", "XAUI1", "XAUI2", "XAUI3",
- "RXAUI0", "RXAUI1", "SFI", "IGNORE"
+ "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
+ "USB3", "USB3_HOST0", "USB3_HOST1",
+ "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP",
+ "IGNORE"
};
- if (type < 0 || type > PHY_TYPE_MAX)
+ if (type < 0 || type > COMPHY_TYPE_MAX)
return "invalid";
return type_strings[type];
@@ -59,7 +58,7 @@
for (lane = 0; lane < chip_cfg->comphy_lanes_count;
lane++, comphy_map_data++) {
- if (comphy_map_data->speed == PHY_SPEED_INVALID) {
+ if (comphy_map_data->speed == COMPHY_SPEED_INVALID) {
printf("Comphy-%d: %-13s\n", lane,
get_type_string(comphy_map_data->type));
} else {
@@ -70,6 +69,16 @@
}
}
+int comphy_rx_training(struct udevice *dev, u32 lane)
+{
+ struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
+
+ if (chip_cfg->rx_training)
+ return chip_cfg->rx_training(chip_cfg, lane);
+
+ return 0;
+}
+
__weak int comphy_update_map(struct comphy_map *serdes_map, int count)
{
return 0;
@@ -80,7 +89,6 @@
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev);
- struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
int subnode;
int lane;
int last_idx = 0;
@@ -114,11 +122,15 @@
fdtdec_locate_array(blob, node, "mux-lane-order",
chip_cfg->comphy_lanes_count);
- if (device_is_compatible(dev, "marvell,comphy-armada-3700"))
+ if (device_is_compatible(dev, "marvell,comphy-armada-3700")) {
chip_cfg->ptr_comphy_chip_init = comphy_a3700_init;
+ chip_cfg->rx_training = NULL;
+ }
- if (device_is_compatible(dev, "marvell,comphy-cp110"))
+ if (device_is_compatible(dev, "marvell,comphy-cp110")) {
chip_cfg->ptr_comphy_chip_init = comphy_cp110_init;
+ chip_cfg->rx_training = comphy_cp110_sfi_rx_training;
+ }
/*
* Bail out if no chip_init function is defined, e.g. no
@@ -135,36 +147,45 @@
if (!fdtdec_get_is_enabled(blob, subnode))
continue;
+ chip_cfg->comphy_map_data[lane].type =
+ fdtdec_get_int(blob, subnode, "phy-type",
+ COMPHY_TYPE_INVALID);
+
- comphy_map_data[lane].speed = fdtdec_get_int(
- blob, subnode, "phy-speed", PHY_TYPE_INVALID);
- comphy_map_data[lane].type = fdtdec_get_int(
- blob, subnode, "phy-type", PHY_SPEED_INVALID);
- comphy_map_data[lane].invert = fdtdec_get_int(
- blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT);
- comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode,
- "clk-src");
- comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode,
- "end_point");
- if (comphy_map_data[lane].type == PHY_TYPE_INVALID) {
+ if (chip_cfg->comphy_map_data[lane].type ==
+ COMPHY_TYPE_INVALID) {
printf("no phy type for lane %d, setting lane as unconnected\n",
lane + 1);
+ continue;
}
+ chip_cfg->comphy_map_data[lane].speed =
+ fdtdec_get_int(blob, subnode, "phy-speed",
+ COMPHY_SPEED_INVALID);
+
+ chip_cfg->comphy_map_data[lane].invert =
+ fdtdec_get_int(blob, subnode, "phy-invert",
+ COMPHY_POLARITY_NO_INVERT);
+
+ chip_cfg->comphy_map_data[lane].clk_src =
+ fdtdec_get_bool(blob, subnode, "clk-src");
+
+ chip_cfg->comphy_map_data[lane].end_point =
+ fdtdec_get_bool(blob, subnode, "end_point");
+
lane++;
}
- res = comphy_update_map(comphy_map_data, chip_cfg->comphy_lanes_count);
+ res = comphy_update_map(chip_cfg->comphy_map_data, chip_cfg->comphy_lanes_count);
if (res < 0)
return res;
/* Save CP index for MultiCP devices (A8K) */
chip_cfg->cp_index = current_idx++;
/* PHY power UP sequence */
- chip_cfg->ptr_comphy_chip_init(chip_cfg, comphy_map_data);
+ chip_cfg->ptr_comphy_chip_init(chip_cfg, chip_cfg->comphy_map_data);
/* PHY print SerDes status */
- if (of_machine_is_compatible("marvell,armada8040"))
- printf("Comphy chip #%d:\n", chip_cfg->cp_index);
- comphy_print(chip_cfg, comphy_map_data);
+ printf("Comphy chip #%d:\n", chip_cfg->cp_index);
+ comphy_print(chip_cfg, chip_cfg->comphy_map_data);
/*
* Only run the dedicated PHY init code once, in the last PHY init call
diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h
index 12ab921..ba64491 100644
--- a/drivers/phy/marvell/comphy_core.h
+++ b/drivers/phy/marvell/comphy_core.h
@@ -17,58 +17,8 @@
#define debug_exit()
#endif
-/* COMPHY registers */
-#define COMMON_PHY_CFG1_REG 0x0
-#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
-#define COMMON_PHY_CFG1_PWR_UP_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
-#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
-#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
- (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
-#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13
-#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
- (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
-#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14
-#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
- (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
-#define COMMON_PHY_PHY_MODE_OFFSET 15
-#define COMMON_PHY_PHY_MODE_MASK \
- (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
-
-#define COMMON_PHY_CFG6_REG 0x14
-#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
-#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
- (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
-
-#define COMMON_SELECTOR_PHY_OFFSET 0x140
-#define COMMON_SELECTOR_PIPE_OFFSET 0x144
-
-#define COMMON_PHY_SD_CTRL1 0x148
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0
-#define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
-#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
-#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
-#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
-#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
-#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
- (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
-
-/* ToDo: Get this address via DT */
-#define MVEBU_CP0_REGS_BASE 0xF2000000UL
-
-#define DFX_DEV_GEN_CTRL12 (MVEBU_CP0_REGS_BASE + 0x400280)
-#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
-#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
- (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
-
#define MAX_LANE_OPTIONS 10
-#define MAX_UTMI_PHY_COUNT 3
+#define MAX_UTMI_PHY_COUNT 6
struct comphy_mux_options {
u32 type;
@@ -84,12 +34,14 @@
struct comphy_mux_data *mux_data;
int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *,
struct comphy_map *);
+ int (*rx_training)(struct chip_serdes_phy_config *, u32);
void __iomem *comphy_base_addr;
void __iomem *hpipe3_base_addr;
u32 comphy_lanes_count;
u32 comphy_mux_bitcount;
const fdt32_t *comphy_mux_lane_order;
u32 cp_index;
+ struct comphy_map comphy_map_data[MAX_LANE_OPTIONS];
};
/* Register helper functions */
@@ -150,6 +102,8 @@
#ifdef CONFIG_ARMADA_8K
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map);
+int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane);
#else
static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
@@ -160,6 +114,17 @@
*/
return -1;
}
+
+static inline int comphy_cp110_sfi_rx_training(
+ struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane)
+{
+ /*
+ * This function should never be called in this configuration, so
+ * lets return an error here.
+ */
+ return -1;
+}
#endif
void comphy_dedicated_phys_init(void);
diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c
index a323de7..418318d 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -14,20 +14,16 @@
#include <linux/delay.h>
#include "comphy_core.h"
-#include "comphy_hpipe.h"
#include "sata.h"
#include "utmi_phy.h"
DECLARE_GLOBAL_DATA_PTR;
-#define SD_ADDR(base, lane) (base + 0x1000 * lane)
-#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
-#define COMPHY_ADDR(base, lane) (base + 0x28 * lane)
-
/* Firmware related definitions used for SMC calls */
#define MV_SIP_COMPHY_POWER_ON 0x82000001
#define MV_SIP_COMPHY_POWER_OFF 0x82000002
#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
+#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
/* Used to distinguish between different possible callers (U-boot/Linux) */
#define COMPHY_CALLER_UBOOT (0x1 << 21)
@@ -59,52 +55,13 @@
#define COMPHY_UNIT_ID3 3
struct utmi_phy_data {
+ void __iomem *utmi_pll_addr;
void __iomem *utmi_base_addr;
void __iomem *usb_cfg_addr;
void __iomem *utmi_cfg_addr;
u32 utmi_phy_port;
};
-/*
- * For CP-110 we have 2 Selector registers "PHY Selectors",
- * and "PIPE Selectors".
- * PIPE selector include USB and PCIe options.
- * PHY selector include the Ethernet and SATA options, every Ethernet
- * option has different options, for example: serdes lane2 had option
- * Eth_port_0 that include (SGMII0, RXAUI0, SFI)
- */
-struct comphy_mux_data cp110_comphy_phy_mux_data[] = {
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */
- {PHY_TYPE_SATA1, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */
- {PHY_TYPE_SATA0, 0x4} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */
- {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1},
- {PHY_TYPE_SATA0, 0x4} } },
- {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */
- {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
- {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */
- {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2},
- {PHY_TYPE_SGMII1, 0x1} } },
- {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */
- {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } },
-};
-
-struct comphy_mux_data cp110_comphy_pipe_mux_data[] = {
- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */
- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2},
- {PHY_TYPE_PEX0, 0x4} } },
- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */
- {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
- {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */
- {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } },
- {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */
- {PHY_TYPE_USB3_HOST1, 0x1},
- {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } },
- {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */
-};
-
static u32 polling_with_timeout(void __iomem *addr, u32 val,
u32 mask, unsigned long usec_timout)
{
@@ -121,128 +78,6 @@
return 0;
}
-static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base)
-{
- u32 mask, data, ret = 1;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
- void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
- void __iomem *addr;
-
- debug_enter();
- debug("stage: RFU configurations - hard reset comphy\n");
- /* RFU configurations - hard reset comphy */
- mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- mask |= COMMON_PHY_PHY_MODE_MASK;
- data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* release from hard reset */
- mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
- mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
- data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- mdelay(1);
-
- /* Start comphy Configuration */
- debug("stage: Comphy configuration\n");
- /* Set PIPE soft reset */
- mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
- data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
- /* Set PHY datapath width mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
- /* Set Data bus width USB mode for V0 */
- mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
- /* Set CORE_CLK output frequency for 250Mhz */
- mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
- data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
- /* Set PLL ready delay for 0x2 */
- reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
- 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
- HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
- /* Set reference clock to come from group 1 - 25Mhz */
- reg_set(hpipe_addr + HPIPE_MISC_REG,
- 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
- HPIPE_MISC_REFCLK_SEL_MASK);
- /* Set reference frequcency select - 0x2 */
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- /* Set PHY mode to USB - 0x5 */
- mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
- /* Set the amount of time spent in the LoZ state - set for 0x7 */
- reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
- 0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
- HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
- /* Set max PHY generation setting - 5Gbps */
- reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
- 0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
- HPIPE_INTERFACE_GEN_MAX_MASK);
- /* Set select data width 20Bit (SEL_BITS[2:0]) */
- reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
- HPIPE_LOOPBACK_SEL_MASK);
- /* select de-emphasize 3.5db */
- reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
- 0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
- HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
- /* override tx margining from the MAC */
- reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
- 0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
- HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
-
- /* Start analog paramters from ETP(HW) */
- debug("stage: Analog paramters from ETP(HW)\n");
- /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
- mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
- data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
- /* Set Override PHY DFE control pins for 0x1 */
- mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
- data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
- /* Set Spread Spectrum Clock Enable fot 0x1 */
- mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
- data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
- reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
- /* End of analog parameters */
-
- debug("stage: Comphy power up\n");
- /* Release from PIPE soft reset */
- reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
- 0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
- HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
-
- /* wait 15ms - for comphy calibration done */
- debug("stage: Check PLL\n");
- /* Read lane status */
- addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
- data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 15000);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
- pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
- ret = 0;
- }
-
- debug_exit();
- return ret;
-}
-
static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
u32 lane, u32 mode)
{
@@ -263,6 +98,35 @@
return pregs.regs[0] ? 0 : 1;
}
+/* This function performs RX training for all FFE possible values.
+ * We get the result for each FFE and eventually the best FFE will
+ * be used and set to the HW.
+ *
+ * Return '1' on succsess.
+ * Return '0' on failure.
+ */
+int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
+ u32 lane)
+{
+ int ret;
+ u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
+
+ debug_enter();
+
+ if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
+ pr_err("Comphy %d isn't configured to SFI\n", lane);
+ return 0;
+ }
+
+ /* Mode is not relevant for xfi training */
+ ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN,
+ ptr_chip_cfg->comphy_base_addr, lane, 0);
+
+ debug_exit();
+
+ return ret;
+}
+
static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
void __iomem *comphy_base_addr, int cp_index,
u32 type)
@@ -357,184 +221,6 @@
return ret;
}
-static int comphy_rxauii_power_up(u32 lane, void __iomem *hpipe_base,
- void __iomem *comphy_base)
-{
- u32 mask, data, ret = 1;
- void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
- void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
- void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
- void __iomem *addr;
-
- debug_enter();
- debug("stage: RFU configurations - hard reset comphy\n");
- /* RFU configurations - hard reset comphy */
- mask = COMMON_PHY_CFG1_PWR_UP_MASK;
- data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
- mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
- data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
- reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
- if (lane == 2) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET,
- COMMON_PHY_SD_CTRL1_RXAUI0_MASK);
- }
- if (lane == 4) {
- reg_set(comphy_base + COMMON_PHY_SD_CTRL1,
- 0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET,
- COMMON_PHY_SD_CTRL1_RXAUI1_MASK);
- }
-
- /* Select Baud Rate of Comphy And PD_PLL/Tx/Rx */
- mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
- data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
- data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
-
- /* release from hard reset */
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- /* Wait 1ms - until band gap and ref clock ready */
- mdelay(1);
-
- /* Start comphy Configuration */
- debug("stage: Comphy configuration\n");
- /* set reference clock */
- reg_set(hpipe_addr + HPIPE_MISC_REG,
- 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
- HPIPE_MISC_REFCLK_SEL_MASK);
- /* Power and PLL Control */
- mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
- data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
- mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
- data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
- reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
- /* Loopback register */
- reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
- 0x1 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK);
- /* rx control 1 */
- mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK;
- data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET;
- mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK;
- data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask);
- /* DTL Control */
- reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG,
- 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET,
- HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
-
- /* Set analog paramters from ETP(HW) */
- debug("stage: Analog paramters from ETP(HW)\n");
- /* SERDES External Configuration 2 */
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG,
- 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET,
- SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK);
- /* 0x7-DFE Resolution control */
- reg_set(hpipe_addr + HPIPE_DFE_REG0, 0x1 << HPIPE_DFE_RES_FORCE_OFFSET,
- HPIPE_DFE_RES_FORCE_MASK);
- /* 0xd-G1_Setting_0 */
- reg_set(hpipe_addr + HPIPE_G1_SET_0_REG,
- 0xd << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET,
- HPIPE_G1_SET_0_G1_TX_EMPH1_MASK);
- /* 0xE-G1_Setting_1 */
- mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
- data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET;
- mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
- data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
- /* 0xA-DFE_Reg3 */
- mask = HPIPE_DFE_F3_F5_DFE_EN_MASK;
- data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET;
- mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK;
- data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET;
- reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask);
-
- /* 0x111-G1_Setting_4 */
- mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK;
- data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET;
- reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask);
-
- debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n");
- /* SERDES External Configuration */
- mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK;
- data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET;
- mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask);
-
-
- /* check PLL rx & tx ready */
- addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
- data = SD_EXTERNAL_STATUS0_PLL_RX_MASK |
- SD_EXTERNAL_STATUS0_PLL_TX_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 15000);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
- pr_err("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n",
- (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK),
- (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK));
- ret = 0;
- }
-
- /* RX init */
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG,
- 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET,
- SD_EXTERNAL_CONFIG1_RX_INIT_MASK);
-
- /* check that RX init done */
- addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG;
- data = SD_EXTERNAL_STATUS0_RX_INIT_MASK;
- mask = data;
- data = polling_with_timeout(addr, data, mask, 100);
- if (data != 0) {
- debug("Read from reg = %p - value = 0x%x\n",
- sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data);
- pr_err("SD_EXTERNAL_STATUS0_RX_INIT is 0\n");
- ret = 0;
- }
-
- debug("stage: RF Reset\n");
- /* RF Reset */
- mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK;
- data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET;
- mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK;
- data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET;
- reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask);
-
- debug_exit();
- return ret;
-}
-
static void comphy_utmi_power_down(u32 utmi_index, void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr,
@@ -580,7 +266,8 @@
return;
}
-static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_base_addr,
+static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr,
+ void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr,
u32 utmi_phy_port)
@@ -598,27 +285,37 @@
/* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/
mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK;
data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET;
- reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask);
+ reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
/* Impedance Calibration Threshold Setting */
- reg_set(utmi_base_addr + UTMI_CALIB_CTRL_REG,
- 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
- UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
+ mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK;
+ data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET;
+ reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
+
+ /* Start Impedance and PLL Calibration */
+ mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK;
+ data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET);
+ mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK;
+ data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET);
+ reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
/* Set LS TX driver strength coarse control */
- mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
- data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
- /* Set LS TX driver fine adjustment */
+ mask = UTMI_TX_CH_CTRL_AMP_MASK;
+ data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
+ mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
+ data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
/* Enable SQ */
mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
- data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
+ data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
/* Enable analog squelch detect */
mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
- data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+ data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
+ mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK;
+ data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET;
reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
/* Set External squelch calibration number */
@@ -641,7 +338,8 @@
return;
}
-static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_base_addr,
+static int comphy_utmi_power_up(u32 utmi_index, void __iomem *utmi_pll_addr,
+ void __iomem *utmi_base_addr,
void __iomem *usb_cfg_addr,
void __iomem *utmi_cfg_addr, u32 utmi_phy_port)
{
@@ -660,7 +358,7 @@
UTMI_CTRL_STATUS0_TEST_SEL_MASK);
debug("stage: Polling for PLL and impedance calibration done, and PLL ready done\n");
- addr = utmi_base_addr + UTMI_CALIB_CTRL_REG;
+ addr = utmi_pll_addr + UTMI_CALIB_CTRL_REG;
data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK;
mask = data;
data = polling_with_timeout(addr, data, mask, 100);
@@ -679,7 +377,7 @@
ret = 0;
}
- addr = utmi_base_addr + UTMI_PLL_CTRL_REG;
+ addr = utmi_pll_addr + UTMI_PLL_CTRL_REG;
data = UTMI_PLL_CTRL_PLL_RDY_MASK;
mask = data;
data = polling_with_timeout(addr, data, mask, 100);
@@ -703,7 +401,7 @@
* the init split in 3 parts:
* 1. Power down transceiver and PLL
* 2. UTMI PHY configure
- * 3. Powe up transceiver and PLL
+ * 3. Power up transceiver and PLL
* Note: - Power down/up should be once for both UTMI PHYs
* - comphy_dedicated_phys_init call this function if at least there is
* one UTMI PHY exists in FDT blob. access to cp110_utmi_data[0] is
@@ -730,14 +428,16 @@
}
/* UTMI configure */
for (i = 0; i < utmi_phy_count; i++) {
- comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_base_addr,
+ comphy_utmi_phy_config(i, cp110_utmi_data[i].utmi_pll_addr,
+ cp110_utmi_data[i].utmi_base_addr,
cp110_utmi_data[i].usb_cfg_addr,
cp110_utmi_data[i].utmi_cfg_addr,
cp110_utmi_data[i].utmi_phy_port);
}
/* UTMI Power up */
for (i = 0; i < utmi_phy_count; i++) {
- if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_base_addr,
+ if (!comphy_utmi_power_up(i, cp110_utmi_data[i].utmi_pll_addr,
+ cp110_utmi_data[i].utmi_base_addr,
cp110_utmi_data[i].usb_cfg_addr,
cp110_utmi_data[i].utmi_cfg_addr,
cp110_utmi_data[i].utmi_phy_port)) {
@@ -770,45 +470,61 @@
void comphy_dedicated_phys_init(void)
{
struct utmi_phy_data cp110_utmi_data[MAX_UTMI_PHY_COUNT];
- int node;
- int i;
+ int node = -1;
+ int node_idx;
+ int parent = -1;
debug_enter();
debug("Initialize USB UTMI PHYs\n");
- /* Find the UTMI phy node in device tree and go over them */
- node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
- "marvell,mvebu-utmi-2.6.0");
+ for (node_idx = 0; node_idx < MAX_UTMI_PHY_COUNT;) {
+ /* Find the UTMI phy node in device tree */
+ node = fdt_node_offset_by_compatible(gd->fdt_blob, node,
+ "marvell,mvebu-utmi-2.6.0");
+ if (node <= 0)
+ break;
+
+ /* check if node is enabled */
+ if (!fdtdec_get_is_enabled(gd->fdt_blob, node))
+ continue;
+
+ parent = fdt_parent_offset(gd->fdt_blob, node);
+ if (parent <= 0)
+ break;
+
+ /* get base address of UTMI PLL */
+ cp110_utmi_data[node_idx].utmi_pll_addr =
+ (void __iomem *)fdtdec_get_addr_size_auto_noparent(
+ gd->fdt_blob, parent, "reg", 0, NULL, true);
+ if (!cp110_utmi_data[node_idx].utmi_pll_addr) {
+ pr_err("UTMI PHY PLL address is invalid\n");
+ continue;
+ }
- i = 0;
- while (node > 0) {
/* get base address of UTMI phy */
- cp110_utmi_data[i].utmi_base_addr =
+ cp110_utmi_data[node_idx].utmi_base_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 0, NULL, true);
- if (cp110_utmi_data[i].utmi_base_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].utmi_base_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
/* get usb config address */
- cp110_utmi_data[i].usb_cfg_addr =
+ cp110_utmi_data[node_idx].usb_cfg_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 1, NULL, true);
- if (cp110_utmi_data[i].usb_cfg_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].usb_cfg_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
/* get UTMI config address */
- cp110_utmi_data[i].utmi_cfg_addr =
+ cp110_utmi_data[node_idx].utmi_cfg_addr =
(void __iomem *)fdtdec_get_addr_size_auto_noparent(
gd->fdt_blob, node, "reg", 2, NULL, true);
- if (cp110_utmi_data[i].utmi_cfg_addr == NULL) {
+ if (!cp110_utmi_data[node_idx].utmi_cfg_addr) {
pr_err("UTMI PHY base address is invalid\n");
- i++;
continue;
}
@@ -816,70 +532,30 @@
* get the port number (to check if the utmi connected to
* host/device)
*/
- cp110_utmi_data[i].utmi_phy_port = fdtdec_get_int(
+ cp110_utmi_data[node_idx].utmi_phy_port = fdtdec_get_int(
gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID);
- if (cp110_utmi_data[i].utmi_phy_port == UTMI_PHY_INVALID) {
+ if (cp110_utmi_data[node_idx].utmi_phy_port ==
+ UTMI_PHY_INVALID) {
pr_err("UTMI PHY port type is invalid\n");
- i++;
continue;
}
- node = fdt_node_offset_by_compatible(
- gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0");
- i++;
+ /* count valid UTMI unit */
+ node_idx++;
}
- if (i > 0)
- comphy_utmi_phy_init(i, cp110_utmi_data);
+ if (node_idx > 0)
+ comphy_utmi_phy_init(node_idx, cp110_utmi_data);
debug_exit();
}
-static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
- struct comphy_map *serdes_map)
-{
- void __iomem *comphy_base_addr;
- struct comphy_map comphy_map_pipe_data[MAX_LANE_OPTIONS];
- struct comphy_map comphy_map_phy_data[MAX_LANE_OPTIONS];
- u32 lane, comphy_max_count;
-
- comphy_max_count = ptr_chip_cfg->comphy_lanes_count;
- comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
-
- /*
- * Copy the SerDes map configuration for PIPE map and PHY map
- * the comphy_mux_init modify the type of the lane if the type
- * is not valid because we have 2 selectores run the
- * comphy_mux_init twice and after that update the original
- * serdes_map
- */
- for (lane = 0; lane < comphy_max_count; lane++) {
- comphy_map_pipe_data[lane].type = serdes_map[lane].type;
- comphy_map_pipe_data[lane].speed = serdes_map[lane].speed;
- comphy_map_phy_data[lane].type = serdes_map[lane].type;
- comphy_map_phy_data[lane].speed = serdes_map[lane].speed;
- }
- ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data;
- comphy_mux_init(ptr_chip_cfg, comphy_map_phy_data,
- comphy_base_addr + COMMON_SELECTOR_PHY_OFFSET);
-
- ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data;
- comphy_mux_init(ptr_chip_cfg, comphy_map_pipe_data,
- comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET);
- /* Fix the type after check the PHY and PIPE configuration */
- for (lane = 0; lane < comphy_max_count; lane++) {
- if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) &&
- (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED))
- serdes_map[lane].type = PHY_TYPE_UNCONNECTED;
- }
-}
-
int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
struct comphy_map *serdes_map)
{
struct comphy_map *ptr_comphy_map;
void __iomem *comphy_base_addr, *hpipe_base_addr;
- u32 comphy_max_count, lane, ret = 0;
+ u32 comphy_max_count, lane, id, ret = 0;
u32 pcie_width = 0;
u32 mode;
@@ -889,13 +565,10 @@
comphy_base_addr = ptr_chip_cfg->comphy_base_addr;
hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
- /* Config Comphy mux configuration */
- comphy_mux_cp110_init(ptr_chip_cfg, serdes_map);
-
/* Check if the first 4 lanes configured as By-4 */
for (lane = 0, ptr_comphy_map = serdes_map; lane < 4;
lane++, ptr_comphy_map++) {
- if (ptr_comphy_map->type != PHY_TYPE_PEX0)
+ if (ptr_comphy_map->type != COMPHY_TYPE_PEX0)
break;
pcie_width++;
}
@@ -912,14 +585,18 @@
pcie_width = 1;
}
switch (ptr_comphy_map->type) {
- case PHY_TYPE_UNCONNECTED:
- case PHY_TYPE_IGNORE:
+ case COMPHY_TYPE_UNCONNECTED:
+ mode = COMPHY_TYPE_UNCONNECTED | COMPHY_CALLER_UBOOT;
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_OFF,
+ ptr_chip_cfg->comphy_base_addr,
+ lane, mode);
+ case COMPHY_TYPE_IGNORE:
continue;
break;
- case PHY_TYPE_PEX0:
- case PHY_TYPE_PEX1:
- case PHY_TYPE_PEX2:
- case PHY_TYPE_PEX3:
+ case COMPHY_TYPE_PEX0:
+ case COMPHY_TYPE_PEX1:
+ case COMPHY_TYPE_PEX2:
+ case COMPHY_TYPE_PEX3:
mode = COMPHY_FW_PCIE_FORMAT(pcie_width,
ptr_comphy_map->clk_src,
COMPHY_PCIE_MODE,
@@ -928,71 +605,61 @@
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SATA0:
- case PHY_TYPE_SATA1:
- case PHY_TYPE_SATA2:
- case PHY_TYPE_SATA3:
+ case COMPHY_TYPE_SATA0:
+ case COMPHY_TYPE_SATA1:
mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE);
ret = comphy_sata_power_up(lane, hpipe_base_addr,
comphy_base_addr,
ptr_chip_cfg->cp_index,
mode);
break;
- case PHY_TYPE_USB3_HOST0:
- case PHY_TYPE_USB3_HOST1:
- case PHY_TYPE_USB3_DEVICE:
- ret = comphy_usb3_power_up(lane, hpipe_base_addr,
- comphy_base_addr);
+ case COMPHY_TYPE_USB3_HOST0:
+ case COMPHY_TYPE_USB3_HOST1:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane,
+ mode);
break;
- case PHY_TYPE_SGMII0:
- case PHY_TYPE_SGMII1:
- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
- debug("Warning: ");
- debug("SGMII PHY speed in lane %d is invalid,",
- lane);
- debug(" set PHY speed to 1.25G\n");
- ptr_comphy_map->speed = PHY_SPEED_1_25G;
- }
-
- /*
- * UINIT_ID not relevant for SGMII0 and SGMII1 - will be
- * ignored by firmware
- */
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID0,
- ptr_comphy_map->speed);
+ case COMPHY_TYPE_USB3_DEVICE:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SGMII2:
- case PHY_TYPE_SGMII3:
- if (ptr_comphy_map->speed == PHY_SPEED_INVALID) {
+ case COMPHY_TYPE_SGMII0:
+ case COMPHY_TYPE_SGMII1:
+ case COMPHY_TYPE_SGMII2:
+ /* Calculate SGMII ID */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SGMII0;
+
+ if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) {
debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n",
lane);
- ptr_comphy_map->speed = PHY_SPEED_1_25G;
+ ptr_comphy_map->speed = COMPHY_SPEED_1_25G;
}
- mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE,
- COMPHY_UNIT_ID2,
+ mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_SFI:
- mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
- COMPHY_UNIT_ID0,
+ case COMPHY_TYPE_SFI0:
+ case COMPHY_TYPE_SFI1:
+ /* Calculate SFI id */
+ id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
+ mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
+ ptr_chip_cfg->comphy_base_addr, lane, mode);
+ break;
+ case COMPHY_TYPE_RXAUI0:
+ case COMPHY_TYPE_RXAUI1:
+ mode = COMPHY_FW_MODE_FORMAT(COMPHY_RXAUI_MODE);
+ ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
- case PHY_TYPE_RXAUI0:
- case PHY_TYPE_RXAUI1:
- ret = comphy_rxauii_power_up(lane, hpipe_base_addr,
- comphy_base_addr);
- break;
default:
debug("Unknown SerDes type, skip initialize SerDes %d\n",
lane);
@@ -1001,9 +668,9 @@
if (ret == 0) {
/*
* If interface wans't initialized, set the lane to
- * PHY_TYPE_UNCONNECTED state.
+ * COMPHY_TYPE_UNCONNECTED state.
*/
- ptr_comphy_map->type = PHY_TYPE_UNCONNECTED;
+ ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED;
pr_err("PLL is not locked - Failed to initialize lane %d\n",
lane);
}
diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h
deleted file mode 100644
index a692035..0000000
--- a/drivers/phy/marvell/comphy_hpipe.h
+++ /dev/null
@@ -1,660 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2015-2016 Marvell International Ltd.
- */
-
-#ifndef _COMPHY_HPIPE_H_
-#define _COMPHY_HPIPE_H_
-
-/* SerDes IP register */
-#define SD_EXTERNAL_CONFIG0_REG 0
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
-#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
- (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
-#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
- (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
-#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
-#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
- (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
-#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
- (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
-#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
-
-#define SD_EXTERNAL_CONFIG1_REG 0x4
-#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
-#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
-#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
-#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
-
-#define SD_EXTERNAL_CONFIG2_REG 0x8
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
-#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
- (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
-#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
- (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
-
-#define SD_EXTERNAL_STATUS0_REG 0x18
-#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
-#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
-#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
-#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
-#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
-#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET 6
-#define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \
- (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET)
-
-/* HPIPE register */
-#define HPIPE_PWR_PLL_REG 0x4
-#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
-#define HPIPE_PWR_PLL_REF_FREQ_MASK \
- (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
-#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
-#define HPIPE_PWR_PLL_PHY_MODE_MASK \
- (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
-
-#define HPIPE_KVCO_CALIB_CTRL_REG 0x8
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET 12
-#define HPIPE_KVCO_CALIB_CTRL_MAX_PLL_MASK \
- (0x1 << HPIPE_KVCO_CALIB_CTRL_MAX_PLL_OFFSET)
-
-#define HPIPE_CAL_REG1_REG 0xc
-#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
-#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
- (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
-#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
- (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
-
-#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018
-
-#define HPIPE_DFE_REG0 0x01C
-#define HPIPE_DFE_RES_FORCE_OFFSET 15
-#define HPIPE_DFE_RES_FORCE_MASK \
- (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
-
-#define HPIPE_DFE_F3_F5_REG 0x028
-#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
-#define HPIPE_DFE_F3_F5_DFE_EN_MASK \
- (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
-#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
-#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
- (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
-
-#define HPIPE_G1_SET_0_REG 0x034
-#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
-#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
- (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
- (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
-
-#define HPIPE_G1_SET_1_REG 0x038
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
-#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
-#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
-#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
-#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
-
-#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
-
-#define HPIPE_G2_SET_0_REG 0x3c
-#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
-#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
- (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
- (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
-
-#define HPIPE_G2_SET_1_REG 0x040
-#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
-#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
-#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
-#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
-#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
-
-#define HPIPE_G3_SET_0_REG 0x44
-#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
-#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
- (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
-#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
- (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
-#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
-#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
- (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
-#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
-#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
- (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
-
-#define HPIPE_G3_SET_1_REG 0x048
-#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
-#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
- (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
-#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
- (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
-#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
-#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
-#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
- (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
-#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
-#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
- (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
-#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
-#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
- (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
-
-#define HPIPE_LOOPBACK_REG 0x08c
-#define HPIPE_LOOPBACK_SEL_OFFSET 1
-#define HPIPE_LOOPBACK_SEL_MASK \
- (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
-
-#define HPIPE_SYNC_PATTERN_REG 0x090
-#define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10
-#define HPIPE_SYNC_PATTERN_TXD_SWAP_MASK \
- (0x1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET)
-#define HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET 11
-#define HPIPE_SYNC_PATTERN_RXD_SWAP_MASK \
- (0x1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET)
-
-#define HPIPE_INTERFACE_REG 0x94
-#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
-#define HPIPE_INTERFACE_GEN_MAX_MASK \
- (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
-#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
-#define HPIPE_INTERFACE_DET_BYPASS_MASK \
- (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
-#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
-#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
- (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
-
-#define HPIPE_ISOLATE_MODE_REG 0x98
-#define HPIPE_ISOLATE_MODE_GEN_RX_OFFSET 0
-#define HPIPE_ISOLATE_MODE_GEN_RX_MASK \
- (0xf << HPIPE_ISOLATE_MODE_GEN_RX_OFFSET)
-#define HPIPE_ISOLATE_MODE_GEN_TX_OFFSET 4
-#define HPIPE_ISOLATE_MODE_GEN_TX_MASK \
- (0xf << HPIPE_ISOLATE_MODE_GEN_TX_OFFSET)
-
-#define HPIPE_G1_SET_2_REG 0xf4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
- (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
-#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
- (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_MASK)
-
-#define HPIPE_VTHIMPCAL_CTRL_REG 0x104
-
-#define HPIPE_VDD_CAL_CTRL_REG 0x114
-#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
-#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
- (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
-
-#define HPIPE_VDD_CAL_0_REG 0x108
-#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
-#define HPIPE_CAL_VDD_CONT_MODE_MASK \
- (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
-
-#define HPIPE_PCIE_REG0 0x120
-#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
-#define HPIPE_PCIE_IDLE_SYNC_MASK \
- (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
-#define HPIPE_PCIE_SEL_BITS_OFFSET 13
-#define HPIPE_PCIE_SEL_BITS_MASK \
- (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
-
-#define HPIPE_LANE_ALIGN_REG 0x124
-#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
-#define HPIPE_LANE_ALIGN_OFF_MASK \
- (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
-
-#define HPIPE_MISC_REG 0x13C
-#define HPIPE_MISC_CLK100M_125M_OFFSET 4
-#define HPIPE_MISC_CLK100M_125M_MASK \
- (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
-#define HPIPE_MISC_ICP_FORCE_OFFSET 5
-#define HPIPE_MISC_ICP_FORCE_MASK \
- (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
-#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
-#define HPIPE_MISC_TXDCLK_2X_MASK \
- (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
-#define HPIPE_MISC_CLK500_EN_OFFSET 7
-#define HPIPE_MISC_CLK500_EN_MASK \
- (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
-#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
-#define HPIPE_MISC_REFCLK_SEL_MASK \
- (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
-
-#define HPIPE_RX_CONTROL_1_REG 0x140
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
-#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
- (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
-#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
- (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_REG 0x148
-#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
-#define HPIPE_PWR_CTR_RST_DFE_MASK \
- (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
-#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
-#define HPIPE_PWR_CTR_SFT_RST_MASK \
- (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
-
-#define HPIPE_SPD_DIV_FORCE_REG 0x154
-#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
-#define HPIPE_TXDIGCK_DIV_FORCE_MASK \
- (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
- (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
-#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
- (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
- (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
-#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
- (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
-
-#define HPIPE_PLLINTP_REG1 0x150
-
-#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
-#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
-#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
- (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
-#define HPIPE_SMAPLER_OFFSET 12
-#define HPIPE_SMAPLER_MASK \
- (0x1 << HPIPE_SMAPLER_OFFSET)
-
-#define HPIPE_TX_REG1_REG 0x174
-#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
-#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
- (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
-#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
-#define HPIPE_TX_REG1_SLC_EN_MASK \
- (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
-
-#define HPIPE_PWR_CTR_DTL_REG 0x184
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
-#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
-#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
-#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
-#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
- (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
-#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
- (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
- (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
-#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
- (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
-
-#define HPIPE_PHASE_CONTROL_REG 0x188
-#define HPIPE_OS_PH_OFFSET_OFFSET 0
-#define HPIPE_OS_PH_OFFSET_MASK \
- (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
-#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
-#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
- (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
-#define HPIPE_OS_PH_VALID_OFFSET 8
-#define HPIPE_OS_PH_VALID_MASK \
- (0x1 << HPIPE_OS_PH_VALID_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
-#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
-#define HPIPE_TRAIN_PAT_NUM_MASK \
- (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
-
-#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
-#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \
- (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
-
-#define HPIPE_DME_REG 0x228
-#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
-#define HPIPE_DME_ETHERNET_MODE_MASK \
- (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
-#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
-#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
- (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
-#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
-#define HPIPE_TX_TRAIN_CTRL_G1_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
-#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
-#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
-#define HPIPE_TX_TRAIN_CTRL_G0_MASK \
- (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
-#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_TRX_TRAIN_TIMER_MASK \
- (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
-
-#define HPIPE_PCIE_REG1 0x288
-#define HPIPE_PCIE_REG3 0x290
-
-#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
-#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
-#define HPIPE_RX_TRAIN_TIMER_MASK \
- (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
-#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
-#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
-#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
-#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
-#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
-
-#define HPIPE_TX_TRAIN_REG 0x31C
-#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
-#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
- (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
-#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
- (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
-#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \
- (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
-#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
-#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
- (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
-
-#define HPIPE_CDR_CONTROL_REG 0x418
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
-#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
- (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
-#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
- (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
-#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
- (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
-
-#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
-#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
-#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
- (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
-#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
-#define HPIPE_TX_NUM_OF_PRESET_MASK \
- (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
-#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
-#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
- (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
-
-#define HPIPE_G1_SETTINGS_3_REG 0x440
-#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
-#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
- (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
-#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
- (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
-#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
- (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
-#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
- (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
-#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
- (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
-#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
-#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
- (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
-
-#define HPIPE_G1_SETTINGS_4_REG 0x444
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
-#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
- (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
-
-#define HPIPE_G2_SETTINGS_3_REG 0x448
-
-#define HPIPE_G2_SETTINGS_4_REG 0x44c
-#define HPIPE_G2_DFE_RES_OFFSET 8
-#define HPIPE_G2_DFE_RES_MASK \
- (0x3 << HPIPE_G2_DFE_RES_OFFSET)
-
-#define HPIPE_G3_SETTING_3_REG 0x450
-#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
-#define HPIPE_G3_FFE_CAP_SEL_MASK \
- (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
-#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
-#define HPIPE_G3_FFE_RES_SEL_MASK \
- (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
-#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
-#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
- (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
-#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
-#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
- (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
-#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
-#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
- (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
-
-#define HPIPE_G3_SETTING_4_REG 0x454
-#define HPIPE_G3_DFE_RES_OFFSET 8
-#define HPIPE_G3_DFE_RES_MASK \
- (0x3 << HPIPE_G3_DFE_RES_OFFSET)
-
-#define HPIPE_TX_PRESET_INDEX_REG 0x468
-#define HPIPE_TX_PRESET_INDEX_OFFSET 0
-#define HPIPE_TX_PRESET_INDEX_MASK \
- (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
-
-#define HPIPE_DFE_CONTROL_REG 0x470
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
-#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
- (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
-
-#define HPIPE_DFE_CTRL_28_REG 0x49C
-#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
-#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
- (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
-
-#define HPIPE_G1_SETTING_5_REG 0x538
-#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
-#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
- (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
-
-#define HPIPE_G3_SETTING_5_REG 0x548
-#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
-#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
- (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
-
-#define HPIPE_LANE_CONFIG0_REG 0x600
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
-#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
- (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
-
-#define HPIPE_LANE_CONFIG1_REG 0x604
-#define HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET 9
-#define HPIPE_LANE_CONFIG1_MAX_PLL_MASK \
- (0x1 << HPIPE_LANE_CONFIG1_MAX_PLL_OFFSET)
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET 10
-#define HPIPE_LANE_CONFIG1_GEN2_PLL_MASK \
- (0x1 << HPIPE_LANE_CONFIG1_GEN2_PLL_OFFSET)
-
-#define HPIPE_LANE_STATUS1_REG 0x60C
-#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
-#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
- (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
-
-#define HPIPE_LANE_CFG4_REG 0x620
-#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
-#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
- (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
-#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
- (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
-#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
-#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
- (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
-#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
-#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
- (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
-
-#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
-#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
-#define HPIPE_CFG_PHY_RC_EP_MASK \
- (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
-
-#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
-#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
-#define HPIPE_CFG_UPDATE_POLARITY_MASK \
- (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
-
-#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
-#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
- (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
-#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
- (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
-#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
- (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
-
-#define HPIPE_RST_CLK_CTRL_REG 0x704
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
-#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
-#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
-#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
-#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
- (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
-
-#define HPIPE_TST_MODE_CTRL_REG 0x708
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
-#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
- (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
-
-#define HPIPE_CLK_SRC_LO_REG 0x70c
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
- (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
-#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
- (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
-#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
- (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
-
-#define HPIPE_CLK_SRC_HI_REG 0x710
-#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
-#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
-#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
-#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
-#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
- (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
-
-#define HPIPE_GLOBAL_MISC_CTRL 0x718
-#define HPIPE_GLOBAL_PM_CTRL 0x740
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
-#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
- (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
-
-#endif /* _COMPHY_HPIPE_H_ */
-
diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c
index 9832755..10981d2 100644
--- a/drivers/phy/marvell/comphy_mux.c
+++ b/drivers/phy/marvell/comphy_mux.c
@@ -8,14 +8,13 @@
#include <asm/io.h>
#include "comphy_core.h"
-#include "comphy_hpipe.h"
/*
* comphy_mux_check_config()
* description: this function passes over the COMPHY lanes and check if the type
* is valid for specific lane. If the type is not valid,
* the function update the struct and set the type of the lane as
- * PHY_TYPE_UNCONNECTED
+ * COMPHY_TYPE_UNCONNECTED
*/
static void comphy_mux_check_config(struct comphy_mux_data *mux_data,
struct comphy_map *comphy_map_data, int comphy_max_lanes)
@@ -28,7 +27,7 @@
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
/* Don't check ignored COMPHYs */
- if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ if (comphy_map_data->type == COMPHY_TYPE_IGNORE)
continue;
mux_opt = mux_data->mux_values;
@@ -43,8 +42,8 @@
debug("lane number %d, had invalid type %d\n",
lane, comphy_map_data->type);
debug("set lane %d as type %d\n", lane,
- PHY_TYPE_UNCONNECTED);
- comphy_map_data->type = PHY_TYPE_UNCONNECTED;
+ COMPHY_TYPE_UNCONNECTED);
+ comphy_map_data->type = COMPHY_TYPE_UNCONNECTED;
} else {
debug("lane number %d, has type %d\n",
lane, comphy_map_data->type);
@@ -88,7 +87,7 @@
for (lane = 0; lane < comphy_max_lanes;
lane++, comphy_map_data++, mux_data++) {
- if (comphy_map_data->type == PHY_TYPE_IGNORE)
+ if (comphy_map_data->type == COMPHY_TYPE_IGNORE)
continue;
/*
diff --git a/drivers/phy/marvell/utmi_phy.h b/drivers/phy/marvell/utmi_phy.h
index 682a3ac..8a570ba 100644
--- a/drivers/phy/marvell/utmi_phy.h
+++ b/drivers/phy/marvell/utmi_phy.h
@@ -38,6 +38,12 @@
#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8
#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \
(0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
+#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13
+#define UTMI_CALIB_CTRL_IMPCAL_START_MASK \
+ (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET)
+#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22
+#define UTMI_CALIB_CTRL_PLLCAL_START_MASK \
+ (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET)
#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23
#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
@@ -45,15 +51,21 @@
#define UTMI_CALIB_CTRL_PLLCAL_DONE_MASK \
(0x1 << UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET)
-#define UTMI_TX_CH_CTRL_REG 0xC
+#define UTMI_TX_CH_CTRL_REG 0x0
#define UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET 12
#define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET)
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16
#define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK \
(0xf << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET)
+#define UTMI_TX_CH_CTRL_AMP_OFFSET 20
+#define UTMI_TX_CH_CTRL_AMP_MASK \
+ (0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
-#define UTMI_RX_CH_CTRL0_REG 0x14
+#define UTMI_RX_CH_CTRL0_REG 0x8
+#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8
+#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK \
+ (0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET)
#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
@@ -61,15 +73,15 @@
#define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK \
(0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET)
-#define UTMI_RX_CH_CTRL1_REG 0x18
+#define UTMI_RX_CH_CTRL1_REG 0xc
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK \
- (0x3 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
+ (0x7 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET)
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3
#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK \
(0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET)
-#define UTMI_CTRL_STATUS0_REG 0x24
+#define UTMI_CTRL_STATUS0_REG 0x18
#define UTMI_CTRL_STATUS0_SUSPENDM_OFFSET 22
#define UTMI_CTRL_STATUS0_SUSPENDM_MASK \
(0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET)
@@ -77,7 +89,7 @@
#define UTMI_CTRL_STATUS0_TEST_SEL_MASK \
(0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET)
-#define UTMI_CHGDTC_CTRL_REG 0x38
+#define UTMI_CHGDTC_CTRL_REG 0x2c
#define UTMI_CHGDTC_CTRL_VDAT_OFFSET 8
#define UTMI_CHGDTC_CTRL_VDAT_MASK \
(0x3 << UTMI_CHGDTC_CTRL_VDAT_OFFSET)
diff --git a/drivers/pinctrl/nxp/pinctrl-imx5.c b/drivers/pinctrl/nxp/pinctrl-imx5.c
index 71e0c94..b32b748 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx5.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx5.c
@@ -10,7 +10,7 @@
#include "pinctrl-imx.h"
-static struct imx_pinctrl_soc_info imx5_pinctrl_soc_info __attribute__((section(".data")));
+static struct imx_pinctrl_soc_info imx5_pinctrl_soc_info __section(".data");
static int imx5_pinctrl_probe(struct udevice *dev)
{
diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c
index 8301413..77ddb8e 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx7.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx7.c
@@ -9,7 +9,7 @@
#include "pinctrl-imx.h"
-static struct imx_pinctrl_soc_info imx7_pinctrl_soc_info __attribute__((section(".data")));
+static struct imx_pinctrl_soc_info imx7_pinctrl_soc_info __section(".data");
static struct imx_pinctrl_soc_info imx7_lpsr_pinctrl_soc_info = {
.flags = ZERO_OFFSET_VALID,
diff --git a/drivers/pinctrl/nxp/pinctrl-imx8m.c b/drivers/pinctrl/nxp/pinctrl-imx8m.c
index 99c6d01..6ea66a0 100644
--- a/drivers/pinctrl/nxp/pinctrl-imx8m.c
+++ b/drivers/pinctrl/nxp/pinctrl-imx8m.c
@@ -8,7 +8,7 @@
#include "pinctrl-imx.h"
-static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info __attribute__((section(".data")));
+static struct imx_pinctrl_soc_info imx8mq_pinctrl_soc_info __section(".data");
static int imx8mq_pinctrl_probe(struct udevice *dev)
{
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 48bdd0f..7af6c5f 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -295,7 +295,7 @@
func->npins = 0;
for (n = 0; n < count; n++, pins++) {
offset = fdt32_to_cpu(pins->reg);
- if (offset < 0 || offset > pdata->offset) {
+ if (offset > pdata->offset) {
dev_err(dev, " invalid register offset 0x%x\n",
offset);
continue;
@@ -335,6 +335,10 @@
phys_addr_t reg;
u32 offset, val, mask, bit_pos, val_pos, mask_pos, submask;
+ /* If function mask is null, needn't enable it. */
+ if (!pdata->mask)
+ return 0;
+
npins_in_reg = pdata->width / priv->bits_per_pin;
func = single_allocate_function(dev, count * npins_in_reg);
if (IS_ERR(func))
@@ -344,7 +348,7 @@
func->npins = 0;
for (n = 0; n < count; n++, pins++) {
offset = fdt32_to_cpu(pins->reg);
- if (offset < 0 || offset > pdata->offset) {
+ if (offset > pdata->offset) {
dev_dbg(dev, " invalid register offset 0x%x\n",
offset);
continue;
@@ -469,6 +473,11 @@
priv->npins = size / (pdata->width / BITS_PER_BYTE);
if (pdata->bits_per_mux) {
+ if (!pdata->mask) {
+ dev_err(dev, "function mask needs to be non-zero\n");
+ return -EINVAL;
+ }
+
priv->bits_per_pin = fls(pdata->mask);
priv->npins *= (pdata->width / priv->bits_per_pin);
}
@@ -500,19 +509,13 @@
return -EINVAL;
}
- addr = dev_read_addr_size(dev, "reg", &size);
+ addr = dev_read_addr_size_index(dev, 0, &size);
if (addr == FDT_ADDR_T_NONE) {
- dev_err(dev, "failed to get base register size\n");
+ dev_err(dev, "failed to get base register address\n");
return -EINVAL;
}
pdata->offset = size - pdata->width / BITS_PER_BYTE;
-
- addr = dev_read_addr(dev);
- if (addr == FDT_ADDR_T_NONE) {
- dev_dbg(dev, "no valid base register address\n");
- return -EINVAL;
- }
pdata->base = addr;
ret = dev_read_u32(dev, "pinctrl-single,function-mask", &pdata->mask);
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 8fb9cba..35f10e2 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -5,57 +5,41 @@
depends on DM && ARCH_RMOBILE
default n if CPU_RZA1
help
- Enable support for clock present on Renesas RCar SoCs.
+ Support pin multiplexing control on Renesas SoCs.
+
+ These drivers are controlled by a device tree node which contains
+ both the GPIO definitions and pin control functions for each
+ available multiplex function.
config PINCTRL_PFC_R8A7790
bool "Renesas RCar Gen2 R8A7790 pin control driver"
depends on PINCTRL_PFC
help
- Support pin multiplexing control on Renesas RCar Gen3 R8A7790 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
+ Support pin multiplexing control on Renesas RCar Gen2 R8A7790 SoCs.
config PINCTRL_PFC_R8A7791
bool "Renesas RCar Gen2 R8A7791 pin control driver"
depends on PINCTRL_PFC
help
- Support pin multiplexing control on Renesas RCar Gen3 R8A7791 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
+ Support pin multiplexing control on Renesas RCar Gen2 R8A7791 SoCs.
config PINCTRL_PFC_R8A7792
bool "Renesas RCar Gen2 R8A7792 pin control driver"
depends on PINCTRL_PFC
help
- Support pin multiplexing control on Renesas RCar Gen3 R8A7792 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
+ Support pin multiplexing control on Renesas RCar Gen2 R8A7792 SoCs.
config PINCTRL_PFC_R8A7793
bool "Renesas RCar Gen2 R8A7793 pin control driver"
depends on PINCTRL_PFC
help
- Support pin multiplexing control on Renesas RCar Gen3 R8A7793 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
+ Support pin multiplexing control on Renesas RCar Gen2 R8A7793 SoCs.
config PINCTRL_PFC_R8A7794
bool "Renesas RCar Gen2 R8A7794 pin control driver"
depends on PINCTRL_PFC
help
- Support pin multiplexing control on Renesas RCar Gen3 R8A7794 SoCs.
-
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
+ Support pin multiplexing control on Renesas RCar Gen2 R8A7794 SoCs.
config PINCTRL_PFC_R8A774A1
bool "Renesas RZ/G2 R8A774A1 pin control driver"
@@ -63,110 +47,66 @@
help
Support pin multiplexing control on Renesas RZ/G2M R8A774A1 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A774B1
bool "Renesas RZ/G2 R8A774B1 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZ/G2N R8A774B1 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A774C0
bool "Renesas RZ/G2 R8A774C0 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZ/G2E R8A774C0 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A774E1
bool "Renesas RZ/G2 R8A774E1 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RZ/G2H R8A774E1 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A7795
bool "Renesas RCar Gen3 R8A7795 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7795 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A7796
bool "Renesas RCar Gen3 R8A7796 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A7796 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A77965
bool "Renesas RCar Gen3 R8A77965 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77965 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A77970
bool "Renesas RCar Gen3 R8A77970 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A77980
bool "Renesas RCar Gen3 R8A77980 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77980 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A77990
bool "Renesas RCar Gen3 R8A77990 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77990 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R8A77995
bool "Renesas RCar Gen3 R8A77995 pin control driver"
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77995 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
config PINCTRL_PFC_R7S72100
bool "Renesas RZ/A1 R7S72100 pin control driver"
depends on CPU_RZA1
@@ -174,8 +114,4 @@
help
Support pin multiplexing control on Renesas RZ/A1 R7S72100 SoCs.
- The driver is controlled by a device tree node which contains both
- the GPIO definitions and pin control functions for each available
- multiplex function.
-
endif
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 07fcc3d..2498eb5 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -131,14 +131,25 @@
return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
}
-void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
+static void sh_pfc_unlock_reg(struct sh_pfc *pfc, u32 reg, u32 data)
{
- void __iomem *unlock_reg =
- (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
+ u32 unlock;
- if (pfc->info->unlock_reg)
- sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
+ if (!pfc->info->unlock_reg)
+ return;
+ if (pfc->info->unlock_reg >= 0x80000000UL)
+ unlock = pfc->info->unlock_reg;
+ else
+ /* unlock_reg is a mask */
+ unlock = reg & ~pfc->info->unlock_reg;
+
+ sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)unlock, 32, ~data);
+}
+
+void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
+{
+ sh_pfc_unlock_reg(pfc, reg, data);
sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
}
@@ -168,8 +179,6 @@
unsigned int field, u32 value)
{
void __iomem *mapped_reg;
- void __iomem *unlock_reg =
- (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
unsigned int pos;
u32 mask, data;
@@ -186,9 +195,7 @@
data &= mask;
data |= value;
- if (pfc->info->unlock_reg)
- sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
-
+ sh_pfc_unlock_reg(pfc, crp->reg, data);
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
@@ -679,8 +686,6 @@
unsigned int size;
unsigned int step;
void __iomem *reg;
- void __iomem *unlock_reg =
- (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
u32 val;
reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
@@ -701,9 +706,7 @@
val &= ~GENMASK(offset + 4 - 1, offset);
val |= strength << offset;
- if (unlock_reg)
- sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
-
+ sh_pfc_unlock_reg(pfc, (uintptr_t)reg, val);
sh_pfc_write_raw_reg(reg, 32, val);
return 0;
@@ -743,8 +746,6 @@
{
struct sh_pfc *pfc = pmx->pfc;
void __iomem *pocctrl;
- void __iomem *unlock_reg =
- (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
u32 addr, val;
int bit, ret;
@@ -790,9 +791,7 @@
else
val &= ~BIT(bit);
- if (unlock_reg)
- sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
-
+ sh_pfc_unlock_reg(pfc, addr, val);
sh_pfc_write_raw_reg(pocctrl, 32, val);
break;
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index f563916..d5a245f 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -284,7 +284,7 @@
const struct pinmux_irq *gpio_irq;
unsigned int gpio_irq_size;
- u32 unlock_reg;
+ u32 unlock_reg; /* can be literal address or mask */
};
u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index a0fd980..99b3f9a 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -72,4 +72,11 @@
help
Generic power domain implementation for TI devices implementing the
TI SCI protocol.
+
+config TI_POWER_DOMAIN
+ bool "Enable the TI K3 Power domain driver"
+ depends on POWER_DOMAIN && ARCH_K3
+ help
+ Generic power domain implementation for TI K3 devices.
+
endmenu
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 45bf9f6..3d1e5f0 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -14,3 +14,4 @@
obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
diff --git a/drivers/power/domain/ti-power-domain.c b/drivers/power/domain/ti-power-domain.c
new file mode 100644
index 0000000..b45e9b8
--- /dev/null
+++ b/drivers/power/domain/ti-power-domain.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments power domain driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <power-domain-uclass.h>
+#include <soc.h>
+#include <k3-dev.h>
+#include <linux/iopoll.h>
+
+#define PSC_PTCMD 0x120
+#define PSC_PTSTAT 0x128
+#define PSC_PDSTAT 0x200
+#define PSC_PDCTL 0x300
+#define PSC_MDSTAT 0x800
+#define PSC_MDCTL 0xa00
+
+#define PDCTL_STATE_MASK 0x1
+#define PDCTL_STATE_OFF 0x0
+#define PDCTL_STATE_ON 0x1
+
+#define MDSTAT_STATE_MASK 0x3f
+#define MDSTAT_BUSY_MASK 0x30
+#define MDSTAT_STATE_SWRSTDISABLE 0x0
+#define MDSTAT_STATE_ENABLE 0x3
+
+#define LPSC_TIMEOUT 1000
+#define PD_TIMEOUT 1000
+
+static u32 psc_read(struct ti_psc *psc, u32 reg)
+{
+ u32 val;
+
+ val = readl(psc->base + reg);
+ debug("%s: 0x%x from %p\n", __func__, val, psc->base + reg);
+ return val;
+}
+
+static void psc_write(u32 val, struct ti_psc *psc, u32 reg)
+{
+ debug("%s: 0x%x to %p\n", __func__, val, psc->base + reg);
+ writel(val, psc->base + reg);
+}
+
+static u32 pd_read(struct ti_pd *pd, u32 reg)
+{
+ return psc_read(pd->psc, reg + 4 * pd->id);
+}
+
+static void pd_write(u32 val, struct ti_pd *pd, u32 reg)
+{
+ psc_write(val, pd->psc, reg + 4 * pd->id);
+}
+
+static u32 lpsc_read(struct ti_lpsc *lpsc, u32 reg)
+{
+ return psc_read(lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static void lpsc_write(u32 val, struct ti_lpsc *lpsc, u32 reg)
+{
+ psc_write(val, lpsc->psc, reg + 4 * lpsc->id);
+}
+
+static const struct soc_attr ti_k3_soc_pd_data[] = {
+#if IS_ENABLED(CONFIG_SOC_K3_J721E)
+ {
+ .family = "J721E",
+ .data = &j721e_pd_platdata,
+ },
+ {
+ .family = "J7200",
+ .data = &j7200_pd_platdata,
+ },
+#endif
+ { /* sentinel */ }
+};
+
+static int ti_power_domain_probe(struct udevice *dev)
+{
+ struct ti_k3_pd_platdata *data = dev_get_priv(dev);
+ const struct soc_attr *soc_match_data;
+ const struct ti_k3_pd_platdata *pdata;
+
+ printf("%s(dev=%p)\n", __func__, dev);
+
+ if (!data)
+ return -ENOMEM;
+
+ soc_match_data = soc_device_match(ti_k3_soc_pd_data);
+ if (!soc_match_data)
+ return -ENODEV;
+
+ pdata = (const struct ti_k3_pd_platdata *)soc_match_data->data;
+
+ data->psc = pdata->psc;
+ data->pd = pdata->pd;
+ data->lpsc = pdata->lpsc;
+ data->devs = pdata->devs;
+ data->num_psc = pdata->num_psc;
+ data->num_pd = pdata->num_pd;
+ data->num_lpsc = pdata->num_lpsc;
+ data->num_devs = pdata->num_devs;
+
+ return 0;
+}
+
+static int ti_pd_wait(struct ti_pd *pd)
+{
+ u32 ptstat;
+ int ret;
+
+ ret = readl_poll_timeout(pd->psc->base + PSC_PTSTAT, ptstat,
+ !(ptstat & BIT(pd->id)), PD_TIMEOUT);
+
+ if (ret)
+ printf("%s: psc%d, pd%d failed to transition.\n", __func__,
+ pd->psc->id, pd->id);
+
+ return ret;
+}
+
+static void ti_pd_transition(struct ti_pd *pd)
+{
+ psc_write(BIT(pd->id), pd->psc, PSC_PTCMD);
+}
+
+u8 ti_pd_state(struct ti_pd *pd)
+{
+ return pd_read(pd, PSC_PDCTL) & PDCTL_STATE_MASK;
+}
+
+static int ti_pd_get(struct ti_pd *pd)
+{
+ u32 pdctl;
+ int ret;
+
+ pd->usecount++;
+
+ if (pd->usecount > 1)
+ return 0;
+
+ if (pd->depend) {
+ ret = ti_pd_get(pd->depend);
+ if (ret)
+ return ret;
+ ti_pd_transition(pd->depend);
+ ret = ti_pd_wait(pd->depend);
+ if (ret)
+ return ret;
+ }
+
+ pdctl = pd_read(pd, PSC_PDCTL);
+
+ if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_ON)
+ return 0;
+
+ debug("%s: enabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+ pdctl &= ~PDCTL_STATE_MASK;
+ pdctl |= PDCTL_STATE_ON;
+
+ pd_write(pdctl, pd, PSC_PDCTL);
+
+ return 0;
+}
+
+static int ti_pd_put(struct ti_pd *pd)
+{
+ u32 pdctl;
+ int ret;
+
+ pd->usecount--;
+
+ if (pd->usecount > 0)
+ return 0;
+
+ pdctl = pd_read(pd, PSC_PDCTL);
+ if ((pdctl & PDCTL_STATE_MASK) == PDCTL_STATE_OFF)
+ return 0;
+
+ pdctl &= ~PDCTL_STATE_MASK;
+ pdctl |= PDCTL_STATE_OFF;
+
+ debug("%s: disabling psc:%d, pd:%d\n", __func__, pd->psc->id, pd->id);
+
+ pd_write(pdctl, pd, PSC_PDCTL);
+
+ if (pd->depend) {
+ ti_pd_transition(pd);
+ ret = ti_pd_wait(pd);
+ if (ret)
+ return ret;
+
+ ret = ti_pd_put(pd->depend);
+ if (ret)
+ return ret;
+ ti_pd_transition(pd->depend);
+ ret = ti_pd_wait(pd->depend);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ti_lpsc_wait(struct ti_lpsc *lpsc)
+{
+ u32 mdstat;
+ int ret;
+
+ ret = readl_poll_timeout(lpsc->psc->base + PSC_MDSTAT + lpsc->id * 4,
+ mdstat,
+ !(mdstat & MDSTAT_BUSY_MASK), LPSC_TIMEOUT);
+
+ if (ret)
+ printf("%s: module %d failed to transition.\n", __func__,
+ lpsc->id);
+
+ return ret;
+}
+
+u8 lpsc_get_state(struct ti_lpsc *lpsc)
+{
+ return lpsc_read(lpsc, PSC_MDCTL) & MDSTAT_STATE_MASK;
+}
+
+int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state)
+{
+ struct ti_pd *psc_pd;
+ int ret;
+ u32 mdctl;
+
+ psc_pd = lpsc->pd;
+
+ if (state == MDSTAT_STATE_ENABLE) {
+ lpsc->usecount++;
+ if (lpsc->usecount > 1)
+ return 0;
+ } else {
+ lpsc->usecount--;
+ if (lpsc->usecount >= 1)
+ return 0;
+ }
+
+ debug("%s: transitioning psc:%d, lpsc:%d to %x\n", __func__,
+ lpsc->psc->id, lpsc->id, state);
+
+ if (lpsc->depend)
+ ti_lpsc_transition(lpsc->depend, state);
+
+ mdctl = lpsc_read(lpsc, PSC_MDCTL);
+ if ((mdctl & MDSTAT_STATE_MASK) == state)
+ return 0;
+
+ if (state == MDSTAT_STATE_ENABLE)
+ ti_pd_get(psc_pd);
+ else
+ ti_pd_put(psc_pd);
+
+ mdctl &= ~MDSTAT_STATE_MASK;
+ mdctl |= state;
+
+ lpsc_write(mdctl, lpsc, PSC_MDCTL);
+
+ ti_pd_transition(psc_pd);
+ ret = ti_pd_wait(psc_pd);
+ if (ret)
+ return ret;
+
+ return ti_lpsc_wait(lpsc);
+}
+
+static int ti_power_domain_transition(struct power_domain *pd, u8 state)
+{
+ struct ti_lpsc *lpsc = pd->priv;
+
+ return ti_lpsc_transition(lpsc, state);
+}
+
+static int ti_power_domain_on(struct power_domain *pd)
+{
+ debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id);
+
+ return ti_power_domain_transition(pd, MDSTAT_STATE_ENABLE);
+}
+
+static int ti_power_domain_off(struct power_domain *pd)
+{
+ debug("%s(pd=%p, id=%lu)\n", __func__, pd, pd->id);
+
+ return ti_power_domain_transition(pd, MDSTAT_STATE_SWRSTDISABLE);
+}
+
+static struct ti_lpsc *lpsc_lookup(struct ti_k3_pd_platdata *data, int id)
+{
+ int idx;
+
+ for (idx = 0; idx < data->num_devs; idx++)
+ if (data->devs[idx].id == id)
+ return data->devs[idx].lpsc;
+
+ return NULL;
+}
+
+static int ti_power_domain_of_xlate(struct power_domain *pd,
+ struct ofnode_phandle_args *args)
+{
+ struct ti_k3_pd_platdata *data = dev_get_priv(pd->dev);
+ struct ti_lpsc *lpsc;
+
+ debug("%s(power_domain=%p, id=%d)\n", __func__, pd, args->args[0]);
+
+ if (args->args_count < 1) {
+ printf("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ lpsc = lpsc_lookup(data, args->args[0]);
+ if (!lpsc) {
+ printf("%s: invalid dev-id: %d\n", __func__, args->args[0]);
+ return -ENOENT;
+ }
+
+ pd->id = lpsc->id;
+ pd->priv = lpsc;
+
+ return 0;
+}
+
+static int ti_power_domain_request(struct power_domain *pd)
+{
+ return 0;
+}
+
+static int ti_power_domain_free(struct power_domain *pd)
+{
+ return 0;
+}
+
+static const struct udevice_id ti_power_domain_of_match[] = {
+ { .compatible = "ti,sci-pm-domain" },
+ { /* sentinel */ }
+};
+
+static struct power_domain_ops ti_power_domain_ops = {
+ .on = ti_power_domain_on,
+ .off = ti_power_domain_off,
+ .of_xlate = ti_power_domain_of_xlate,
+ .request = ti_power_domain_request,
+ .rfree = ti_power_domain_free,
+};
+
+U_BOOT_DRIVER(ti_pm_domains) = {
+ .name = "ti-pm-domains",
+ .id = UCLASS_POWER_DOMAIN,
+ .of_match = ti_power_domain_of_match,
+ .probe = ti_power_domain_probe,
+ .priv_auto = sizeof(struct ti_k3_pd_platdata),
+ .ops = &ti_power_domain_ops,
+};
diff --git a/drivers/power/pmic/pmic_tps62362.c b/drivers/power/pmic/pmic_tps62362.c
index 76fd14d..59190d6 100644
--- a/drivers/power/pmic/pmic_tps62362.c
+++ b/drivers/power/pmic/pmic_tps62362.c
@@ -11,7 +11,7 @@
#include <power/tps62362.h>
#if CONFIG_IS_ENABLED(DM_I2C)
-struct udevice *tps62362_dev __attribute__((section(".data"))) = NULL;
+struct udevice *tps62362_dev __section(".data") = NULL;
#endif
/**
diff --git a/drivers/power/pmic/pmic_tps65217.c b/drivers/power/pmic/pmic_tps65217.c
index 54b5bed..c7f532d 100644
--- a/drivers/power/pmic/pmic_tps65217.c
+++ b/drivers/power/pmic/pmic_tps65217.c
@@ -8,7 +8,7 @@
#include <i2c.h>
#include <power/tps65217.h>
-struct udevice *tps65217_dev __attribute__((section(".data"))) = NULL;
+struct udevice *tps65217_dev __section(".data") = NULL;
/**
* tps65217_reg_read() - Generic function that can read a TPS65217 register
diff --git a/drivers/power/pmic/pmic_tps65218.c b/drivers/power/pmic/pmic_tps65218.c
index f8bae45..6717490 100644
--- a/drivers/power/pmic/pmic_tps65218.c
+++ b/drivers/power/pmic/pmic_tps65218.c
@@ -86,7 +86,7 @@
return 0;
}
#else
-struct udevice *tps65218_dev __attribute__((section(".data"))) = NULL;
+struct udevice *tps65218_dev __section(".data") = NULL;
int tps65218_reg_read(uchar dest_reg, uchar *dest_val)
{
diff --git a/drivers/power/pmic/pmic_tps65910.c b/drivers/power/pmic/pmic_tps65910.c
index 84a58c2..fcd0a65 100644
--- a/drivers/power/pmic/pmic_tps65910.c
+++ b/drivers/power/pmic/pmic_tps65910.c
@@ -8,7 +8,7 @@
#include <i2c.h>
#include <power/tps65910.h>
-struct udevice *tps65910_dev __attribute__((section(".data"))) = NULL;
+struct udevice *tps65910_dev __section(".data") = NULL;
static inline int tps65910_read_reg(int addr, uchar *buf)
{
diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c
index 4d2e730..fac9606 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -311,6 +311,17 @@
return ret;
}
+int regulator_unset(struct udevice *dev)
+{
+ struct dm_regulator_uclass_plat *uc_pdata;
+
+ uc_pdata = dev_get_uclass_plat(dev);
+ if (uc_pdata && uc_pdata->force_off)
+ return regulator_set_enable(dev, false);
+
+ return -EMEDIUMTYPE;
+}
+
static void regulator_show(struct udevice *dev, int ret)
{
struct dm_regulator_uclass_plat *uc_pdata;
@@ -443,6 +454,7 @@
uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on");
uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay",
0);
+ uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off");
node = dev_read_subnode(dev, "regulator-state-mem");
if (ofnode_valid(node)) {
@@ -495,6 +507,32 @@
return ret;
}
+int regulators_enable_boot_off(bool verbose)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_REGULATOR, &uc);
+ if (ret)
+ return ret;
+ for (uclass_first_device(UCLASS_REGULATOR, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ ret = regulator_unset(dev);
+ if (ret == -EMEDIUMTYPE) {
+ ret = 0;
+ continue;
+ }
+ if (verbose)
+ regulator_show(dev, ret);
+ if (ret == -ENOSYS)
+ ret = 0;
+ }
+
+ return ret;
+}
+
UCLASS_DRIVER(regulator) = {
.id = UCLASS_REGULATOR,
.name = "regulator",
diff --git a/drivers/pwm/cros_ec_pwm.c b/drivers/pwm/cros_ec_pwm.c
index 44f4105..4a39c31 100644
--- a/drivers/pwm/cros_ec_pwm.c
+++ b/drivers/pwm/cros_ec_pwm.c
@@ -80,5 +80,5 @@
.id = UCLASS_PWM,
.of_match = cros_ec_pwm_ids,
.ops = &cros_ec_pwm_ops,
- .priv_auto_alloc_size = sizeof(struct cros_ec_pwm_priv),
+ .priv_auto = sizeof(struct cros_ec_pwm_priv),
};
diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c
index 01212d6..b9813a3 100644
--- a/drivers/pwm/pwm-sifive.c
+++ b/drivers/pwm/pwm-sifive.c
@@ -38,6 +38,9 @@
#define PWM_SIFIVE_SIZE_PWMCMP 4
#define PWM_SIFIVE_CMPWIDTH 16
+#define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0
+#define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0xffff
+
DECLARE_GLOBAL_DATA_PTR;
struct pwm_sifive_regs {
@@ -77,7 +80,7 @@
*/
scale_pow = lldiv((uint64_t)priv->freq * period_ns, 1000000000);
scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf);
- val |= FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale);
+ val |= (FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale) | PWM_SIFIVE_PWMCFG_EN_ALWAYS);
/*
* The problem of output producing mixed setting as mentioned at top,
@@ -88,6 +91,7 @@
num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH);
frac = DIV_ROUND_CLOSEST_ULL(num, period_ns);
frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1);
+ frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac;
writel(val, priv->base + regs->cfg);
writel(frac, priv->base + regs->cmp0 + channel *
@@ -100,18 +104,15 @@
{
struct pwm_sifive_priv *priv = dev_get_priv(dev);
const struct pwm_sifive_regs *regs = &priv->data->regs;
- u32 val;
debug("%s: Enable '%s'\n", __func__, dev->name);
- if (enable) {
- val = readl(priv->base + regs->cfg);
- val |= PWM_SIFIVE_PWMCFG_EN_ALWAYS;
- writel(val, priv->base + regs->cfg);
- } else {
- writel(0, priv->base + regs->cmp0 + channel *
- PWM_SIFIVE_SIZE_PWMCMP);
- }
+ if (enable)
+ writel(PWM_SIFIVE_CHANNEL_ENABLE_VAL, priv->base +
+ regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
+ else
+ writel(PWM_SIFIVE_CHANNEL_DISABLE_VAL, priv->base +
+ regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP);
return 0;
}
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index a270e13..a79594d 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -54,9 +54,19 @@
config add support for the initialization of the external
SDRAM devices connected to DDR subsystem.
+config K3_DDRSS
+ bool "Enable K3 DDRSS support"
+ depends on RAM
+
+choice
+ depends on K3_DDRSS
+ prompt "K3 DDRSS Arch Support"
+
+ default K3_J721E_DDRSS if SOC_K3_J721E
+ default K3_AM64_DDRSS if SOC_K3_AM642
+
config K3_J721E_DDRSS
bool "Enable J721E DDRSS support"
- depends on RAM
help
The J721E DDR subsystem comprises DDR controller, DDR PHY and
wrapper logic to integrate these blocks in the device. The DDR
@@ -65,6 +75,18 @@
Enabling this config adds support for the DDR memory controller
on J721E family of SoCs.
+config K3_AM64_DDRSS
+ bool "Enable AM64 DDRSS support"
+ help
+ The AM64 DDR subsystem comprises DDR controller, DDR PHY and
+ wrapper logic to integrate these blocks in the device. The DDR
+ subsystem is used to provide an interface to external SDRAM
+ devices which can be utilized for storing program or data.
+ Enabling this config adds support for the DDR memory controller
+ on AM642 family of SoCs.
+
+endchoice
+
config IMXRT_SDRAM
bool "Enable i.MXRT SDRAM support"
depends on RAM
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
index 209a78c..5a39611 100644
--- a/drivers/ram/Makefile
+++ b/drivers/ram/Makefile
@@ -15,7 +15,7 @@
obj-$(CONFIG_K3_AM654_DDRSS) += k3-am654-ddrss.o
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_ASPEED) += aspeed/
-obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/
+obj-$(CONFIG_K3_DDRSS) += k3-ddrss/
obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
new file mode 100644
index 0000000..94202c9
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_IF_H
+#define LPDDR4_16BIT_IF_H
+
+#include <linux/types.h>
+
+#define LPDDR4_INTR_MAX_CS (2U)
+
+#define LPDDR4_INTR_CTL_REG_COUNT (423U)
+
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
+
+#define LPDDR4_INTR_PHY_REG_COUNT (1406U)
+
+typedef enum {
+ LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT = 0U,
+ LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH = 1U,
+ LPDDR4_INTR_TIMEOUT_ZQ_CALSTART = 2U,
+ LPDDR4_INTR_TIMEOUT_MRR_TEMP = 3U,
+ LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ = 4U,
+ LPDDR4_INTR_TIMEOUT_DFI_UPDATE = 5U,
+ LPDDR4_INTR_TIMEOUT_LP_WAKEUP = 6U,
+ LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX = 7U,
+ LPDDR4_INTR_ECC_ERROR = 8U,
+ LPDDR4_INTR_LP_DONE = 9U,
+ LPDDR4_INTR_LP_TIMEOUT = 10U,
+ LPDDR4_INTR_PORT_TIMEOUT = 11U,
+ LPDDR4_INTR_RFIFO_TIMEOUT = 12U,
+ LPDDR4_INTR_TRAINING_ZQ_STATUS = 13U,
+ LPDDR4_INTR_TRAINING_DQS_OSC_DONE = 14U,
+ LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE = 15U,
+ LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW = 16U,
+ LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT = 17U,
+ LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS = 18U,
+ LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS = 19U,
+ LPDDR4_INTR_USERIF_PORT_CMD_ERROR = 20U,
+ LPDDR4_INTR_USERIF_WRAP = 21U,
+ LPDDR4_INTR_USERIF_INVAL_SETTING = 22U,
+ LPDDR4_INTR_MISC_MRR_TRAFFIC = 23U,
+ LPDDR4_INTR_MISC_SW_REQ_MODE = 24U,
+ LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH = 25U,
+ LPDDR4_INTR_MISC_TEMP_ALERT = 26U,
+ LPDDR4_INTR_MISC_REFRESH_STATUS = 27U,
+ LPDDR4_INTR_BIST_DONE = 28U,
+ LPDDR4_INTR_CRC = 29U,
+ LPDDR4_INTR_DFI_UPDATE_ERROR = 30U,
+ LPDDR4_INTR_DFI_PHY_ERROR = 31U,
+ LPDDR4_INTR_DFI_BUS_ERROR = 32U,
+ LPDDR4_INTR_DFI_STATE_CHANGE = 33U,
+ LPDDR4_INTR_DFI_DLL_SYNC_DONE = 34U,
+ LPDDR4_INTR_DFI_TIMEOUT = 35U,
+ LPDDR4_INTR_DIMM = 36U,
+ LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE = 37U,
+ LPDDR4_INTR_FREQ_DFS_HW_TERMINATE = 38U,
+ LPDDR4_INTR_FREQ_DFS_HW_DONE = 39U,
+ LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE = 40U,
+ LPDDR4_INTR_FREQ_DFS_SW_TERMINATE = 41U,
+ LPDDR4_INTR_FREQ_DFS_SW_DONE = 42U,
+ LPDDR4_INTR_INIT_MEM_RESET_DONE = 43U,
+ LPDDR4_INTR_MC_INIT_DONE = 44U,
+ LPDDR4_INTR_INIT_POWER_ON_STATE = 45U,
+ LPDDR4_INTR_MRR_ERROR = 46U,
+ LPDDR4_INTR_MR_READ_DONE = 47U,
+ LPDDR4_INTR_MR_WRITE_DONE = 48U,
+ LPDDR4_INTR_PARITY_ERROR = 49U,
+ LPDDR4_INTR_LOR_BITS = 50U
+} lpddr4_intr_ctlinterrupt;
+
+typedef enum {
+ LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U,
+ LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 1U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 2U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 3U,
+ LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 4U,
+ LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 5U,
+ LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 6U,
+ LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 7U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 8U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 9U,
+ LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 10U,
+ LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 11U,
+ LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 12U,
+ LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 13U,
+ LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 14U,
+ LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 15U,
+ LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U,
+ LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT = 17U,
+ LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT = 18U,
+ LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT = 19U,
+ LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT = 20U,
+ LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT = 21U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT = 22U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT = 23U,
+ LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT = 24U,
+ LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT = 25U,
+ LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT = 26U,
+ LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT = 27U,
+ LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT = 28U
+} lpddr4_intr_phyindepinterrupt;
+
+#endif /* LPDDR4_16BIT_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
new file mode 100644
index 0000000..6c57dd9
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_OBJ_IF_H
+#define LPDDR4_16BIT_OBJ_IF_H
+
+#include "lpddr4_16bit_if.h"
+
+#endif /* LPDDR4_16BIT_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
new file mode 100644
index 0000000..5297348
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_STRUCTS_IF_H
+#define LPDDR4_16BIT_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_16bit_if.h"
+
+#endif /* LPDDR4_16BIT_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
new file mode 100644
index 0000000..f22a20a
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_512_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_512
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_512
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH 3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_512
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_513_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_513
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_514_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_514
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_514
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_514
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_515_READ_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_515
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_516_READ_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_516
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_516
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_516
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_516
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_517_READ_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_WIDTH 7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH 5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_518_READ_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_WIDTH 2U
+#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0
+
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH 3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_519_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_WIDTH 27U
+#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_519
+#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_520
+#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_521
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_522_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_522
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_523_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_523
+#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0
+
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_523
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0
+
+#define LPDDR4__DENALI_PHY_524_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_524
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0
+
+#define LPDDR4__DENALI_PHY_525_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_525
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_526_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_526
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_526
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0
+
+#define LPDDR4__DENALI_PHY_527_READ_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_527
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0
+
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_527
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH 9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_527
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_528_READ_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_528
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_528
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_528
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0
+
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_528
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_529_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS0_0__REG DENALI_PHY_529
+#define LPDDR4__PHY_ADR_CALVL_OBS0_0__FLD LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0
+
+#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_530
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0
+
+#define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_531
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0
+
+#define LPDDR4__DENALI_PHY_532_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_532
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0
+
+#define LPDDR4__DENALI_PHY_533_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_533
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0
+
+#define LPDDR4__DENALI_PHY_534_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_534
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0
+
+#define LPDDR4__DENALI_PHY_535_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_535
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0
+
+#define LPDDR4__DENALI_PHY_536_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_536
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0
+
+#define LPDDR4__DENALI_PHY_537_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_537
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0
+
+#define LPDDR4__DENALI_PHY_538_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_538
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0
+
+#define LPDDR4__DENALI_PHY_539_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_539
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0
+
+#define LPDDR4__DENALI_PHY_540_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_WIDTH 30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_540
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0
+
+#define LPDDR4__DENALI_PHY_541_READ_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_541
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_541
+#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0
+
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_541
+#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0
+
+#define LPDDR4__DENALI_PHY_542_READ_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_543_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_543
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_544_READ_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_544
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_544
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH 3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_544
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_545_READ_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_545
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_546_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_546
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_546
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_547_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_547
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_547
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_548_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_548
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_548
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_549_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_549
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_549
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_550_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_550
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_550
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_551
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH 6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_551
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_551
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_552_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_552
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH 10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_552
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET 0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_552
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_553_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_553
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_554_READ_MASK 0x0000010FU
+#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x0000010FU
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_554
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET 0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_554
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
new file mode 100644
index 0000000..df5ab95
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_768_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_768
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_768
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH 3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_768
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_769_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_769
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_770_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_770
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_770
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_770
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_771_READ_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_771
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_772_READ_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_772
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_772
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_772
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_772
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_773_READ_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_WIDTH 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_WIDTH 7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH 5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_774_READ_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_WIDTH 2U
+#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1
+
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH 3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_775_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_WIDTH 27U
+#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_775
+#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_776
+#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_777_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_777
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_778_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_778
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_779_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_779
+#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1
+
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_779
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1
+
+#define LPDDR4__DENALI_PHY_780_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_780
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1
+
+#define LPDDR4__DENALI_PHY_781_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_781
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_782_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_782
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_782
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1
+
+#define LPDDR4__DENALI_PHY_783_READ_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_783
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1
+
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_783
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH 9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_783
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_784_READ_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_784
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_784
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_784
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1
+
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH 3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_784
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_785_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS0_1__REG DENALI_PHY_785
+#define LPDDR4__PHY_ADR_CALVL_OBS0_1__FLD LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1
+
+#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_786
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1
+
+#define LPDDR4__DENALI_PHY_787_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_787
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1
+
+#define LPDDR4__DENALI_PHY_788_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_788
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1
+
+#define LPDDR4__DENALI_PHY_789_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_789
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1
+
+#define LPDDR4__DENALI_PHY_790_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_790
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1
+
+#define LPDDR4__DENALI_PHY_791_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_791
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1
+
+#define LPDDR4__DENALI_PHY_792_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_792
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1
+
+#define LPDDR4__DENALI_PHY_793_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_793
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1
+
+#define LPDDR4__DENALI_PHY_794_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_794
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1
+
+#define LPDDR4__DENALI_PHY_795_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_795
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1
+
+#define LPDDR4__DENALI_PHY_796_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_WIDTH 30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_796
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1
+
+#define LPDDR4__DENALI_PHY_797_READ_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_797
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_797
+#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1
+
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_797
+#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1
+
+#define LPDDR4__DENALI_PHY_798_READ_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_799_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_799
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_800_READ_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_800
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_WIDTH 11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_800
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH 3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_800
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_801_READ_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_801
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_802_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_802
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_802
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_803_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_803
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_803
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_804_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_804
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_804
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_805_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_805
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_805
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_806_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_806
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_806
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_807
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH 6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_807
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_807
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_808_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_808
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH 10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_808
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET 0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_808
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_809_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_809
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_810_READ_MASK 0x0000010FU
+#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x0000010FU
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_810
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET 0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_810
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
new file mode 100644
index 0000000..924013e
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2
+
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH 3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1024
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2
+
+#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1025
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH 7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH 3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1028
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_WIDTH 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_WIDTH 7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH 5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_WIDTH 2U
+#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH 3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2
+
+#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_WIDTH 27U
+#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1031
+#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2
+
+#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1032
+#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2
+
+#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1033
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2
+
+#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1034
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2
+
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2
+
+#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1036
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2
+
+#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1037
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2
+
+#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH 24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2
+
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH 2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH 9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET 0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2
+
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH 3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS0_2__REG DENALI_PHY_1041
+#define LPDDR4__PHY_ADR_CALVL_OBS0_2__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2
+
+#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1042
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2
+
+#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_WIDTH 32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1043
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2
+
+#define LPDDR4__DENALI_PHY_1044_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1044
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2
+
+#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1045
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2
+
+#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1046
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2
+
+#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1047
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2
+
+#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1048
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2
+
+#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1049
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2
+
+#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1050
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2
+
+#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_WIDTH 20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1051
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2
+
+#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_WIDTH 30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1052
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2
+
+#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH 10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2
+
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2
+
+#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1056_READ_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_WIDTH 11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1056
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH 3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1056
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2
+
+#define LPDDR4__DENALI_PHY_1063_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1063_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_WIDTH 11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2
+
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH 6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2
+
+#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH 8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2
+
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH 10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2
+
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET 0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2
+
+#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x0000010FU
+#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x0000010FU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH 4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET 0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
new file mode 100644
index 0000000..21e96c9
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
@@ -0,0 +1,1306 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_CTL_REGS_H_
+#define REG_LPDDR4_CTL_REGS_H_
+
+#include "lpddr4_ddr_controller_macros.h"
+#include "lpddr4_pi_macros.h"
+#include "lpddr4_data_slice_0_macros.h"
+#include "lpddr4_data_slice_1_macros.h"
+#include "lpddr4_address_slice_0_macros.h"
+#include "lpddr4_address_slice_1_macros.h"
+#include "lpddr4_address_slice_2_macros.h"
+#include "lpddr4_phy_core_macros.h"
+
+typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
+ volatile u32 DENALI_CTL_0;
+ volatile u32 DENALI_CTL_1;
+ volatile u32 DENALI_CTL_2;
+ volatile u32 DENALI_CTL_3;
+ volatile u32 DENALI_CTL_4;
+ volatile u32 DENALI_CTL_5;
+ volatile u32 DENALI_CTL_6;
+ volatile u32 DENALI_CTL_7;
+ volatile u32 DENALI_CTL_8;
+ volatile u32 DENALI_CTL_9;
+ volatile u32 DENALI_CTL_10;
+ volatile u32 DENALI_CTL_11;
+ volatile u32 DENALI_CTL_12;
+ volatile u32 DENALI_CTL_13;
+ volatile u32 DENALI_CTL_14;
+ volatile u32 DENALI_CTL_15;
+ volatile u32 DENALI_CTL_16;
+ volatile u32 DENALI_CTL_17;
+ volatile u32 DENALI_CTL_18;
+ volatile u32 DENALI_CTL_19;
+ volatile u32 DENALI_CTL_20;
+ volatile u32 DENALI_CTL_21;
+ volatile u32 DENALI_CTL_22;
+ volatile u32 DENALI_CTL_23;
+ volatile u32 DENALI_CTL_24;
+ volatile u32 DENALI_CTL_25;
+ volatile u32 DENALI_CTL_26;
+ volatile u32 DENALI_CTL_27;
+ volatile u32 DENALI_CTL_28;
+ volatile u32 DENALI_CTL_29;
+ volatile u32 DENALI_CTL_30;
+ volatile u32 DENALI_CTL_31;
+ volatile u32 DENALI_CTL_32;
+ volatile u32 DENALI_CTL_33;
+ volatile u32 DENALI_CTL_34;
+ volatile u32 DENALI_CTL_35;
+ volatile u32 DENALI_CTL_36;
+ volatile u32 DENALI_CTL_37;
+ volatile u32 DENALI_CTL_38;
+ volatile u32 DENALI_CTL_39;
+ volatile u32 DENALI_CTL_40;
+ volatile u32 DENALI_CTL_41;
+ volatile u32 DENALI_CTL_42;
+ volatile u32 DENALI_CTL_43;
+ volatile u32 DENALI_CTL_44;
+ volatile u32 DENALI_CTL_45;
+ volatile u32 DENALI_CTL_46;
+ volatile u32 DENALI_CTL_47;
+ volatile u32 DENALI_CTL_48;
+ volatile u32 DENALI_CTL_49;
+ volatile u32 DENALI_CTL_50;
+ volatile u32 DENALI_CTL_51;
+ volatile u32 DENALI_CTL_52;
+ volatile u32 DENALI_CTL_53;
+ volatile u32 DENALI_CTL_54;
+ volatile u32 DENALI_CTL_55;
+ volatile u32 DENALI_CTL_56;
+ volatile u32 DENALI_CTL_57;
+ volatile u32 DENALI_CTL_58;
+ volatile u32 DENALI_CTL_59;
+ volatile u32 DENALI_CTL_60;
+ volatile u32 DENALI_CTL_61;
+ volatile u32 DENALI_CTL_62;
+ volatile u32 DENALI_CTL_63;
+ volatile u32 DENALI_CTL_64;
+ volatile u32 DENALI_CTL_65;
+ volatile u32 DENALI_CTL_66;
+ volatile u32 DENALI_CTL_67;
+ volatile u32 DENALI_CTL_68;
+ volatile u32 DENALI_CTL_69;
+ volatile u32 DENALI_CTL_70;
+ volatile u32 DENALI_CTL_71;
+ volatile u32 DENALI_CTL_72;
+ volatile u32 DENALI_CTL_73;
+ volatile u32 DENALI_CTL_74;
+ volatile u32 DENALI_CTL_75;
+ volatile u32 DENALI_CTL_76;
+ volatile u32 DENALI_CTL_77;
+ volatile u32 DENALI_CTL_78;
+ volatile u32 DENALI_CTL_79;
+ volatile u32 DENALI_CTL_80;
+ volatile u32 DENALI_CTL_81;
+ volatile u32 DENALI_CTL_82;
+ volatile u32 DENALI_CTL_83;
+ volatile u32 DENALI_CTL_84;
+ volatile u32 DENALI_CTL_85;
+ volatile u32 DENALI_CTL_86;
+ volatile u32 DENALI_CTL_87;
+ volatile u32 DENALI_CTL_88;
+ volatile u32 DENALI_CTL_89;
+ volatile u32 DENALI_CTL_90;
+ volatile u32 DENALI_CTL_91;
+ volatile u32 DENALI_CTL_92;
+ volatile u32 DENALI_CTL_93;
+ volatile u32 DENALI_CTL_94;
+ volatile u32 DENALI_CTL_95;
+ volatile u32 DENALI_CTL_96;
+ volatile u32 DENALI_CTL_97;
+ volatile u32 DENALI_CTL_98;
+ volatile u32 DENALI_CTL_99;
+ volatile u32 DENALI_CTL_100;
+ volatile u32 DENALI_CTL_101;
+ volatile u32 DENALI_CTL_102;
+ volatile u32 DENALI_CTL_103;
+ volatile u32 DENALI_CTL_104;
+ volatile u32 DENALI_CTL_105;
+ volatile u32 DENALI_CTL_106;
+ volatile u32 DENALI_CTL_107;
+ volatile u32 DENALI_CTL_108;
+ volatile u32 DENALI_CTL_109;
+ volatile u32 DENALI_CTL_110;
+ volatile u32 DENALI_CTL_111;
+ volatile u32 DENALI_CTL_112;
+ volatile u32 DENALI_CTL_113;
+ volatile u32 DENALI_CTL_114;
+ volatile u32 DENALI_CTL_115;
+ volatile u32 DENALI_CTL_116;
+ volatile u32 DENALI_CTL_117;
+ volatile u32 DENALI_CTL_118;
+ volatile u32 DENALI_CTL_119;
+ volatile u32 DENALI_CTL_120;
+ volatile u32 DENALI_CTL_121;
+ volatile u32 DENALI_CTL_122;
+ volatile u32 DENALI_CTL_123;
+ volatile u32 DENALI_CTL_124;
+ volatile u32 DENALI_CTL_125;
+ volatile u32 DENALI_CTL_126;
+ volatile u32 DENALI_CTL_127;
+ volatile u32 DENALI_CTL_128;
+ volatile u32 DENALI_CTL_129;
+ volatile u32 DENALI_CTL_130;
+ volatile u32 DENALI_CTL_131;
+ volatile u32 DENALI_CTL_132;
+ volatile u32 DENALI_CTL_133;
+ volatile u32 DENALI_CTL_134;
+ volatile u32 DENALI_CTL_135;
+ volatile u32 DENALI_CTL_136;
+ volatile u32 DENALI_CTL_137;
+ volatile u32 DENALI_CTL_138;
+ volatile u32 DENALI_CTL_139;
+ volatile u32 DENALI_CTL_140;
+ volatile u32 DENALI_CTL_141;
+ volatile u32 DENALI_CTL_142;
+ volatile u32 DENALI_CTL_143;
+ volatile u32 DENALI_CTL_144;
+ volatile u32 DENALI_CTL_145;
+ volatile u32 DENALI_CTL_146;
+ volatile u32 DENALI_CTL_147;
+ volatile u32 DENALI_CTL_148;
+ volatile u32 DENALI_CTL_149;
+ volatile u32 DENALI_CTL_150;
+ volatile u32 DENALI_CTL_151;
+ volatile u32 DENALI_CTL_152;
+ volatile u32 DENALI_CTL_153;
+ volatile u32 DENALI_CTL_154;
+ volatile u32 DENALI_CTL_155;
+ volatile u32 DENALI_CTL_156;
+ volatile u32 DENALI_CTL_157;
+ volatile u32 DENALI_CTL_158;
+ volatile u32 DENALI_CTL_159;
+ volatile u32 DENALI_CTL_160;
+ volatile u32 DENALI_CTL_161;
+ volatile u32 DENALI_CTL_162;
+ volatile u32 DENALI_CTL_163;
+ volatile u32 DENALI_CTL_164;
+ volatile u32 DENALI_CTL_165;
+ volatile u32 DENALI_CTL_166;
+ volatile u32 DENALI_CTL_167;
+ volatile u32 DENALI_CTL_168;
+ volatile u32 DENALI_CTL_169;
+ volatile u32 DENALI_CTL_170;
+ volatile u32 DENALI_CTL_171;
+ volatile u32 DENALI_CTL_172;
+ volatile u32 DENALI_CTL_173;
+ volatile u32 DENALI_CTL_174;
+ volatile u32 DENALI_CTL_175;
+ volatile u32 DENALI_CTL_176;
+ volatile u32 DENALI_CTL_177;
+ volatile u32 DENALI_CTL_178;
+ volatile u32 DENALI_CTL_179;
+ volatile u32 DENALI_CTL_180;
+ volatile u32 DENALI_CTL_181;
+ volatile u32 DENALI_CTL_182;
+ volatile u32 DENALI_CTL_183;
+ volatile u32 DENALI_CTL_184;
+ volatile u32 DENALI_CTL_185;
+ volatile u32 DENALI_CTL_186;
+ volatile u32 DENALI_CTL_187;
+ volatile u32 DENALI_CTL_188;
+ volatile u32 DENALI_CTL_189;
+ volatile u32 DENALI_CTL_190;
+ volatile u32 DENALI_CTL_191;
+ volatile u32 DENALI_CTL_192;
+ volatile u32 DENALI_CTL_193;
+ volatile u32 DENALI_CTL_194;
+ volatile u32 DENALI_CTL_195;
+ volatile u32 DENALI_CTL_196;
+ volatile u32 DENALI_CTL_197;
+ volatile u32 DENALI_CTL_198;
+ volatile u32 DENALI_CTL_199;
+ volatile u32 DENALI_CTL_200;
+ volatile u32 DENALI_CTL_201;
+ volatile u32 DENALI_CTL_202;
+ volatile u32 DENALI_CTL_203;
+ volatile u32 DENALI_CTL_204;
+ volatile u32 DENALI_CTL_205;
+ volatile u32 DENALI_CTL_206;
+ volatile u32 DENALI_CTL_207;
+ volatile u32 DENALI_CTL_208;
+ volatile u32 DENALI_CTL_209;
+ volatile u32 DENALI_CTL_210;
+ volatile u32 DENALI_CTL_211;
+ volatile u32 DENALI_CTL_212;
+ volatile u32 DENALI_CTL_213;
+ volatile u32 DENALI_CTL_214;
+ volatile u32 DENALI_CTL_215;
+ volatile u32 DENALI_CTL_216;
+ volatile u32 DENALI_CTL_217;
+ volatile u32 DENALI_CTL_218;
+ volatile u32 DENALI_CTL_219;
+ volatile u32 DENALI_CTL_220;
+ volatile u32 DENALI_CTL_221;
+ volatile u32 DENALI_CTL_222;
+ volatile u32 DENALI_CTL_223;
+ volatile u32 DENALI_CTL_224;
+ volatile u32 DENALI_CTL_225;
+ volatile u32 DENALI_CTL_226;
+ volatile u32 DENALI_CTL_227;
+ volatile u32 DENALI_CTL_228;
+ volatile u32 DENALI_CTL_229;
+ volatile u32 DENALI_CTL_230;
+ volatile u32 DENALI_CTL_231;
+ volatile u32 DENALI_CTL_232;
+ volatile u32 DENALI_CTL_233;
+ volatile u32 DENALI_CTL_234;
+ volatile u32 DENALI_CTL_235;
+ volatile u32 DENALI_CTL_236;
+ volatile u32 DENALI_CTL_237;
+ volatile u32 DENALI_CTL_238;
+ volatile u32 DENALI_CTL_239;
+ volatile u32 DENALI_CTL_240;
+ volatile u32 DENALI_CTL_241;
+ volatile u32 DENALI_CTL_242;
+ volatile u32 DENALI_CTL_243;
+ volatile u32 DENALI_CTL_244;
+ volatile u32 DENALI_CTL_245;
+ volatile u32 DENALI_CTL_246;
+ volatile u32 DENALI_CTL_247;
+ volatile u32 DENALI_CTL_248;
+ volatile u32 DENALI_CTL_249;
+ volatile u32 DENALI_CTL_250;
+ volatile u32 DENALI_CTL_251;
+ volatile u32 DENALI_CTL_252;
+ volatile u32 DENALI_CTL_253;
+ volatile u32 DENALI_CTL_254;
+ volatile u32 DENALI_CTL_255;
+ volatile u32 DENALI_CTL_256;
+ volatile u32 DENALI_CTL_257;
+ volatile u32 DENALI_CTL_258;
+ volatile u32 DENALI_CTL_259;
+ volatile u32 DENALI_CTL_260;
+ volatile u32 DENALI_CTL_261;
+ volatile u32 DENALI_CTL_262;
+ volatile u32 DENALI_CTL_263;
+ volatile u32 DENALI_CTL_264;
+ volatile u32 DENALI_CTL_265;
+ volatile u32 DENALI_CTL_266;
+ volatile u32 DENALI_CTL_267;
+ volatile u32 DENALI_CTL_268;
+ volatile u32 DENALI_CTL_269;
+ volatile u32 DENALI_CTL_270;
+ volatile u32 DENALI_CTL_271;
+ volatile u32 DENALI_CTL_272;
+ volatile u32 DENALI_CTL_273;
+ volatile u32 DENALI_CTL_274;
+ volatile u32 DENALI_CTL_275;
+ volatile u32 DENALI_CTL_276;
+ volatile u32 DENALI_CTL_277;
+ volatile u32 DENALI_CTL_278;
+ volatile u32 DENALI_CTL_279;
+ volatile u32 DENALI_CTL_280;
+ volatile u32 DENALI_CTL_281;
+ volatile u32 DENALI_CTL_282;
+ volatile u32 DENALI_CTL_283;
+ volatile u32 DENALI_CTL_284;
+ volatile u32 DENALI_CTL_285;
+ volatile u32 DENALI_CTL_286;
+ volatile u32 DENALI_CTL_287;
+ volatile u32 DENALI_CTL_288;
+ volatile u32 DENALI_CTL_289;
+ volatile u32 DENALI_CTL_290;
+ volatile u32 DENALI_CTL_291;
+ volatile u32 DENALI_CTL_292;
+ volatile u32 DENALI_CTL_293;
+ volatile u32 DENALI_CTL_294;
+ volatile u32 DENALI_CTL_295;
+ volatile u32 DENALI_CTL_296;
+ volatile u32 DENALI_CTL_297;
+ volatile u32 DENALI_CTL_298;
+ volatile u32 DENALI_CTL_299;
+ volatile u32 DENALI_CTL_300;
+ volatile u32 DENALI_CTL_301;
+ volatile u32 DENALI_CTL_302;
+ volatile u32 DENALI_CTL_303;
+ volatile u32 DENALI_CTL_304;
+ volatile u32 DENALI_CTL_305;
+ volatile u32 DENALI_CTL_306;
+ volatile u32 DENALI_CTL_307;
+ volatile u32 DENALI_CTL_308;
+ volatile u32 DENALI_CTL_309;
+ volatile u32 DENALI_CTL_310;
+ volatile u32 DENALI_CTL_311;
+ volatile u32 DENALI_CTL_312;
+ volatile u32 DENALI_CTL_313;
+ volatile u32 DENALI_CTL_314;
+ volatile u32 DENALI_CTL_315;
+ volatile u32 DENALI_CTL_316;
+ volatile u32 DENALI_CTL_317;
+ volatile u32 DENALI_CTL_318;
+ volatile u32 DENALI_CTL_319;
+ volatile u32 DENALI_CTL_320;
+ volatile u32 DENALI_CTL_321;
+ volatile u32 DENALI_CTL_322;
+ volatile u32 DENALI_CTL_323;
+ volatile u32 DENALI_CTL_324;
+ volatile u32 DENALI_CTL_325;
+ volatile u32 DENALI_CTL_326;
+ volatile u32 DENALI_CTL_327;
+ volatile u32 DENALI_CTL_328;
+ volatile u32 DENALI_CTL_329;
+ volatile u32 DENALI_CTL_330;
+ volatile u32 DENALI_CTL_331;
+ volatile u32 DENALI_CTL_332;
+ volatile u32 DENALI_CTL_333;
+ volatile u32 DENALI_CTL_334;
+ volatile u32 DENALI_CTL_335;
+ volatile u32 DENALI_CTL_336;
+ volatile u32 DENALI_CTL_337;
+ volatile u32 DENALI_CTL_338;
+ volatile u32 DENALI_CTL_339;
+ volatile u32 DENALI_CTL_340;
+ volatile u32 DENALI_CTL_341;
+ volatile u32 DENALI_CTL_342;
+ volatile u32 DENALI_CTL_343;
+ volatile u32 DENALI_CTL_344;
+ volatile u32 DENALI_CTL_345;
+ volatile u32 DENALI_CTL_346;
+ volatile u32 DENALI_CTL_347;
+ volatile u32 DENALI_CTL_348;
+ volatile u32 DENALI_CTL_349;
+ volatile u32 DENALI_CTL_350;
+ volatile u32 DENALI_CTL_351;
+ volatile u32 DENALI_CTL_352;
+ volatile u32 DENALI_CTL_353;
+ volatile u32 DENALI_CTL_354;
+ volatile u32 DENALI_CTL_355;
+ volatile u32 DENALI_CTL_356;
+ volatile u32 DENALI_CTL_357;
+ volatile u32 DENALI_CTL_358;
+ volatile u32 DENALI_CTL_359;
+ volatile u32 DENALI_CTL_360;
+ volatile u32 DENALI_CTL_361;
+ volatile u32 DENALI_CTL_362;
+ volatile u32 DENALI_CTL_363;
+ volatile u32 DENALI_CTL_364;
+ volatile u32 DENALI_CTL_365;
+ volatile u32 DENALI_CTL_366;
+ volatile u32 DENALI_CTL_367;
+ volatile u32 DENALI_CTL_368;
+ volatile u32 DENALI_CTL_369;
+ volatile u32 DENALI_CTL_370;
+ volatile u32 DENALI_CTL_371;
+ volatile u32 DENALI_CTL_372;
+ volatile u32 DENALI_CTL_373;
+ volatile u32 DENALI_CTL_374;
+ volatile u32 DENALI_CTL_375;
+ volatile u32 DENALI_CTL_376;
+ volatile u32 DENALI_CTL_377;
+ volatile u32 DENALI_CTL_378;
+ volatile u32 DENALI_CTL_379;
+ volatile u32 DENALI_CTL_380;
+ volatile u32 DENALI_CTL_381;
+ volatile u32 DENALI_CTL_382;
+ volatile u32 DENALI_CTL_383;
+ volatile u32 DENALI_CTL_384;
+ volatile u32 DENALI_CTL_385;
+ volatile u32 DENALI_CTL_386;
+ volatile u32 DENALI_CTL_387;
+ volatile u32 DENALI_CTL_388;
+ volatile u32 DENALI_CTL_389;
+ volatile u32 DENALI_CTL_390;
+ volatile u32 DENALI_CTL_391;
+ volatile u32 DENALI_CTL_392;
+ volatile u32 DENALI_CTL_393;
+ volatile u32 DENALI_CTL_394;
+ volatile u32 DENALI_CTL_395;
+ volatile u32 DENALI_CTL_396;
+ volatile u32 DENALI_CTL_397;
+ volatile u32 DENALI_CTL_398;
+ volatile u32 DENALI_CTL_399;
+ volatile u32 DENALI_CTL_400;
+ volatile u32 DENALI_CTL_401;
+ volatile u32 DENALI_CTL_402;
+ volatile u32 DENALI_CTL_403;
+ volatile u32 DENALI_CTL_404;
+ volatile u32 DENALI_CTL_405;
+ volatile u32 DENALI_CTL_406;
+ volatile u32 DENALI_CTL_407;
+ volatile u32 DENALI_CTL_408;
+ volatile u32 DENALI_CTL_409;
+ volatile u32 DENALI_CTL_410;
+ volatile u32 DENALI_CTL_411;
+ volatile u32 DENALI_CTL_412;
+ volatile u32 DENALI_CTL_413;
+ volatile u32 DENALI_CTL_414;
+ volatile u32 DENALI_CTL_415;
+ volatile u32 DENALI_CTL_416;
+ volatile u32 DENALI_CTL_417;
+ volatile u32 DENALI_CTL_418;
+ volatile u32 DENALI_CTL_419;
+ volatile u32 DENALI_CTL_420;
+ volatile u32 DENALI_CTL_421;
+ volatile u32 DENALI_CTL_422;
+ volatile char pad__0[0x1964U];
+ volatile u32 DENALI_PI_0;
+ volatile u32 DENALI_PI_1;
+ volatile u32 DENALI_PI_2;
+ volatile u32 DENALI_PI_3;
+ volatile u32 DENALI_PI_4;
+ volatile u32 DENALI_PI_5;
+ volatile u32 DENALI_PI_6;
+ volatile u32 DENALI_PI_7;
+ volatile u32 DENALI_PI_8;
+ volatile u32 DENALI_PI_9;
+ volatile u32 DENALI_PI_10;
+ volatile u32 DENALI_PI_11;
+ volatile u32 DENALI_PI_12;
+ volatile u32 DENALI_PI_13;
+ volatile u32 DENALI_PI_14;
+ volatile u32 DENALI_PI_15;
+ volatile u32 DENALI_PI_16;
+ volatile u32 DENALI_PI_17;
+ volatile u32 DENALI_PI_18;
+ volatile u32 DENALI_PI_19;
+ volatile u32 DENALI_PI_20;
+ volatile u32 DENALI_PI_21;
+ volatile u32 DENALI_PI_22;
+ volatile u32 DENALI_PI_23;
+ volatile u32 DENALI_PI_24;
+ volatile u32 DENALI_PI_25;
+ volatile u32 DENALI_PI_26;
+ volatile u32 DENALI_PI_27;
+ volatile u32 DENALI_PI_28;
+ volatile u32 DENALI_PI_29;
+ volatile u32 DENALI_PI_30;
+ volatile u32 DENALI_PI_31;
+ volatile u32 DENALI_PI_32;
+ volatile u32 DENALI_PI_33;
+ volatile u32 DENALI_PI_34;
+ volatile u32 DENALI_PI_35;
+ volatile u32 DENALI_PI_36;
+ volatile u32 DENALI_PI_37;
+ volatile u32 DENALI_PI_38;
+ volatile u32 DENALI_PI_39;
+ volatile u32 DENALI_PI_40;
+ volatile u32 DENALI_PI_41;
+ volatile u32 DENALI_PI_42;
+ volatile u32 DENALI_PI_43;
+ volatile u32 DENALI_PI_44;
+ volatile u32 DENALI_PI_45;
+ volatile u32 DENALI_PI_46;
+ volatile u32 DENALI_PI_47;
+ volatile u32 DENALI_PI_48;
+ volatile u32 DENALI_PI_49;
+ volatile u32 DENALI_PI_50;
+ volatile u32 DENALI_PI_51;
+ volatile u32 DENALI_PI_52;
+ volatile u32 DENALI_PI_53;
+ volatile u32 DENALI_PI_54;
+ volatile u32 DENALI_PI_55;
+ volatile u32 DENALI_PI_56;
+ volatile u32 DENALI_PI_57;
+ volatile u32 DENALI_PI_58;
+ volatile u32 DENALI_PI_59;
+ volatile u32 DENALI_PI_60;
+ volatile u32 DENALI_PI_61;
+ volatile u32 DENALI_PI_62;
+ volatile u32 DENALI_PI_63;
+ volatile u32 DENALI_PI_64;
+ volatile u32 DENALI_PI_65;
+ volatile u32 DENALI_PI_66;
+ volatile u32 DENALI_PI_67;
+ volatile u32 DENALI_PI_68;
+ volatile u32 DENALI_PI_69;
+ volatile u32 DENALI_PI_70;
+ volatile u32 DENALI_PI_71;
+ volatile u32 DENALI_PI_72;
+ volatile u32 DENALI_PI_73;
+ volatile u32 DENALI_PI_74;
+ volatile u32 DENALI_PI_75;
+ volatile u32 DENALI_PI_76;
+ volatile u32 DENALI_PI_77;
+ volatile u32 DENALI_PI_78;
+ volatile u32 DENALI_PI_79;
+ volatile u32 DENALI_PI_80;
+ volatile u32 DENALI_PI_81;
+ volatile u32 DENALI_PI_82;
+ volatile u32 DENALI_PI_83;
+ volatile u32 DENALI_PI_84;
+ volatile u32 DENALI_PI_85;
+ volatile u32 DENALI_PI_86;
+ volatile u32 DENALI_PI_87;
+ volatile u32 DENALI_PI_88;
+ volatile u32 DENALI_PI_89;
+ volatile u32 DENALI_PI_90;
+ volatile u32 DENALI_PI_91;
+ volatile u32 DENALI_PI_92;
+ volatile u32 DENALI_PI_93;
+ volatile u32 DENALI_PI_94;
+ volatile u32 DENALI_PI_95;
+ volatile u32 DENALI_PI_96;
+ volatile u32 DENALI_PI_97;
+ volatile u32 DENALI_PI_98;
+ volatile u32 DENALI_PI_99;
+ volatile u32 DENALI_PI_100;
+ volatile u32 DENALI_PI_101;
+ volatile u32 DENALI_PI_102;
+ volatile u32 DENALI_PI_103;
+ volatile u32 DENALI_PI_104;
+ volatile u32 DENALI_PI_105;
+ volatile u32 DENALI_PI_106;
+ volatile u32 DENALI_PI_107;
+ volatile u32 DENALI_PI_108;
+ volatile u32 DENALI_PI_109;
+ volatile u32 DENALI_PI_110;
+ volatile u32 DENALI_PI_111;
+ volatile u32 DENALI_PI_112;
+ volatile u32 DENALI_PI_113;
+ volatile u32 DENALI_PI_114;
+ volatile u32 DENALI_PI_115;
+ volatile u32 DENALI_PI_116;
+ volatile u32 DENALI_PI_117;
+ volatile u32 DENALI_PI_118;
+ volatile u32 DENALI_PI_119;
+ volatile u32 DENALI_PI_120;
+ volatile u32 DENALI_PI_121;
+ volatile u32 DENALI_PI_122;
+ volatile u32 DENALI_PI_123;
+ volatile u32 DENALI_PI_124;
+ volatile u32 DENALI_PI_125;
+ volatile u32 DENALI_PI_126;
+ volatile u32 DENALI_PI_127;
+ volatile u32 DENALI_PI_128;
+ volatile u32 DENALI_PI_129;
+ volatile u32 DENALI_PI_130;
+ volatile u32 DENALI_PI_131;
+ volatile u32 DENALI_PI_132;
+ volatile u32 DENALI_PI_133;
+ volatile u32 DENALI_PI_134;
+ volatile u32 DENALI_PI_135;
+ volatile u32 DENALI_PI_136;
+ volatile u32 DENALI_PI_137;
+ volatile u32 DENALI_PI_138;
+ volatile u32 DENALI_PI_139;
+ volatile u32 DENALI_PI_140;
+ volatile u32 DENALI_PI_141;
+ volatile u32 DENALI_PI_142;
+ volatile u32 DENALI_PI_143;
+ volatile u32 DENALI_PI_144;
+ volatile u32 DENALI_PI_145;
+ volatile u32 DENALI_PI_146;
+ volatile u32 DENALI_PI_147;
+ volatile u32 DENALI_PI_148;
+ volatile u32 DENALI_PI_149;
+ volatile u32 DENALI_PI_150;
+ volatile u32 DENALI_PI_151;
+ volatile u32 DENALI_PI_152;
+ volatile u32 DENALI_PI_153;
+ volatile u32 DENALI_PI_154;
+ volatile u32 DENALI_PI_155;
+ volatile u32 DENALI_PI_156;
+ volatile u32 DENALI_PI_157;
+ volatile u32 DENALI_PI_158;
+ volatile u32 DENALI_PI_159;
+ volatile u32 DENALI_PI_160;
+ volatile u32 DENALI_PI_161;
+ volatile u32 DENALI_PI_162;
+ volatile u32 DENALI_PI_163;
+ volatile u32 DENALI_PI_164;
+ volatile u32 DENALI_PI_165;
+ volatile u32 DENALI_PI_166;
+ volatile u32 DENALI_PI_167;
+ volatile u32 DENALI_PI_168;
+ volatile u32 DENALI_PI_169;
+ volatile u32 DENALI_PI_170;
+ volatile u32 DENALI_PI_171;
+ volatile u32 DENALI_PI_172;
+ volatile u32 DENALI_PI_173;
+ volatile u32 DENALI_PI_174;
+ volatile u32 DENALI_PI_175;
+ volatile u32 DENALI_PI_176;
+ volatile u32 DENALI_PI_177;
+ volatile u32 DENALI_PI_178;
+ volatile u32 DENALI_PI_179;
+ volatile u32 DENALI_PI_180;
+ volatile u32 DENALI_PI_181;
+ volatile u32 DENALI_PI_182;
+ volatile u32 DENALI_PI_183;
+ volatile u32 DENALI_PI_184;
+ volatile u32 DENALI_PI_185;
+ volatile u32 DENALI_PI_186;
+ volatile u32 DENALI_PI_187;
+ volatile u32 DENALI_PI_188;
+ volatile u32 DENALI_PI_189;
+ volatile u32 DENALI_PI_190;
+ volatile u32 DENALI_PI_191;
+ volatile u32 DENALI_PI_192;
+ volatile u32 DENALI_PI_193;
+ volatile u32 DENALI_PI_194;
+ volatile u32 DENALI_PI_195;
+ volatile u32 DENALI_PI_196;
+ volatile u32 DENALI_PI_197;
+ volatile u32 DENALI_PI_198;
+ volatile u32 DENALI_PI_199;
+ volatile u32 DENALI_PI_200;
+ volatile u32 DENALI_PI_201;
+ volatile u32 DENALI_PI_202;
+ volatile u32 DENALI_PI_203;
+ volatile u32 DENALI_PI_204;
+ volatile u32 DENALI_PI_205;
+ volatile u32 DENALI_PI_206;
+ volatile u32 DENALI_PI_207;
+ volatile u32 DENALI_PI_208;
+ volatile u32 DENALI_PI_209;
+ volatile u32 DENALI_PI_210;
+ volatile u32 DENALI_PI_211;
+ volatile u32 DENALI_PI_212;
+ volatile u32 DENALI_PI_213;
+ volatile u32 DENALI_PI_214;
+ volatile u32 DENALI_PI_215;
+ volatile u32 DENALI_PI_216;
+ volatile u32 DENALI_PI_217;
+ volatile u32 DENALI_PI_218;
+ volatile u32 DENALI_PI_219;
+ volatile u32 DENALI_PI_220;
+ volatile u32 DENALI_PI_221;
+ volatile u32 DENALI_PI_222;
+ volatile u32 DENALI_PI_223;
+ volatile u32 DENALI_PI_224;
+ volatile u32 DENALI_PI_225;
+ volatile u32 DENALI_PI_226;
+ volatile u32 DENALI_PI_227;
+ volatile u32 DENALI_PI_228;
+ volatile u32 DENALI_PI_229;
+ volatile u32 DENALI_PI_230;
+ volatile u32 DENALI_PI_231;
+ volatile u32 DENALI_PI_232;
+ volatile u32 DENALI_PI_233;
+ volatile u32 DENALI_PI_234;
+ volatile u32 DENALI_PI_235;
+ volatile u32 DENALI_PI_236;
+ volatile u32 DENALI_PI_237;
+ volatile u32 DENALI_PI_238;
+ volatile u32 DENALI_PI_239;
+ volatile u32 DENALI_PI_240;
+ volatile u32 DENALI_PI_241;
+ volatile u32 DENALI_PI_242;
+ volatile u32 DENALI_PI_243;
+ volatile u32 DENALI_PI_244;
+ volatile u32 DENALI_PI_245;
+ volatile u32 DENALI_PI_246;
+ volatile u32 DENALI_PI_247;
+ volatile u32 DENALI_PI_248;
+ volatile u32 DENALI_PI_249;
+ volatile u32 DENALI_PI_250;
+ volatile u32 DENALI_PI_251;
+ volatile u32 DENALI_PI_252;
+ volatile u32 DENALI_PI_253;
+ volatile u32 DENALI_PI_254;
+ volatile u32 DENALI_PI_255;
+ volatile u32 DENALI_PI_256;
+ volatile u32 DENALI_PI_257;
+ volatile u32 DENALI_PI_258;
+ volatile u32 DENALI_PI_259;
+ volatile u32 DENALI_PI_260;
+ volatile u32 DENALI_PI_261;
+ volatile u32 DENALI_PI_262;
+ volatile u32 DENALI_PI_263;
+ volatile u32 DENALI_PI_264;
+ volatile u32 DENALI_PI_265;
+ volatile u32 DENALI_PI_266;
+ volatile u32 DENALI_PI_267;
+ volatile u32 DENALI_PI_268;
+ volatile u32 DENALI_PI_269;
+ volatile u32 DENALI_PI_270;
+ volatile u32 DENALI_PI_271;
+ volatile u32 DENALI_PI_272;
+ volatile u32 DENALI_PI_273;
+ volatile u32 DENALI_PI_274;
+ volatile u32 DENALI_PI_275;
+ volatile u32 DENALI_PI_276;
+ volatile u32 DENALI_PI_277;
+ volatile u32 DENALI_PI_278;
+ volatile u32 DENALI_PI_279;
+ volatile u32 DENALI_PI_280;
+ volatile u32 DENALI_PI_281;
+ volatile u32 DENALI_PI_282;
+ volatile u32 DENALI_PI_283;
+ volatile u32 DENALI_PI_284;
+ volatile u32 DENALI_PI_285;
+ volatile u32 DENALI_PI_286;
+ volatile u32 DENALI_PI_287;
+ volatile u32 DENALI_PI_288;
+ volatile u32 DENALI_PI_289;
+ volatile u32 DENALI_PI_290;
+ volatile u32 DENALI_PI_291;
+ volatile u32 DENALI_PI_292;
+ volatile u32 DENALI_PI_293;
+ volatile u32 DENALI_PI_294;
+ volatile u32 DENALI_PI_295;
+ volatile u32 DENALI_PI_296;
+ volatile u32 DENALI_PI_297;
+ volatile u32 DENALI_PI_298;
+ volatile u32 DENALI_PI_299;
+ volatile u32 DENALI_PI_300;
+ volatile u32 DENALI_PI_301;
+ volatile u32 DENALI_PI_302;
+ volatile u32 DENALI_PI_303;
+ volatile u32 DENALI_PI_304;
+ volatile u32 DENALI_PI_305;
+ volatile u32 DENALI_PI_306;
+ volatile u32 DENALI_PI_307;
+ volatile u32 DENALI_PI_308;
+ volatile u32 DENALI_PI_309;
+ volatile u32 DENALI_PI_310;
+ volatile u32 DENALI_PI_311;
+ volatile u32 DENALI_PI_312;
+ volatile u32 DENALI_PI_313;
+ volatile u32 DENALI_PI_314;
+ volatile u32 DENALI_PI_315;
+ volatile u32 DENALI_PI_316;
+ volatile u32 DENALI_PI_317;
+ volatile u32 DENALI_PI_318;
+ volatile u32 DENALI_PI_319;
+ volatile u32 DENALI_PI_320;
+ volatile u32 DENALI_PI_321;
+ volatile u32 DENALI_PI_322;
+ volatile u32 DENALI_PI_323;
+ volatile u32 DENALI_PI_324;
+ volatile u32 DENALI_PI_325;
+ volatile u32 DENALI_PI_326;
+ volatile u32 DENALI_PI_327;
+ volatile u32 DENALI_PI_328;
+ volatile u32 DENALI_PI_329;
+ volatile u32 DENALI_PI_330;
+ volatile u32 DENALI_PI_331;
+ volatile u32 DENALI_PI_332;
+ volatile u32 DENALI_PI_333;
+ volatile u32 DENALI_PI_334;
+ volatile u32 DENALI_PI_335;
+ volatile u32 DENALI_PI_336;
+ volatile u32 DENALI_PI_337;
+ volatile u32 DENALI_PI_338;
+ volatile u32 DENALI_PI_339;
+ volatile u32 DENALI_PI_340;
+ volatile u32 DENALI_PI_341;
+ volatile u32 DENALI_PI_342;
+ volatile u32 DENALI_PI_343;
+ volatile u32 DENALI_PI_344;
+ volatile char pad__1[0x1A9CU];
+ volatile u32 DENALI_PHY_0;
+ volatile u32 DENALI_PHY_1;
+ volatile u32 DENALI_PHY_2;
+ volatile u32 DENALI_PHY_3;
+ volatile u32 DENALI_PHY_4;
+ volatile u32 DENALI_PHY_5;
+ volatile u32 DENALI_PHY_6;
+ volatile u32 DENALI_PHY_7;
+ volatile u32 DENALI_PHY_8;
+ volatile u32 DENALI_PHY_9;
+ volatile u32 DENALI_PHY_10;
+ volatile u32 DENALI_PHY_11;
+ volatile u32 DENALI_PHY_12;
+ volatile u32 DENALI_PHY_13;
+ volatile u32 DENALI_PHY_14;
+ volatile u32 DENALI_PHY_15;
+ volatile u32 DENALI_PHY_16;
+ volatile u32 DENALI_PHY_17;
+ volatile u32 DENALI_PHY_18;
+ volatile u32 DENALI_PHY_19;
+ volatile u32 DENALI_PHY_20;
+ volatile u32 DENALI_PHY_21;
+ volatile u32 DENALI_PHY_22;
+ volatile u32 DENALI_PHY_23;
+ volatile u32 DENALI_PHY_24;
+ volatile u32 DENALI_PHY_25;
+ volatile u32 DENALI_PHY_26;
+ volatile u32 DENALI_PHY_27;
+ volatile u32 DENALI_PHY_28;
+ volatile u32 DENALI_PHY_29;
+ volatile u32 DENALI_PHY_30;
+ volatile u32 DENALI_PHY_31;
+ volatile u32 DENALI_PHY_32;
+ volatile u32 DENALI_PHY_33;
+ volatile u32 DENALI_PHY_34;
+ volatile u32 DENALI_PHY_35;
+ volatile u32 DENALI_PHY_36;
+ volatile u32 DENALI_PHY_37;
+ volatile u32 DENALI_PHY_38;
+ volatile u32 DENALI_PHY_39;
+ volatile u32 DENALI_PHY_40;
+ volatile u32 DENALI_PHY_41;
+ volatile u32 DENALI_PHY_42;
+ volatile u32 DENALI_PHY_43;
+ volatile u32 DENALI_PHY_44;
+ volatile u32 DENALI_PHY_45;
+ volatile u32 DENALI_PHY_46;
+ volatile u32 DENALI_PHY_47;
+ volatile u32 DENALI_PHY_48;
+ volatile u32 DENALI_PHY_49;
+ volatile u32 DENALI_PHY_50;
+ volatile u32 DENALI_PHY_51;
+ volatile u32 DENALI_PHY_52;
+ volatile u32 DENALI_PHY_53;
+ volatile u32 DENALI_PHY_54;
+ volatile u32 DENALI_PHY_55;
+ volatile u32 DENALI_PHY_56;
+ volatile u32 DENALI_PHY_57;
+ volatile u32 DENALI_PHY_58;
+ volatile u32 DENALI_PHY_59;
+ volatile u32 DENALI_PHY_60;
+ volatile u32 DENALI_PHY_61;
+ volatile u32 DENALI_PHY_62;
+ volatile u32 DENALI_PHY_63;
+ volatile u32 DENALI_PHY_64;
+ volatile u32 DENALI_PHY_65;
+ volatile u32 DENALI_PHY_66;
+ volatile u32 DENALI_PHY_67;
+ volatile u32 DENALI_PHY_68;
+ volatile u32 DENALI_PHY_69;
+ volatile u32 DENALI_PHY_70;
+ volatile u32 DENALI_PHY_71;
+ volatile u32 DENALI_PHY_72;
+ volatile u32 DENALI_PHY_73;
+ volatile u32 DENALI_PHY_74;
+ volatile u32 DENALI_PHY_75;
+ volatile u32 DENALI_PHY_76;
+ volatile u32 DENALI_PHY_77;
+ volatile u32 DENALI_PHY_78;
+ volatile u32 DENALI_PHY_79;
+ volatile u32 DENALI_PHY_80;
+ volatile u32 DENALI_PHY_81;
+ volatile u32 DENALI_PHY_82;
+ volatile u32 DENALI_PHY_83;
+ volatile u32 DENALI_PHY_84;
+ volatile u32 DENALI_PHY_85;
+ volatile u32 DENALI_PHY_86;
+ volatile u32 DENALI_PHY_87;
+ volatile u32 DENALI_PHY_88;
+ volatile u32 DENALI_PHY_89;
+ volatile u32 DENALI_PHY_90;
+ volatile u32 DENALI_PHY_91;
+ volatile u32 DENALI_PHY_92;
+ volatile u32 DENALI_PHY_93;
+ volatile u32 DENALI_PHY_94;
+ volatile u32 DENALI_PHY_95;
+ volatile u32 DENALI_PHY_96;
+ volatile u32 DENALI_PHY_97;
+ volatile u32 DENALI_PHY_98;
+ volatile u32 DENALI_PHY_99;
+ volatile u32 DENALI_PHY_100;
+ volatile u32 DENALI_PHY_101;
+ volatile u32 DENALI_PHY_102;
+ volatile u32 DENALI_PHY_103;
+ volatile u32 DENALI_PHY_104;
+ volatile u32 DENALI_PHY_105;
+ volatile u32 DENALI_PHY_106;
+ volatile u32 DENALI_PHY_107;
+ volatile u32 DENALI_PHY_108;
+ volatile u32 DENALI_PHY_109;
+ volatile u32 DENALI_PHY_110;
+ volatile u32 DENALI_PHY_111;
+ volatile u32 DENALI_PHY_112;
+ volatile u32 DENALI_PHY_113;
+ volatile u32 DENALI_PHY_114;
+ volatile u32 DENALI_PHY_115;
+ volatile u32 DENALI_PHY_116;
+ volatile u32 DENALI_PHY_117;
+ volatile u32 DENALI_PHY_118;
+ volatile u32 DENALI_PHY_119;
+ volatile u32 DENALI_PHY_120;
+ volatile u32 DENALI_PHY_121;
+ volatile u32 DENALI_PHY_122;
+ volatile u32 DENALI_PHY_123;
+ volatile u32 DENALI_PHY_124;
+ volatile u32 DENALI_PHY_125;
+ volatile char pad__2[0x208U];
+ volatile u32 DENALI_PHY_256;
+ volatile u32 DENALI_PHY_257;
+ volatile u32 DENALI_PHY_258;
+ volatile u32 DENALI_PHY_259;
+ volatile u32 DENALI_PHY_260;
+ volatile u32 DENALI_PHY_261;
+ volatile u32 DENALI_PHY_262;
+ volatile u32 DENALI_PHY_263;
+ volatile u32 DENALI_PHY_264;
+ volatile u32 DENALI_PHY_265;
+ volatile u32 DENALI_PHY_266;
+ volatile u32 DENALI_PHY_267;
+ volatile u32 DENALI_PHY_268;
+ volatile u32 DENALI_PHY_269;
+ volatile u32 DENALI_PHY_270;
+ volatile u32 DENALI_PHY_271;
+ volatile u32 DENALI_PHY_272;
+ volatile u32 DENALI_PHY_273;
+ volatile u32 DENALI_PHY_274;
+ volatile u32 DENALI_PHY_275;
+ volatile u32 DENALI_PHY_276;
+ volatile u32 DENALI_PHY_277;
+ volatile u32 DENALI_PHY_278;
+ volatile u32 DENALI_PHY_279;
+ volatile u32 DENALI_PHY_280;
+ volatile u32 DENALI_PHY_281;
+ volatile u32 DENALI_PHY_282;
+ volatile u32 DENALI_PHY_283;
+ volatile u32 DENALI_PHY_284;
+ volatile u32 DENALI_PHY_285;
+ volatile u32 DENALI_PHY_286;
+ volatile u32 DENALI_PHY_287;
+ volatile u32 DENALI_PHY_288;
+ volatile u32 DENALI_PHY_289;
+ volatile u32 DENALI_PHY_290;
+ volatile u32 DENALI_PHY_291;
+ volatile u32 DENALI_PHY_292;
+ volatile u32 DENALI_PHY_293;
+ volatile u32 DENALI_PHY_294;
+ volatile u32 DENALI_PHY_295;
+ volatile u32 DENALI_PHY_296;
+ volatile u32 DENALI_PHY_297;
+ volatile u32 DENALI_PHY_298;
+ volatile u32 DENALI_PHY_299;
+ volatile u32 DENALI_PHY_300;
+ volatile u32 DENALI_PHY_301;
+ volatile u32 DENALI_PHY_302;
+ volatile u32 DENALI_PHY_303;
+ volatile u32 DENALI_PHY_304;
+ volatile u32 DENALI_PHY_305;
+ volatile u32 DENALI_PHY_306;
+ volatile u32 DENALI_PHY_307;
+ volatile u32 DENALI_PHY_308;
+ volatile u32 DENALI_PHY_309;
+ volatile u32 DENALI_PHY_310;
+ volatile u32 DENALI_PHY_311;
+ volatile u32 DENALI_PHY_312;
+ volatile u32 DENALI_PHY_313;
+ volatile u32 DENALI_PHY_314;
+ volatile u32 DENALI_PHY_315;
+ volatile u32 DENALI_PHY_316;
+ volatile u32 DENALI_PHY_317;
+ volatile u32 DENALI_PHY_318;
+ volatile u32 DENALI_PHY_319;
+ volatile u32 DENALI_PHY_320;
+ volatile u32 DENALI_PHY_321;
+ volatile u32 DENALI_PHY_322;
+ volatile u32 DENALI_PHY_323;
+ volatile u32 DENALI_PHY_324;
+ volatile u32 DENALI_PHY_325;
+ volatile u32 DENALI_PHY_326;
+ volatile u32 DENALI_PHY_327;
+ volatile u32 DENALI_PHY_328;
+ volatile u32 DENALI_PHY_329;
+ volatile u32 DENALI_PHY_330;
+ volatile u32 DENALI_PHY_331;
+ volatile u32 DENALI_PHY_332;
+ volatile u32 DENALI_PHY_333;
+ volatile u32 DENALI_PHY_334;
+ volatile u32 DENALI_PHY_335;
+ volatile u32 DENALI_PHY_336;
+ volatile u32 DENALI_PHY_337;
+ volatile u32 DENALI_PHY_338;
+ volatile u32 DENALI_PHY_339;
+ volatile u32 DENALI_PHY_340;
+ volatile u32 DENALI_PHY_341;
+ volatile u32 DENALI_PHY_342;
+ volatile u32 DENALI_PHY_343;
+ volatile u32 DENALI_PHY_344;
+ volatile u32 DENALI_PHY_345;
+ volatile u32 DENALI_PHY_346;
+ volatile u32 DENALI_PHY_347;
+ volatile u32 DENALI_PHY_348;
+ volatile u32 DENALI_PHY_349;
+ volatile u32 DENALI_PHY_350;
+ volatile u32 DENALI_PHY_351;
+ volatile u32 DENALI_PHY_352;
+ volatile u32 DENALI_PHY_353;
+ volatile u32 DENALI_PHY_354;
+ volatile u32 DENALI_PHY_355;
+ volatile u32 DENALI_PHY_356;
+ volatile u32 DENALI_PHY_357;
+ volatile u32 DENALI_PHY_358;
+ volatile u32 DENALI_PHY_359;
+ volatile u32 DENALI_PHY_360;
+ volatile u32 DENALI_PHY_361;
+ volatile u32 DENALI_PHY_362;
+ volatile u32 DENALI_PHY_363;
+ volatile u32 DENALI_PHY_364;
+ volatile u32 DENALI_PHY_365;
+ volatile u32 DENALI_PHY_366;
+ volatile u32 DENALI_PHY_367;
+ volatile u32 DENALI_PHY_368;
+ volatile u32 DENALI_PHY_369;
+ volatile u32 DENALI_PHY_370;
+ volatile u32 DENALI_PHY_371;
+ volatile u32 DENALI_PHY_372;
+ volatile u32 DENALI_PHY_373;
+ volatile u32 DENALI_PHY_374;
+ volatile u32 DENALI_PHY_375;
+ volatile u32 DENALI_PHY_376;
+ volatile u32 DENALI_PHY_377;
+ volatile u32 DENALI_PHY_378;
+ volatile u32 DENALI_PHY_379;
+ volatile u32 DENALI_PHY_380;
+ volatile u32 DENALI_PHY_381;
+ volatile char pad__3[0x208U];
+ volatile u32 DENALI_PHY_512;
+ volatile u32 DENALI_PHY_513;
+ volatile u32 DENALI_PHY_514;
+ volatile u32 DENALI_PHY_515;
+ volatile u32 DENALI_PHY_516;
+ volatile u32 DENALI_PHY_517;
+ volatile u32 DENALI_PHY_518;
+ volatile u32 DENALI_PHY_519;
+ volatile u32 DENALI_PHY_520;
+ volatile u32 DENALI_PHY_521;
+ volatile u32 DENALI_PHY_522;
+ volatile u32 DENALI_PHY_523;
+ volatile u32 DENALI_PHY_524;
+ volatile u32 DENALI_PHY_525;
+ volatile u32 DENALI_PHY_526;
+ volatile u32 DENALI_PHY_527;
+ volatile u32 DENALI_PHY_528;
+ volatile u32 DENALI_PHY_529;
+ volatile u32 DENALI_PHY_530;
+ volatile u32 DENALI_PHY_531;
+ volatile u32 DENALI_PHY_532;
+ volatile u32 DENALI_PHY_533;
+ volatile u32 DENALI_PHY_534;
+ volatile u32 DENALI_PHY_535;
+ volatile u32 DENALI_PHY_536;
+ volatile u32 DENALI_PHY_537;
+ volatile u32 DENALI_PHY_538;
+ volatile u32 DENALI_PHY_539;
+ volatile u32 DENALI_PHY_540;
+ volatile u32 DENALI_PHY_541;
+ volatile u32 DENALI_PHY_542;
+ volatile u32 DENALI_PHY_543;
+ volatile u32 DENALI_PHY_544;
+ volatile u32 DENALI_PHY_545;
+ volatile u32 DENALI_PHY_546;
+ volatile u32 DENALI_PHY_547;
+ volatile u32 DENALI_PHY_548;
+ volatile u32 DENALI_PHY_549;
+ volatile u32 DENALI_PHY_550;
+ volatile u32 DENALI_PHY_551;
+ volatile u32 DENALI_PHY_552;
+ volatile u32 DENALI_PHY_553;
+ volatile u32 DENALI_PHY_554;
+ volatile char pad__4[0x354U];
+ volatile u32 DENALI_PHY_768;
+ volatile u32 DENALI_PHY_769;
+ volatile u32 DENALI_PHY_770;
+ volatile u32 DENALI_PHY_771;
+ volatile u32 DENALI_PHY_772;
+ volatile u32 DENALI_PHY_773;
+ volatile u32 DENALI_PHY_774;
+ volatile u32 DENALI_PHY_775;
+ volatile u32 DENALI_PHY_776;
+ volatile u32 DENALI_PHY_777;
+ volatile u32 DENALI_PHY_778;
+ volatile u32 DENALI_PHY_779;
+ volatile u32 DENALI_PHY_780;
+ volatile u32 DENALI_PHY_781;
+ volatile u32 DENALI_PHY_782;
+ volatile u32 DENALI_PHY_783;
+ volatile u32 DENALI_PHY_784;
+ volatile u32 DENALI_PHY_785;
+ volatile u32 DENALI_PHY_786;
+ volatile u32 DENALI_PHY_787;
+ volatile u32 DENALI_PHY_788;
+ volatile u32 DENALI_PHY_789;
+ volatile u32 DENALI_PHY_790;
+ volatile u32 DENALI_PHY_791;
+ volatile u32 DENALI_PHY_792;
+ volatile u32 DENALI_PHY_793;
+ volatile u32 DENALI_PHY_794;
+ volatile u32 DENALI_PHY_795;
+ volatile u32 DENALI_PHY_796;
+ volatile u32 DENALI_PHY_797;
+ volatile u32 DENALI_PHY_798;
+ volatile u32 DENALI_PHY_799;
+ volatile u32 DENALI_PHY_800;
+ volatile u32 DENALI_PHY_801;
+ volatile u32 DENALI_PHY_802;
+ volatile u32 DENALI_PHY_803;
+ volatile u32 DENALI_PHY_804;
+ volatile u32 DENALI_PHY_805;
+ volatile u32 DENALI_PHY_806;
+ volatile u32 DENALI_PHY_807;
+ volatile u32 DENALI_PHY_808;
+ volatile u32 DENALI_PHY_809;
+ volatile u32 DENALI_PHY_810;
+ volatile char pad__5[0x354U];
+ volatile u32 DENALI_PHY_1024;
+ volatile u32 DENALI_PHY_1025;
+ volatile u32 DENALI_PHY_1026;
+ volatile u32 DENALI_PHY_1027;
+ volatile u32 DENALI_PHY_1028;
+ volatile u32 DENALI_PHY_1029;
+ volatile u32 DENALI_PHY_1030;
+ volatile u32 DENALI_PHY_1031;
+ volatile u32 DENALI_PHY_1032;
+ volatile u32 DENALI_PHY_1033;
+ volatile u32 DENALI_PHY_1034;
+ volatile u32 DENALI_PHY_1035;
+ volatile u32 DENALI_PHY_1036;
+ volatile u32 DENALI_PHY_1037;
+ volatile u32 DENALI_PHY_1038;
+ volatile u32 DENALI_PHY_1039;
+ volatile u32 DENALI_PHY_1040;
+ volatile u32 DENALI_PHY_1041;
+ volatile u32 DENALI_PHY_1042;
+ volatile u32 DENALI_PHY_1043;
+ volatile u32 DENALI_PHY_1044;
+ volatile u32 DENALI_PHY_1045;
+ volatile u32 DENALI_PHY_1046;
+ volatile u32 DENALI_PHY_1047;
+ volatile u32 DENALI_PHY_1048;
+ volatile u32 DENALI_PHY_1049;
+ volatile u32 DENALI_PHY_1050;
+ volatile u32 DENALI_PHY_1051;
+ volatile u32 DENALI_PHY_1052;
+ volatile u32 DENALI_PHY_1053;
+ volatile u32 DENALI_PHY_1054;
+ volatile u32 DENALI_PHY_1055;
+ volatile u32 DENALI_PHY_1056;
+ volatile u32 DENALI_PHY_1057;
+ volatile u32 DENALI_PHY_1058;
+ volatile u32 DENALI_PHY_1059;
+ volatile u32 DENALI_PHY_1060;
+ volatile u32 DENALI_PHY_1061;
+ volatile u32 DENALI_PHY_1062;
+ volatile u32 DENALI_PHY_1063;
+ volatile u32 DENALI_PHY_1064;
+ volatile u32 DENALI_PHY_1065;
+ volatile u32 DENALI_PHY_1066;
+ volatile char pad__6[0x354U];
+ volatile u32 DENALI_PHY_1280;
+ volatile u32 DENALI_PHY_1281;
+ volatile u32 DENALI_PHY_1282;
+ volatile u32 DENALI_PHY_1283;
+ volatile u32 DENALI_PHY_1284;
+ volatile u32 DENALI_PHY_1285;
+ volatile u32 DENALI_PHY_1286;
+ volatile u32 DENALI_PHY_1287;
+ volatile u32 DENALI_PHY_1288;
+ volatile u32 DENALI_PHY_1289;
+ volatile u32 DENALI_PHY_1290;
+ volatile u32 DENALI_PHY_1291;
+ volatile u32 DENALI_PHY_1292;
+ volatile u32 DENALI_PHY_1293;
+ volatile u32 DENALI_PHY_1294;
+ volatile u32 DENALI_PHY_1295;
+ volatile u32 DENALI_PHY_1296;
+ volatile u32 DENALI_PHY_1297;
+ volatile u32 DENALI_PHY_1298;
+ volatile u32 DENALI_PHY_1299;
+ volatile u32 DENALI_PHY_1300;
+ volatile u32 DENALI_PHY_1301;
+ volatile u32 DENALI_PHY_1302;
+ volatile u32 DENALI_PHY_1303;
+ volatile u32 DENALI_PHY_1304;
+ volatile u32 DENALI_PHY_1305;
+ volatile u32 DENALI_PHY_1306;
+ volatile u32 DENALI_PHY_1307;
+ volatile u32 DENALI_PHY_1308;
+ volatile u32 DENALI_PHY_1309;
+ volatile u32 DENALI_PHY_1310;
+ volatile u32 DENALI_PHY_1311;
+ volatile u32 DENALI_PHY_1312;
+ volatile u32 DENALI_PHY_1313;
+ volatile u32 DENALI_PHY_1314;
+ volatile u32 DENALI_PHY_1315;
+ volatile u32 DENALI_PHY_1316;
+ volatile u32 DENALI_PHY_1317;
+ volatile u32 DENALI_PHY_1318;
+ volatile u32 DENALI_PHY_1319;
+ volatile u32 DENALI_PHY_1320;
+ volatile u32 DENALI_PHY_1321;
+ volatile u32 DENALI_PHY_1322;
+ volatile u32 DENALI_PHY_1323;
+ volatile u32 DENALI_PHY_1324;
+ volatile u32 DENALI_PHY_1325;
+ volatile u32 DENALI_PHY_1326;
+ volatile u32 DENALI_PHY_1327;
+ volatile u32 DENALI_PHY_1328;
+ volatile u32 DENALI_PHY_1329;
+ volatile u32 DENALI_PHY_1330;
+ volatile u32 DENALI_PHY_1331;
+ volatile u32 DENALI_PHY_1332;
+ volatile u32 DENALI_PHY_1333;
+ volatile u32 DENALI_PHY_1334;
+ volatile u32 DENALI_PHY_1335;
+ volatile u32 DENALI_PHY_1336;
+ volatile u32 DENALI_PHY_1337;
+ volatile u32 DENALI_PHY_1338;
+ volatile u32 DENALI_PHY_1339;
+ volatile u32 DENALI_PHY_1340;
+ volatile u32 DENALI_PHY_1341;
+ volatile u32 DENALI_PHY_1342;
+ volatile u32 DENALI_PHY_1343;
+ volatile u32 DENALI_PHY_1344;
+ volatile u32 DENALI_PHY_1345;
+ volatile u32 DENALI_PHY_1346;
+ volatile u32 DENALI_PHY_1347;
+ volatile u32 DENALI_PHY_1348;
+ volatile u32 DENALI_PHY_1349;
+ volatile u32 DENALI_PHY_1350;
+ volatile u32 DENALI_PHY_1351;
+ volatile u32 DENALI_PHY_1352;
+ volatile u32 DENALI_PHY_1353;
+ volatile u32 DENALI_PHY_1354;
+ volatile u32 DENALI_PHY_1355;
+ volatile u32 DENALI_PHY_1356;
+ volatile u32 DENALI_PHY_1357;
+ volatile u32 DENALI_PHY_1358;
+ volatile u32 DENALI_PHY_1359;
+ volatile u32 DENALI_PHY_1360;
+ volatile u32 DENALI_PHY_1361;
+ volatile u32 DENALI_PHY_1362;
+ volatile u32 DENALI_PHY_1363;
+ volatile u32 DENALI_PHY_1364;
+ volatile u32 DENALI_PHY_1365;
+ volatile u32 DENALI_PHY_1366;
+ volatile u32 DENALI_PHY_1367;
+ volatile u32 DENALI_PHY_1368;
+ volatile u32 DENALI_PHY_1369;
+ volatile u32 DENALI_PHY_1370;
+ volatile u32 DENALI_PHY_1371;
+ volatile u32 DENALI_PHY_1372;
+ volatile u32 DENALI_PHY_1373;
+ volatile u32 DENALI_PHY_1374;
+ volatile u32 DENALI_PHY_1375;
+ volatile u32 DENALI_PHY_1376;
+ volatile u32 DENALI_PHY_1377;
+ volatile u32 DENALI_PHY_1378;
+ volatile u32 DENALI_PHY_1379;
+ volatile u32 DENALI_PHY_1380;
+ volatile u32 DENALI_PHY_1381;
+ volatile u32 DENALI_PHY_1382;
+ volatile u32 DENALI_PHY_1383;
+ volatile u32 DENALI_PHY_1384;
+ volatile u32 DENALI_PHY_1385;
+ volatile u32 DENALI_PHY_1386;
+ volatile u32 DENALI_PHY_1387;
+ volatile u32 DENALI_PHY_1388;
+ volatile u32 DENALI_PHY_1389;
+ volatile u32 DENALI_PHY_1390;
+ volatile u32 DENALI_PHY_1391;
+ volatile u32 DENALI_PHY_1392;
+ volatile u32 DENALI_PHY_1393;
+ volatile u32 DENALI_PHY_1394;
+ volatile u32 DENALI_PHY_1395;
+ volatile u32 DENALI_PHY_1396;
+ volatile u32 DENALI_PHY_1397;
+ volatile u32 DENALI_PHY_1398;
+ volatile u32 DENALI_PHY_1399;
+ volatile u32 DENALI_PHY_1400;
+ volatile u32 DENALI_PHY_1401;
+ volatile u32 DENALI_PHY_1402;
+ volatile u32 DENALI_PHY_1403;
+ volatile u32 DENALI_PHY_1404;
+ volatile u32 DENALI_PHY_1405;
+} lpddr4_ctlregs;
+
+#endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
new file mode 100644
index 0000000..d46b77b
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_RW_MASKS_H_
+#define LPDDR4_RW_MASKS_H_
+
+#include <stdint.h>
+
+extern u32 g_lpddr4_ddr_controller_rw_mask[423];
+extern u32 g_lpddr4_pi_rw_mask[345];
+extern u32 g_lpddr4_data_slice_0_rw_mask[126];
+extern u32 g_lpddr4_data_slice_1_rw_mask[126];
+extern u32 g_lpddr4_address_slice_0_rw_mask[43];
+extern u32 g_lpddr4_address_slice_1_rw_mask[43];
+extern u32 g_lpddr4_address_slice_2_rw_mask[43];
+extern u32 g_lpddr4_phy_core_rw_mask[126];
+
+#endif /* LPDDR4_RW_MASKS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
new file mode 100644
index 0000000..d3bf24e
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
@@ -0,0 +1,2036 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_0_READ_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0_WRITE_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_WIDTH 3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_WIDTH 7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1_READ_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1_WRITE_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_2_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_2_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH 2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_3_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_5_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH 4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_6_READ_MASK 0x030F0F1FU
+#define LPDDR4__DENALI_PHY_6_WRITE_MASK 0x030F0F1FU
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_7_READ_MASK 0x01FF031FU
+#define LPDDR4__DENALI_PHY_7_WRITE_MASK 0x01FF031FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_WIDTH 2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_WIDTH 9U
+#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_8_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_8_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0
+
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__FLD LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_9_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH 32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_10_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH 28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_11_READ_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_11_WRITE_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_WIDTH 9U
+#define LPDDR4__PHY_DQ_IDLE_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_DQ_IDLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0
+
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WOSET 0U
+#define LPDDR4__PHY_PDA_MODE_EN_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_PDA_MODE_EN_0__FLD LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0
+
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_12_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_12_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_WIDTH 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_13_READ_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_13_WRITE_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH 6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_14_READ_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_14_WRITE_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0
+
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WOSET 0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_14
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_15_READ_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_15_WRITE_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WOSET 0U
+#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_15__PHY_LPDDR_0
+
+#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_WIDTH 3U
+#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0
+
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_16_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_16_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_WIDTH 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_16
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0
+
+#define LPDDR4__DENALI_PHY_17_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_17_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_17
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0
+
+#define LPDDR4__DENALI_PHY_18_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_18_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_WIDTH 2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_18
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0
+
+#define LPDDR4__DENALI_PHY_19_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_19
+#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0
+
+#define LPDDR4__DENALI_PHY_20_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_20
+#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0
+
+#define LPDDR4__DENALI_PHY_21_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_21
+#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0
+
+#define LPDDR4__DENALI_PHY_22_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_22
+#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0
+
+#define LPDDR4__DENALI_PHY_23_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_23
+#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0
+
+#define LPDDR4__DENALI_PHY_24_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_24
+#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0
+
+#define LPDDR4__DENALI_PHY_25_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_25
+#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0
+
+#define LPDDR4__DENALI_PHY_26_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_26
+#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0
+
+#define LPDDR4__DENALI_PHY_27_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_27_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_28_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29_READ_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_29_WRITE_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WOSET 0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WOSET 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_29
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_30_READ_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_30_WRITE_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH 5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_32_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_32_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH 8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_MASK 0x03FFFF00U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_WIDTH 18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0
+
+#define LPDDR4__DENALI_PHY_33_READ_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_33_WRITE_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH 3U
+#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0
+
+#define LPDDR4__DENALI_PHY_34_READ_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_34_WRITE_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_35_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_35_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET 0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_35
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0
+
+#define LPDDR4__DENALI_PHY_36_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_36_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0
+
+#define LPDDR4__DENALI_PHY_37_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_37
+#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0
+
+#define LPDDR4__DENALI_PHY_38_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_38
+#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0
+
+#define LPDDR4__DENALI_PHY_39_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_39
+#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0
+
+#define LPDDR4__DENALI_PHY_40_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_40
+#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0
+
+#define LPDDR4__DENALI_PHY_41_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_41_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_WIDTH 16U
+#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0
+
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WOSET 0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0
+
+#define LPDDR4__DENALI_PHY_42_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_WIDTH 10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_43_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0
+
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0
+
+#define LPDDR4__DENALI_PHY_44_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_44_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET 0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0
+
+#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_WIDTH 6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_44
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0
+
+#define LPDDR4__DENALI_PHY_45_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_45_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_45
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_46_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_46_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_47_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_47_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_48_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH 7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_49_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_WIDTH 3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_50_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_50_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_51_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_51_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_WIDTH 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_51
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_52_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_52_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_53_READ_MASK 0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_53_WRITE_MASK 0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_54_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_55_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_56_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_56_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0
+
+#define LPDDR4__DENALI_PHY_57_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_58_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_58_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_58
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_58
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_59_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_59
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_60_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_60
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0
+
+#define LPDDR4__DENALI_PHY_61_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_61_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_WIDTH 31U
+#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_61
+#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_62_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_62_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_WIDTH 6U
+#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_62
+#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_63_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_63_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_63
+#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_64_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_64
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_65_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_65_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH 8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WOSET 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0
+
+#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0
+
+#define LPDDR4__DENALI_PHY_66_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_66_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0
+
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0
+
+#define LPDDR4__DENALI_PHY_67_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0
+
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0
+
+#define LPDDR4__DENALI_PHY_68_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0
+
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0
+
+#define LPDDR4__DENALI_PHY_69_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_69_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_69
+#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0
+
+#define LPDDR4__DENALI_PHY_70_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_70_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_WIDTH 18U
+#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_70
+#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0
+
+#define LPDDR4__DENALI_PHY_71_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_71_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_71
+#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0
+
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_71
+#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0
+
+#define LPDDR4__DENALI_PHY_72_READ_MASK 0x071F07FFU
+#define LPDDR4__DENALI_PHY_72_WRITE_MASK 0x071F07FFU
+#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_WIDTH 11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0
+
+#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_WIDTH 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_WIDTH 3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_73_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_73_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET 0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_74_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_74_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_WIDTH 3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_WIDTH 16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_WIDTH 3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_75_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_75_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_WIDTH 16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_WIDTH 2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0
+
+#define LPDDR4__DENALI_PHY_76_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_76_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_WIDTH 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WOSET 0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0
+
+#define LPDDR4__DENALI_PHY_77_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_77_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0
+
+#define LPDDR4__DENALI_PHY_78_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_78_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_WIDTH 10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET 0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_79_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_79_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_WIDTH 4U
+#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0
+
+#define LPDDR4__DENALI_PHY_80_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_80_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0
+
+#define LPDDR4__DENALI_PHY_81_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_81_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_82_READ_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_82_WRITE_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_WIDTH 5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_WIDTH 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_83_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_83_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_84_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_84_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_85_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_85_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_86_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_86_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_87_READ_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_87_WRITE_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_WIDTH 3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__FLD LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0
+
+#define LPDDR4__DENALI_PHY_88_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_88_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_89_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_90_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_90_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_WIDTH 16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0
+
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_WIDTH 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0
+
+#define LPDDR4__DENALI_PHY_91_READ_MASK 0x0303FFFFU
+#define LPDDR4__DENALI_PHY_91_WRITE_MASK 0x0303FFFFU
+#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_WIDTH 8U
+#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_WIDTH 2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_WIDTH 2U
+#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_92_READ_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_92_WRITE_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_WIDTH 2U
+#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WOSET 0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_93_READ_MASK 0x000F1F1FU
+#define LPDDR4__DENALI_PHY_93_WRITE_MASK 0x000F1F1FU
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_WIDTH 4U
+#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_94_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_94_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_WIDTH 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_95_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_95_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_WIDTH 4U
+#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_WIDTH 8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0
+
+#define LPDDR4__DENALI_PHY_96_READ_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_96_WRITE_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH 5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_97_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_97_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0
+
+#define LPDDR4__DENALI_PHY_98_READ_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_98_WRITE_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0
+
+#define LPDDR4__DENALI_PHY_99_READ_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_99_WRITE_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WOSET 0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_100_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_100_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0
+
+#define LPDDR4__DENALI_PHY_101_READ_MASK 0x7F7F0703U
+#define LPDDR4__DENALI_PHY_101_WRITE_MASK 0x7F7F0703U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_WIDTH 2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_WIDTH 3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_WIDTH 7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH 7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_102_READ_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_102_WRITE_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_103_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_103_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_WIDTH 32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_104_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_104_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_WIDTH 4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_105_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_105_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_106_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_106_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_107_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_107_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_108_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_108_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_109_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_109_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_110_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_110_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_111_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_111_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_112_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_112_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_113_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_113_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_114_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_115_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_116_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_117_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_118_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_120_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_120_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0
+
+#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_121_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_121_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET 0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0
+
+#define LPDDR4__DENALI_PHY_122_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_122_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0
+
+#define LPDDR4__DENALI_PHY_123_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_123_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_WIDTH 4U
+#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0
+
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WOSET 0U
+#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0
+
+#define LPDDR4__DENALI_PHY_124_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_124_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_124
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_125_READ_MASK 0x003FFFFFU
+#define LPDDR4__DENALI_PHY_125_WRITE_MASK 0x003FFFFFU
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH 16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0
+
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH 6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0
+
+#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
new file mode 100644
index 0000000..d60bb6a
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
@@ -0,0 +1,2036 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_256_READ_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256_WRITE_MASK 0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_WIDTH 3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_WIDTH 7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_257_READ_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257_WRITE_MASK 0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_258_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_258_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH 2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_259_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_261_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH 6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH 4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_262_READ_MASK 0x030F0F1FU
+#define LPDDR4__DENALI_PHY_262_WRITE_MASK 0x030F0F1FU
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH 4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH 2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_263_READ_MASK 0x01FF031FU
+#define LPDDR4__DENALI_PHY_263_WRITE_MASK 0x01FF031FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_WIDTH 2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_WIDTH 9U
+#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_264_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_264_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1
+
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__FLD LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_265_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH 32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_266_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH 28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_267_READ_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_267_WRITE_MASK 0x7F0101FFU
+#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_WIDTH 9U
+#define LPDDR4__PHY_DQ_IDLE_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_DQ_IDLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1
+
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WOSET 0U
+#define LPDDR4__PHY_PDA_MODE_EN_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_PDA_MODE_EN_1__FLD LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1
+
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_268_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_268_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_WIDTH 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_269_READ_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_269_WRITE_MASK 0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH 6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_270_READ_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_270_WRITE_MASK 0x01FF000FU
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1
+
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WOSET 0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_270
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_271_READ_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_271_WRITE_MASK 0x01FF0701U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WOSET 0U
+#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_271__PHY_LPDDR_1
+
+#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_WIDTH 3U
+#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1
+
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH 9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_272_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_272_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_WIDTH 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_272
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1
+
+#define LPDDR4__DENALI_PHY_273_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_273_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_273
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1
+
+#define LPDDR4__DENALI_PHY_274_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_274_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_WIDTH 2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_274
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1
+
+#define LPDDR4__DENALI_PHY_275_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_275
+#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1
+
+#define LPDDR4__DENALI_PHY_276_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_276
+#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1
+
+#define LPDDR4__DENALI_PHY_277_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_277
+#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1
+
+#define LPDDR4__DENALI_PHY_278_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_278
+#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1
+
+#define LPDDR4__DENALI_PHY_279_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_279
+#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1
+
+#define LPDDR4__DENALI_PHY_280_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_280
+#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1
+
+#define LPDDR4__DENALI_PHY_281_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_281
+#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1
+
+#define LPDDR4__DENALI_PHY_282_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_282
+#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1
+
+#define LPDDR4__DENALI_PHY_283_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_283_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH 3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_284_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285_READ_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_285_WRITE_MASK 0x3F030001U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WOSET 0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WOSET 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_285
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_286_READ_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_286_WRITE_MASK 0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH 5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_288_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_288_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH 8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_MASK 0x03FFFF00U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_WIDTH 18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1
+
+#define LPDDR4__DENALI_PHY_289_READ_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_289_WRITE_MASK 0x00073FFFU
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH 3U
+#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1
+
+#define LPDDR4__DENALI_PHY_290_READ_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_290_WRITE_MASK 0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_291_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_291_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET 0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_291
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1
+
+#define LPDDR4__DENALI_PHY_292_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_292_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1
+
+#define LPDDR4__DENALI_PHY_293_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_293
+#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1
+
+#define LPDDR4__DENALI_PHY_294_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_294
+#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1
+
+#define LPDDR4__DENALI_PHY_295_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_295
+#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1
+
+#define LPDDR4__DENALI_PHY_296_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_WIDTH 32U
+#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_296
+#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1
+
+#define LPDDR4__DENALI_PHY_297_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_297_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_WIDTH 16U
+#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1
+
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WOSET 0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1
+
+#define LPDDR4__DENALI_PHY_298_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_WIDTH 10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_299_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1
+
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH 10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1
+
+#define LPDDR4__DENALI_PHY_300_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_300_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET 0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1
+
+#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_WIDTH 6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_300
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1
+
+#define LPDDR4__DENALI_PHY_301_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_301_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_301
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_302_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_302_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_303_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_303_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH 8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_304_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH 7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_305_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_WIDTH 3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_306_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_306_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_307_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_307_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_WIDTH 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_307
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_308_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_308_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_309_READ_MASK 0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_309_WRITE_MASK 0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH 14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_310_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_311_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_312_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_312_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH 2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1
+
+#define LPDDR4__DENALI_PHY_313_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_314_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_314_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_314
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_314
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_315_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_315
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_316_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_316
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1
+
+#define LPDDR4__DENALI_PHY_317_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_317_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_WIDTH 31U
+#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_317
+#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_318_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_318_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_WIDTH 6U
+#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_318
+#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_319_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_319_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_319
+#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_320_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_320
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_321_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_321_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH 8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WOSET 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1
+
+#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1
+
+#define LPDDR4__DENALI_PHY_322_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_322_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1
+
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1
+
+#define LPDDR4__DENALI_PHY_323_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1
+
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1
+
+#define LPDDR4__DENALI_PHY_324_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1
+
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1
+
+#define LPDDR4__DENALI_PHY_325_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_325_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_325
+#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1
+
+#define LPDDR4__DENALI_PHY_326_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_326_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_WIDTH 18U
+#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_326
+#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1
+
+#define LPDDR4__DENALI_PHY_327_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_327_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_327
+#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1
+
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_WIDTH 9U
+#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_327
+#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1
+
+#define LPDDR4__DENALI_PHY_328_READ_MASK 0x071F07FFU
+#define LPDDR4__DENALI_PHY_328_WRITE_MASK 0x071F07FFU
+#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_WIDTH 11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1
+
+#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_WIDTH 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_WIDTH 3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_329_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_329_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET 0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_330_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_330_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_WIDTH 3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_WIDTH 16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_WIDTH 3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_331_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_331_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_WIDTH 16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_WIDTH 2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1
+
+#define LPDDR4__DENALI_PHY_332_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_332_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH 7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_WIDTH 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WOSET 0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1
+
+#define LPDDR4__DENALI_PHY_333_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_333_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_WIDTH 11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1
+
+#define LPDDR4__DENALI_PHY_334_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_334_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_WIDTH 8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_WIDTH 10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET 0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_335_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_335_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH 6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_WIDTH 4U
+#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1
+
+#define LPDDR4__DENALI_PHY_336_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_336_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1
+
+#define LPDDR4__DENALI_PHY_337_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_337_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_338_READ_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_338_WRITE_MASK 0x007F1F1FU
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_WIDTH 5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_WIDTH 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_339_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_339_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_340_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_340_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_341_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_341_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_342_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_342_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_343_READ_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_343_WRITE_MASK 0x1F0703FFU
+#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_WIDTH 3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__FLD LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1
+
+#define LPDDR4__DENALI_PHY_344_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_344_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_345_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_WIDTH 4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_346_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_346_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_WIDTH 16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1
+
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_WIDTH 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1
+
+#define LPDDR4__DENALI_PHY_347_READ_MASK 0x0303FFFFU
+#define LPDDR4__DENALI_PHY_347_WRITE_MASK 0x0303FFFFU
+#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_WIDTH 8U
+#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_WIDTH 2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_WIDTH 2U
+#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_348_READ_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_348_WRITE_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_WIDTH 2U
+#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WOSET 0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_349_READ_MASK 0x000F1F1FU
+#define LPDDR4__DENALI_PHY_349_WRITE_MASK 0x000F1F1FU
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_WIDTH 4U
+#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_350_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_350_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_WIDTH 11U
+#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_WIDTH 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_351_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_351_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH 8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_WIDTH 4U
+#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_WIDTH 8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1
+
+#define LPDDR4__DENALI_PHY_352_READ_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_352_WRITE_MASK 0x001F0F3FU
+#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH 6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH 5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_353_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_353_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1
+
+#define LPDDR4__DENALI_PHY_354_READ_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_354_WRITE_MASK 0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_WIDTH 8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_WIDTH 9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1
+
+#define LPDDR4__DENALI_PHY_355_READ_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_355_WRITE_MASK 0x00000F01U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WOSET 0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_356_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_356_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1
+
+#define LPDDR4__DENALI_PHY_357_READ_MASK 0x7F7F0703U
+#define LPDDR4__DENALI_PHY_357_WRITE_MASK 0x7F7F0703U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_WIDTH 2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_WIDTH 3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_WIDTH 7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH 7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_358_READ_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_358_WRITE_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_WIDTH 5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_359_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_359_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_WIDTH 32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_360_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_360_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_WIDTH 4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_361_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_361_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_362_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_362_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_363_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_363_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_364_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_364_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_365_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_365_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_366_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_366_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH 2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_367_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_367_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_368_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_368_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_369_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_369_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_370_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_371_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_372_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_373_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_374_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_376_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_376_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH 4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_WIDTH 3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1
+
+#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_377_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_377_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH 10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET 0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1
+
+#define LPDDR4__DENALI_PHY_378_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_378_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH 10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_WIDTH 4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1
+
+#define LPDDR4__DENALI_PHY_379_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_379_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH 11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_WIDTH 4U
+#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1
+
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WOSET 0U
+#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1
+
+#define LPDDR4__DENALI_PHY_380_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_380_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH 10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_380
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_381_READ_MASK 0x003FFFFFU
+#define LPDDR4__DENALI_PHY_381_WRITE_MASK 0x003FFFFFU
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH 16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1
+
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH 6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1
+
+#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
new file mode 100644
index 0000000..3df803e
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
@@ -0,0 +1,6436 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+
+#define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_0__START_SHIFT 0U
+#define LPDDR4__DENALI_CTL_0__START_WIDTH 1U
+#define LPDDR4__DENALI_CTL_0__START_WOCLR 0U
+#define LPDDR4__DENALI_CTL_0__START_WOSET 0U
+#define LPDDR4__START__REG DENALI_CTL_0
+#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
+
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U
+#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
+#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
+
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U
+#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
+#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
+
+#define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U
+#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
+#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
+
+#define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U
+#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
+#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
+
+#define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U
+#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U
+#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U
+#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
+
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U
+#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
+#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U
+#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
+#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
+
+#define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U
+#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
+#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
+
+#define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U
+#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
+#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
+
+#define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U
+#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
+#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
+
+#define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U
+#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
+#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
+
+#define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U
+#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
+#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
+
+#define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U
+#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
+#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
+
+#define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U
+#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
+#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
+
+#define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U
+#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
+#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
+
+#define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U
+#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
+#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
+
+#define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U
+#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
+#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
+
+#define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U
+#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
+#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
+
+#define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U
+#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
+#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
+
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U
+#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
+#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_CTL_19_READ_MASK 0x03030301U
+#define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x03030301U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U
+#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
+#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_WIDTH 2U
+#define LPDDR4__DFI_FREQ_RATIO_F0__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F0__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_WIDTH 2U
+#define LPDDR4__DFI_FREQ_RATIO_F1__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F1__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_WIDTH 2U
+#define LPDDR4__DFI_FREQ_RATIO_F2__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F2__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2
+
+#define LPDDR4__DENALI_CTL_20_READ_MASK 0x01030101U
+#define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x01030101U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_SHIFT 0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WIDTH 1U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOCLR 0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOSET 0U
+#define LPDDR4__DFI_CMD_RATIO__REG DENALI_CTL_20
+#define LPDDR4__DFI_CMD_RATIO__FLD LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO
+
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOSET 0U
+#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_20
+#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_20__NO_MRW_INIT
+
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_WIDTH 2U
+#define LPDDR4__ODT_VALUE__REG DENALI_CTL_20
+#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_20__ODT_VALUE
+
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
+
+#define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_WIDTH 6U
+#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_21
+#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR
+
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOSET 0U
+#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_21
+#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U
+#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U
+#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
+
+#define LPDDR4__DENALI_CTL_22_READ_MASK 0x0303031FU
+#define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x0303031FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_WIDTH 5U
+#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_22
+#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
+
+#define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U
+#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
+#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
+
+#define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U
+#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
+#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
+
+#define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_WIDTH 16U
+#define LPDDR4__TDLL_F0__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F0__FLD LPDDR4__DENALI_CTL_25__TDLL_F0
+
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_WIDTH 16U
+#define LPDDR4__TDLL_F1__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F1__FLD LPDDR4__DENALI_CTL_25__TDLL_F1
+
+#define LPDDR4__DENALI_CTL_26_READ_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_WIDTH 16U
+#define LPDDR4__TDLL_F2__REG DENALI_CTL_26
+#define LPDDR4__TDLL_F2__FLD LPDDR4__DENALI_CTL_26__TDLL_F2
+
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOSET 0U
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__REG DENALI_CTL_26
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__FLD LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS
+
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_WIDTH 2U
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__REG DENALI_CTL_26
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS
+
+#define LPDDR4__DENALI_CTL_27_READ_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_SHIFT 0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WIDTH 1U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOCLR 0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOSET 0U
+#define LPDDR4__DQS_OSC_TST__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_TST__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_TST
+
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_MASK 0xFFFFFF00U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_WIDTH 24U
+#define LPDDR4__DQS_OSC_MPC_CMD__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_MPC_CMD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD
+
+#define LPDDR4__DENALI_CTL_28_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_WIDTH 8U
+#define LPDDR4__MRR_LSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_LSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_LSB_REG
+
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_SHIFT 8U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_WIDTH 8U
+#define LPDDR4__MRR_MSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_MSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_MSB_REG
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOSET 0U
+#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE
+
+#define LPDDR4__DENALI_CTL_29_READ_MASK 0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29_WRITE_MASK 0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_MASK 0x00007FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_WIDTH 15U
+#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD
+
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_SHIFT 16U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_WIDTH 4U
+#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_29
+#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES
+
+#define LPDDR4__DENALI_CTL_30_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_WIDTH 32U
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_30
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_WIDTH 32U
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_31
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_WIDTH 32U
+#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_32
+#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 32U
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_33
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_34_READ_MASK 0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34_WRITE_MASK 0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_WIDTH 16U
+#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_34
+#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT
+
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_SHIFT 16U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WIDTH 1U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOCLR 0U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOSET 0U
+#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_34
+#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST
+
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_WIDTH 8U
+#define LPDDR4__TOSCO_F0__REG DENALI_CTL_34
+#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_34__TOSCO_F0
+
+#define LPDDR4__DENALI_CTL_35_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_WIDTH 8U
+#define LPDDR4__TOSCO_F1__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_35__TOSCO_F1
+
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_WIDTH 8U
+#define LPDDR4__TOSCO_F2__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_35__TOSCO_F2
+
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_35
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0
+
+#define LPDDR4__DENALI_CTL_36_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0
+
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1
+
+#define LPDDR4__DENALI_CTL_37_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_37_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_WIDTH 16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1
+
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_WIDTH 4U
+#define LPDDR4__DQS_OSC_STATUS__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_STATUS__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS
+
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WOSET 0U
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS
+
+#define LPDDR4__DENALI_CTL_38_READ_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_38_WRITE_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_WIDTH 7U
+#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_38
+#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_CTL_38__WRLAT_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_38__WRLAT_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_38__WRLAT_F0_WIDTH 7U
+#define LPDDR4__WRLAT_F0__REG DENALI_CTL_38
+#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_38__WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_WIDTH 6U
+#define LPDDR4__ADDITIVE_LAT_F0__REG DENALI_CTL_38
+#define LPDDR4__ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0
+
+#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_WIDTH 4U
+#define LPDDR4__CA_PARITY_LAT_F0__REG DENALI_CTL_38
+#define LPDDR4__CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0
+
+#define LPDDR4__DENALI_CTL_39_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_39_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_WIDTH 8U
+#define LPDDR4__TMOD_PAR_F0__REG DENALI_CTL_39
+#define LPDDR4__TMOD_PAR_F0__FLD LPDDR4__DENALI_CTL_39__TMOD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_WIDTH 8U
+#define LPDDR4__TMRD_PAR_F0__REG DENALI_CTL_39
+#define LPDDR4__TMRD_PAR_F0__FLD LPDDR4__DENALI_CTL_39__TMRD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_WIDTH 8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__REG DENALI_CTL_39
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_WIDTH 8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__REG DENALI_CTL_39
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_40_READ_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40_WRITE_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_WIDTH 7U
+#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_40
+#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_CTL_40__WRLAT_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F1_WIDTH 7U
+#define LPDDR4__WRLAT_F1__REG DENALI_CTL_40
+#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_40__WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_WIDTH 6U
+#define LPDDR4__ADDITIVE_LAT_F1__REG DENALI_CTL_40
+#define LPDDR4__ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1
+
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_WIDTH 4U
+#define LPDDR4__CA_PARITY_LAT_F1__REG DENALI_CTL_40
+#define LPDDR4__CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1
+
+#define LPDDR4__DENALI_CTL_41_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_WIDTH 8U
+#define LPDDR4__TMOD_PAR_F1__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_F1__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_WIDTH 8U
+#define LPDDR4__TMRD_PAR_F1__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_F1__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_WIDTH 8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_WIDTH 8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_42_READ_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_WIDTH 7U
+#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_42
+#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_CTL_42__WRLAT_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F2_WIDTH 7U
+#define LPDDR4__WRLAT_F2__REG DENALI_CTL_42
+#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_42__WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_WIDTH 6U
+#define LPDDR4__ADDITIVE_LAT_F2__REG DENALI_CTL_42
+#define LPDDR4__ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2
+
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_WIDTH 4U
+#define LPDDR4__CA_PARITY_LAT_F2__REG DENALI_CTL_42
+#define LPDDR4__CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2
+
+#define LPDDR4__DENALI_CTL_43_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_WIDTH 8U
+#define LPDDR4__TMOD_PAR_F2__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_F2__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_WIDTH 8U
+#define LPDDR4__TMRD_PAR_F2__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_F2__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_WIDTH 8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_WIDTH 8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_44_READ_MASK 0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_44_WRITE_MASK 0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_WIDTH 3U
+#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_44
+#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL
+
+#define LPDDR4__DENALI_CTL_44__TCCD_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_44__TCCD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_44__TCCD_WIDTH 5U
+#define LPDDR4__TCCD__REG DENALI_CTL_44
+#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_44__TCCD
+
+#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_WIDTH 5U
+#define LPDDR4__TCCD_L_F0__REG DENALI_CTL_44
+#define LPDDR4__TCCD_L_F0__FLD LPDDR4__DENALI_CTL_44__TCCD_L_F0
+
+#define LPDDR4__DENALI_CTL_44__TRRD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_44__TRRD_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_44__TRRD_F0_WIDTH 8U
+#define LPDDR4__TRRD_F0__REG DENALI_CTL_44
+#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_44__TRRD_F0
+
+#define LPDDR4__DENALI_CTL_45_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_45_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_WIDTH 8U
+#define LPDDR4__TRRD_L_F0__REG DENALI_CTL_45
+#define LPDDR4__TRRD_L_F0__FLD LPDDR4__DENALI_CTL_45__TRRD_L_F0
+
+#define LPDDR4__DENALI_CTL_45__TRC_F0_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_45__TRC_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_45__TRC_F0_WIDTH 9U
+#define LPDDR4__TRC_F0__REG DENALI_CTL_45
+#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_45__TRC_F0
+
+#define LPDDR4__DENALI_CTL_46_READ_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_46_WRITE_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_MASK 0x000001FFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_WIDTH 9U
+#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_46
+#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_46__TRAS_MIN_F0
+
+#define LPDDR4__DENALI_CTL_46__TWTR_F0_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_46__TWTR_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_46__TWTR_F0_WIDTH 6U
+#define LPDDR4__TWTR_F0__REG DENALI_CTL_46
+#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_46__TWTR_F0
+
+#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_WIDTH 6U
+#define LPDDR4__TWTR_L_F0__REG DENALI_CTL_46
+#define LPDDR4__TWTR_L_F0__FLD LPDDR4__DENALI_CTL_46__TWTR_L_F0
+
+#define LPDDR4__DENALI_CTL_47_READ_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_47_WRITE_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_47__TRP_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_47__TRP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_47__TRP_F0_WIDTH 8U
+#define LPDDR4__TRP_F0__REG DENALI_CTL_47
+#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_47__TRP_F0
+
+#define LPDDR4__DENALI_CTL_47__TFAW_F0_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_47__TFAW_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_47__TFAW_F0_WIDTH 9U
+#define LPDDR4__TFAW_F0__REG DENALI_CTL_47
+#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_47__TFAW_F0
+
+#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_WIDTH 5U
+#define LPDDR4__TCCD_L_F1__REG DENALI_CTL_47
+#define LPDDR4__TCCD_L_F1__FLD LPDDR4__DENALI_CTL_47__TCCD_L_F1
+
+#define LPDDR4__DENALI_CTL_48_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_48__TRRD_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_48__TRRD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_48__TRRD_F1_WIDTH 8U
+#define LPDDR4__TRRD_F1__REG DENALI_CTL_48
+#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_48__TRRD_F1
+
+#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_WIDTH 8U
+#define LPDDR4__TRRD_L_F1__REG DENALI_CTL_48
+#define LPDDR4__TRRD_L_F1__FLD LPDDR4__DENALI_CTL_48__TRRD_L_F1
+
+#define LPDDR4__DENALI_CTL_48__TRC_F1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_CTL_48__TRC_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_48__TRC_F1_WIDTH 9U
+#define LPDDR4__TRC_F1__REG DENALI_CTL_48
+#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_48__TRC_F1
+
+#define LPDDR4__DENALI_CTL_49_READ_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_MASK 0x000001FFU
+#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_WIDTH 9U
+#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_49
+#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_49__TRAS_MIN_F1
+
+#define LPDDR4__DENALI_CTL_49__TWTR_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_49__TWTR_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_49__TWTR_F1_WIDTH 6U
+#define LPDDR4__TWTR_F1__REG DENALI_CTL_49
+#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_49__TWTR_F1
+
+#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_WIDTH 6U
+#define LPDDR4__TWTR_L_F1__REG DENALI_CTL_49
+#define LPDDR4__TWTR_L_F1__FLD LPDDR4__DENALI_CTL_49__TWTR_L_F1
+
+#define LPDDR4__DENALI_CTL_50_READ_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_50_WRITE_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_50__TRP_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_50__TRP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_50__TRP_F1_WIDTH 8U
+#define LPDDR4__TRP_F1__REG DENALI_CTL_50
+#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_50__TRP_F1
+
+#define LPDDR4__DENALI_CTL_50__TFAW_F1_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_50__TFAW_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_50__TFAW_F1_WIDTH 9U
+#define LPDDR4__TFAW_F1__REG DENALI_CTL_50
+#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_50__TFAW_F1
+
+#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_WIDTH 5U
+#define LPDDR4__TCCD_L_F2__REG DENALI_CTL_50
+#define LPDDR4__TCCD_L_F2__FLD LPDDR4__DENALI_CTL_50__TCCD_L_F2
+
+#define LPDDR4__DENALI_CTL_51_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_51__TRRD_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_51__TRRD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_51__TRRD_F2_WIDTH 8U
+#define LPDDR4__TRRD_F2__REG DENALI_CTL_51
+#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_51__TRRD_F2
+
+#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_WIDTH 8U
+#define LPDDR4__TRRD_L_F2__REG DENALI_CTL_51
+#define LPDDR4__TRRD_L_F2__FLD LPDDR4__DENALI_CTL_51__TRRD_L_F2
+
+#define LPDDR4__DENALI_CTL_51__TRC_F2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_CTL_51__TRC_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_51__TRC_F2_WIDTH 9U
+#define LPDDR4__TRC_F2__REG DENALI_CTL_51
+#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_51__TRC_F2
+
+#define LPDDR4__DENALI_CTL_52_READ_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_MASK 0x000001FFU
+#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_WIDTH 9U
+#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_52
+#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_52__TRAS_MIN_F2
+
+#define LPDDR4__DENALI_CTL_52__TWTR_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_52__TWTR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_52__TWTR_F2_WIDTH 6U
+#define LPDDR4__TWTR_F2__REG DENALI_CTL_52
+#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_52__TWTR_F2
+
+#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_WIDTH 6U
+#define LPDDR4__TWTR_L_F2__REG DENALI_CTL_52
+#define LPDDR4__TWTR_L_F2__FLD LPDDR4__DENALI_CTL_52__TWTR_L_F2
+
+#define LPDDR4__DENALI_CTL_53_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_53_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_53__TRP_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_53__TRP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_53__TRP_F2_WIDTH 8U
+#define LPDDR4__TRP_F2__REG DENALI_CTL_53
+#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_53__TRP_F2
+
+#define LPDDR4__DENALI_CTL_53__TFAW_F2_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_53__TFAW_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_53__TFAW_F2_WIDTH 9U
+#define LPDDR4__TFAW_F2__REG DENALI_CTL_53
+#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_53__TFAW_F2
+
+#define LPDDR4__DENALI_CTL_53__TRTP_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_53__TRTP_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_53__TRTP_F0_WIDTH 8U
+#define LPDDR4__TRTP_F0__REG DENALI_CTL_53
+#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_53__TRTP_F0
+
+#define LPDDR4__DENALI_CTL_54_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_WIDTH 8U
+#define LPDDR4__TRTP_AP_F0__REG DENALI_CTL_54
+#define LPDDR4__TRTP_AP_F0__FLD LPDDR4__DENALI_CTL_54__TRTP_AP_F0
+
+#define LPDDR4__DENALI_CTL_54__TMRD_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_54__TMRD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_54__TMRD_F0_WIDTH 8U
+#define LPDDR4__TMRD_F0__REG DENALI_CTL_54
+#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_54__TMRD_F0
+
+#define LPDDR4__DENALI_CTL_54__TMOD_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_54__TMOD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_54__TMOD_F0_WIDTH 8U
+#define LPDDR4__TMOD_F0__REG DENALI_CTL_54
+#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_54__TMOD_F0
+
+#define LPDDR4__DENALI_CTL_55_READ_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_55_WRITE_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_WIDTH 20U
+#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_55
+#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_55__TRAS_MAX_F0
+
+#define LPDDR4__DENALI_CTL_55__TCKE_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_55__TCKE_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_55__TCKE_F0_WIDTH 5U
+#define LPDDR4__TCKE_F0__REG DENALI_CTL_55
+#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_55__TCKE_F0
+
+#define LPDDR4__DENALI_CTL_56_READ_MASK 0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_56_WRITE_MASK 0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_56__TCKESR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_56__TCKESR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_56__TCKESR_F0_WIDTH 8U
+#define LPDDR4__TCKESR_F0__REG DENALI_CTL_56
+#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_56__TCKESR_F0
+
+#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_WIDTH 6U
+#define LPDDR4__TCCDMW_F0__REG DENALI_CTL_56
+#define LPDDR4__TCCDMW_F0__FLD LPDDR4__DENALI_CTL_56__TCCDMW_F0
+
+#define LPDDR4__DENALI_CTL_56__TRTP_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_56__TRTP_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_56__TRTP_F1_WIDTH 8U
+#define LPDDR4__TRTP_F1__REG DENALI_CTL_56
+#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_56__TRTP_F1
+
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_WIDTH 8U
+#define LPDDR4__TRTP_AP_F1__REG DENALI_CTL_56
+#define LPDDR4__TRTP_AP_F1__FLD LPDDR4__DENALI_CTL_56__TRTP_AP_F1
+
+#define LPDDR4__DENALI_CTL_57_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_57__TMRD_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_57__TMRD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_57__TMRD_F1_WIDTH 8U
+#define LPDDR4__TMRD_F1__REG DENALI_CTL_57
+#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_57__TMRD_F1
+
+#define LPDDR4__DENALI_CTL_57__TMOD_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_57__TMOD_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_57__TMOD_F1_WIDTH 8U
+#define LPDDR4__TMOD_F1__REG DENALI_CTL_57
+#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_57__TMOD_F1
+
+#define LPDDR4__DENALI_CTL_58_READ_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_58_WRITE_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_WIDTH 20U
+#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_58
+#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_58__TRAS_MAX_F1
+
+#define LPDDR4__DENALI_CTL_58__TCKE_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_58__TCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_58__TCKE_F1_WIDTH 5U
+#define LPDDR4__TCKE_F1__REG DENALI_CTL_58
+#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_58__TCKE_F1
+
+#define LPDDR4__DENALI_CTL_59_READ_MASK 0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_59_WRITE_MASK 0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_59__TCKESR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_59__TCKESR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_59__TCKESR_F1_WIDTH 8U
+#define LPDDR4__TCKESR_F1__REG DENALI_CTL_59
+#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_59__TCKESR_F1
+
+#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_WIDTH 6U
+#define LPDDR4__TCCDMW_F1__REG DENALI_CTL_59
+#define LPDDR4__TCCDMW_F1__FLD LPDDR4__DENALI_CTL_59__TCCDMW_F1
+
+#define LPDDR4__DENALI_CTL_59__TRTP_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_59__TRTP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_59__TRTP_F2_WIDTH 8U
+#define LPDDR4__TRTP_F2__REG DENALI_CTL_59
+#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_59__TRTP_F2
+
+#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_WIDTH 8U
+#define LPDDR4__TRTP_AP_F2__REG DENALI_CTL_59
+#define LPDDR4__TRTP_AP_F2__FLD LPDDR4__DENALI_CTL_59__TRTP_AP_F2
+
+#define LPDDR4__DENALI_CTL_60_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_60__TMRD_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_60__TMRD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_60__TMRD_F2_WIDTH 8U
+#define LPDDR4__TMRD_F2__REG DENALI_CTL_60
+#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_60__TMRD_F2
+
+#define LPDDR4__DENALI_CTL_60__TMOD_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_60__TMOD_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_60__TMOD_F2_WIDTH 8U
+#define LPDDR4__TMOD_F2__REG DENALI_CTL_60
+#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_60__TMOD_F2
+
+#define LPDDR4__DENALI_CTL_61_READ_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_61_WRITE_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_WIDTH 20U
+#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_61
+#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_61__TRAS_MAX_F2
+
+#define LPDDR4__DENALI_CTL_61__TCKE_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_61__TCKE_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_61__TCKE_F2_WIDTH 5U
+#define LPDDR4__TCKE_F2__REG DENALI_CTL_61
+#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_61__TCKE_F2
+
+#define LPDDR4__DENALI_CTL_62_READ_MASK 0x07073FFFU
+#define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x07073FFFU
+#define LPDDR4__DENALI_CTL_62__TCKESR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_62__TCKESR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_62__TCKESR_F2_WIDTH 8U
+#define LPDDR4__TCKESR_F2__REG DENALI_CTL_62
+#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_62__TCKESR_F2
+
+#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_WIDTH 6U
+#define LPDDR4__TCCDMW_F2__REG DENALI_CTL_62
+#define LPDDR4__TCCDMW_F2__FLD LPDDR4__DENALI_CTL_62__TCCDMW_F2
+
+#define LPDDR4__DENALI_CTL_62__TPPD_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_62__TPPD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_62__TPPD_WIDTH 3U
+#define LPDDR4__TPPD__REG DENALI_CTL_62
+#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_62__TPPD
+
+#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_WIDTH 3U
+#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_62
+#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_62__MC_RESERVED0
+
+#define LPDDR4__DENALI_CTL_63_READ_MASK 0xFFFF0107U
+#define LPDDR4__DENALI_CTL_63_WRITE_MASK 0xFFFF0107U
+#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_WIDTH 3U
+#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_63
+#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_63__MC_RESERVED1
+
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WOSET 0U
+#define LPDDR4__WRITEINTERP__REG DENALI_CTL_63
+#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_63__WRITEINTERP
+
+#define LPDDR4__DENALI_CTL_63__TRCD_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_63__TRCD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_63__TRCD_F0_WIDTH 8U
+#define LPDDR4__TRCD_F0__REG DENALI_CTL_63
+#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_63__TRCD_F0
+
+#define LPDDR4__DENALI_CTL_63__TWR_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_63__TWR_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_63__TWR_F0_WIDTH 8U
+#define LPDDR4__TWR_F0__REG DENALI_CTL_63
+#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_63__TWR_F0
+
+#define LPDDR4__DENALI_CTL_64_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_64_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_64__TRCD_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_64__TRCD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_64__TRCD_F1_WIDTH 8U
+#define LPDDR4__TRCD_F1__REG DENALI_CTL_64
+#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_64__TRCD_F1
+
+#define LPDDR4__DENALI_CTL_64__TWR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_64__TWR_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_64__TWR_F1_WIDTH 8U
+#define LPDDR4__TWR_F1__REG DENALI_CTL_64
+#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_64__TWR_F1
+
+#define LPDDR4__DENALI_CTL_64__TRCD_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_64__TRCD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_64__TRCD_F2_WIDTH 8U
+#define LPDDR4__TRCD_F2__REG DENALI_CTL_64
+#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_64__TRCD_F2
+
+#define LPDDR4__DENALI_CTL_64__TWR_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_64__TWR_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_64__TWR_F2_WIDTH 8U
+#define LPDDR4__TWR_F2__REG DENALI_CTL_64
+#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_64__TWR_F2
+
+#define LPDDR4__DENALI_CTL_65_READ_MASK 0x0101010FU
+#define LPDDR4__DENALI_CTL_65_WRITE_MASK 0x0101010FU
+#define LPDDR4__DENALI_CTL_65__TMRR_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_65__TMRR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_65__TMRR_WIDTH 4U
+#define LPDDR4__TMRR__REG DENALI_CTL_65
+#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_65__TMRR
+
+#define LPDDR4__DENALI_CTL_65__AP_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_65__AP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_65__AP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_65__AP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_65__AP_WOSET 0U
+#define LPDDR4__AP__REG DENALI_CTL_65
+#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_65__AP
+
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_SHIFT 16U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WOSET 0U
+#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_65
+#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_65__CONCURRENTAP
+
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WOSET 0U
+#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_65
+#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT
+
+#define LPDDR4__DENALI_CTL_66_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_66_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_66__TDAL_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_66__TDAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_66__TDAL_F0_WIDTH 8U
+#define LPDDR4__TDAL_F0__REG DENALI_CTL_66
+#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_66__TDAL_F0
+
+#define LPDDR4__DENALI_CTL_66__TDAL_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_66__TDAL_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_66__TDAL_F1_WIDTH 8U
+#define LPDDR4__TDAL_F1__REG DENALI_CTL_66
+#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_66__TDAL_F1
+
+#define LPDDR4__DENALI_CTL_66__TDAL_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_66__TDAL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_66__TDAL_F2_WIDTH 8U
+#define LPDDR4__TDAL_F2__REG DENALI_CTL_66
+#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_66__TDAL_F2
+
+#define LPDDR4__DENALI_CTL_66__BSTLEN_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_66__BSTLEN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_66__BSTLEN_WIDTH 6U
+#define LPDDR4__BSTLEN__REG DENALI_CTL_66
+#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_66__BSTLEN
+
+#define LPDDR4__DENALI_CTL_67_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_67_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_WIDTH 8U
+#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F0_0
+
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_WIDTH 8U
+#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F1_0
+
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_WIDTH 8U
+#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F2_0
+
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_WIDTH 8U
+#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F0_1
+
+#define LPDDR4__DENALI_CTL_68_READ_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_WIDTH 8U
+#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_68
+#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_68__TRP_AB_F1_1
+
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_WIDTH 8U
+#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_68
+#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_68__TRP_AB_F2_1
+
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WOSET 0U
+#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_68
+#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_SHIFT 24U
+#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_WIDTH 2U
+#define LPDDR4__ADDRESS_MIRRORING__REG DENALI_CTL_68
+#define LPDDR4__ADDRESS_MIRRORING__FLD LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING
+
+#define LPDDR4__DENALI_CTL_69_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_69_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WOSET 0U
+#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_69
+#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN
+
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WOSET 0U
+#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_69
+#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_69__MC_RESERVED2
+
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_SHIFT 16U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WIDTH 1U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WOCLR 0U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WOSET 0U
+#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_69
+#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_69__NO_MEMORY_DM
+
+#define LPDDR4__DENALI_CTL_70_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_70_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_WIDTH 26U
+#define LPDDR4__CA_PARITY_ERROR_INJECT__REG DENALI_CTL_70
+#define LPDDR4__CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT
+
+#define LPDDR4__DENALI_CTL_71_READ_MASK 0x01010001U
+#define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x01010001U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WIDTH 1U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WOCLR 0U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WOSET 0U
+#define LPDDR4__CA_PARITY_ERROR__REG DENALI_CTL_71
+#define LPDDR4__CA_PARITY_ERROR__FLD LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR
+
+#define LPDDR4__DENALI_CTL_71__AREFRESH_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_WIDTH 1U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_WOCLR 0U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_WOSET 0U
+#define LPDDR4__AREFRESH__REG DENALI_CTL_71
+#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_71__AREFRESH
+
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WOSET 0U
+#define LPDDR4__AREF_STATUS__REG DENALI_CTL_71
+#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_71__AREF_STATUS
+
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WOSET 0U
+#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_71
+#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_71__TREF_ENABLE
+
+#define LPDDR4__DENALI_CTL_72_READ_MASK 0x03FF3F07U
+#define LPDDR4__DENALI_CTL_72_WRITE_MASK 0x03FF3F07U
+#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_WIDTH 3U
+#define LPDDR4__TRFC_OPT_THRESHOLD__REG DENALI_CTL_72
+#define LPDDR4__TRFC_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_72
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH
+
+#define LPDDR4__DENALI_CTL_72__TRFC_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_72__TRFC_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_72__TRFC_F0_WIDTH 10U
+#define LPDDR4__TRFC_F0__REG DENALI_CTL_72
+#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_72__TRFC_F0
+
+#define LPDDR4__DENALI_CTL_73_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_73_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_73__TREF_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_73__TREF_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_73__TREF_F0_WIDTH 20U
+#define LPDDR4__TREF_F0__REG DENALI_CTL_73
+#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_73__TREF_F0
+
+#define LPDDR4__DENALI_CTL_74_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_74__TRFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_74__TRFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_74__TRFC_F1_WIDTH 10U
+#define LPDDR4__TRFC_F1__REG DENALI_CTL_74
+#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_74__TRFC_F1
+
+#define LPDDR4__DENALI_CTL_75_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_75__TREF_F1_WIDTH 20U
+#define LPDDR4__TREF_F1__REG DENALI_CTL_75
+#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_75__TREF_F1
+
+#define LPDDR4__DENALI_CTL_76_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_76__TRFC_F2_WIDTH 10U
+#define LPDDR4__TRFC_F2__REG DENALI_CTL_76
+#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_76__TRFC_F2
+
+#define LPDDR4__DENALI_CTL_77_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_77__TREF_F2_WIDTH 20U
+#define LPDDR4__TREF_F2__REG DENALI_CTL_77
+#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_77__TREF_F2
+
+#define LPDDR4__DENALI_CTL_78_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_WIDTH 20U
+#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_78
+#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_78__TREF_INTERVAL
+
+#define LPDDR4__DENALI_CTL_79_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_79_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_WIDTH 10U
+#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_79
+#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_79__TRFC_PB_F0
+
+#define LPDDR4__DENALI_CTL_80_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_WIDTH 20U
+#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_80
+#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_80__TREFI_PB_F0
+
+#define LPDDR4__DENALI_CTL_81_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_81_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_WIDTH 10U
+#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_81
+#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_81__TRFC_PB_F1
+
+#define LPDDR4__DENALI_CTL_82_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_WIDTH 20U
+#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_82
+#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_82__TREFI_PB_F1
+
+#define LPDDR4__DENALI_CTL_83_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_WIDTH 10U
+#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_83
+#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_83__TRFC_PB_F2
+
+#define LPDDR4__DENALI_CTL_84_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_84_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_WIDTH 20U
+#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_84
+#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_84__TREFI_PB_F2
+
+#define LPDDR4__DENALI_CTL_84__PBR_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_WOSET 0U
+#define LPDDR4__PBR_EN__REG DENALI_CTL_84
+#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_84__PBR_EN
+
+#define LPDDR4__DENALI_CTL_85_READ_MASK 0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_SHIFT 0U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WIDTH 1U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WOCLR 0U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WOSET 0U
+#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_85
+#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER
+
+#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_WIDTH 16U
+#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_85
+#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT
+
+#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_SHIFT 24U
+#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_WIDTH 4U
+#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_85
+#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY
+
+#define LPDDR4__DENALI_CTL_86_READ_MASK 0x001F1F01U
+#define LPDDR4__DENALI_CTL_86_WRITE_MASK 0x001F1F01U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WOSET 0U
+#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_86
+#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN
+
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_86
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_86
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_87_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_87_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_87__TPDEX_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_87__TPDEX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_87__TPDEX_F0_WIDTH 16U
+#define LPDDR4__TPDEX_F0__REG DENALI_CTL_87
+#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_87__TPDEX_F0
+
+#define LPDDR4__DENALI_CTL_87__TPDEX_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_87__TPDEX_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_87__TPDEX_F1_WIDTH 16U
+#define LPDDR4__TPDEX_F1__REG DENALI_CTL_87
+#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_87__TPDEX_F1
+
+#define LPDDR4__DENALI_CTL_88_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_88__TPDEX_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_88__TPDEX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_88__TPDEX_F2_WIDTH 16U
+#define LPDDR4__TPDEX_F2__REG DENALI_CTL_88
+#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_88__TPDEX_F2
+
+#define LPDDR4__DENALI_CTL_89_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_WIDTH 32U
+#define LPDDR4__CTL_UNUSED_REG_0__REG DENALI_CTL_89
+#define LPDDR4__CTL_UNUSED_REG_0__FLD LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0
+
+#define LPDDR4__DENALI_CTL_90_READ_MASK 0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_90_WRITE_MASK 0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_WIDTH 8U
+#define LPDDR4__TMRRI_F0__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_90__TMRRI_F0
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_WIDTH 8U
+#define LPDDR4__TMRRI_F1__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_90__TMRRI_F1
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F2_WIDTH 8U
+#define LPDDR4__TMRRI_F2__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_90__TMRRI_F2
+
+#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_WIDTH 5U
+#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_90
+#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_90__TCKELCS_F0
+
+#define LPDDR4__DENALI_CTL_91_READ_MASK 0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_91_WRITE_MASK 0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_WIDTH 5U
+#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_91
+#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKEHCS_F0
+
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_WIDTH 5U
+#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_91
+#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_91__TMRWCKEL_F0
+
+#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_WIDTH 4U
+#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_91
+#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_91__TZQCKE_F0
+
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_WIDTH 5U
+#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_91
+#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_91__TCKELCS_F1
+
+#define LPDDR4__DENALI_CTL_92_READ_MASK 0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_WIDTH 5U
+#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_92
+#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKEHCS_F1
+
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_WIDTH 5U
+#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_92
+#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_92__TMRWCKEL_F1
+
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_WIDTH 4U
+#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_92
+#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_92__TZQCKE_F1
+
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_WIDTH 5U
+#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_92
+#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_92__TCKELCS_F2
+
+#define LPDDR4__DENALI_CTL_93_READ_MASK 0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_93_WRITE_MASK 0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_WIDTH 5U
+#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_93
+#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKEHCS_F2
+
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_WIDTH 5U
+#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_93
+#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_93__TMRWCKEL_F2
+
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_WIDTH 4U
+#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_93
+#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_93__TZQCKE_F2
+
+#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_WIDTH 5U
+#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_93
+#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_93__TCSCKE_F0
+
+#define LPDDR4__DENALI_CTL_94_READ_MASK 0x1F011F01U
+#define LPDDR4__DENALI_CTL_94_WRITE_MASK 0x1F011F01U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOSET 0U
+#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_94
+#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_WIDTH 5U
+#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F1
+
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WOSET 0U
+#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_94
+#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_WIDTH 5U
+#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F2
+
+#define LPDDR4__DENALI_CTL_95_READ_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_CTL_95_WRITE_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOSET 0U
+#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_95
+#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2
+
+#define LPDDR4__DENALI_CTL_95__TXSR_F0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_95__TXSR_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_95__TXSR_F0_WIDTH 16U
+#define LPDDR4__TXSR_F0__REG DENALI_CTL_95
+#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_95__TXSR_F0
+
+#define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_WIDTH 16U
+#define LPDDR4__TXSNR_F0__REG DENALI_CTL_96
+#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_96__TXSNR_F0
+
+#define LPDDR4__DENALI_CTL_96__TXSR_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_96__TXSR_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_96__TXSR_F1_WIDTH 16U
+#define LPDDR4__TXSR_F1__REG DENALI_CTL_96
+#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_96__TXSR_F1
+
+#define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_WIDTH 16U
+#define LPDDR4__TXSNR_F1__REG DENALI_CTL_97
+#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_97__TXSNR_F1
+
+#define LPDDR4__DENALI_CTL_97__TXSR_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_97__TXSR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_97__TXSR_F2_WIDTH 16U
+#define LPDDR4__TXSR_F2__REG DENALI_CTL_97
+#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_97__TXSR_F2
+
+#define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_WIDTH 16U
+#define LPDDR4__TXSNR_F2__REG DENALI_CTL_98
+#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_98__TXSNR_F2
+
+#define LPDDR4__DENALI_CTL_98__TXPR_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_98__TXPR_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_98__TXPR_F0_WIDTH 16U
+#define LPDDR4__TXPR_F0__REG DENALI_CTL_98
+#define LPDDR4__TXPR_F0__FLD LPDDR4__DENALI_CTL_98__TXPR_F0
+
+#define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_WIDTH 16U
+#define LPDDR4__TXPR_F1__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F1__FLD LPDDR4__DENALI_CTL_99__TXPR_F1
+
+#define LPDDR4__DENALI_CTL_99__TXPR_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_99__TXPR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_99__TXPR_F2_WIDTH 16U
+#define LPDDR4__TXPR_F2__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F2__FLD LPDDR4__DENALI_CTL_99__TXPR_F2
+
+#define LPDDR4__DENALI_CTL_100_READ_MASK 0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_100_WRITE_MASK 0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_100__TSR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_100__TSR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_100__TSR_F0_WIDTH 8U
+#define LPDDR4__TSR_F0__REG DENALI_CTL_100
+#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_100__TSR_F0
+
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_WIDTH 3U
+#define LPDDR4__TESCKE_F0__REG DENALI_CTL_100
+#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_100__TESCKE_F0
+
+#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_WIDTH 5U
+#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_100
+#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_100__TCSCKEH_F0
+
+#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_WIDTH 5U
+#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_100
+#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_100__TCKELCMD_F0
+
+#define LPDDR4__DENALI_CTL_101_READ_MASK 0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_101_WRITE_MASK 0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_WIDTH 5U
+#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKEHCMD_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_WIDTH 5U
+#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_101__TCKCKEL_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_WIDTH 5U
+#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_101__TCKELPD_F0
+
+#define LPDDR4__DENALI_CTL_101__TSR_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_101__TSR_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_101__TSR_F1_WIDTH 8U
+#define LPDDR4__TSR_F1__REG DENALI_CTL_101
+#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_101__TSR_F1
+
+#define LPDDR4__DENALI_CTL_102_READ_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_102_WRITE_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_WIDTH 3U
+#define LPDDR4__TESCKE_F1__REG DENALI_CTL_102
+#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_102__TESCKE_F1
+
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_WIDTH 5U
+#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_102
+#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_102__TCSCKEH_F1
+
+#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_WIDTH 5U
+#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_102
+#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_102__TCKELCMD_F1
+
+#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_WIDTH 5U
+#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_102
+#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_102__TCKEHCMD_F1
+
+#define LPDDR4__DENALI_CTL_103_READ_MASK 0x07FF1F1FU
+#define LPDDR4__DENALI_CTL_103_WRITE_MASK 0x07FF1F1FU
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_WIDTH 5U
+#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_103__TCKCKEL_F1
+
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_WIDTH 5U
+#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELPD_F1
+
+#define LPDDR4__DENALI_CTL_103__TSR_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_103__TSR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_103__TSR_F2_WIDTH 8U
+#define LPDDR4__TSR_F2__REG DENALI_CTL_103
+#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_103__TSR_F2
+
+#define LPDDR4__DENALI_CTL_103__TESCKE_F2_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_103__TESCKE_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_103__TESCKE_F2_WIDTH 3U
+#define LPDDR4__TESCKE_F2__REG DENALI_CTL_103
+#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_103__TESCKE_F2
+
+#define LPDDR4__DENALI_CTL_104_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_104_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_WIDTH 5U
+#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_104
+#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_104__TCSCKEH_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_WIDTH 5U
+#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKELCMD_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_WIDTH 5U
+#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKEHCMD_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_WIDTH 5U
+#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_104__TCKCKEL_F2
+
+#define LPDDR4__DENALI_CTL_105_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_WIDTH 5U
+#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_105
+#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_105__TCKELPD_F2
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_WIDTH 5U
+#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F0
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_WIDTH 5U
+#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F1
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_WIDTH 5U
+#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F2
+
+#define LPDDR4__DENALI_CTL_106_READ_MASK 0x07010101U
+#define LPDDR4__DENALI_CTL_106_WRITE_MASK 0x07010101U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOSET 0U
+#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_106
+#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WIDTH 1U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOCLR 0U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOSET 0U
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__REG DENALI_CTL_106
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WIDTH 1U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WOCLR 0U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WOSET 0U
+#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_106
+#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH
+
+#define LPDDR4__DENALI_CTL_106__CKE_DELAY_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_106__CKE_DELAY_SHIFT 24U
+#define LPDDR4__DENALI_CTL_106__CKE_DELAY_WIDTH 3U
+#define LPDDR4__CKE_DELAY__REG DENALI_CTL_106
+#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_106__CKE_DELAY
+
+#define LPDDR4__DENALI_CTL_107_READ_MASK 0x00017F00U
+#define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x00017F00U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_WIDTH 5U
+#define LPDDR4__DFS_CMD__REG DENALI_CTL_107
+#define LPDDR4__DFS_CMD__FLD LPDDR4__DENALI_CTL_107__DFS_CMD
+
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_WIDTH 7U
+#define LPDDR4__DFS_STATUS__REG DENALI_CTL_107
+#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_107__DFS_STATUS
+
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WOSET 0U
+#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_107
+#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_107__DFS_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_108_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_108_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_108
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_108
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_109_READ_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_CTL_109_WRITE_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_109
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_SHIFT 16U
+#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_WIDTH 3U
+#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_109
+#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG
+
+#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_SHIFT 24U
+#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_WIDTH 3U
+#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_109
+#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_109__MC_RESERVED3
+
+#define LPDDR4__DENALI_CTL_110_READ_MASK 0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_SHIFT 0U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_WIDTH 3U
+#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED4
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_SHIFT 8U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_WIDTH 8U
+#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED5
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_SHIFT 16U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_WIDTH 8U
+#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED6
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_SHIFT 24U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_WIDTH 8U
+#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED7
+
+#define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_111
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_111
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_113
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_114_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_115_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_116
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_116
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_118_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_119
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0
+
+#define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_120
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_121_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_121
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_122_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_122
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_123_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_123
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_124_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_125_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_WIDTH 20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_125
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0
+
+#define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_126
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1
+
+#define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_127
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_128_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_128
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_129_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_129
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_130_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_130
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_131_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_131
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_132_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_WIDTH 20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_132
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1
+
+#define LPDDR4__DENALI_CTL_133_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_133
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2
+
+#define LPDDR4__DENALI_CTL_134_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_134
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_135_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_135
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_136_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_136
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_137_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_137
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_138_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_138
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_139_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_WIDTH 20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_139
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2
+
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_SHIFT 24U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WIDTH 1U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOCLR 0U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOSET 0U
+#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_139
+#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF
+
+#define LPDDR4__DENALI_CTL_140_READ_MASK 0x00010103U
+#define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x00010103U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
+
+#define LPDDR4__DENALI_CTL_141_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_141
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_142_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_142
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_143_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_143
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_144_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_144
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_145_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_145
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_146_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_146
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_147_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_147
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_148_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_148
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_149
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_SHIFT 24U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WIDTH 1U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOCLR 0U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOSET 0U
+#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_149
+#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_149__PPR_CONTROL
+
+#define LPDDR4__DENALI_CTL_150_READ_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_150_WRITE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_SHIFT 0U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_WIDTH 3U
+#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND
+
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_SHIFT 8U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_WIDTH 8U
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM
+
+#define LPDDR4__DENALI_CTL_151_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_SHIFT 0U
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_WIDTH 17U
+#define LPDDR4__PPR_COMMAND_MRW_DATA__REG DENALI_CTL_151
+#define LPDDR4__PPR_COMMAND_MRW_DATA__FLD LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA
+
+#define LPDDR4__DENALI_CTL_152_READ_MASK 0x0F01FFFFU
+#define LPDDR4__DENALI_CTL_152_WRITE_MASK 0x0F01FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_WIDTH 17U
+#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS
+
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_WIDTH 4U
+#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS
+
+#define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOSET 0U
+#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_153
+#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS
+
+#define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_WIDTH 32U
+#define LPDDR4__PPR_DATA_0__REG DENALI_CTL_154
+#define LPDDR4__PPR_DATA_0__FLD LPDDR4__DENALI_CTL_154__PPR_DATA_0
+
+#define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_WIDTH 32U
+#define LPDDR4__PPR_DATA_1__REG DENALI_CTL_155
+#define LPDDR4__PPR_DATA_1__FLD LPDDR4__DENALI_CTL_155__PPR_DATA_1
+
+#define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFF0103U
+#define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFF0103U
+#define LPDDR4__DENALI_CTL_156__PPR_STATUS_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_156__PPR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_156__PPR_STATUS_WIDTH 2U
+#define LPDDR4__PPR_STATUS__REG DENALI_CTL_156
+#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_156__PPR_STATUS
+
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_SHIFT 8U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WIDTH 1U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WOCLR 0U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WOSET 0U
+#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_156
+#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL
+
+#define LPDDR4__DENALI_CTL_156__CKSRE_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_156__CKSRE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_156__CKSRE_F0_WIDTH 8U
+#define LPDDR4__CKSRE_F0__REG DENALI_CTL_156
+#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_156__CKSRE_F0
+
+#define LPDDR4__DENALI_CTL_156__CKSRX_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_156__CKSRX_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_156__CKSRX_F0_WIDTH 8U
+#define LPDDR4__CKSRX_F0__REG DENALI_CTL_156
+#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_156__CKSRX_F0
+
+#define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__CKSRE_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_157__CKSRE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_157__CKSRE_F1_WIDTH 8U
+#define LPDDR4__CKSRE_F1__REG DENALI_CTL_157
+#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_157__CKSRE_F1
+
+#define LPDDR4__DENALI_CTL_157__CKSRX_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F1_WIDTH 8U
+#define LPDDR4__CKSRX_F1__REG DENALI_CTL_157
+#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_157__CKSRX_F1
+
+#define LPDDR4__DENALI_CTL_157__CKSRE_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_157__CKSRE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_157__CKSRE_F2_WIDTH 8U
+#define LPDDR4__CKSRE_F2__REG DENALI_CTL_157
+#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_157__CKSRE_F2
+
+#define LPDDR4__DENALI_CTL_157__CKSRX_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F2_WIDTH 8U
+#define LPDDR4__CKSRX_F2__REG DENALI_CTL_157
+#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_157__CKSRX_F2
+
+#define LPDDR4__DENALI_CTL_158_READ_MASK 0x0F0F0003U
+#define LPDDR4__DENALI_CTL_158_WRITE_MASK 0x0F0F0003U
+#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_WIDTH 2U
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_158
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE
+
+#define LPDDR4__DENALI_CTL_158__LP_CMD_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_158__LP_CMD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_158__LP_CMD_WIDTH 7U
+#define LPDDR4__LP_CMD__REG DENALI_CTL_158
+#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_158__LP_CMD
+
+#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__REG DENALI_CTL_158
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_158
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_159_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__REG DENALI_CTL_160
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165_READ_MASK 0x00013F0FU
+#define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x00013F0FU
+#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_WIDTH 6U
+#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_165
+#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN
+
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WOSET 0U
+#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_165
+#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN
+
+#define LPDDR4__DENALI_CTL_166_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_166_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_WIDTH 12U
+#define LPDDR4__LPI_TIMER_COUNT__REG DENALI_CTL_166
+#define LPDDR4__LPI_TIMER_COUNT__FLD LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT
+
+#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_WIDTH 12U
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_166
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_167_READ_MASK 0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_SHIFT 0U
+#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_WIDTH 3U
+#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_167
+#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_167__TDFI_LP_RESP
+
+#define LPDDR4__DENALI_CTL_167__LP_STATE_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_167__LP_STATE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_167__LP_STATE_WIDTH 7U
+#define LPDDR4__LP_STATE__REG DENALI_CTL_167
+#define LPDDR4__LP_STATE__FLD LPDDR4__DENALI_CTL_167__LP_STATE
+
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_WIDTH 4U
+#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_167
+#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN
+
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_WIDTH 4U
+#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_167
+#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN
+
+#define LPDDR4__DENALI_CTL_168_READ_MASK 0x000FFF07U
+#define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x000FFF07U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_WIDTH 3U
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_168
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN
+
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_WIDTH 12U
+#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_168
+#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE
+
+#define LPDDR4__DENALI_CTL_169_READ_MASK 0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_169_WRITE_MASK 0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_WIDTH 8U
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE
+
+#define LPDDR4__DENALI_CTL_170_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_170_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_170
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_170
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_171
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_171
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_172
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_173_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_173_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WOSET 0U
+#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN
+
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WOSET 0U
+#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN
+
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WOSET 0U
+#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN
+
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WOSET 0U
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN
+
+#define LPDDR4__DENALI_CTL_174_READ_MASK 0x0101FF01U
+#define LPDDR4__DENALI_CTL_174_WRITE_MASK 0x0101FF01U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WOSET 0U
+#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_174
+#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_WIDTH 9U
+#define LPDDR4__PWRDN_SHIFT_DELAY__REG DENALI_CTL_174
+#define LPDDR4__PWRDN_SHIFT_DELAY__FLD LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY
+
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WOSET 0U
+#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_174
+#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_174__DFS_ENABLE
+
+#define LPDDR4__DENALI_CTL_175_READ_MASK 0x00000107U
+#define LPDDR4__DENALI_CTL_175_WRITE_MASK 0x00000107U
+#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_SHIFT 0U
+#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_WIDTH 3U
+#define LPDDR4__DFS_DLL_OFF__REG DENALI_CTL_175
+#define LPDDR4__DFS_DLL_OFF__FLD LPDDR4__DENALI_CTL_175__DFS_DLL_OFF
+
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WOSET 0U
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_175
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN
+
+#define LPDDR4__DENALI_CTL_176_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_176
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR
+
+#define LPDDR4__DENALI_CTL_177_READ_MASK 0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_177_WRITE_MASK 0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_WIDTH 4U
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_177
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK
+
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_177
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT
+
+#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_SHIFT 24U
+#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_WIDTH 2U
+#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_177
+#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY
+
+#define LPDDR4__DENALI_CTL_178_READ_MASK 0x00000303U
+#define LPDDR4__DENALI_CTL_178_WRITE_MASK 0x00000303U
+#define LPDDR4__DENALI_CTL_178__INIT_FREQ_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_178__INIT_FREQ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_178__INIT_FREQ_WIDTH 2U
+#define LPDDR4__INIT_FREQ__REG DENALI_CTL_178
+#define LPDDR4__INIT_FREQ__FLD LPDDR4__DENALI_CTL_178__INIT_FREQ
+
+#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_WIDTH 2U
+#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_178
+#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ
+
+#define LPDDR4__DENALI_CTL_179_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_179
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0
+
+#define LPDDR4__DENALI_CTL_180_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_180
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1
+
+#define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_181
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2
+
+#define LPDDR4__DENALI_CTL_182_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_182_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_WIDTH 24U
+#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_182
+#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_CTL_183_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_183_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_WIDTH 24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_183
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_CTL_184_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_WIDTH 24U
+#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_184
+#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_CTL_185_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_WIDTH 24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_185
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_CTL_186_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_WIDTH 24U
+#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_186
+#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_CTL_187_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_WIDTH 24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_187
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_CTL_188_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_188_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_WIDTH 27U
+#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_188
+#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_188__WRITE_MODEREG
+
+#define LPDDR4__DENALI_CTL_189_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_189_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_189__MRW_STATUS_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_189__MRW_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_189__MRW_STATUS_WIDTH 8U
+#define LPDDR4__MRW_STATUS__REG DENALI_CTL_189
+#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_189__MRW_STATUS
+
+#define LPDDR4__DENALI_CTL_189__READ_MODEREG_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_189__READ_MODEREG_SHIFT 8U
+#define LPDDR4__DENALI_CTL_189__READ_MODEREG_WIDTH 17U
+#define LPDDR4__READ_MODEREG__REG DENALI_CTL_189
+#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_189__READ_MODEREG
+
+#define LPDDR4__DENALI_CTL_190_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_190_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_SHIFT 0U
+#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_WIDTH 24U
+#define LPDDR4__PERIPHERAL_MRR_DATA__REG DENALI_CTL_190
+#define LPDDR4__PERIPHERAL_MRR_DATA__FLD LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA
+
+#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_WIDTH 8U
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_190
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0
+
+#define LPDDR4__DENALI_CTL_191_READ_MASK 0x000301FFU
+#define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x000301FFU
+#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_WIDTH 8U
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_191
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1
+
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_SHIFT 8U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WIDTH 1U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WOCLR 0U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WOSET 0U
+#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_191
+#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG
+
+#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_SHIFT 16U
+#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_WIDTH 2U
+#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_191
+#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC
+
+#define LPDDR4__DENALI_CTL_192_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_192_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_WIDTH 10U
+#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_192
+#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0
+
+#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_WIDTH 10U
+#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_192
+#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0
+
+#define LPDDR4__DENALI_CTL_193_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_193__TFC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_193__TFC_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_193__TFC_F0_WIDTH 10U
+#define LPDDR4__TFC_F0__REG DENALI_CTL_193
+#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_193__TFC_F0
+
+#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_WIDTH 5U
+#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_193
+#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_193__TCKFSPE_F0
+
+#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_WIDTH 5U
+#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_193
+#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_193__TCKFSPX_F0
+
+#define LPDDR4__DENALI_CTL_194_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_WIDTH 20U
+#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_194
+#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_194__TVREF_LONG_F0
+
+#define LPDDR4__DENALI_CTL_195_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_WIDTH 10U
+#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1
+
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_WIDTH 10U
+#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1
+
+#define LPDDR4__DENALI_CTL_196_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_196__TFC_F1_WIDTH 10U
+#define LPDDR4__TFC_F1__REG DENALI_CTL_196
+#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_196__TFC_F1
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_WIDTH 5U
+#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_196__TCKFSPE_F1
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_WIDTH 5U
+#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_196__TCKFSPX_F1
+
+#define LPDDR4__DENALI_CTL_197_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_WIDTH 20U
+#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_197
+#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_197__TVREF_LONG_F1
+
+#define LPDDR4__DENALI_CTL_198_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_WIDTH 10U
+#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2
+
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_WIDTH 10U
+#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2
+
+#define LPDDR4__DENALI_CTL_199_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_199__TFC_F2_WIDTH 10U
+#define LPDDR4__TFC_F2__REG DENALI_CTL_199
+#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_199__TFC_F2
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_WIDTH 5U
+#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_199__TCKFSPE_F2
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_WIDTH 5U
+#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_199__TCKFSPX_F2
+
+#define LPDDR4__DENALI_CTL_200_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_WIDTH 20U
+#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_200
+#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_200__TVREF_LONG_F2
+
+#define LPDDR4__DENALI_CTL_201_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_201
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_201
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_202_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_202
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_202
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_203_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_203
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_203
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_204_READ_MASK 0x01FFFF01U
+#define LPDDR4__DENALI_CTL_204_WRITE_MASK 0x01FFFF01U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_SHIFT 0U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WIDTH 1U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WOCLR 0U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WOSET 0U
+#define LPDDR4__MR4_DLL_RST__REG DENALI_CTL_204
+#define LPDDR4__MR4_DLL_RST__FLD LPDDR4__DENALI_CTL_204__MR4_DLL_RST
+
+#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR0_DATA_F0_0__REG DENALI_CTL_204
+#define LPDDR4__MR0_DATA_F0_0__FLD LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_205_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_205_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_205
+#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_206_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_206_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_206
+#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_207_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR0_DATA_F1_0__REG DENALI_CTL_207
+#define LPDDR4__MR0_DATA_F1_0__FLD LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_208_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_208
+#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_209_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_209
+#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_210_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR0_DATA_F2_0__REG DENALI_CTL_210
+#define LPDDR4__MR0_DATA_F2_0__FLD LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_211_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_211
+#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_212_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_212
+#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_213_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR0_DATA_F0_1__REG DENALI_CTL_213
+#define LPDDR4__MR0_DATA_F0_1__FLD LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_214_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_214
+#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_215_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_215
+#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_216_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR0_DATA_F1_1__REG DENALI_CTL_216
+#define LPDDR4__MR0_DATA_F1_1__FLD LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_217_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_217
+#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_218_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_218
+#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_219_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR0_DATA_F2_1__REG DENALI_CTL_219
+#define LPDDR4__MR0_DATA_F2_1__FLD LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_220_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_220
+#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_221_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_221
+#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_222_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_WIDTH 17U
+#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_222
+#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_CTL_223_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_WIDTH 17U
+#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_223
+#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_CTL_224_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_224
+#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_225_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_225
+#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_226_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_226
+#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_227_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_227
+#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_228_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_228
+#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_229_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_229
+#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_230_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_230
+#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_231_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_231
+#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_232_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_232
+#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_233_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_233
+#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_234_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_234
+#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_235_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_235
+#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_236_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR5_DATA_F0_0__REG DENALI_CTL_236
+#define LPDDR4__MR5_DATA_F0_0__FLD LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_237_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR5_DATA_F1_0__REG DENALI_CTL_237
+#define LPDDR4__MR5_DATA_F1_0__FLD LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_238_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR5_DATA_F2_0__REG DENALI_CTL_238
+#define LPDDR4__MR5_DATA_F2_0__FLD LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_239_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR5_DATA_F0_1__REG DENALI_CTL_239
+#define LPDDR4__MR5_DATA_F0_1__FLD LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_240_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR5_DATA_F1_1__REG DENALI_CTL_240
+#define LPDDR4__MR5_DATA_F1_1__FLD LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_241_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR5_DATA_F2_1__REG DENALI_CTL_241
+#define LPDDR4__MR5_DATA_F2_1__FLD LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_242_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR6_DATA_F0_0__REG DENALI_CTL_242
+#define LPDDR4__MR6_DATA_F0_0__FLD LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_243_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR6_DATA_F1_0__REG DENALI_CTL_243
+#define LPDDR4__MR6_DATA_F1_0__FLD LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_244_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR6_DATA_F2_0__REG DENALI_CTL_244
+#define LPDDR4__MR6_DATA_F2_0__FLD LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_245_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR6_DATA_F0_1__REG DENALI_CTL_245
+#define LPDDR4__MR6_DATA_F0_1__FLD LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_246_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR6_DATA_F1_1__REG DENALI_CTL_246
+#define LPDDR4__MR6_DATA_F1_1__FLD LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_247_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_247_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR6_DATA_F2_1__REG DENALI_CTL_247
+#define LPDDR4__MR6_DATA_F2_1__FLD LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_WIDTH 8U
+#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_247
+#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_247__MR8_DATA_0
+
+#define LPDDR4__DENALI_CTL_248_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_248_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_WIDTH 8U
+#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_248
+#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_248__MR8_DATA_1
+
+#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR10_DATA_F0_0__REG DENALI_CTL_248
+#define LPDDR4__MR10_DATA_F0_0__FLD LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_249_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR10_DATA_F1_0__REG DENALI_CTL_249
+#define LPDDR4__MR10_DATA_F1_0__FLD LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_250_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR10_DATA_F2_0__REG DENALI_CTL_250
+#define LPDDR4__MR10_DATA_F2_0__FLD LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_251_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_251_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR10_DATA_F0_1__REG DENALI_CTL_251
+#define LPDDR4__MR10_DATA_F0_1__FLD LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_252_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR10_DATA_F1_1__REG DENALI_CTL_252
+#define LPDDR4__MR10_DATA_F1_1__FLD LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_253_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_253_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR10_DATA_F2_1__REG DENALI_CTL_253
+#define LPDDR4__MR10_DATA_F2_1__FLD LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_253
+#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_254_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_255_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_255
+#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_255
+#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_256_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_256
+#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_257_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_257_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_257
+#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_258_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_258
+#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_259_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_259
+#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_260_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_260
+#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_261_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_WIDTH 17U
+#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_261
+#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_261__MR13_DATA_0
+
+#define LPDDR4__DENALI_CTL_262_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_WIDTH 17U
+#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_262
+#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_262__MR13_DATA_1
+
+#define LPDDR4__DENALI_CTL_263_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_263
+#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_264_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_264
+#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_265_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_265
+#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_266_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_266
+#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_267_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_267
+#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_268_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_268_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_268
+#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_WIDTH 8U
+#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_268
+#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_268__MR16_DATA_0
+
+#define LPDDR4__DENALI_CTL_269_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_269_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_WIDTH 8U
+#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_269
+#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_269__MR16_DATA_1
+
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_WIDTH 8U
+#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_269
+#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_269__MR17_DATA_0
+
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_WIDTH 8U
+#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_269
+#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_269__MR17_DATA_1
+
+#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_WIDTH 8U
+#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_269
+#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_269__MR20_DATA_0
+
+#define LPDDR4__DENALI_CTL_270_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_WIDTH 8U
+#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_270
+#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_270__MR20_DATA_1
+
+#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_WIDTH 17U
+#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_270
+#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_271_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_WIDTH 17U
+#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_271
+#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_272_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_272_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_WIDTH 17U
+#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_272
+#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_273_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_WIDTH 17U
+#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_273
+#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_274_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_WIDTH 17U
+#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_274
+#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_275_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_WIDTH 17U
+#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_275
+#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_276_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_276__MR23_DATA_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_276__MR23_DATA_SHIFT 0U
+#define LPDDR4__DENALI_CTL_276__MR23_DATA_WIDTH 17U
+#define LPDDR4__MR23_DATA__REG DENALI_CTL_276
+#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_276__MR23_DATA
+
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WOSET 0U
+#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_276
+#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0
+
+#define LPDDR4__DENALI_CTL_277_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WOSET 0U
+#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_277
+#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1
+
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WOSET 0U
+#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_277
+#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2
+
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WOSET 0U
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__REG DENALI_CTL_277
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__FLD LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE
+
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WOSET 0U
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__REG DENALI_CTL_277
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__FLD LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE
+
+#define LPDDR4__DENALI_CTL_278_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_SHIFT 0U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WIDTH 1U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WOCLR 0U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WOSET 0U
+#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_278
+#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW
+
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WOSET 0U
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_278
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP
+
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WOSET 0U
+#define LPDDR4__FSP_STATUS__REG DENALI_CTL_278
+#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_278__FSP_STATUS
+
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WOSET 0U
+#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_278
+#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT
+
+#define LPDDR4__DENALI_CTL_279_READ_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WOSET 0U
+#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_279
+#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT
+
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_SHIFT 8U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WIDTH 1U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WOCLR 0U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WOSET 0U
+#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_279
+#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_SHIFT 16U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WIDTH 1U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WOCLR 0U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WOSET 0U
+#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_279
+#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_SHIFT 24U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_WIDTH 2U
+#define LPDDR4__FSP0_FRC__REG DENALI_CTL_279
+#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_279__FSP0_FRC
+
+#define LPDDR4__DENALI_CTL_280_READ_MASK 0x3F030003U
+#define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x3F030003U
+#define LPDDR4__DENALI_CTL_280__FSP1_FRC_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_280__FSP1_FRC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_280__FSP1_FRC_WIDTH 2U
+#define LPDDR4__FSP1_FRC__REG DENALI_CTL_280
+#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_280__FSP1_FRC
+
+#define LPDDR4__DENALI_CTL_280__BIST_GO_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_SHIFT 8U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_WIDTH 1U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_WOCLR 0U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_WOSET 0U
+#define LPDDR4__BIST_GO__REG DENALI_CTL_280
+#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_280__BIST_GO
+
+#define LPDDR4__DENALI_CTL_280__BIST_RESULT_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_280__BIST_RESULT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_280__BIST_RESULT_WIDTH 2U
+#define LPDDR4__BIST_RESULT__REG DENALI_CTL_280
+#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_280__BIST_RESULT
+
+#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_WIDTH 6U
+#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_280
+#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_280__ADDR_SPACE
+
+#define LPDDR4__DENALI_CTL_281_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WOSET 0U
+#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_281
+#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_SHIFT 8U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WOSET 0U
+#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_281
+#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_CTL_282_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_282_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_WIDTH 32U
+#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_282
+#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_283_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WOSET 0U
+#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_283
+#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_284_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_284_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_WIDTH 32U
+#define LPDDR4__BIST_DATA_MASK__REG DENALI_CTL_284
+#define LPDDR4__BIST_DATA_MASK__FLD LPDDR4__DENALI_CTL_284__BIST_DATA_MASK
+
+#define LPDDR4__DENALI_CTL_285_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_285_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_WIDTH 3U
+#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_285
+#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_285__BIST_TEST_MODE
+
+#define LPDDR4__DENALI_CTL_286_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_286_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_286
+#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0
+
+#define LPDDR4__DENALI_CTL_287_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_287
+#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1
+
+#define LPDDR4__DENALI_CTL_288_READ_MASK 0x000FFF01U
+#define LPDDR4__DENALI_CTL_288_WRITE_MASK 0x000FFF01U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WOSET 0U
+#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_288
+#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_288__BIST_RET_STATE
+
+#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_WIDTH 12U
+#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_288
+#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_288__BIST_ERR_STOP
+
+#define LPDDR4__DENALI_CTL_289_READ_MASK 0x1F000FFFU
+#define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x1F000FFFU
+#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_WIDTH 12U
+#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_289
+#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WOSET 0U
+#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_289
+#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT
+
+#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_SHIFT 24U
+#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_WIDTH 5U
+#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_289
+#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_CTL_290_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_290_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_290
+#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_290
+#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_WIDTH 5U
+#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_290
+#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT
+
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_WIDTH 5U
+#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_290
+#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT
+
+#define LPDDR4__DENALI_CTL_291_READ_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_291_WRITE_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_SHIFT 0U
+#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_WIDTH 4U
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_291
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI
+
+#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_WIDTH 3U
+#define LPDDR4__ZQCS_OPT_THRESHOLD__REG DENALI_CTL_291
+#define LPDDR4__ZQCS_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_291
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_292_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_292
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_292
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_293
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_293
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_294_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_294_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_294
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_294
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_295_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_295_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_295
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_295
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_296_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_296_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_296
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_296
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_297
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_297
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_298_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_300_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_300
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_300
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_301_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_301
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_301
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_304
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_304
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_305_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_305_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_WIDTH 8U
+#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_305
+#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG
+
+#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_WIDTH 12U
+#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_305
+#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_305__ZQINIT_F0
+
+#define LPDDR4__DENALI_CTL_306_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_306_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_306__ZQCL_F0_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_306__ZQCL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_306__ZQCL_F0_WIDTH 12U
+#define LPDDR4__ZQCL_F0__REG DENALI_CTL_306
+#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_306__ZQCL_F0
+
+#define LPDDR4__DENALI_CTL_306__ZQCS_F0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_306__ZQCS_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_306__ZQCS_F0_WIDTH 12U
+#define LPDDR4__ZQCS_F0__REG DENALI_CTL_306
+#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_306__ZQCS_F0
+
+#define LPDDR4__DENALI_CTL_307_READ_MASK 0x007F0FFFU
+#define LPDDR4__DENALI_CTL_307_WRITE_MASK 0x007F0FFFU
+#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_WIDTH 12U
+#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_307
+#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_307__TZQCAL_F0
+
+#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_WIDTH 7U
+#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_307
+#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_307__TZQLAT_F0
+
+#define LPDDR4__DENALI_CTL_308_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_308_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_WIDTH 12U
+#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_308
+#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_308__ZQINIT_F1
+
+#define LPDDR4__DENALI_CTL_308__ZQCL_F1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_308__ZQCL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_308__ZQCL_F1_WIDTH 12U
+#define LPDDR4__ZQCL_F1__REG DENALI_CTL_308
+#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_308__ZQCL_F1
+
+#define LPDDR4__DENALI_CTL_309_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_309_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_309__ZQCS_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_309__ZQCS_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_309__ZQCS_F1_WIDTH 12U
+#define LPDDR4__ZQCS_F1__REG DENALI_CTL_309
+#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_309__ZQCS_F1
+
+#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_WIDTH 12U
+#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_309
+#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_309__TZQCAL_F1
+
+#define LPDDR4__DENALI_CTL_310_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_CTL_310_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_WIDTH 7U
+#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_310
+#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_310__TZQLAT_F1
+
+#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_WIDTH 12U
+#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_310
+#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_310__ZQINIT_F2
+
+#define LPDDR4__DENALI_CTL_311_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_311__ZQCL_F2_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_311__ZQCL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_311__ZQCL_F2_WIDTH 12U
+#define LPDDR4__ZQCL_F2__REG DENALI_CTL_311
+#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_311__ZQCL_F2
+
+#define LPDDR4__DENALI_CTL_311__ZQCS_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_311__ZQCS_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_311__ZQCS_F2_WIDTH 12U
+#define LPDDR4__ZQCS_F2__REG DENALI_CTL_311
+#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_311__ZQCS_F2
+
+#define LPDDR4__DENALI_CTL_312_READ_MASK 0x037F0FFFU
+#define LPDDR4__DENALI_CTL_312_WRITE_MASK 0x037F0FFFU
+#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_WIDTH 12U
+#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_312
+#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_312__TZQCAL_F2
+
+#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_WIDTH 7U
+#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_312
+#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_312__TZQLAT_F2
+
+#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 24U
+#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_312
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP
+
+#define LPDDR4__DENALI_CTL_313_READ_MASK 0x0FFF0100U
+#define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x0FFF0100U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_WIDTH 4U
+#define LPDDR4__ZQ_REQ__REG DENALI_CTL_313
+#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_313__ZQ_REQ
+
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_SHIFT 8U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WIDTH 1U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WOCLR 0U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WOSET 0U
+#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_313
+#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_WIDTH 12U
+#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_313
+#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_313__ZQRESET_F0
+
+#define LPDDR4__DENALI_CTL_314_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_WIDTH 12U
+#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_314
+#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_314__ZQRESET_F1
+
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_WIDTH 12U
+#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_314
+#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_314__ZQRESET_F2
+
+#define LPDDR4__DENALI_CTL_315_READ_MASK 0x03030101U
+#define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x03030101U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WOSET 0U
+#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_315
+#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_315__NO_ZQ_INIT
+
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WOSET 0U
+#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_315
+#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_315__ZQCS_ROTATE
+
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_WIDTH 2U
+#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_315
+#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_WIDTH 2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_315
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_CTL_316_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_WIDTH 2U
+#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_316
+#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_WIDTH 2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_316
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_WIDTH 2U
+#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_316
+#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_316__BANK_DIFF_0
+
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_WIDTH 2U
+#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_316
+#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_316__BANK_DIFF_1
+
+#define LPDDR4__DENALI_CTL_317_READ_MASK 0x0F0F0707U
+#define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x0F0F0707U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_WIDTH 3U
+#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_317
+#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_317__ROW_DIFF_0
+
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_WIDTH 3U
+#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_317
+#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_317__ROW_DIFF_1
+
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_WIDTH 4U
+#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_317
+#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_317__COL_DIFF_0
+
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_WIDTH 4U
+#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_317
+#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_317__COL_DIFF_1
+
+#define LPDDR4__DENALI_CTL_318_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_318_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_WIDTH 16U
+#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_318
+#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0
+
+#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_WIDTH 16U
+#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_318
+#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0
+
+#define LPDDR4__DENALI_CTL_319_READ_MASK 0x00FFFF03U
+#define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x00FFFF03U
+#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_WIDTH 2U
+#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_319
+#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_319__ROW_START_VAL_0
+
+#define LPDDR4__DENALI_CTL_319__CS_MSK_0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_319__CS_MSK_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_319__CS_MSK_0_WIDTH 16U
+#define LPDDR4__CS_MSK_0__REG DENALI_CTL_319
+#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_319__CS_MSK_0
+
+#define LPDDR4__DENALI_CTL_320_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_320_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_WIDTH 16U
+#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_320
+#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1
+
+#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_WIDTH 16U
+#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_320
+#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1
+
+#define LPDDR4__DENALI_CTL_321_READ_MASK 0x03FFFF03U
+#define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x03FFFF03U
+#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_WIDTH 2U
+#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_321
+#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_321__ROW_START_VAL_1
+
+#define LPDDR4__DENALI_CTL_321__CS_MSK_1_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_321__CS_MSK_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_321__CS_MSK_1_WIDTH 16U
+#define LPDDR4__CS_MSK_1__REG DENALI_CTL_321
+#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_321__CS_MSK_1
+
+#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_WIDTH 2U
+#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_321
+#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2
+
+#define LPDDR4__DENALI_CTL_322_READ_MASK 0x1F011F01U
+#define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x1F011F01U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WOSET 0U
+#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_322
+#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN
+
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_SHIFT 8U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_WIDTH 5U
+#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_322
+#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_322__MC_RESERVED8
+
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_SHIFT 16U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WIDTH 1U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WOCLR 0U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WOSET 0U
+#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_322
+#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_322__MC_RESERVED9
+
+#define LPDDR4__DENALI_CTL_322__APREBIT_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_322__APREBIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_322__APREBIT_WIDTH 5U
+#define LPDDR4__APREBIT__REG DENALI_CTL_322
+#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_322__APREBIT
+
+#define LPDDR4__DENALI_CTL_323_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_323__AGE_COUNT_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_323__AGE_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_323__AGE_COUNT_WIDTH 8U
+#define LPDDR4__AGE_COUNT__REG DENALI_CTL_323
+#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_323__AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_WIDTH 8U
+#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_323
+#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WOSET 0U
+#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_323
+#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_323__ADDR_CMP_EN
+
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WOSET 0U
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_323
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS
+
+#define LPDDR4__DENALI_CTL_324_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_324_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WOSET 0U
+#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_324
+#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WOSET 0U
+#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_324
+#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_324__PLACEMENT_EN
+
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WOSET 0U
+#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_324
+#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_324__PRIORITY_EN
+
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WOSET 0U
+#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_324
+#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_324__RW_SAME_EN
+
+#define LPDDR4__DENALI_CTL_325_READ_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WOSET 0U
+#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_325
+#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN
+
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WOSET 0U
+#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_325
+#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_325__CS_SAME_EN
+
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WOSET 0U
+#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_325
+#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_325
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT
+
+#define LPDDR4__DENALI_CTL_326_READ_MASK 0x0301011FU
+#define LPDDR4__DENALI_CTL_326_WRITE_MASK 0x0301011FU
+#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_326
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE
+
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_WOSET 0U
+#define LPDDR4__SWAP_EN__REG DENALI_CTL_326
+#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_326__SWAP_EN
+
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WOSET 0U
+#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_326
+#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE
+
+#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_WIDTH 2U
+#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_326
+#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD
+
+#define LPDDR4__DENALI_CTL_327_READ_MASK 0x07010F03U
+#define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x07010F03U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_SHIFT 0U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_WIDTH 2U
+#define LPDDR4__CS_MAP__REG DENALI_CTL_327
+#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_327__CS_MAP
+
+#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_WIDTH 4U
+#define LPDDR4__BURST_ON_FLY_BIT__REG DENALI_CTL_327
+#define LPDDR4__BURST_ON_FLY_BIT__FLD LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT
+
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_SHIFT 16U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WIDTH 1U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WOCLR 0U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WOSET 0U
+#define LPDDR4__MEM_DP_REDUCTION__REG DENALI_CTL_327
+#define LPDDR4__MEM_DP_REDUCTION__FLD LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION
+
+#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_WIDTH 3U
+#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_327
+#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_CTL_328_READ_MASK 0x03030307U
+#define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x03030307U
+#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_WIDTH 3U
+#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_328
+#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_WIDTH 2U
+#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_328
+#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_WIDTH 2U
+#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_328
+#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_WIDTH 2U
+#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_328
+#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_329_READ_MASK 0x03011F03U
+#define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x03011F03U
+#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_WIDTH 2U
+#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_329
+#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_WIDTH 5U
+#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_329
+#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_329__Q_FULLNESS
+
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WOSET 0U
+#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_329
+#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT
+
+#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_WIDTH 2U
+#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_329
+#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_329__WR_ORDER_REQ
+
+#define LPDDR4__DENALI_CTL_330_READ_MASK 0x01010001U
+#define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x01010001U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WOSET 0U
+#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_330
+#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY
+
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WOSET 0U
+#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_330
+#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_REQ
+
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_330
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WOSET 0U
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_330
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE
+
+#define LPDDR4__DENALI_CTL_331_READ_MASK 0x01030303U
+#define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x01030303U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_WIDTH 2U
+#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_331
+#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_WIDTH 2U
+#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_331
+#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_WIDTH 2U
+#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_331
+#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WOSET 0U
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_331
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_CTL_332_READ_MASK 0x00070101U
+#define LPDDR4__DENALI_CTL_332_WRITE_MASK 0x00070101U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WOSET 0U
+#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_332
+#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_332__WR_DBI_EN
+
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WOSET 0U
+#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_332
+#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_332__RD_DBI_EN
+
+#define LPDDR4__DENALI_CTL_332__DFI_ERROR_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_332__DFI_ERROR_SHIFT 16U
+#define LPDDR4__DENALI_CTL_332__DFI_ERROR_WIDTH 3U
+#define LPDDR4__DFI_ERROR__REG DENALI_CTL_332
+#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_332__DFI_ERROR
+
+#define LPDDR4__DENALI_CTL_333_READ_MASK 0x00010FFFU
+#define LPDDR4__DENALI_CTL_333_WRITE_MASK 0x00010FFFU
+#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_SHIFT 0U
+#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_WIDTH 12U
+#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_333
+#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO
+
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WOSET 0U
+#define LPDDR4__BG_ROTATE_EN__REG DENALI_CTL_333
+#define LPDDR4__BG_ROTATE_EN__FLD LPDDR4__DENALI_CTL_333__BG_ROTATE_EN
+
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_SHIFT 24U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WIDTH 1U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WOCLR 0U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WOSET 0U
+#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_333
+#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_333__MC_RESERVED10
+
+#define LPDDR4__DENALI_CTL_334_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_SHIFT 0U
+#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_WIDTH 32U
+#define LPDDR4__INT_STATUS_MASTER__REG DENALI_CTL_334
+#define LPDDR4__INT_STATUS_MASTER__FLD LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER
+
+#define LPDDR4__DENALI_CTL_335_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_SHIFT 0U
+#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_WIDTH 32U
+#define LPDDR4__INT_MASK_MASTER__REG DENALI_CTL_335
+#define LPDDR4__INT_MASK_MASTER__FLD LPDDR4__DENALI_CTL_335__INT_MASK_MASTER
+
+#define LPDDR4__DENALI_CTL_336_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_WIDTH 32U
+#define LPDDR4__INT_STATUS_TIMEOUT__REG DENALI_CTL_336
+#define LPDDR4__INT_STATUS_TIMEOUT__FLD LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_337_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_SHIFT 0U
+#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_WIDTH 16U
+#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_337
+#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_337__MC_RESERVED11
+
+#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_SHIFT 16U
+#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_WIDTH 16U
+#define LPDDR4__INT_STATUS_LOWPOWER__REG DENALI_CTL_337
+#define LPDDR4__INT_STATUS_LOWPOWER__FLD LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_338_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_SHIFT 0U
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_WIDTH 16U
+#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_338
+#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_338__MC_RESERVED12
+
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_SHIFT 16U
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_WIDTH 16U
+#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_338
+#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_338__MC_RESERVED13
+
+#define LPDDR4__DENALI_CTL_339_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_339_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_SHIFT 0U
+#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_WIDTH 32U
+#define LPDDR4__INT_STATUS_TRAINING__REG DENALI_CTL_339
+#define LPDDR4__INT_STATUS_TRAINING__FLD LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING
+
+#define LPDDR4__DENALI_CTL_340_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_340_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_SHIFT 0U
+#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_WIDTH 32U
+#define LPDDR4__INT_STATUS_USERIF__REG DENALI_CTL_340
+#define LPDDR4__INT_STATUS_USERIF__FLD LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF
+
+#define LPDDR4__DENALI_CTL_341_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_341_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_WIDTH 16U
+#define LPDDR4__INT_STATUS_MISC__REG DENALI_CTL_341
+#define LPDDR4__INT_STATUS_MISC__FLD LPDDR4__DENALI_CTL_341__INT_STATUS_MISC
+
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_SHIFT 16U
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_WIDTH 8U
+#define LPDDR4__INT_STATUS_BIST__REG DENALI_CTL_341
+#define LPDDR4__INT_STATUS_BIST__FLD LPDDR4__DENALI_CTL_341__INT_STATUS_BIST
+
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_SHIFT 24U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_WIDTH 8U
+#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_341
+#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_341__MC_RESERVED14
+
+#define LPDDR4__DENALI_CTL_342_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_SHIFT 0U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_WIDTH 8U
+#define LPDDR4__INT_STATUS_DFI__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_DFI__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_DFI
+
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_SHIFT 8U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_WIDTH 8U
+#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_342
+#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED15
+
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_WIDTH 8U
+#define LPDDR4__INT_STATUS_FREQ__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_FREQ__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ
+
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_WIDTH 8U
+#define LPDDR4__INT_STATUS_INIT__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_INIT__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_INIT
+
+#define LPDDR4__DENALI_CTL_343_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_343_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_WIDTH 8U
+#define LPDDR4__INT_STATUS_MODE__REG DENALI_CTL_343
+#define LPDDR4__INT_STATUS_MODE__FLD LPDDR4__DENALI_CTL_343__INT_STATUS_MODE
+
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_WIDTH 8U
+#define LPDDR4__INT_STATUS_PARITY__REG DENALI_CTL_343
+#define LPDDR4__INT_STATUS_PARITY__FLD LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY
+
+#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_WIDTH 32U
+#define LPDDR4__INT_ACK_TIMEOUT__REG DENALI_CTL_344
+#define LPDDR4__INT_ACK_TIMEOUT__FLD LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_SHIFT 0U
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_WIDTH 16U
+#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_345
+#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_345__MC_RESERVED16
+
+#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_SHIFT 16U
+#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_WIDTH 16U
+#define LPDDR4__INT_ACK_LOWPOWER__REG DENALI_CTL_345
+#define LPDDR4__INT_ACK_LOWPOWER__FLD LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_SHIFT 0U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_WIDTH 16U
+#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED17
+
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_SHIFT 16U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_WIDTH 16U
+#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED18
+
+#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_SHIFT 0U
+#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_WIDTH 32U
+#define LPDDR4__INT_ACK_TRAINING__REG DENALI_CTL_347
+#define LPDDR4__INT_ACK_TRAINING__FLD LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING
+
+#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_SHIFT 0U
+#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_WIDTH 32U
+#define LPDDR4__INT_ACK_USERIF__REG DENALI_CTL_348
+#define LPDDR4__INT_ACK_USERIF__FLD LPDDR4__DENALI_CTL_348__INT_ACK_USERIF
+
+#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_WIDTH 16U
+#define LPDDR4__INT_ACK_MISC__REG DENALI_CTL_349
+#define LPDDR4__INT_ACK_MISC__FLD LPDDR4__DENALI_CTL_349__INT_ACK_MISC
+
+#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_SHIFT 16U
+#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_WIDTH 8U
+#define LPDDR4__INT_ACK_BIST__REG DENALI_CTL_349
+#define LPDDR4__INT_ACK_BIST__FLD LPDDR4__DENALI_CTL_349__INT_ACK_BIST
+
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_SHIFT 24U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_WIDTH 8U
+#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_349
+#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_349__MC_RESERVED19
+
+#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_SHIFT 0U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_WIDTH 8U
+#define LPDDR4__INT_ACK_DFI__REG DENALI_CTL_350
+#define LPDDR4__INT_ACK_DFI__FLD LPDDR4__DENALI_CTL_350__INT_ACK_DFI
+
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_SHIFT 8U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_WIDTH 8U
+#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_350
+#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_350__MC_RESERVED20
+
+#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_WIDTH 8U
+#define LPDDR4__INT_ACK_FREQ__REG DENALI_CTL_350
+#define LPDDR4__INT_ACK_FREQ__FLD LPDDR4__DENALI_CTL_350__INT_ACK_FREQ
+
+#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_WIDTH 8U
+#define LPDDR4__INT_ACK_INIT__REG DENALI_CTL_350
+#define LPDDR4__INT_ACK_INIT__FLD LPDDR4__DENALI_CTL_350__INT_ACK_INIT
+
+#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_WIDTH 8U
+#define LPDDR4__INT_ACK_MODE__REG DENALI_CTL_351
+#define LPDDR4__INT_ACK_MODE__FLD LPDDR4__DENALI_CTL_351__INT_ACK_MODE
+
+#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_WIDTH 8U
+#define LPDDR4__INT_ACK_PARITY__REG DENALI_CTL_351
+#define LPDDR4__INT_ACK_PARITY__FLD LPDDR4__DENALI_CTL_351__INT_ACK_PARITY
+
+#define LPDDR4__DENALI_CTL_352_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_WIDTH 32U
+#define LPDDR4__INT_MASK_TIMEOUT__REG DENALI_CTL_352
+#define LPDDR4__INT_MASK_TIMEOUT__FLD LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_353_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_SHIFT 0U
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_WIDTH 16U
+#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_353
+#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_353__MC_RESERVED21
+
+#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_SHIFT 16U
+#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_WIDTH 16U
+#define LPDDR4__INT_MASK_LOWPOWER__REG DENALI_CTL_353
+#define LPDDR4__INT_MASK_LOWPOWER__FLD LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_354_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_SHIFT 0U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_WIDTH 16U
+#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED22
+
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_SHIFT 16U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_WIDTH 16U
+#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED23
+
+#define LPDDR4__DENALI_CTL_355_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_SHIFT 0U
+#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_WIDTH 32U
+#define LPDDR4__INT_MASK_TRAINING__REG DENALI_CTL_355
+#define LPDDR4__INT_MASK_TRAINING__FLD LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING
+
+#define LPDDR4__DENALI_CTL_356_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_SHIFT 0U
+#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_WIDTH 32U
+#define LPDDR4__INT_MASK_USERIF__REG DENALI_CTL_356
+#define LPDDR4__INT_MASK_USERIF__FLD LPDDR4__DENALI_CTL_356__INT_MASK_USERIF
+
+#define LPDDR4__DENALI_CTL_357_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_WIDTH 16U
+#define LPDDR4__INT_MASK_MISC__REG DENALI_CTL_357
+#define LPDDR4__INT_MASK_MISC__FLD LPDDR4__DENALI_CTL_357__INT_MASK_MISC
+
+#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_SHIFT 16U
+#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_WIDTH 8U
+#define LPDDR4__INT_MASK_BIST__REG DENALI_CTL_357
+#define LPDDR4__INT_MASK_BIST__FLD LPDDR4__DENALI_CTL_357__INT_MASK_BIST
+
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_SHIFT 24U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_WIDTH 8U
+#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_357
+#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_357__MC_RESERVED24
+
+#define LPDDR4__DENALI_CTL_358_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_SHIFT 0U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_WIDTH 8U
+#define LPDDR4__INT_MASK_DFI__REG DENALI_CTL_358
+#define LPDDR4__INT_MASK_DFI__FLD LPDDR4__DENALI_CTL_358__INT_MASK_DFI
+
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_SHIFT 8U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_WIDTH 8U
+#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_358
+#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_358__MC_RESERVED25
+
+#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_WIDTH 8U
+#define LPDDR4__INT_MASK_FREQ__REG DENALI_CTL_358
+#define LPDDR4__INT_MASK_FREQ__FLD LPDDR4__DENALI_CTL_358__INT_MASK_FREQ
+
+#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_WIDTH 8U
+#define LPDDR4__INT_MASK_INIT__REG DENALI_CTL_358
+#define LPDDR4__INT_MASK_INIT__FLD LPDDR4__DENALI_CTL_358__INT_MASK_INIT
+
+#define LPDDR4__DENALI_CTL_359_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_359_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_WIDTH 8U
+#define LPDDR4__INT_MASK_MODE__REG DENALI_CTL_359
+#define LPDDR4__INT_MASK_MODE__FLD LPDDR4__DENALI_CTL_359__INT_MASK_MODE
+
+#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_WIDTH 8U
+#define LPDDR4__INT_MASK_PARITY__REG DENALI_CTL_359
+#define LPDDR4__INT_MASK_PARITY__FLD LPDDR4__DENALI_CTL_359__INT_MASK_PARITY
+
+#define LPDDR4__DENALI_CTL_360_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_WIDTH 32U
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_360
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0
+
+#define LPDDR4__DENALI_CTL_361_READ_MASK 0x7F07FF01U
+#define LPDDR4__DENALI_CTL_361_WRITE_MASK 0x7F07FF01U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WOSET 0U
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_361
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1
+
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_MASK 0x0007FF00U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_WIDTH 11U
+#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_361
+#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH
+
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_WIDTH 7U
+#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_361
+#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE
+
+#define LPDDR4__DENALI_CTL_362_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_362_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U
+#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_362
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID
+
+#define LPDDR4__DENALI_CTL_363_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_363
+#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_CTL_364_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_364
+#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_CTL_365_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_365
+#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_CTL_366_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_366
+#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_CTL_367_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_367_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_WIDTH 32U
+#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_367
+#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_CTL_368_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_368_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WOSET 0U
+#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_368
+#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_CTL_369_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_369_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_WIDTH 32U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_369
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0
+
+#define LPDDR4__DENALI_CTL_370_READ_MASK 0xFF033F01U
+#define LPDDR4__DENALI_CTL_370_WRITE_MASK 0xFF033F01U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WOSET 0U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_370
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1
+
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_SHIFT 8U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_WIDTH 6U
+#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_370
+#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID
+
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_WIDTH 2U
+#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_370
+#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE
+
+#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_WIDTH 8U
+#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_370
+#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_CTL_371_READ_MASK 0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_371_WRITE_MASK 0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_WIDTH 4U
+#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_371
+#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_371__TODTH_WR_F0
+
+#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_WIDTH 4U
+#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_371
+#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_371__TODTH_RD_F0
+
+#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_WIDTH 8U
+#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_371
+#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_WIDTH 4U
+#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_371
+#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_371__TODTH_WR_F1
+
+#define LPDDR4__DENALI_CTL_372_READ_MASK 0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_372_WRITE_MASK 0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_WIDTH 4U
+#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_372
+#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_372__TODTH_RD_F1
+
+#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_WIDTH 8U
+#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_372
+#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_WIDTH 4U
+#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_372
+#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_372__TODTH_WR_F2
+
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_WIDTH 4U
+#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_372
+#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_372__TODTH_RD_F2
+
+#define LPDDR4__DENALI_CTL_373_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_373_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WOSET 0U
+#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_373
+#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F0
+
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WOSET 0U
+#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_373
+#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F1
+
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WOSET 0U
+#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_373
+#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F2
+
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_373
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD
+
+#define LPDDR4__DENALI_CTL_374_READ_MASK 0x033F3F3FU
+#define LPDDR4__DENALI_CTL_374_WRITE_MASK 0x033F3F3FU
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_374
+#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_374
+#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_374
+#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_WIDTH 2U
+#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_374
+#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_375_READ_MASK 0x3F030303U
+#define LPDDR4__DENALI_CTL_375_WRITE_MASK 0x3F030303U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_WIDTH 2U
+#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_375
+#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_WIDTH 2U
+#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_375
+#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_WIDTH 2U
+#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_375
+#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_375
+#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_376_READ_MASK 0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_376_WRITE_MASK 0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_376
+#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_376
+#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_WIDTH 5U
+#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_376
+#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0
+
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_WIDTH 5U
+#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_376
+#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1
+
+#define LPDDR4__DENALI_CTL_377_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_377_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_WIDTH 5U
+#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_377
+#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2
+
+#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_377
+#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_377
+#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_377
+#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_378_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_378_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_378
+#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_378
+#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_378
+#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_378
+#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_379_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_379_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_379
+#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_379
+#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_379
+#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_379
+#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_380_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_380
+#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_WIDTH 5U
+#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_380
+#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_WIDTH 5U
+#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_380
+#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_WIDTH 5U
+#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_380
+#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_381_READ_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_381_WRITE_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_WIDTH 5U
+#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_381
+#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_WIDTH 5U
+#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_381
+#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_SHIFT 16U
+#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_WIDTH 5U
+#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_381
+#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_WIDTH 4U
+#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_381
+#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_CTL_382_READ_MASK 0x0F070F07U
+#define LPDDR4__DENALI_CTL_382_WRITE_MASK 0x0F070F07U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_WIDTH 3U
+#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0
+
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_WIDTH 4U
+#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_WIDTH 3U
+#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1
+
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_WIDTH 4U
+#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_CTL_383_READ_MASK 0x07010107U
+#define LPDDR4__DENALI_CTL_383_WRITE_MASK 0x07010107U
+#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_WIDTH 3U
+#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_383
+#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2
+
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_383
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE
+
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_383
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE
+
+#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_SHIFT 24U
+#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_WIDTH 3U
+#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_383
+#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY
+
+#define LPDDR4__DENALI_CTL_384_READ_MASK 0xFF010307U
+#define LPDDR4__DENALI_CTL_384_WRITE_MASK 0xFF010307U
+#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_WIDTH 3U
+#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_384
+#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY
+
+#define LPDDR4__DENALI_CTL_384__CKE_STATUS_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_384__CKE_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_384__CKE_STATUS_WIDTH 2U
+#define LPDDR4__CKE_STATUS__REG DENALI_CTL_384
+#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_384__CKE_STATUS
+
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_SHIFT 16U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WIDTH 1U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WOCLR 0U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WOSET 0U
+#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_384
+#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_384__MEM_RST_VALID
+
+#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_WIDTH 8U
+#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_384
+#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0
+
+#define LPDDR4__DENALI_CTL_385_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_WIDTH 21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_385
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_CTL_386_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_386_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_386
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_387_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_387_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_387
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_388_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_388_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_388
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_389_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_389_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_389
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_390_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_390_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_WIDTH 23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_390
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0
+
+#define LPDDR4__DENALI_CTL_391_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_391
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_CTL_392_READ_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_392_WRITE_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_WIDTH 4U
+#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_WIDTH 3U
+#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_WIDTH 8U
+#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_WIDTH 8U
+#define LPDDR4__TDFI_RDDATA_EN_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_RDDATA_EN_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0
+
+#define LPDDR4__DENALI_CTL_393_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_393_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_WIDTH 8U
+#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_393
+#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_WIDTH 8U
+#define LPDDR4__TDFI_PHY_WRLAT_F0__REG DENALI_CTL_393
+#define LPDDR4__TDFI_PHY_WRLAT_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_WIDTH 8U
+#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_393
+#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1
+
+#define LPDDR4__DENALI_CTL_394_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_WIDTH 21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_394
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_CTL_395_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_395
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_396_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_396_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_396
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_397_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_397_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_397
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_398
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_399_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_399_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_WIDTH 23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_399
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1
+
+#define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_400
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_WIDTH 4U
+#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_WIDTH 3U
+#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_WIDTH 8U
+#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_WIDTH 8U
+#define LPDDR4__TDFI_RDDATA_EN_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_RDDATA_EN_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1
+
+#define LPDDR4__DENALI_CTL_402_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_WIDTH 8U
+#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_402
+#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_WIDTH 8U
+#define LPDDR4__TDFI_PHY_WRLAT_F1__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHY_WRLAT_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_WIDTH 8U
+#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2
+
+#define LPDDR4__DENALI_CTL_403_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_403_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_WIDTH 21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_403
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_CTL_404_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_404_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_404
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_405_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_405_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_405
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_406_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_406
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_407
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_408_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_408_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_WIDTH 23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_408
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2
+
+#define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_409
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_CTL_410_READ_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_410_WRITE_MASK 0xFFFF070FU
+#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_WIDTH 4U
+#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_WIDTH 3U
+#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_WIDTH 8U
+#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_WIDTH 8U
+#define LPDDR4__TDFI_RDDATA_EN_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_RDDATA_EN_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2
+
+#define LPDDR4__DENALI_CTL_411_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_WIDTH 8U
+#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_411
+#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_WIDTH 8U
+#define LPDDR4__TDFI_PHY_WRLAT_F2__REG DENALI_CTL_411
+#define LPDDR4__TDFI_PHY_WRLAT_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_SHIFT 16U
+#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_WIDTH 16U
+#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_411
+#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_411__DLL_RST_DELAY
+
+#define LPDDR4__DENALI_CTL_412_READ_MASK 0x00037FFFU
+#define LPDDR4__DENALI_CTL_412_WRITE_MASK 0x00037FFFU
+#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_WIDTH 8U
+#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_412
+#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_WIDTH 7U
+#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_412
+#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_WIDTH 2U
+#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_412
+#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_413_READ_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_CTL_413_WRITE_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_WIDTH 16U
+#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_413
+#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH 4U
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH 4U
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE
+
+#define LPDDR4__DENALI_CTL_414_READ_MASK 0x0701FF07U
+#define LPDDR4__DENALI_CTL_414_WRITE_MASK 0x0701FF07U
+#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_WIDTH 3U
+#define LPDDR4__TDFI_PARIN_LAT__REG DENALI_CTL_414
+#define LPDDR4__TDFI_PARIN_LAT__FLD LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT
+
+#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_WIDTH 8U
+#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_414
+#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY
+
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_414
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE
+
+#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_WIDTH 3U
+#define LPDDR4__STRATEGY_2TICK_COUNT__REG DENALI_CTL_414
+#define LPDDR4__STRATEGY_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415_READ_MASK 0x07070707U
+#define LPDDR4__DENALI_CTL_415_WRITE_MASK 0x07070707U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_WIDTH 3U
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_WIDTH 3U
+#define LPDDR4__PRE_2TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__PRE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_WIDTH 3U
+#define LPDDR4__STRATEGY_4TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__STRATEGY_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_WIDTH 3U
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_416_READ_MASK 0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_416_WRITE_MASK 0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_WIDTH 3U
+#define LPDDR4__PRE_4TICK_COUNT__REG DENALI_CTL_416
+#define LPDDR4__PRE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__REG DENALI_CTL_416
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__REG DENALI_CTL_416
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__REG DENALI_CTL_416
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_417_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__ODT_TICK_PLUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__ODT_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__ODT_TICK_MINUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__ODT_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_418_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TRP_TICK_PLUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TRP_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TRP_TICK_MINUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TRP_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TWR_TICK_PLUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TWR_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_419_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TWR_TICK_MINUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TWR_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_420_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__RL_TICK_PLUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__RL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__RL_TICK_MINUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__RL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_WIDTH 4U
+#define LPDDR4__WL_TICK_PLUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__WL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_421_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_CTL_421_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_WIDTH 4U
+#define LPDDR4__WL_TICK_MINUS_ADJ__REG DENALI_CTL_421
+#define LPDDR4__WL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_421__NWR_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_421__NWR_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_421__NWR_F0_WIDTH 8U
+#define LPDDR4__NWR_F0__REG DENALI_CTL_421
+#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_421__NWR_F0
+
+#define LPDDR4__DENALI_CTL_421__NWR_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_421__NWR_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_421__NWR_F1_WIDTH 8U
+#define LPDDR4__NWR_F1__REG DENALI_CTL_421
+#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_421__NWR_F1
+
+#define LPDDR4__DENALI_CTL_421__NWR_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_421__NWR_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_421__NWR_F2_WIDTH 8U
+#define LPDDR4__NWR_F2__REG DENALI_CTL_421
+#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_421__NWR_F2
+
+#define LPDDR4__DENALI_CTL_422_READ_MASK 0x007F7F7FU
+#define LPDDR4__DENALI_CTL_422_WRITE_MASK 0x007F7F7FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_WIDTH 7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0
+
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_WIDTH 7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1
+
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_WIDTH 7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2
+
+#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
new file mode 100644
index 0000000..dcfd7d9
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
@@ -0,0 +1,1838 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
+#define REG_LPDDR4_PHY_CORE_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1280_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH 2U
+#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1280
+#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1281_READ_MASK 0x1F030101U
+#define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0x1F030101U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET 0U
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1281
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOSET 0U
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1281
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN
+
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH 2U
+#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1281
+#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX
+
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1281
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1285_READ_MASK 0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__REG DENALI_PHY_1285
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__REG DENALI_PHY_1285
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__REG DENALI_PHY_1285
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1286_READ_MASK 0x011F07FFU
+#define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x011F07FFU
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH 11U
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1286
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY
+
+#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_WIDTH 5U
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1286
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT
+
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WOSET 0U
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1286
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1287_READ_MASK 0x07FF0100U
+#define LPDDR4__DENALI_PHY_1287_WRITE_MASK 0x07FF0100U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WOSET 0U
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1287
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET 0U
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1287
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE
+
+#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_WIDTH 11U
+#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1287
+#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START
+
+#define LPDDR4__DENALI_PHY_1288_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_WIDTH 11U
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1288
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY
+
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WOSET 0U
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1288
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE
+
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WOSET 0U
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1288
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT
+
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WOSET 0U
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1289
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR
+
+#define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_WIDTH 32U
+#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1290
+#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0
+
+#define LPDDR4__DENALI_PHY_1291_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_WIDTH 32U
+#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1291
+#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1
+
+#define LPDDR4__DENALI_PHY_1292_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_WIDTH 32U
+#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1292
+#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2
+
+#define LPDDR4__DENALI_PHY_1293_READ_MASK 0x0101FF01U
+#define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0x0101FF01U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WOSET 0U
+#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1293
+#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE
+
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH 9U
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1293
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET
+
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WOSET 0U
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1293
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE
+
+#define LPDDR4__DENALI_PHY_1294_READ_MASK 0x0007FF03U
+#define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x0007FF03U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_WIDTH 2U
+#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1294
+#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP
+
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_WIDTH 11U
+#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1294
+#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR
+
+#define LPDDR4__DENALI_PHY_1295_READ_MASK 0x070F07FFU
+#define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0x070F07FFU
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_WIDTH 11U
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1295
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK
+
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH 4U
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1295
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH 3U
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1295
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE
+
+#define LPDDR4__DENALI_PHY_1296_READ_MASK 0x01010300U
+#define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0x01010300U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WOSET 0U
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS
+
+#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_WIDTH 2U
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1296
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE
+
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WOSET 0U
+#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR
+
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WOSET 0U
+#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1296
+#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE
+
+#define LPDDR4__DENALI_PHY_1297_READ_MASK 0x0F010001U
+#define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0x0F010001U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WOSET 0U
+#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1297
+#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS
+
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET 0U
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1297
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES
+
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET 0U
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1297
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_WIDTH 4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1297
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1298_READ_MASK 0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH 4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1298
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_WIDTH 4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__REG DENALI_PHY_1298
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_WIDTH 4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__REG DENALI_PHY_1298
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WOSET 0U
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1298
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL
+
+#define LPDDR4__DENALI_PHY_1299_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1300_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET 0U
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1300
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL
+
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOSET 0U
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1300
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET 0U
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1300
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1301_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_WIDTH 16U
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1301
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL
+
+#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH 4U
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1301
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET 0U
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1301
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1302_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WOSET 0U
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1302
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1303_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_WIDTH 32U
+#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1303
+#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS
+
+#define LPDDR4__DENALI_PHY_1304_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_WIDTH 16U
+#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1304
+#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT
+
+#define LPDDR4__DENALI_PHY_1305_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WOSET 0U
+#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1305
+#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1306_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_WIDTH 4U
+#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0
+
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_WIDTH 4U
+#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1
+
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_WIDTH 4U
+#define LPDDR4__PHY_SET_DFI_INPUT_2__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_2__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2
+
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_WIDTH 4U
+#define LPDDR4__PHY_SET_DFI_INPUT_3__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_3__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3
+
+#define LPDDR4__DENALI_PHY_1307_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0
+
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0
+
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0
+
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0
+
+#define LPDDR4__DENALI_PHY_1308_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1
+
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1
+
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1
+
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1
+
+#define LPDDR4__DENALI_PHY_1309_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2
+
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2
+
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2
+
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2
+
+#define LPDDR4__DENALI_PHY_1310_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3
+
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3
+
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3
+
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_WIDTH 2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3
+
+#define LPDDR4__DENALI_PHY_1311_READ_MASK 0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_WIDTH 13U
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1311
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_WIDTH 16U
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1311
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1312_READ_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WOSET 0U
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1312
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK
+
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_WIDTH 8U
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1312
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL
+
+#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH 2U
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1312
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS
+
+#define LPDDR4__DENALI_PHY_1313_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_WIDTH 16U
+#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1313
+#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1314_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_WIDTH 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1314
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_WIDTH 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__REG DENALI_PHY_1315
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_WIDTH 12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__REG DENALI_PHY_1315
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1316_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_WIDTH 16U
+#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1316
+#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1317_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_WIDTH 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1317
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1318_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_WIDTH 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_WIDTH 12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1319_READ_MASK 0xFF0F0101U
+#define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0xFF0F0101U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WOSET 0U
+#define LPDDR4__PHY_PLL_REFOUT_SEL__REG DENALI_PHY_1319
+#define LPDDR4__PHY_PLL_REFOUT_SEL__FLD LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL
+
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET 0U
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1319
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_WIDTH 4U
+#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1319
+#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT
+
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_WIDTH 8U
+#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1319
+#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP
+
+#define LPDDR4__DENALI_PHY_1320_READ_MASK 0x0003FF01U
+#define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x0003FF01U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WOSET 0U
+#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1320
+#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN
+
+#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH 10U
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1320
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG
+
+#define LPDDR4__DENALI_PHY_1321_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_WIDTH 17U
+#define LPDDR4__PHY_DS_EXIT_CTRL__REG DENALI_PHY_1321
+#define LPDDR4__PHY_DS_EXIT_CTRL__FLD LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL
+
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WOSET 0U
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1321
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY
+
+#define LPDDR4__DENALI_PHY_1322_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1322
+#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM
+
+#define LPDDR4__DENALI_PHY_1323_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_WIDTH 17U
+#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1323
+#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM
+
+#define LPDDR4__DENALI_PHY_1324_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_WIDTH 17U
+#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1324
+#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM
+
+#define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1325
+#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM
+
+#define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1326
+#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM
+
+#define LPDDR4__DENALI_PHY_1327_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_ERR_TERM__REG DENALI_PHY_1327
+#define LPDDR4__PHY_PAD_ERR_TERM__FLD LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM
+
+#define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1328
+#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM
+
+#define LPDDR4__DENALI_PHY_1329_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1329_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1329
+#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM
+
+#define LPDDR4__DENALI_PHY_1330_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1330_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1330
+#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM
+
+#define LPDDR4__DENALI_PHY_1331_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1331_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_WIDTH 18U
+#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1331
+#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM
+
+#define LPDDR4__DENALI_PHY_1332_READ_MASK 0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1332_WRITE_MASK 0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_WIDTH 10U
+#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1332
+#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_MASK 0x1FFF0000U
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_WIDTH 13U
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1332
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1333_READ_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1333_WRITE_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_WIDTH 13U
+#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1333
+#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0
+
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WOSET 0U
+#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1333
+#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WOSET 0U
+#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1333
+#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_1334_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1334_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_WIDTH 32U
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1334
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0
+
+#define LPDDR4__DENALI_PHY_1335_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1335_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_WIDTH 8U
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1335
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1335
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1336_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1336
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1337_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1337
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0
+
+#define LPDDR4__DENALI_PHY_1338_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1338_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1338
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0
+
+#define LPDDR4__DENALI_PHY_1339_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1339_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1339
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0
+
+#define LPDDR4__DENALI_PHY_1340_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1340_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1340
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0
+
+#define LPDDR4__DENALI_PHY_1341_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1341_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_WIDTH 24U
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1341
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0
+
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_WIDTH 7U
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1341
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0
+
+#define LPDDR4__DENALI_PHY_1342_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1342_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_WIDTH 8U
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_WIDTH 8U
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_WIDTH 8U
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WOSET 0U
+#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0
+
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WOSET 0U
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1343
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0
+
+#define LPDDR4__DENALI_PHY_1344_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1344_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_WIDTH 32U
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1344
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0
+
+#define LPDDR4__DENALI_PHY_1345_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1345_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_WIDTH 8U
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1345
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0
+
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_MASK 0x0FFFFF00U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_WIDTH 20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1345
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1346_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1346_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH 20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1346
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0
+
+#define LPDDR4__DENALI_PHY_1347_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1347_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_WIDTH 25U
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1347
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0
+
+#define LPDDR4__DENALI_PHY_1348_READ_MASK 0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1348_WRITE_MASK 0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_WIDTH 23U
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1348
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0
+
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1348
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349_READ_MASK 0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1349_WRITE_MASK 0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH 5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350_READ_MASK 0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1350_WRITE_MASK 0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH 5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH 5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1351_READ_MASK 0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1351_WRITE_MASK 0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1351
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH 6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1351
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH 5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1351
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1352_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1352_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_WIDTH 16U
+#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1352
+#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL
+
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WOSET 0U
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1352
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WOSET 0U
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1352
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR
+
+#define LPDDR4__DENALI_PHY_1353_READ_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1353_WRITE_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_WIDTH 2U
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1353
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_WIDTH 4U
+#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1353
+#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_WIDTH 9U
+#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1353
+#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1354_READ_MASK 0x00000F7FU
+#define LPDDR4__DENALI_PHY_1354_WRITE_MASK 0x00000F7FU
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_MASK 0x0000007FU
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_WIDTH 7U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1354
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START
+
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_WIDTH 4U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1354
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK
+
+#define LPDDR4__DENALI_PHY_1355_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1355_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_WIDTH 32U
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1355
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1356_READ_MASK 0x003F0101U
+#define LPDDR4__DENALI_PHY_1356_WRITE_MASK 0x003F0101U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET 0U
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1356
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WOSET 0U
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1356
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_WIDTH 6U
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1356
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1357_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1357_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH 16U
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1357
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WOSET 0U
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1357
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WOSET 0U
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1357
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1358_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1358_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET 0U
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1358
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE
+
+#define LPDDR4__DENALI_PHY_1359_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_WIDTH 32U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1359
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL
+
+#define LPDDR4__DENALI_PHY_1360_READ_MASK 0x03071FFFU
+#define LPDDR4__DENALI_PHY_1360_WRITE_MASK 0x03071FFFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH 8U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1360
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH
+
+#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_WIDTH 5U
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1360
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP
+
+#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_WIDTH 3U
+#define LPDDR4__PHY_ADR_DISABLE__REG DENALI_PHY_1360
+#define LPDDR4__PHY_ADR_DISABLE__FLD LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE
+
+#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH 2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1360
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0
+
+#define LPDDR4__DENALI_PHY_1361_READ_MASK 0x00030303U
+#define LPDDR4__DENALI_PHY_1361_WRITE_MASK 0x00030303U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH 2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1361
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1
+
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_WIDTH 2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__REG DENALI_PHY_1361
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2
+
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_WIDTH 2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__REG DENALI_PHY_1361
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3
+
+#define LPDDR4__DENALI_PHY_1362_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1362_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_WIDTH 32U
+#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1362
+#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE
+
+#define LPDDR4__DENALI_PHY_1363_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1363_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_WIDTH 26U
+#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1363
+#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE
+
+#define LPDDR4__DENALI_PHY_1364_READ_MASK 0x00FF073FU
+#define LPDDR4__DENALI_PHY_1364_WRITE_MASK 0x00FF073FU
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_WIDTH 6U
+#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1364
+#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK
+
+#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_WIDTH 3U
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1364
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG
+
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH 8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1364
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC
+
+#define LPDDR4__DENALI_PHY_1365_READ_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1365_WRITE_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_WIDTH 16U
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__REG DENALI_PHY_1365
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__FLD LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN
+
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_WIDTH 3U
+#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1365
+#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN
+
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_WIDTH 3U
+#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1365
+#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS
+
+#define LPDDR4__DENALI_PHY_1366_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_WIDTH 32U
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1366
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1367_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1367_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_WIDTH 32U
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1367
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1368_READ_MASK 0x030FFF03U
+#define LPDDR4__DENALI_PHY_1368_WRITE_MASK 0x030FFF03U
+#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_WIDTH 2U
+#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1368
+#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN
+
+#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_WIDTH 12U
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1368
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_WIDTH 2U
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1368
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1369_READ_MASK 0x0F1F0101U
+#define LPDDR4__DENALI_PHY_1369_WRITE_MASK 0x0F1F0101U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WOSET 0U
+#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1369
+#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK
+
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WOSET 0U
+#define LPDDR4__PHY_ERR_IE__REG DENALI_PHY_1369
+#define LPDDR4__PHY_ERR_IE__FLD LPDDR4__DENALI_PHY_1369__PHY_ERR_IE
+
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH 5U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1369
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_WIDTH 4U
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1369
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1370_READ_MASK 0x000707FFU
+#define LPDDR4__DENALI_PHY_1370_WRITE_MASK 0x000707FFU
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH 11U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1370
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS
+
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_WIDTH 3U
+#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1370
+#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS
+
+#define LPDDR4__DENALI_PHY_1371_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1371_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_WIDTH 18U
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1371
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_1372_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1372_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_WIDTH 16U
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1372
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG
+
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_MASK 0x00070000U
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_WIDTH 3U
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__REG DENALI_PHY_1372
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__FLD LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL
+
+#define LPDDR4__DENALI_PHY_1373_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1373_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WOSET 0U
+#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1373
+#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1374_READ_MASK 0x00011FFFU
+#define LPDDR4__DENALI_PHY_1374_WRITE_MASK 0x00011FFFU
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_WIDTH 13U
+#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1374
+#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WOSET 0U
+#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1374
+#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1375_READ_MASK 0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1375_WRITE_MASK 0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_WIDTH 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1375
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC
+
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_WIDTH 4U
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1375
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_WIDTH 4U
+#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1375
+#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP
+
+#define LPDDR4__DENALI_PHY_1376_READ_MASK 0x010103FFU
+#define LPDDR4__DENALI_PHY_1376_WRITE_MASK 0x010103FFU
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_WIDTH 10U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1376
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN
+
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WOSET 0U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1376
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN
+
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET 0U
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1376
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE
+
+#define LPDDR4__DENALI_PHY_1377_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1377_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1377
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1377
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1378_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1378_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1378
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1378
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1379_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1379_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1379
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1379
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1380_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1380_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1380
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1380
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1381_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1381_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__REG DENALI_PHY_1381
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__REG DENALI_PHY_1381
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1382_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1382_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__REG DENALI_PHY_1382
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_WIDTH 11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__REG DENALI_PHY_1382
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1383_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1383_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__REG DENALI_PHY_1383
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1384_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1384_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__REG DENALI_PHY_1384
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1385_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1385_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__REG DENALI_PHY_1385
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1386_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1386_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_WIDTH 11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__REG DENALI_PHY_1386
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1387_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1387
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1388_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1388_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_WIDTH 18U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1388
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1389_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1389_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_WIDTH 31U
+#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1389
+#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE
+
+#define LPDDR4__DENALI_PHY_1390_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1390_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_WIDTH 32U
+#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1390
+#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1391_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1391_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1391
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1392_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1392_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1392
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1393_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1393_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_WIDTH 32U
+#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1393
+#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1394_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1394_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_WIDTH 19U
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1394
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1395_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1395_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_ERR_DRIVE__REG DENALI_PHY_1395
+#define LPDDR4__PHY_PAD_ERR_DRIVE__FLD LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1396_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1396_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__REG DENALI_PHY_1396
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__FLD LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1397_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1397_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1397
+#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE
+
+#define LPDDR4__DENALI_PHY_1398_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1398_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1398
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1399_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1399_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1399
+#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE
+
+#define LPDDR4__DENALI_PHY_1400_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1400_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1400
+#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1401_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1401_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1401
+#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1402_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1402_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1402
+#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1403_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1403_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_WIDTH 30U
+#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1403
+#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE
+
+#define LPDDR4__DENALI_PHY_1404_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1404_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_WIDTH 28U
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1404
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1405_READ_MASK 0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1405_WRITE_MASK 0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_WIDTH 3U
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1405
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH 16U
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1405
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0
+
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_WIDTH 7U
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1405
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0
+
+#endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
new file mode 100644
index 0000000..9aa281a
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
@@ -0,0 +1,5784 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PI_MACROS_H_
+#define REG_LPDDR4_PI_MACROS_H_
+
+#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U
+#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U
+#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U
+#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U
+#define LPDDR4__PI_START__REG DENALI_PI_0
+#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
+
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U
+#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
+#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
+
+#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U
+#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
+#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
+
+#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U
+#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
+#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
+
+#define LPDDR4__DENALI_PI_3_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U
+#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U
+#define LPDDR4__PI_ID__REG DENALI_PI_3
+#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
+
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_SHIFT 16U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WIDTH 1U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOCLR 0U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOSET 0U
+#define LPDDR4__PI_RELEASE_DFI__REG DENALI_PI_3
+#define LPDDR4__PI_RELEASE_DFI__FLD LPDDR4__DENALI_PI_3__PI_RELEASE_DFI
+
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOSET 0U
+#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_3
+#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ
+
+#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOSET 0U
+#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_4
+#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN
+
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_SHIFT 8U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_WIDTH 2U
+#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_4
+#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD
+
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_SHIFT 16U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_WIDTH 16U
+#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_4
+#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_4__PI_TCMD_GAP
+
+#define LPDDR4__DENALI_PI_5_READ_MASK 0x030100FFU
+#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x030100FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_SHIFT 0U
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_WIDTH 8U
+#define LPDDR4__PI_RESERVED0__REG DENALI_PI_5
+#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_5__PI_RESERVED0
+
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_SHIFT 8U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_5
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_SHIFT 16U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WIDTH 1U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOCLR 0U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOSET 0U
+#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_5__PI_DFI_VERSION
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_SHIFT 24U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_WIDTH 2U
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_6_READ_MASK 0x00000101U
+#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00000101U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R
+
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 8U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R
+
+#define LPDDR4__DENALI_PI_7_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_7
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX
+
+#define LPDDR4__DENALI_PI_8_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_8_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_WIDTH 20U
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_8
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP
+
+#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_WIDTH 20U
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_9
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP
+
+#define LPDDR4__DENALI_PI_10_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_10
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX
+
+#define LPDDR4__DENALI_PI_11_READ_MASK 0x0000011FU
+#define LPDDR4__DENALI_PI_11_WRITE_MASK 0x0000011FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_SHIFT 0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_WIDTH 5U
+#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ
+
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOSET 0U
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY
+
+#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U
+#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
+#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
+
+#define LPDDR4__DENALI_PI_13_READ_MASK 0x01030101U
+#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x01030101U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U
+#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
+#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
+
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 8U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U
+#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
+#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
+
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_SHIFT 16U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_WIDTH 2U
+#define LPDDR4__PI_CS_MAP__REG DENALI_PI_13
+#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_13__PI_CS_MAP
+
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_SHIFT 24U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOSET 0U
+#define LPDDR4__PI_SWLVL_CS_SEL__REG DENALI_PI_13
+#define LPDDR4__PI_SWLVL_CS_SEL__FLD LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL
+
+#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F03U
+#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F03U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_WIDTH 2U
+#define LPDDR4__PI_CS_MASK__REG DENALI_PI_14
+#define LPDDR4__PI_CS_MASK__FLD LPDDR4__DENALI_PI_14__PI_CS_MASK
+
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U
+#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
+#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
+
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
+
+#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U
+#define LPDDR4__PI_TMRR__REG DENALI_PI_14
+#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
+
+#define LPDDR4__DENALI_PI_15_READ_MASK 0x0101070FU
+#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x0101070FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_SHIFT 0U
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_WIDTH 4U
+#define LPDDR4__PI_TMPRR__REG DENALI_PI_15
+#define LPDDR4__PI_TMPRR__FLD LPDDR4__DENALI_PI_15__PI_TMPRR
+
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_WIDTH 3U
+#define LPDDR4__PI_VRCG_EN__REG DENALI_PI_15
+#define LPDDR4__PI_VRCG_EN__FLD LPDDR4__DENALI_PI_15__PI_VRCG_EN
+
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 16U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
+
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 24U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U
+#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
+#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
+
+#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U
+#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
+#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
+
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U
+#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
+#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
+
+#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U
+#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U
+#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
+#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U
+#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U
+#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
+
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
+#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18_READ_MASK 0x03030301U
+#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03030301U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_WIDTH 2U
+#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0
+
+#define LPDDR4__DENALI_PI_19_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_SHIFT 0U
+#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_WIDTH 3U
+#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_19
+#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE
+
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_SHIFT 8U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOSET 0U
+#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_19
+#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_START
+
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_WOSET 0U
+#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_19
+#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT
+
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_19
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_WR_SLICE_0
+
+#define LPDDR4__DENALI_PI_20_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_RD_SLICE_0
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_VREF_UPDATE_SLICE_0
+
+#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_20
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_20__PI_SW_WDQLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_1
+
+#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_1
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_1
+
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_21
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_SHIFT 24U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_SM2_START
+
+#define LPDDR4__DENALI_PI_22_READ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_SHIFT 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_WR
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_SHIFT 8U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_SM2_RD
+
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ_WOSET 0U
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_22
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_22__PI_SEQUENTIAL_LVL_REQ
+
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_22
+#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_22__PI_DFS_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_23_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_23
+#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_23__PI_SRE_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_MPD_PERIOD_EN__REG DENALI_PI_23
+#define LPDDR4__PI_MPD_PERIOD_EN__FLD LPDDR4__DENALI_PI_23__PI_MPD_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_SHIFT 16U
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY_WOSET 0U
+#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_23
+#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_23__PI_DFI40_POLARITY
+
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_WRLVL_REQ_WOSET 0U
+#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_23
+#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_23__PI_WRLVL_REQ
+
+#define LPDDR4__DENALI_PI_24_READ_MASK 0x3F3F0103U
+#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x3F3F0103U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_SHIFT 0U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW_WIDTH 2U
+#define LPDDR4__PI_WRLVL_CS_SW__REG DENALI_PI_24
+#define LPDDR4__PI_WRLVL_CS_SW__FLD LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_SHIFT 8U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WIDTH 1U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WOCLR 0U
+#define LPDDR4__DENALI_PI_24__PI_WRLVL_CS_WOSET 0U
+#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_24
+#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_24__PI_WRLVL_CS
+
+#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_SHIFT 16U
+#define LPDDR4__DENALI_PI_24__PI_WLDQSEN_WIDTH 6U
+#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_24
+#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_24__PI_WLDQSEN
+
+#define LPDDR4__DENALI_PI_24__PI_WLMRD_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_24__PI_WLMRD_SHIFT 24U
+#define LPDDR4__DENALI_PI_24__PI_WLMRD_WIDTH 6U
+#define LPDDR4__PI_WLMRD__REG DENALI_PI_24
+#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_24__PI_WLMRD
+
+#define LPDDR4__DENALI_PI_25_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_25
+#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_25
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_SHIFT 24U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_25
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_25__PI_WRLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_26_READ_MASK 0x01030103U
+#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x01030103U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK_WIDTH 2U
+#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_SHIFT 8U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_SHIFT 16U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP_WIDTH 2U
+#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT_WOSET 0U
+#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_27_READ_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS_WOSET 0U
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_27
+#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_27__PI_TDFI_WRLVL_EN
+
+#define LPDDR4__DENALI_PI_28_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_28_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_28
+#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_28__PI_TDFI_WRLVL_RESP
+
+#define LPDDR4__DENALI_PI_29_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_29_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_29
+#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_29__PI_TDFI_WRLVL_MAX
+
+#define LPDDR4__DENALI_PI_30_READ_MASK 0x030F0F1FU
+#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x030F0F1FU
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_SHIFT 0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_30
+#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_SHIFT 8U
+#define LPDDR4__DENALI_PI_30__PI_TODTH_WR_WIDTH 4U
+#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_30
+#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_30__PI_TODTH_WR
+
+#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_SHIFT 16U
+#define LPDDR4__DENALI_PI_30__PI_TODTH_RD_WIDTH 4U
+#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_30
+#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_30__PI_TODTH_RD
+
+#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_SHIFT 24U
+#define LPDDR4__DENALI_PI_30__PI_ODT_VALUE_WIDTH 2U
+#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_30
+#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_30__PI_ODT_VALUE
+
+#define LPDDR4__DENALI_PI_31_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_31_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_SHIFT 0U
+#define LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING_WIDTH 2U
+#define LPDDR4__PI_ADDRESS_MIRRORING__REG DENALI_PI_31
+#define LPDDR4__PI_ADDRESS_MIRRORING__FLD LPDDR4__DENALI_PI_31__PI_ADDRESS_MIRRORING
+
+#define LPDDR4__DENALI_PI_32_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_32_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_SHIFT 0U
+#define LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT_WIDTH 26U
+#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__REG DENALI_PI_32
+#define LPDDR4__PI_CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_PI_32__PI_CA_PARITY_ERROR_INJECT
+
+#define LPDDR4__DENALI_PI_33_READ_MASK 0x00000F07U
+#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x00000F07U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED3_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED3_SHIFT 0U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED3_WIDTH 3U
+#define LPDDR4__PI_RESERVED3__REG DENALI_PI_33
+#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_33__PI_RESERVED3
+
+#define LPDDR4__DENALI_PI_33__PI_RESERVED4_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED4_SHIFT 8U
+#define LPDDR4__DENALI_PI_33__PI_RESERVED4_WIDTH 4U
+#define LPDDR4__PI_RESERVED4__REG DENALI_PI_33
+#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_33__PI_RESERVED4
+
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_SHIFT 16U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_REQ_WOSET 0U
+#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_33
+#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_33__PI_RDLVL_REQ
+
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_33
+#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_33__PI_RDLVL_GATE_REQ
+
+#define LPDDR4__DENALI_PI_34_READ_MASK 0x00000103U
+#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x00000103U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_SHIFT 0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW_WIDTH 2U
+#define LPDDR4__PI_RDLVL_CS_SW__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_CS_SW__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT 8U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH 1U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WOCLR 0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WOSET 0U
+#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS
+
+#define LPDDR4__DENALI_PI_35_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35
+#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0
+
+#define LPDDR4__DENALI_PI_36_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36
+#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1
+
+#define LPDDR4__DENALI_PI_37_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37
+#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2
+
+#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38
+#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3
+
+#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT 0U
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39
+#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4
+
+#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT 0U
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40
+#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5
+
+#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT 0U
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41
+#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6
+
+#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT 0U
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42
+#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7
+
+#define LPDDR4__DENALI_PI_43_READ_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_43_WRITE_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH 4U
+#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT 16U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_GATE_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_44_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_44_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT 24U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_45_READ_MASK 0x00030301U
+#define LPDDR4__DENALI_PI_45_WRITE_MASK 0x00030301U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT 0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE
+
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT 8U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH 2U
+#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT 16U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP
+
+#define LPDDR4__DENALI_PI_46_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT 0U
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH 10U
+#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46
+#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR
+
+#define LPDDR4__DENALI_PI_47_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47
+#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP
+
+#define LPDDR4__DENALI_PI_48_READ_MASK 0x0000FF03U
+#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x0000FF03U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48
+#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN
+
+#define LPDDR4__DENALI_PI_49_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49
+#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX
+
+#define LPDDR4__DENALI_PI_50_READ_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_PI_50_WRITE_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET 0U
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT 8U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50
+#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_51_READ_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL
+
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT 16U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH 4U
+#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START
+
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT 24U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH 4U
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM
+
+#define LPDDR4__DENALI_PI_52_READ_MASK 0x01011F1FU
+#define LPDDR4__DENALI_PI_52_WRITE_MASK 0x01011F1FU
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT 0U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52
+#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET 0U
+#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52
+#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_PI_53_READ_MASK 0x0300FFFFU
+#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x0300FFFFU
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53
+#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN
+
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT 8U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH 8U
+#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53
+#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT
+
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT 16U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET 0U
+#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53
+#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ
+
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_SHIFT 24U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW_WIDTH 2U
+#define LPDDR4__PI_CALVL_CS_SW__REG DENALI_PI_53
+#define LPDDR4__PI_CALVL_CS_SW__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS_SW
+
+#define LPDDR4__DENALI_PI_54_READ_MASK 0x030F0101U
+#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x030F0101U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_SHIFT 0U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WIDTH 1U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WOCLR 0U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_CS_WOSET 0U
+#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_54
+#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_54__PI_CALVL_CS
+
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_SHIFT 8U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WIDTH 1U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WOCLR 0U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED5_WOSET 0U
+#define LPDDR4__PI_RESERVED5__REG DENALI_PI_54
+#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_54__PI_RESERVED5
+
+#define LPDDR4__DENALI_PI_54__PI_RESERVED6_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED6_SHIFT 16U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED6_WIDTH 4U
+#define LPDDR4__PI_RESERVED6__REG DENALI_PI_54
+#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_54__PI_RESERVED6
+
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH 2U
+#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54
+#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_55_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_SHIFT 0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC_WOSET 0U
+#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_55__PI_CALVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT 16U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT 24U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE
+
+#define LPDDR4__DENALI_PI_56_READ_MASK 0x0000FF03U
+#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x0000FF03U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP_WIDTH 2U
+#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_56
+#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_56__PI_CALVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56
+#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN
+
+#define LPDDR4__DENALI_PI_57_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57
+#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP
+
+#define LPDDR4__DENALI_PI_58_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58
+#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX
+
+#define LPDDR4__DENALI_PI_59_READ_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_59_WRITE_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH 1U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR 0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET 0U
+#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT 16U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_60_READ_MASK 0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_60_WRITE_MASK 0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT 0U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH 5U
+#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60
+#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL
+
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT 8U
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH 6U
+#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60
+#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD
+
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT 16U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH 5U
+#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60
+#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH
+
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT 24U
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH 5U
+#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60
+#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT
+
+#define LPDDR4__DENALI_PI_61_READ_MASK 0xFF0F0F01U
+#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFF0F0F01U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET 0U
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN
+
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT 24U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH 8U
+#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61
+#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN
+
+#define LPDDR4__DENALI_PI_62_READ_MASK 0x017F1FFFU
+#define LPDDR4__DENALI_PI_62_WRITE_MASK 0x017F1FFFU
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT 0U
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH 8U
+#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62
+#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH
+
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT 8U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT 16U
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH 7U
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF
+
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_62
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_62__PI_REFRESH_BETWEEN_SEGMENT_DISABLE
+
+#define LPDDR4__DENALI_PI_63_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_63_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT 0U
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH 8U
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START
+
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
+
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL
+
+#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 24U
+#define LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_63
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_63__PI_TDFI_INIT_COMPLETE_MIN
+
+#define LPDDR4__DENALI_PI_64_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_64_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_SHIFT 0U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WIDTH 1U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WOCLR 0U
+#define LPDDR4__DENALI_PI_64__PI_VREF_CS_WOSET 0U
+#define LPDDR4__PI_VREF_CS__REG DENALI_PI_64
+#define LPDDR4__PI_VREF_CS__FLD LPDDR4__DENALI_PI_64__PI_VREF_CS
+
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN_WOSET 0U
+#define LPDDR4__PI_VREF_PDA_EN__REG DENALI_PI_64
+#define LPDDR4__PI_VREF_PDA_EN__FLD LPDDR4__DENALI_PI_64__PI_VREF_PDA_EN
+
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_SHIFT 16U
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_VREFLVL_DISABLE_DFS__REG DENALI_PI_64
+#define LPDDR4__PI_VREFLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_64__PI_VREFLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE
+
+#define LPDDR4__DENALI_PI_65_READ_MASK 0x030701FFU
+#define LPDDR4__DENALI_PI_65_WRITE_MASK 0x030701FFU
+#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT_WIDTH 8U
+#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__REG DENALI_PI_65
+#define LPDDR4__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT__FLD LPDDR4__DENALI_PI_65__PI_INIT_COMPLETE_TO_MC_DELAY_COUNT
+
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_65
+#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_VREF_EN
+
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_MASK 0x00070000U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_SHIFT 16U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM_WIDTH 3U
+#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_65
+#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_BST_NUM
+
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_SHIFT 24U
+#define LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_65
+#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_65__PI_WDQLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_66_READ_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PI_66_WRITE_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT 0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_SHIFT 8U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 16U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 24U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_67_READ_MASK 0x01030001U
+#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x01030001U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT 0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET 0U
+#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_SHIFT 8U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ_WOSET 0U
+#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_REQ
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_SHIFT 16U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_CS_SW__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_CS_SW__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SW
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_SHIFT 24U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WIDTH 1U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WOCLR 0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_WOSET 0U
+#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS
+
+#define LPDDR4__DENALI_PI_68_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68
+#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_69_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP
+
+#define LPDDR4__DENALI_PI_70_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX
+
+#define LPDDR4__DENALI_PI_71_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT_WOSET 0U
+#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_ON_MPD_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_MPD_EXIT
+
+#define LPDDR4__DENALI_PI_72_READ_MASK 0x00030301U
+#define LPDDR4__DENALI_PI_72_WRITE_MASK 0x00030301U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_SHIFT 0U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_SHIFT 16U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_NEED_SAVE_RESTORE__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_NEED_SAVE_RESTORE
+
+#define LPDDR4__DENALI_PI_73_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0_WIDTH 32U
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__REG DENALI_PI_73
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_0__FLD LPDDR4__DENALI_PI_73__PI_WDQLVL_DRAM_LVL_START_ADDR_0
+
+#define LPDDR4__DENALI_PI_74_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1_WOSET 0U
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_DRAM_LVL_START_ADDR_1__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_DRAM_LVL_START_ADDR_1
+
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__REG DENALI_PI_74
+#define LPDDR4__PI_WDQLVL_DM_LEVEL_EN__FLD LPDDR4__DENALI_PI_74__PI_WDQLVL_DM_LEVEL_EN
+
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_SHIFT 16U
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WIDTH 1U
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WOCLR 0U
+#define LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM_WOSET 0U
+#define LPDDR4__PI_NO_MEMORY_DM__REG DENALI_PI_74
+#define LPDDR4__PI_NO_MEMORY_DM__FLD LPDDR4__DENALI_PI_74__PI_NO_MEMORY_DM
+
+#define LPDDR4__DENALI_PI_75_READ_MASK 0x010003FFU
+#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x010003FFU
+#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_SHIFT 0U
+#define LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WW__REG DENALI_PI_75
+#define LPDDR4__PI_TDFI_WDQLVL_WW__FLD LPDDR4__DENALI_PI_75__PI_TDFI_WDQLVL_WW
+
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_SHIFT 16U
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__REG DENALI_PI_75
+#define LPDDR4__PI_SWLVL_SM2_DM_NIBBLE_START__FLD LPDDR4__DENALI_PI_75__PI_SWLVL_SM2_DM_NIBBLE_START
+
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_SHIFT 24U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WIDTH 1U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WOCLR 0U
+#define LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE_WOSET 0U
+#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__REG DENALI_PI_75
+#define LPDDR4__PI_WDQLVL_NIBBLE_MODE__FLD LPDDR4__DENALI_PI_75__PI_WDQLVL_NIBBLE_MODE
+
+#define LPDDR4__DENALI_PI_76_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_76_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_76
+#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_OSC_EN
+
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_76
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_76__PI_DQS_OSC_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_PDA_EN__REG DENALI_PI_76
+#define LPDDR4__PI_WDQLVL_PDA_EN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_EN
+
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_SHIFT 24U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WIDTH 1U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WOCLR 0U
+#define LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__REG DENALI_PI_76
+#define LPDDR4__PI_WDQLVL_PDA_VREF_TRAIN__FLD LPDDR4__DENALI_PI_76__PI_WDQLVL_PDA_VREF_TRAIN
+
+#define LPDDR4__DENALI_PI_77_READ_MASK 0x1F070303U
+#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x1F070303U
+#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK_WIDTH 2U
+#define LPDDR4__PI_DBILVL_RESP_MASK__REG DENALI_PI_77
+#define LPDDR4__PI_DBILVL_RESP_MASK__FLD LPDDR4__DENALI_PI_77__PI_DBILVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_SHIFT 8U
+#define LPDDR4__DENALI_PI_77__PI_BANK_DIFF_WIDTH 2U
+#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_77
+#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_77__PI_BANK_DIFF
+
+#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_MASK 0x00070000U
+#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_SHIFT 16U
+#define LPDDR4__DENALI_PI_77__PI_ROW_DIFF_WIDTH 3U
+#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_77
+#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_77__PI_ROW_DIFF
+
+#define LPDDR4__DENALI_PI_77__PI_TCCD_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_77__PI_TCCD_SHIFT 24U
+#define LPDDR4__DENALI_PI_77__PI_TCCD_WIDTH 5U
+#define LPDDR4__PI_TCCD__REG DENALI_PI_77
+#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_77__PI_TCCD
+
+#define LPDDR4__DENALI_PI_78_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_78__PI_RESERVED7_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_78__PI_RESERVED7_SHIFT 0U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED7_WIDTH 4U
+#define LPDDR4__PI_RESERVED7__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_78__PI_RESERVED7
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED8_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED8_SHIFT 8U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED8_WIDTH 4U
+#define LPDDR4__PI_RESERVED8__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_78__PI_RESERVED8
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED9_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED9_SHIFT 16U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED9_WIDTH 4U
+#define LPDDR4__PI_RESERVED9__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_78__PI_RESERVED9
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED10_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED10_SHIFT 24U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED10_WIDTH 4U
+#define LPDDR4__PI_RESERVED10__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_78__PI_RESERVED10
+
+#define LPDDR4__DENALI_PI_79_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_79__PI_RESERVED11_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_79__PI_RESERVED11_SHIFT 0U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED11_WIDTH 4U
+#define LPDDR4__PI_RESERVED11__REG DENALI_PI_79
+#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_79__PI_RESERVED11
+
+#define LPDDR4__DENALI_PI_79__PI_RESERVED12_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED12_SHIFT 8U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED12_WIDTH 4U
+#define LPDDR4__PI_RESERVED12__REG DENALI_PI_79
+#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_79__PI_RESERVED12
+
+#define LPDDR4__DENALI_PI_79__PI_RESERVED13_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED13_SHIFT 16U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED13_WIDTH 4U
+#define LPDDR4__PI_RESERVED13__REG DENALI_PI_79
+#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_79__PI_RESERVED13
+
+#define LPDDR4__DENALI_PI_79__PI_RESERVED14_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED14_SHIFT 24U
+#define LPDDR4__DENALI_PI_79__PI_RESERVED14_WIDTH 4U
+#define LPDDR4__PI_RESERVED14__REG DENALI_PI_79
+#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_79__PI_RESERVED14
+
+#define LPDDR4__DENALI_PI_80_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_80_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_80__PI_RESERVED15_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_80__PI_RESERVED15_SHIFT 0U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED15_WIDTH 4U
+#define LPDDR4__PI_RESERVED15__REG DENALI_PI_80
+#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_80__PI_RESERVED15
+
+#define LPDDR4__DENALI_PI_80__PI_RESERVED16_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED16_SHIFT 8U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED16_WIDTH 4U
+#define LPDDR4__PI_RESERVED16__REG DENALI_PI_80
+#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_80__PI_RESERVED16
+
+#define LPDDR4__DENALI_PI_80__PI_RESERVED17_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED17_SHIFT 16U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED17_WIDTH 4U
+#define LPDDR4__PI_RESERVED17__REG DENALI_PI_80
+#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_80__PI_RESERVED17
+
+#define LPDDR4__DENALI_PI_80__PI_RESERVED18_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED18_SHIFT 24U
+#define LPDDR4__DENALI_PI_80__PI_RESERVED18_WIDTH 4U
+#define LPDDR4__PI_RESERVED18__REG DENALI_PI_80
+#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_80__PI_RESERVED18
+
+#define LPDDR4__DENALI_PI_81_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_81__PI_RESERVED19_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_81__PI_RESERVED19_SHIFT 0U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED19_WIDTH 4U
+#define LPDDR4__PI_RESERVED19__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_81__PI_RESERVED19
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED20_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED20_SHIFT 8U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED20_WIDTH 4U
+#define LPDDR4__PI_RESERVED20__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_81__PI_RESERVED20
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED21_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED21_SHIFT 16U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED21_WIDTH 4U
+#define LPDDR4__PI_RESERVED21__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_81__PI_RESERVED21
+
+#define LPDDR4__DENALI_PI_81__PI_RESERVED22_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED22_SHIFT 24U
+#define LPDDR4__DENALI_PI_81__PI_RESERVED22_WIDTH 4U
+#define LPDDR4__PI_RESERVED22__REG DENALI_PI_81
+#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_81__PI_RESERVED22
+
+#define LPDDR4__DENALI_PI_82_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_82_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_82__PI_RESERVED23_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_82__PI_RESERVED23_SHIFT 0U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED23_WIDTH 4U
+#define LPDDR4__PI_RESERVED23__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_82__PI_RESERVED23
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED24_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED24_SHIFT 8U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED24_WIDTH 4U
+#define LPDDR4__PI_RESERVED24__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_82__PI_RESERVED24
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED25_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED25_SHIFT 16U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED25_WIDTH 4U
+#define LPDDR4__PI_RESERVED25__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_82__PI_RESERVED25
+
+#define LPDDR4__DENALI_PI_82__PI_RESERVED26_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED26_SHIFT 24U
+#define LPDDR4__DENALI_PI_82__PI_RESERVED26_WIDTH 4U
+#define LPDDR4__PI_RESERVED26__REG DENALI_PI_82
+#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_82__PI_RESERVED26
+
+#define LPDDR4__DENALI_PI_83_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_83_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_83__PI_INT_STATUS_WIDTH 30U
+#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_83
+#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_83__PI_INT_STATUS
+
+#define LPDDR4__DENALI_PI_84__PI_INT_ACK_MASK 0x1FFFFFFFU
+#define LPDDR4__DENALI_PI_84__PI_INT_ACK_SHIFT 0U
+#define LPDDR4__DENALI_PI_84__PI_INT_ACK_WIDTH 29U
+#define LPDDR4__PI_INT_ACK__REG DENALI_PI_84
+#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_84__PI_INT_ACK
+
+#define LPDDR4__DENALI_PI_85_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_85_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_85__PI_INT_MASK_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_85__PI_INT_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_85__PI_INT_MASK_WIDTH 30U
+#define LPDDR4__PI_INT_MASK__REG DENALI_PI_85
+#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_85__PI_INT_MASK
+
+#define LPDDR4__DENALI_PI_86_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_86
+#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_PI_87_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_87
+#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_PI_88_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_88
+#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_PI_89_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_89
+#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_PI_91_READ_MASK 0x011F3F01U
+#define LPDDR4__DENALI_PI_91_WRITE_MASK 0x011F3F01U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WOSET 0U
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT 8U
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH 6U
+#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91
+#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN
+
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT 16U
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH 5U
+#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91
+#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET 0U
+#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91
+#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN
+
+#define LPDDR4__DENALI_PI_92_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_92_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_SHIFT 0U
+#define LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX_WIDTH 5U
+#define LPDDR4__PI_PARITY_IN_MUX__REG DENALI_PI_92
+#define LPDDR4__PI_PARITY_IN_MUX__FLD LPDDR4__DENALI_PI_92__PI_PARITY_IN_MUX
+
+#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_SHIFT 8U
+#define LPDDR4__DENALI_PI_92__PI_ACT_N_MUX_WIDTH 5U
+#define LPDDR4__PI_ACT_N_MUX__REG DENALI_PI_92
+#define LPDDR4__PI_ACT_N_MUX__FLD LPDDR4__DENALI_PI_92__PI_ACT_N_MUX
+
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_0_WIDTH 5U
+#define LPDDR4__PI_BG_MUX_0__REG DENALI_PI_92
+#define LPDDR4__PI_BG_MUX_0__FLD LPDDR4__DENALI_PI_92__PI_BG_MUX_0
+
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_92__PI_BG_MUX_1_WIDTH 5U
+#define LPDDR4__PI_BG_MUX_1__REG DENALI_PI_92
+#define LPDDR4__PI_BG_MUX_1__FLD LPDDR4__DENALI_PI_92__PI_BG_MUX_1
+
+#define LPDDR4__DENALI_PI_93_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_93_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_SHIFT 0U
+#define LPDDR4__DENALI_PI_93__PI_RAS_N_MUX_WIDTH 5U
+#define LPDDR4__PI_RAS_N_MUX__REG DENALI_PI_93
+#define LPDDR4__PI_RAS_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_RAS_N_MUX
+
+#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_SHIFT 8U
+#define LPDDR4__DENALI_PI_93__PI_CAS_N_MUX_WIDTH 5U
+#define LPDDR4__PI_CAS_N_MUX__REG DENALI_PI_93
+#define LPDDR4__PI_CAS_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_CAS_N_MUX
+
+#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_SHIFT 16U
+#define LPDDR4__DENALI_PI_93__PI_WE_N_MUX_WIDTH 5U
+#define LPDDR4__PI_WE_N_MUX__REG DENALI_PI_93
+#define LPDDR4__PI_WE_N_MUX__FLD LPDDR4__DENALI_PI_93__PI_WE_N_MUX
+
+#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_93__PI_BANK_MUX_0_WIDTH 5U
+#define LPDDR4__PI_BANK_MUX_0__REG DENALI_PI_93
+#define LPDDR4__PI_BANK_MUX_0__FLD LPDDR4__DENALI_PI_93__PI_BANK_MUX_0
+
+#define LPDDR4__DENALI_PI_94_READ_MASK 0x0101011FU
+#define LPDDR4__DENALI_PI_94_WRITE_MASK 0x0101011FU
+#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_94__PI_BANK_MUX_1_WIDTH 5U
+#define LPDDR4__PI_BANK_MUX_1__REG DENALI_PI_94
+#define LPDDR4__PI_BANK_MUX_1__FLD LPDDR4__DENALI_PI_94__PI_BANK_MUX_1
+
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN_WOSET 0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_94
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_EN
+
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 16U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 1U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WOCLR 0U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0_WOSET 0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_94
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE0
+
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 24U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 1U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WOCLR 0U
+#define LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1_WOSET 0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_94
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_94__PI_DATA_BYTE_SWAP_SLICE1
+
+#define LPDDR4__DENALI_PI_95_READ_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PI_95_WRITE_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_95
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_95__PI_CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_SHIFT 8U
+#define LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN_WIDTH 16U
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_95
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_95__PI_TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_95
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_95__PI_UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_96_READ_MASK 0x01030107U
+#define LPDDR4__DENALI_PI_96_WRITE_MASK 0x01030107U
+#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_SHIFT 0U
+#define LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT_WIDTH 3U
+#define LPDDR4__PI_TDFI_PARIN_LAT__REG DENALI_PI_96
+#define LPDDR4__PI_TDFI_PARIN_LAT__FLD LPDDR4__DENALI_PI_96__PI_TDFI_PARIN_LAT
+
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_SHIFT 8U
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WIDTH 1U
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WOCLR 0U
+#define LPDDR4__DENALI_PI_96__PI_BIST_GO_WOSET 0U
+#define LPDDR4__PI_BIST_GO__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_96__PI_BIST_GO
+
+#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_SHIFT 16U
+#define LPDDR4__DENALI_PI_96__PI_BIST_RESULT_WIDTH 2U
+#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_96__PI_BIST_RESULT
+
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_SHIFT 24U
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WIDTH 1U
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WOCLR 0U
+#define LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE_WOSET 0U
+#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_LFSR_PATTERN_DONE__FLD LPDDR4__DENALI_PI_96__PI_BIST_LFSR_PATTERN_DONE
+
+#define LPDDR4__DENALI_PI_97_READ_MASK 0x000101FFU
+#define LPDDR4__DENALI_PI_97_WRITE_MASK 0x000101FFU
+#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_SHIFT 0U
+#define LPDDR4__DENALI_PI_97__PI_ADDR_SPACE_WIDTH 8U
+#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_97
+#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_97__PI_ADDR_SPACE
+
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_SHIFT 8U
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK_WOSET 0U
+#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_97
+#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_97__PI_BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_SHIFT 16U
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK_WOSET 0U
+#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_97
+#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_97__PI_BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0_WIDTH 32U
+#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_98
+#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_PI_99_READ_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PI_99_WRITE_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1_WOSET 0U
+#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_99
+#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_SHIFT 8U
+#define LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN_WIDTH 8U
+#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_99
+#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_99__PI_MBIST_INIT_PATTERN
+
+#define LPDDR4__DENALI_PI_100_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_100_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK_WIDTH 32U
+#define LPDDR4__PI_BIST_DATA_MASK__REG DENALI_PI_100
+#define LPDDR4__PI_BIST_DATA_MASK__FLD LPDDR4__DENALI_PI_100__PI_BIST_DATA_MASK
+
+#define LPDDR4__DENALI_PI_101_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_101_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT_WIDTH 12U
+#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_101
+#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_101__PI_BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_SHIFT 16U
+#define LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP_WIDTH 12U
+#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_101
+#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_101__PI_BIST_ERR_STOP
+
+#define LPDDR4__DENALI_PI_102_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_102_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_102
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_0
+
+#define LPDDR4__DENALI_PI_103_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_103_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_103
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_0_1
+
+#define LPDDR4__DENALI_PI_104_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_104_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_104
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_0
+
+#define LPDDR4__DENALI_PI_105_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_105_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_1_1
+
+#define LPDDR4__DENALI_PI_106_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_106_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_106
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_0
+
+#define LPDDR4__DENALI_PI_107_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_107_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_107
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_2_1
+
+#define LPDDR4__DENALI_PI_108_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_108_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_108
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_0
+
+#define LPDDR4__DENALI_PI_109_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_109_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_109
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_3_1
+
+#define LPDDR4__DENALI_PI_110_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_110
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_0
+
+#define LPDDR4__DENALI_PI_111_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_111_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_111
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_4_1
+
+#define LPDDR4__DENALI_PI_112_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_112
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_0
+
+#define LPDDR4__DENALI_PI_113_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_113_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_113
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_5_1
+
+#define LPDDR4__DENALI_PI_114_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_114
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_0
+
+#define LPDDR4__DENALI_PI_115_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_115_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_115
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_6_1
+
+#define LPDDR4__DENALI_PI_116_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_116
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_0
+
+#define LPDDR4__DENALI_PI_117_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_117_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_117
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_7_1
+
+#define LPDDR4__DENALI_PI_118_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_118
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_0
+
+#define LPDDR4__DENALI_PI_119_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_119_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_119
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_8_1
+
+#define LPDDR4__DENALI_PI_120_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_0
+
+#define LPDDR4__DENALI_PI_121_READ_MASK 0x03030703U
+#define LPDDR4__DENALI_PI_121_WRITE_MASK 0x03030703U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MASK_9_1
+
+#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_SHIFT 8U
+#define LPDDR4__DENALI_PI_121__PI_BIST_MODE_WIDTH 3U
+#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_MODE
+
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_SHIFT 16U
+#define LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_ADDR_MODE
+
+#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_SHIFT 24U
+#define LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE_WIDTH 2U
+#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_121__PI_BIST_PAT_MODE
+
+#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_122
+#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_0
+
+#define LPDDR4__DENALI_PI_123_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_123
+#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_1
+
+#define LPDDR4__DENALI_PI_124_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_124_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_SHIFT 0U
+#define LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM_WIDTH 6U
+#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_124
+#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_124__PI_BIST_PAT_NUM
+
+#define LPDDR4__DENALI_PI_125_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_125
+#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_125__PI_BIST_STAGE_0
+
+#define LPDDR4__DENALI_PI_126_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_126
+#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_1
+
+#define LPDDR4__DENALI_PI_127_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_127
+#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_2
+
+#define LPDDR4__DENALI_PI_128_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_128
+#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_3
+
+#define LPDDR4__DENALI_PI_129_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_SHIFT 0U
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_129
+#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_4
+
+#define LPDDR4__DENALI_PI_130_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_SHIFT 0U
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_130
+#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_5
+
+#define LPDDR4__DENALI_PI_131_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_SHIFT 0U
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_6
+
+#define LPDDR4__DENALI_PI_132_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_SHIFT 0U
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_132
+#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_7
+
+#define LPDDR4__DENALI_PI_133_READ_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_133_WRITE_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_SHIFT 0U
+#define LPDDR4__DENALI_PI_133__PI_COL_DIFF_WIDTH 4U
+#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_133
+#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_133__PI_COL_DIFF
+
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN_WOSET 0U
+#define LPDDR4__PI_BG_ROTATE_EN__REG DENALI_PI_133
+#define LPDDR4__PI_BG_ROTATE_EN__FLD LPDDR4__DENALI_PI_133__PI_BG_ROTATE_EN
+
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_SHIFT 16U
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WIDTH 1U
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WOCLR 0U
+#define LPDDR4__DENALI_PI_133__PI_CRC_CALC_WOSET 0U
+#define LPDDR4__PI_CRC_CALC__REG DENALI_PI_133
+#define LPDDR4__PI_CRC_CALC__FLD LPDDR4__DENALI_PI_133__PI_CRC_CALC
+
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN_WOSET 0U
+#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_133
+#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_133__PI_SELF_REFRESH_EN
+
+#define LPDDR4__DENALI_PI_134_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_134_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT_WOSET 0U
+#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134
+#define LPDDR4__PI_MC_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_MC_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET 0U
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 16U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ_WOSET 0U
+#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_134
+#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_134__PI_SREF_ENTRY_REQ
+
+#define LPDDR4__DENALI_PI_135_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_135_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET 0U
+#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET 0U
+#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT_WOSET 0U
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_PI_136_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_136_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_SHIFT 0U
+#define LPDDR4__DENALI_PI_136__PI_TRST_PWRON_WIDTH 32U
+#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_136
+#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_136__PI_TRST_PWRON
+
+#define LPDDR4__DENALI_PI_137_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_SHIFT 0U
+#define LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE_WIDTH 32U
+#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_137
+#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_137__PI_CKE_INACTIVE
+
+#define LPDDR4__DENALI_PI_138_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PI_138_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_SHIFT 0U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WIDTH 1U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WOCLR 0U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_WOSET 0U
+#define LPDDR4__PI_DLL_RST__REG DENALI_PI_138
+#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_138__PI_DLL_RST
+
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN_WOSET 0U
+#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_138
+#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_138__PI_DRAM_INIT_EN
+
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_SHIFT 16U
+#define LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY_WIDTH 16U
+#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_138
+#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_138__PI_DLL_RST_DELAY
+
+#define LPDDR4__DENALI_PI_139_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_139_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_SHIFT 0U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY_WIDTH 8U
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_139
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_PI_140_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_SHIFT 0U
+#define LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG_WIDTH 26U
+#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_140
+#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_140__PI_WRITE_MODEREG
+
+#define LPDDR4__DENALI_PI_141_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_141__PI_MRW_STATUS_WIDTH 8U
+#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_141
+#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_141__PI_MRW_STATUS
+
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_SHIFT 8U
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WIDTH 1U
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WOCLR 0U
+#define LPDDR4__DENALI_PI_141__PI_RESERVED27_WOSET 0U
+#define LPDDR4__PI_RESERVED27__REG DENALI_PI_141
+#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_141__PI_RESERVED27
+
+#define LPDDR4__DENALI_PI_142_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT 0U
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH 17U
+#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142
+#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG
+
+#define LPDDR4__DENALI_PI_143_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET 0U
+#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143
+#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT
+
+#define LPDDR4__DENALI_PI_144_READ_MASK 0x01010003U
+#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x01010003U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED28_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED28_SHIFT 0U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED28_WIDTH 2U
+#define LPDDR4__PI_RESERVED28__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_144__PI_RESERVED28
+
+#define LPDDR4__DENALI_PI_144__PI_RESERVED29_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED29_SHIFT 8U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED29_WIDTH 4U
+#define LPDDR4__PI_RESERVED29__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_144__PI_RESERVED29
+
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT 16U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH 1U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR 0U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET 0U
+#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144
+#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_SHIFT 24U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WIDTH 1U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WOCLR 0U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED30_WOSET 0U
+#define LPDDR4__PI_RESERVED30__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_144__PI_RESERVED30
+
+#define LPDDR4__DENALI_PI_145_READ_MASK 0xFF010F07U
+#define LPDDR4__DENALI_PI_145_WRITE_MASK 0xFF010F07U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED31_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED31_SHIFT 0U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED31_WIDTH 3U
+#define LPDDR4__PI_RESERVED31__REG DENALI_PI_145
+#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_145__PI_RESERVED31
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH 8U
+#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0
+
+#define LPDDR4__DENALI_PI_146_READ_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH 8U
+#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2
+
+#define LPDDR4__DENALI_PI_147_READ_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH 8U
+#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3
+
+#define LPDDR4__DENALI_PI_148_READ_MASK 0xFF010FFFU
+#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFF010FFFU
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH 8U
+#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT 8U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT 16U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH 1U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR 0U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT 24U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH 8U
+#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4
+
+#define LPDDR4__DENALI_PI_149_READ_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_149_WRITE_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT 0U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT 8U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH 1U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR 0U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT 16U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH 8U
+#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT 24U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6
+
+#define LPDDR4__DENALI_PI_150_READ_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_150_WRITE_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT 0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH 1U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR 0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT 8U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH 8U
+#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT 16U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT 24U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH 1U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR 0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7
+
+#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT 0U
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH 8U
+#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151
+#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7
+
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT 0U
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH 8U
+#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152
+#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE
+
+#define LPDDR4__DENALI_PI_153_READ_MASK 0x011F1F01U
+#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x011F1F01U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT 0U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH 1U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR 0U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET 0U
+#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153
+#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK
+
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH 5U
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS
+
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT 16U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH 5U
+#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153
+#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM
+
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_SHIFT 24U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WIDTH 1U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WOCLR 0U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED32_WOSET 0U
+#define LPDDR4__PI_RESERVED32__REG DENALI_PI_153
+#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_153__PI_RESERVED32
+
+#define LPDDR4__DENALI_PI_154_READ_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT 0U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH 2U
+#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154
+#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_SHIFT 8U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WIDTH 1U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WOCLR 0U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED33_WOSET 0U
+#define LPDDR4__PI_RESERVED33__REG DENALI_PI_154
+#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_154__PI_RESERVED33
+
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET 0U
+#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154
+#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN
+
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_SHIFT 24U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WIDTH 1U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WOCLR 0U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED34_WOSET 0U
+#define LPDDR4__PI_RESERVED34__REG DENALI_PI_154
+#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_154__PI_RESERVED34
+
+#define LPDDR4__DENALI_PI_155_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH 1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET 0U
+#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_SHIFT 8U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WIDTH 1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WOCLR 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED36_WOSET 0U
+#define LPDDR4__PI_RESERVED36__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_155__PI_RESERVED36
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_SHIFT 16U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WIDTH 1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WOCLR 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED37_WOSET 0U
+#define LPDDR4__PI_RESERVED37__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_155__PI_RESERVED37
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_SHIFT 24U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WIDTH 1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WOCLR 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED38_WOSET 0U
+#define LPDDR4__PI_RESERVED38__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_155__PI_RESERVED38
+
+#define LPDDR4__DENALI_PI_156_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET 0U
+#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_SHIFT 8U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED40_WOSET 0U
+#define LPDDR4__PI_RESERVED40__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_156__PI_RESERVED40
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_SHIFT 16U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED41_WOSET 0U
+#define LPDDR4__PI_RESERVED41__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_156__PI_RESERVED41
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_SHIFT 24U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED42_WOSET 0U
+#define LPDDR4__PI_RESERVED42__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_156__PI_RESERVED42
+
+#define LPDDR4__DENALI_PI_157_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_157_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH 1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET 0U
+#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_SHIFT 8U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WIDTH 1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WOCLR 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED44_WOSET 0U
+#define LPDDR4__PI_RESERVED44__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_157__PI_RESERVED44
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_SHIFT 16U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WIDTH 1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WOCLR 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED45_WOSET 0U
+#define LPDDR4__PI_RESERVED45__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_157__PI_RESERVED45
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_SHIFT 24U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WIDTH 1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WOCLR 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED46_WOSET 0U
+#define LPDDR4__PI_RESERVED46__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_157__PI_RESERVED46
+
+#define LPDDR4__DENALI_PI_158_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH 1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET 0U
+#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_SHIFT 8U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WIDTH 1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WOCLR 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED48_WOSET 0U
+#define LPDDR4__PI_RESERVED48__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_158__PI_RESERVED48
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_SHIFT 16U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WIDTH 1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WOCLR 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED49_WOSET 0U
+#define LPDDR4__PI_RESERVED49__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_158__PI_RESERVED49
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_SHIFT 24U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WIDTH 1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WOCLR 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED50_WOSET 0U
+#define LPDDR4__PI_RESERVED50__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_158__PI_RESERVED50
+
+#define LPDDR4__DENALI_PI_159_READ_MASK 0x00FF0101U
+#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x00FF0101U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_SHIFT 0U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WIDTH 1U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WOCLR 0U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED51_WOSET 0U
+#define LPDDR4__PI_RESERVED51__REG DENALI_PI_159
+#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_159__PI_RESERVED51
+
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_SHIFT 8U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WIDTH 1U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WOCLR 0U
+#define LPDDR4__DENALI_PI_159__PI_RESERVED52_WOSET 0U
+#define LPDDR4__PI_RESERVED52__REG DENALI_PI_159
+#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_159__PI_RESERVED52
+
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT 16U
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND
+
+#define LPDDR4__DENALI_PI_160_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_160_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_SHIFT 0U
+#define LPDDR4__DENALI_PI_160__PI_TREFBW_THR_WIDTH 9U
+#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_160
+#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_160__PI_TREFBW_THR
+
+#define LPDDR4__DENALI_PI_161_READ_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_161
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_161__PI_FREQ_CHANGE_REG_COPY
+
+#define LPDDR4__DENALI_PI_162_READ_MASK 0x01031F01U
+#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x01031F01U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U
+#define LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF_WOSET 0U
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_162
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_162__PI_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PI_162__PI_RESERVED53_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_162__PI_RESERVED53_SHIFT 8U
+#define LPDDR4__DENALI_PI_162__PI_RESERVED53_WIDTH 5U
+#define LPDDR4__PI_RESERVED53__REG DENALI_PI_162
+#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_162__PI_RESERVED53
+
+#define LPDDR4__DENALI_PI_162__PI_CATR_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_162__PI_CATR_SHIFT 16U
+#define LPDDR4__DENALI_PI_162__PI_CATR_WIDTH 2U
+#define LPDDR4__PI_CATR__REG DENALI_PI_162
+#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_162__PI_CATR
+
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT 24U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH 1U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR 0U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET 0U
+#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162
+#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ
+
+#define LPDDR4__DENALI_PI_163_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_163_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_SHIFT 0U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WIDTH 1U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WOCLR 0U
+#define LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE_WOSET 0U
+#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_163
+#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_163__PI_MASK_INIT_COMPLETE
+
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_SHIFT 8U
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WIDTH 1U
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WOCLR 0U
+#define LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC_WOSET 0U
+#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_163
+#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_163__PI_DISCONNECT_MC
+
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_SHIFT 16U
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ_WOSET 0U
+#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__REG DENALI_PI_163
+#define LPDDR4__PI_DISABLE_PHYMSTR_REQ__FLD LPDDR4__DENALI_PI_163__PI_DISABLE_PHYMSTR_REQ
+
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_SHIFT 24U
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START_WOSET 0U
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_163
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_163__PI_NOTCARE_MC_INIT_START
+
+#define LPDDR4__DENALI_PI_164_READ_MASK 0x00FFFF07U
+#define LPDDR4__DENALI_PI_164_WRITE_MASK 0x00FFFF07U
+#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_SHIFT 0U
+#define LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY_WIDTH 3U
+#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__REG DENALI_PI_164
+#define LPDDR4__PI_PHYMSTR_REQ_ACK_LOOP_DELAY__FLD LPDDR4__DENALI_PI_164__PI_PHYMSTR_REQ_ACK_LOOP_DELAY
+
+#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_164__PI_TVREF_F0_WIDTH 16U
+#define LPDDR4__PI_TVREF_F0__REG DENALI_PI_164
+#define LPDDR4__PI_TVREF_F0__FLD LPDDR4__DENALI_PI_164__PI_TVREF_F0
+
+#define LPDDR4__DENALI_PI_165_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_165_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F1_WIDTH 16U
+#define LPDDR4__PI_TVREF_F1__REG DENALI_PI_165
+#define LPDDR4__PI_TVREF_F1__FLD LPDDR4__DENALI_PI_165__PI_TVREF_F1
+
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_165__PI_TVREF_F2_WIDTH 16U
+#define LPDDR4__PI_TVREF_F2__REG DENALI_PI_165
+#define LPDDR4__PI_TVREF_F2__FLD LPDDR4__DENALI_PI_165__PI_TVREF_F2
+
+#define LPDDR4__DENALI_PI_166_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F0_WIDTH 8U
+#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_166
+#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F0
+
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F1_WIDTH 8U
+#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_166
+#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F1
+
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_166__PI_TSDO_F2_WIDTH 8U
+#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_166
+#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_166__PI_TSDO_F2
+
+#define LPDDR4__DENALI_PI_167_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_167
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_167__PI_TDELAY_RDWR_2_BUS_IDLE_F0
+
+#define LPDDR4__DENALI_PI_168_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_168
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_168__PI_TDELAY_RDWR_2_BUS_IDLE_F1
+
+#define LPDDR4__DENALI_PI_169_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_169
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_169__PI_TDELAY_RDWR_2_BUS_IDLE_F2
+
+#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_169__PI_ZQINIT_F0_WIDTH 12U
+#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_169
+#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_169__PI_ZQINIT_F0
+
+#define LPDDR4__DENALI_PI_170_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F1_WIDTH 12U
+#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_170
+#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_170__PI_ZQINIT_F1
+
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_170__PI_ZQINIT_F2_WIDTH 12U
+#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_170
+#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_170__PI_ZQINIT_F2
+
+#define LPDDR4__DENALI_PI_171_READ_MASK 0xFF0F3F7FU
+#define LPDDR4__DENALI_PI_171_WRITE_MASK 0xFF0F3F7FU
+#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_171__PI_WRLAT_F0_WIDTH 7U
+#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_171
+#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_171__PI_WRLAT_F0
+
+#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0_WIDTH 6U
+#define LPDDR4__PI_ADDITIVE_LAT_F0__REG DENALI_PI_171
+#define LPDDR4__PI_ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_PI_171__PI_ADDITIVE_LAT_F0
+
+#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0_WIDTH 4U
+#define LPDDR4__PI_CA_PARITY_LAT_F0__REG DENALI_PI_171
+#define LPDDR4__PI_CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_PI_171__PI_CA_PARITY_LAT_F0
+
+#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0_WIDTH 8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__REG DENALI_PI_171
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F0__FLD LPDDR4__DENALI_PI_171__PI_TPARITY_ERROR_CMD_INHIBIT_F0
+
+#define LPDDR4__DENALI_PI_172_READ_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x0F3F7F7FU
+#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0_WIDTH 7U
+#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_172
+#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_172__PI_CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_172__PI_WRLAT_F1_WIDTH 7U
+#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_172
+#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_172__PI_WRLAT_F1
+
+#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1_WIDTH 6U
+#define LPDDR4__PI_ADDITIVE_LAT_F1__REG DENALI_PI_172
+#define LPDDR4__PI_ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_PI_172__PI_ADDITIVE_LAT_F1
+
+#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1_WIDTH 4U
+#define LPDDR4__PI_CA_PARITY_LAT_F1__REG DENALI_PI_172
+#define LPDDR4__PI_CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_PI_172__PI_CA_PARITY_LAT_F1
+
+#define LPDDR4__DENALI_PI_173_READ_MASK 0x3F7F7FFFU
+#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x3F7F7FFFU
+#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1_WIDTH 8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__REG DENALI_PI_173
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F1__FLD LPDDR4__DENALI_PI_173__PI_TPARITY_ERROR_CMD_INHIBIT_F1
+
+#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1_WIDTH 7U
+#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_173
+#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_173__PI_CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_173__PI_WRLAT_F2_WIDTH 7U
+#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_173
+#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_173__PI_WRLAT_F2
+
+#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2_WIDTH 6U
+#define LPDDR4__PI_ADDITIVE_LAT_F2__REG DENALI_PI_173
+#define LPDDR4__PI_ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_PI_173__PI_ADDITIVE_LAT_F2
+
+#define LPDDR4__DENALI_PI_174_READ_MASK 0x007FFF0FU
+#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x007FFF0FU
+#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2_WIDTH 4U
+#define LPDDR4__PI_CA_PARITY_LAT_F2__REG DENALI_PI_174
+#define LPDDR4__PI_CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_PI_174__PI_CA_PARITY_LAT_F2
+
+#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2_WIDTH 8U
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__REG DENALI_PI_174
+#define LPDDR4__PI_TPARITY_ERROR_CMD_INHIBIT_F2__FLD LPDDR4__DENALI_PI_174__PI_TPARITY_ERROR_CMD_INHIBIT_F2
+
+#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2_WIDTH 7U
+#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_174
+#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_174__PI_CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_PI_175_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_175__PI_TRFC_F0_WIDTH 10U
+#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_175
+#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_175__PI_TRFC_F0
+
+#define LPDDR4__DENALI_PI_176_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_176_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_176__PI_TREF_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_176__PI_TREF_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_176__PI_TREF_F0_WIDTH 20U
+#define LPDDR4__PI_TREF_F0__REG DENALI_PI_176
+#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_176__PI_TREF_F0
+
+#define LPDDR4__DENALI_PI_177_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_177_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_177__PI_TRFC_F1_WIDTH 10U
+#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_177
+#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_177__PI_TRFC_F1
+
+#define LPDDR4__DENALI_PI_178_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_178__PI_TREF_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_178__PI_TREF_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_178__PI_TREF_F1_WIDTH 20U
+#define LPDDR4__PI_TREF_F1__REG DENALI_PI_178
+#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_178__PI_TREF_F1
+
+#define LPDDR4__DENALI_PI_179_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_179__PI_TRFC_F2_WIDTH 10U
+#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_179
+#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_179__PI_TRFC_F2
+
+#define LPDDR4__DENALI_PI_180_READ_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_180__PI_TREF_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_180__PI_TREF_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_180__PI_TREF_F2_WIDTH 20U
+#define LPDDR4__PI_TREF_F2__REG DENALI_PI_180
+#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_180__PI_TREF_F2
+
+#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_180
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_180__PI_TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_PI_181_READ_MASK 0x03030F0FU
+#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x03030F0FU
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_181
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_181
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_181__PI_TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_181
+#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_181
+#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_WRLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_182_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_182
+#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_WRLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_182
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_182__PI_TDFI_WRLVL_WW_F0
+
+#define LPDDR4__DENALI_PI_183_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_183_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_183
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F1
+
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_183
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_183__PI_TDFI_WRLVL_WW_F2
+
+#define LPDDR4__DENALI_PI_184_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0_WIDTH 8U
+#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_184
+#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WIDTH 1U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WOCLR 0U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F0_WOSET 0U
+#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_184
+#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_184__PI_ODT_EN_F0
+
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1_WIDTH 8U
+#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_184
+#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_184__PI_TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WIDTH 1U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WOCLR 0U
+#define LPDDR4__DENALI_PI_184__PI_ODT_EN_F1_WOSET 0U
+#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_184
+#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_ODT_EN_F1
+
+#define LPDDR4__DENALI_PI_185_READ_MASK 0x0F0F01FFU
+#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x0F0F01FFU
+#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2_WIDTH 8U
+#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_185
+#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_185__PI_TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WIDTH 1U
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WOCLR 0U
+#define LPDDR4__DENALI_PI_185__PI_ODT_EN_F2_WOSET 0U
+#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_185
+#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_ODT_EN_F2
+
+#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_185__PI_ODTLON_F0_WIDTH 4U
+#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_185
+#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_185__PI_ODTLON_F0
+
+#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0_WIDTH 4U
+#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_185
+#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_185__PI_TODTON_MIN_F0
+
+#define LPDDR4__DENALI_PI_186_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F1_WIDTH 4U
+#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_186
+#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_186__PI_ODTLON_F1
+
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1_WIDTH 4U
+#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_186
+#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F1
+
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_186__PI_ODTLON_F2_WIDTH 4U
+#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_186
+#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_186__PI_ODTLON_F2
+
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2_WIDTH 4U
+#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_186
+#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_186__PI_TODTON_MIN_F2
+
+#define LPDDR4__DENALI_PI_187_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__PI_WR_TO_ODTH_F0__REG DENALI_PI_187
+#define LPDDR4__PI_WR_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__PI_WR_TO_ODTH_F1__REG DENALI_PI_187
+#define LPDDR4__PI_WR_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__PI_WR_TO_ODTH_F2__REG DENALI_PI_187
+#define LPDDR4__PI_WR_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_187__PI_WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__PI_RD_TO_ODTH_F0__REG DENALI_PI_187
+#define LPDDR4__PI_RD_TO_ODTH_F0__FLD LPDDR4__DENALI_PI_187__PI_RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_PI_188_READ_MASK 0x03033F3FU
+#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x03033F3FU
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__PI_RD_TO_ODTH_F1__REG DENALI_PI_188
+#define LPDDR4__PI_RD_TO_ODTH_F1__FLD LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__PI_RD_TO_ODTH_F2__REG DENALI_PI_188
+#define LPDDR4__PI_RD_TO_ODTH_F2__FLD LPDDR4__DENALI_PI_188__PI_RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_188
+#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_188__PI_RDLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_188
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_188__PI_RDLVL_GATE_EN_F0
+
+#define LPDDR4__DENALI_PI_189_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_189
+#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_189
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F1
+
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_189
+#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_189
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_189__PI_RDLVL_GATE_EN_F2
+
+#define LPDDR4__DENALI_PI_190_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0_WIDTH 8U
+#define LPDDR4__PI_TWR_MPR_F0__REG DENALI_PI_190
+#define LPDDR4__PI_TWR_MPR_F0__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F0
+
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1_WIDTH 8U
+#define LPDDR4__PI_TWR_MPR_F1__REG DENALI_PI_190
+#define LPDDR4__PI_TWR_MPR_F1__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F1
+
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2_WIDTH 8U
+#define LPDDR4__PI_TWR_MPR_F2__REG DENALI_PI_190
+#define LPDDR4__PI_TWR_MPR_F2__FLD LPDDR4__DENALI_PI_190__PI_TWR_MPR_F2
+
+#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_190
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_190__PI_RDLVL_PAT0_EN_F0
+
+#define LPDDR4__DENALI_PI_191_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_191
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_RXCAL_EN_F0
+
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_191
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_DFE_EN_F0
+
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_191
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_MULTI_EN_F0
+
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_191
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_RDLVL_PAT0_EN_F1
+
+#define LPDDR4__DENALI_PI_192_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_192
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_RXCAL_EN_F1
+
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_192
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_DFE_EN_F1
+
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_192
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_MULTI_EN_F1
+
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_192
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_192__PI_RDLVL_PAT0_EN_F2
+
+#define LPDDR4__DENALI_PI_193_READ_MASK 0xFF030303U
+#define LPDDR4__DENALI_PI_193_WRITE_MASK 0xFF030303U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_193
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_RXCAL_EN_F2
+
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_193
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_DFE_EN_F2
+
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_193
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_193__PI_RDLVL_MULTI_EN_F2
+
+#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0_WIDTH 8U
+#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_193
+#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_193__PI_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_194_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_194_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1_WIDTH 8U
+#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_194
+#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2_WIDTH 8U
+#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_194
+#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_194__PI_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0_WIDTH 8U
+#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_194
+#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1_WIDTH 8U
+#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_194
+#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_194__PI_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_195_READ_MASK 0x070707FFU
+#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x070707FFU
+#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2_WIDTH 8U
+#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_195
+#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_195__PI_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_MASK 0x00070000U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_MASK 0x07000000U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_195
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_195__PI_TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_PI_196_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_196
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CC_F0
+
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_196
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CALVL_CAPTURE_F0
+
+#define LPDDR4__DENALI_PI_197_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_197
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CC_F1
+
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_197
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CALVL_CAPTURE_F1
+
+#define LPDDR4__DENALI_PI_198_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CC_F2
+
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_198__PI_TDFI_CALVL_CAPTURE_F2
+
+#define LPDDR4__DENALI_PI_199_READ_MASK 0x1F030303U
+#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x1F030303U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F0
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F1
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_199__PI_CALVL_EN_F2
+
+#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_199__PI_TMRZ_F0_WIDTH 5U
+#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_199
+#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_199__PI_TMRZ_F0
+
+#define LPDDR4__DENALI_PI_200_READ_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_200__PI_TCAENT_F0_WIDTH 14U
+#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_200
+#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_200__PI_TCAENT_F0
+
+#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_200__PI_TMRZ_F1_WIDTH 5U
+#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_200
+#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_200__PI_TMRZ_F1
+
+#define LPDDR4__DENALI_PI_201_READ_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_201_WRITE_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_201__PI_TCAENT_F1_WIDTH 14U
+#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_201
+#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_201__PI_TCAENT_F1
+
+#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_201__PI_TMRZ_F2_WIDTH 5U
+#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_201
+#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_201__PI_TMRZ_F2
+
+#define LPDDR4__DENALI_PI_202_READ_MASK 0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_202_WRITE_MASK 0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_202__PI_TCAENT_F2_WIDTH 14U
+#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_202
+#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_202__PI_TCAENT_F2
+
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0_WIDTH 5U
+#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_202
+#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CACSCA_F0
+
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0_WIDTH 5U
+#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_202
+#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CASEL_F0
+
+#define LPDDR4__DENALI_PI_203_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_203_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0_WIDTH 10U
+#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_203
+#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_203__PI_TVREF_SHORT_F0
+
+#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0_WIDTH 10U
+#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_203
+#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_203__PI_TVREF_LONG_F0
+
+#define LPDDR4__DENALI_PI_204_READ_MASK 0x03FF1F1FU
+#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x03FF1F1FU
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1_WIDTH 5U
+#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_204
+#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_204__PI_TDFI_CACSCA_F1
+
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1_WIDTH 5U
+#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_204
+#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_204__PI_TDFI_CASEL_F1
+
+#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1_WIDTH 10U
+#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_204
+#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_204__PI_TVREF_SHORT_F1
+
+#define LPDDR4__DENALI_PI_205_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_PI_205_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1_WIDTH 10U
+#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_205
+#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_205__PI_TVREF_LONG_F1
+
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2_WIDTH 5U
+#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_205
+#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_205__PI_TDFI_CACSCA_F2
+
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2_WIDTH 5U
+#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_205
+#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_205__PI_TDFI_CASEL_F2
+
+#define LPDDR4__DENALI_PI_206_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_206_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2_WIDTH 10U
+#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_206
+#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_206__PI_TVREF_SHORT_F2
+
+#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2_WIDTH 10U
+#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_206
+#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_206__PI_TVREF_LONG_F2
+
+#define LPDDR4__DENALI_PI_207_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_207
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_207
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_207
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_207
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_207__PI_CALVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_208_READ_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_208
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_208
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_208
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_208
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_208__PI_CALVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_209_READ_MASK 0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_209_WRITE_MASK 0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_209
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_209__PI_CALVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_209
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_209__PI_TDFI_CALVL_STROBE_F0
+
+#define LPDDR4__DENALI_PI_209__PI_TXP_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_209__PI_TXP_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_209__PI_TXP_F0_WIDTH 5U
+#define LPDDR4__PI_TXP_F0__REG DENALI_PI_209
+#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_209__PI_TXP_F0
+
+#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0_WIDTH 8U
+#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_209
+#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_209__PI_TMRWCKEL_F0
+
+#define LPDDR4__DENALI_PI_210_READ_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_210_WRITE_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_210__PI_TCKELCK_F0_WIDTH 5U
+#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_210
+#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_210__PI_TCKELCK_F0
+
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_210
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_210__PI_TDFI_CALVL_STROBE_F1
+
+#define LPDDR4__DENALI_PI_210__PI_TXP_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_210__PI_TXP_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_210__PI_TXP_F1_WIDTH 5U
+#define LPDDR4__PI_TXP_F1__REG DENALI_PI_210
+#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_210__PI_TXP_F1
+
+#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1_WIDTH 8U
+#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_210
+#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_210__PI_TMRWCKEL_F1
+
+#define LPDDR4__DENALI_PI_211_READ_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_211_WRITE_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_211__PI_TCKELCK_F1_WIDTH 5U
+#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_211
+#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_211__PI_TCKELCK_F1
+
+#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_211
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_211__PI_TDFI_CALVL_STROBE_F2
+
+#define LPDDR4__DENALI_PI_211__PI_TXP_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_211__PI_TXP_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_211__PI_TXP_F2_WIDTH 5U
+#define LPDDR4__PI_TXP_F2__REG DENALI_PI_211
+#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_211__PI_TXP_F2
+
+#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2_WIDTH 8U
+#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_211
+#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_211__PI_TMRWCKEL_F2
+
+#define LPDDR4__DENALI_PI_212_READ_MASK 0xFFFFFF1FU
+#define LPDDR4__DENALI_PI_212_WRITE_MASK 0xFFFFFF1FU
+#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_212__PI_TCKELCK_F2_WIDTH 5U
+#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_212
+#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_212__PI_TCKELCK_F2
+
+#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_MASK 0xFFFFFF00U
+#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_212
+#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_212__PI_TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_PI_213_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_213
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_213__PI_TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_PI_214_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_214
+#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_214__PI_TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_PI_215_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_215
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_215__PI_TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_PI_216_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_216
+#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_PI_217_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_217_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2_WIDTH 24U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_217
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_217__PI_TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0_WIDTH 6U
+#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_217
+#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_217__PI_TCKEHDQS_F0
+
+#define LPDDR4__DENALI_PI_218_READ_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_218_WRITE_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_218__PI_TFC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_218__PI_TFC_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_218__PI_TFC_F0_WIDTH 10U
+#define LPDDR4__PI_TFC_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_218__PI_TFC_F0
+
+#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1_WIDTH 6U
+#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_218
+#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_218__PI_TCKEHDQS_F1
+
+#define LPDDR4__DENALI_PI_219_READ_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_219_WRITE_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_219__PI_TFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_219__PI_TFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_219__PI_TFC_F1_WIDTH 10U
+#define LPDDR4__PI_TFC_F1__REG DENALI_PI_219
+#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_219__PI_TFC_F1
+
+#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2_WIDTH 6U
+#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_219
+#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_219__PI_TCKEHDQS_F2
+
+#define LPDDR4__DENALI_PI_220_READ_MASK 0x030303FFU
+#define LPDDR4__DENALI_PI_220_WRITE_MASK 0x030303FFU
+#define LPDDR4__DENALI_PI_220__PI_TFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_220__PI_TFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_220__PI_TFC_F2_WIDTH 10U
+#define LPDDR4__PI_TFC_F2__REG DENALI_PI_220
+#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_220__PI_TFC_F2
+
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F0_WIDTH 2U
+#define LPDDR4__PI_VREF_EN_F0__REG DENALI_PI_220
+#define LPDDR4__PI_VREF_EN_F0__FLD LPDDR4__DENALI_PI_220__PI_VREF_EN_F0
+
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_220__PI_VREF_EN_F1_WIDTH 2U
+#define LPDDR4__PI_VREF_EN_F1__REG DENALI_PI_220
+#define LPDDR4__PI_VREF_EN_F1__FLD LPDDR4__DENALI_PI_220__PI_VREF_EN_F1
+
+#define LPDDR4__DENALI_PI_221_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_221_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_221__PI_VREF_EN_F2_WIDTH 2U
+#define LPDDR4__PI_VREF_EN_F2__REG DENALI_PI_221
+#define LPDDR4__PI_VREF_EN_F2__FLD LPDDR4__DENALI_PI_221__PI_VREF_EN_F2
+
+#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_221__PI_TDFI_WDQLVL_WR_F0
+
+#define LPDDR4__DENALI_PI_222_READ_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_222_WRITE_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_222
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_222__PI_TDFI_WDQLVL_RW_F0
+
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_222
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_222
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_222__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_223_READ_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_223_WRITE_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_223
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_223
+#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0_WIDTH 2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_223
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_223__PI_NTP_TRAIN_EN_F0
+
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_CL_F0__REG DENALI_PI_223
+#define LPDDR4__PI_WDQLVL_CL_F0__FLD LPDDR4__DENALI_PI_223__PI_WDQLVL_CL_F0
+
+#define LPDDR4__DENALI_PI_224_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_224_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__REG DENALI_PI_224
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_224__PI_WDQLVL_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__REG DENALI_PI_224
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_224__PI_WDQLVL_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_224__PI_TDFI_WDQLVL_WR_F1
+
+#define LPDDR4__DENALI_PI_225_READ_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_225_WRITE_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_225
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_225__PI_TDFI_WDQLVL_RW_F1
+
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_225
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_225
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_225__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_226_READ_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_226
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_226
+#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1_WIDTH 2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_226
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_226__PI_NTP_TRAIN_EN_F1
+
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_CL_F1__REG DENALI_PI_226
+#define LPDDR4__PI_WDQLVL_CL_F1__FLD LPDDR4__DENALI_PI_226__PI_WDQLVL_CL_F1
+
+#define LPDDR4__DENALI_PI_227_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_227_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__REG DENALI_PI_227
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_227__PI_WDQLVL_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__REG DENALI_PI_227
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_227__PI_WDQLVL_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_227
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_227__PI_TDFI_WDQLVL_WR_F2
+
+#define LPDDR4__DENALI_PI_228_READ_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_228_WRITE_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_228__PI_TDFI_WDQLVL_RW_F2
+
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_228
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_228
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_228__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_229_READ_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x1F03030FU
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_229
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_229
+#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2_WIDTH 2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_229
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_229__PI_NTP_TRAIN_EN_F2
+
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_CL_F2__REG DENALI_PI_229
+#define LPDDR4__PI_WDQLVL_CL_F2__FLD LPDDR4__DENALI_PI_229__PI_WDQLVL_CL_F2
+
+#define LPDDR4__DENALI_PI_230_READ_MASK 0x0303FFFFU
+#define LPDDR4__DENALI_PI_230_WRITE_MASK 0x0303FFFFU
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__REG DENALI_PI_230
+#define LPDDR4__PI_WDQLVL_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_230__PI_WDQLVL_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2_WIDTH 8U
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__REG DENALI_PI_230
+#define LPDDR4__PI_WDQLVL_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_230__PI_WDQLVL_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__REG DENALI_PI_230
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F0__FLD LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F0
+
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__REG DENALI_PI_230
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F1__FLD LPDDR4__DENALI_PI_230__PI_RD_DBI_LEVEL_EN_F1
+
+#define LPDDR4__DENALI_PI_231_READ_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PI_231_WRITE_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__REG DENALI_PI_231
+#define LPDDR4__PI_RD_DBI_LEVEL_EN_F2__FLD LPDDR4__DENALI_PI_231__PI_RD_DBI_LEVEL_EN_F2
+
+#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_231__PI_TRTP_F0_WIDTH 8U
+#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_231
+#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_231__PI_TRTP_F0
+
+#define LPDDR4__DENALI_PI_231__PI_TRP_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_231__PI_TRP_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_231__PI_TRP_F0_WIDTH 8U
+#define LPDDR4__PI_TRP_F0__REG DENALI_PI_231
+#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_231__PI_TRP_F0
+
+#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_231__PI_TRCD_F0_WIDTH 8U
+#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_231
+#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_231__PI_TRCD_F0
+
+#define LPDDR4__DENALI_PI_232_READ_MASK 0x00FF3F1FU
+#define LPDDR4__DENALI_PI_232_WRITE_MASK 0x00FF3F1FU
+#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_232__PI_TCCD_L_F0_WIDTH 5U
+#define LPDDR4__PI_TCCD_L_F0__REG DENALI_PI_232
+#define LPDDR4__PI_TCCD_L_F0__FLD LPDDR4__DENALI_PI_232__PI_TCCD_L_F0
+
+#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_232__PI_TWTR_F0_WIDTH 6U
+#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_232
+#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_232__PI_TWTR_F0
+
+#define LPDDR4__DENALI_PI_232__PI_TWR_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_232__PI_TWR_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_232__PI_TWR_F0_WIDTH 8U
+#define LPDDR4__PI_TWR_F0__REG DENALI_PI_232
+#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_232__PI_TWR_F0
+
+#define LPDDR4__DENALI_PI_233_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0_WIDTH 20U
+#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_233
+#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_233__PI_TRAS_MAX_F0
+
+#define LPDDR4__DENALI_PI_234_READ_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_234_WRITE_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0_WIDTH 9U
+#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_234
+#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_234__PI_TRAS_MIN_F0
+
+#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0_WIDTH 4U
+#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_234
+#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_234__PI_TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_234__PI_TCCDMW_F0_WIDTH 6U
+#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_234
+#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_234__PI_TCCDMW_F0
+
+#define LPDDR4__DENALI_PI_235_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_235_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_235__PI_TSR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_235__PI_TSR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_235__PI_TSR_F0_WIDTH 8U
+#define LPDDR4__PI_TSR_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TSR_F0
+
+#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_235__PI_TMRD_F0_WIDTH 8U
+#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_235__PI_TMRD_F0
+
+#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_235__PI_TMRW_F0_WIDTH 8U
+#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_235__PI_TMRW_F0
+
+#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_235__PI_TMOD_F0_WIDTH 8U
+#define LPDDR4__PI_TMOD_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TMOD_F0__FLD LPDDR4__DENALI_PI_235__PI_TMOD_F0
+
+#define LPDDR4__DENALI_PI_236_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_236_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0_WIDTH 8U
+#define LPDDR4__PI_TMOD_PAR_F0__REG DENALI_PI_236
+#define LPDDR4__PI_TMOD_PAR_F0__FLD LPDDR4__DENALI_PI_236__PI_TMOD_PAR_F0
+
+#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0_WIDTH 8U
+#define LPDDR4__PI_TMRD_PAR_F0__REG DENALI_PI_236
+#define LPDDR4__PI_TMRD_PAR_F0__FLD LPDDR4__DENALI_PI_236__PI_TMRD_PAR_F0
+
+#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_236__PI_TRTP_F1_WIDTH 8U
+#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_236
+#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_236__PI_TRTP_F1
+
+#define LPDDR4__DENALI_PI_236__PI_TRP_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_236__PI_TRP_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_236__PI_TRP_F1_WIDTH 8U
+#define LPDDR4__PI_TRP_F1__REG DENALI_PI_236
+#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_236__PI_TRP_F1
+
+#define LPDDR4__DENALI_PI_237_READ_MASK 0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_237_WRITE_MASK 0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_237__PI_TRCD_F1_WIDTH 8U
+#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_237__PI_TRCD_F1
+
+#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_237__PI_TCCD_L_F1_WIDTH 5U
+#define LPDDR4__PI_TCCD_L_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TCCD_L_F1__FLD LPDDR4__DENALI_PI_237__PI_TCCD_L_F1
+
+#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_237__PI_TWTR_F1_WIDTH 6U
+#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_237__PI_TWTR_F1
+
+#define LPDDR4__DENALI_PI_237__PI_TWR_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_237__PI_TWR_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_237__PI_TWR_F1_WIDTH 8U
+#define LPDDR4__PI_TWR_F1__REG DENALI_PI_237
+#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_237__PI_TWR_F1
+
+#define LPDDR4__DENALI_PI_238_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1_WIDTH 20U
+#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_238
+#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_238__PI_TRAS_MAX_F1
+
+#define LPDDR4__DENALI_PI_239_READ_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1_WIDTH 9U
+#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_239
+#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_239__PI_TRAS_MIN_F1
+
+#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1_WIDTH 4U
+#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_239
+#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_239__PI_TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_239__PI_TCCDMW_F1_WIDTH 6U
+#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_239
+#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_239__PI_TCCDMW_F1
+
+#define LPDDR4__DENALI_PI_240_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_240_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_240__PI_TSR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_240__PI_TSR_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_240__PI_TSR_F1_WIDTH 8U
+#define LPDDR4__PI_TSR_F1__REG DENALI_PI_240
+#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_240__PI_TSR_F1
+
+#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_240__PI_TMRD_F1_WIDTH 8U
+#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_240
+#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_240__PI_TMRD_F1
+
+#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_240__PI_TMRW_F1_WIDTH 8U
+#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_240
+#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_240__PI_TMRW_F1
+
+#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_240__PI_TMOD_F1_WIDTH 8U
+#define LPDDR4__PI_TMOD_F1__REG DENALI_PI_240
+#define LPDDR4__PI_TMOD_F1__FLD LPDDR4__DENALI_PI_240__PI_TMOD_F1
+
+#define LPDDR4__DENALI_PI_241_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_241_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1_WIDTH 8U
+#define LPDDR4__PI_TMOD_PAR_F1__REG DENALI_PI_241
+#define LPDDR4__PI_TMOD_PAR_F1__FLD LPDDR4__DENALI_PI_241__PI_TMOD_PAR_F1
+
+#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1_WIDTH 8U
+#define LPDDR4__PI_TMRD_PAR_F1__REG DENALI_PI_241
+#define LPDDR4__PI_TMRD_PAR_F1__FLD LPDDR4__DENALI_PI_241__PI_TMRD_PAR_F1
+
+#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_241__PI_TRTP_F2_WIDTH 8U
+#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_241
+#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_241__PI_TRTP_F2
+
+#define LPDDR4__DENALI_PI_241__PI_TRP_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_241__PI_TRP_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_241__PI_TRP_F2_WIDTH 8U
+#define LPDDR4__PI_TRP_F2__REG DENALI_PI_241
+#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_241__PI_TRP_F2
+
+#define LPDDR4__DENALI_PI_242_READ_MASK 0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_242_WRITE_MASK 0xFF3F1FFFU
+#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_242__PI_TRCD_F2_WIDTH 8U
+#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_242
+#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_242__PI_TRCD_F2
+
+#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_242__PI_TCCD_L_F2_WIDTH 5U
+#define LPDDR4__PI_TCCD_L_F2__REG DENALI_PI_242
+#define LPDDR4__PI_TCCD_L_F2__FLD LPDDR4__DENALI_PI_242__PI_TCCD_L_F2
+
+#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_242__PI_TWTR_F2_WIDTH 6U
+#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_242
+#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_242__PI_TWTR_F2
+
+#define LPDDR4__DENALI_PI_242__PI_TWR_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_242__PI_TWR_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_242__PI_TWR_F2_WIDTH 8U
+#define LPDDR4__PI_TWR_F2__REG DENALI_PI_242
+#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_242__PI_TWR_F2
+
+#define LPDDR4__DENALI_PI_243_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_243_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2_WIDTH 20U
+#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_243
+#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_243__PI_TRAS_MAX_F2
+
+#define LPDDR4__DENALI_PI_244_READ_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x3F0F01FFU
+#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2_WIDTH 9U
+#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_244
+#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_244__PI_TRAS_MIN_F2
+
+#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2_WIDTH 4U
+#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_244
+#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_244__PI_TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_244__PI_TCCDMW_F2_WIDTH 6U
+#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_244
+#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_244__PI_TCCDMW_F2
+
+#define LPDDR4__DENALI_PI_245_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_245_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TSR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_245__PI_TSR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_245__PI_TSR_F2_WIDTH 8U
+#define LPDDR4__PI_TSR_F2__REG DENALI_PI_245
+#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_245__PI_TSR_F2
+
+#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_245__PI_TMRD_F2_WIDTH 8U
+#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_245
+#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_245__PI_TMRD_F2
+
+#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_245__PI_TMRW_F2_WIDTH 8U
+#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_245
+#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_245__PI_TMRW_F2
+
+#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_245__PI_TMOD_F2_WIDTH 8U
+#define LPDDR4__PI_TMOD_F2__REG DENALI_PI_245
+#define LPDDR4__PI_TMOD_F2__FLD LPDDR4__DENALI_PI_245__PI_TMOD_F2
+
+#define LPDDR4__DENALI_PI_246_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2_WIDTH 8U
+#define LPDDR4__PI_TMOD_PAR_F2__REG DENALI_PI_246
+#define LPDDR4__PI_TMOD_PAR_F2__FLD LPDDR4__DENALI_PI_246__PI_TMOD_PAR_F2
+
+#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2_WIDTH 8U
+#define LPDDR4__PI_TMRD_PAR_F2__REG DENALI_PI_246
+#define LPDDR4__PI_TMRD_PAR_F2__FLD LPDDR4__DENALI_PI_246__PI_TMRD_PAR_F2
+
+#define LPDDR4__DENALI_PI_247_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_247_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_247
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_247__PI_TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_PI_248_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_248
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_248__PI_TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_PI_249_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_249_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_249
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_249__PI_TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_PI_250_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_250_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_250
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_250__PI_TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_PI_251_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_251
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_251__PI_TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_PI_252_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_252
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_252__PI_TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_PI_253_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_253_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F0_WIDTH 16U
+#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_253
+#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_253__PI_TXSR_F0
+
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_253__PI_TXSR_F1_WIDTH 16U
+#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_253
+#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_253__PI_TXSR_F1
+
+#define LPDDR4__DENALI_PI_254_READ_MASK 0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_254_WRITE_MASK 0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_254__PI_TXSR_F2_WIDTH 16U
+#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_254
+#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_254__PI_TXSR_F2
+
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F0_WIDTH 6U
+#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_254
+#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_254__PI_TEXCKE_F0
+
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_254__PI_TEXCKE_F1_WIDTH 6U
+#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_254
+#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_254__PI_TEXCKE_F1
+
+#define LPDDR4__DENALI_PI_255_READ_MASK 0x00FFFF3FU
+#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x00FFFF3FU
+#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_255__PI_TEXCKE_F2_WIDTH 6U
+#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_255
+#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_255__PI_TEXCKE_F2
+
+#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_255__PI_TDLL_F0_WIDTH 16U
+#define LPDDR4__PI_TDLL_F0__REG DENALI_PI_255
+#define LPDDR4__PI_TDLL_F0__FLD LPDDR4__DENALI_PI_255__PI_TDLL_F0
+
+#define LPDDR4__DENALI_PI_256_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_256_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F1_WIDTH 16U
+#define LPDDR4__PI_TDLL_F1__REG DENALI_PI_256
+#define LPDDR4__PI_TDLL_F1__FLD LPDDR4__DENALI_PI_256__PI_TDLL_F1
+
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_256__PI_TDLL_F2_WIDTH 16U
+#define LPDDR4__PI_TDLL_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TDLL_F2__FLD LPDDR4__DENALI_PI_256__PI_TDLL_F2
+
+#define LPDDR4__DENALI_PI_257_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_257_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F0_WIDTH 8U
+#define LPDDR4__PI_TCKSRX_F0__REG DENALI_PI_257
+#define LPDDR4__PI_TCKSRX_F0__FLD LPDDR4__DENALI_PI_257__PI_TCKSRX_F0
+
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F0_WIDTH 8U
+#define LPDDR4__PI_TCKSRE_F0__REG DENALI_PI_257
+#define LPDDR4__PI_TCKSRE_F0__FLD LPDDR4__DENALI_PI_257__PI_TCKSRE_F0
+
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRX_F1_WIDTH 8U
+#define LPDDR4__PI_TCKSRX_F1__REG DENALI_PI_257
+#define LPDDR4__PI_TCKSRX_F1__FLD LPDDR4__DENALI_PI_257__PI_TCKSRX_F1
+
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_257__PI_TCKSRE_F1_WIDTH 8U
+#define LPDDR4__PI_TCKSRE_F1__REG DENALI_PI_257
+#define LPDDR4__PI_TCKSRE_F1__FLD LPDDR4__DENALI_PI_257__PI_TCKSRE_F1
+
+#define LPDDR4__DENALI_PI_258_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_258__PI_TCKSRX_F2_WIDTH 8U
+#define LPDDR4__PI_TCKSRX_F2__REG DENALI_PI_258
+#define LPDDR4__PI_TCKSRX_F2__FLD LPDDR4__DENALI_PI_258__PI_TCKSRX_F2
+
+#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_258__PI_TCKSRE_F2_WIDTH 8U
+#define LPDDR4__PI_TCKSRE_F2__REG DENALI_PI_258
+#define LPDDR4__PI_TCKSRE_F2__FLD LPDDR4__DENALI_PI_258__PI_TCKSRE_F2
+
+#define LPDDR4__DENALI_PI_259_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_259_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_259__PI_TINIT_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_259
+#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_259__PI_TINIT_F0
+
+#define LPDDR4__DENALI_PI_260_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_260_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_260__PI_TINIT3_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_260
+#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_260__PI_TINIT3_F0
+
+#define LPDDR4__DENALI_PI_261_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_261_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_261__PI_TINIT4_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_261
+#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_261__PI_TINIT4_F0
+
+#define LPDDR4__DENALI_PI_262_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_262_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_262__PI_TINIT5_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_262
+#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_262__PI_TINIT5_F0
+
+#define LPDDR4__DENALI_PI_263_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_263_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_263__PI_TXSNR_F0_WIDTH 16U
+#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_263
+#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_263__PI_TXSNR_F0
+
+#define LPDDR4__DENALI_PI_264_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_264_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_264__PI_TINIT_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_264
+#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_264__PI_TINIT_F1
+
+#define LPDDR4__DENALI_PI_265_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_265_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_265__PI_TINIT3_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_265
+#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_265__PI_TINIT3_F1
+
+#define LPDDR4__DENALI_PI_266_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_266__PI_TINIT4_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_266
+#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_266__PI_TINIT4_F1
+
+#define LPDDR4__DENALI_PI_267_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_267__PI_TINIT5_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_267
+#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_267__PI_TINIT5_F1
+
+#define LPDDR4__DENALI_PI_268_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_268_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_268__PI_TXSNR_F1_WIDTH 16U
+#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_268
+#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_268__PI_TXSNR_F1
+
+#define LPDDR4__DENALI_PI_269_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_269_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_269__PI_TINIT_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_269
+#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_269__PI_TINIT_F2
+
+#define LPDDR4__DENALI_PI_270_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_270__PI_TINIT3_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_270
+#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_270__PI_TINIT3_F2
+
+#define LPDDR4__DENALI_PI_271_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_271__PI_TINIT4_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_271
+#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_271__PI_TINIT4_F2
+
+#define LPDDR4__DENALI_PI_272_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_272__PI_TINIT5_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_272
+#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_272__PI_TINIT5_F2
+
+#define LPDDR4__DENALI_PI_273_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_273_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_273__PI_TXSNR_F2_WIDTH 16U
+#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_273
+#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_273__PI_TXSNR_F2
+
+#define LPDDR4__DENALI_PI_273__PI_RESERVED54_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_273__PI_RESERVED54_SHIFT 16U
+#define LPDDR4__DENALI_PI_273__PI_RESERVED54_WIDTH 12U
+#define LPDDR4__PI_RESERVED54__REG DENALI_PI_273
+#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_273__PI_RESERVED54
+
+#define LPDDR4__DENALI_PI_274_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_274_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_274__PI_RESERVED55_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_274__PI_RESERVED55_SHIFT 0U
+#define LPDDR4__DENALI_PI_274__PI_RESERVED55_WIDTH 12U
+#define LPDDR4__PI_RESERVED55__REG DENALI_PI_274
+#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_274__PI_RESERVED55
+
+#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_274__PI_TZQCAL_F0_WIDTH 12U
+#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_274
+#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_274__PI_TZQCAL_F0
+
+#define LPDDR4__DENALI_PI_275_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_275_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_275__PI_TZQLAT_F0_WIDTH 7U
+#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_275
+#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_275__PI_TZQLAT_F0
+
+#define LPDDR4__DENALI_PI_275__PI_RESERVED56_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_275__PI_RESERVED56_SHIFT 8U
+#define LPDDR4__DENALI_PI_275__PI_RESERVED56_WIDTH 12U
+#define LPDDR4__PI_RESERVED56__REG DENALI_PI_275
+#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_275__PI_RESERVED56
+
+#define LPDDR4__DENALI_PI_276_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_276_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_276__PI_RESERVED57_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_276__PI_RESERVED57_SHIFT 0U
+#define LPDDR4__DENALI_PI_276__PI_RESERVED57_WIDTH 12U
+#define LPDDR4__PI_RESERVED57__REG DENALI_PI_276
+#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_276__PI_RESERVED57
+
+#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_276__PI_TZQCAL_F1_WIDTH 12U
+#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_276
+#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_276__PI_TZQCAL_F1
+
+#define LPDDR4__DENALI_PI_277_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_277_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_277__PI_TZQLAT_F1_WIDTH 7U
+#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_277
+#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_277__PI_TZQLAT_F1
+
+#define LPDDR4__DENALI_PI_277__PI_RESERVED58_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_277__PI_RESERVED58_SHIFT 8U
+#define LPDDR4__DENALI_PI_277__PI_RESERVED58_WIDTH 12U
+#define LPDDR4__PI_RESERVED58__REG DENALI_PI_277
+#define LPDDR4__PI_RESERVED58__FLD LPDDR4__DENALI_PI_277__PI_RESERVED58
+
+#define LPDDR4__DENALI_PI_278_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_278_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_278__PI_RESERVED59_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_278__PI_RESERVED59_SHIFT 0U
+#define LPDDR4__DENALI_PI_278__PI_RESERVED59_WIDTH 12U
+#define LPDDR4__PI_RESERVED59__REG DENALI_PI_278
+#define LPDDR4__PI_RESERVED59__FLD LPDDR4__DENALI_PI_278__PI_RESERVED59
+
+#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_278__PI_TZQCAL_F2_WIDTH 12U
+#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_278
+#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_278__PI_TZQCAL_F2
+
+#define LPDDR4__DENALI_PI_279_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_279_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_279__PI_TZQLAT_F2_WIDTH 7U
+#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_279
+#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_279__PI_TZQLAT_F2
+
+#define LPDDR4__DENALI_PI_279__PI_RESERVED60_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_279__PI_RESERVED60_SHIFT 8U
+#define LPDDR4__DENALI_PI_279__PI_RESERVED60_WIDTH 12U
+#define LPDDR4__PI_RESERVED60__REG DENALI_PI_279
+#define LPDDR4__PI_RESERVED60__FLD LPDDR4__DENALI_PI_279__PI_RESERVED60
+
+#define LPDDR4__DENALI_PI_280_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_280_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_280__PI_RESERVED61_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_280__PI_RESERVED61_SHIFT 0U
+#define LPDDR4__DENALI_PI_280__PI_RESERVED61_WIDTH 12U
+#define LPDDR4__PI_RESERVED61__REG DENALI_PI_280
+#define LPDDR4__PI_RESERVED61__FLD LPDDR4__DENALI_PI_280__PI_RESERVED61
+
+#define LPDDR4__DENALI_PI_280__PI_RESERVED62_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_280__PI_RESERVED62_SHIFT 16U
+#define LPDDR4__DENALI_PI_280__PI_RESERVED62_WIDTH 12U
+#define LPDDR4__PI_RESERVED62__REG DENALI_PI_280
+#define LPDDR4__PI_RESERVED62__FLD LPDDR4__DENALI_PI_280__PI_RESERVED62
+
+#define LPDDR4__DENALI_PI_281_READ_MASK 0x030F0F0FU
+#define LPDDR4__DENALI_PI_281_WRITE_MASK 0x030F0F0FU
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_281
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F0
+
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_281
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F1
+
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_281
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_281__PI_WDQ_OSC_DELTA_INDEX_F2
+
+#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0_WIDTH 2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__REG DENALI_PI_281
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_PI_281__PI_PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_PI_282_READ_MASK 0x07070303U
+#define LPDDR4__DENALI_PI_282_WRITE_MASK 0x07070303U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1_WIDTH 2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__REG DENALI_PI_282
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2_WIDTH 2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__REG DENALI_PI_282
+#define LPDDR4__PI_PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_PI_282__PI_PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_MASK 0x00070000U
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0_WIDTH 3U
+#define LPDDR4__PI_MEMDATA_RATIO_0__REG DENALI_PI_282
+#define LPDDR4__PI_MEMDATA_RATIO_0__FLD LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1_WIDTH 3U
+#define LPDDR4__PI_MEMDATA_RATIO_1__REG DENALI_PI_282
+#define LPDDR4__PI_MEMDATA_RATIO_1__FLD LPDDR4__DENALI_PI_282__PI_MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_PI_283_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_283_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_SHIFT 0U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0_WIDTH 2U
+#define LPDDR4__PI_ODT_RD_MAP_CS0__REG DENALI_PI_283
+#define LPDDR4__PI_ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_SHIFT 8U
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0_WIDTH 2U
+#define LPDDR4__PI_ODT_WR_MAP_CS0__REG DENALI_PI_283
+#define LPDDR4__PI_ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_SHIFT 16U
+#define LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1_WIDTH 2U
+#define LPDDR4__PI_ODT_RD_MAP_CS1__REG DENALI_PI_283
+#define LPDDR4__PI_ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_PI_283__PI_ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_SHIFT 24U
+#define LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1_WIDTH 2U
+#define LPDDR4__PI_ODT_WR_MAP_CS1__REG DENALI_PI_283
+#define LPDDR4__PI_ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_PI_283__PI_ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_PI_284_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_284_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV0_0__REG DENALI_PI_284
+#define LPDDR4__PI_VREF_VAL_DEV0_0__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_0
+
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV0_1__REG DENALI_PI_284
+#define LPDDR4__PI_VREF_VAL_DEV0_1__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV0_1
+
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV1_0__REG DENALI_PI_284
+#define LPDDR4__PI_VREF_VAL_DEV1_0__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_0
+
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1_WIDTH 7U
+#define LPDDR4__PI_VREF_VAL_DEV1_1__REG DENALI_PI_284
+#define LPDDR4__PI_VREF_VAL_DEV1_1__FLD LPDDR4__DENALI_PI_284__PI_VREF_VAL_DEV1_1
+
+#define LPDDR4__DENALI_PI_285_READ_MASK 0x3F3F0303U
+#define LPDDR4__DENALI_PI_285_WRITE_MASK 0x3F3F0303U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0_WIDTH 2U
+#define LPDDR4__PI_SLICE_PER_DEV_0__REG DENALI_PI_285
+#define LPDDR4__PI_SLICE_PER_DEV_0__FLD LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_0
+
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1_WIDTH 2U
+#define LPDDR4__PI_SLICE_PER_DEV_1__REG DENALI_PI_285
+#define LPDDR4__PI_SLICE_PER_DEV_1__FLD LPDDR4__DENALI_PI_285__PI_SLICE_PER_DEV_1
+
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_0_0__REG DENALI_PI_285
+#define LPDDR4__PI_MR6_VREF_0_0__FLD LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_0
+
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_0_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR6_VREF_0_1__FLD LPDDR4__DENALI_PI_285__PI_MR6_VREF_0_1
+
+#define LPDDR4__DENALI_PI_286_READ_MASK 0xFFFF3F3FU
+#define LPDDR4__DENALI_PI_286_WRITE_MASK 0xFFFF3F3FU
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_1_0__REG DENALI_PI_286
+#define LPDDR4__PI_MR6_VREF_1_0__FLD LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_0
+
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1_WIDTH 6U
+#define LPDDR4__PI_MR6_VREF_1_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR6_VREF_1_1__FLD LPDDR4__DENALI_PI_286__PI_MR6_VREF_1_1
+
+#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_286__PI_MR13_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_286
+#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_286__PI_MR13_DATA_0
+
+#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_286__PI_MR15_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_286
+#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_286__PI_MR15_DATA_0
+
+#define LPDDR4__DENALI_PI_287_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_287_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_287__PI_MR16_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_287
+#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR16_DATA_0
+
+#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_287__PI_MR17_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_287
+#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR17_DATA_0
+
+#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_287__PI_MR20_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_287
+#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_287__PI_MR20_DATA_0
+
+#define LPDDR4__DENALI_PI_288_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_288_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_288__PI_MR32_DATA_0_WIDTH 17U
+#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_288
+#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_288__PI_MR32_DATA_0
+
+#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_288__PI_MR40_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_288
+#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_288__PI_MR40_DATA_0
+
+#define LPDDR4__DENALI_PI_289_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_289_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_289__PI_MR13_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_289
+#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR13_DATA_1
+
+#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_289__PI_MR15_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_289
+#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR15_DATA_1
+
+#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_289__PI_MR16_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_289
+#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR16_DATA_1
+
+#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_289__PI_MR17_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_289
+#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_289__PI_MR17_DATA_1
+
+#define LPDDR4__DENALI_PI_290_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_290_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_290__PI_MR20_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_290
+#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_290__PI_MR20_DATA_1
+
+#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_290__PI_MR32_DATA_1_WIDTH 17U
+#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_290
+#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_290__PI_MR32_DATA_1
+
+#define LPDDR4__DENALI_PI_291_READ_MASK 0x1F1F1FFFU
+#define LPDDR4__DENALI_PI_291_WRITE_MASK 0x1F1F1FFFU
+#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_291__PI_MR40_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_291
+#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_291__PI_MR40_DATA_1
+
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_0_WIDTH 5U
+#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_291
+#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_291__PI_CKE_MUX_0
+
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_291__PI_CKE_MUX_1_WIDTH 5U
+#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_291
+#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_291__PI_CKE_MUX_1
+
+#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_291__PI_CS_MUX_0_WIDTH 5U
+#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_291
+#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_291__PI_CS_MUX_0
+
+#define LPDDR4__DENALI_PI_292_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_292_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_292__PI_CS_MUX_1_WIDTH 5U
+#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_292
+#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_292__PI_CS_MUX_1
+
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_0_WIDTH 5U
+#define LPDDR4__PI_ODT_MUX_0__REG DENALI_PI_292
+#define LPDDR4__PI_ODT_MUX_0__FLD LPDDR4__DENALI_PI_292__PI_ODT_MUX_0
+
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_292__PI_ODT_MUX_1_WIDTH 5U
+#define LPDDR4__PI_ODT_MUX_1__REG DENALI_PI_292
+#define LPDDR4__PI_ODT_MUX_1__FLD LPDDR4__DENALI_PI_292__PI_ODT_MUX_1
+
+#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0_WIDTH 5U
+#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_292
+#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_292__PI_RESET_N_MUX_0
+
+#define LPDDR4__DENALI_PI_293_READ_MASK 0x01FFFF1FU
+#define LPDDR4__DENALI_PI_293_WRITE_MASK 0x01FFFF1FU
+#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1_WIDTH 5U
+#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_293
+#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_293__PI_RESET_N_MUX_1
+
+#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0_WIDTH 17U
+#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_293
+#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_293__PI_MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_PI_294_READ_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_PI_294_WRITE_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1_WIDTH 17U
+#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_294
+#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_294__PI_MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0_WIDTH 2U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_294
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_294__PI_ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_PI_295_READ_MASK 0x00030303U
+#define LPDDR4__DENALI_PI_295_WRITE_MASK 0x00030303U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 2U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_295
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1_WIDTH 2U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_295
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 2U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_295
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_295__PI_ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_PI_296_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_296_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_296
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_0
+
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_296
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_296__PI_DQS_OSC_BASE_VALUE_0_1
+
+#define LPDDR4__DENALI_PI_297_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_297_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F0_0__REG DENALI_PI_297
+#define LPDDR4__PI_MR0_DATA_F0_0__FLD LPDDR4__DENALI_PI_297__PI_MR0_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_298_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_298_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_298
+#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_298__PI_MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_299_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_299
+#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_299__PI_MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_300_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_300_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_300
+#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_300__PI_MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_301_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_301_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F0_0__REG DENALI_PI_301
+#define LPDDR4__PI_MR4_DATA_F0_0__FLD LPDDR4__DENALI_PI_301__PI_MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_302_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_302_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F0_0__REG DENALI_PI_302
+#define LPDDR4__PI_MR5_DATA_F0_0__FLD LPDDR4__DENALI_PI_302__PI_MR5_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_303_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_303_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F0_0__REG DENALI_PI_303
+#define LPDDR4__PI_MR6_DATA_F0_0__FLD LPDDR4__DENALI_PI_303__PI_MR6_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_303
+#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_303__PI_MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_304_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_304_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_304
+#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_304__PI_MR23_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_305_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_305_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F1_0__REG DENALI_PI_305
+#define LPDDR4__PI_MR0_DATA_F1_0__FLD LPDDR4__DENALI_PI_305__PI_MR0_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_306_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_306_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_306
+#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_306__PI_MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_307_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_307_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_307
+#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_307__PI_MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_308_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_308_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_308
+#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_308__PI_MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_309_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_309_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F1_0__REG DENALI_PI_309
+#define LPDDR4__PI_MR4_DATA_F1_0__FLD LPDDR4__DENALI_PI_309__PI_MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_310_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_310_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F1_0__REG DENALI_PI_310
+#define LPDDR4__PI_MR5_DATA_F1_0__FLD LPDDR4__DENALI_PI_310__PI_MR5_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_311_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_311_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F1_0__REG DENALI_PI_311
+#define LPDDR4__PI_MR6_DATA_F1_0__FLD LPDDR4__DENALI_PI_311__PI_MR6_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_311
+#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_311__PI_MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_312_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_312_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_312
+#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_312
+#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_312
+#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_312
+#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_312__PI_MR23_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_313_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_313_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F2_0__REG DENALI_PI_313
+#define LPDDR4__PI_MR0_DATA_F2_0__FLD LPDDR4__DENALI_PI_313__PI_MR0_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_314_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_314_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_314
+#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_314__PI_MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_315_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_315_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_315
+#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_315__PI_MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_316_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_316_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_316
+#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_316__PI_MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_317_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_317_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F2_0__REG DENALI_PI_317
+#define LPDDR4__PI_MR4_DATA_F2_0__FLD LPDDR4__DENALI_PI_317__PI_MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_318_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_318_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F2_0__REG DENALI_PI_318
+#define LPDDR4__PI_MR5_DATA_F2_0__FLD LPDDR4__DENALI_PI_318__PI_MR5_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_319_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_319_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F2_0__REG DENALI_PI_319
+#define LPDDR4__PI_MR6_DATA_F2_0__FLD LPDDR4__DENALI_PI_319__PI_MR6_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_319
+#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_319__PI_MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_320_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_320_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_320
+#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_320
+#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_320
+#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_320
+#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_320__PI_MR23_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_321_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_321_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F0_1__REG DENALI_PI_321
+#define LPDDR4__PI_MR0_DATA_F0_1__FLD LPDDR4__DENALI_PI_321__PI_MR0_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_322_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_322_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_322
+#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_322__PI_MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_323_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_323_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_323
+#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_323__PI_MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_324_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_324_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_324
+#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_324__PI_MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_325_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_325_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F0_1__REG DENALI_PI_325
+#define LPDDR4__PI_MR4_DATA_F0_1__FLD LPDDR4__DENALI_PI_325__PI_MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_326_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_326_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F0_1__REG DENALI_PI_326
+#define LPDDR4__PI_MR5_DATA_F0_1__FLD LPDDR4__DENALI_PI_326__PI_MR5_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_327_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_327_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F0_1__REG DENALI_PI_327
+#define LPDDR4__PI_MR6_DATA_F0_1__FLD LPDDR4__DENALI_PI_327__PI_MR6_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_327
+#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_327__PI_MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_328_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_328_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_328
+#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_328
+#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_328
+#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_328
+#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_328__PI_MR23_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_329_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_329_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F1_1__REG DENALI_PI_329
+#define LPDDR4__PI_MR0_DATA_F1_1__FLD LPDDR4__DENALI_PI_329__PI_MR0_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_330_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_330_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_330
+#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_330__PI_MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_331_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_331_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_331
+#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_331__PI_MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_332_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_332_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_332
+#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_332__PI_MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_333_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_333_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F1_1__REG DENALI_PI_333
+#define LPDDR4__PI_MR4_DATA_F1_1__FLD LPDDR4__DENALI_PI_333__PI_MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_334_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_334_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F1_1__REG DENALI_PI_334
+#define LPDDR4__PI_MR5_DATA_F1_1__FLD LPDDR4__DENALI_PI_334__PI_MR5_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_335_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_335_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F1_1__REG DENALI_PI_335
+#define LPDDR4__PI_MR6_DATA_F1_1__FLD LPDDR4__DENALI_PI_335__PI_MR6_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_335
+#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_335__PI_MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_336_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_336_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_336
+#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_336
+#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_336
+#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_336
+#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_336__PI_MR23_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_337_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_337_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR0_DATA_F2_1__REG DENALI_PI_337
+#define LPDDR4__PI_MR0_DATA_F2_1__FLD LPDDR4__DENALI_PI_337__PI_MR0_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_338_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_338_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_338
+#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_338__PI_MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_339_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_339_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_339
+#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_339__PI_MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_340_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_340_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_340
+#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_340__PI_MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_341_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_341_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR4_DATA_F2_1__REG DENALI_PI_341
+#define LPDDR4__PI_MR4_DATA_F2_1__FLD LPDDR4__DENALI_PI_341__PI_MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_342_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_342_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR5_DATA_F2_1__REG DENALI_PI_342
+#define LPDDR4__PI_MR5_DATA_F2_1__FLD LPDDR4__DENALI_PI_342__PI_MR5_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_343_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_343_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1_WIDTH 17U
+#define LPDDR4__PI_MR6_DATA_F2_1__REG DENALI_PI_343
+#define LPDDR4__PI_MR6_DATA_F2_1__FLD LPDDR4__DENALI_PI_343__PI_MR6_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_343
+#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_343__PI_MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_344_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_344_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_344
+#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_344
+#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_344
+#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_344
+#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_344__PI_MR23_DATA_F2_1
+
+#endif /* REG_LPDDR4_PI_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
new file mode 100644
index 0000000..f14ca24
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_IF_H
+#define LPDDR4_32BIT_IF_H
+
+#include <linux/types.h>
+
+#define LPDDR4_INTR_MAX_CS (2U)
+
+#define LPDDR4_INTR_CTL_REG_COUNT (459U)
+
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (300U)
+
+#define LPDDR4_INTR_PHY_REG_COUNT (1423U)
+
+typedef enum {
+ LPDDR4_INTR_RESET_DONE = 0U,
+ LPDDR4_INTR_BUS_ACCESS_ERROR = 1U,
+ LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR = 2U,
+ LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR = 3U,
+ LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR = 4U,
+ LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR = 5U,
+ LPDDR4_INTR_ECC_SCRUB_DONE = 6U,
+ LPDDR4_INTR_ECC_SCRUB_ERROR = 7U,
+ LPDDR4_INTR_PORT_COMMAND_ERROR = 8U,
+ LPDDR4_INTR_MC_INIT_DONE = 9U,
+ LPDDR4_INTR_LP_DONE = 10U,
+ LPDDR4_INTR_BIST_DONE = 11U,
+ LPDDR4_INTR_WRAP_ERROR = 12U,
+ LPDDR4_INTR_INVALID_BURST_ERROR = 13U,
+ LPDDR4_INTR_RDLVL_ERROR = 14U,
+ LPDDR4_INTR_RDLVL_GATE_ERROR = 15U,
+ LPDDR4_INTR_WRLVL_ERROR = 16U,
+ LPDDR4_INTR_CA_TRAINING_ERROR = 17U,
+ LPDDR4_INTR_DFI_UPDATE_ERROR = 18U,
+ LPDDR4_INTR_MRR_ERROR = 19U,
+ LPDDR4_INTR_PHY_MASTER_ERROR = 20U,
+ LPDDR4_INTR_WRLVL_REQ = 21U,
+ LPDDR4_INTR_RDLVL_REQ = 22U,
+ LPDDR4_INTR_RDLVL_GATE_REQ = 23U,
+ LPDDR4_INTR_CA_TRAINING_REQ = 24U,
+ LPDDR4_INTR_LEVELING_DONE = 25U,
+ LPDDR4_INTR_PHY_ERROR = 26U,
+ LPDDR4_INTR_MR_READ_DONE = 27U,
+ LPDDR4_INTR_TEMP_CHANGE = 28U,
+ LPDDR4_INTR_TEMP_ALERT = 29U,
+ LPDDR4_INTR_SW_DQS_COMPLETE = 30U,
+ LPDDR4_INTR_DQS_OSC_BV_UPDATED = 31U,
+ LPDDR4_INTR_DQS_OSC_OVERFLOW = 32U,
+ LPDDR4_INTR_DQS_OSC_VAR_OUT = 33U,
+ LPDDR4_INTR_MR_WRITE_DONE = 34U,
+ LPDDR4_INTR_INHIBIT_DRAM_DONE = 35U,
+ LPDDR4_INTR_DFI_INIT_STATE = 36U,
+ LPDDR4_INTR_DLL_RESYNC_DONE = 37U,
+ LPDDR4_INTR_TDFI_TO = 38U,
+ LPDDR4_INTR_DFS_DONE = 39U,
+ LPDDR4_INTR_DFS_STATUS = 40U,
+ LPDDR4_INTR_REFRESH_STATUS = 41U,
+ LPDDR4_INTR_ZQ_STATUS = 42U,
+ LPDDR4_INTR_SW_REQ_MODE = 43U,
+ LPDDR4_INTR_LOR_BITS = 44U
+} lpddr4_intr_ctlinterrupt;
+
+typedef enum {
+ LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U,
+ LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
+ LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 4U,
+ LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
+ LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 6U,
+ LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
+ LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 9U,
+ LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
+ LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 11U,
+ LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 12U,
+ LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
+ LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 14U,
+ LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 15U,
+ LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
+ LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
+} lpddr4_intr_phyindepinterrupt;
+
+#endif /* LPDDR4_32BIT_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
new file mode 100644
index 0000000..7fee54f
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_OBJ_IF_H
+#define LPDDR4_32BIT_OBJ_IF_H
+
+#include "lpddr4_32bit_if.h"
+
+#endif /* LPDDR4_32BIT_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
new file mode 100644
index 0000000..69b2a47
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_STRUCTS_IF_H
+#define LPDDR4_32BIT_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_32bit_if.h"
+
+#endif /* LPDDR4_32BIT_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
similarity index 76%
rename from drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
rename to drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
index bc8059e..58ba340 100644
--- a/drivers/ram/k3-j721e/lpddr4_address_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
@@ -1,17 +1,16 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
*
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
-#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
-#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1024_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1024_WRITE_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
@@ -32,16 +31,16 @@
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_1024
#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_0
-#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_1025
#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_0
-#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
@@ -60,8 +59,8 @@
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_1026
#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
-#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
-#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027_READ_MASK 0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027_WRITE_MASK 0xFF7F07FFU
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH 11U
@@ -80,8 +79,8 @@
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_1027
#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
-#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
-#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1028_READ_MASK 0x01000707U
+#define LPDDR4__DENALI_PHY_1028_WRITE_MASK 0x01000707U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
@@ -103,18 +102,18 @@
#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_0
#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0_WOSET 0U
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_1028
#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_0
-#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
-#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029_READ_MASK 0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029_WRITE_MASK 0x011F7F7FU
#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0_WIDTH 7U
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_0
@@ -138,8 +137,8 @@
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_1029
#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_0
-#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
-#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1030_READ_MASK 0x01070301U
+#define LPDDR4__DENALI_PHY_1030_WRITE_MASK 0x01070301U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
@@ -148,9 +147,9 @@
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0_WIDTH 2U
#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_0
@@ -161,50 +160,50 @@
#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_0
#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0_WOSET 0U
#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_1030
#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_0
-#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0_WIDTH 27U
#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_1031
#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_0
-#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1032_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1032_WRITE_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_1032
#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_0
-#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_1033
#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_0
-#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_1034
#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
-#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_1035
#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_0
@@ -214,24 +213,24 @@
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_1035
#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_0
-#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1036_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1036_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0_WIDTH 11U
#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_1036
#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_0
-#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH 24U
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_1037
#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_0
-#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038_WRITE_MASK 0x03FFFFFFU
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH 24U
@@ -244,8 +243,8 @@
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_1038
#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_0
-#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
-#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039_READ_MASK 0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039_WRITE_MASK 0x01FF0F03U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH 2U
@@ -264,8 +263,8 @@
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_1039
#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
-#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
-#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1040_READ_MASK 0x07000001U
+#define LPDDR4__DENALI_PHY_1040_WRITE_MASK 0x07000001U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH 1U
@@ -296,112 +295,112 @@
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_1040
#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_0
-#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__REG DENALI_PHY_1041
#define LPDDR4__PHY_ADR_CALVL_CH0_OBS0_0__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_CH0_OBS0_0
-#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__REG DENALI_PHY_1042
#define LPDDR4__PHY_ADR_CALVL_CH1_OBS0_0__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_CH1_OBS0_0
-#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_1043
#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS1_0
-#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1044_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0_WIDTH 32U
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_1044
#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_OBS2_0
-#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_1045
#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_FG_0_0
-#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_1046
#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_BG_0_0
-#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_1047
#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_FG_1_0
-#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_1048
#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_BG_1_0
-#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_1049
#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_FG_2_0
-#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_1050
#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_BG_2_0
-#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_1051
#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_FG_3_0
-#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1052_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0_WIDTH 20U
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_1052
#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_CALVL_BG_3_0
-#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1053_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1053_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 24U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0_WIDTH 24U
#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_1053
#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_ADDR_SEL_0
-#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU
-#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1054_READ_MASK 0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1054_WRITE_MASK 0x3F3F03FFU
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH 10U
@@ -409,19 +408,19 @@
#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_LP4_BOOT_SLV_DELAY_0
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_BIT_MASK_0
#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_1054
#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SEG_MASK_0
-#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU
-#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1055_READ_MASK 0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1055_WRITE_MASK 0x3F0F3F3FU
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH 6U
@@ -441,13 +440,13 @@
#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_STATIC_TOG_DISABLE_0
#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_1055
#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXIO_CTRL_0
-#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U
-#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1056_READ_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_PHY_1056_WRITE_MASK 0xFFFFFF03U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_INIT_DISABLE_0_WIDTH 2U
@@ -472,8 +471,8 @@
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__REG DENALI_PHY_1056
#define LPDDR4__PHY_ADR_DC_ADR2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_DC_ADR2_CLK_ADJUST_0
-#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1057_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1057_WRITE_MASK 0x01FFFFFFU
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1057__PHY_ADR_DC_ADR3_CLK_ADJUST_0_WIDTH 8U
@@ -500,8 +499,8 @@
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_1057
#define LPDDR4__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0
-#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU
-#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1058_READ_MASK 0x3F03FFFFU
+#define LPDDR4__DENALI_PHY_1058_WRITE_MASK 0x3F03FFFFU
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_SAMPLE_WAIT_0_WIDTH 8U
@@ -515,8 +514,8 @@
#define LPDDR4__PHY_ADR_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_CAL_TIMEOUT_0
#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0_WIDTH 2U
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_WEIGHT_0
@@ -526,8 +525,8 @@
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__REG DENALI_PHY_1058
#define LPDDR4__PHY_ADR_DC_ADJUST_START_0__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR_DC_ADJUST_START_0
-#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1059_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1059_WRITE_MASK 0x0101FFFFU
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_ADJUST_SAMPLE_CNT_0_WIDTH 8U
@@ -556,19 +555,19 @@
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__REG DENALI_PHY_1059
#define LPDDR4__PHY_ADR_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR_DC_CAL_POLARITY_0
-#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x07FF3F01U
-#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x07FF3F01U
+#define LPDDR4__DENALI_PHY_1060_READ_MASK 0x07FF3F01U
+#define LPDDR4__DENALI_PHY_1060_WRITE_MASK 0x07FF3F01U
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0_WOSET 0U
#define LPDDR4__PHY_ADR_DC_CAL_START_0__REG DENALI_PHY_1060
#define LPDDR4__PHY_ADR_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_DC_CAL_START_0
#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH 6U
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_1060
#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR_SW_TXPWR_CTRL_0
@@ -578,11 +577,11 @@
#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__REG DENALI_PHY_1060
#define LPDDR4__PHY_PARITY_ERROR_REGIF_ADR_0__FLD LPDDR4__DENALI_PHY_1060__PHY_PARITY_ERROR_REGIF_ADR_0
-#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_1061_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_1061_WRITE_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0_WIDTH 9U
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__REG DENALI_PHY_1061
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_0
@@ -592,8 +591,8 @@
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__REG DENALI_PHY_1061
#define LPDDR4__PHY_AS_FSM_ERROR_INFO_MASK_0__FLD LPDDR4__DENALI_PHY_1061__PHY_AS_FSM_ERROR_INFO_MASK_0
-#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x01010000U
-#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x01010000U
+#define LPDDR4__DENALI_PHY_1062_READ_MASK 0x01010000U
+#define LPDDR4__DENALI_PHY_1062_WRITE_MASK 0x01010000U
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1062__SC_PHY_AS_FSM_ERROR_INFO_WOCLR_0_WIDTH 9U
@@ -624,11 +623,11 @@
#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1063
#define LPDDR4__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1063__SC_PHY_AS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
-#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1064_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1064_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0_WIDTH 8U
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_1064
#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_TSEL_SELECT_0
@@ -639,13 +638,13 @@
#define LPDDR4__PHY_ADR_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_DC_CAL_CLK_SEL_0
#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0_WIDTH 11U
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_1064
#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1064__PHY_PAD_ADR_IO_CFG_0
-#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x1F07FF1FU
-#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1065_READ_MASK 0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1065_WRITE_MASK 0x1F07FF1FU
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1065__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH 5U
@@ -664,8 +663,8 @@
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1065
#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR1_SW_WRADDR_SHIFT_0
-#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU
-#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1066_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1066_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1066__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@@ -678,8 +677,8 @@
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1066
#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR2_SW_WRADDR_SHIFT_0
-#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x001F07FFU
-#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1067_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1067_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1067__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@@ -692,8 +691,8 @@
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1067
#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1067__PHY_ADR3_SW_WRADDR_SHIFT_0
-#define LPDDR4__DENALI_PHY_1068_READ_MASK 0x001F07FFU
-#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1068_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1068_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1068__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@@ -706,8 +705,8 @@
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1068
#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1068__PHY_ADR4_SW_WRADDR_SHIFT_0
-#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x001F07FFU
-#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1069_READ_MASK 0x001F07FFU
+#define LPDDR4__DENALI_PHY_1069_WRITE_MASK 0x001F07FFU
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1069__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@@ -720,8 +719,8 @@
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_1069
#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_1069__PHY_ADR5_SW_WRADDR_SHIFT_0
-#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x000F07FFU
-#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1070_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_1070_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1070__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH 11U
@@ -734,8 +733,8 @@
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_1070
#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_1070__PHY_ADR_SW_MASTER_MODE_0
-#define LPDDR4__DENALI_PHY_1071_READ_MASK 0xFF3F07FFU
-#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1071_READ_MASK 0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1071_WRITE_MASK 0xFF3F07FFU
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_START_0_WIDTH 11U
@@ -754,8 +753,8 @@
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_1071
#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_1071__PHY_ADR_MASTER_DELAY_WAIT_0
-#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1072_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1072_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1072__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH 8U
@@ -776,16 +775,16 @@
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_1072
#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_1072__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
-#define LPDDR4__DENALI_PHY_1073_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_1073_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1073_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1073_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0_WIDTH 4U
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_1073
#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_1073__PHY_ADR_CALVL_DLY_STEP_0
-#define LPDDR4__DENALI_PHY_1074_READ_MASK 0x03FF010FU
-#define LPDDR4__DENALI_PHY_1074_WRITE_MASK 0x03FF010FU
+#define LPDDR4__DENALI_PHY_1074_READ_MASK 0x03FF010FU
+#define LPDDR4__DENALI_PHY_1074_WRITE_MASK 0x03FF010FU
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1074__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH 4U
@@ -806,8 +805,8 @@
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__REG DENALI_PHY_1074
#define LPDDR4__PHY_ADR_DC_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_1074__PHY_ADR_DC_INIT_SLV_DELAY_0
-#define LPDDR4__DENALI_PHY_1075_READ_MASK 0x0000FF01U
-#define LPDDR4__DENALI_PHY_1075_WRITE_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1075_READ_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PHY_1075_WRITE_MASK 0x0000FF01U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1075__PHY_ADR_DC_CALVL_ENABLE_0_WIDTH 1U
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
new file mode 100644
index 0000000..4113608
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
@@ -0,0 +1,1545 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_CTL_REGS_H_
+#define REG_LPDDR4_CTL_REGS_H_
+
+#include "lpddr4_ddr_controller_macros.h"
+#include "lpddr4_pi_macros.h"
+#include "lpddr4_data_slice_0_macros.h"
+#include "lpddr4_data_slice_1_macros.h"
+#include "lpddr4_data_slice_2_macros.h"
+#include "lpddr4_data_slice_3_macros.h"
+#include "lpddr4_address_slice_0_macros.h"
+#include "lpddr4_phy_core_macros.h"
+
+typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
+ volatile u32 DENALI_CTL_0;
+ volatile u32 DENALI_CTL_1;
+ volatile u32 DENALI_CTL_2;
+ volatile u32 DENALI_CTL_3;
+ volatile u32 DENALI_CTL_4;
+ volatile u32 DENALI_CTL_5;
+ volatile u32 DENALI_CTL_6;
+ volatile u32 DENALI_CTL_7;
+ volatile u32 DENALI_CTL_8;
+ volatile u32 DENALI_CTL_9;
+ volatile u32 DENALI_CTL_10;
+ volatile u32 DENALI_CTL_11;
+ volatile u32 DENALI_CTL_12;
+ volatile u32 DENALI_CTL_13;
+ volatile u32 DENALI_CTL_14;
+ volatile u32 DENALI_CTL_15;
+ volatile u32 DENALI_CTL_16;
+ volatile u32 DENALI_CTL_17;
+ volatile u32 DENALI_CTL_18;
+ volatile u32 DENALI_CTL_19;
+ volatile u32 DENALI_CTL_20;
+ volatile u32 DENALI_CTL_21;
+ volatile u32 DENALI_CTL_22;
+ volatile u32 DENALI_CTL_23;
+ volatile u32 DENALI_CTL_24;
+ volatile u32 DENALI_CTL_25;
+ volatile u32 DENALI_CTL_26;
+ volatile u32 DENALI_CTL_27;
+ volatile u32 DENALI_CTL_28;
+ volatile u32 DENALI_CTL_29;
+ volatile u32 DENALI_CTL_30;
+ volatile u32 DENALI_CTL_31;
+ volatile u32 DENALI_CTL_32;
+ volatile u32 DENALI_CTL_33;
+ volatile u32 DENALI_CTL_34;
+ volatile u32 DENALI_CTL_35;
+ volatile u32 DENALI_CTL_36;
+ volatile u32 DENALI_CTL_37;
+ volatile u32 DENALI_CTL_38;
+ volatile u32 DENALI_CTL_39;
+ volatile u32 DENALI_CTL_40;
+ volatile u32 DENALI_CTL_41;
+ volatile u32 DENALI_CTL_42;
+ volatile u32 DENALI_CTL_43;
+ volatile u32 DENALI_CTL_44;
+ volatile u32 DENALI_CTL_45;
+ volatile u32 DENALI_CTL_46;
+ volatile u32 DENALI_CTL_47;
+ volatile u32 DENALI_CTL_48;
+ volatile u32 DENALI_CTL_49;
+ volatile u32 DENALI_CTL_50;
+ volatile u32 DENALI_CTL_51;
+ volatile u32 DENALI_CTL_52;
+ volatile u32 DENALI_CTL_53;
+ volatile u32 DENALI_CTL_54;
+ volatile u32 DENALI_CTL_55;
+ volatile u32 DENALI_CTL_56;
+ volatile u32 DENALI_CTL_57;
+ volatile u32 DENALI_CTL_58;
+ volatile u32 DENALI_CTL_59;
+ volatile u32 DENALI_CTL_60;
+ volatile u32 DENALI_CTL_61;
+ volatile u32 DENALI_CTL_62;
+ volatile u32 DENALI_CTL_63;
+ volatile u32 DENALI_CTL_64;
+ volatile u32 DENALI_CTL_65;
+ volatile u32 DENALI_CTL_66;
+ volatile u32 DENALI_CTL_67;
+ volatile u32 DENALI_CTL_68;
+ volatile u32 DENALI_CTL_69;
+ volatile u32 DENALI_CTL_70;
+ volatile u32 DENALI_CTL_71;
+ volatile u32 DENALI_CTL_72;
+ volatile u32 DENALI_CTL_73;
+ volatile u32 DENALI_CTL_74;
+ volatile u32 DENALI_CTL_75;
+ volatile u32 DENALI_CTL_76;
+ volatile u32 DENALI_CTL_77;
+ volatile u32 DENALI_CTL_78;
+ volatile u32 DENALI_CTL_79;
+ volatile u32 DENALI_CTL_80;
+ volatile u32 DENALI_CTL_81;
+ volatile u32 DENALI_CTL_82;
+ volatile u32 DENALI_CTL_83;
+ volatile u32 DENALI_CTL_84;
+ volatile u32 DENALI_CTL_85;
+ volatile u32 DENALI_CTL_86;
+ volatile u32 DENALI_CTL_87;
+ volatile u32 DENALI_CTL_88;
+ volatile u32 DENALI_CTL_89;
+ volatile u32 DENALI_CTL_90;
+ volatile u32 DENALI_CTL_91;
+ volatile u32 DENALI_CTL_92;
+ volatile u32 DENALI_CTL_93;
+ volatile u32 DENALI_CTL_94;
+ volatile u32 DENALI_CTL_95;
+ volatile u32 DENALI_CTL_96;
+ volatile u32 DENALI_CTL_97;
+ volatile u32 DENALI_CTL_98;
+ volatile u32 DENALI_CTL_99;
+ volatile u32 DENALI_CTL_100;
+ volatile u32 DENALI_CTL_101;
+ volatile u32 DENALI_CTL_102;
+ volatile u32 DENALI_CTL_103;
+ volatile u32 DENALI_CTL_104;
+ volatile u32 DENALI_CTL_105;
+ volatile u32 DENALI_CTL_106;
+ volatile u32 DENALI_CTL_107;
+ volatile u32 DENALI_CTL_108;
+ volatile u32 DENALI_CTL_109;
+ volatile u32 DENALI_CTL_110;
+ volatile u32 DENALI_CTL_111;
+ volatile u32 DENALI_CTL_112;
+ volatile u32 DENALI_CTL_113;
+ volatile u32 DENALI_CTL_114;
+ volatile u32 DENALI_CTL_115;
+ volatile u32 DENALI_CTL_116;
+ volatile u32 DENALI_CTL_117;
+ volatile u32 DENALI_CTL_118;
+ volatile u32 DENALI_CTL_119;
+ volatile u32 DENALI_CTL_120;
+ volatile u32 DENALI_CTL_121;
+ volatile u32 DENALI_CTL_122;
+ volatile u32 DENALI_CTL_123;
+ volatile u32 DENALI_CTL_124;
+ volatile u32 DENALI_CTL_125;
+ volatile u32 DENALI_CTL_126;
+ volatile u32 DENALI_CTL_127;
+ volatile u32 DENALI_CTL_128;
+ volatile u32 DENALI_CTL_129;
+ volatile u32 DENALI_CTL_130;
+ volatile u32 DENALI_CTL_131;
+ volatile u32 DENALI_CTL_132;
+ volatile u32 DENALI_CTL_133;
+ volatile u32 DENALI_CTL_134;
+ volatile u32 DENALI_CTL_135;
+ volatile u32 DENALI_CTL_136;
+ volatile u32 DENALI_CTL_137;
+ volatile u32 DENALI_CTL_138;
+ volatile u32 DENALI_CTL_139;
+ volatile u32 DENALI_CTL_140;
+ volatile u32 DENALI_CTL_141;
+ volatile u32 DENALI_CTL_142;
+ volatile u32 DENALI_CTL_143;
+ volatile u32 DENALI_CTL_144;
+ volatile u32 DENALI_CTL_145;
+ volatile u32 DENALI_CTL_146;
+ volatile u32 DENALI_CTL_147;
+ volatile u32 DENALI_CTL_148;
+ volatile u32 DENALI_CTL_149;
+ volatile u32 DENALI_CTL_150;
+ volatile u32 DENALI_CTL_151;
+ volatile u32 DENALI_CTL_152;
+ volatile u32 DENALI_CTL_153;
+ volatile u32 DENALI_CTL_154;
+ volatile u32 DENALI_CTL_155;
+ volatile u32 DENALI_CTL_156;
+ volatile u32 DENALI_CTL_157;
+ volatile u32 DENALI_CTL_158;
+ volatile u32 DENALI_CTL_159;
+ volatile u32 DENALI_CTL_160;
+ volatile u32 DENALI_CTL_161;
+ volatile u32 DENALI_CTL_162;
+ volatile u32 DENALI_CTL_163;
+ volatile u32 DENALI_CTL_164;
+ volatile u32 DENALI_CTL_165;
+ volatile u32 DENALI_CTL_166;
+ volatile u32 DENALI_CTL_167;
+ volatile u32 DENALI_CTL_168;
+ volatile u32 DENALI_CTL_169;
+ volatile u32 DENALI_CTL_170;
+ volatile u32 DENALI_CTL_171;
+ volatile u32 DENALI_CTL_172;
+ volatile u32 DENALI_CTL_173;
+ volatile u32 DENALI_CTL_174;
+ volatile u32 DENALI_CTL_175;
+ volatile u32 DENALI_CTL_176;
+ volatile u32 DENALI_CTL_177;
+ volatile u32 DENALI_CTL_178;
+ volatile u32 DENALI_CTL_179;
+ volatile u32 DENALI_CTL_180;
+ volatile u32 DENALI_CTL_181;
+ volatile u32 DENALI_CTL_182;
+ volatile u32 DENALI_CTL_183;
+ volatile u32 DENALI_CTL_184;
+ volatile u32 DENALI_CTL_185;
+ volatile u32 DENALI_CTL_186;
+ volatile u32 DENALI_CTL_187;
+ volatile u32 DENALI_CTL_188;
+ volatile u32 DENALI_CTL_189;
+ volatile u32 DENALI_CTL_190;
+ volatile u32 DENALI_CTL_191;
+ volatile u32 DENALI_CTL_192;
+ volatile u32 DENALI_CTL_193;
+ volatile u32 DENALI_CTL_194;
+ volatile u32 DENALI_CTL_195;
+ volatile u32 DENALI_CTL_196;
+ volatile u32 DENALI_CTL_197;
+ volatile u32 DENALI_CTL_198;
+ volatile u32 DENALI_CTL_199;
+ volatile u32 DENALI_CTL_200;
+ volatile u32 DENALI_CTL_201;
+ volatile u32 DENALI_CTL_202;
+ volatile u32 DENALI_CTL_203;
+ volatile u32 DENALI_CTL_204;
+ volatile u32 DENALI_CTL_205;
+ volatile u32 DENALI_CTL_206;
+ volatile u32 DENALI_CTL_207;
+ volatile u32 DENALI_CTL_208;
+ volatile u32 DENALI_CTL_209;
+ volatile u32 DENALI_CTL_210;
+ volatile u32 DENALI_CTL_211;
+ volatile u32 DENALI_CTL_212;
+ volatile u32 DENALI_CTL_213;
+ volatile u32 DENALI_CTL_214;
+ volatile u32 DENALI_CTL_215;
+ volatile u32 DENALI_CTL_216;
+ volatile u32 DENALI_CTL_217;
+ volatile u32 DENALI_CTL_218;
+ volatile u32 DENALI_CTL_219;
+ volatile u32 DENALI_CTL_220;
+ volatile u32 DENALI_CTL_221;
+ volatile u32 DENALI_CTL_222;
+ volatile u32 DENALI_CTL_223;
+ volatile u32 DENALI_CTL_224;
+ volatile u32 DENALI_CTL_225;
+ volatile u32 DENALI_CTL_226;
+ volatile u32 DENALI_CTL_227;
+ volatile u32 DENALI_CTL_228;
+ volatile u32 DENALI_CTL_229;
+ volatile u32 DENALI_CTL_230;
+ volatile u32 DENALI_CTL_231;
+ volatile u32 DENALI_CTL_232;
+ volatile u32 DENALI_CTL_233;
+ volatile u32 DENALI_CTL_234;
+ volatile u32 DENALI_CTL_235;
+ volatile u32 DENALI_CTL_236;
+ volatile u32 DENALI_CTL_237;
+ volatile u32 DENALI_CTL_238;
+ volatile u32 DENALI_CTL_239;
+ volatile u32 DENALI_CTL_240;
+ volatile u32 DENALI_CTL_241;
+ volatile u32 DENALI_CTL_242;
+ volatile u32 DENALI_CTL_243;
+ volatile u32 DENALI_CTL_244;
+ volatile u32 DENALI_CTL_245;
+ volatile u32 DENALI_CTL_246;
+ volatile u32 DENALI_CTL_247;
+ volatile u32 DENALI_CTL_248;
+ volatile u32 DENALI_CTL_249;
+ volatile u32 DENALI_CTL_250;
+ volatile u32 DENALI_CTL_251;
+ volatile u32 DENALI_CTL_252;
+ volatile u32 DENALI_CTL_253;
+ volatile u32 DENALI_CTL_254;
+ volatile u32 DENALI_CTL_255;
+ volatile u32 DENALI_CTL_256;
+ volatile u32 DENALI_CTL_257;
+ volatile u32 DENALI_CTL_258;
+ volatile u32 DENALI_CTL_259;
+ volatile u32 DENALI_CTL_260;
+ volatile u32 DENALI_CTL_261;
+ volatile u32 DENALI_CTL_262;
+ volatile u32 DENALI_CTL_263;
+ volatile u32 DENALI_CTL_264;
+ volatile u32 DENALI_CTL_265;
+ volatile u32 DENALI_CTL_266;
+ volatile u32 DENALI_CTL_267;
+ volatile u32 DENALI_CTL_268;
+ volatile u32 DENALI_CTL_269;
+ volatile u32 DENALI_CTL_270;
+ volatile u32 DENALI_CTL_271;
+ volatile u32 DENALI_CTL_272;
+ volatile u32 DENALI_CTL_273;
+ volatile u32 DENALI_CTL_274;
+ volatile u32 DENALI_CTL_275;
+ volatile u32 DENALI_CTL_276;
+ volatile u32 DENALI_CTL_277;
+ volatile u32 DENALI_CTL_278;
+ volatile u32 DENALI_CTL_279;
+ volatile u32 DENALI_CTL_280;
+ volatile u32 DENALI_CTL_281;
+ volatile u32 DENALI_CTL_282;
+ volatile u32 DENALI_CTL_283;
+ volatile u32 DENALI_CTL_284;
+ volatile u32 DENALI_CTL_285;
+ volatile u32 DENALI_CTL_286;
+ volatile u32 DENALI_CTL_287;
+ volatile u32 DENALI_CTL_288;
+ volatile u32 DENALI_CTL_289;
+ volatile u32 DENALI_CTL_290;
+ volatile u32 DENALI_CTL_291;
+ volatile u32 DENALI_CTL_292;
+ volatile u32 DENALI_CTL_293;
+ volatile u32 DENALI_CTL_294;
+ volatile u32 DENALI_CTL_295;
+ volatile u32 DENALI_CTL_296;
+ volatile u32 DENALI_CTL_297;
+ volatile u32 DENALI_CTL_298;
+ volatile u32 DENALI_CTL_299;
+ volatile u32 DENALI_CTL_300;
+ volatile u32 DENALI_CTL_301;
+ volatile u32 DENALI_CTL_302;
+ volatile u32 DENALI_CTL_303;
+ volatile u32 DENALI_CTL_304;
+ volatile u32 DENALI_CTL_305;
+ volatile u32 DENALI_CTL_306;
+ volatile u32 DENALI_CTL_307;
+ volatile u32 DENALI_CTL_308;
+ volatile u32 DENALI_CTL_309;
+ volatile u32 DENALI_CTL_310;
+ volatile u32 DENALI_CTL_311;
+ volatile u32 DENALI_CTL_312;
+ volatile u32 DENALI_CTL_313;
+ volatile u32 DENALI_CTL_314;
+ volatile u32 DENALI_CTL_315;
+ volatile u32 DENALI_CTL_316;
+ volatile u32 DENALI_CTL_317;
+ volatile u32 DENALI_CTL_318;
+ volatile u32 DENALI_CTL_319;
+ volatile u32 DENALI_CTL_320;
+ volatile u32 DENALI_CTL_321;
+ volatile u32 DENALI_CTL_322;
+ volatile u32 DENALI_CTL_323;
+ volatile u32 DENALI_CTL_324;
+ volatile u32 DENALI_CTL_325;
+ volatile u32 DENALI_CTL_326;
+ volatile u32 DENALI_CTL_327;
+ volatile u32 DENALI_CTL_328;
+ volatile u32 DENALI_CTL_329;
+ volatile u32 DENALI_CTL_330;
+ volatile u32 DENALI_CTL_331;
+ volatile u32 DENALI_CTL_332;
+ volatile u32 DENALI_CTL_333;
+ volatile u32 DENALI_CTL_334;
+ volatile u32 DENALI_CTL_335;
+ volatile u32 DENALI_CTL_336;
+ volatile u32 DENALI_CTL_337;
+ volatile u32 DENALI_CTL_338;
+ volatile u32 DENALI_CTL_339;
+ volatile u32 DENALI_CTL_340;
+ volatile u32 DENALI_CTL_341;
+ volatile u32 DENALI_CTL_342;
+ volatile u32 DENALI_CTL_343;
+ volatile u32 DENALI_CTL_344;
+ volatile u32 DENALI_CTL_345;
+ volatile u32 DENALI_CTL_346;
+ volatile u32 DENALI_CTL_347;
+ volatile u32 DENALI_CTL_348;
+ volatile u32 DENALI_CTL_349;
+ volatile u32 DENALI_CTL_350;
+ volatile u32 DENALI_CTL_351;
+ volatile u32 DENALI_CTL_352;
+ volatile u32 DENALI_CTL_353;
+ volatile u32 DENALI_CTL_354;
+ volatile u32 DENALI_CTL_355;
+ volatile u32 DENALI_CTL_356;
+ volatile u32 DENALI_CTL_357;
+ volatile u32 DENALI_CTL_358;
+ volatile u32 DENALI_CTL_359;
+ volatile u32 DENALI_CTL_360;
+ volatile u32 DENALI_CTL_361;
+ volatile u32 DENALI_CTL_362;
+ volatile u32 DENALI_CTL_363;
+ volatile u32 DENALI_CTL_364;
+ volatile u32 DENALI_CTL_365;
+ volatile u32 DENALI_CTL_366;
+ volatile u32 DENALI_CTL_367;
+ volatile u32 DENALI_CTL_368;
+ volatile u32 DENALI_CTL_369;
+ volatile u32 DENALI_CTL_370;
+ volatile u32 DENALI_CTL_371;
+ volatile u32 DENALI_CTL_372;
+ volatile u32 DENALI_CTL_373;
+ volatile u32 DENALI_CTL_374;
+ volatile u32 DENALI_CTL_375;
+ volatile u32 DENALI_CTL_376;
+ volatile u32 DENALI_CTL_377;
+ volatile u32 DENALI_CTL_378;
+ volatile u32 DENALI_CTL_379;
+ volatile u32 DENALI_CTL_380;
+ volatile u32 DENALI_CTL_381;
+ volatile u32 DENALI_CTL_382;
+ volatile u32 DENALI_CTL_383;
+ volatile u32 DENALI_CTL_384;
+ volatile u32 DENALI_CTL_385;
+ volatile u32 DENALI_CTL_386;
+ volatile u32 DENALI_CTL_387;
+ volatile u32 DENALI_CTL_388;
+ volatile u32 DENALI_CTL_389;
+ volatile u32 DENALI_CTL_390;
+ volatile u32 DENALI_CTL_391;
+ volatile u32 DENALI_CTL_392;
+ volatile u32 DENALI_CTL_393;
+ volatile u32 DENALI_CTL_394;
+ volatile u32 DENALI_CTL_395;
+ volatile u32 DENALI_CTL_396;
+ volatile u32 DENALI_CTL_397;
+ volatile u32 DENALI_CTL_398;
+ volatile u32 DENALI_CTL_399;
+ volatile u32 DENALI_CTL_400;
+ volatile u32 DENALI_CTL_401;
+ volatile u32 DENALI_CTL_402;
+ volatile u32 DENALI_CTL_403;
+ volatile u32 DENALI_CTL_404;
+ volatile u32 DENALI_CTL_405;
+ volatile u32 DENALI_CTL_406;
+ volatile u32 DENALI_CTL_407;
+ volatile u32 DENALI_CTL_408;
+ volatile u32 DENALI_CTL_409;
+ volatile u32 DENALI_CTL_410;
+ volatile u32 DENALI_CTL_411;
+ volatile u32 DENALI_CTL_412;
+ volatile u32 DENALI_CTL_413;
+ volatile u32 DENALI_CTL_414;
+ volatile u32 DENALI_CTL_415;
+ volatile u32 DENALI_CTL_416;
+ volatile u32 DENALI_CTL_417;
+ volatile u32 DENALI_CTL_418;
+ volatile u32 DENALI_CTL_419;
+ volatile u32 DENALI_CTL_420;
+ volatile u32 DENALI_CTL_421;
+ volatile u32 DENALI_CTL_422;
+ volatile u32 DENALI_CTL_423;
+ volatile u32 DENALI_CTL_424;
+ volatile u32 DENALI_CTL_425;
+ volatile u32 DENALI_CTL_426;
+ volatile u32 DENALI_CTL_427;
+ volatile u32 DENALI_CTL_428;
+ volatile u32 DENALI_CTL_429;
+ volatile u32 DENALI_CTL_430;
+ volatile u32 DENALI_CTL_431;
+ volatile u32 DENALI_CTL_432;
+ volatile u32 DENALI_CTL_433;
+ volatile u32 DENALI_CTL_434;
+ volatile u32 DENALI_CTL_435;
+ volatile u32 DENALI_CTL_436;
+ volatile u32 DENALI_CTL_437;
+ volatile u32 DENALI_CTL_438;
+ volatile u32 DENALI_CTL_439;
+ volatile u32 DENALI_CTL_440;
+ volatile u32 DENALI_CTL_441;
+ volatile u32 DENALI_CTL_442;
+ volatile u32 DENALI_CTL_443;
+ volatile u32 DENALI_CTL_444;
+ volatile u32 DENALI_CTL_445;
+ volatile u32 DENALI_CTL_446;
+ volatile u32 DENALI_CTL_447;
+ volatile u32 DENALI_CTL_448;
+ volatile u32 DENALI_CTL_449;
+ volatile u32 DENALI_CTL_450;
+ volatile u32 DENALI_CTL_451;
+ volatile u32 DENALI_CTL_452;
+ volatile u32 DENALI_CTL_453;
+ volatile u32 DENALI_CTL_454;
+ volatile u32 DENALI_CTL_455;
+ volatile u32 DENALI_CTL_456;
+ volatile u32 DENALI_CTL_457;
+ volatile u32 DENALI_CTL_458;
+ volatile char pad__0[0x18D4U];
+ volatile u32 DENALI_PI_0;
+ volatile u32 DENALI_PI_1;
+ volatile u32 DENALI_PI_2;
+ volatile u32 DENALI_PI_3;
+ volatile u32 DENALI_PI_4;
+ volatile u32 DENALI_PI_5;
+ volatile u32 DENALI_PI_6;
+ volatile u32 DENALI_PI_7;
+ volatile u32 DENALI_PI_8;
+ volatile u32 DENALI_PI_9;
+ volatile u32 DENALI_PI_10;
+ volatile u32 DENALI_PI_11;
+ volatile u32 DENALI_PI_12;
+ volatile u32 DENALI_PI_13;
+ volatile u32 DENALI_PI_14;
+ volatile u32 DENALI_PI_15;
+ volatile u32 DENALI_PI_16;
+ volatile u32 DENALI_PI_17;
+ volatile u32 DENALI_PI_18;
+ volatile u32 DENALI_PI_19;
+ volatile u32 DENALI_PI_20;
+ volatile u32 DENALI_PI_21;
+ volatile u32 DENALI_PI_22;
+ volatile u32 DENALI_PI_23;
+ volatile u32 DENALI_PI_24;
+ volatile u32 DENALI_PI_25;
+ volatile u32 DENALI_PI_26;
+ volatile u32 DENALI_PI_27;
+ volatile u32 DENALI_PI_28;
+ volatile u32 DENALI_PI_29;
+ volatile u32 DENALI_PI_30;
+ volatile u32 DENALI_PI_31;
+ volatile u32 DENALI_PI_32;
+ volatile u32 DENALI_PI_33;
+ volatile u32 DENALI_PI_34;
+ volatile u32 DENALI_PI_35;
+ volatile u32 DENALI_PI_36;
+ volatile u32 DENALI_PI_37;
+ volatile u32 DENALI_PI_38;
+ volatile u32 DENALI_PI_39;
+ volatile u32 DENALI_PI_40;
+ volatile u32 DENALI_PI_41;
+ volatile u32 DENALI_PI_42;
+ volatile u32 DENALI_PI_43;
+ volatile u32 DENALI_PI_44;
+ volatile u32 DENALI_PI_45;
+ volatile u32 DENALI_PI_46;
+ volatile u32 DENALI_PI_47;
+ volatile u32 DENALI_PI_48;
+ volatile u32 DENALI_PI_49;
+ volatile u32 DENALI_PI_50;
+ volatile u32 DENALI_PI_51;
+ volatile u32 DENALI_PI_52;
+ volatile u32 DENALI_PI_53;
+ volatile u32 DENALI_PI_54;
+ volatile u32 DENALI_PI_55;
+ volatile u32 DENALI_PI_56;
+ volatile u32 DENALI_PI_57;
+ volatile u32 DENALI_PI_58;
+ volatile u32 DENALI_PI_59;
+ volatile u32 DENALI_PI_60;
+ volatile u32 DENALI_PI_61;
+ volatile u32 DENALI_PI_62;
+ volatile u32 DENALI_PI_63;
+ volatile u32 DENALI_PI_64;
+ volatile u32 DENALI_PI_65;
+ volatile u32 DENALI_PI_66;
+ volatile u32 DENALI_PI_67;
+ volatile u32 DENALI_PI_68;
+ volatile u32 DENALI_PI_69;
+ volatile u32 DENALI_PI_70;
+ volatile u32 DENALI_PI_71;
+ volatile u32 DENALI_PI_72;
+ volatile u32 DENALI_PI_73;
+ volatile u32 DENALI_PI_74;
+ volatile u32 DENALI_PI_75;
+ volatile u32 DENALI_PI_76;
+ volatile u32 DENALI_PI_77;
+ volatile u32 DENALI_PI_78;
+ volatile u32 DENALI_PI_79;
+ volatile u32 DENALI_PI_80;
+ volatile u32 DENALI_PI_81;
+ volatile u32 DENALI_PI_82;
+ volatile u32 DENALI_PI_83;
+ volatile u32 DENALI_PI_84;
+ volatile u32 DENALI_PI_85;
+ volatile u32 DENALI_PI_86;
+ volatile u32 DENALI_PI_87;
+ volatile u32 DENALI_PI_88;
+ volatile u32 DENALI_PI_89;
+ volatile u32 DENALI_PI_90;
+ volatile u32 DENALI_PI_91;
+ volatile u32 DENALI_PI_92;
+ volatile u32 DENALI_PI_93;
+ volatile u32 DENALI_PI_94;
+ volatile u32 DENALI_PI_95;
+ volatile u32 DENALI_PI_96;
+ volatile u32 DENALI_PI_97;
+ volatile u32 DENALI_PI_98;
+ volatile u32 DENALI_PI_99;
+ volatile u32 DENALI_PI_100;
+ volatile u32 DENALI_PI_101;
+ volatile u32 DENALI_PI_102;
+ volatile u32 DENALI_PI_103;
+ volatile u32 DENALI_PI_104;
+ volatile u32 DENALI_PI_105;
+ volatile u32 DENALI_PI_106;
+ volatile u32 DENALI_PI_107;
+ volatile u32 DENALI_PI_108;
+ volatile u32 DENALI_PI_109;
+ volatile u32 DENALI_PI_110;
+ volatile u32 DENALI_PI_111;
+ volatile u32 DENALI_PI_112;
+ volatile u32 DENALI_PI_113;
+ volatile u32 DENALI_PI_114;
+ volatile u32 DENALI_PI_115;
+ volatile u32 DENALI_PI_116;
+ volatile u32 DENALI_PI_117;
+ volatile u32 DENALI_PI_118;
+ volatile u32 DENALI_PI_119;
+ volatile u32 DENALI_PI_120;
+ volatile u32 DENALI_PI_121;
+ volatile u32 DENALI_PI_122;
+ volatile u32 DENALI_PI_123;
+ volatile u32 DENALI_PI_124;
+ volatile u32 DENALI_PI_125;
+ volatile u32 DENALI_PI_126;
+ volatile u32 DENALI_PI_127;
+ volatile u32 DENALI_PI_128;
+ volatile u32 DENALI_PI_129;
+ volatile u32 DENALI_PI_130;
+ volatile u32 DENALI_PI_131;
+ volatile u32 DENALI_PI_132;
+ volatile u32 DENALI_PI_133;
+ volatile u32 DENALI_PI_134;
+ volatile u32 DENALI_PI_135;
+ volatile u32 DENALI_PI_136;
+ volatile u32 DENALI_PI_137;
+ volatile u32 DENALI_PI_138;
+ volatile u32 DENALI_PI_139;
+ volatile u32 DENALI_PI_140;
+ volatile u32 DENALI_PI_141;
+ volatile u32 DENALI_PI_142;
+ volatile u32 DENALI_PI_143;
+ volatile u32 DENALI_PI_144;
+ volatile u32 DENALI_PI_145;
+ volatile u32 DENALI_PI_146;
+ volatile u32 DENALI_PI_147;
+ volatile u32 DENALI_PI_148;
+ volatile u32 DENALI_PI_149;
+ volatile u32 DENALI_PI_150;
+ volatile u32 DENALI_PI_151;
+ volatile u32 DENALI_PI_152;
+ volatile u32 DENALI_PI_153;
+ volatile u32 DENALI_PI_154;
+ volatile u32 DENALI_PI_155;
+ volatile u32 DENALI_PI_156;
+ volatile u32 DENALI_PI_157;
+ volatile u32 DENALI_PI_158;
+ volatile u32 DENALI_PI_159;
+ volatile u32 DENALI_PI_160;
+ volatile u32 DENALI_PI_161;
+ volatile u32 DENALI_PI_162;
+ volatile u32 DENALI_PI_163;
+ volatile u32 DENALI_PI_164;
+ volatile u32 DENALI_PI_165;
+ volatile u32 DENALI_PI_166;
+ volatile u32 DENALI_PI_167;
+ volatile u32 DENALI_PI_168;
+ volatile u32 DENALI_PI_169;
+ volatile u32 DENALI_PI_170;
+ volatile u32 DENALI_PI_171;
+ volatile u32 DENALI_PI_172;
+ volatile u32 DENALI_PI_173;
+ volatile u32 DENALI_PI_174;
+ volatile u32 DENALI_PI_175;
+ volatile u32 DENALI_PI_176;
+ volatile u32 DENALI_PI_177;
+ volatile u32 DENALI_PI_178;
+ volatile u32 DENALI_PI_179;
+ volatile u32 DENALI_PI_180;
+ volatile u32 DENALI_PI_181;
+ volatile u32 DENALI_PI_182;
+ volatile u32 DENALI_PI_183;
+ volatile u32 DENALI_PI_184;
+ volatile u32 DENALI_PI_185;
+ volatile u32 DENALI_PI_186;
+ volatile u32 DENALI_PI_187;
+ volatile u32 DENALI_PI_188;
+ volatile u32 DENALI_PI_189;
+ volatile u32 DENALI_PI_190;
+ volatile u32 DENALI_PI_191;
+ volatile u32 DENALI_PI_192;
+ volatile u32 DENALI_PI_193;
+ volatile u32 DENALI_PI_194;
+ volatile u32 DENALI_PI_195;
+ volatile u32 DENALI_PI_196;
+ volatile u32 DENALI_PI_197;
+ volatile u32 DENALI_PI_198;
+ volatile u32 DENALI_PI_199;
+ volatile u32 DENALI_PI_200;
+ volatile u32 DENALI_PI_201;
+ volatile u32 DENALI_PI_202;
+ volatile u32 DENALI_PI_203;
+ volatile u32 DENALI_PI_204;
+ volatile u32 DENALI_PI_205;
+ volatile u32 DENALI_PI_206;
+ volatile u32 DENALI_PI_207;
+ volatile u32 DENALI_PI_208;
+ volatile u32 DENALI_PI_209;
+ volatile u32 DENALI_PI_210;
+ volatile u32 DENALI_PI_211;
+ volatile u32 DENALI_PI_212;
+ volatile u32 DENALI_PI_213;
+ volatile u32 DENALI_PI_214;
+ volatile u32 DENALI_PI_215;
+ volatile u32 DENALI_PI_216;
+ volatile u32 DENALI_PI_217;
+ volatile u32 DENALI_PI_218;
+ volatile u32 DENALI_PI_219;
+ volatile u32 DENALI_PI_220;
+ volatile u32 DENALI_PI_221;
+ volatile u32 DENALI_PI_222;
+ volatile u32 DENALI_PI_223;
+ volatile u32 DENALI_PI_224;
+ volatile u32 DENALI_PI_225;
+ volatile u32 DENALI_PI_226;
+ volatile u32 DENALI_PI_227;
+ volatile u32 DENALI_PI_228;
+ volatile u32 DENALI_PI_229;
+ volatile u32 DENALI_PI_230;
+ volatile u32 DENALI_PI_231;
+ volatile u32 DENALI_PI_232;
+ volatile u32 DENALI_PI_233;
+ volatile u32 DENALI_PI_234;
+ volatile u32 DENALI_PI_235;
+ volatile u32 DENALI_PI_236;
+ volatile u32 DENALI_PI_237;
+ volatile u32 DENALI_PI_238;
+ volatile u32 DENALI_PI_239;
+ volatile u32 DENALI_PI_240;
+ volatile u32 DENALI_PI_241;
+ volatile u32 DENALI_PI_242;
+ volatile u32 DENALI_PI_243;
+ volatile u32 DENALI_PI_244;
+ volatile u32 DENALI_PI_245;
+ volatile u32 DENALI_PI_246;
+ volatile u32 DENALI_PI_247;
+ volatile u32 DENALI_PI_248;
+ volatile u32 DENALI_PI_249;
+ volatile u32 DENALI_PI_250;
+ volatile u32 DENALI_PI_251;
+ volatile u32 DENALI_PI_252;
+ volatile u32 DENALI_PI_253;
+ volatile u32 DENALI_PI_254;
+ volatile u32 DENALI_PI_255;
+ volatile u32 DENALI_PI_256;
+ volatile u32 DENALI_PI_257;
+ volatile u32 DENALI_PI_258;
+ volatile u32 DENALI_PI_259;
+ volatile u32 DENALI_PI_260;
+ volatile u32 DENALI_PI_261;
+ volatile u32 DENALI_PI_262;
+ volatile u32 DENALI_PI_263;
+ volatile u32 DENALI_PI_264;
+ volatile u32 DENALI_PI_265;
+ volatile u32 DENALI_PI_266;
+ volatile u32 DENALI_PI_267;
+ volatile u32 DENALI_PI_268;
+ volatile u32 DENALI_PI_269;
+ volatile u32 DENALI_PI_270;
+ volatile u32 DENALI_PI_271;
+ volatile u32 DENALI_PI_272;
+ volatile u32 DENALI_PI_273;
+ volatile u32 DENALI_PI_274;
+ volatile u32 DENALI_PI_275;
+ volatile u32 DENALI_PI_276;
+ volatile u32 DENALI_PI_277;
+ volatile u32 DENALI_PI_278;
+ volatile u32 DENALI_PI_279;
+ volatile u32 DENALI_PI_280;
+ volatile u32 DENALI_PI_281;
+ volatile u32 DENALI_PI_282;
+ volatile u32 DENALI_PI_283;
+ volatile u32 DENALI_PI_284;
+ volatile u32 DENALI_PI_285;
+ volatile u32 DENALI_PI_286;
+ volatile u32 DENALI_PI_287;
+ volatile u32 DENALI_PI_288;
+ volatile u32 DENALI_PI_289;
+ volatile u32 DENALI_PI_290;
+ volatile u32 DENALI_PI_291;
+ volatile u32 DENALI_PI_292;
+ volatile u32 DENALI_PI_293;
+ volatile u32 DENALI_PI_294;
+ volatile u32 DENALI_PI_295;
+ volatile u32 DENALI_PI_296;
+ volatile u32 DENALI_PI_297;
+ volatile u32 DENALI_PI_298;
+ volatile u32 DENALI_PI_299;
+ volatile char pad__1[0x1B50U];
+ volatile u32 DENALI_PHY_0;
+ volatile u32 DENALI_PHY_1;
+ volatile u32 DENALI_PHY_2;
+ volatile u32 DENALI_PHY_3;
+ volatile u32 DENALI_PHY_4;
+ volatile u32 DENALI_PHY_5;
+ volatile u32 DENALI_PHY_6;
+ volatile u32 DENALI_PHY_7;
+ volatile u32 DENALI_PHY_8;
+ volatile u32 DENALI_PHY_9;
+ volatile u32 DENALI_PHY_10;
+ volatile u32 DENALI_PHY_11;
+ volatile u32 DENALI_PHY_12;
+ volatile u32 DENALI_PHY_13;
+ volatile u32 DENALI_PHY_14;
+ volatile u32 DENALI_PHY_15;
+ volatile u32 DENALI_PHY_16;
+ volatile u32 DENALI_PHY_17;
+ volatile u32 DENALI_PHY_18;
+ volatile u32 DENALI_PHY_19;
+ volatile u32 DENALI_PHY_20;
+ volatile u32 DENALI_PHY_21;
+ volatile u32 DENALI_PHY_22;
+ volatile u32 DENALI_PHY_23;
+ volatile u32 DENALI_PHY_24;
+ volatile u32 DENALI_PHY_25;
+ volatile u32 DENALI_PHY_26;
+ volatile u32 DENALI_PHY_27;
+ volatile u32 DENALI_PHY_28;
+ volatile u32 DENALI_PHY_29;
+ volatile u32 DENALI_PHY_30;
+ volatile u32 DENALI_PHY_31;
+ volatile u32 DENALI_PHY_32;
+ volatile u32 DENALI_PHY_33;
+ volatile u32 DENALI_PHY_34;
+ volatile u32 DENALI_PHY_35;
+ volatile u32 DENALI_PHY_36;
+ volatile u32 DENALI_PHY_37;
+ volatile u32 DENALI_PHY_38;
+ volatile u32 DENALI_PHY_39;
+ volatile u32 DENALI_PHY_40;
+ volatile u32 DENALI_PHY_41;
+ volatile u32 DENALI_PHY_42;
+ volatile u32 DENALI_PHY_43;
+ volatile u32 DENALI_PHY_44;
+ volatile u32 DENALI_PHY_45;
+ volatile u32 DENALI_PHY_46;
+ volatile u32 DENALI_PHY_47;
+ volatile u32 DENALI_PHY_48;
+ volatile u32 DENALI_PHY_49;
+ volatile u32 DENALI_PHY_50;
+ volatile u32 DENALI_PHY_51;
+ volatile u32 DENALI_PHY_52;
+ volatile u32 DENALI_PHY_53;
+ volatile u32 DENALI_PHY_54;
+ volatile u32 DENALI_PHY_55;
+ volatile u32 DENALI_PHY_56;
+ volatile u32 DENALI_PHY_57;
+ volatile u32 DENALI_PHY_58;
+ volatile u32 DENALI_PHY_59;
+ volatile u32 DENALI_PHY_60;
+ volatile u32 DENALI_PHY_61;
+ volatile u32 DENALI_PHY_62;
+ volatile u32 DENALI_PHY_63;
+ volatile u32 DENALI_PHY_64;
+ volatile u32 DENALI_PHY_65;
+ volatile u32 DENALI_PHY_66;
+ volatile u32 DENALI_PHY_67;
+ volatile u32 DENALI_PHY_68;
+ volatile u32 DENALI_PHY_69;
+ volatile u32 DENALI_PHY_70;
+ volatile u32 DENALI_PHY_71;
+ volatile u32 DENALI_PHY_72;
+ volatile u32 DENALI_PHY_73;
+ volatile u32 DENALI_PHY_74;
+ volatile u32 DENALI_PHY_75;
+ volatile u32 DENALI_PHY_76;
+ volatile u32 DENALI_PHY_77;
+ volatile u32 DENALI_PHY_78;
+ volatile u32 DENALI_PHY_79;
+ volatile u32 DENALI_PHY_80;
+ volatile u32 DENALI_PHY_81;
+ volatile u32 DENALI_PHY_82;
+ volatile u32 DENALI_PHY_83;
+ volatile u32 DENALI_PHY_84;
+ volatile u32 DENALI_PHY_85;
+ volatile u32 DENALI_PHY_86;
+ volatile u32 DENALI_PHY_87;
+ volatile u32 DENALI_PHY_88;
+ volatile u32 DENALI_PHY_89;
+ volatile u32 DENALI_PHY_90;
+ volatile u32 DENALI_PHY_91;
+ volatile u32 DENALI_PHY_92;
+ volatile u32 DENALI_PHY_93;
+ volatile u32 DENALI_PHY_94;
+ volatile u32 DENALI_PHY_95;
+ volatile u32 DENALI_PHY_96;
+ volatile u32 DENALI_PHY_97;
+ volatile u32 DENALI_PHY_98;
+ volatile u32 DENALI_PHY_99;
+ volatile u32 DENALI_PHY_100;
+ volatile u32 DENALI_PHY_101;
+ volatile u32 DENALI_PHY_102;
+ volatile u32 DENALI_PHY_103;
+ volatile u32 DENALI_PHY_104;
+ volatile u32 DENALI_PHY_105;
+ volatile u32 DENALI_PHY_106;
+ volatile u32 DENALI_PHY_107;
+ volatile u32 DENALI_PHY_108;
+ volatile u32 DENALI_PHY_109;
+ volatile u32 DENALI_PHY_110;
+ volatile u32 DENALI_PHY_111;
+ volatile u32 DENALI_PHY_112;
+ volatile u32 DENALI_PHY_113;
+ volatile u32 DENALI_PHY_114;
+ volatile u32 DENALI_PHY_115;
+ volatile u32 DENALI_PHY_116;
+ volatile u32 DENALI_PHY_117;
+ volatile u32 DENALI_PHY_118;
+ volatile u32 DENALI_PHY_119;
+ volatile u32 DENALI_PHY_120;
+ volatile u32 DENALI_PHY_121;
+ volatile u32 DENALI_PHY_122;
+ volatile u32 DENALI_PHY_123;
+ volatile u32 DENALI_PHY_124;
+ volatile u32 DENALI_PHY_125;
+ volatile u32 DENALI_PHY_126;
+ volatile u32 DENALI_PHY_127;
+ volatile u32 DENALI_PHY_128;
+ volatile u32 DENALI_PHY_129;
+ volatile u32 DENALI_PHY_130;
+ volatile u32 DENALI_PHY_131;
+ volatile u32 DENALI_PHY_132;
+ volatile u32 DENALI_PHY_133;
+ volatile u32 DENALI_PHY_134;
+ volatile u32 DENALI_PHY_135;
+ volatile u32 DENALI_PHY_136;
+ volatile u32 DENALI_PHY_137;
+ volatile u32 DENALI_PHY_138;
+ volatile u32 DENALI_PHY_139;
+ volatile char pad__2[0x1D0U];
+ volatile u32 DENALI_PHY_256;
+ volatile u32 DENALI_PHY_257;
+ volatile u32 DENALI_PHY_258;
+ volatile u32 DENALI_PHY_259;
+ volatile u32 DENALI_PHY_260;
+ volatile u32 DENALI_PHY_261;
+ volatile u32 DENALI_PHY_262;
+ volatile u32 DENALI_PHY_263;
+ volatile u32 DENALI_PHY_264;
+ volatile u32 DENALI_PHY_265;
+ volatile u32 DENALI_PHY_266;
+ volatile u32 DENALI_PHY_267;
+ volatile u32 DENALI_PHY_268;
+ volatile u32 DENALI_PHY_269;
+ volatile u32 DENALI_PHY_270;
+ volatile u32 DENALI_PHY_271;
+ volatile u32 DENALI_PHY_272;
+ volatile u32 DENALI_PHY_273;
+ volatile u32 DENALI_PHY_274;
+ volatile u32 DENALI_PHY_275;
+ volatile u32 DENALI_PHY_276;
+ volatile u32 DENALI_PHY_277;
+ volatile u32 DENALI_PHY_278;
+ volatile u32 DENALI_PHY_279;
+ volatile u32 DENALI_PHY_280;
+ volatile u32 DENALI_PHY_281;
+ volatile u32 DENALI_PHY_282;
+ volatile u32 DENALI_PHY_283;
+ volatile u32 DENALI_PHY_284;
+ volatile u32 DENALI_PHY_285;
+ volatile u32 DENALI_PHY_286;
+ volatile u32 DENALI_PHY_287;
+ volatile u32 DENALI_PHY_288;
+ volatile u32 DENALI_PHY_289;
+ volatile u32 DENALI_PHY_290;
+ volatile u32 DENALI_PHY_291;
+ volatile u32 DENALI_PHY_292;
+ volatile u32 DENALI_PHY_293;
+ volatile u32 DENALI_PHY_294;
+ volatile u32 DENALI_PHY_295;
+ volatile u32 DENALI_PHY_296;
+ volatile u32 DENALI_PHY_297;
+ volatile u32 DENALI_PHY_298;
+ volatile u32 DENALI_PHY_299;
+ volatile u32 DENALI_PHY_300;
+ volatile u32 DENALI_PHY_301;
+ volatile u32 DENALI_PHY_302;
+ volatile u32 DENALI_PHY_303;
+ volatile u32 DENALI_PHY_304;
+ volatile u32 DENALI_PHY_305;
+ volatile u32 DENALI_PHY_306;
+ volatile u32 DENALI_PHY_307;
+ volatile u32 DENALI_PHY_308;
+ volatile u32 DENALI_PHY_309;
+ volatile u32 DENALI_PHY_310;
+ volatile u32 DENALI_PHY_311;
+ volatile u32 DENALI_PHY_312;
+ volatile u32 DENALI_PHY_313;
+ volatile u32 DENALI_PHY_314;
+ volatile u32 DENALI_PHY_315;
+ volatile u32 DENALI_PHY_316;
+ volatile u32 DENALI_PHY_317;
+ volatile u32 DENALI_PHY_318;
+ volatile u32 DENALI_PHY_319;
+ volatile u32 DENALI_PHY_320;
+ volatile u32 DENALI_PHY_321;
+ volatile u32 DENALI_PHY_322;
+ volatile u32 DENALI_PHY_323;
+ volatile u32 DENALI_PHY_324;
+ volatile u32 DENALI_PHY_325;
+ volatile u32 DENALI_PHY_326;
+ volatile u32 DENALI_PHY_327;
+ volatile u32 DENALI_PHY_328;
+ volatile u32 DENALI_PHY_329;
+ volatile u32 DENALI_PHY_330;
+ volatile u32 DENALI_PHY_331;
+ volatile u32 DENALI_PHY_332;
+ volatile u32 DENALI_PHY_333;
+ volatile u32 DENALI_PHY_334;
+ volatile u32 DENALI_PHY_335;
+ volatile u32 DENALI_PHY_336;
+ volatile u32 DENALI_PHY_337;
+ volatile u32 DENALI_PHY_338;
+ volatile u32 DENALI_PHY_339;
+ volatile u32 DENALI_PHY_340;
+ volatile u32 DENALI_PHY_341;
+ volatile u32 DENALI_PHY_342;
+ volatile u32 DENALI_PHY_343;
+ volatile u32 DENALI_PHY_344;
+ volatile u32 DENALI_PHY_345;
+ volatile u32 DENALI_PHY_346;
+ volatile u32 DENALI_PHY_347;
+ volatile u32 DENALI_PHY_348;
+ volatile u32 DENALI_PHY_349;
+ volatile u32 DENALI_PHY_350;
+ volatile u32 DENALI_PHY_351;
+ volatile u32 DENALI_PHY_352;
+ volatile u32 DENALI_PHY_353;
+ volatile u32 DENALI_PHY_354;
+ volatile u32 DENALI_PHY_355;
+ volatile u32 DENALI_PHY_356;
+ volatile u32 DENALI_PHY_357;
+ volatile u32 DENALI_PHY_358;
+ volatile u32 DENALI_PHY_359;
+ volatile u32 DENALI_PHY_360;
+ volatile u32 DENALI_PHY_361;
+ volatile u32 DENALI_PHY_362;
+ volatile u32 DENALI_PHY_363;
+ volatile u32 DENALI_PHY_364;
+ volatile u32 DENALI_PHY_365;
+ volatile u32 DENALI_PHY_366;
+ volatile u32 DENALI_PHY_367;
+ volatile u32 DENALI_PHY_368;
+ volatile u32 DENALI_PHY_369;
+ volatile u32 DENALI_PHY_370;
+ volatile u32 DENALI_PHY_371;
+ volatile u32 DENALI_PHY_372;
+ volatile u32 DENALI_PHY_373;
+ volatile u32 DENALI_PHY_374;
+ volatile u32 DENALI_PHY_375;
+ volatile u32 DENALI_PHY_376;
+ volatile u32 DENALI_PHY_377;
+ volatile u32 DENALI_PHY_378;
+ volatile u32 DENALI_PHY_379;
+ volatile u32 DENALI_PHY_380;
+ volatile u32 DENALI_PHY_381;
+ volatile u32 DENALI_PHY_382;
+ volatile u32 DENALI_PHY_383;
+ volatile u32 DENALI_PHY_384;
+ volatile u32 DENALI_PHY_385;
+ volatile u32 DENALI_PHY_386;
+ volatile u32 DENALI_PHY_387;
+ volatile u32 DENALI_PHY_388;
+ volatile u32 DENALI_PHY_389;
+ volatile u32 DENALI_PHY_390;
+ volatile u32 DENALI_PHY_391;
+ volatile u32 DENALI_PHY_392;
+ volatile u32 DENALI_PHY_393;
+ volatile u32 DENALI_PHY_394;
+ volatile u32 DENALI_PHY_395;
+ volatile char pad__3[0x1D0U];
+ volatile u32 DENALI_PHY_512;
+ volatile u32 DENALI_PHY_513;
+ volatile u32 DENALI_PHY_514;
+ volatile u32 DENALI_PHY_515;
+ volatile u32 DENALI_PHY_516;
+ volatile u32 DENALI_PHY_517;
+ volatile u32 DENALI_PHY_518;
+ volatile u32 DENALI_PHY_519;
+ volatile u32 DENALI_PHY_520;
+ volatile u32 DENALI_PHY_521;
+ volatile u32 DENALI_PHY_522;
+ volatile u32 DENALI_PHY_523;
+ volatile u32 DENALI_PHY_524;
+ volatile u32 DENALI_PHY_525;
+ volatile u32 DENALI_PHY_526;
+ volatile u32 DENALI_PHY_527;
+ volatile u32 DENALI_PHY_528;
+ volatile u32 DENALI_PHY_529;
+ volatile u32 DENALI_PHY_530;
+ volatile u32 DENALI_PHY_531;
+ volatile u32 DENALI_PHY_532;
+ volatile u32 DENALI_PHY_533;
+ volatile u32 DENALI_PHY_534;
+ volatile u32 DENALI_PHY_535;
+ volatile u32 DENALI_PHY_536;
+ volatile u32 DENALI_PHY_537;
+ volatile u32 DENALI_PHY_538;
+ volatile u32 DENALI_PHY_539;
+ volatile u32 DENALI_PHY_540;
+ volatile u32 DENALI_PHY_541;
+ volatile u32 DENALI_PHY_542;
+ volatile u32 DENALI_PHY_543;
+ volatile u32 DENALI_PHY_544;
+ volatile u32 DENALI_PHY_545;
+ volatile u32 DENALI_PHY_546;
+ volatile u32 DENALI_PHY_547;
+ volatile u32 DENALI_PHY_548;
+ volatile u32 DENALI_PHY_549;
+ volatile u32 DENALI_PHY_550;
+ volatile u32 DENALI_PHY_551;
+ volatile u32 DENALI_PHY_552;
+ volatile u32 DENALI_PHY_553;
+ volatile u32 DENALI_PHY_554;
+ volatile u32 DENALI_PHY_555;
+ volatile u32 DENALI_PHY_556;
+ volatile u32 DENALI_PHY_557;
+ volatile u32 DENALI_PHY_558;
+ volatile u32 DENALI_PHY_559;
+ volatile u32 DENALI_PHY_560;
+ volatile u32 DENALI_PHY_561;
+ volatile u32 DENALI_PHY_562;
+ volatile u32 DENALI_PHY_563;
+ volatile u32 DENALI_PHY_564;
+ volatile u32 DENALI_PHY_565;
+ volatile u32 DENALI_PHY_566;
+ volatile u32 DENALI_PHY_567;
+ volatile u32 DENALI_PHY_568;
+ volatile u32 DENALI_PHY_569;
+ volatile u32 DENALI_PHY_570;
+ volatile u32 DENALI_PHY_571;
+ volatile u32 DENALI_PHY_572;
+ volatile u32 DENALI_PHY_573;
+ volatile u32 DENALI_PHY_574;
+ volatile u32 DENALI_PHY_575;
+ volatile u32 DENALI_PHY_576;
+ volatile u32 DENALI_PHY_577;
+ volatile u32 DENALI_PHY_578;
+ volatile u32 DENALI_PHY_579;
+ volatile u32 DENALI_PHY_580;
+ volatile u32 DENALI_PHY_581;
+ volatile u32 DENALI_PHY_582;
+ volatile u32 DENALI_PHY_583;
+ volatile u32 DENALI_PHY_584;
+ volatile u32 DENALI_PHY_585;
+ volatile u32 DENALI_PHY_586;
+ volatile u32 DENALI_PHY_587;
+ volatile u32 DENALI_PHY_588;
+ volatile u32 DENALI_PHY_589;
+ volatile u32 DENALI_PHY_590;
+ volatile u32 DENALI_PHY_591;
+ volatile u32 DENALI_PHY_592;
+ volatile u32 DENALI_PHY_593;
+ volatile u32 DENALI_PHY_594;
+ volatile u32 DENALI_PHY_595;
+ volatile u32 DENALI_PHY_596;
+ volatile u32 DENALI_PHY_597;
+ volatile u32 DENALI_PHY_598;
+ volatile u32 DENALI_PHY_599;
+ volatile u32 DENALI_PHY_600;
+ volatile u32 DENALI_PHY_601;
+ volatile u32 DENALI_PHY_602;
+ volatile u32 DENALI_PHY_603;
+ volatile u32 DENALI_PHY_604;
+ volatile u32 DENALI_PHY_605;
+ volatile u32 DENALI_PHY_606;
+ volatile u32 DENALI_PHY_607;
+ volatile u32 DENALI_PHY_608;
+ volatile u32 DENALI_PHY_609;
+ volatile u32 DENALI_PHY_610;
+ volatile u32 DENALI_PHY_611;
+ volatile u32 DENALI_PHY_612;
+ volatile u32 DENALI_PHY_613;
+ volatile u32 DENALI_PHY_614;
+ volatile u32 DENALI_PHY_615;
+ volatile u32 DENALI_PHY_616;
+ volatile u32 DENALI_PHY_617;
+ volatile u32 DENALI_PHY_618;
+ volatile u32 DENALI_PHY_619;
+ volatile u32 DENALI_PHY_620;
+ volatile u32 DENALI_PHY_621;
+ volatile u32 DENALI_PHY_622;
+ volatile u32 DENALI_PHY_623;
+ volatile u32 DENALI_PHY_624;
+ volatile u32 DENALI_PHY_625;
+ volatile u32 DENALI_PHY_626;
+ volatile u32 DENALI_PHY_627;
+ volatile u32 DENALI_PHY_628;
+ volatile u32 DENALI_PHY_629;
+ volatile u32 DENALI_PHY_630;
+ volatile u32 DENALI_PHY_631;
+ volatile u32 DENALI_PHY_632;
+ volatile u32 DENALI_PHY_633;
+ volatile u32 DENALI_PHY_634;
+ volatile u32 DENALI_PHY_635;
+ volatile u32 DENALI_PHY_636;
+ volatile u32 DENALI_PHY_637;
+ volatile u32 DENALI_PHY_638;
+ volatile u32 DENALI_PHY_639;
+ volatile u32 DENALI_PHY_640;
+ volatile u32 DENALI_PHY_641;
+ volatile u32 DENALI_PHY_642;
+ volatile u32 DENALI_PHY_643;
+ volatile u32 DENALI_PHY_644;
+ volatile u32 DENALI_PHY_645;
+ volatile u32 DENALI_PHY_646;
+ volatile u32 DENALI_PHY_647;
+ volatile u32 DENALI_PHY_648;
+ volatile u32 DENALI_PHY_649;
+ volatile u32 DENALI_PHY_650;
+ volatile u32 DENALI_PHY_651;
+ volatile char pad__4[0x1D0U];
+ volatile u32 DENALI_PHY_768;
+ volatile u32 DENALI_PHY_769;
+ volatile u32 DENALI_PHY_770;
+ volatile u32 DENALI_PHY_771;
+ volatile u32 DENALI_PHY_772;
+ volatile u32 DENALI_PHY_773;
+ volatile u32 DENALI_PHY_774;
+ volatile u32 DENALI_PHY_775;
+ volatile u32 DENALI_PHY_776;
+ volatile u32 DENALI_PHY_777;
+ volatile u32 DENALI_PHY_778;
+ volatile u32 DENALI_PHY_779;
+ volatile u32 DENALI_PHY_780;
+ volatile u32 DENALI_PHY_781;
+ volatile u32 DENALI_PHY_782;
+ volatile u32 DENALI_PHY_783;
+ volatile u32 DENALI_PHY_784;
+ volatile u32 DENALI_PHY_785;
+ volatile u32 DENALI_PHY_786;
+ volatile u32 DENALI_PHY_787;
+ volatile u32 DENALI_PHY_788;
+ volatile u32 DENALI_PHY_789;
+ volatile u32 DENALI_PHY_790;
+ volatile u32 DENALI_PHY_791;
+ volatile u32 DENALI_PHY_792;
+ volatile u32 DENALI_PHY_793;
+ volatile u32 DENALI_PHY_794;
+ volatile u32 DENALI_PHY_795;
+ volatile u32 DENALI_PHY_796;
+ volatile u32 DENALI_PHY_797;
+ volatile u32 DENALI_PHY_798;
+ volatile u32 DENALI_PHY_799;
+ volatile u32 DENALI_PHY_800;
+ volatile u32 DENALI_PHY_801;
+ volatile u32 DENALI_PHY_802;
+ volatile u32 DENALI_PHY_803;
+ volatile u32 DENALI_PHY_804;
+ volatile u32 DENALI_PHY_805;
+ volatile u32 DENALI_PHY_806;
+ volatile u32 DENALI_PHY_807;
+ volatile u32 DENALI_PHY_808;
+ volatile u32 DENALI_PHY_809;
+ volatile u32 DENALI_PHY_810;
+ volatile u32 DENALI_PHY_811;
+ volatile u32 DENALI_PHY_812;
+ volatile u32 DENALI_PHY_813;
+ volatile u32 DENALI_PHY_814;
+ volatile u32 DENALI_PHY_815;
+ volatile u32 DENALI_PHY_816;
+ volatile u32 DENALI_PHY_817;
+ volatile u32 DENALI_PHY_818;
+ volatile u32 DENALI_PHY_819;
+ volatile u32 DENALI_PHY_820;
+ volatile u32 DENALI_PHY_821;
+ volatile u32 DENALI_PHY_822;
+ volatile u32 DENALI_PHY_823;
+ volatile u32 DENALI_PHY_824;
+ volatile u32 DENALI_PHY_825;
+ volatile u32 DENALI_PHY_826;
+ volatile u32 DENALI_PHY_827;
+ volatile u32 DENALI_PHY_828;
+ volatile u32 DENALI_PHY_829;
+ volatile u32 DENALI_PHY_830;
+ volatile u32 DENALI_PHY_831;
+ volatile u32 DENALI_PHY_832;
+ volatile u32 DENALI_PHY_833;
+ volatile u32 DENALI_PHY_834;
+ volatile u32 DENALI_PHY_835;
+ volatile u32 DENALI_PHY_836;
+ volatile u32 DENALI_PHY_837;
+ volatile u32 DENALI_PHY_838;
+ volatile u32 DENALI_PHY_839;
+ volatile u32 DENALI_PHY_840;
+ volatile u32 DENALI_PHY_841;
+ volatile u32 DENALI_PHY_842;
+ volatile u32 DENALI_PHY_843;
+ volatile u32 DENALI_PHY_844;
+ volatile u32 DENALI_PHY_845;
+ volatile u32 DENALI_PHY_846;
+ volatile u32 DENALI_PHY_847;
+ volatile u32 DENALI_PHY_848;
+ volatile u32 DENALI_PHY_849;
+ volatile u32 DENALI_PHY_850;
+ volatile u32 DENALI_PHY_851;
+ volatile u32 DENALI_PHY_852;
+ volatile u32 DENALI_PHY_853;
+ volatile u32 DENALI_PHY_854;
+ volatile u32 DENALI_PHY_855;
+ volatile u32 DENALI_PHY_856;
+ volatile u32 DENALI_PHY_857;
+ volatile u32 DENALI_PHY_858;
+ volatile u32 DENALI_PHY_859;
+ volatile u32 DENALI_PHY_860;
+ volatile u32 DENALI_PHY_861;
+ volatile u32 DENALI_PHY_862;
+ volatile u32 DENALI_PHY_863;
+ volatile u32 DENALI_PHY_864;
+ volatile u32 DENALI_PHY_865;
+ volatile u32 DENALI_PHY_866;
+ volatile u32 DENALI_PHY_867;
+ volatile u32 DENALI_PHY_868;
+ volatile u32 DENALI_PHY_869;
+ volatile u32 DENALI_PHY_870;
+ volatile u32 DENALI_PHY_871;
+ volatile u32 DENALI_PHY_872;
+ volatile u32 DENALI_PHY_873;
+ volatile u32 DENALI_PHY_874;
+ volatile u32 DENALI_PHY_875;
+ volatile u32 DENALI_PHY_876;
+ volatile u32 DENALI_PHY_877;
+ volatile u32 DENALI_PHY_878;
+ volatile u32 DENALI_PHY_879;
+ volatile u32 DENALI_PHY_880;
+ volatile u32 DENALI_PHY_881;
+ volatile u32 DENALI_PHY_882;
+ volatile u32 DENALI_PHY_883;
+ volatile u32 DENALI_PHY_884;
+ volatile u32 DENALI_PHY_885;
+ volatile u32 DENALI_PHY_886;
+ volatile u32 DENALI_PHY_887;
+ volatile u32 DENALI_PHY_888;
+ volatile u32 DENALI_PHY_889;
+ volatile u32 DENALI_PHY_890;
+ volatile u32 DENALI_PHY_891;
+ volatile u32 DENALI_PHY_892;
+ volatile u32 DENALI_PHY_893;
+ volatile u32 DENALI_PHY_894;
+ volatile u32 DENALI_PHY_895;
+ volatile u32 DENALI_PHY_896;
+ volatile u32 DENALI_PHY_897;
+ volatile u32 DENALI_PHY_898;
+ volatile u32 DENALI_PHY_899;
+ volatile u32 DENALI_PHY_900;
+ volatile u32 DENALI_PHY_901;
+ volatile u32 DENALI_PHY_902;
+ volatile u32 DENALI_PHY_903;
+ volatile u32 DENALI_PHY_904;
+ volatile u32 DENALI_PHY_905;
+ volatile u32 DENALI_PHY_906;
+ volatile u32 DENALI_PHY_907;
+ volatile char pad__5[0x1D0U];
+ volatile u32 DENALI_PHY_1024;
+ volatile u32 DENALI_PHY_1025;
+ volatile u32 DENALI_PHY_1026;
+ volatile u32 DENALI_PHY_1027;
+ volatile u32 DENALI_PHY_1028;
+ volatile u32 DENALI_PHY_1029;
+ volatile u32 DENALI_PHY_1030;
+ volatile u32 DENALI_PHY_1031;
+ volatile u32 DENALI_PHY_1032;
+ volatile u32 DENALI_PHY_1033;
+ volatile u32 DENALI_PHY_1034;
+ volatile u32 DENALI_PHY_1035;
+ volatile u32 DENALI_PHY_1036;
+ volatile u32 DENALI_PHY_1037;
+ volatile u32 DENALI_PHY_1038;
+ volatile u32 DENALI_PHY_1039;
+ volatile u32 DENALI_PHY_1040;
+ volatile u32 DENALI_PHY_1041;
+ volatile u32 DENALI_PHY_1042;
+ volatile u32 DENALI_PHY_1043;
+ volatile u32 DENALI_PHY_1044;
+ volatile u32 DENALI_PHY_1045;
+ volatile u32 DENALI_PHY_1046;
+ volatile u32 DENALI_PHY_1047;
+ volatile u32 DENALI_PHY_1048;
+ volatile u32 DENALI_PHY_1049;
+ volatile u32 DENALI_PHY_1050;
+ volatile u32 DENALI_PHY_1051;
+ volatile u32 DENALI_PHY_1052;
+ volatile u32 DENALI_PHY_1053;
+ volatile u32 DENALI_PHY_1054;
+ volatile u32 DENALI_PHY_1055;
+ volatile u32 DENALI_PHY_1056;
+ volatile u32 DENALI_PHY_1057;
+ volatile u32 DENALI_PHY_1058;
+ volatile u32 DENALI_PHY_1059;
+ volatile u32 DENALI_PHY_1060;
+ volatile u32 DENALI_PHY_1061;
+ volatile u32 DENALI_PHY_1062;
+ volatile u32 DENALI_PHY_1063;
+ volatile u32 DENALI_PHY_1064;
+ volatile u32 DENALI_PHY_1065;
+ volatile u32 DENALI_PHY_1066;
+ volatile u32 DENALI_PHY_1067;
+ volatile u32 DENALI_PHY_1068;
+ volatile u32 DENALI_PHY_1069;
+ volatile u32 DENALI_PHY_1070;
+ volatile u32 DENALI_PHY_1071;
+ volatile u32 DENALI_PHY_1072;
+ volatile u32 DENALI_PHY_1073;
+ volatile u32 DENALI_PHY_1074;
+ volatile u32 DENALI_PHY_1075;
+ volatile char pad__6[0x330U];
+ volatile u32 DENALI_PHY_1280;
+ volatile u32 DENALI_PHY_1281;
+ volatile u32 DENALI_PHY_1282;
+ volatile u32 DENALI_PHY_1283;
+ volatile u32 DENALI_PHY_1284;
+ volatile u32 DENALI_PHY_1285;
+ volatile u32 DENALI_PHY_1286;
+ volatile u32 DENALI_PHY_1287;
+ volatile u32 DENALI_PHY_1288;
+ volatile u32 DENALI_PHY_1289;
+ volatile u32 DENALI_PHY_1290;
+ volatile u32 DENALI_PHY_1291;
+ volatile u32 DENALI_PHY_1292;
+ volatile u32 DENALI_PHY_1293;
+ volatile u32 DENALI_PHY_1294;
+ volatile u32 DENALI_PHY_1295;
+ volatile u32 DENALI_PHY_1296;
+ volatile u32 DENALI_PHY_1297;
+ volatile u32 DENALI_PHY_1298;
+ volatile u32 DENALI_PHY_1299;
+ volatile u32 DENALI_PHY_1300;
+ volatile u32 DENALI_PHY_1301;
+ volatile u32 DENALI_PHY_1302;
+ volatile u32 DENALI_PHY_1303;
+ volatile u32 DENALI_PHY_1304;
+ volatile u32 DENALI_PHY_1305;
+ volatile u32 DENALI_PHY_1306;
+ volatile u32 DENALI_PHY_1307;
+ volatile u32 DENALI_PHY_1308;
+ volatile u32 DENALI_PHY_1309;
+ volatile u32 DENALI_PHY_1310;
+ volatile u32 DENALI_PHY_1311;
+ volatile u32 DENALI_PHY_1312;
+ volatile u32 DENALI_PHY_1313;
+ volatile u32 DENALI_PHY_1314;
+ volatile u32 DENALI_PHY_1315;
+ volatile u32 DENALI_PHY_1316;
+ volatile u32 DENALI_PHY_1317;
+ volatile u32 DENALI_PHY_1318;
+ volatile u32 DENALI_PHY_1319;
+ volatile u32 DENALI_PHY_1320;
+ volatile u32 DENALI_PHY_1321;
+ volatile u32 DENALI_PHY_1322;
+ volatile u32 DENALI_PHY_1323;
+ volatile u32 DENALI_PHY_1324;
+ volatile u32 DENALI_PHY_1325;
+ volatile u32 DENALI_PHY_1326;
+ volatile u32 DENALI_PHY_1327;
+ volatile u32 DENALI_PHY_1328;
+ volatile u32 DENALI_PHY_1329;
+ volatile u32 DENALI_PHY_1330;
+ volatile u32 DENALI_PHY_1331;
+ volatile u32 DENALI_PHY_1332;
+ volatile u32 DENALI_PHY_1333;
+ volatile u32 DENALI_PHY_1334;
+ volatile u32 DENALI_PHY_1335;
+ volatile u32 DENALI_PHY_1336;
+ volatile u32 DENALI_PHY_1337;
+ volatile u32 DENALI_PHY_1338;
+ volatile u32 DENALI_PHY_1339;
+ volatile u32 DENALI_PHY_1340;
+ volatile u32 DENALI_PHY_1341;
+ volatile u32 DENALI_PHY_1342;
+ volatile u32 DENALI_PHY_1343;
+ volatile u32 DENALI_PHY_1344;
+ volatile u32 DENALI_PHY_1345;
+ volatile u32 DENALI_PHY_1346;
+ volatile u32 DENALI_PHY_1347;
+ volatile u32 DENALI_PHY_1348;
+ volatile u32 DENALI_PHY_1349;
+ volatile u32 DENALI_PHY_1350;
+ volatile u32 DENALI_PHY_1351;
+ volatile u32 DENALI_PHY_1352;
+ volatile u32 DENALI_PHY_1353;
+ volatile u32 DENALI_PHY_1354;
+ volatile u32 DENALI_PHY_1355;
+ volatile u32 DENALI_PHY_1356;
+ volatile u32 DENALI_PHY_1357;
+ volatile u32 DENALI_PHY_1358;
+ volatile u32 DENALI_PHY_1359;
+ volatile u32 DENALI_PHY_1360;
+ volatile u32 DENALI_PHY_1361;
+ volatile u32 DENALI_PHY_1362;
+ volatile u32 DENALI_PHY_1363;
+ volatile u32 DENALI_PHY_1364;
+ volatile u32 DENALI_PHY_1365;
+ volatile u32 DENALI_PHY_1366;
+ volatile u32 DENALI_PHY_1367;
+ volatile u32 DENALI_PHY_1368;
+ volatile u32 DENALI_PHY_1369;
+ volatile u32 DENALI_PHY_1370;
+ volatile u32 DENALI_PHY_1371;
+ volatile u32 DENALI_PHY_1372;
+ volatile u32 DENALI_PHY_1373;
+ volatile u32 DENALI_PHY_1374;
+ volatile u32 DENALI_PHY_1375;
+ volatile u32 DENALI_PHY_1376;
+ volatile u32 DENALI_PHY_1377;
+ volatile u32 DENALI_PHY_1378;
+ volatile u32 DENALI_PHY_1379;
+ volatile u32 DENALI_PHY_1380;
+ volatile u32 DENALI_PHY_1381;
+ volatile u32 DENALI_PHY_1382;
+ volatile u32 DENALI_PHY_1383;
+ volatile u32 DENALI_PHY_1384;
+ volatile u32 DENALI_PHY_1385;
+ volatile u32 DENALI_PHY_1386;
+ volatile u32 DENALI_PHY_1387;
+ volatile u32 DENALI_PHY_1388;
+ volatile u32 DENALI_PHY_1389;
+ volatile u32 DENALI_PHY_1390;
+ volatile u32 DENALI_PHY_1391;
+ volatile u32 DENALI_PHY_1392;
+ volatile u32 DENALI_PHY_1393;
+ volatile u32 DENALI_PHY_1394;
+ volatile u32 DENALI_PHY_1395;
+ volatile u32 DENALI_PHY_1396;
+ volatile u32 DENALI_PHY_1397;
+ volatile u32 DENALI_PHY_1398;
+ volatile u32 DENALI_PHY_1399;
+ volatile u32 DENALI_PHY_1400;
+ volatile u32 DENALI_PHY_1401;
+ volatile u32 DENALI_PHY_1402;
+ volatile u32 DENALI_PHY_1403;
+ volatile u32 DENALI_PHY_1404;
+ volatile u32 DENALI_PHY_1405;
+ volatile u32 DENALI_PHY_1406;
+ volatile u32 DENALI_PHY_1407;
+ volatile u32 DENALI_PHY_1408;
+ volatile u32 DENALI_PHY_1409;
+ volatile u32 DENALI_PHY_1410;
+ volatile u32 DENALI_PHY_1411;
+ volatile u32 DENALI_PHY_1412;
+ volatile u32 DENALI_PHY_1413;
+ volatile u32 DENALI_PHY_1414;
+ volatile u32 DENALI_PHY_1415;
+ volatile u32 DENALI_PHY_1416;
+ volatile u32 DENALI_PHY_1417;
+ volatile u32 DENALI_PHY_1418;
+ volatile u32 DENALI_PHY_1419;
+ volatile u32 DENALI_PHY_1420;
+ volatile u32 DENALI_PHY_1421;
+ volatile u32 DENALI_PHY_1422;
+} lpddr4_ctlregs;
+
+#endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
new file mode 100644
index 0000000..7112294
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_RW_MASKS_H_
+#define LPDDR4_RW_MASKS_H_
+
+#include <stdint.h>
+
+extern u32 g_lpddr4_ddr_controller_rw_mask[459];
+extern u32 g_lpddr4_pi_rw_mask[300];
+extern u32 g_lpddr4_data_slice_0_rw_mask[140];
+extern u32 g_lpddr4_data_slice_1_rw_mask[140];
+extern u32 g_lpddr4_data_slice_2_rw_mask[140];
+extern u32 g_lpddr4_data_slice_3_rw_mask[140];
+extern u32 g_lpddr4_address_slice_0_rw_mask[52];
+extern u32 g_lpddr4_phy_core_rw_mask[143];
+
+#endif /* LPDDR4_RW_MASKS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
similarity index 64%
rename from drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
rename to drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
index 3208b1c..ad45dd9 100644
--- a/drivers/ram/k3-j721e/lpddr4_data_slice_0_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
@@ -1,17 +1,16 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
*
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_
-#define LPDDR4__DENALI_PHY_0_READ_MASK 0x000F07FFU
-#define LPDDR4__DENALI_PHY_0_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_0_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_0_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH 11U
@@ -24,8 +23,8 @@
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_0
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_0__PHY_IO_PAD_DELAY_TIMING_BYPASS_0
-#define LPDDR4__DENALI_PHY_1_READ_MASK 0x000703FFU
-#define LPDDR4__DENALI_PHY_1_WRITE_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_1_READ_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_1_WRITE_MASK 0x000703FFU
#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH 10U
@@ -38,8 +37,8 @@
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0
-#define LPDDR4__DENALI_PHY_2_READ_MASK 0x010303FFU
-#define LPDDR4__DENALI_PHY_2_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_2_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_2_WRITE_MASK 0x010303FFU
#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH 10U
@@ -53,82 +52,82 @@
#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0
#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET 0U
#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2
#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0
-#define LPDDR4__DENALI_PHY_3_READ_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_3_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_WRITE_MASK 0x3F3F3F3FU
#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3
#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0
#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3
#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0
#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3
#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0
#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3
#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0
-#define LPDDR4__DENALI_PHY_4_READ_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_4_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_WRITE_MASK 0x3F3F3F3FU
#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4
#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0
#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4
#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0
#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4
#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0
#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4
#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0
-#define LPDDR4__DENALI_PHY_5_READ_MASK 0x01030F3FU
-#define LPDDR4__DENALI_PHY_5_WRITE_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_5_READ_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_5_WRITE_MASK 0x01030F3FU
#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH 6U
#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5
#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0
#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH 4U
#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5
#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0
#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0_WIDTH 2U
#define LPDDR4__PHY_PER_RANK_CS_MAP_0__REG DENALI_PHY_5
#define LPDDR4__PHY_PER_RANK_CS_MAP_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_RANK_CS_MAP_0
@@ -140,8 +139,8 @@
#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__REG DENALI_PHY_5
#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_0__FLD LPDDR4__DENALI_PHY_5__PHY_PER_CS_TRAINING_MULTICAST_EN_0
-#define LPDDR4__DENALI_PHY_6_READ_MASK 0x1F1F0301U
-#define LPDDR4__DENALI_PHY_6_WRITE_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6_READ_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_6_WRITE_MASK 0x1F1F0301U
#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_6__PHY_PER_CS_TRAINING_INDEX_0_WIDTH 1U
@@ -168,11 +167,11 @@
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0
-#define LPDDR4__DENALI_PHY_7_READ_MASK 0x1F030F0FU
-#define LPDDR4__DENALI_PHY_7_WRITE_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7_READ_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_7_WRITE_MASK 0x1F030F0FU
#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH 4U
#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_7
#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RPTR_UPDATE_0
@@ -194,55 +193,55 @@
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0
-#define LPDDR4__DENALI_PHY_8_READ_MASK 0x0101FF03U
-#define LPDDR4__DENALI_PHY_8_WRITE_MASK 0x0101FF03U
-#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_8_READ_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_8_WRITE_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0_WIDTH 2U
#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_8
#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_CTRL_LPBK_EN_0
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0_WIDTH 9U
#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_8
#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_CONTROL_0
#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET 0U
#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8
#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0
-#define LPDDR4__DENALI_PHY_9_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_9_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH 32U
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0
-#define LPDDR4__DENALI_PHY_10_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_10_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH 28U
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0
-#define LPDDR4__DENALI_PHY_11_READ_MASK 0x0101FF7FU
-#define LPDDR4__DENALI_PHY_11_WRITE_MASK 0x0101FF7FU
+#define LPDDR4__DENALI_PHY_11_READ_MASK 0x0101FF7FU
+#define LPDDR4__DENALI_PHY_11_WRITE_MASK 0x0101FF7FU
#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH 7U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH 7U
#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11
#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0
#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0_WIDTH 9U
#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_11
#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_MASK_0
@@ -254,8 +253,8 @@
#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_11
#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_RDLVL_MULTI_PATT_ENABLE_0
-#define LPDDR4__DENALI_PHY_12_READ_MASK 0x007F3F01U
-#define LPDDR4__DENALI_PHY_12_WRITE_MASK 0x007F3F01U
+#define LPDDR4__DENALI_PHY_12_READ_MASK 0x007F3F01U
+#define LPDDR4__DENALI_PHY_12_WRITE_MASK 0x007F3F01U
#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH 1U
@@ -271,13 +270,13 @@
#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_INITIAL_STEPSIZE_0
#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_MASK 0x007F0000U
-#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_WIDTH 7U
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0_WIDTH 7U
#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_12
#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_12__PHY_VREF_TRAIN_OBS_0
-#define LPDDR4__DENALI_PHY_13_READ_MASK 0x000F03FFU
-#define LPDDR4__DENALI_PHY_13_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_13_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_13_WRITE_MASK 0x000F03FFU
#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH 10U
@@ -291,37 +290,37 @@
#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_13__PHY_GATE_ERROR_DELAY_SELECT_0
#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0_WOSET 0U
#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_13
#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_13__SC_PHY_SNAP_OBS_REGS_0
-#define LPDDR4__DENALI_PHY_14_READ_MASK 0x070101FFU
-#define LPDDR4__DENALI_PHY_14_WRITE_MASK 0x070101FFU
+#define LPDDR4__DENALI_PHY_14_READ_MASK 0x070101FFU
+#define LPDDR4__DENALI_PHY_14_WRITE_MASK 0x070101FFU
#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH 9U
#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14
#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_14__PHY_LPDDR_0_WOSET 0U
#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_14
#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_14__PHY_LPDDR_0
-#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0_WIDTH 3U
#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_14
#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_14__PHY_MEM_CLASS_0
-#define LPDDR4__DENALI_PHY_15_READ_MASK 0x000301FFU
-#define LPDDR4__DENALI_PHY_15_WRITE_MASK 0x000301FFU
+#define LPDDR4__DENALI_PHY_15_READ_MASK 0x000301FFU
+#define LPDDR4__DENALI_PHY_15_WRITE_MASK 0x000301FFU
#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH 9U
@@ -329,101 +328,101 @@
#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0_WIDTH 2U
#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_15
#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_15__ON_FLY_GATE_ADJUST_EN_0
-#define LPDDR4__DENALI_PHY_16_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_16_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_16_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_16_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0_WIDTH 32U
#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_16
#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_16__PHY_GATE_TRACKING_OBS_0
-#define LPDDR4__DENALI_PHY_17_READ_MASK 0x00000301U
-#define LPDDR4__DENALI_PHY_17_WRITE_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_17_READ_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_17_WRITE_MASK 0x00000301U
#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0_WOSET 0U
#define LPDDR4__PHY_DFI40_POLARITY_0__REG DENALI_PHY_17
#define LPDDR4__PHY_DFI40_POLARITY_0__FLD LPDDR4__DENALI_PHY_17__PHY_DFI40_POLARITY_0
#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0_WIDTH 2U
#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_17
#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_17__PHY_LP4_PST_AMBLE_0
-#define LPDDR4__DENALI_PHY_18_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_18_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_18_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_18
#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_18__PHY_RDLVL_PATT8_0
-#define LPDDR4__DENALI_PHY_19_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_19_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_19_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_19
#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT9_0
-#define LPDDR4__DENALI_PHY_20_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_20_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_20
#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT10_0
-#define LPDDR4__DENALI_PHY_21_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_21_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_21
#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT11_0
-#define LPDDR4__DENALI_PHY_22_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_22_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_22
#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT12_0
-#define LPDDR4__DENALI_PHY_23_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_23_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_23
#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT13_0
-#define LPDDR4__DENALI_PHY_24_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_24_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_24
#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT14_0
-#define LPDDR4__DENALI_PHY_25_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_25_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_25
#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT15_0
-#define LPDDR4__DENALI_PHY_26_READ_MASK 0x070F0107U
-#define LPDDR4__DENALI_PHY_26_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_26_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_26_WRITE_MASK 0x070F0107U
#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_26__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH 3U
@@ -446,12 +445,12 @@
#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_MASK 0x07000000U
#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH 3U
#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_26
#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDDQ_ENC_OBS_SELECT_0
-#define LPDDR4__DENALI_PHY_27_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_27_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_27_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_27_WRITE_MASK 0x0F0F0F0FU
#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH 4U
@@ -459,110 +458,110 @@
#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQS_DQ_ENC_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0_WIDTH 4U
#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_27
#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_ENC_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH 4U
#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_27
#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_WR_SHIFT_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_MASK 0x0F000000U
#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH 4U
#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_27
#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_FIFO_PTR_OBS_SELECT_0
-#define LPDDR4__DENALI_PHY_28_READ_MASK 0xFF030001U
-#define LPDDR4__DENALI_PHY_28_WRITE_MASK 0xFF030001U
+#define LPDDR4__DENALI_PHY_28_READ_MASK 0xFF030001U
+#define LPDDR4__DENALI_PHY_28_WRITE_MASK 0xFF030001U
#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0_WOSET 0U
#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_28
#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_28__PHY_LVL_DEBUG_MODE_0
#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0_WOSET 0U
#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_28
#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_28__SC_PHY_LVL_DEBUG_CONT_0
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0_WIDTH 2U
#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_28
#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_ALGO_0
#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0_WIDTH 8U
#define LPDDR4__PHY_WRLVL_PER_START_0__REG DENALI_PHY_28
#define LPDDR4__PHY_WRLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_28__PHY_WRLVL_PER_START_0
-#define LPDDR4__DENALI_PHY_29_READ_MASK 0x00FF0F3FU
-#define LPDDR4__DENALI_PHY_29_WRITE_MASK 0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_29_READ_MASK 0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_29_WRITE_MASK 0x00FF0F3FU
#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH 6U
#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29
#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0
#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH 4U
#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_29
#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_UPDT_WAIT_CNT_0
-#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0_WIDTH 8U
#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_29
#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_29__PHY_DQ_MASK_0
-#define LPDDR4__DENALI_PHY_30_READ_MASK 0x0F3F03FFU
-#define LPDDR4__DENALI_PHY_30_WRITE_MASK 0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_30_READ_MASK 0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_30_WRITE_MASK 0x0F3F03FFU
#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0_WIDTH 10U
#define LPDDR4__PHY_GTLVL_PER_START_0__REG DENALI_PHY_30
#define LPDDR4__PHY_GTLVL_PER_START_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_PER_START_0
#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH 6U
#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30
#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0
#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK 0x0F000000U
#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH 4U
#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0
-#define LPDDR4__DENALI_PHY_31_READ_MASK 0x1F030F3FU
-#define LPDDR4__DENALI_PHY_31_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31_WRITE_MASK 0x1F030F3FU
#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH 6U
#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31
#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0
#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH 4U
#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0
#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH 2U
#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31
#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0
@@ -572,8 +571,8 @@
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0
-#define LPDDR4__DENALI_PHY_32_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_32_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_32_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_32_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0_WIDTH 8U
@@ -581,8 +580,8 @@
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_PERIODIC_OBS_SELECT_0
#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH 8U
#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32
#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0
@@ -593,16 +592,16 @@
#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0_WIDTH 6U
#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_32
#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_32__PHY_WDQLVL_BURST_CNT_0
-#define LPDDR4__DENALI_PHY_33_READ_MASK 0x0F07FF07U
-#define LPDDR4__DENALI_PHY_33_WRITE_MASK 0x0F07FF07U
-#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_33_READ_MASK 0x0F07FF07U
+#define LPDDR4__DENALI_PHY_33_WRITE_MASK 0x0F07FF07U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH 3U
#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33
#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0
@@ -618,8 +617,8 @@
#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_33
#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_UPDT_WAIT_CNT_0
-#define LPDDR4__DENALI_PHY_34_READ_MASK 0x0000FF0FU
-#define LPDDR4__DENALI_PHY_34_WRITE_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PHY_34_READ_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PHY_34_WRITE_MASK 0x0000FF0FU
#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH 4U
@@ -640,66 +639,66 @@
#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_34
#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_34__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0
-#define LPDDR4__DENALI_PHY_35_READ_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_35_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_35_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_35_WRITE_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0_WIDTH 9U
#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_35
#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DATADM_MASK_0
-#define LPDDR4__DENALI_PHY_36_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_36_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_36_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_36_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0_WIDTH 32U
#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_36
#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_36__PHY_USER_PATT0_0
-#define LPDDR4__DENALI_PHY_37_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_37_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_37_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0_WIDTH 32U
#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_37
#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT1_0
-#define LPDDR4__DENALI_PHY_38_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_38_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_38_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0_WIDTH 32U
#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_38
#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT2_0
-#define LPDDR4__DENALI_PHY_39_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_39_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_39_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0_WIDTH 32U
#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_39
#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT3_0
-#define LPDDR4__DENALI_PHY_40_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_40_WRITE_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_WIDTH 16U
+#define LPDDR4__DENALI_PHY_40_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_40_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0_WIDTH 16U
#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_40
#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT4_0
#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0_WOSET 0U
#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_40
#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_40__PHY_NTP_MULT_TRAIN_0
-#define LPDDR4__DENALI_PHY_41_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_41_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_41_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_41_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0_WIDTH 10U
#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_41
#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_EARLY_THRESHOLD_0
@@ -710,8 +709,8 @@
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_41
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_PERIOD_THRESHOLD_0
-#define LPDDR4__DENALI_PHY_42_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_42_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH 10U
@@ -724,8 +723,8 @@
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_42
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_MAX_0
-#define LPDDR4__DENALI_PHY_43_READ_MASK 0x00FF0001U
-#define LPDDR4__DENALI_PHY_43_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_43_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_43_WRITE_MASK 0x00FF0001U
#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH 1U
@@ -735,27 +734,27 @@
#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_43__PHY_CALVL_VREF_DRIVING_SLICE_0
#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0_WIDTH 6U
#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_43
#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_43__SC_PHY_MANUAL_CLEAR_0
#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0_WIDTH 8U
#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_43
#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_43__PHY_FIFO_PTR_OBS_0
-#define LPDDR4__DENALI_PHY_44_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_44_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_44_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_44_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0_WIDTH 32U
#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_44
#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_LPBK_RESULT_OBS_0
-#define LPDDR4__DENALI_PHY_45_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_45_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_45_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_45_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_45__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH 16U
@@ -768,8 +767,8 @@
#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_45
#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_MASTER_DLY_LOCK_OBS_0
-#define LPDDR4__DENALI_PHY_46_READ_MASK 0xFFFF7F7FU
-#define LPDDR4__DENALI_PHY_46_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_46_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_46_WRITE_MASK 0xFFFF7F7FU
#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_46__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH 7U
@@ -784,7 +783,7 @@
#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_MASK 0x00FF0000U
#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH 8U
#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_46
#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_46__PHY_MEAS_DLY_STEP_VALUE_0
@@ -794,8 +793,8 @@
#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_46
#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0
-#define LPDDR4__DENALI_PHY_47_READ_MASK 0x7F07FFFFU
-#define LPDDR4__DENALI_PHY_47_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_47_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_47_WRITE_MASK 0x7F07FFFFU
#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
@@ -814,8 +813,8 @@
#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0
-#define LPDDR4__DENALI_PHY_48_READ_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_PHY_48_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_48_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_48_WRITE_MASK 0x0007FFFFU
#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_48__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH 8U
@@ -829,13 +828,13 @@
#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0
#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_MASK 0x00070000U
-#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0_WIDTH 3U
#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_48
#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WR_SHIFT_OBS_0
-#define LPDDR4__DENALI_PHY_49_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_49_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_49_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_49_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH 10U
@@ -848,16 +847,16 @@
#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_49
#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRLVL_HARD1_DELAY_OBS_0
-#define LPDDR4__DENALI_PHY_50_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_50_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_50_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_50_WRITE_MASK 0x0001FFFFU
#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_WIDTH 17U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0_WIDTH 17U
#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_50
#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_STATUS_OBS_0
-#define LPDDR4__DENALI_PHY_51_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_51_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_51_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH 10U
@@ -870,11 +869,11 @@
#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_51
#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0
-#define LPDDR4__DENALI_PHY_52_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_52_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_52_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_52_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_WIDTH 16U
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0_WIDTH 16U
#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG DENALI_PHY_52
#define LPDDR4__PHY_WRLVL_ERROR_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_WRLVL_ERROR_OBS_0
@@ -884,24 +883,24 @@
#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_52
#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GTLVL_HARD0_DELAY_OBS_0
-#define LPDDR4__DENALI_PHY_53_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_53_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_53_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_53_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH 14U
#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53
#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0
-#define LPDDR4__DENALI_PHY_54_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_54_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH 18U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH 18U
#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54
#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0
-#define LPDDR4__DENALI_PHY_55_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_55_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH 10U
@@ -914,32 +913,32 @@
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0
-#define LPDDR4__DENALI_PHY_56_READ_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_56_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_56_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_56_WRITE_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH 2U
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0
-#define LPDDR4__DENALI_PHY_57_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_57_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57
#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0
-#define LPDDR4__DENALI_PHY_58_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_58_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_58_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_58_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__REG DENALI_PHY_58
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_RDLVL_PERIODIC_OBS_0
-#define LPDDR4__DENALI_PHY_59_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_59_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_59_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_59_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH 11U
@@ -952,56 +951,56 @@
#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_59
#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_DQDM_TE_DLY_OBS_0
-#define LPDDR4__DENALI_PHY_60_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_60_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0_WIDTH 32U
#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_60
#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_STATUS_OBS_0
-#define LPDDR4__DENALI_PHY_61_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_61_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_61_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH 32U
#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_61
#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_61__PHY_WDQLVL_PERIODIC_OBS_0
-#define LPDDR4__DENALI_PHY_62_READ_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_62_WRITE_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_WIDTH 31U
+#define LPDDR4__DENALI_PHY_62_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_62_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0_WIDTH 31U
#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_62
#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MODE_0
-#define LPDDR4__DENALI_PHY_63_READ_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_63_WRITE_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_63_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_63_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0_WIDTH 6U
#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_63
#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_MASK_0
-#define LPDDR4__DENALI_PHY_64_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_64_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0_WIDTH 32U
#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_64
#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_OBS_0
-#define LPDDR4__DENALI_PHY_65_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_65_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_65_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH 32U
#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_65
#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TEST_MSTR_DLY_OBS_0
-#define LPDDR4__DENALI_PHY_66_READ_MASK 0x010001FFU
-#define LPDDR4__DENALI_PHY_66_WRITE_MASK 0x010001FFU
+#define LPDDR4__DENALI_PHY_66_READ_MASK 0x010001FFU
+#define LPDDR4__DENALI_PHY_66_WRITE_MASK 0x010001FFU
#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH 8U
@@ -1009,34 +1008,34 @@
#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_66__PHY_DDL_TRACK_UPD_THRESHOLD_0
#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0_WOSET 0U
#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_66
#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_66__PHY_LP4_WDQS_OE_EXTEND_0
#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0_WOSET 0U
#define LPDDR4__SC_PHY_RX_CAL_START_0__REG DENALI_PHY_66
#define LPDDR4__SC_PHY_RX_CAL_START_0__FLD LPDDR4__DENALI_PHY_66__SC_PHY_RX_CAL_START_0
#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0_WOSET 0U
#define LPDDR4__PHY_RX_CAL_OVERRIDE_0__REG DENALI_PHY_66
#define LPDDR4__PHY_RX_CAL_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_OVERRIDE_0
-#define LPDDR4__DENALI_PHY_67_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_67_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_WRITE_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0_WIDTH 8U
#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_67
#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_SAMPLE_WAIT_0
@@ -1048,147 +1047,147 @@
#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__REG DENALI_PHY_67
#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0__FLD LPDDR4__DENALI_PHY_67__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_0
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_67
#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ0_0
-#define LPDDR4__DENALI_PHY_68_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_68_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_68_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_68
#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ1_0
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_68
#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ2_0
-#define LPDDR4__DENALI_PHY_69_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_69_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_69_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_69
#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ3_0
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_69
#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ4_0
-#define LPDDR4__DENALI_PHY_70_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_70_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_70_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_70
#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ5_0
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_70
#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DQ6_0
-#define LPDDR4__DENALI_PHY_71_READ_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_71_WRITE_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_71_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_71_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_71
#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQ7_0
-#define LPDDR4__DENALI_PHY_72_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_72_WRITE_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH 18U
+#define LPDDR4__DENALI_PHY_72_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0_WIDTH 18U
#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_72
#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_72__PHY_RX_CAL_DM_0
-#define LPDDR4__DENALI_PHY_73_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_73_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_73_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_73
#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_DQS_0
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_73
#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_73__PHY_RX_CAL_FDBK_0
-#define LPDDR4__DENALI_PHY_74_READ_MASK 0x01FF07FFU
-#define LPDDR4__DENALI_PHY_74_WRITE_MASK 0x01FF07FFU
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_74_READ_MASK 0x01FF07FFU
+#define LPDDR4__DENALI_PHY_74_WRITE_MASK 0x01FF07FFU
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0_WIDTH 11U
#define LPDDR4__PHY_RX_CAL_OBS_0__REG DENALI_PHY_74
#define LPDDR4__PHY_RX_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_OBS_0
#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_WIDTH 9U
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG DENALI_PHY_74
#define LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_74__PHY_RX_CAL_LOCK_OBS_0
-#define LPDDR4__DENALI_PHY_75_READ_MASK 0x017F7F01U
-#define LPDDR4__DENALI_PHY_75_WRITE_MASK 0x017F7F01U
+#define LPDDR4__DENALI_PHY_75_READ_MASK 0x017F7F01U
+#define LPDDR4__DENALI_PHY_75_WRITE_MASK 0x017F7F01U
#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0_WOSET 0U
#define LPDDR4__PHY_RX_CAL_DISABLE_0__REG DENALI_PHY_75
#define LPDDR4__PHY_RX_CAL_DISABLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DISABLE_0
#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_MASK 0x00007F00U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_WIDTH 7U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0_WIDTH 7U
#define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__REG DENALI_PHY_75
#define LPDDR4__PHY_RX_CAL_SE_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_SE_ADJUST_0
#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_MASK 0x007F0000U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_WIDTH 7U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0_WIDTH 7U
#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__REG DENALI_PHY_75
#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_DIFF_ADJUST_0
#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0_WOSET 0U
#define LPDDR4__PHY_RX_CAL_COMP_VAL_0__REG DENALI_PHY_75
#define LPDDR4__PHY_RX_CAL_COMP_VAL_0__FLD LPDDR4__DENALI_PHY_75__PHY_RX_CAL_COMP_VAL_0
-#define LPDDR4__DENALI_PHY_76_READ_MASK 0x07FF0FFFU
-#define LPDDR4__DENALI_PHY_76_WRITE_MASK 0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_76_READ_MASK 0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_76_WRITE_MASK 0x07FF0FFFU
#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_WIDTH 12U
+#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0_WIDTH 12U
#define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__REG DENALI_PHY_76
#define LPDDR4__PHY_RX_CAL_INDEX_MASK_0__FLD LPDDR4__DENALI_PHY_76__PHY_RX_CAL_INDEX_MASK_0
#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0_WIDTH 11U
#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_76
#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_PAD_RX_BIAS_EN_0
-#define LPDDR4__DENALI_PHY_77_READ_MASK 0x03FFFF1FU
-#define LPDDR4__DENALI_PHY_77_WRITE_MASK 0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_77_READ_MASK 0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_77_WRITE_MASK 0x03FFFF1FU
#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0_WIDTH 5U
#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_77
#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_77__PHY_STATIC_TOG_DISABLE_0
@@ -1200,18 +1199,18 @@
#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_MASK 0x00FF0000U
#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0_WIDTH 8U
#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__REG DENALI_PHY_77
#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_CAL_TIMEOUT_0
#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_MASK 0x03000000U
-#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0_WIDTH 2U
#define LPDDR4__PHY_DATA_DC_WEIGHT_0__REG DENALI_PHY_77
#define LPDDR4__PHY_DATA_DC_WEIGHT_0__FLD LPDDR4__DENALI_PHY_77__PHY_DATA_DC_WEIGHT_0
-#define LPDDR4__DENALI_PHY_78_READ_MASK 0x01FFFF3FU
-#define LPDDR4__DENALI_PHY_78_WRITE_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_78_READ_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_78_WRITE_MASK 0x01FFFF3FU
#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_START_0_WIDTH 6U
@@ -1238,8 +1237,8 @@
#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__REG DENALI_PHY_78
#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_0__FLD LPDDR4__DENALI_PHY_78__PHY_DATA_DC_ADJUST_DIRECT_0
-#define LPDDR4__DENALI_PHY_79_READ_MASK 0x07030101U
-#define LPDDR4__DENALI_PHY_79_WRITE_MASK 0x07030101U
+#define LPDDR4__DENALI_PHY_79_READ_MASK 0x07030101U
+#define LPDDR4__DENALI_PHY_79_WRITE_MASK 0x07030101U
#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0_WIDTH 1U
@@ -1249,27 +1248,27 @@
#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_POLARITY_0
#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0_WOSET 0U
#define LPDDR4__PHY_DATA_DC_CAL_START_0__REG DENALI_PHY_79
#define LPDDR4__PHY_DATA_DC_CAL_START_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_CAL_START_0
#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0_WIDTH 2U
#define LPDDR4__PHY_DATA_DC_SW_RANK_0__REG DENALI_PHY_79
#define LPDDR4__PHY_DATA_DC_SW_RANK_0__FLD LPDDR4__DENALI_PHY_79__PHY_DATA_DC_SW_RANK_0
#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0_WIDTH 3U
#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_79
#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_79__PHY_FDBK_PWR_CTRL_0
-#define LPDDR4__DENALI_PHY_80_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PHY_80_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_80_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_80_WRITE_MASK 0x01010101U
#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH 1U
@@ -1279,10 +1278,10 @@
#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLV_DLY_CTRL_GATE_DISABLE_0
#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0_WOSET 0U
#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_80
#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_RDPATH_GATE_DISABLE_0
@@ -1302,22 +1301,22 @@
#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_80
#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_80__PHY_SLICE_PWR_RDC_DISABLE_0
-#define LPDDR4__DENALI_PHY_81_READ_MASK 0x3FFF07FFU
-#define LPDDR4__DENALI_PHY_81_WRITE_MASK 0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_81_READ_MASK 0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_81_WRITE_MASK 0x3FFF07FFU
#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0_WIDTH 11U
#define LPDDR4__PHY_PARITY_ERROR_REGIF_0__REG DENALI_PHY_81
#define LPDDR4__PHY_PARITY_ERROR_REGIF_0__FLD LPDDR4__DENALI_PHY_81__PHY_PARITY_ERROR_REGIF_0
#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_MASK 0x3FFF0000U
-#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_WIDTH 14U
+#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0_WIDTH 14U
#define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__REG DENALI_PHY_81
#define LPDDR4__PHY_DS_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_81__PHY_DS_FSM_ERROR_INFO_0
-#define LPDDR4__DENALI_PHY_82_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_82_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_82_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_82_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_82__PHY_DS_FSM_ERROR_INFO_MASK_0_WIDTH 14U
@@ -1330,8 +1329,8 @@
#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_82
#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_82__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_0
-#define LPDDR4__DENALI_PHY_83_READ_MASK 0x00001F1FU
-#define LPDDR4__DENALI_PHY_83_WRITE_MASK 0x00001F1FU
+#define LPDDR4__DENALI_PHY_83_READ_MASK 0x00001F1FU
+#define LPDDR4__DENALI_PHY_83_WRITE_MASK 0x00001F1FU
#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_83__PHY_DS_TRAIN_CALIB_ERROR_INFO_0_WIDTH 5U
@@ -1350,37 +1349,37 @@
#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__REG DENALI_PHY_83
#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_83__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_0
-#define LPDDR4__DENALI_PHY_84_READ_MASK 0x07FFFF07U
-#define LPDDR4__DENALI_PHY_84_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_84_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_84_WRITE_MASK 0x07FFFF07U
#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0_WIDTH 3U
#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_84
#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_ENABLE_0
#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_WIDTH 16U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0_WIDTH 16U
#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_84
#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQ_TSEL_SELECT_0
#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0_WIDTH 3U
#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_84
#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_84__PHY_DQS_TSEL_ENABLE_0
-#define LPDDR4__DENALI_PHY_85_READ_MASK 0x7F03FFFFU
-#define LPDDR4__DENALI_PHY_85_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_85_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_85_WRITE_MASK 0x7F03FFFFU
#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_WIDTH 16U
+#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0_WIDTH 16U
#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_85
#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_85__PHY_DQS_TSEL_SELECT_0
#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0_WIDTH 2U
#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_85
#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_85__PHY_TWO_CYC_PREAMBLE_0
@@ -1390,8 +1389,8 @@
#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_85
#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_85__PHY_VREF_INITIAL_START_POINT_0
-#define LPDDR4__DENALI_PHY_86_READ_MASK 0xFF01037FU
-#define LPDDR4__DENALI_PHY_86_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_86_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_86_WRITE_MASK 0xFF01037FU
#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH 7U
@@ -1399,50 +1398,50 @@
#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_INITIAL_STOP_POINT_0
#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0_WIDTH 2U
#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_86
#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_86__PHY_VREF_TRAINING_CTRL_0
#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0_WOSET 0U
#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_86
#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_TRAIN_EN_0
#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH 8U
#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_86
#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_86__PHY_NTP_WDQ_STEP_SIZE_0
-#define LPDDR4__DENALI_PHY_87_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_87_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_87_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_87_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0_WIDTH 11U
#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_87
#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_START_0
#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0_WIDTH 11U
#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_87
#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_87__PHY_NTP_WDQ_STOP_0
-#define LPDDR4__DENALI_PHY_88_READ_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_PHY_88_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_88_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_88_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0_WIDTH 8U
#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_88
#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_NTP_WDQ_BIT_EN_0
#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_MASK 0x0003FF00U
-#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0_WIDTH 10U
#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_88
#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_88__PHY_WDQLVL_DVW_MIN_0
@@ -1454,321 +1453,321 @@
#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_88
#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_88__PHY_SW_WDQLVL_DVW_MIN_EN_0
-#define LPDDR4__DENALI_PHY_89_READ_MASK 0x1F1F0F3FU
-#define LPDDR4__DENALI_PHY_89_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_89_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_89_WRITE_MASK 0x1F1F0F3FU
#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH 6U
#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_89
#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_89__PHY_WDQLVL_PER_START_OFFSET_0
-#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0_WIDTH 4U
#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_89
#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_89__PHY_FAST_LVL_EN_0
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0_WIDTH 5U
#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_89
#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_TX_DCD_0
#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_89
#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_89__PHY_PAD_RX_DCD_0_0
-#define LPDDR4__DENALI_PHY_90_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_90_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_90_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_90_WRITE_MASK 0x1F1F1F1FU
#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_90
#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_1_0
#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_90
#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_2_0
#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_90
#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_3_0
#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_90
#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_RX_DCD_4_0
-#define LPDDR4__DENALI_PHY_91_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_91_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_91_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_91_WRITE_MASK 0x1F1F1F1FU
#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_91
#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_5_0
#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_91
#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_6_0
#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_91
#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_RX_DCD_7_0
#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0_WIDTH 5U
#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_91
#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_91__PHY_PAD_DM_RX_DCD_0
-#define LPDDR4__DENALI_PHY_92_READ_MASK 0x003F1F1FU
-#define LPDDR4__DENALI_PHY_92_WRITE_MASK 0x003F1F1FU
+#define LPDDR4__DENALI_PHY_92_READ_MASK 0x003F1F1FU
+#define LPDDR4__DENALI_PHY_92_WRITE_MASK 0x003F1F1FU
#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0_WIDTH 5U
#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_92
#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DQS_RX_DCD_0
#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0_WIDTH 5U
#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_92
#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_FDBK_RX_DCD_0
#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0_WIDTH 6U
#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_92
#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_92__PHY_PAD_DSLICE_IO_CFG_0
-#define LPDDR4__DENALI_PHY_93_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_93_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_93_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_93_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_93
#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ0_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_93
#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDQ1_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_94_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_94_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_94_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_94_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_94
#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ2_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_94
#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_94__PHY_RDDQ3_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_95_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_95_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_95_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_95_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_95
#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ4_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_95
#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_95__PHY_RDDQ5_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_96_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_96_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_96_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_96_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_96
#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ6_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_96
#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_96__PHY_RDDQ7_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_97_READ_MASK 0x000703FFU
-#define LPDDR4__DENALI_PHY_97_WRITE_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_97_READ_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_97_WRITE_MASK 0x000703FFU
#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0_WIDTH 10U
#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_97
#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_97__PHY_RDDM_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_MASK 0x00070000U
#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0_WIDTH 3U
#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__REG DENALI_PHY_97
#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_97__PHY_DATA_DC_CAL_CLK_SEL_0
-#define LPDDR4__DENALI_PHY_98_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_98_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_98_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_98_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0_WIDTH 8U
#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_98
#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_OE_TIMING_0
#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0_WIDTH 8U
#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_98
#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_RD_TIMING_0
#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0_WIDTH 8U
#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_98
#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQ_TSEL_WR_TIMING_0
#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0_WIDTH 8U
#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_98
#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_98__PHY_DQS_OE_TIMING_0
-#define LPDDR4__DENALI_PHY_99_READ_MASK 0xFFFFFF0FU
-#define LPDDR4__DENALI_PHY_99_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_99_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_99_WRITE_MASK 0xFFFFFF0FU
#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0_WIDTH 4U
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_99
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_IO_PAD_DELAY_TIMING_0
#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0_WIDTH 8U
#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_99
#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_RD_TIMING_0
#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0_WIDTH 8U
#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_99
#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_OE_RD_TIMING_0
#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0_WIDTH 8U
#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_99
#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_99__PHY_DQS_TSEL_WR_TIMING_0
-#define LPDDR4__DENALI_PHY_100_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_100_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_100_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_100_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_WIDTH 16U
+#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0_WIDTH 16U
#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_100
#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_100__PHY_VREF_SETTING_TIME_0
#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_WIDTH 12U
+#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0_WIDTH 12U
#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_100
#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_100__PHY_PAD_VREF_CTRL_DQ_0
-#define LPDDR4__DENALI_PHY_101_READ_MASK 0x03FFFF01U
-#define LPDDR4__DENALI_PHY_101_WRITE_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_101_READ_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_101_WRITE_MASK 0x03FFFF01U
#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0_WOSET 0U
#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__REG DENALI_PHY_101
#define LPDDR4__PHY_PER_CS_TRAINING_EN_0__FLD LPDDR4__DENALI_PHY_101__PHY_PER_CS_TRAINING_EN_0
#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0_WIDTH 8U
#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_101
#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQ_IE_TIMING_0
#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0_WIDTH 8U
#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_101
#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_DQS_IE_TIMING_0
#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_MASK 0x03000000U
-#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0_WIDTH 2U
#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_101
#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_101__PHY_RDDATA_EN_IE_DLY_0
-#define LPDDR4__DENALI_PHY_102_READ_MASK 0x1F1F0103U
-#define LPDDR4__DENALI_PHY_102_WRITE_MASK 0x1F1F0103U
-#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_102_READ_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_102_WRITE_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0_WIDTH 2U
#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_102
#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_IE_MODE_0
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0_WOSET 0U
#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_102
#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_102__PHY_DBI_MODE_0
#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_102
#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_TSEL_DLY_0
#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_102
#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_OE_DLY_0
-#define LPDDR4__DENALI_PHY_103_READ_MASK 0x3F07FF0FU
-#define LPDDR4__DENALI_PHY_103_WRITE_MASK 0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_103_READ_MASK 0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_103_WRITE_MASK 0x3F07FF0FU
#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0_WIDTH 4U
#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_103
#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_103__PHY_SW_MASTER_MODE_0
#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_MASK 0x0007FF00U
-#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_SHIFT 8U
#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0_WIDTH 11U
#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_103
#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_START_0
#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_WIDTH 6U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0_WIDTH 6U
#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_103
#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_103__PHY_MASTER_DELAY_STEP_0
-#define LPDDR4__DENALI_PHY_104_READ_MASK 0xFF0FFFFFU
-#define LPDDR4__DENALI_PHY_104_WRITE_MASK 0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_104_READ_MASK 0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_104_WRITE_MASK 0xFF0FFFFFU
#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0_WIDTH 8U
#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_104
#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_WAIT_0
@@ -1779,19 +1778,19 @@
#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_104__PHY_MASTER_DELAY_HALF_MEASURE_0
#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0_WIDTH 4U
#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_104
#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_104__PHY_RPTR_UPDATE_0
#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0_WIDTH 8U
#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_104
#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_104__PHY_WRLVL_DLY_STEP_0
-#define LPDDR4__DENALI_PHY_105_READ_MASK 0x1F0F3F0FU
-#define LPDDR4__DENALI_PHY_105_WRITE_MASK 0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_105_READ_MASK 0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_105_WRITE_MASK 0x1F0F3F0FU
#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_105__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH 4U
@@ -1805,8 +1804,8 @@
#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_WRLVL_RESP_WAIT_CNT_0
#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0_WIDTH 4U
#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_105
#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_DLY_STEP_0
@@ -1816,25 +1815,25 @@
#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_105
#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_105__PHY_GTLVL_RESP_WAIT_CNT_0
-#define LPDDR4__DENALI_PHY_106_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_106_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_106_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_106_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0_WIDTH 10U
#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_106
#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_BACK_STEP_0
#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0_WIDTH 10U
#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_106
#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_106__PHY_GTLVL_FINAL_STEP_0
-#define LPDDR4__DENALI_PHY_107_READ_MASK 0x0F010FFFU
-#define LPDDR4__DENALI_PHY_107_WRITE_MASK 0x0F010FFFU
+#define LPDDR4__DENALI_PHY_107_READ_MASK 0x0F010FFFU
+#define LPDDR4__DENALI_PHY_107_WRITE_MASK 0x0F010FFFU
#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0_WIDTH 8U
#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_107
#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_WDQLVL_DLY_STEP_0
@@ -1846,31 +1845,31 @@
#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0_WOSET 0U
#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_107
#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_107__PHY_TOGGLE_PRE_SUPPORT_0
#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_MASK 0x0F000000U
-#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0_WIDTH 4U
#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_107
#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_107__PHY_RDLVL_DLY_STEP_0
-#define LPDDR4__DENALI_PHY_108_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_108_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_108_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_108_WRITE_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0_WIDTH 10U
#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_108
#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_108__PHY_RDLVL_MAX_EDGE_0
-#define LPDDR4__DENALI_PHY_109_READ_MASK 0x3F0103FFU
-#define LPDDR4__DENALI_PHY_109_WRITE_MASK 0x3F0103FFU
+#define LPDDR4__DENALI_PHY_109_READ_MASK 0x3F0103FFU
+#define LPDDR4__DENALI_PHY_109_WRITE_MASK 0x3F0103FFU
#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_WIDTH 10U
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0_WIDTH 10U
#define LPDDR4__PHY_RDLVL_DVW_MIN_0__REG DENALI_PHY_109
#define LPDDR4__PHY_RDLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_DVW_MIN_0
@@ -1888,8 +1887,8 @@
#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__REG DENALI_PHY_109
#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_109__PHY_RDLVL_PER_START_OFFSET_0
-#define LPDDR4__DENALI_PHY_110_READ_MASK 0x00030703U
-#define LPDDR4__DENALI_PHY_110_WRITE_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_110_READ_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_110_WRITE_MASK 0x00030703U
#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0_WIDTH 2U
@@ -1897,8 +1896,8 @@
#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_DISABLE_0
#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_MASK 0x00000700U
-#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0_WIDTH 3U
#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_110
#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRPATH_GATE_TIMING_0
@@ -1908,8 +1907,8 @@
#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__REG DENALI_PHY_110
#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_0__FLD LPDDR4__DENALI_PHY_110__PHY_DATA_DC_INIT_DISABLE_0
-#define LPDDR4__DENALI_PHY_111_READ_MASK 0x07FF03FFU
-#define LPDDR4__DENALI_PHY_111_WRITE_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_111_READ_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_111_WRITE_MASK 0x07FF03FFU
#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQS_INIT_SLV_DELAY_0_WIDTH 10U
@@ -1922,8 +1921,8 @@
#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__REG DENALI_PHY_111
#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_DATA_DC_DQ_INIT_SLV_DELAY_0
-#define LPDDR4__DENALI_PHY_112_READ_MASK 0xFFFF0101U
-#define LPDDR4__DENALI_PHY_112_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_112_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_112_WRITE_MASK 0xFFFF0101U
#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_112__PHY_DATA_DC_WRLVL_ENABLE_0_WIDTH 1U
@@ -1952,11 +1951,11 @@
#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__REG DENALI_PHY_112
#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0__FLD LPDDR4__DENALI_PHY_112__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0
-#define LPDDR4__DENALI_PHY_113_READ_MASK 0x001F3F7FU
-#define LPDDR4__DENALI_PHY_113_WRITE_MASK 0x001F3F7FU
+#define LPDDR4__DENALI_PHY_113_READ_MASK 0x001F3F7FU
+#define LPDDR4__DENALI_PHY_113_WRITE_MASK 0x001F3F7FU
#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_WIDTH 7U
+#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0_WIDTH 7U
#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_113
#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_113__PHY_WDQ_OSC_DELTA_0
@@ -1967,29 +1966,29 @@
#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_113__PHY_MEAS_DLY_STEP_ENABLE_0
#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_113
#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDATA_EN_DLY_0
-#define LPDDR4__DENALI_PHY_114_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_114_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_114_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_114_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0_WIDTH 32U
#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_114
#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_114__PHY_DQ_DM_SWIZZLE0_0
-#define LPDDR4__DENALI_PHY_115_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_115_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_115_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_115_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0_WIDTH 4U
#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_115
#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_115__PHY_DQ_DM_SWIZZLE1_0
-#define LPDDR4__DENALI_PHY_116_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_116_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_116_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH 11U
@@ -2002,8 +2001,8 @@
#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_116
#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_CLK_WRDQ1_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_117_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_117_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_117_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_117_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH 11U
@@ -2016,8 +2015,8 @@
#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_117
#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_CLK_WRDQ3_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_118_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_118_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_118_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_118_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH 11U
@@ -2030,8 +2029,8 @@
#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_118
#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_CLK_WRDQ5_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_119_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_119_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_119_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_119_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH 11U
@@ -2044,8 +2043,8 @@
#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_119
#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_CLK_WRDQ7_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_120_READ_MASK 0x03FF07FFU
-#define LPDDR4__DENALI_PHY_120_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_120_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_120_WRITE_MASK 0x03FF07FFU
#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_120__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH 11U
@@ -2058,8 +2057,8 @@
#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_120
#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_120__PHY_CLK_WRDQS_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_121_READ_MASK 0x0003FF03U
-#define LPDDR4__DENALI_PHY_121_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_121_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_121_WRITE_MASK 0x0003FF03U
#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH 2U
@@ -2072,8 +2071,8 @@
#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_121
#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_121__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_122_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_122_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_122_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH 10U
@@ -2086,8 +2085,8 @@
#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_122
#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_122__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_123_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_123_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_123_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH 10U
@@ -2100,8 +2099,8 @@
#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_123
#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_123__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_124_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_124_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_124_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH 10U
@@ -2114,8 +2113,8 @@
#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_124
#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_125_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_125_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_125_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH 10U
@@ -2128,8 +2127,8 @@
#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_125
#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_125__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_126_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_126_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_126_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH 10U
@@ -2142,8 +2141,8 @@
#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_126
#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_126__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_127_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_127_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_127_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH 10U
@@ -2156,8 +2155,8 @@
#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_127
#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_127__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_128_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_128_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_128_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_128_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH 10U
@@ -2170,8 +2169,8 @@
#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_128
#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_128__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_129_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_129_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_129_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_129_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_129__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH 10U
@@ -2184,8 +2183,8 @@
#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_129
#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_129__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_130_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_130_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_130_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_130_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_130__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH 10U
@@ -2198,8 +2197,8 @@
#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_130
#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_130__PHY_RDDQS_GATE_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_131_READ_MASK 0x03FF070FU
-#define LPDDR4__DENALI_PHY_131_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_131_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_131_WRITE_MASK 0x03FF070FU
#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH 4U
@@ -2207,8 +2206,8 @@
#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_131__PHY_RDDQS_LATENCY_ADJUST_0
#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_MASK 0x00000700U
-#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0_WIDTH 3U
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_131
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRITE_PATH_LAT_ADD_0
@@ -2218,8 +2217,8 @@
#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_131
#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_131__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0
-#define LPDDR4__DENALI_PHY_132_READ_MASK 0x000103FFU
-#define LPDDR4__DENALI_PHY_132_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_132_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_132_WRITE_MASK 0x000103FFU
#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_132__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH 10U
@@ -2234,8 +2233,8 @@
#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_132
#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_132__PHY_WRLVL_EARLY_FORCE_ZERO_0
-#define LPDDR4__DENALI_PHY_133_READ_MASK 0x000F03FFU
-#define LPDDR4__DENALI_PHY_133_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_133_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_133_WRITE_MASK 0x000F03FFU
#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_133__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH 10U
@@ -2248,8 +2247,8 @@
#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_133
#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_133__PHY_GTLVL_LAT_ADJ_START_0
-#define LPDDR4__DENALI_PHY_134_READ_MASK 0x010F07FFU
-#define LPDDR4__DENALI_PHY_134_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_134_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_134_WRITE_MASK 0x010F07FFU
#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH 11U
@@ -2257,29 +2256,29 @@
#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_WDQLVL_DQDM_SLV_DLY_START_0
#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0_WIDTH 4U
#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_134
#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_WRLAT_START_0
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0_WOSET 0U
#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_134
#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_134__PHY_NTP_PASS_0
-#define LPDDR4__DENALI_PHY_135_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_135_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_135_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_135_WRITE_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH 10U
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_135
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_135__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0
-#define LPDDR4__DENALI_PHY_136_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_136_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_136_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_136_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQS_CLK_ADJUST_0_WIDTH 8U
@@ -2304,8 +2303,8 @@
#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__REG DENALI_PHY_136
#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_136__PHY_DATA_DC_DQ2_CLK_ADJUST_0
-#define LPDDR4__DENALI_PHY_137_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_137_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_137_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_137_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ3_CLK_ADJUST_0_WIDTH 8U
@@ -2330,8 +2329,8 @@
#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__REG DENALI_PHY_137
#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_0__FLD LPDDR4__DENALI_PHY_137__PHY_DATA_DC_DQ6_CLK_ADJUST_0
-#define LPDDR4__DENALI_PHY_138_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_138_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_138_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_138_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_138__PHY_DATA_DC_DQ7_CLK_ADJUST_0_WIDTH 8U
@@ -2350,23 +2349,23 @@
#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_138
#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_138__PHY_DSLICE_PAD_BOOSTPN_SETTING_0
-#define LPDDR4__DENALI_PHY_139_READ_MASK 0x0003033FU
-#define LPDDR4__DENALI_PHY_139_WRITE_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_139_READ_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_139_WRITE_MASK 0x0003033FU
#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH 6U
#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_139
#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_139__PHY_DSLICE_PAD_RX_CTLE_SETTING_0
-#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0_WIDTH 2U
#define LPDDR4__PHY_DQ_FFE_0__REG DENALI_PHY_139
#define LPDDR4__PHY_DQ_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQ_FFE_0
-#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_WIDTH 2U
+#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0_WIDTH 2U
#define LPDDR4__PHY_DQS_FFE_0__REG DENALI_PHY_139
#define LPDDR4__PHY_DQS_FFE_0__FLD LPDDR4__DENALI_PHY_139__PHY_DQS_FFE_0
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
similarity index 66%
rename from drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h
rename to drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
index 124f58f..5385e1e 100644
--- a/drivers/ram/k3-j721e/lpddr4_data_slice_1_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
@@ -1,17 +1,16 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
*
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_
-#define LPDDR4__DENALI_PHY_256_READ_MASK 0x000F07FFU
-#define LPDDR4__DENALI_PHY_256_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_256_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_256_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH 11U
@@ -24,8 +23,8 @@
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_256
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_256__PHY_IO_PAD_DELAY_TIMING_BYPASS_1
-#define LPDDR4__DENALI_PHY_257_READ_MASK 0x000703FFU
-#define LPDDR4__DENALI_PHY_257_WRITE_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_257_READ_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_257_WRITE_MASK 0x000703FFU
#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH 10U
@@ -38,8 +37,8 @@
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1
-#define LPDDR4__DENALI_PHY_258_READ_MASK 0x010303FFU
-#define LPDDR4__DENALI_PHY_258_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_258_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_258_WRITE_MASK 0x010303FFU
#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH 10U
@@ -60,75 +59,75 @@
#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258
#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1
-#define LPDDR4__DENALI_PHY_259_READ_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_259_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_WRITE_MASK 0x3F3F3F3FU
#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259
#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1
#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259
#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1
#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259
#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1
#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259
#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1
-#define LPDDR4__DENALI_PHY_260_READ_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_260_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_WRITE_MASK 0x3F3F3F3FU
#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260
#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1
#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260
#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1
#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260
#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1
#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260
#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1
-#define LPDDR4__DENALI_PHY_261_READ_MASK 0x01030F3FU
-#define LPDDR4__DENALI_PHY_261_WRITE_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_261_READ_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_261_WRITE_MASK 0x01030F3FU
#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH 6U
#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261
#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1
#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH 4U
#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261
#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1
#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1_WIDTH 2U
#define LPDDR4__PHY_PER_RANK_CS_MAP_1__REG DENALI_PHY_261
#define LPDDR4__PHY_PER_RANK_CS_MAP_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_RANK_CS_MAP_1
@@ -140,8 +139,8 @@
#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__REG DENALI_PHY_261
#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_1__FLD LPDDR4__DENALI_PHY_261__PHY_PER_CS_TRAINING_MULTICAST_EN_1
-#define LPDDR4__DENALI_PHY_262_READ_MASK 0x1F1F0301U
-#define LPDDR4__DENALI_PHY_262_WRITE_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262_READ_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_262_WRITE_MASK 0x1F1F0301U
#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_262__PHY_PER_CS_TRAINING_INDEX_1_WIDTH 1U
@@ -168,8 +167,8 @@
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1
-#define LPDDR4__DENALI_PHY_263_READ_MASK 0x1F030F0FU
-#define LPDDR4__DENALI_PHY_263_WRITE_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263_READ_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_263_WRITE_MASK 0x1F030F0FU
#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH 4U
@@ -194,17 +193,17 @@
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1
-#define LPDDR4__DENALI_PHY_264_READ_MASK 0x0101FF03U
-#define LPDDR4__DENALI_PHY_264_WRITE_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_264_READ_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_264_WRITE_MASK 0x0101FF03U
#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1_WIDTH 2U
#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_264
#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_CTRL_LPBK_EN_1
#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1_WIDTH 9U
#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_264
#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_CONTROL_1
@@ -216,33 +215,33 @@
#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264
#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1
-#define LPDDR4__DENALI_PHY_265_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_265_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH 32U
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1
-#define LPDDR4__DENALI_PHY_266_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_266_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH 28U
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1
-#define LPDDR4__DENALI_PHY_267_READ_MASK 0x0101FF7FU
-#define LPDDR4__DENALI_PHY_267_WRITE_MASK 0x0101FF7FU
+#define LPDDR4__DENALI_PHY_267_READ_MASK 0x0101FF7FU
+#define LPDDR4__DENALI_PHY_267_WRITE_MASK 0x0101FF7FU
#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH 7U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH 7U
#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267
#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1
#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1_WIDTH 9U
#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_267
#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_MASK_1
@@ -254,8 +253,8 @@
#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_267
#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_RDLVL_MULTI_PATT_ENABLE_1
-#define LPDDR4__DENALI_PHY_268_READ_MASK 0x007F3F01U
-#define LPDDR4__DENALI_PHY_268_WRITE_MASK 0x007F3F01U
+#define LPDDR4__DENALI_PHY_268_READ_MASK 0x007F3F01U
+#define LPDDR4__DENALI_PHY_268_WRITE_MASK 0x007F3F01U
#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH 1U
@@ -271,13 +270,13 @@
#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_INITIAL_STEPSIZE_1
#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_MASK 0x007F0000U
-#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_WIDTH 7U
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1_WIDTH 7U
#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_268
#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_268__PHY_VREF_TRAIN_OBS_1
-#define LPDDR4__DENALI_PHY_269_READ_MASK 0x000F03FFU
-#define LPDDR4__DENALI_PHY_269_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_269_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_269_WRITE_MASK 0x000F03FFU
#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH 10U
@@ -291,37 +290,37 @@
#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_269__PHY_GATE_ERROR_DELAY_SELECT_1
#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1_WOSET 0U
#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_269
#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_269__SC_PHY_SNAP_OBS_REGS_1
-#define LPDDR4__DENALI_PHY_270_READ_MASK 0x070101FFU
-#define LPDDR4__DENALI_PHY_270_WRITE_MASK 0x070101FFU
+#define LPDDR4__DENALI_PHY_270_READ_MASK 0x070101FFU
+#define LPDDR4__DENALI_PHY_270_WRITE_MASK 0x070101FFU
#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH 9U
#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270
#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_270__PHY_LPDDR_1_WOSET 0U
#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_270
#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_270__PHY_LPDDR_1
-#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_WIDTH 3U
+#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1_WIDTH 3U
#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_270
#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_270__PHY_MEM_CLASS_1
-#define LPDDR4__DENALI_PHY_271_READ_MASK 0x000301FFU
-#define LPDDR4__DENALI_PHY_271_WRITE_MASK 0x000301FFU
+#define LPDDR4__DENALI_PHY_271_READ_MASK 0x000301FFU
+#define LPDDR4__DENALI_PHY_271_WRITE_MASK 0x000301FFU
#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH 9U
@@ -329,101 +328,101 @@
#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1_WIDTH 2U
#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_271
#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_271__ON_FLY_GATE_ADJUST_EN_1
-#define LPDDR4__DENALI_PHY_272_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_272_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_272_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_272_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1_WIDTH 32U
#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_272
#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_272__PHY_GATE_TRACKING_OBS_1
-#define LPDDR4__DENALI_PHY_273_READ_MASK 0x00000301U
-#define LPDDR4__DENALI_PHY_273_WRITE_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_273_READ_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_273_WRITE_MASK 0x00000301U
#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1_WOSET 0U
#define LPDDR4__PHY_DFI40_POLARITY_1__REG DENALI_PHY_273
#define LPDDR4__PHY_DFI40_POLARITY_1__FLD LPDDR4__DENALI_PHY_273__PHY_DFI40_POLARITY_1
#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1_WIDTH 2U
#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_273
#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_273__PHY_LP4_PST_AMBLE_1
-#define LPDDR4__DENALI_PHY_274_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_274_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_274_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_274
#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_274__PHY_RDLVL_PATT8_1
-#define LPDDR4__DENALI_PHY_275_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_275_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_275
#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT9_1
-#define LPDDR4__DENALI_PHY_276_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_276_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_276
#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT10_1
-#define LPDDR4__DENALI_PHY_277_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_277_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_277
#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT11_1
-#define LPDDR4__DENALI_PHY_278_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_278_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_278
#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT12_1
-#define LPDDR4__DENALI_PHY_279_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_279_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_279
#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT13_1
-#define LPDDR4__DENALI_PHY_280_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_280_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_280
#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT14_1
-#define LPDDR4__DENALI_PHY_281_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_281_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_281
#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT15_1
-#define LPDDR4__DENALI_PHY_282_READ_MASK 0x070F0107U
-#define LPDDR4__DENALI_PHY_282_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_282_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_282_WRITE_MASK 0x070F0107U
#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_282__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH 3U
@@ -450,8 +449,8 @@
#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_282
#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDDQ_ENC_OBS_SELECT_1
-#define LPDDR4__DENALI_PHY_283_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_283_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_283_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_283_WRITE_MASK 0x0F0F0F0FU
#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH 4U
@@ -459,8 +458,8 @@
#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQS_DQ_ENC_OBS_SELECT_1
#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1_WIDTH 4U
#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_283
#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_WR_ENC_OBS_SELECT_1
@@ -476,41 +475,41 @@
#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_283
#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_FIFO_PTR_OBS_SELECT_1
-#define LPDDR4__DENALI_PHY_284_READ_MASK 0xFF030001U
-#define LPDDR4__DENALI_PHY_284_WRITE_MASK 0xFF030001U
+#define LPDDR4__DENALI_PHY_284_READ_MASK 0xFF030001U
+#define LPDDR4__DENALI_PHY_284_WRITE_MASK 0xFF030001U
#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1_WOSET 0U
#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_284
#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_284__PHY_LVL_DEBUG_MODE_1
#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1_WOSET 0U
#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_284
#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_284__SC_PHY_LVL_DEBUG_CONT_1
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1_WIDTH 2U
#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_284
#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_ALGO_1
#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1_WIDTH 8U
#define LPDDR4__PHY_WRLVL_PER_START_1__REG DENALI_PHY_284
#define LPDDR4__PHY_WRLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_284__PHY_WRLVL_PER_START_1
-#define LPDDR4__DENALI_PHY_285_READ_MASK 0x00FF0F3FU
-#define LPDDR4__DENALI_PHY_285_WRITE_MASK 0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_285_READ_MASK 0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_285_WRITE_MASK 0x00FF0F3FU
#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH 6U
#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285
#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1
@@ -520,23 +519,23 @@
#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_285
#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_UPDT_WAIT_CNT_1
-#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1_WIDTH 8U
#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_285
#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_285__PHY_DQ_MASK_1
-#define LPDDR4__DENALI_PHY_286_READ_MASK 0x0F3F03FFU
-#define LPDDR4__DENALI_PHY_286_WRITE_MASK 0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_286_READ_MASK 0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_286_WRITE_MASK 0x0F3F03FFU
#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1_WIDTH 10U
#define LPDDR4__PHY_GTLVL_PER_START_1__REG DENALI_PHY_286
#define LPDDR4__PHY_GTLVL_PER_START_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_PER_START_1
#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH 6U
#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286
#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1
@@ -546,11 +545,11 @@
#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1
-#define LPDDR4__DENALI_PHY_287_READ_MASK 0x1F030F3FU
-#define LPDDR4__DENALI_PHY_287_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287_WRITE_MASK 0x1F030F3FU
#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH 6U
#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287
#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1
@@ -561,8 +560,8 @@
#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1
#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH 2U
#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287
#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1
@@ -572,8 +571,8 @@
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1
-#define LPDDR4__DENALI_PHY_288_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_288_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_288_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_288_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1_WIDTH 8U
@@ -581,8 +580,8 @@
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_PERIODIC_OBS_SELECT_1
#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH 8U
#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288
#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1
@@ -593,16 +592,16 @@
#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1_WIDTH 6U
#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_288
#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_288__PHY_WDQLVL_BURST_CNT_1
-#define LPDDR4__DENALI_PHY_289_READ_MASK 0x0F07FF07U
-#define LPDDR4__DENALI_PHY_289_WRITE_MASK 0x0F07FF07U
+#define LPDDR4__DENALI_PHY_289_READ_MASK 0x0F07FF07U
+#define LPDDR4__DENALI_PHY_289_WRITE_MASK 0x0F07FF07U
#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH 3U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH 3U
#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289
#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1
@@ -618,8 +617,8 @@
#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_289
#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_UPDT_WAIT_CNT_1
-#define LPDDR4__DENALI_PHY_290_READ_MASK 0x0000FF0FU
-#define LPDDR4__DENALI_PHY_290_WRITE_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PHY_290_READ_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PHY_290_WRITE_MASK 0x0000FF0FU
#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH 4U
@@ -640,64 +639,64 @@
#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_290
#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_290__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1
-#define LPDDR4__DENALI_PHY_291_READ_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_291_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_291_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_291_WRITE_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1_WIDTH 9U
#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_291
#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DATADM_MASK_1
-#define LPDDR4__DENALI_PHY_292_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_292_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_292_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_292_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1_WIDTH 32U
#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_292
#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_292__PHY_USER_PATT0_1
-#define LPDDR4__DENALI_PHY_293_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_293_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_293_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1_WIDTH 32U
#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_293
#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT1_1
-#define LPDDR4__DENALI_PHY_294_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_294_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_294_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1_WIDTH 32U
#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_294
#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT2_1
-#define LPDDR4__DENALI_PHY_295_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_295_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_295_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1_WIDTH 32U
#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_295
#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT3_1
-#define LPDDR4__DENALI_PHY_296_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_296_WRITE_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_WIDTH 16U
+#define LPDDR4__DENALI_PHY_296_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_296_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1_WIDTH 16U
#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_296
#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT4_1
#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1_WOSET 0U
#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_296
#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_296__PHY_NTP_MULT_TRAIN_1
-#define LPDDR4__DENALI_PHY_297_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_297_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_297_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_297_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_297__PHY_NTP_EARLY_THRESHOLD_1_WIDTH 10U
@@ -710,8 +709,8 @@
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_297
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_PERIOD_THRESHOLD_1
-#define LPDDR4__DENALI_PHY_298_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_298_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH 10U
@@ -724,8 +723,8 @@
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_298
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_MAX_1
-#define LPDDR4__DENALI_PHY_299_READ_MASK 0x00FF0001U
-#define LPDDR4__DENALI_PHY_299_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_299_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_299_WRITE_MASK 0x00FF0001U
#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH 1U
@@ -735,27 +734,27 @@
#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_299__PHY_CALVL_VREF_DRIVING_SLICE_1
#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1_WIDTH 6U
#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_299
#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_299__SC_PHY_MANUAL_CLEAR_1
#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1_WIDTH 8U
#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_299
#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_299__PHY_FIFO_PTR_OBS_1
-#define LPDDR4__DENALI_PHY_300_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_300_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_300_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_300_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1_WIDTH 32U
#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_300
#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_LPBK_RESULT_OBS_1
-#define LPDDR4__DENALI_PHY_301_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_301_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_301_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_301_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_301__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH 16U
@@ -768,8 +767,8 @@
#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_301
#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_MASTER_DLY_LOCK_OBS_1
-#define LPDDR4__DENALI_PHY_302_READ_MASK 0xFFFF7F7FU
-#define LPDDR4__DENALI_PHY_302_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_302_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_302_WRITE_MASK 0xFFFF7F7FU
#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_302__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH 7U
@@ -794,8 +793,8 @@
#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_302
#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1
-#define LPDDR4__DENALI_PHY_303_READ_MASK 0x7F07FFFFU
-#define LPDDR4__DENALI_PHY_303_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_303_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_303_WRITE_MASK 0x7F07FFFFU
#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
@@ -814,8 +813,8 @@
#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1
-#define LPDDR4__DENALI_PHY_304_READ_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_PHY_304_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_304_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_304_WRITE_MASK 0x0007FFFFU
#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_304__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH 8U
@@ -829,13 +828,13 @@
#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1
#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_MASK 0x00070000U
-#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_WIDTH 3U
+#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1_WIDTH 3U
#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_304
#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WR_SHIFT_OBS_1
-#define LPDDR4__DENALI_PHY_305_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_305_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_305_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_305_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH 10U
@@ -848,16 +847,16 @@
#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_305
#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRLVL_HARD1_DELAY_OBS_1
-#define LPDDR4__DENALI_PHY_306_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_306_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_306_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_306_WRITE_MASK 0x0001FFFFU
#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_WIDTH 17U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1_WIDTH 17U
#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_306
#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_STATUS_OBS_1
-#define LPDDR4__DENALI_PHY_307_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_307_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_307_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH 10U
@@ -870,11 +869,11 @@
#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_307
#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1
-#define LPDDR4__DENALI_PHY_308_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_308_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_308_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_308_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_WIDTH 16U
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1_WIDTH 16U
#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__REG DENALI_PHY_308
#define LPDDR4__PHY_WRLVL_ERROR_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_WRLVL_ERROR_OBS_1
@@ -884,24 +883,24 @@
#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_308
#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GTLVL_HARD0_DELAY_OBS_1
-#define LPDDR4__DENALI_PHY_309_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_309_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_309_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_309_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH 14U
#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309
#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1
-#define LPDDR4__DENALI_PHY_310_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_310_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH 18U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH 18U
#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310
#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1
-#define LPDDR4__DENALI_PHY_311_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_311_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH 10U
@@ -914,32 +913,32 @@
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1
-#define LPDDR4__DENALI_PHY_312_READ_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_312_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_312_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_312_WRITE_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH 2U
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1
-#define LPDDR4__DENALI_PHY_313_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_313_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313
#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1
-#define LPDDR4__DENALI_PHY_314_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_314_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_314_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_314_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__REG DENALI_PHY_314
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_RDLVL_PERIODIC_OBS_1
-#define LPDDR4__DENALI_PHY_315_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_315_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_315_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_315_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH 11U
@@ -952,56 +951,56 @@
#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_315
#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_DQDM_TE_DLY_OBS_1
-#define LPDDR4__DENALI_PHY_316_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_316_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1_WIDTH 32U
#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_316
#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_STATUS_OBS_1
-#define LPDDR4__DENALI_PHY_317_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_317_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_317_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH 32U
#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_317
#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_317__PHY_WDQLVL_PERIODIC_OBS_1
-#define LPDDR4__DENALI_PHY_318_READ_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_318_WRITE_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_WIDTH 31U
+#define LPDDR4__DENALI_PHY_318_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_318_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1_WIDTH 31U
#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_318
#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MODE_1
-#define LPDDR4__DENALI_PHY_319_READ_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_319_WRITE_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_319_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_319_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1_WIDTH 6U
#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_319
#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_MASK_1
-#define LPDDR4__DENALI_PHY_320_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_320_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1_WIDTH 32U
#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_320
#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_OBS_1
-#define LPDDR4__DENALI_PHY_321_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_321_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_321_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH 32U
#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_321
#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TEST_MSTR_DLY_OBS_1
-#define LPDDR4__DENALI_PHY_322_READ_MASK 0x010001FFU
-#define LPDDR4__DENALI_PHY_322_WRITE_MASK 0x010001FFU
+#define LPDDR4__DENALI_PHY_322_READ_MASK 0x010001FFU
+#define LPDDR4__DENALI_PHY_322_WRITE_MASK 0x010001FFU
#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH 8U
@@ -1009,34 +1008,34 @@
#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_322__PHY_DDL_TRACK_UPD_THRESHOLD_1
#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1_WOSET 0U
#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_322
#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_322__PHY_LP4_WDQS_OE_EXTEND_1
#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1_WOSET 0U
#define LPDDR4__SC_PHY_RX_CAL_START_1__REG DENALI_PHY_322
#define LPDDR4__SC_PHY_RX_CAL_START_1__FLD LPDDR4__DENALI_PHY_322__SC_PHY_RX_CAL_START_1
#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1_WOSET 0U
#define LPDDR4__PHY_RX_CAL_OVERRIDE_1__REG DENALI_PHY_322
#define LPDDR4__PHY_RX_CAL_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_OVERRIDE_1
-#define LPDDR4__DENALI_PHY_323_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_323_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_WRITE_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1_WIDTH 8U
#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__REG DENALI_PHY_323
#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_SAMPLE_WAIT_1
@@ -1048,147 +1047,147 @@
#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__REG DENALI_PHY_323
#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1__FLD LPDDR4__DENALI_PHY_323__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_1
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_323
#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ0_1
-#define LPDDR4__DENALI_PHY_324_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_324_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_324_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_324
#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ1_1
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_324
#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ2_1
-#define LPDDR4__DENALI_PHY_325_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_325_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_325_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_325
#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ3_1
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_325
#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ4_1
-#define LPDDR4__DENALI_PHY_326_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_326_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_326_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_326
#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ5_1
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_326
#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DQ6_1
-#define LPDDR4__DENALI_PHY_327_READ_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_327_WRITE_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_327_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_327_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_327
#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQ7_1
-#define LPDDR4__DENALI_PHY_328_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_328_WRITE_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH 18U
+#define LPDDR4__DENALI_PHY_328_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1_WIDTH 18U
#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_328
#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_328__PHY_RX_CAL_DM_1
-#define LPDDR4__DENALI_PHY_329_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_329_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_329_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_329
#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_DQS_1
#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_329
#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_329__PHY_RX_CAL_FDBK_1
-#define LPDDR4__DENALI_PHY_330_READ_MASK 0x01FF07FFU
-#define LPDDR4__DENALI_PHY_330_WRITE_MASK 0x01FF07FFU
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_WIDTH 11U
+#define LPDDR4__DENALI_PHY_330_READ_MASK 0x01FF07FFU
+#define LPDDR4__DENALI_PHY_330_WRITE_MASK 0x01FF07FFU
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1_WIDTH 11U
#define LPDDR4__PHY_RX_CAL_OBS_1__REG DENALI_PHY_330
#define LPDDR4__PHY_RX_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_OBS_1
#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_WIDTH 9U
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__REG DENALI_PHY_330
#define LPDDR4__PHY_RX_CAL_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_330__PHY_RX_CAL_LOCK_OBS_1
-#define LPDDR4__DENALI_PHY_331_READ_MASK 0x017F7F01U
-#define LPDDR4__DENALI_PHY_331_WRITE_MASK 0x017F7F01U
+#define LPDDR4__DENALI_PHY_331_READ_MASK 0x017F7F01U
+#define LPDDR4__DENALI_PHY_331_WRITE_MASK 0x017F7F01U
#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1_WOSET 0U
#define LPDDR4__PHY_RX_CAL_DISABLE_1__REG DENALI_PHY_331
#define LPDDR4__PHY_RX_CAL_DISABLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DISABLE_1
#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_MASK 0x00007F00U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_WIDTH 7U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1_WIDTH 7U
#define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__REG DENALI_PHY_331
#define LPDDR4__PHY_RX_CAL_SE_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_SE_ADJUST_1
#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_MASK 0x007F0000U
#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_WIDTH 7U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1_WIDTH 7U
#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__REG DENALI_PHY_331
#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_DIFF_ADJUST_1
#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1_WOSET 0U
#define LPDDR4__PHY_RX_CAL_COMP_VAL_1__REG DENALI_PHY_331
#define LPDDR4__PHY_RX_CAL_COMP_VAL_1__FLD LPDDR4__DENALI_PHY_331__PHY_RX_CAL_COMP_VAL_1
-#define LPDDR4__DENALI_PHY_332_READ_MASK 0x07FF0FFFU
-#define LPDDR4__DENALI_PHY_332_WRITE_MASK 0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_332_READ_MASK 0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_332_WRITE_MASK 0x07FF0FFFU
#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_WIDTH 12U
+#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1_WIDTH 12U
#define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__REG DENALI_PHY_332
#define LPDDR4__PHY_RX_CAL_INDEX_MASK_1__FLD LPDDR4__DENALI_PHY_332__PHY_RX_CAL_INDEX_MASK_1
#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_WIDTH 11U
+#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1_WIDTH 11U
#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_332
#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_PAD_RX_BIAS_EN_1
-#define LPDDR4__DENALI_PHY_333_READ_MASK 0x03FFFF1FU
-#define LPDDR4__DENALI_PHY_333_WRITE_MASK 0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_333_READ_MASK 0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_333_WRITE_MASK 0x03FFFF1FU
#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1_WIDTH 5U
#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_333
#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_333__PHY_STATIC_TOG_DISABLE_1
@@ -1205,13 +1204,13 @@
#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_CAL_TIMEOUT_1
#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_MASK 0x03000000U
-#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1_WIDTH 2U
#define LPDDR4__PHY_DATA_DC_WEIGHT_1__REG DENALI_PHY_333
#define LPDDR4__PHY_DATA_DC_WEIGHT_1__FLD LPDDR4__DENALI_PHY_333__PHY_DATA_DC_WEIGHT_1
-#define LPDDR4__DENALI_PHY_334_READ_MASK 0x01FFFF3FU
-#define LPDDR4__DENALI_PHY_334_WRITE_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_334_READ_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_334_WRITE_MASK 0x01FFFF3FU
#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_START_1_WIDTH 6U
@@ -1238,8 +1237,8 @@
#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__REG DENALI_PHY_334
#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_1__FLD LPDDR4__DENALI_PHY_334__PHY_DATA_DC_ADJUST_DIRECT_1
-#define LPDDR4__DENALI_PHY_335_READ_MASK 0x07030101U
-#define LPDDR4__DENALI_PHY_335_WRITE_MASK 0x07030101U
+#define LPDDR4__DENALI_PHY_335_READ_MASK 0x07030101U
+#define LPDDR4__DENALI_PHY_335_WRITE_MASK 0x07030101U
#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1_WIDTH 1U
@@ -1249,27 +1248,27 @@
#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_POLARITY_1
#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1_WOSET 0U
#define LPDDR4__PHY_DATA_DC_CAL_START_1__REG DENALI_PHY_335
#define LPDDR4__PHY_DATA_DC_CAL_START_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_CAL_START_1
#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1_WIDTH 2U
#define LPDDR4__PHY_DATA_DC_SW_RANK_1__REG DENALI_PHY_335
#define LPDDR4__PHY_DATA_DC_SW_RANK_1__FLD LPDDR4__DENALI_PHY_335__PHY_DATA_DC_SW_RANK_1
#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_WIDTH 3U
+#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1_WIDTH 3U
#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_335
#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_335__PHY_FDBK_PWR_CTRL_1
-#define LPDDR4__DENALI_PHY_336_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PHY_336_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_336_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_336_WRITE_MASK 0x01010101U
#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_336__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH 1U
@@ -1302,22 +1301,22 @@
#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_336
#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_336__PHY_SLICE_PWR_RDC_DISABLE_1
-#define LPDDR4__DENALI_PHY_337_READ_MASK 0x3FFF07FFU
-#define LPDDR4__DENALI_PHY_337_WRITE_MASK 0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_337_READ_MASK 0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_337_WRITE_MASK 0x3FFF07FFU
#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1_WIDTH 11U
#define LPDDR4__PHY_PARITY_ERROR_REGIF_1__REG DENALI_PHY_337
#define LPDDR4__PHY_PARITY_ERROR_REGIF_1__FLD LPDDR4__DENALI_PHY_337__PHY_PARITY_ERROR_REGIF_1
#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_MASK 0x3FFF0000U
-#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_WIDTH 14U
+#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1_WIDTH 14U
#define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__REG DENALI_PHY_337
#define LPDDR4__PHY_DS_FSM_ERROR_INFO_1__FLD LPDDR4__DENALI_PHY_337__PHY_DS_FSM_ERROR_INFO_1
-#define LPDDR4__DENALI_PHY_338_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_338_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_338_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_338_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_338__PHY_DS_FSM_ERROR_INFO_MASK_1_WIDTH 14U
@@ -1330,8 +1329,8 @@
#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__REG DENALI_PHY_338
#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_338__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_1
-#define LPDDR4__DENALI_PHY_339_READ_MASK 0x00001F1FU
-#define LPDDR4__DENALI_PHY_339_WRITE_MASK 0x00001F1FU
+#define LPDDR4__DENALI_PHY_339_READ_MASK 0x00001F1FU
+#define LPDDR4__DENALI_PHY_339_WRITE_MASK 0x00001F1FU
#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_339__PHY_DS_TRAIN_CALIB_ERROR_INFO_1_WIDTH 5U
@@ -1350,37 +1349,37 @@
#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__REG DENALI_PHY_339
#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1__FLD LPDDR4__DENALI_PHY_339__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_1
-#define LPDDR4__DENALI_PHY_340_READ_MASK 0x07FFFF07U
-#define LPDDR4__DENALI_PHY_340_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_340_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_340_WRITE_MASK 0x07FFFF07U
#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_WIDTH 3U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1_WIDTH 3U
#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_340
#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_ENABLE_1
#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_WIDTH 16U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1_WIDTH 16U
#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_340
#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQ_TSEL_SELECT_1
#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_WIDTH 3U
+#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1_WIDTH 3U
#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_340
#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_340__PHY_DQS_TSEL_ENABLE_1
-#define LPDDR4__DENALI_PHY_341_READ_MASK 0x7F03FFFFU
-#define LPDDR4__DENALI_PHY_341_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_341_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_341_WRITE_MASK 0x7F03FFFFU
#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_WIDTH 16U
+#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1_WIDTH 16U
#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_341
#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_341__PHY_DQS_TSEL_SELECT_1
#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1_WIDTH 2U
#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_341
#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_341__PHY_TWO_CYC_PREAMBLE_1
@@ -1390,8 +1389,8 @@
#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_341
#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_341__PHY_VREF_INITIAL_START_POINT_1
-#define LPDDR4__DENALI_PHY_342_READ_MASK 0xFF01037FU
-#define LPDDR4__DENALI_PHY_342_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_342_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_342_WRITE_MASK 0xFF01037FU
#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH 7U
@@ -1399,50 +1398,50 @@
#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_INITIAL_STOP_POINT_1
#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1_WIDTH 2U
#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_342
#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_342__PHY_VREF_TRAINING_CTRL_1
#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1_WOSET 0U
#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_342
#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_TRAIN_EN_1
#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH 8U
#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_342
#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_342__PHY_NTP_WDQ_STEP_SIZE_1
-#define LPDDR4__DENALI_PHY_343_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_343_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_343_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_343_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_WIDTH 11U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1_WIDTH 11U
#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_343
#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_START_1
#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_WIDTH 11U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1_WIDTH 11U
#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_343
#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_343__PHY_NTP_WDQ_STOP_1
-#define LPDDR4__DENALI_PHY_344_READ_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_PHY_344_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_344_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_344_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1_WIDTH 8U
#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_344
#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_NTP_WDQ_BIT_EN_1
#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_MASK 0x0003FF00U
-#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1_WIDTH 10U
#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_344
#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_344__PHY_WDQLVL_DVW_MIN_1
@@ -1454,8 +1453,8 @@
#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_344
#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_344__PHY_SW_WDQLVL_DVW_MIN_EN_1
-#define LPDDR4__DENALI_PHY_345_READ_MASK 0x1F1F0F3FU
-#define LPDDR4__DENALI_PHY_345_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_345_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_345_WRITE_MASK 0x1F1F0F3FU
#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH 6U
@@ -1463,156 +1462,156 @@
#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_345__PHY_WDQLVL_PER_START_OFFSET_1
#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1_WIDTH 4U
#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_345
#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_345__PHY_FAST_LVL_EN_1
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1_WIDTH 5U
#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_345
#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_TX_DCD_1
#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_345
#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_345__PHY_PAD_RX_DCD_0_1
-#define LPDDR4__DENALI_PHY_346_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_346_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_346_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_346_WRITE_MASK 0x1F1F1F1FU
#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_346
#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_1_1
#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_346
#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_2_1
#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_346
#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_3_1
#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_346
#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_RX_DCD_4_1
-#define LPDDR4__DENALI_PHY_347_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_347_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_347_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_347_WRITE_MASK 0x1F1F1F1FU
#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_347
#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_5_1
#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_347
#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_6_1
#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_347
#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_RX_DCD_7_1
#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1_WIDTH 5U
#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_347
#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_347__PHY_PAD_DM_RX_DCD_1
-#define LPDDR4__DENALI_PHY_348_READ_MASK 0x003F1F1FU
-#define LPDDR4__DENALI_PHY_348_WRITE_MASK 0x003F1F1FU
+#define LPDDR4__DENALI_PHY_348_READ_MASK 0x003F1F1FU
+#define LPDDR4__DENALI_PHY_348_WRITE_MASK 0x003F1F1FU
#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1_WIDTH 5U
#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_348
#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DQS_RX_DCD_1
#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1_WIDTH 5U
#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_348
#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_FDBK_RX_DCD_1
#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1_WIDTH 6U
#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_348
#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_348__PHY_PAD_DSLICE_IO_CFG_1
-#define LPDDR4__DENALI_PHY_349_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_349_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_349_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_349_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_349
#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ0_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_349
#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDQ1_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_350_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_350_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_350_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_350_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_350
#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ2_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_350
#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_350__PHY_RDDQ3_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_351_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_351_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_351_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_351_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_351
#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ4_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_351
#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_351__PHY_RDDQ5_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_352_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_352_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_352_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_352_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_352
#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ6_SLAVE_DELAY_1
#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_352
#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_352__PHY_RDDQ7_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_353_READ_MASK 0x000703FFU
-#define LPDDR4__DENALI_PHY_353_WRITE_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_353_READ_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_353_WRITE_MASK 0x000703FFU
#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1_WIDTH 10U
#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_353
#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_353__PHY_RDDM_SLAVE_DELAY_1
@@ -1622,34 +1621,34 @@
#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__REG DENALI_PHY_353
#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_353__PHY_DATA_DC_CAL_CLK_SEL_1
-#define LPDDR4__DENALI_PHY_354_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_354_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_354_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_354_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1_WIDTH 8U
#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_354
#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_OE_TIMING_1
#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1_WIDTH 8U
#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_354
#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_RD_TIMING_1
#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1_WIDTH 8U
#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_354
#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQ_TSEL_WR_TIMING_1
#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1_WIDTH 8U
#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_354
#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_354__PHY_DQS_OE_TIMING_1
-#define LPDDR4__DENALI_PHY_355_READ_MASK 0xFFFFFF0FU
-#define LPDDR4__DENALI_PHY_355_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_355_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_355_WRITE_MASK 0xFFFFFF0FU
#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1_WIDTH 4U
@@ -1657,118 +1656,118 @@
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_IO_PAD_DELAY_TIMING_1
#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1_WIDTH 8U
#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_355
#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_RD_TIMING_1
#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1_WIDTH 8U
#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_355
#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_OE_RD_TIMING_1
#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1_WIDTH 8U
#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_355
#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_355__PHY_DQS_TSEL_WR_TIMING_1
-#define LPDDR4__DENALI_PHY_356_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_356_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_356_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_356_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_WIDTH 16U
+#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1_WIDTH 16U
#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_356
#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_356__PHY_VREF_SETTING_TIME_1
#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_WIDTH 12U
+#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1_WIDTH 12U
#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_356
#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_356__PHY_PAD_VREF_CTRL_DQ_1
-#define LPDDR4__DENALI_PHY_357_READ_MASK 0x03FFFF01U
-#define LPDDR4__DENALI_PHY_357_WRITE_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_357_READ_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_357_WRITE_MASK 0x03FFFF01U
#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1_WOSET 0U
#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__REG DENALI_PHY_357
#define LPDDR4__PHY_PER_CS_TRAINING_EN_1__FLD LPDDR4__DENALI_PHY_357__PHY_PER_CS_TRAINING_EN_1
#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1_WIDTH 8U
#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_357
#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQ_IE_TIMING_1
#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1_WIDTH 8U
#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_357
#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_DQS_IE_TIMING_1
#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_MASK 0x03000000U
-#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1_WIDTH 2U
#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_357
#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_357__PHY_RDDATA_EN_IE_DLY_1
-#define LPDDR4__DENALI_PHY_358_READ_MASK 0x1F1F0103U
-#define LPDDR4__DENALI_PHY_358_WRITE_MASK 0x1F1F0103U
-#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_358_READ_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_358_WRITE_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1_WIDTH 2U
#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_358
#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_IE_MODE_1
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1_WOSET 0U
#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_358
#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_358__PHY_DBI_MODE_1
#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_358
#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_TSEL_DLY_1
#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_358
#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_OE_DLY_1
-#define LPDDR4__DENALI_PHY_359_READ_MASK 0x3F07FF0FU
-#define LPDDR4__DENALI_PHY_359_WRITE_MASK 0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_359_READ_MASK 0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_359_WRITE_MASK 0x3F07FF0FU
#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1_WIDTH 4U
#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_359
#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_359__PHY_SW_MASTER_MODE_1
#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_MASK 0x0007FF00U
-#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_SHIFT 8U
#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1_WIDTH 11U
#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_359
#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_START_1
#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_WIDTH 6U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1_WIDTH 6U
#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_359
#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_359__PHY_MASTER_DELAY_STEP_1
-#define LPDDR4__DENALI_PHY_360_READ_MASK 0xFF0FFFFFU
-#define LPDDR4__DENALI_PHY_360_WRITE_MASK 0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_360_READ_MASK 0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_360_WRITE_MASK 0xFF0FFFFFU
#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1_WIDTH 8U
#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_360
#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_WAIT_1
@@ -1779,19 +1778,19 @@
#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_360__PHY_MASTER_DELAY_HALF_MEASURE_1
#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1_WIDTH 4U
#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_360
#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_360__PHY_RPTR_UPDATE_1
#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1_WIDTH 8U
#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_360
#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_360__PHY_WRLVL_DLY_STEP_1
-#define LPDDR4__DENALI_PHY_361_READ_MASK 0x1F0F3F0FU
-#define LPDDR4__DENALI_PHY_361_WRITE_MASK 0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_361_READ_MASK 0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_361_WRITE_MASK 0x1F0F3F0FU
#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_361__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH 4U
@@ -1805,8 +1804,8 @@
#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_WRLVL_RESP_WAIT_CNT_1
#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1_WIDTH 4U
#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_361
#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_DLY_STEP_1
@@ -1816,25 +1815,25 @@
#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_361
#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_361__PHY_GTLVL_RESP_WAIT_CNT_1
-#define LPDDR4__DENALI_PHY_362_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_362_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_362_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_362_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1_WIDTH 10U
#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_362
#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_BACK_STEP_1
#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1_WIDTH 10U
#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_362
#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_362__PHY_GTLVL_FINAL_STEP_1
-#define LPDDR4__DENALI_PHY_363_READ_MASK 0x0F010FFFU
-#define LPDDR4__DENALI_PHY_363_WRITE_MASK 0x0F010FFFU
+#define LPDDR4__DENALI_PHY_363_READ_MASK 0x0F010FFFU
+#define LPDDR4__DENALI_PHY_363_WRITE_MASK 0x0F010FFFU
#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_WIDTH 8U
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1_WIDTH 8U
#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_363
#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_WDQLVL_DLY_STEP_1
@@ -1846,31 +1845,31 @@
#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1_WOSET 0U
#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_363
#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_363__PHY_TOGGLE_PRE_SUPPORT_1
#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_MASK 0x0F000000U
-#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1_WIDTH 4U
#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_363
#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_363__PHY_RDLVL_DLY_STEP_1
-#define LPDDR4__DENALI_PHY_364_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_364_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_364_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_364_WRITE_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1_WIDTH 10U
#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_364
#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_364__PHY_RDLVL_MAX_EDGE_1
-#define LPDDR4__DENALI_PHY_365_READ_MASK 0x3F0103FFU
-#define LPDDR4__DENALI_PHY_365_WRITE_MASK 0x3F0103FFU
+#define LPDDR4__DENALI_PHY_365_READ_MASK 0x3F0103FFU
+#define LPDDR4__DENALI_PHY_365_WRITE_MASK 0x3F0103FFU
#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_WIDTH 10U
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1_WIDTH 10U
#define LPDDR4__PHY_RDLVL_DVW_MIN_1__REG DENALI_PHY_365
#define LPDDR4__PHY_RDLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_DVW_MIN_1
@@ -1888,8 +1887,8 @@
#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__REG DENALI_PHY_365
#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_365__PHY_RDLVL_PER_START_OFFSET_1
-#define LPDDR4__DENALI_PHY_366_READ_MASK 0x00030703U
-#define LPDDR4__DENALI_PHY_366_WRITE_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_366_READ_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_366_WRITE_MASK 0x00030703U
#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1_WIDTH 2U
@@ -1897,8 +1896,8 @@
#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_DISABLE_1
#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_MASK 0x00000700U
-#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_WIDTH 3U
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1_WIDTH 3U
#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_366
#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRPATH_GATE_TIMING_1
@@ -1908,8 +1907,8 @@
#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__REG DENALI_PHY_366
#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_1__FLD LPDDR4__DENALI_PHY_366__PHY_DATA_DC_INIT_DISABLE_1
-#define LPDDR4__DENALI_PHY_367_READ_MASK 0x07FF03FFU
-#define LPDDR4__DENALI_PHY_367_WRITE_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_367_READ_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_367_WRITE_MASK 0x07FF03FFU
#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQS_INIT_SLV_DELAY_1_WIDTH 10U
@@ -1922,8 +1921,8 @@
#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__REG DENALI_PHY_367
#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_DATA_DC_DQ_INIT_SLV_DELAY_1
-#define LPDDR4__DENALI_PHY_368_READ_MASK 0xFFFF0101U
-#define LPDDR4__DENALI_PHY_368_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_368_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_368_WRITE_MASK 0xFFFF0101U
#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_368__PHY_DATA_DC_WRLVL_ENABLE_1_WIDTH 1U
@@ -1952,11 +1951,11 @@
#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__REG DENALI_PHY_368
#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1__FLD LPDDR4__DENALI_PHY_368__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1
-#define LPDDR4__DENALI_PHY_369_READ_MASK 0x001F3F7FU
-#define LPDDR4__DENALI_PHY_369_WRITE_MASK 0x001F3F7FU
+#define LPDDR4__DENALI_PHY_369_READ_MASK 0x001F3F7FU
+#define LPDDR4__DENALI_PHY_369_WRITE_MASK 0x001F3F7FU
#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_WIDTH 7U
+#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1_WIDTH 7U
#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_369
#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_369__PHY_WDQ_OSC_DELTA_1
@@ -1967,29 +1966,29 @@
#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_369__PHY_MEAS_DLY_STEP_ENABLE_1
#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_369
#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDATA_EN_DLY_1
-#define LPDDR4__DENALI_PHY_370_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_370_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_370_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_370_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1_WIDTH 32U
#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_370
#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_370__PHY_DQ_DM_SWIZZLE0_1
-#define LPDDR4__DENALI_PHY_371_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_371_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_371_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_371_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1_WIDTH 4U
#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_371
#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_371__PHY_DQ_DM_SWIZZLE1_1
-#define LPDDR4__DENALI_PHY_372_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_372_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_372_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH 11U
@@ -2002,8 +2001,8 @@
#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_372
#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_CLK_WRDQ1_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_373_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_373_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_373_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_373_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH 11U
@@ -2016,8 +2015,8 @@
#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_373
#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_CLK_WRDQ3_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_374_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_374_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_374_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_374_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH 11U
@@ -2030,8 +2029,8 @@
#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_374
#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_CLK_WRDQ5_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_375_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_375_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_375_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_375_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH 11U
@@ -2044,8 +2043,8 @@
#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_375
#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_CLK_WRDQ7_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_376_READ_MASK 0x03FF07FFU
-#define LPDDR4__DENALI_PHY_376_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_376_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_376_WRITE_MASK 0x03FF07FFU
#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_376__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH 11U
@@ -2058,8 +2057,8 @@
#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_376
#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_376__PHY_CLK_WRDQS_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_377_READ_MASK 0x0003FF03U
-#define LPDDR4__DENALI_PHY_377_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_377_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_377_WRITE_MASK 0x0003FF03U
#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH 2U
@@ -2072,8 +2071,8 @@
#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_377
#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_377__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_378_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_378_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_378_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH 10U
@@ -2086,8 +2085,8 @@
#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_378
#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_378__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_379_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_379_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_379_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH 10U
@@ -2100,8 +2099,8 @@
#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_379
#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_379__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_380_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_380_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_380_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH 10U
@@ -2114,8 +2113,8 @@
#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_380
#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_381_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_381_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_381_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH 10U
@@ -2128,8 +2127,8 @@
#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_381
#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_381__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_382_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_382_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_382_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH 10U
@@ -2142,8 +2141,8 @@
#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_382
#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_382__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_383_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_383_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_383_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH 10U
@@ -2156,8 +2155,8 @@
#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_383
#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_383__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_384_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_384_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_384_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_384_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH 10U
@@ -2170,8 +2169,8 @@
#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_384
#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_384__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_385_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_385_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_385_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_385_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_385__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH 10U
@@ -2184,8 +2183,8 @@
#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_385
#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_385__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_386_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_386_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_386_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_386_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_386__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH 10U
@@ -2198,8 +2197,8 @@
#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_386
#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_386__PHY_RDDQS_GATE_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_387_READ_MASK 0x03FF070FU
-#define LPDDR4__DENALI_PHY_387_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_387_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_387_WRITE_MASK 0x03FF070FU
#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH 4U
@@ -2207,8 +2206,8 @@
#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_387__PHY_RDDQS_LATENCY_ADJUST_1
#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_MASK 0x00000700U
-#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_WIDTH 3U
+#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1_WIDTH 3U
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_387
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRITE_PATH_LAT_ADD_1
@@ -2218,8 +2217,8 @@
#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_387
#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_387__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1
-#define LPDDR4__DENALI_PHY_388_READ_MASK 0x000103FFU
-#define LPDDR4__DENALI_PHY_388_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_388_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_388_WRITE_MASK 0x000103FFU
#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_388__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH 10U
@@ -2234,8 +2233,8 @@
#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_388
#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_388__PHY_WRLVL_EARLY_FORCE_ZERO_1
-#define LPDDR4__DENALI_PHY_389_READ_MASK 0x000F03FFU
-#define LPDDR4__DENALI_PHY_389_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_389_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_389_WRITE_MASK 0x000F03FFU
#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_389__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH 10U
@@ -2248,8 +2247,8 @@
#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_389
#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_389__PHY_GTLVL_LAT_ADJ_START_1
-#define LPDDR4__DENALI_PHY_390_READ_MASK 0x010F07FFU
-#define LPDDR4__DENALI_PHY_390_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_390_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_390_WRITE_MASK 0x010F07FFU
#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH 11U
@@ -2257,29 +2256,29 @@
#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_WDQLVL_DQDM_SLV_DLY_START_1
#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1_WIDTH 4U
#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_390
#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_WRLAT_START_1
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WIDTH 1U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOCLR 0U
-#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOSET 0U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WIDTH 1U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOCLR 0U
+#define LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1_WOSET 0U
#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_390
#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_390__PHY_NTP_PASS_1
-#define LPDDR4__DENALI_PHY_391_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_391_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_391_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_391_WRITE_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH 10U
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_391
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_391__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1
-#define LPDDR4__DENALI_PHY_392_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_392_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_392_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_392_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQS_CLK_ADJUST_1_WIDTH 8U
@@ -2304,8 +2303,8 @@
#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__REG DENALI_PHY_392
#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_392__PHY_DATA_DC_DQ2_CLK_ADJUST_1
-#define LPDDR4__DENALI_PHY_393_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_393_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_393_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_393_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ3_CLK_ADJUST_1_WIDTH 8U
@@ -2330,8 +2329,8 @@
#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__REG DENALI_PHY_393
#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_1__FLD LPDDR4__DENALI_PHY_393__PHY_DATA_DC_DQ6_CLK_ADJUST_1
-#define LPDDR4__DENALI_PHY_394_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_394_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_394_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_394_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_394__PHY_DATA_DC_DQ7_CLK_ADJUST_1_WIDTH 8U
@@ -2350,23 +2349,23 @@
#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_394
#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_394__PHY_DSLICE_PAD_BOOSTPN_SETTING_1
-#define LPDDR4__DENALI_PHY_395_READ_MASK 0x0003033FU
-#define LPDDR4__DENALI_PHY_395_WRITE_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_395_READ_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_395_WRITE_MASK 0x0003033FU
#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH 6U
#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_395
#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_395__PHY_DSLICE_PAD_RX_CTLE_SETTING_1
-#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1_WIDTH 2U
#define LPDDR4__PHY_DQ_FFE_1__REG DENALI_PHY_395
#define LPDDR4__PHY_DQ_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQ_FFE_1
-#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_WIDTH 2U
+#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1_WIDTH 2U
#define LPDDR4__PHY_DQS_FFE_1__REG DENALI_PHY_395
#define LPDDR4__PHY_DQS_FFE_1__FLD LPDDR4__DENALI_PHY_395__PHY_DQS_FFE_1
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
similarity index 66%
rename from drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h
rename to drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
index 7c3756c..f6edad4 100644
--- a/drivers/ram/k3-j721e/lpddr4_data_slice_2_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
@@ -1,17 +1,16 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
*
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
#define REG_LPDDR4_DATA_SLICE_2_MACROS_H_
-#define LPDDR4__DENALI_PHY_512_READ_MASK 0x000F07FFU
-#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_512_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_512_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_512__PHY_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH 11U
@@ -24,8 +23,8 @@
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__REG DENALI_PHY_512
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_2__FLD LPDDR4__DENALI_PHY_512__PHY_IO_PAD_DELAY_TIMING_BYPASS_2
-#define LPDDR4__DENALI_PHY_513_READ_MASK 0x000703FFU
-#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_513_READ_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_513_WRITE_MASK 0x000703FFU
#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_513__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2_WIDTH 10U
@@ -38,8 +37,8 @@
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__REG DENALI_PHY_513
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_2__FLD LPDDR4__DENALI_PHY_513__PHY_WRITE_PATH_LAT_ADD_BYPASS_2
-#define LPDDR4__DENALI_PHY_514_READ_MASK 0x010303FFU
-#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_514_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_514_WRITE_MASK 0x010303FFU
#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_514__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2_WIDTH 10U
@@ -60,75 +59,75 @@
#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_514
#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_514__PHY_CLK_BYPASS_OVERRIDE_2
-#define LPDDR4__DENALI_PHY_515_READ_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_515_WRITE_MASK 0x3F3F3F3FU
#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__REG DENALI_PHY_515
#define LPDDR4__PHY_SW_WRDQ0_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ0_SHIFT_2
#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__REG DENALI_PHY_515
#define LPDDR4__PHY_SW_WRDQ1_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ1_SHIFT_2
#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__REG DENALI_PHY_515
#define LPDDR4__PHY_SW_WRDQ2_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ2_SHIFT_2
#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__REG DENALI_PHY_515
#define LPDDR4__PHY_SW_WRDQ3_SHIFT_2__FLD LPDDR4__DENALI_PHY_515__PHY_SW_WRDQ3_SHIFT_2
-#define LPDDR4__DENALI_PHY_516_READ_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_516_WRITE_MASK 0x3F3F3F3FU
#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__REG DENALI_PHY_516
#define LPDDR4__PHY_SW_WRDQ4_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ4_SHIFT_2
#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__REG DENALI_PHY_516
#define LPDDR4__PHY_SW_WRDQ5_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ5_SHIFT_2
#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__REG DENALI_PHY_516
#define LPDDR4__PHY_SW_WRDQ6_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ6_SHIFT_2
#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__REG DENALI_PHY_516
#define LPDDR4__PHY_SW_WRDQ7_SHIFT_2__FLD LPDDR4__DENALI_PHY_516__PHY_SW_WRDQ7_SHIFT_2
-#define LPDDR4__DENALI_PHY_517_READ_MASK 0x01030F3FU
-#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_517_READ_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_517_WRITE_MASK 0x01030F3FU
#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2_WIDTH 6U
#define LPDDR4__PHY_SW_WRDM_SHIFT_2__REG DENALI_PHY_517
#define LPDDR4__PHY_SW_WRDM_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDM_SHIFT_2
#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH 4U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2_WIDTH 4U
#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__REG DENALI_PHY_517
#define LPDDR4__PHY_SW_WRDQS_SHIFT_2__FLD LPDDR4__DENALI_PHY_517__PHY_SW_WRDQS_SHIFT_2
#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2_WIDTH 2U
#define LPDDR4__PHY_PER_RANK_CS_MAP_2__REG DENALI_PHY_517
#define LPDDR4__PHY_PER_RANK_CS_MAP_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_RANK_CS_MAP_2
@@ -140,8 +139,8 @@
#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__REG DENALI_PHY_517
#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_2__FLD LPDDR4__DENALI_PHY_517__PHY_PER_CS_TRAINING_MULTICAST_EN_2
-#define LPDDR4__DENALI_PHY_518_READ_MASK 0x1F1F0301U
-#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518_READ_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_518_WRITE_MASK 0x1F1F0301U
#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_518__PHY_PER_CS_TRAINING_INDEX_2_WIDTH 1U
@@ -168,8 +167,8 @@
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_518
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_518__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2
-#define LPDDR4__DENALI_PHY_519_READ_MASK 0x1F030F0FU
-#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519_READ_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_519_WRITE_MASK 0x1F030F0FU
#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RPTR_UPDATE_2_WIDTH 4U
@@ -194,17 +193,17 @@
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_519
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_519__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2
-#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0101FF03U
-#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_520_READ_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_520_WRITE_MASK 0x0101FF03U
#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2_WIDTH 2U
#define LPDDR4__PHY_CTRL_LPBK_EN_2__REG DENALI_PHY_520
#define LPDDR4__PHY_CTRL_LPBK_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_CTRL_LPBK_EN_2
#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2_WIDTH 9U
#define LPDDR4__PHY_LPBK_CONTROL_2__REG DENALI_PHY_520
#define LPDDR4__PHY_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_CONTROL_2
@@ -216,33 +215,33 @@
#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__REG DENALI_PHY_520
#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_2__FLD LPDDR4__DENALI_PHY_520__PHY_LPBK_DFX_TIMEOUT_EN_2
-#define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2_WIDTH 32U
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__REG DENALI_PHY_521
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_2__FLD LPDDR4__DENALI_PHY_521__PHY_AUTO_TIMING_MARGIN_CONTROL_2
-#define LPDDR4__DENALI_PHY_522_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_522_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_522_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2_WIDTH 28U
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__REG DENALI_PHY_522
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_2__FLD LPDDR4__DENALI_PHY_522__PHY_AUTO_TIMING_MARGIN_OBS_2
-#define LPDDR4__DENALI_PHY_523_READ_MASK 0x0101FF7FU
-#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x0101FF7FU
+#define LPDDR4__DENALI_PHY_523_READ_MASK 0x0101FF7FU
+#define LPDDR4__DENALI_PHY_523_WRITE_MASK 0x0101FF7FU
#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_WIDTH 7U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2_WIDTH 7U
#define LPDDR4__PHY_PRBS_PATTERN_START_2__REG DENALI_PHY_523
#define LPDDR4__PHY_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_START_2
#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2_WIDTH 9U
#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__REG DENALI_PHY_523
#define LPDDR4__PHY_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_523__PHY_PRBS_PATTERN_MASK_2
@@ -254,8 +253,8 @@
#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__REG DENALI_PHY_523
#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_2__FLD LPDDR4__DENALI_PHY_523__PHY_RDLVL_MULTI_PATT_ENABLE_2
-#define LPDDR4__DENALI_PHY_524_READ_MASK 0x007F3F01U
-#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x007F3F01U
+#define LPDDR4__DENALI_PHY_524_READ_MASK 0x007F3F01U
+#define LPDDR4__DENALI_PHY_524_WRITE_MASK 0x007F3F01U
#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_524__PHY_RDLVL_MULTI_PATT_RST_DISABLE_2_WIDTH 1U
@@ -271,13 +270,13 @@
#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_INITIAL_STEPSIZE_2
#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_MASK 0x007F0000U
-#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_WIDTH 7U
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2_WIDTH 7U
#define LPDDR4__PHY_VREF_TRAIN_OBS_2__REG DENALI_PHY_524
#define LPDDR4__PHY_VREF_TRAIN_OBS_2__FLD LPDDR4__DENALI_PHY_524__PHY_VREF_TRAIN_OBS_2
-#define LPDDR4__DENALI_PHY_525_READ_MASK 0x000F03FFU
-#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_525_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_525_WRITE_MASK 0x000F03FFU
#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_525__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2_WIDTH 10U
@@ -291,37 +290,37 @@
#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_2__FLD LPDDR4__DENALI_PHY_525__PHY_GATE_ERROR_DELAY_SELECT_2
#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2_WOSET 0U
#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__REG DENALI_PHY_525
#define LPDDR4__SC_PHY_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_525__SC_PHY_SNAP_OBS_REGS_2
-#define LPDDR4__DENALI_PHY_526_READ_MASK 0x070101FFU
-#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x070101FFU
+#define LPDDR4__DENALI_PHY_526_READ_MASK 0x070101FFU
+#define LPDDR4__DENALI_PHY_526_WRITE_MASK 0x070101FFU
#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2_WIDTH 9U
#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__REG DENALI_PHY_526
#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_526__PHY_GATE_SMPL1_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_526__PHY_LPDDR_2_WOSET 0U
#define LPDDR4__PHY_LPDDR_2__REG DENALI_PHY_526
#define LPDDR4__PHY_LPDDR_2__FLD LPDDR4__DENALI_PHY_526__PHY_LPDDR_2
-#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_WIDTH 3U
+#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2_WIDTH 3U
#define LPDDR4__PHY_MEM_CLASS_2__REG DENALI_PHY_526
#define LPDDR4__PHY_MEM_CLASS_2__FLD LPDDR4__DENALI_PHY_526__PHY_MEM_CLASS_2
-#define LPDDR4__DENALI_PHY_527_READ_MASK 0x000301FFU
-#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x000301FFU
+#define LPDDR4__DENALI_PHY_527_READ_MASK 0x000301FFU
+#define LPDDR4__DENALI_PHY_527_WRITE_MASK 0x000301FFU
#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2_WIDTH 9U
@@ -329,101 +328,101 @@
#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_527__PHY_GATE_SMPL2_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2_WIDTH 2U
#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__REG DENALI_PHY_527
#define LPDDR4__ON_FLY_GATE_ADJUST_EN_2__FLD LPDDR4__DENALI_PHY_527__ON_FLY_GATE_ADJUST_EN_2
-#define LPDDR4__DENALI_PHY_528_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_528_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_528_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2_WIDTH 32U
#define LPDDR4__PHY_GATE_TRACKING_OBS_2__REG DENALI_PHY_528
#define LPDDR4__PHY_GATE_TRACKING_OBS_2__FLD LPDDR4__DENALI_PHY_528__PHY_GATE_TRACKING_OBS_2
-#define LPDDR4__DENALI_PHY_529_READ_MASK 0x00000301U
-#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_529_READ_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_529_WRITE_MASK 0x00000301U
#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2_WOSET 0U
#define LPDDR4__PHY_DFI40_POLARITY_2__REG DENALI_PHY_529
#define LPDDR4__PHY_DFI40_POLARITY_2__FLD LPDDR4__DENALI_PHY_529__PHY_DFI40_POLARITY_2
#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2_WIDTH 2U
#define LPDDR4__PHY_LP4_PST_AMBLE_2__REG DENALI_PHY_529
#define LPDDR4__PHY_LP4_PST_AMBLE_2__FLD LPDDR4__DENALI_PHY_529__PHY_LP4_PST_AMBLE_2
-#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT8_2__REG DENALI_PHY_530
#define LPDDR4__PHY_RDLVL_PATT8_2__FLD LPDDR4__DENALI_PHY_530__PHY_RDLVL_PATT8_2
-#define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT9_2__REG DENALI_PHY_531
#define LPDDR4__PHY_RDLVL_PATT9_2__FLD LPDDR4__DENALI_PHY_531__PHY_RDLVL_PATT9_2
-#define LPDDR4__DENALI_PHY_532_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_532_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT10_2__REG DENALI_PHY_532
#define LPDDR4__PHY_RDLVL_PATT10_2__FLD LPDDR4__DENALI_PHY_532__PHY_RDLVL_PATT10_2
-#define LPDDR4__DENALI_PHY_533_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_533_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT11_2__REG DENALI_PHY_533
#define LPDDR4__PHY_RDLVL_PATT11_2__FLD LPDDR4__DENALI_PHY_533__PHY_RDLVL_PATT11_2
-#define LPDDR4__DENALI_PHY_534_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_534_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT12_2__REG DENALI_PHY_534
#define LPDDR4__PHY_RDLVL_PATT12_2__FLD LPDDR4__DENALI_PHY_534__PHY_RDLVL_PATT12_2
-#define LPDDR4__DENALI_PHY_535_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_535_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT13_2__REG DENALI_PHY_535
#define LPDDR4__PHY_RDLVL_PATT13_2__FLD LPDDR4__DENALI_PHY_535__PHY_RDLVL_PATT13_2
-#define LPDDR4__DENALI_PHY_536_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_536_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT14_2__REG DENALI_PHY_536
#define LPDDR4__PHY_RDLVL_PATT14_2__FLD LPDDR4__DENALI_PHY_536__PHY_RDLVL_PATT14_2
-#define LPDDR4__DENALI_PHY_537_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_537_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT15_2__REG DENALI_PHY_537
#define LPDDR4__PHY_RDLVL_PATT15_2__FLD LPDDR4__DENALI_PHY_537__PHY_RDLVL_PATT15_2
-#define LPDDR4__DENALI_PHY_538_READ_MASK 0x070F0107U
-#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_538_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_538_WRITE_MASK 0x070F0107U
#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_538__PHY_SLAVE_LOOP_CNT_UPDATE_2_WIDTH 3U
@@ -450,8 +449,8 @@
#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__REG DENALI_PHY_538
#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_538__PHY_RDDQ_ENC_OBS_SELECT_2
-#define LPDDR4__DENALI_PHY_539_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_539_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_539_WRITE_MASK 0x0F0F0F0FU
#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2_WIDTH 4U
@@ -459,8 +458,8 @@
#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_RDDQS_DQ_ENC_OBS_SELECT_2
#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_WIDTH 4U
+#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2_WIDTH 4U
#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__REG DENALI_PHY_539
#define LPDDR4__PHY_WR_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_WR_ENC_OBS_SELECT_2
@@ -476,41 +475,41 @@
#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__REG DENALI_PHY_539
#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_539__PHY_FIFO_PTR_OBS_SELECT_2
-#define LPDDR4__DENALI_PHY_540_READ_MASK 0xFF030001U
-#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0xFF030001U
+#define LPDDR4__DENALI_PHY_540_READ_MASK 0xFF030001U
+#define LPDDR4__DENALI_PHY_540_WRITE_MASK 0xFF030001U
#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2_WOSET 0U
#define LPDDR4__PHY_LVL_DEBUG_MODE_2__REG DENALI_PHY_540
#define LPDDR4__PHY_LVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_540__PHY_LVL_DEBUG_MODE_2
#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2_WOSET 0U
#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__REG DENALI_PHY_540
#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_540__SC_PHY_LVL_DEBUG_CONT_2
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2_WIDTH 2U
#define LPDDR4__PHY_WRLVL_ALGO_2__REG DENALI_PHY_540
#define LPDDR4__PHY_WRLVL_ALGO_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_ALGO_2
#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2_WIDTH 8U
#define LPDDR4__PHY_WRLVL_PER_START_2__REG DENALI_PHY_540
#define LPDDR4__PHY_WRLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_540__PHY_WRLVL_PER_START_2
-#define LPDDR4__DENALI_PHY_541_READ_MASK 0x00FF0F3FU
-#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_541_READ_MASK 0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_541_WRITE_MASK 0x00FF0F3FU
#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2_WIDTH 6U
#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__REG DENALI_PHY_541
#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_CAPTURE_CNT_2
@@ -520,23 +519,23 @@
#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_541
#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_541__PHY_WRLVL_UPDT_WAIT_CNT_2
-#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2_WIDTH 8U
#define LPDDR4__PHY_DQ_MASK_2__REG DENALI_PHY_541
#define LPDDR4__PHY_DQ_MASK_2__FLD LPDDR4__DENALI_PHY_541__PHY_DQ_MASK_2
-#define LPDDR4__DENALI_PHY_542_READ_MASK 0x0F3F03FFU
-#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_542_READ_MASK 0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_542_WRITE_MASK 0x0F3F03FFU
#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2_WIDTH 10U
#define LPDDR4__PHY_GTLVL_PER_START_2__REG DENALI_PHY_542
#define LPDDR4__PHY_GTLVL_PER_START_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_PER_START_2
#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2_WIDTH 6U
#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__REG DENALI_PHY_542
#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_CAPTURE_CNT_2
@@ -546,11 +545,11 @@
#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_542
#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_542__PHY_GTLVL_UPDT_WAIT_CNT_2
-#define LPDDR4__DENALI_PHY_543_READ_MASK 0x1F030F3FU
-#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_543_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_543_WRITE_MASK 0x1F030F3FU
#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2_WIDTH 6U
#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__REG DENALI_PHY_543
#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_CAPTURE_CNT_2
@@ -561,8 +560,8 @@
#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_UPDT_WAIT_CNT_2
#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2_WIDTH 2U
#define LPDDR4__PHY_RDLVL_OP_MODE_2__REG DENALI_PHY_543
#define LPDDR4__PHY_RDLVL_OP_MODE_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_OP_MODE_2
@@ -572,8 +571,8 @@
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__REG DENALI_PHY_543
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_543__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2
-#define LPDDR4__DENALI_PHY_544_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_544_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_544_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2_WIDTH 8U
@@ -581,8 +580,8 @@
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_PERIODIC_OBS_SELECT_2
#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2_WIDTH 8U
#define LPDDR4__PHY_RDLVL_DATA_MASK_2__REG DENALI_PHY_544
#define LPDDR4__PHY_RDLVL_DATA_MASK_2__FLD LPDDR4__DENALI_PHY_544__PHY_RDLVL_DATA_MASK_2
@@ -593,16 +592,16 @@
#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_CLK_JITTER_TOLERANCE_2
#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2_WIDTH 6U
#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__REG DENALI_PHY_544
#define LPDDR4__PHY_WDQLVL_BURST_CNT_2__FLD LPDDR4__DENALI_PHY_544__PHY_WDQLVL_BURST_CNT_2
-#define LPDDR4__DENALI_PHY_545_READ_MASK 0x0F07FF07U
-#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x0F07FF07U
+#define LPDDR4__DENALI_PHY_545_READ_MASK 0x0F07FF07U
+#define LPDDR4__DENALI_PHY_545_WRITE_MASK 0x0F07FF07U
#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_WIDTH 3U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2_WIDTH 3U
#define LPDDR4__PHY_WDQLVL_PATT_2__REG DENALI_PHY_545
#define LPDDR4__PHY_WDQLVL_PATT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_PATT_2
@@ -618,8 +617,8 @@
#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__REG DENALI_PHY_545
#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_545__PHY_WDQLVL_UPDT_WAIT_CNT_2
-#define LPDDR4__DENALI_PHY_546_READ_MASK 0x0000FF0FU
-#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PHY_546_READ_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PHY_546_WRITE_MASK 0x0000FF0FU
#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_546__PHY_WDQLVL_DQDM_OBS_SELECT_2_WIDTH 4U
@@ -640,64 +639,64 @@
#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__REG DENALI_PHY_546
#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2__FLD LPDDR4__DENALI_PHY_546__SC_PHY_WDQLVL_CLR_PREV_RESULTS_2
-#define LPDDR4__DENALI_PHY_547_READ_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_547_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_547_WRITE_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2_WIDTH 9U
#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__REG DENALI_PHY_547
#define LPDDR4__PHY_WDQLVL_DATADM_MASK_2__FLD LPDDR4__DENALI_PHY_547__PHY_WDQLVL_DATADM_MASK_2
-#define LPDDR4__DENALI_PHY_548_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_548_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_548_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2_WIDTH 32U
#define LPDDR4__PHY_USER_PATT0_2__REG DENALI_PHY_548
#define LPDDR4__PHY_USER_PATT0_2__FLD LPDDR4__DENALI_PHY_548__PHY_USER_PATT0_2
-#define LPDDR4__DENALI_PHY_549_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_549_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_549_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2_WIDTH 32U
#define LPDDR4__PHY_USER_PATT1_2__REG DENALI_PHY_549
#define LPDDR4__PHY_USER_PATT1_2__FLD LPDDR4__DENALI_PHY_549__PHY_USER_PATT1_2
-#define LPDDR4__DENALI_PHY_550_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_550_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2_WIDTH 32U
#define LPDDR4__PHY_USER_PATT2_2__REG DENALI_PHY_550
#define LPDDR4__PHY_USER_PATT2_2__FLD LPDDR4__DENALI_PHY_550__PHY_USER_PATT2_2
-#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_551_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2_WIDTH 32U
#define LPDDR4__PHY_USER_PATT3_2__REG DENALI_PHY_551
#define LPDDR4__PHY_USER_PATT3_2__FLD LPDDR4__DENALI_PHY_551__PHY_USER_PATT3_2
-#define LPDDR4__DENALI_PHY_552_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_WIDTH 16U
+#define LPDDR4__DENALI_PHY_552_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_552_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2_WIDTH 16U
#define LPDDR4__PHY_USER_PATT4_2__REG DENALI_PHY_552
#define LPDDR4__PHY_USER_PATT4_2__FLD LPDDR4__DENALI_PHY_552__PHY_USER_PATT4_2
#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2_WOSET 0U
#define LPDDR4__PHY_NTP_MULT_TRAIN_2__REG DENALI_PHY_552
#define LPDDR4__PHY_NTP_MULT_TRAIN_2__FLD LPDDR4__DENALI_PHY_552__PHY_NTP_MULT_TRAIN_2
-#define LPDDR4__DENALI_PHY_553_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_553_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_553_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_553__PHY_NTP_EARLY_THRESHOLD_2_WIDTH 10U
@@ -710,8 +709,8 @@
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__REG DENALI_PHY_553
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_553__PHY_NTP_PERIOD_THRESHOLD_2
-#define LPDDR4__DENALI_PHY_554_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_554_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_554_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MIN_2_WIDTH 10U
@@ -724,8 +723,8 @@
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__REG DENALI_PHY_554
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_2__FLD LPDDR4__DENALI_PHY_554__PHY_NTP_PERIOD_THRESHOLD_MAX_2
-#define LPDDR4__DENALI_PHY_555_READ_MASK 0x00FF0001U
-#define LPDDR4__DENALI_PHY_555_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_555_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_555_WRITE_MASK 0x00FF0001U
#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2_WIDTH 1U
@@ -735,27 +734,27 @@
#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_2__FLD LPDDR4__DENALI_PHY_555__PHY_CALVL_VREF_DRIVING_SLICE_2
#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2_WIDTH 6U
#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__REG DENALI_PHY_555
#define LPDDR4__SC_PHY_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_555__SC_PHY_MANUAL_CLEAR_2
#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2_WIDTH 8U
#define LPDDR4__PHY_FIFO_PTR_OBS_2__REG DENALI_PHY_555
#define LPDDR4__PHY_FIFO_PTR_OBS_2__FLD LPDDR4__DENALI_PHY_555__PHY_FIFO_PTR_OBS_2
-#define LPDDR4__DENALI_PHY_556_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_556_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_556_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_556_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2_WIDTH 32U
#define LPDDR4__PHY_LPBK_RESULT_OBS_2__REG DENALI_PHY_556
#define LPDDR4__PHY_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_556__PHY_LPBK_RESULT_OBS_2
-#define LPDDR4__DENALI_PHY_557_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_557_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_557_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_557_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_557__PHY_LPBK_ERROR_COUNT_OBS_2_WIDTH 16U
@@ -768,8 +767,8 @@
#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_557
#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_557__PHY_MASTER_DLY_LOCK_OBS_2
-#define LPDDR4__DENALI_PHY_558_READ_MASK 0xFFFF7F7FU
-#define LPDDR4__DENALI_PHY_558_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_558_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_558_WRITE_MASK 0xFFFF7F7FU
#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_558__PHY_RDDQ_SLV_DLY_ENC_OBS_2_WIDTH 7U
@@ -794,8 +793,8 @@
#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_558
#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_558__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2
-#define LPDDR4__DENALI_PHY_559_READ_MASK 0x7F07FFFFU
-#define LPDDR4__DENALI_PHY_559_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_559_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_559_WRITE_MASK 0x7F07FFFFU
#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_559__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2_WIDTH 8U
@@ -814,8 +813,8 @@
#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_559
#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_559__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2
-#define LPDDR4__DENALI_PHY_560_READ_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_PHY_560_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_560_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_560_WRITE_MASK 0x0007FFFFU
#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_560__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2_WIDTH 8U
@@ -829,13 +828,13 @@
#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_ADDER_SLV_DLY_ENC_OBS_2
#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_MASK 0x00070000U
-#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_WIDTH 3U
+#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2_WIDTH 3U
#define LPDDR4__PHY_WR_SHIFT_OBS_2__REG DENALI_PHY_560
#define LPDDR4__PHY_WR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_560__PHY_WR_SHIFT_OBS_2
-#define LPDDR4__DENALI_PHY_561_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_561_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_561_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_561_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD0_DELAY_OBS_2_WIDTH 10U
@@ -848,16 +847,16 @@
#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_561
#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_561__PHY_WRLVL_HARD1_DELAY_OBS_2
-#define LPDDR4__DENALI_PHY_562_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_562_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_562_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_562_WRITE_MASK 0x0001FFFFU
#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_WIDTH 17U
+#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2_WIDTH 17U
#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__REG DENALI_PHY_562
#define LPDDR4__PHY_WRLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_562__PHY_WRLVL_STATUS_OBS_2
-#define LPDDR4__DENALI_PHY_563_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_563_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_563_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2_WIDTH 10U
@@ -870,11 +869,11 @@
#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_563
#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_563__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2
-#define LPDDR4__DENALI_PHY_564_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_564_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_564_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_564_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_WIDTH 16U
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2_WIDTH 16U
#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__REG DENALI_PHY_564
#define LPDDR4__PHY_WRLVL_ERROR_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_WRLVL_ERROR_OBS_2
@@ -884,24 +883,24 @@
#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__REG DENALI_PHY_564
#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_564__PHY_GTLVL_HARD0_DELAY_OBS_2
-#define LPDDR4__DENALI_PHY_565_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_565_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_565_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_565_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2_WIDTH 14U
#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__REG DENALI_PHY_565
#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_2__FLD LPDDR4__DENALI_PHY_565__PHY_GTLVL_HARD1_DELAY_OBS_2
-#define LPDDR4__DENALI_PHY_566_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_566_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_566_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_566_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_WIDTH 18U
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2_WIDTH 18U
#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__REG DENALI_PHY_566
#define LPDDR4__PHY_GTLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_566__PHY_GTLVL_STATUS_OBS_2
-#define LPDDR4__DENALI_PHY_567_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_567_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_567_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_567_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2_WIDTH 10U
@@ -914,32 +913,32 @@
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__REG DENALI_PHY_567
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_567__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2
-#define LPDDR4__DENALI_PHY_568_READ_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_568_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_568_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_568_WRITE_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2_WIDTH 2U
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__REG DENALI_PHY_568
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2__FLD LPDDR4__DENALI_PHY_568__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2
-#define LPDDR4__DENALI_PHY_569_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_569_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_569_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_569_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__REG DENALI_PHY_569
#define LPDDR4__PHY_RDLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_569__PHY_RDLVL_STATUS_OBS_2
-#define LPDDR4__DENALI_PHY_570_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_570_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_570_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_570_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__REG DENALI_PHY_570
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_570__PHY_RDLVL_PERIODIC_OBS_2
-#define LPDDR4__DENALI_PHY_571_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_571_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_571_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_571_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_LE_DLY_OBS_2_WIDTH 11U
@@ -952,56 +951,56 @@
#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__REG DENALI_PHY_571
#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_571__PHY_WDQLVL_DQDM_TE_DLY_OBS_2
-#define LPDDR4__DENALI_PHY_572_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_572_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_572_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_572_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2_WIDTH 32U
#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__REG DENALI_PHY_572
#define LPDDR4__PHY_WDQLVL_STATUS_OBS_2__FLD LPDDR4__DENALI_PHY_572__PHY_WDQLVL_STATUS_OBS_2
-#define LPDDR4__DENALI_PHY_573_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_573_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_573_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2_WIDTH 32U
#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__REG DENALI_PHY_573
#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_2__FLD LPDDR4__DENALI_PHY_573__PHY_WDQLVL_PERIODIC_OBS_2
-#define LPDDR4__DENALI_PHY_574_READ_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_574_WRITE_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_WIDTH 31U
+#define LPDDR4__DENALI_PHY_574_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_574_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2_WIDTH 31U
#define LPDDR4__PHY_DDL_MODE_2__REG DENALI_PHY_574
#define LPDDR4__PHY_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_574__PHY_DDL_MODE_2
-#define LPDDR4__DENALI_PHY_575_READ_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_575_WRITE_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_575_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_575_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2_WIDTH 6U
#define LPDDR4__PHY_DDL_MASK_2__REG DENALI_PHY_575
#define LPDDR4__PHY_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_575__PHY_DDL_MASK_2
-#define LPDDR4__DENALI_PHY_576_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_576_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_576_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_576_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2_WIDTH 32U
#define LPDDR4__PHY_DDL_TEST_OBS_2__REG DENALI_PHY_576
#define LPDDR4__PHY_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_576__PHY_DDL_TEST_OBS_2
-#define LPDDR4__DENALI_PHY_577_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_577_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_577_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2_WIDTH 32U
#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_577
#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_577__PHY_DDL_TEST_MSTR_DLY_OBS_2
-#define LPDDR4__DENALI_PHY_578_READ_MASK 0x010001FFU
-#define LPDDR4__DENALI_PHY_578_WRITE_MASK 0x010001FFU
+#define LPDDR4__DENALI_PHY_578_READ_MASK 0x010001FFU
+#define LPDDR4__DENALI_PHY_578_WRITE_MASK 0x010001FFU
#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2_WIDTH 8U
@@ -1009,34 +1008,34 @@
#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_578__PHY_DDL_TRACK_UPD_THRESHOLD_2
#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2_WOSET 0U
#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__REG DENALI_PHY_578
#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_2__FLD LPDDR4__DENALI_PHY_578__PHY_LP4_WDQS_OE_EXTEND_2
#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2_WOSET 0U
#define LPDDR4__SC_PHY_RX_CAL_START_2__REG DENALI_PHY_578
#define LPDDR4__SC_PHY_RX_CAL_START_2__FLD LPDDR4__DENALI_PHY_578__SC_PHY_RX_CAL_START_2
#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2_WOSET 0U
#define LPDDR4__PHY_RX_CAL_OVERRIDE_2__REG DENALI_PHY_578
#define LPDDR4__PHY_RX_CAL_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_578__PHY_RX_CAL_OVERRIDE_2
-#define LPDDR4__DENALI_PHY_579_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_579_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_579_WRITE_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2_WIDTH 8U
#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__REG DENALI_PHY_579
#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_SAMPLE_WAIT_2
@@ -1048,147 +1047,147 @@
#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__REG DENALI_PHY_579
#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2__FLD LPDDR4__DENALI_PHY_579__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_2
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ0_2__REG DENALI_PHY_579
#define LPDDR4__PHY_RX_CAL_DQ0_2__FLD LPDDR4__DENALI_PHY_579__PHY_RX_CAL_DQ0_2
-#define LPDDR4__DENALI_PHY_580_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_580_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_580_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ1_2__REG DENALI_PHY_580
#define LPDDR4__PHY_RX_CAL_DQ1_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ1_2
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ2_2__REG DENALI_PHY_580
#define LPDDR4__PHY_RX_CAL_DQ2_2__FLD LPDDR4__DENALI_PHY_580__PHY_RX_CAL_DQ2_2
-#define LPDDR4__DENALI_PHY_581_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_581_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_581_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ3_2__REG DENALI_PHY_581
#define LPDDR4__PHY_RX_CAL_DQ3_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ3_2
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ4_2__REG DENALI_PHY_581
#define LPDDR4__PHY_RX_CAL_DQ4_2__FLD LPDDR4__DENALI_PHY_581__PHY_RX_CAL_DQ4_2
-#define LPDDR4__DENALI_PHY_582_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_582_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_582_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ5_2__REG DENALI_PHY_582
#define LPDDR4__PHY_RX_CAL_DQ5_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ5_2
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ6_2__REG DENALI_PHY_582
#define LPDDR4__PHY_RX_CAL_DQ6_2__FLD LPDDR4__DENALI_PHY_582__PHY_RX_CAL_DQ6_2
-#define LPDDR4__DENALI_PHY_583_READ_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_583_WRITE_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_583_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_583_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ7_2__REG DENALI_PHY_583
#define LPDDR4__PHY_RX_CAL_DQ7_2__FLD LPDDR4__DENALI_PHY_583__PHY_RX_CAL_DQ7_2
-#define LPDDR4__DENALI_PHY_584_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_584_WRITE_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH 18U
+#define LPDDR4__DENALI_PHY_584_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2_WIDTH 18U
#define LPDDR4__PHY_RX_CAL_DM_2__REG DENALI_PHY_584
#define LPDDR4__PHY_RX_CAL_DM_2__FLD LPDDR4__DENALI_PHY_584__PHY_RX_CAL_DM_2
-#define LPDDR4__DENALI_PHY_585_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_585_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_585_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQS_2__REG DENALI_PHY_585
#define LPDDR4__PHY_RX_CAL_DQS_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_DQS_2
#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_FDBK_2__REG DENALI_PHY_585
#define LPDDR4__PHY_RX_CAL_FDBK_2__FLD LPDDR4__DENALI_PHY_585__PHY_RX_CAL_FDBK_2
-#define LPDDR4__DENALI_PHY_586_READ_MASK 0x01FF07FFU
-#define LPDDR4__DENALI_PHY_586_WRITE_MASK 0x01FF07FFU
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_WIDTH 11U
+#define LPDDR4__DENALI_PHY_586_READ_MASK 0x01FF07FFU
+#define LPDDR4__DENALI_PHY_586_WRITE_MASK 0x01FF07FFU
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2_WIDTH 11U
#define LPDDR4__PHY_RX_CAL_OBS_2__REG DENALI_PHY_586
#define LPDDR4__PHY_RX_CAL_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_OBS_2
#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_WIDTH 9U
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__REG DENALI_PHY_586
#define LPDDR4__PHY_RX_CAL_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_586__PHY_RX_CAL_LOCK_OBS_2
-#define LPDDR4__DENALI_PHY_587_READ_MASK 0x017F7F01U
-#define LPDDR4__DENALI_PHY_587_WRITE_MASK 0x017F7F01U
+#define LPDDR4__DENALI_PHY_587_READ_MASK 0x017F7F01U
+#define LPDDR4__DENALI_PHY_587_WRITE_MASK 0x017F7F01U
#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2_WOSET 0U
#define LPDDR4__PHY_RX_CAL_DISABLE_2__REG DENALI_PHY_587
#define LPDDR4__PHY_RX_CAL_DISABLE_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DISABLE_2
#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_MASK 0x00007F00U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_WIDTH 7U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2_WIDTH 7U
#define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__REG DENALI_PHY_587
#define LPDDR4__PHY_RX_CAL_SE_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_SE_ADJUST_2
#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_MASK 0x007F0000U
#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_WIDTH 7U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2_WIDTH 7U
#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__REG DENALI_PHY_587
#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_DIFF_ADJUST_2
#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2_WOSET 0U
#define LPDDR4__PHY_RX_CAL_COMP_VAL_2__REG DENALI_PHY_587
#define LPDDR4__PHY_RX_CAL_COMP_VAL_2__FLD LPDDR4__DENALI_PHY_587__PHY_RX_CAL_COMP_VAL_2
-#define LPDDR4__DENALI_PHY_588_READ_MASK 0x07FF0FFFU
-#define LPDDR4__DENALI_PHY_588_WRITE_MASK 0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_588_READ_MASK 0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_588_WRITE_MASK 0x07FF0FFFU
#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_WIDTH 12U
+#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2_WIDTH 12U
#define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__REG DENALI_PHY_588
#define LPDDR4__PHY_RX_CAL_INDEX_MASK_2__FLD LPDDR4__DENALI_PHY_588__PHY_RX_CAL_INDEX_MASK_2
#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_WIDTH 11U
+#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2_WIDTH 11U
#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__REG DENALI_PHY_588
#define LPDDR4__PHY_PAD_RX_BIAS_EN_2__FLD LPDDR4__DENALI_PHY_588__PHY_PAD_RX_BIAS_EN_2
-#define LPDDR4__DENALI_PHY_589_READ_MASK 0x03FFFF1FU
-#define LPDDR4__DENALI_PHY_589_WRITE_MASK 0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_589_READ_MASK 0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_589_WRITE_MASK 0x03FFFF1FU
#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2_WIDTH 5U
#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__REG DENALI_PHY_589
#define LPDDR4__PHY_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_589__PHY_STATIC_TOG_DISABLE_2
@@ -1205,13 +1204,13 @@
#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_CAL_TIMEOUT_2
#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_MASK 0x03000000U
-#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2_WIDTH 2U
#define LPDDR4__PHY_DATA_DC_WEIGHT_2__REG DENALI_PHY_589
#define LPDDR4__PHY_DATA_DC_WEIGHT_2__FLD LPDDR4__DENALI_PHY_589__PHY_DATA_DC_WEIGHT_2
-#define LPDDR4__DENALI_PHY_590_READ_MASK 0x01FFFF3FU
-#define LPDDR4__DENALI_PHY_590_WRITE_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_590_READ_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_590_WRITE_MASK 0x01FFFF3FU
#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_START_2_WIDTH 6U
@@ -1238,8 +1237,8 @@
#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__REG DENALI_PHY_590
#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_2__FLD LPDDR4__DENALI_PHY_590__PHY_DATA_DC_ADJUST_DIRECT_2
-#define LPDDR4__DENALI_PHY_591_READ_MASK 0x07030101U
-#define LPDDR4__DENALI_PHY_591_WRITE_MASK 0x07030101U
+#define LPDDR4__DENALI_PHY_591_READ_MASK 0x07030101U
+#define LPDDR4__DENALI_PHY_591_WRITE_MASK 0x07030101U
#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2_WIDTH 1U
@@ -1249,27 +1248,27 @@
#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_POLARITY_2
#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2_WOSET 0U
#define LPDDR4__PHY_DATA_DC_CAL_START_2__REG DENALI_PHY_591
#define LPDDR4__PHY_DATA_DC_CAL_START_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_CAL_START_2
#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2_WIDTH 2U
#define LPDDR4__PHY_DATA_DC_SW_RANK_2__REG DENALI_PHY_591
#define LPDDR4__PHY_DATA_DC_SW_RANK_2__FLD LPDDR4__DENALI_PHY_591__PHY_DATA_DC_SW_RANK_2
#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_WIDTH 3U
+#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2_WIDTH 3U
#define LPDDR4__PHY_FDBK_PWR_CTRL_2__REG DENALI_PHY_591
#define LPDDR4__PHY_FDBK_PWR_CTRL_2__FLD LPDDR4__DENALI_PHY_591__PHY_FDBK_PWR_CTRL_2
-#define LPDDR4__DENALI_PHY_592_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PHY_592_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_592_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_592_WRITE_MASK 0x01010101U
#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_592__PHY_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH 1U
@@ -1302,22 +1301,22 @@
#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__REG DENALI_PHY_592
#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_592__PHY_SLICE_PWR_RDC_DISABLE_2
-#define LPDDR4__DENALI_PHY_593_READ_MASK 0x3FFF07FFU
-#define LPDDR4__DENALI_PHY_593_WRITE_MASK 0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_593_READ_MASK 0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_593_WRITE_MASK 0x3FFF07FFU
#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2_WIDTH 11U
#define LPDDR4__PHY_PARITY_ERROR_REGIF_2__REG DENALI_PHY_593
#define LPDDR4__PHY_PARITY_ERROR_REGIF_2__FLD LPDDR4__DENALI_PHY_593__PHY_PARITY_ERROR_REGIF_2
#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_MASK 0x3FFF0000U
-#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_WIDTH 14U
+#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2_WIDTH 14U
#define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__REG DENALI_PHY_593
#define LPDDR4__PHY_DS_FSM_ERROR_INFO_2__FLD LPDDR4__DENALI_PHY_593__PHY_DS_FSM_ERROR_INFO_2
-#define LPDDR4__DENALI_PHY_594_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_594_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_594_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_594_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_594__PHY_DS_FSM_ERROR_INFO_MASK_2_WIDTH 14U
@@ -1330,8 +1329,8 @@
#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__REG DENALI_PHY_594
#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_594__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_2
-#define LPDDR4__DENALI_PHY_595_READ_MASK 0x00001F1FU
-#define LPDDR4__DENALI_PHY_595_WRITE_MASK 0x00001F1FU
+#define LPDDR4__DENALI_PHY_595_READ_MASK 0x00001F1FU
+#define LPDDR4__DENALI_PHY_595_WRITE_MASK 0x00001F1FU
#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_595__PHY_DS_TRAIN_CALIB_ERROR_INFO_2_WIDTH 5U
@@ -1350,37 +1349,37 @@
#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__REG DENALI_PHY_595
#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2__FLD LPDDR4__DENALI_PHY_595__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_2
-#define LPDDR4__DENALI_PHY_596_READ_MASK 0x07FFFF07U
-#define LPDDR4__DENALI_PHY_596_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_596_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_596_WRITE_MASK 0x07FFFF07U
#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_WIDTH 3U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2_WIDTH 3U
#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__REG DENALI_PHY_596
#define LPDDR4__PHY_DQ_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_ENABLE_2
#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_WIDTH 16U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2_WIDTH 16U
#define LPDDR4__PHY_DQ_TSEL_SELECT_2__REG DENALI_PHY_596
#define LPDDR4__PHY_DQ_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQ_TSEL_SELECT_2
#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_WIDTH 3U
+#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2_WIDTH 3U
#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__REG DENALI_PHY_596
#define LPDDR4__PHY_DQS_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_596__PHY_DQS_TSEL_ENABLE_2
-#define LPDDR4__DENALI_PHY_597_READ_MASK 0x7F03FFFFU
-#define LPDDR4__DENALI_PHY_597_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_597_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_597_WRITE_MASK 0x7F03FFFFU
#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_WIDTH 16U
+#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2_WIDTH 16U
#define LPDDR4__PHY_DQS_TSEL_SELECT_2__REG DENALI_PHY_597
#define LPDDR4__PHY_DQS_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_597__PHY_DQS_TSEL_SELECT_2
#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2_WIDTH 2U
#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__REG DENALI_PHY_597
#define LPDDR4__PHY_TWO_CYC_PREAMBLE_2__FLD LPDDR4__DENALI_PHY_597__PHY_TWO_CYC_PREAMBLE_2
@@ -1390,8 +1389,8 @@
#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__REG DENALI_PHY_597
#define LPDDR4__PHY_VREF_INITIAL_START_POINT_2__FLD LPDDR4__DENALI_PHY_597__PHY_VREF_INITIAL_START_POINT_2
-#define LPDDR4__DENALI_PHY_598_READ_MASK 0xFF01037FU
-#define LPDDR4__DENALI_PHY_598_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_598_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_598_WRITE_MASK 0xFF01037FU
#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2_WIDTH 7U
@@ -1399,50 +1398,50 @@
#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_INITIAL_STOP_POINT_2
#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2_WIDTH 2U
#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__REG DENALI_PHY_598
#define LPDDR4__PHY_VREF_TRAINING_CTRL_2__FLD LPDDR4__DENALI_PHY_598__PHY_VREF_TRAINING_CTRL_2
#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2_WOSET 0U
#define LPDDR4__PHY_NTP_TRAIN_EN_2__REG DENALI_PHY_598
#define LPDDR4__PHY_NTP_TRAIN_EN_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_TRAIN_EN_2
#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2_WIDTH 8U
#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__REG DENALI_PHY_598
#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_2__FLD LPDDR4__DENALI_PHY_598__PHY_NTP_WDQ_STEP_SIZE_2
-#define LPDDR4__DENALI_PHY_599_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_599_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_599_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_599_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_WIDTH 11U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2_WIDTH 11U
#define LPDDR4__PHY_NTP_WDQ_START_2__REG DENALI_PHY_599
#define LPDDR4__PHY_NTP_WDQ_START_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_START_2
#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_WIDTH 11U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2_WIDTH 11U
#define LPDDR4__PHY_NTP_WDQ_STOP_2__REG DENALI_PHY_599
#define LPDDR4__PHY_NTP_WDQ_STOP_2__FLD LPDDR4__DENALI_PHY_599__PHY_NTP_WDQ_STOP_2
-#define LPDDR4__DENALI_PHY_600_READ_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_PHY_600_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_600_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_600_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2_WIDTH 8U
#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__REG DENALI_PHY_600
#define LPDDR4__PHY_NTP_WDQ_BIT_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_NTP_WDQ_BIT_EN_2
#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_MASK 0x0003FF00U
-#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2_WIDTH 10U
#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__REG DENALI_PHY_600
#define LPDDR4__PHY_WDQLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_600__PHY_WDQLVL_DVW_MIN_2
@@ -1454,8 +1453,8 @@
#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__REG DENALI_PHY_600
#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_600__PHY_SW_WDQLVL_DVW_MIN_EN_2
-#define LPDDR4__DENALI_PHY_601_READ_MASK 0x1F1F0F3FU
-#define LPDDR4__DENALI_PHY_601_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_601_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_601_WRITE_MASK 0x1F1F0F3FU
#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2_WIDTH 6U
@@ -1463,156 +1462,156 @@
#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_601__PHY_WDQLVL_PER_START_OFFSET_2
#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_WIDTH 4U
+#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2_WIDTH 4U
#define LPDDR4__PHY_FAST_LVL_EN_2__REG DENALI_PHY_601
#define LPDDR4__PHY_FAST_LVL_EN_2__FLD LPDDR4__DENALI_PHY_601__PHY_FAST_LVL_EN_2
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2_WIDTH 5U
#define LPDDR4__PHY_PAD_TX_DCD_2__REG DENALI_PHY_601
#define LPDDR4__PHY_PAD_TX_DCD_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_TX_DCD_2
#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_0_2__REG DENALI_PHY_601
#define LPDDR4__PHY_PAD_RX_DCD_0_2__FLD LPDDR4__DENALI_PHY_601__PHY_PAD_RX_DCD_0_2
-#define LPDDR4__DENALI_PHY_602_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_602_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_602_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_602_WRITE_MASK 0x1F1F1F1FU
#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_1_2__REG DENALI_PHY_602
#define LPDDR4__PHY_PAD_RX_DCD_1_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_1_2
#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_2_2__REG DENALI_PHY_602
#define LPDDR4__PHY_PAD_RX_DCD_2_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_2_2
#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_3_2__REG DENALI_PHY_602
#define LPDDR4__PHY_PAD_RX_DCD_3_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_3_2
#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_4_2__REG DENALI_PHY_602
#define LPDDR4__PHY_PAD_RX_DCD_4_2__FLD LPDDR4__DENALI_PHY_602__PHY_PAD_RX_DCD_4_2
-#define LPDDR4__DENALI_PHY_603_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_603_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_603_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_603_WRITE_MASK 0x1F1F1F1FU
#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_5_2__REG DENALI_PHY_603
#define LPDDR4__PHY_PAD_RX_DCD_5_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_5_2
#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_6_2__REG DENALI_PHY_603
#define LPDDR4__PHY_PAD_RX_DCD_6_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_6_2
#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_7_2__REG DENALI_PHY_603
#define LPDDR4__PHY_PAD_RX_DCD_7_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_RX_DCD_7_2
#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2_WIDTH 5U
#define LPDDR4__PHY_PAD_DM_RX_DCD_2__REG DENALI_PHY_603
#define LPDDR4__PHY_PAD_DM_RX_DCD_2__FLD LPDDR4__DENALI_PHY_603__PHY_PAD_DM_RX_DCD_2
-#define LPDDR4__DENALI_PHY_604_READ_MASK 0x003F1F1FU
-#define LPDDR4__DENALI_PHY_604_WRITE_MASK 0x003F1F1FU
+#define LPDDR4__DENALI_PHY_604_READ_MASK 0x003F1F1FU
+#define LPDDR4__DENALI_PHY_604_WRITE_MASK 0x003F1F1FU
#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2_WIDTH 5U
#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__REG DENALI_PHY_604
#define LPDDR4__PHY_PAD_DQS_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DQS_RX_DCD_2
#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2_WIDTH 5U
#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__REG DENALI_PHY_604
#define LPDDR4__PHY_PAD_FDBK_RX_DCD_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_FDBK_RX_DCD_2
#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2_WIDTH 6U
#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__REG DENALI_PHY_604
#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_2__FLD LPDDR4__DENALI_PHY_604__PHY_PAD_DSLICE_IO_CFG_2
-#define LPDDR4__DENALI_PHY_605_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_605_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_605_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_605_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__REG DENALI_PHY_605
#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ0_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__REG DENALI_PHY_605
#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_605__PHY_RDDQ1_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_606_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_606_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_606_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_606_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__REG DENALI_PHY_606
#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ2_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__REG DENALI_PHY_606
#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_606__PHY_RDDQ3_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_607_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_607_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_607_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_607_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__REG DENALI_PHY_607
#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ4_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__REG DENALI_PHY_607
#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_607__PHY_RDDQ5_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_608_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_608_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_608_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_608_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__REG DENALI_PHY_608
#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ6_SLAVE_DELAY_2
#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__REG DENALI_PHY_608
#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_608__PHY_RDDQ7_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_609_READ_MASK 0x000703FFU
-#define LPDDR4__DENALI_PHY_609_WRITE_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_609_READ_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_609_WRITE_MASK 0x000703FFU
#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2_WIDTH 10U
#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__REG DENALI_PHY_609
#define LPDDR4__PHY_RDDM_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_609__PHY_RDDM_SLAVE_DELAY_2
@@ -1622,34 +1621,34 @@
#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__REG DENALI_PHY_609
#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_609__PHY_DATA_DC_CAL_CLK_SEL_2
-#define LPDDR4__DENALI_PHY_610_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_610_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_610_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_610_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2_WIDTH 8U
#define LPDDR4__PHY_DQ_OE_TIMING_2__REG DENALI_PHY_610
#define LPDDR4__PHY_DQ_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_OE_TIMING_2
#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2_WIDTH 8U
#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__REG DENALI_PHY_610
#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_RD_TIMING_2
#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2_WIDTH 8U
#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__REG DENALI_PHY_610
#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQ_TSEL_WR_TIMING_2
#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2_WIDTH 8U
#define LPDDR4__PHY_DQS_OE_TIMING_2__REG DENALI_PHY_610
#define LPDDR4__PHY_DQS_OE_TIMING_2__FLD LPDDR4__DENALI_PHY_610__PHY_DQS_OE_TIMING_2
-#define LPDDR4__DENALI_PHY_611_READ_MASK 0xFFFFFF0FU
-#define LPDDR4__DENALI_PHY_611_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_611_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_611_WRITE_MASK 0xFFFFFF0FU
#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2_WIDTH 4U
@@ -1657,118 +1656,118 @@
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_IO_PAD_DELAY_TIMING_2
#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2_WIDTH 8U
#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__REG DENALI_PHY_611
#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_RD_TIMING_2
#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2_WIDTH 8U
#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__REG DENALI_PHY_611
#define LPDDR4__PHY_DQS_OE_RD_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_OE_RD_TIMING_2
#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2_WIDTH 8U
#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__REG DENALI_PHY_611
#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_2__FLD LPDDR4__DENALI_PHY_611__PHY_DQS_TSEL_WR_TIMING_2
-#define LPDDR4__DENALI_PHY_612_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_612_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_612_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_612_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_WIDTH 16U
+#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2_WIDTH 16U
#define LPDDR4__PHY_VREF_SETTING_TIME_2__REG DENALI_PHY_612
#define LPDDR4__PHY_VREF_SETTING_TIME_2__FLD LPDDR4__DENALI_PHY_612__PHY_VREF_SETTING_TIME_2
#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_WIDTH 12U
+#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2_WIDTH 12U
#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__REG DENALI_PHY_612
#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_2__FLD LPDDR4__DENALI_PHY_612__PHY_PAD_VREF_CTRL_DQ_2
-#define LPDDR4__DENALI_PHY_613_READ_MASK 0x03FFFF01U
-#define LPDDR4__DENALI_PHY_613_WRITE_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_613_READ_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_613_WRITE_MASK 0x03FFFF01U
#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2_WOSET 0U
#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__REG DENALI_PHY_613
#define LPDDR4__PHY_PER_CS_TRAINING_EN_2__FLD LPDDR4__DENALI_PHY_613__PHY_PER_CS_TRAINING_EN_2
#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2_WIDTH 8U
#define LPDDR4__PHY_DQ_IE_TIMING_2__REG DENALI_PHY_613
#define LPDDR4__PHY_DQ_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQ_IE_TIMING_2
#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2_WIDTH 8U
#define LPDDR4__PHY_DQS_IE_TIMING_2__REG DENALI_PHY_613
#define LPDDR4__PHY_DQS_IE_TIMING_2__FLD LPDDR4__DENALI_PHY_613__PHY_DQS_IE_TIMING_2
#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_MASK 0x03000000U
-#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2_WIDTH 2U
#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__REG DENALI_PHY_613
#define LPDDR4__PHY_RDDATA_EN_IE_DLY_2__FLD LPDDR4__DENALI_PHY_613__PHY_RDDATA_EN_IE_DLY_2
-#define LPDDR4__DENALI_PHY_614_READ_MASK 0x1F1F0103U
-#define LPDDR4__DENALI_PHY_614_WRITE_MASK 0x1F1F0103U
-#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_614_READ_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_614_WRITE_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2_WIDTH 2U
#define LPDDR4__PHY_IE_MODE_2__REG DENALI_PHY_614
#define LPDDR4__PHY_IE_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_IE_MODE_2
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2_WOSET 0U
#define LPDDR4__PHY_DBI_MODE_2__REG DENALI_PHY_614
#define LPDDR4__PHY_DBI_MODE_2__FLD LPDDR4__DENALI_PHY_614__PHY_DBI_MODE_2
#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__REG DENALI_PHY_614
#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_TSEL_DLY_2
#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__REG DENALI_PHY_614
#define LPDDR4__PHY_RDDATA_EN_OE_DLY_2__FLD LPDDR4__DENALI_PHY_614__PHY_RDDATA_EN_OE_DLY_2
-#define LPDDR4__DENALI_PHY_615_READ_MASK 0x3F07FF0FU
-#define LPDDR4__DENALI_PHY_615_WRITE_MASK 0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_615_READ_MASK 0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_615_WRITE_MASK 0x3F07FF0FU
#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_WIDTH 4U
+#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2_WIDTH 4U
#define LPDDR4__PHY_SW_MASTER_MODE_2__REG DENALI_PHY_615
#define LPDDR4__PHY_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_615__PHY_SW_MASTER_MODE_2
#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_MASK 0x0007FF00U
-#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_SHIFT 8U
#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2_WIDTH 11U
#define LPDDR4__PHY_MASTER_DELAY_START_2__REG DENALI_PHY_615
#define LPDDR4__PHY_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_START_2
#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_WIDTH 6U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2_WIDTH 6U
#define LPDDR4__PHY_MASTER_DELAY_STEP_2__REG DENALI_PHY_615
#define LPDDR4__PHY_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_615__PHY_MASTER_DELAY_STEP_2
-#define LPDDR4__DENALI_PHY_616_READ_MASK 0xFF0FFFFFU
-#define LPDDR4__DENALI_PHY_616_WRITE_MASK 0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_616_READ_MASK 0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_616_WRITE_MASK 0xFF0FFFFFU
#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2_WIDTH 8U
#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__REG DENALI_PHY_616
#define LPDDR4__PHY_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_WAIT_2
@@ -1779,19 +1778,19 @@
#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_616__PHY_MASTER_DELAY_HALF_MEASURE_2
#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_WIDTH 4U
+#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2_WIDTH 4U
#define LPDDR4__PHY_RPTR_UPDATE_2__REG DENALI_PHY_616
#define LPDDR4__PHY_RPTR_UPDATE_2__FLD LPDDR4__DENALI_PHY_616__PHY_RPTR_UPDATE_2
#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2_WIDTH 8U
#define LPDDR4__PHY_WRLVL_DLY_STEP_2__REG DENALI_PHY_616
#define LPDDR4__PHY_WRLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_616__PHY_WRLVL_DLY_STEP_2
-#define LPDDR4__DENALI_PHY_617_READ_MASK 0x1F0F3F0FU
-#define LPDDR4__DENALI_PHY_617_WRITE_MASK 0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_617_READ_MASK 0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_617_WRITE_MASK 0x1F0F3F0FU
#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_617__PHY_WRLVL_DLY_FINE_STEP_2_WIDTH 4U
@@ -1805,8 +1804,8 @@
#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_WRLVL_RESP_WAIT_CNT_2
#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_WIDTH 4U
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2_WIDTH 4U
#define LPDDR4__PHY_GTLVL_DLY_STEP_2__REG DENALI_PHY_617
#define LPDDR4__PHY_GTLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_DLY_STEP_2
@@ -1816,25 +1815,25 @@
#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__REG DENALI_PHY_617
#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_617__PHY_GTLVL_RESP_WAIT_CNT_2
-#define LPDDR4__DENALI_PHY_618_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_618_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_618_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_618_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2_WIDTH 10U
#define LPDDR4__PHY_GTLVL_BACK_STEP_2__REG DENALI_PHY_618
#define LPDDR4__PHY_GTLVL_BACK_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_BACK_STEP_2
#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2_WIDTH 10U
#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__REG DENALI_PHY_618
#define LPDDR4__PHY_GTLVL_FINAL_STEP_2__FLD LPDDR4__DENALI_PHY_618__PHY_GTLVL_FINAL_STEP_2
-#define LPDDR4__DENALI_PHY_619_READ_MASK 0x0F010FFFU
-#define LPDDR4__DENALI_PHY_619_WRITE_MASK 0x0F010FFFU
+#define LPDDR4__DENALI_PHY_619_READ_MASK 0x0F010FFFU
+#define LPDDR4__DENALI_PHY_619_WRITE_MASK 0x0F010FFFU
#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_WIDTH 8U
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2_WIDTH 8U
#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__REG DENALI_PHY_619
#define LPDDR4__PHY_WDQLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_WDQLVL_DLY_STEP_2
@@ -1846,31 +1845,31 @@
#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2_WOSET 0U
#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__REG DENALI_PHY_619
#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_2__FLD LPDDR4__DENALI_PHY_619__PHY_TOGGLE_PRE_SUPPORT_2
#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_MASK 0x0F000000U
-#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_WIDTH 4U
+#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2_WIDTH 4U
#define LPDDR4__PHY_RDLVL_DLY_STEP_2__REG DENALI_PHY_619
#define LPDDR4__PHY_RDLVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_619__PHY_RDLVL_DLY_STEP_2
-#define LPDDR4__DENALI_PHY_620_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_620_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_620_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_620_WRITE_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2_WIDTH 10U
#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__REG DENALI_PHY_620
#define LPDDR4__PHY_RDLVL_MAX_EDGE_2__FLD LPDDR4__DENALI_PHY_620__PHY_RDLVL_MAX_EDGE_2
-#define LPDDR4__DENALI_PHY_621_READ_MASK 0x3F0103FFU
-#define LPDDR4__DENALI_PHY_621_WRITE_MASK 0x3F0103FFU
+#define LPDDR4__DENALI_PHY_621_READ_MASK 0x3F0103FFU
+#define LPDDR4__DENALI_PHY_621_WRITE_MASK 0x3F0103FFU
#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_WIDTH 10U
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2_WIDTH 10U
#define LPDDR4__PHY_RDLVL_DVW_MIN_2__REG DENALI_PHY_621
#define LPDDR4__PHY_RDLVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_DVW_MIN_2
@@ -1888,8 +1887,8 @@
#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__REG DENALI_PHY_621
#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_621__PHY_RDLVL_PER_START_OFFSET_2
-#define LPDDR4__DENALI_PHY_622_READ_MASK 0x00030703U
-#define LPDDR4__DENALI_PHY_622_WRITE_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_622_READ_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_622_WRITE_MASK 0x00030703U
#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2_WIDTH 2U
@@ -1897,8 +1896,8 @@
#define LPDDR4__PHY_WRPATH_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_DISABLE_2
#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_MASK 0x00000700U
-#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_WIDTH 3U
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2_WIDTH 3U
#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__REG DENALI_PHY_622
#define LPDDR4__PHY_WRPATH_GATE_TIMING_2__FLD LPDDR4__DENALI_PHY_622__PHY_WRPATH_GATE_TIMING_2
@@ -1908,8 +1907,8 @@
#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__REG DENALI_PHY_622
#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_2__FLD LPDDR4__DENALI_PHY_622__PHY_DATA_DC_INIT_DISABLE_2
-#define LPDDR4__DENALI_PHY_623_READ_MASK 0x07FF03FFU
-#define LPDDR4__DENALI_PHY_623_WRITE_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_623_READ_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_623_WRITE_MASK 0x07FF03FFU
#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQS_INIT_SLV_DELAY_2_WIDTH 10U
@@ -1922,8 +1921,8 @@
#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__REG DENALI_PHY_623
#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_623__PHY_DATA_DC_DQ_INIT_SLV_DELAY_2
-#define LPDDR4__DENALI_PHY_624_READ_MASK 0xFFFF0101U
-#define LPDDR4__DENALI_PHY_624_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_624_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_624_WRITE_MASK 0xFFFF0101U
#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_624__PHY_DATA_DC_WRLVL_ENABLE_2_WIDTH 1U
@@ -1952,11 +1951,11 @@
#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__REG DENALI_PHY_624
#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2__FLD LPDDR4__DENALI_PHY_624__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2
-#define LPDDR4__DENALI_PHY_625_READ_MASK 0x001F3F7FU
-#define LPDDR4__DENALI_PHY_625_WRITE_MASK 0x001F3F7FU
+#define LPDDR4__DENALI_PHY_625_READ_MASK 0x001F3F7FU
+#define LPDDR4__DENALI_PHY_625_WRITE_MASK 0x001F3F7FU
#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_WIDTH 7U
+#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2_WIDTH 7U
#define LPDDR4__PHY_WDQ_OSC_DELTA_2__REG DENALI_PHY_625
#define LPDDR4__PHY_WDQ_OSC_DELTA_2__FLD LPDDR4__DENALI_PHY_625__PHY_WDQ_OSC_DELTA_2
@@ -1967,29 +1966,29 @@
#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_625__PHY_MEAS_DLY_STEP_ENABLE_2
#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_WIDTH 5U
+#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_DLY_2__REG DENALI_PHY_625
#define LPDDR4__PHY_RDDATA_EN_DLY_2__FLD LPDDR4__DENALI_PHY_625__PHY_RDDATA_EN_DLY_2
-#define LPDDR4__DENALI_PHY_626_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_626_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_626_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_626_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2_WIDTH 32U
#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__REG DENALI_PHY_626
#define LPDDR4__PHY_DQ_DM_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_626__PHY_DQ_DM_SWIZZLE0_2
-#define LPDDR4__DENALI_PHY_627_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_627_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_627_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_627_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_WIDTH 4U
+#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2_WIDTH 4U
#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__REG DENALI_PHY_627
#define LPDDR4__PHY_DQ_DM_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_627__PHY_DQ_DM_SWIZZLE1_2
-#define LPDDR4__DENALI_PHY_628_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_628_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_628_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ0_SLAVE_DELAY_2_WIDTH 11U
@@ -2002,8 +2001,8 @@
#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__REG DENALI_PHY_628
#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_628__PHY_CLK_WRDQ1_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_629_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_629_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_629_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_629_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ2_SLAVE_DELAY_2_WIDTH 11U
@@ -2016,8 +2015,8 @@
#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__REG DENALI_PHY_629
#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_629__PHY_CLK_WRDQ3_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_630_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_630_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_630_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_630_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ4_SLAVE_DELAY_2_WIDTH 11U
@@ -2030,8 +2029,8 @@
#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__REG DENALI_PHY_630
#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_630__PHY_CLK_WRDQ5_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_631_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_631_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_631_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_631_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ6_SLAVE_DELAY_2_WIDTH 11U
@@ -2044,8 +2043,8 @@
#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__REG DENALI_PHY_631
#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_631__PHY_CLK_WRDQ7_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_632_READ_MASK 0x03FF07FFU
-#define LPDDR4__DENALI_PHY_632_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_632_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_632_WRITE_MASK 0x03FF07FFU
#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_632__PHY_CLK_WRDM_SLAVE_DELAY_2_WIDTH 11U
@@ -2058,8 +2057,8 @@
#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__REG DENALI_PHY_632
#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_632__PHY_CLK_WRDQS_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_633_READ_MASK 0x0003FF03U
-#define LPDDR4__DENALI_PHY_633_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_633_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_633_WRITE_MASK 0x0003FF03U
#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_633__PHY_WRLVL_THRESHOLD_ADJUST_2_WIDTH 2U
@@ -2072,8 +2071,8 @@
#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__REG DENALI_PHY_633
#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_633__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_634_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_634_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_634_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2_WIDTH 10U
@@ -2086,8 +2085,8 @@
#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__REG DENALI_PHY_634
#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_634__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_635_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_635_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_635_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2_WIDTH 10U
@@ -2100,8 +2099,8 @@
#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__REG DENALI_PHY_635
#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_635__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_636_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_636_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_636_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2_WIDTH 10U
@@ -2114,8 +2113,8 @@
#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__REG DENALI_PHY_636
#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_636__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_637_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_637_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_637_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2_WIDTH 10U
@@ -2128,8 +2127,8 @@
#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__REG DENALI_PHY_637
#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_637__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_638_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_638_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_638_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2_WIDTH 10U
@@ -2142,8 +2141,8 @@
#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__REG DENALI_PHY_638
#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_638__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_639_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_639_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_639_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2_WIDTH 10U
@@ -2156,8 +2155,8 @@
#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__REG DENALI_PHY_639
#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_639__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_640_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_640_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_640_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_640_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2_WIDTH 10U
@@ -2170,8 +2169,8 @@
#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__REG DENALI_PHY_640
#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_640__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_641_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_641_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_641_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_641_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_641__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2_WIDTH 10U
@@ -2184,8 +2183,8 @@
#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__REG DENALI_PHY_641
#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_641__PHY_RDDQS_DM_RISE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_642_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_642_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_642_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_642_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_642__PHY_RDDQS_DM_FALL_SLAVE_DELAY_2_WIDTH 10U
@@ -2198,8 +2197,8 @@
#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__REG DENALI_PHY_642
#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_642__PHY_RDDQS_GATE_SLAVE_DELAY_2
-#define LPDDR4__DENALI_PHY_643_READ_MASK 0x03FF070FU
-#define LPDDR4__DENALI_PHY_643_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_643_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_643_WRITE_MASK 0x03FF070FU
#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2_WIDTH 4U
@@ -2207,8 +2206,8 @@
#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_2__FLD LPDDR4__DENALI_PHY_643__PHY_RDDQS_LATENCY_ADJUST_2
#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_MASK 0x00000700U
-#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_WIDTH 3U
+#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2_WIDTH 3U
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__REG DENALI_PHY_643
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRITE_PATH_LAT_ADD_2
@@ -2218,8 +2217,8 @@
#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__REG DENALI_PHY_643
#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2__FLD LPDDR4__DENALI_PHY_643__PHY_WRLVL_DELAY_EARLY_THRESHOLD_2
-#define LPDDR4__DENALI_PHY_644_READ_MASK 0x000103FFU
-#define LPDDR4__DENALI_PHY_644_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_644_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_644_WRITE_MASK 0x000103FFU
#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_644__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2_WIDTH 10U
@@ -2234,8 +2233,8 @@
#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__REG DENALI_PHY_644
#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_2__FLD LPDDR4__DENALI_PHY_644__PHY_WRLVL_EARLY_FORCE_ZERO_2
-#define LPDDR4__DENALI_PHY_645_READ_MASK 0x000F03FFU
-#define LPDDR4__DENALI_PHY_645_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_645_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_645_WRITE_MASK 0x000F03FFU
#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_645__PHY_GTLVL_RDDQS_SLV_DLY_START_2_WIDTH 10U
@@ -2248,8 +2247,8 @@
#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__REG DENALI_PHY_645
#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_2__FLD LPDDR4__DENALI_PHY_645__PHY_GTLVL_LAT_ADJ_START_2
-#define LPDDR4__DENALI_PHY_646_READ_MASK 0x010F07FFU
-#define LPDDR4__DENALI_PHY_646_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_646_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_646_WRITE_MASK 0x010F07FFU
#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2_WIDTH 11U
@@ -2257,29 +2256,29 @@
#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_WDQLVL_DQDM_SLV_DLY_START_2
#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_WIDTH 4U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2_WIDTH 4U
#define LPDDR4__PHY_NTP_WRLAT_START_2__REG DENALI_PHY_646
#define LPDDR4__PHY_NTP_WRLAT_START_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_WRLAT_START_2
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_SHIFT 24U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WIDTH 1U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOCLR 0U
-#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOSET 0U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_SHIFT 24U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WIDTH 1U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOCLR 0U
+#define LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2_WOSET 0U
#define LPDDR4__PHY_NTP_PASS_2__REG DENALI_PHY_646
#define LPDDR4__PHY_NTP_PASS_2__FLD LPDDR4__DENALI_PHY_646__PHY_NTP_PASS_2
-#define LPDDR4__DENALI_PHY_647_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_647_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_647_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_647_WRITE_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2_WIDTH 10U
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__REG DENALI_PHY_647
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2__FLD LPDDR4__DENALI_PHY_647__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2
-#define LPDDR4__DENALI_PHY_648_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_648_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_648_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_648_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQS_CLK_ADJUST_2_WIDTH 8U
@@ -2304,8 +2303,8 @@
#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__REG DENALI_PHY_648
#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_648__PHY_DATA_DC_DQ2_CLK_ADJUST_2
-#define LPDDR4__DENALI_PHY_649_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_649_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_649_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_649_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ3_CLK_ADJUST_2_WIDTH 8U
@@ -2330,8 +2329,8 @@
#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__REG DENALI_PHY_649
#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_2__FLD LPDDR4__DENALI_PHY_649__PHY_DATA_DC_DQ6_CLK_ADJUST_2
-#define LPDDR4__DENALI_PHY_650_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_650_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_650_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_650_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_650__PHY_DATA_DC_DQ7_CLK_ADJUST_2_WIDTH 8U
@@ -2350,23 +2349,23 @@
#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__REG DENALI_PHY_650
#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_2__FLD LPDDR4__DENALI_PHY_650__PHY_DSLICE_PAD_BOOSTPN_SETTING_2
-#define LPDDR4__DENALI_PHY_651_READ_MASK 0x0003033FU
-#define LPDDR4__DENALI_PHY_651_WRITE_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_651_READ_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_651_WRITE_MASK 0x0003033FU
#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_SHIFT 0U
#define LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2_WIDTH 6U
#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__REG DENALI_PHY_651
#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_2__FLD LPDDR4__DENALI_PHY_651__PHY_DSLICE_PAD_RX_CTLE_SETTING_2
-#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_SHIFT 8U
-#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_SHIFT 8U
+#define LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2_WIDTH 2U
#define LPDDR4__PHY_DQ_FFE_2__REG DENALI_PHY_651
#define LPDDR4__PHY_DQ_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQ_FFE_2
-#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_SHIFT 16U
-#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_WIDTH 2U
+#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2_WIDTH 2U
#define LPDDR4__PHY_DQS_FFE_2__REG DENALI_PHY_651
#define LPDDR4__PHY_DQS_FFE_2__FLD LPDDR4__DENALI_PHY_651__PHY_DQS_FFE_2
diff --git a/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
similarity index 66%
rename from drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h
rename to drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
index bfde51d..73e5f71 100644
--- a/drivers/ram/k3-j721e/lpddr4_data_slice_3_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
@@ -1,17 +1,16 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
*
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
#define REG_LPDDR4_DATA_SLICE_3_MACROS_H_
-#define LPDDR4__DENALI_PHY_768_READ_MASK 0x000F07FFU
-#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_768_READ_MASK 0x000F07FFU
+#define LPDDR4__DENALI_PHY_768_WRITE_MASK 0x000F07FFU
#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_768__PHY_CLK_WR_BYPASS_SLAVE_DELAY_3_WIDTH 11U
@@ -24,8 +23,8 @@
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__REG DENALI_PHY_768
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_3__FLD LPDDR4__DENALI_PHY_768__PHY_IO_PAD_DELAY_TIMING_BYPASS_3
-#define LPDDR4__DENALI_PHY_769_READ_MASK 0x000703FFU
-#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_769_READ_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_769_WRITE_MASK 0x000703FFU
#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_769__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3_WIDTH 10U
@@ -38,8 +37,8 @@
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__REG DENALI_PHY_769
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_3__FLD LPDDR4__DENALI_PHY_769__PHY_WRITE_PATH_LAT_ADD_BYPASS_3
-#define LPDDR4__DENALI_PHY_770_READ_MASK 0x010303FFU
-#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_770_READ_MASK 0x010303FFU
+#define LPDDR4__DENALI_PHY_770_WRITE_MASK 0x010303FFU
#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_770__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3_WIDTH 10U
@@ -60,75 +59,75 @@
#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__REG DENALI_PHY_770
#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_770__PHY_CLK_BYPASS_OVERRIDE_3
-#define LPDDR4__DENALI_PHY_771_READ_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_771_WRITE_MASK 0x3F3F3F3FU
#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__REG DENALI_PHY_771
#define LPDDR4__PHY_SW_WRDQ0_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ0_SHIFT_3
#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__REG DENALI_PHY_771
#define LPDDR4__PHY_SW_WRDQ1_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ1_SHIFT_3
#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__REG DENALI_PHY_771
#define LPDDR4__PHY_SW_WRDQ2_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ2_SHIFT_3
#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__REG DENALI_PHY_771
#define LPDDR4__PHY_SW_WRDQ3_SHIFT_3__FLD LPDDR4__DENALI_PHY_771__PHY_SW_WRDQ3_SHIFT_3
-#define LPDDR4__DENALI_PHY_772_READ_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_772_WRITE_MASK 0x3F3F3F3FU
#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__REG DENALI_PHY_772
#define LPDDR4__PHY_SW_WRDQ4_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ4_SHIFT_3
#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__REG DENALI_PHY_772
#define LPDDR4__PHY_SW_WRDQ5_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ5_SHIFT_3
#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__REG DENALI_PHY_772
#define LPDDR4__PHY_SW_WRDQ6_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ6_SHIFT_3
#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3_WIDTH 6U
#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__REG DENALI_PHY_772
#define LPDDR4__PHY_SW_WRDQ7_SHIFT_3__FLD LPDDR4__DENALI_PHY_772__PHY_SW_WRDQ7_SHIFT_3
-#define LPDDR4__DENALI_PHY_773_READ_MASK 0x01030F3FU
-#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_773_READ_MASK 0x01030F3FU
+#define LPDDR4__DENALI_PHY_773_WRITE_MASK 0x01030F3FU
#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3_WIDTH 6U
#define LPDDR4__PHY_SW_WRDM_SHIFT_3__REG DENALI_PHY_773
#define LPDDR4__PHY_SW_WRDM_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDM_SHIFT_3
#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH 4U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3_WIDTH 4U
#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__REG DENALI_PHY_773
#define LPDDR4__PHY_SW_WRDQS_SHIFT_3__FLD LPDDR4__DENALI_PHY_773__PHY_SW_WRDQS_SHIFT_3
#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3_WIDTH 2U
#define LPDDR4__PHY_PER_RANK_CS_MAP_3__REG DENALI_PHY_773
#define LPDDR4__PHY_PER_RANK_CS_MAP_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_RANK_CS_MAP_3
@@ -140,8 +139,8 @@
#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__REG DENALI_PHY_773
#define LPDDR4__PHY_PER_CS_TRAINING_MULTICAST_EN_3__FLD LPDDR4__DENALI_PHY_773__PHY_PER_CS_TRAINING_MULTICAST_EN_3
-#define LPDDR4__DENALI_PHY_774_READ_MASK 0x1F1F0301U
-#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774_READ_MASK 0x1F1F0301U
+#define LPDDR4__DENALI_PHY_774_WRITE_MASK 0x1F1F0301U
#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_774__PHY_PER_CS_TRAINING_INDEX_3_WIDTH 1U
@@ -168,8 +167,8 @@
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_774
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_774__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3
-#define LPDDR4__DENALI_PHY_775_READ_MASK 0x1F030F0FU
-#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775_READ_MASK 0x1F030F0FU
+#define LPDDR4__DENALI_PHY_775_WRITE_MASK 0x1F030F0FU
#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RPTR_UPDATE_3_WIDTH 4U
@@ -194,17 +193,17 @@
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_775
#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_775__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3
-#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0101FF03U
-#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_776_READ_MASK 0x0101FF03U
+#define LPDDR4__DENALI_PHY_776_WRITE_MASK 0x0101FF03U
#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3_WIDTH 2U
#define LPDDR4__PHY_CTRL_LPBK_EN_3__REG DENALI_PHY_776
#define LPDDR4__PHY_CTRL_LPBK_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_CTRL_LPBK_EN_3
#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3_WIDTH 9U
#define LPDDR4__PHY_LPBK_CONTROL_3__REG DENALI_PHY_776
#define LPDDR4__PHY_LPBK_CONTROL_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_CONTROL_3
@@ -216,33 +215,33 @@
#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__REG DENALI_PHY_776
#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_3__FLD LPDDR4__DENALI_PHY_776__PHY_LPBK_DFX_TIMEOUT_EN_3
-#define LPDDR4__DENALI_PHY_777_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3_WIDTH 32U
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__REG DENALI_PHY_777
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_3__FLD LPDDR4__DENALI_PHY_777__PHY_AUTO_TIMING_MARGIN_CONTROL_3
-#define LPDDR4__DENALI_PHY_778_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_778_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_778_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3_WIDTH 28U
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__REG DENALI_PHY_778
#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_3__FLD LPDDR4__DENALI_PHY_778__PHY_AUTO_TIMING_MARGIN_OBS_3
-#define LPDDR4__DENALI_PHY_779_READ_MASK 0x0101FF7FU
-#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x0101FF7FU
+#define LPDDR4__DENALI_PHY_779_READ_MASK 0x0101FF7FU
+#define LPDDR4__DENALI_PHY_779_WRITE_MASK 0x0101FF7FU
#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_WIDTH 7U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3_WIDTH 7U
#define LPDDR4__PHY_PRBS_PATTERN_START_3__REG DENALI_PHY_779
#define LPDDR4__PHY_PRBS_PATTERN_START_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_START_3
#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3_WIDTH 9U
#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__REG DENALI_PHY_779
#define LPDDR4__PHY_PRBS_PATTERN_MASK_3__FLD LPDDR4__DENALI_PHY_779__PHY_PRBS_PATTERN_MASK_3
@@ -254,8 +253,8 @@
#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__REG DENALI_PHY_779
#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_3__FLD LPDDR4__DENALI_PHY_779__PHY_RDLVL_MULTI_PATT_ENABLE_3
-#define LPDDR4__DENALI_PHY_780_READ_MASK 0x007F3F01U
-#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x007F3F01U
+#define LPDDR4__DENALI_PHY_780_READ_MASK 0x007F3F01U
+#define LPDDR4__DENALI_PHY_780_WRITE_MASK 0x007F3F01U
#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_780__PHY_RDLVL_MULTI_PATT_RST_DISABLE_3_WIDTH 1U
@@ -271,13 +270,13 @@
#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_INITIAL_STEPSIZE_3
#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_MASK 0x007F0000U
-#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_WIDTH 7U
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3_WIDTH 7U
#define LPDDR4__PHY_VREF_TRAIN_OBS_3__REG DENALI_PHY_780
#define LPDDR4__PHY_VREF_TRAIN_OBS_3__FLD LPDDR4__DENALI_PHY_780__PHY_VREF_TRAIN_OBS_3
-#define LPDDR4__DENALI_PHY_781_READ_MASK 0x000F03FFU
-#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_781_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_781_WRITE_MASK 0x000F03FFU
#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_781__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3_WIDTH 10U
@@ -291,37 +290,37 @@
#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_3__FLD LPDDR4__DENALI_PHY_781__PHY_GATE_ERROR_DELAY_SELECT_3
#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3_WOSET 0U
#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__REG DENALI_PHY_781
#define LPDDR4__SC_PHY_SNAP_OBS_REGS_3__FLD LPDDR4__DENALI_PHY_781__SC_PHY_SNAP_OBS_REGS_3
-#define LPDDR4__DENALI_PHY_782_READ_MASK 0x070101FFU
-#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x070101FFU
+#define LPDDR4__DENALI_PHY_782_READ_MASK 0x070101FFU
+#define LPDDR4__DENALI_PHY_782_WRITE_MASK 0x070101FFU
#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3_WIDTH 9U
#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__REG DENALI_PHY_782
#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_782__PHY_GATE_SMPL1_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_782__PHY_LPDDR_3_WOSET 0U
#define LPDDR4__PHY_LPDDR_3__REG DENALI_PHY_782
#define LPDDR4__PHY_LPDDR_3__FLD LPDDR4__DENALI_PHY_782__PHY_LPDDR_3
-#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_WIDTH 3U
+#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3_WIDTH 3U
#define LPDDR4__PHY_MEM_CLASS_3__REG DENALI_PHY_782
#define LPDDR4__PHY_MEM_CLASS_3__FLD LPDDR4__DENALI_PHY_782__PHY_MEM_CLASS_3
-#define LPDDR4__DENALI_PHY_783_READ_MASK 0x000301FFU
-#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x000301FFU
+#define LPDDR4__DENALI_PHY_783_READ_MASK 0x000301FFU
+#define LPDDR4__DENALI_PHY_783_WRITE_MASK 0x000301FFU
#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3_WIDTH 9U
@@ -329,101 +328,101 @@
#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_783__PHY_GATE_SMPL2_SLAVE_DELAY_3
#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3_WIDTH 2U
#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__REG DENALI_PHY_783
#define LPDDR4__ON_FLY_GATE_ADJUST_EN_3__FLD LPDDR4__DENALI_PHY_783__ON_FLY_GATE_ADJUST_EN_3
-#define LPDDR4__DENALI_PHY_784_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_784_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_784_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3_WIDTH 32U
#define LPDDR4__PHY_GATE_TRACKING_OBS_3__REG DENALI_PHY_784
#define LPDDR4__PHY_GATE_TRACKING_OBS_3__FLD LPDDR4__DENALI_PHY_784__PHY_GATE_TRACKING_OBS_3
-#define LPDDR4__DENALI_PHY_785_READ_MASK 0x00000301U
-#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_785_READ_MASK 0x00000301U
+#define LPDDR4__DENALI_PHY_785_WRITE_MASK 0x00000301U
#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3_WOSET 0U
#define LPDDR4__PHY_DFI40_POLARITY_3__REG DENALI_PHY_785
#define LPDDR4__PHY_DFI40_POLARITY_3__FLD LPDDR4__DENALI_PHY_785__PHY_DFI40_POLARITY_3
#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3_WIDTH 2U
#define LPDDR4__PHY_LP4_PST_AMBLE_3__REG DENALI_PHY_785
#define LPDDR4__PHY_LP4_PST_AMBLE_3__FLD LPDDR4__DENALI_PHY_785__PHY_LP4_PST_AMBLE_3
-#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT8_3__REG DENALI_PHY_786
#define LPDDR4__PHY_RDLVL_PATT8_3__FLD LPDDR4__DENALI_PHY_786__PHY_RDLVL_PATT8_3
-#define LPDDR4__DENALI_PHY_787_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT9_3__REG DENALI_PHY_787
#define LPDDR4__PHY_RDLVL_PATT9_3__FLD LPDDR4__DENALI_PHY_787__PHY_RDLVL_PATT9_3
-#define LPDDR4__DENALI_PHY_788_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_788_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT10_3__REG DENALI_PHY_788
#define LPDDR4__PHY_RDLVL_PATT10_3__FLD LPDDR4__DENALI_PHY_788__PHY_RDLVL_PATT10_3
-#define LPDDR4__DENALI_PHY_789_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_789_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT11_3__REG DENALI_PHY_789
#define LPDDR4__PHY_RDLVL_PATT11_3__FLD LPDDR4__DENALI_PHY_789__PHY_RDLVL_PATT11_3
-#define LPDDR4__DENALI_PHY_790_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_790_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT12_3__REG DENALI_PHY_790
#define LPDDR4__PHY_RDLVL_PATT12_3__FLD LPDDR4__DENALI_PHY_790__PHY_RDLVL_PATT12_3
-#define LPDDR4__DENALI_PHY_791_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_791_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT13_3__REG DENALI_PHY_791
#define LPDDR4__PHY_RDLVL_PATT13_3__FLD LPDDR4__DENALI_PHY_791__PHY_RDLVL_PATT13_3
-#define LPDDR4__DENALI_PHY_792_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_792_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT14_3__REG DENALI_PHY_792
#define LPDDR4__PHY_RDLVL_PATT14_3__FLD LPDDR4__DENALI_PHY_792__PHY_RDLVL_PATT14_3
-#define LPDDR4__DENALI_PHY_793_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_793_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PATT15_3__REG DENALI_PHY_793
#define LPDDR4__PHY_RDLVL_PATT15_3__FLD LPDDR4__DENALI_PHY_793__PHY_RDLVL_PATT15_3
-#define LPDDR4__DENALI_PHY_794_READ_MASK 0x070F0107U
-#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_794_READ_MASK 0x070F0107U
+#define LPDDR4__DENALI_PHY_794_WRITE_MASK 0x070F0107U
#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_794__PHY_SLAVE_LOOP_CNT_UPDATE_3_WIDTH 3U
@@ -450,8 +449,8 @@
#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__REG DENALI_PHY_794
#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_794__PHY_RDDQ_ENC_OBS_SELECT_3
-#define LPDDR4__DENALI_PHY_795_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_795_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_795_WRITE_MASK 0x0F0F0F0FU
#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3_WIDTH 4U
@@ -459,8 +458,8 @@
#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_RDDQS_DQ_ENC_OBS_SELECT_3
#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_WIDTH 4U
+#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3_WIDTH 4U
#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__REG DENALI_PHY_795
#define LPDDR4__PHY_WR_ENC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_WR_ENC_OBS_SELECT_3
@@ -476,41 +475,41 @@
#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__REG DENALI_PHY_795
#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_795__PHY_FIFO_PTR_OBS_SELECT_3
-#define LPDDR4__DENALI_PHY_796_READ_MASK 0xFF030001U
-#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0xFF030001U
+#define LPDDR4__DENALI_PHY_796_READ_MASK 0xFF030001U
+#define LPDDR4__DENALI_PHY_796_WRITE_MASK 0xFF030001U
#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3_WOSET 0U
#define LPDDR4__PHY_LVL_DEBUG_MODE_3__REG DENALI_PHY_796
#define LPDDR4__PHY_LVL_DEBUG_MODE_3__FLD LPDDR4__DENALI_PHY_796__PHY_LVL_DEBUG_MODE_3
#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3_WOSET 0U
#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__REG DENALI_PHY_796
#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_3__FLD LPDDR4__DENALI_PHY_796__SC_PHY_LVL_DEBUG_CONT_3
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3_WIDTH 2U
#define LPDDR4__PHY_WRLVL_ALGO_3__REG DENALI_PHY_796
#define LPDDR4__PHY_WRLVL_ALGO_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_ALGO_3
#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3_WIDTH 8U
#define LPDDR4__PHY_WRLVL_PER_START_3__REG DENALI_PHY_796
#define LPDDR4__PHY_WRLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_796__PHY_WRLVL_PER_START_3
-#define LPDDR4__DENALI_PHY_797_READ_MASK 0x00FF0F3FU
-#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_797_READ_MASK 0x00FF0F3FU
+#define LPDDR4__DENALI_PHY_797_WRITE_MASK 0x00FF0F3FU
#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3_WIDTH 6U
#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__REG DENALI_PHY_797
#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_CAPTURE_CNT_3
@@ -520,23 +519,23 @@
#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_797
#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_797__PHY_WRLVL_UPDT_WAIT_CNT_3
-#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3_WIDTH 8U
#define LPDDR4__PHY_DQ_MASK_3__REG DENALI_PHY_797
#define LPDDR4__PHY_DQ_MASK_3__FLD LPDDR4__DENALI_PHY_797__PHY_DQ_MASK_3
-#define LPDDR4__DENALI_PHY_798_READ_MASK 0x0F3F03FFU
-#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_798_READ_MASK 0x0F3F03FFU
+#define LPDDR4__DENALI_PHY_798_WRITE_MASK 0x0F3F03FFU
#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3_WIDTH 10U
#define LPDDR4__PHY_GTLVL_PER_START_3__REG DENALI_PHY_798
#define LPDDR4__PHY_GTLVL_PER_START_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_PER_START_3
#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3_WIDTH 6U
#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__REG DENALI_PHY_798
#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_CAPTURE_CNT_3
@@ -546,11 +545,11 @@
#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_798
#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_798__PHY_GTLVL_UPDT_WAIT_CNT_3
-#define LPDDR4__DENALI_PHY_799_READ_MASK 0x1F030F3FU
-#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_799_READ_MASK 0x1F030F3FU
+#define LPDDR4__DENALI_PHY_799_WRITE_MASK 0x1F030F3FU
#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3_WIDTH 6U
#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__REG DENALI_PHY_799
#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_CAPTURE_CNT_3
@@ -561,8 +560,8 @@
#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_UPDT_WAIT_CNT_3
#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3_WIDTH 2U
#define LPDDR4__PHY_RDLVL_OP_MODE_3__REG DENALI_PHY_799
#define LPDDR4__PHY_RDLVL_OP_MODE_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_OP_MODE_3
@@ -572,8 +571,8 @@
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__REG DENALI_PHY_799
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_799__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3
-#define LPDDR4__DENALI_PHY_800_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_800_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_800_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3_WIDTH 8U
@@ -581,8 +580,8 @@
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_SELECT_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_PERIODIC_OBS_SELECT_3
#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3_WIDTH 8U
#define LPDDR4__PHY_RDLVL_DATA_MASK_3__REG DENALI_PHY_800
#define LPDDR4__PHY_RDLVL_DATA_MASK_3__FLD LPDDR4__DENALI_PHY_800__PHY_RDLVL_DATA_MASK_3
@@ -593,16 +592,16 @@
#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_CLK_JITTER_TOLERANCE_3
#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3_WIDTH 6U
#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__REG DENALI_PHY_800
#define LPDDR4__PHY_WDQLVL_BURST_CNT_3__FLD LPDDR4__DENALI_PHY_800__PHY_WDQLVL_BURST_CNT_3
-#define LPDDR4__DENALI_PHY_801_READ_MASK 0x0F07FF07U
-#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x0F07FF07U
+#define LPDDR4__DENALI_PHY_801_READ_MASK 0x0F07FF07U
+#define LPDDR4__DENALI_PHY_801_WRITE_MASK 0x0F07FF07U
#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_WIDTH 3U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3_WIDTH 3U
#define LPDDR4__PHY_WDQLVL_PATT_3__REG DENALI_PHY_801
#define LPDDR4__PHY_WDQLVL_PATT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_PATT_3
@@ -618,8 +617,8 @@
#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__REG DENALI_PHY_801
#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_801__PHY_WDQLVL_UPDT_WAIT_CNT_3
-#define LPDDR4__DENALI_PHY_802_READ_MASK 0x0000FF0FU
-#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PHY_802_READ_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PHY_802_WRITE_MASK 0x0000FF0FU
#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_802__PHY_WDQLVL_DQDM_OBS_SELECT_3_WIDTH 4U
@@ -640,64 +639,64 @@
#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__REG DENALI_PHY_802
#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3__FLD LPDDR4__DENALI_PHY_802__SC_PHY_WDQLVL_CLR_PREV_RESULTS_3
-#define LPDDR4__DENALI_PHY_803_READ_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_803_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_803_WRITE_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3_WIDTH 9U
#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__REG DENALI_PHY_803
#define LPDDR4__PHY_WDQLVL_DATADM_MASK_3__FLD LPDDR4__DENALI_PHY_803__PHY_WDQLVL_DATADM_MASK_3
-#define LPDDR4__DENALI_PHY_804_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_804_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_804_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3_WIDTH 32U
#define LPDDR4__PHY_USER_PATT0_3__REG DENALI_PHY_804
#define LPDDR4__PHY_USER_PATT0_3__FLD LPDDR4__DENALI_PHY_804__PHY_USER_PATT0_3
-#define LPDDR4__DENALI_PHY_805_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_805_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_805_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3_WIDTH 32U
#define LPDDR4__PHY_USER_PATT1_3__REG DENALI_PHY_805
#define LPDDR4__PHY_USER_PATT1_3__FLD LPDDR4__DENALI_PHY_805__PHY_USER_PATT1_3
-#define LPDDR4__DENALI_PHY_806_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_806_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3_WIDTH 32U
#define LPDDR4__PHY_USER_PATT2_3__REG DENALI_PHY_806
#define LPDDR4__PHY_USER_PATT2_3__FLD LPDDR4__DENALI_PHY_806__PHY_USER_PATT2_3
-#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_807_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3_WIDTH 32U
#define LPDDR4__PHY_USER_PATT3_3__REG DENALI_PHY_807
#define LPDDR4__PHY_USER_PATT3_3__FLD LPDDR4__DENALI_PHY_807__PHY_USER_PATT3_3
-#define LPDDR4__DENALI_PHY_808_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_WIDTH 16U
+#define LPDDR4__DENALI_PHY_808_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_808_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3_WIDTH 16U
#define LPDDR4__PHY_USER_PATT4_3__REG DENALI_PHY_808
#define LPDDR4__PHY_USER_PATT4_3__FLD LPDDR4__DENALI_PHY_808__PHY_USER_PATT4_3
#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3_WOSET 0U
#define LPDDR4__PHY_NTP_MULT_TRAIN_3__REG DENALI_PHY_808
#define LPDDR4__PHY_NTP_MULT_TRAIN_3__FLD LPDDR4__DENALI_PHY_808__PHY_NTP_MULT_TRAIN_3
-#define LPDDR4__DENALI_PHY_809_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_809_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_809_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_809__PHY_NTP_EARLY_THRESHOLD_3_WIDTH 10U
@@ -710,8 +709,8 @@
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__REG DENALI_PHY_809
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_809__PHY_NTP_PERIOD_THRESHOLD_3
-#define LPDDR4__DENALI_PHY_810_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_810_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_810_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MIN_3_WIDTH 10U
@@ -724,8 +723,8 @@
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__REG DENALI_PHY_810
#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_3__FLD LPDDR4__DENALI_PHY_810__PHY_NTP_PERIOD_THRESHOLD_MAX_3
-#define LPDDR4__DENALI_PHY_811_READ_MASK 0x00FF0001U
-#define LPDDR4__DENALI_PHY_811_WRITE_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_811_READ_MASK 0x00FF0001U
+#define LPDDR4__DENALI_PHY_811_WRITE_MASK 0x00FF0001U
#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3_WIDTH 1U
@@ -735,27 +734,27 @@
#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_3__FLD LPDDR4__DENALI_PHY_811__PHY_CALVL_VREF_DRIVING_SLICE_3
#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_MASK 0x00003F00U
-#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3_WIDTH 6U
#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__REG DENALI_PHY_811
#define LPDDR4__SC_PHY_MANUAL_CLEAR_3__FLD LPDDR4__DENALI_PHY_811__SC_PHY_MANUAL_CLEAR_3
#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3_WIDTH 8U
#define LPDDR4__PHY_FIFO_PTR_OBS_3__REG DENALI_PHY_811
#define LPDDR4__PHY_FIFO_PTR_OBS_3__FLD LPDDR4__DENALI_PHY_811__PHY_FIFO_PTR_OBS_3
-#define LPDDR4__DENALI_PHY_812_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_812_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_812_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_812_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3_WIDTH 32U
#define LPDDR4__PHY_LPBK_RESULT_OBS_3__REG DENALI_PHY_812
#define LPDDR4__PHY_LPBK_RESULT_OBS_3__FLD LPDDR4__DENALI_PHY_812__PHY_LPBK_RESULT_OBS_3
-#define LPDDR4__DENALI_PHY_813_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_813_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_813_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_813_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_813__PHY_LPBK_ERROR_COUNT_OBS_3_WIDTH 16U
@@ -768,8 +767,8 @@
#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__REG DENALI_PHY_813
#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_813__PHY_MASTER_DLY_LOCK_OBS_3
-#define LPDDR4__DENALI_PHY_814_READ_MASK 0xFFFF7F7FU
-#define LPDDR4__DENALI_PHY_814_WRITE_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_814_READ_MASK 0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_814_WRITE_MASK 0xFFFF7F7FU
#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_814__PHY_RDDQ_SLV_DLY_ENC_OBS_3_WIDTH 7U
@@ -794,8 +793,8 @@
#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_814
#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_814__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3
-#define LPDDR4__DENALI_PHY_815_READ_MASK 0x7F07FFFFU
-#define LPDDR4__DENALI_PHY_815_WRITE_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_815_READ_MASK 0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_815_WRITE_MASK 0x7F07FFFFU
#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_815__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3_WIDTH 8U
@@ -814,8 +813,8 @@
#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_815
#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_815__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3
-#define LPDDR4__DENALI_PHY_816_READ_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_PHY_816_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_816_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_816_WRITE_MASK 0x0007FFFFU
#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_816__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3_WIDTH 8U
@@ -829,13 +828,13 @@
#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_ADDER_SLV_DLY_ENC_OBS_3
#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_MASK 0x00070000U
-#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_WIDTH 3U
+#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3_WIDTH 3U
#define LPDDR4__PHY_WR_SHIFT_OBS_3__REG DENALI_PHY_816
#define LPDDR4__PHY_WR_SHIFT_OBS_3__FLD LPDDR4__DENALI_PHY_816__PHY_WR_SHIFT_OBS_3
-#define LPDDR4__DENALI_PHY_817_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_817_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_817_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_817_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD0_DELAY_OBS_3_WIDTH 10U
@@ -848,16 +847,16 @@
#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_817
#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_817__PHY_WRLVL_HARD1_DELAY_OBS_3
-#define LPDDR4__DENALI_PHY_818_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_818_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_818_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_818_WRITE_MASK 0x0001FFFFU
#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_WIDTH 17U
+#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3_WIDTH 17U
#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__REG DENALI_PHY_818
#define LPDDR4__PHY_WRLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_818__PHY_WRLVL_STATUS_OBS_3
-#define LPDDR4__DENALI_PHY_819_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_819_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_819_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3_WIDTH 10U
@@ -870,11 +869,11 @@
#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__REG DENALI_PHY_819
#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3__FLD LPDDR4__DENALI_PHY_819__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3
-#define LPDDR4__DENALI_PHY_820_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_820_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_820_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_820_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_WIDTH 16U
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3_WIDTH 16U
#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__REG DENALI_PHY_820
#define LPDDR4__PHY_WRLVL_ERROR_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_WRLVL_ERROR_OBS_3
@@ -884,24 +883,24 @@
#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__REG DENALI_PHY_820
#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_820__PHY_GTLVL_HARD0_DELAY_OBS_3
-#define LPDDR4__DENALI_PHY_821_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_821_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_821_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_821_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3_WIDTH 14U
#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__REG DENALI_PHY_821
#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_3__FLD LPDDR4__DENALI_PHY_821__PHY_GTLVL_HARD1_DELAY_OBS_3
-#define LPDDR4__DENALI_PHY_822_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_822_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_822_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_822_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_WIDTH 18U
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3_WIDTH 18U
#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__REG DENALI_PHY_822
#define LPDDR4__PHY_GTLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_822__PHY_GTLVL_STATUS_OBS_3
-#define LPDDR4__DENALI_PHY_823_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_823_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_823_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_823_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3_WIDTH 10U
@@ -914,32 +913,32 @@
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__REG DENALI_PHY_823
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_823__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3
-#define LPDDR4__DENALI_PHY_824_READ_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_824_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_824_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_824_WRITE_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3_WIDTH 2U
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__REG DENALI_PHY_824
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3__FLD LPDDR4__DENALI_PHY_824__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3
-#define LPDDR4__DENALI_PHY_825_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_825_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_825_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_825_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__REG DENALI_PHY_825
#define LPDDR4__PHY_RDLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_825__PHY_RDLVL_STATUS_OBS_3
-#define LPDDR4__DENALI_PHY_826_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_826_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_826_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_826_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3_WIDTH 32U
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__REG DENALI_PHY_826
#define LPDDR4__PHY_RDLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_826__PHY_RDLVL_PERIODIC_OBS_3
-#define LPDDR4__DENALI_PHY_827_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_827_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_827_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_827_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_LE_DLY_OBS_3_WIDTH 11U
@@ -952,56 +951,56 @@
#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__REG DENALI_PHY_827
#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_827__PHY_WDQLVL_DQDM_TE_DLY_OBS_3
-#define LPDDR4__DENALI_PHY_828_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_828_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_828_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_828_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3_WIDTH 32U
#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__REG DENALI_PHY_828
#define LPDDR4__PHY_WDQLVL_STATUS_OBS_3__FLD LPDDR4__DENALI_PHY_828__PHY_WDQLVL_STATUS_OBS_3
-#define LPDDR4__DENALI_PHY_829_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_829_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_829_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3_WIDTH 32U
#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__REG DENALI_PHY_829
#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_3__FLD LPDDR4__DENALI_PHY_829__PHY_WDQLVL_PERIODIC_OBS_3
-#define LPDDR4__DENALI_PHY_830_READ_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_830_WRITE_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_WIDTH 31U
+#define LPDDR4__DENALI_PHY_830_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_830_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3_WIDTH 31U
#define LPDDR4__PHY_DDL_MODE_3__REG DENALI_PHY_830
#define LPDDR4__PHY_DDL_MODE_3__FLD LPDDR4__DENALI_PHY_830__PHY_DDL_MODE_3
-#define LPDDR4__DENALI_PHY_831_READ_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_831_WRITE_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_831_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_831_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3_WIDTH 6U
#define LPDDR4__PHY_DDL_MASK_3__REG DENALI_PHY_831
#define LPDDR4__PHY_DDL_MASK_3__FLD LPDDR4__DENALI_PHY_831__PHY_DDL_MASK_3
-#define LPDDR4__DENALI_PHY_832_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_832_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_832_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_832_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3_WIDTH 32U
#define LPDDR4__PHY_DDL_TEST_OBS_3__REG DENALI_PHY_832
#define LPDDR4__PHY_DDL_TEST_OBS_3__FLD LPDDR4__DENALI_PHY_832__PHY_DDL_TEST_OBS_3
-#define LPDDR4__DENALI_PHY_833_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_833_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_833_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3_WIDTH 32U
#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__REG DENALI_PHY_833
#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_3__FLD LPDDR4__DENALI_PHY_833__PHY_DDL_TEST_MSTR_DLY_OBS_3
-#define LPDDR4__DENALI_PHY_834_READ_MASK 0x010001FFU
-#define LPDDR4__DENALI_PHY_834_WRITE_MASK 0x010001FFU
+#define LPDDR4__DENALI_PHY_834_READ_MASK 0x010001FFU
+#define LPDDR4__DENALI_PHY_834_WRITE_MASK 0x010001FFU
#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3_WIDTH 8U
@@ -1009,34 +1008,34 @@
#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_834__PHY_DDL_TRACK_UPD_THRESHOLD_3
#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3_WOSET 0U
#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__REG DENALI_PHY_834
#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_3__FLD LPDDR4__DENALI_PHY_834__PHY_LP4_WDQS_OE_EXTEND_3
#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3_WOSET 0U
#define LPDDR4__SC_PHY_RX_CAL_START_3__REG DENALI_PHY_834
#define LPDDR4__SC_PHY_RX_CAL_START_3__FLD LPDDR4__DENALI_PHY_834__SC_PHY_RX_CAL_START_3
#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3_WOSET 0U
#define LPDDR4__PHY_RX_CAL_OVERRIDE_3__REG DENALI_PHY_834
#define LPDDR4__PHY_RX_CAL_OVERRIDE_3__FLD LPDDR4__DENALI_PHY_834__PHY_RX_CAL_OVERRIDE_3
-#define LPDDR4__DENALI_PHY_835_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_835_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_835_WRITE_MASK 0x01FF01FFU
#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3_WIDTH 8U
#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__REG DENALI_PHY_835
#define LPDDR4__PHY_RX_CAL_SAMPLE_WAIT_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_SAMPLE_WAIT_3
@@ -1048,147 +1047,147 @@
#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__REG DENALI_PHY_835
#define LPDDR4__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3__FLD LPDDR4__DENALI_PHY_835__PHY_SLICE_RXCAL_SHUTOFF_FDBK_OE_3
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ0_3__REG DENALI_PHY_835
#define LPDDR4__PHY_RX_CAL_DQ0_3__FLD LPDDR4__DENALI_PHY_835__PHY_RX_CAL_DQ0_3
-#define LPDDR4__DENALI_PHY_836_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_836_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_836_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ1_3__REG DENALI_PHY_836
#define LPDDR4__PHY_RX_CAL_DQ1_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ1_3
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ2_3__REG DENALI_PHY_836
#define LPDDR4__PHY_RX_CAL_DQ2_3__FLD LPDDR4__DENALI_PHY_836__PHY_RX_CAL_DQ2_3
-#define LPDDR4__DENALI_PHY_837_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_837_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_837_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ3_3__REG DENALI_PHY_837
#define LPDDR4__PHY_RX_CAL_DQ3_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ3_3
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ4_3__REG DENALI_PHY_837
#define LPDDR4__PHY_RX_CAL_DQ4_3__FLD LPDDR4__DENALI_PHY_837__PHY_RX_CAL_DQ4_3
-#define LPDDR4__DENALI_PHY_838_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_838_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_838_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ5_3__REG DENALI_PHY_838
#define LPDDR4__PHY_RX_CAL_DQ5_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ5_3
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ6_3__REG DENALI_PHY_838
#define LPDDR4__PHY_RX_CAL_DQ6_3__FLD LPDDR4__DENALI_PHY_838__PHY_RX_CAL_DQ6_3
-#define LPDDR4__DENALI_PHY_839_READ_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_839_WRITE_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_839_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_839_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQ7_3__REG DENALI_PHY_839
#define LPDDR4__PHY_RX_CAL_DQ7_3__FLD LPDDR4__DENALI_PHY_839__PHY_RX_CAL_DQ7_3
-#define LPDDR4__DENALI_PHY_840_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_840_WRITE_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH 18U
+#define LPDDR4__DENALI_PHY_840_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3_WIDTH 18U
#define LPDDR4__PHY_RX_CAL_DM_3__REG DENALI_PHY_840
#define LPDDR4__PHY_RX_CAL_DM_3__FLD LPDDR4__DENALI_PHY_840__PHY_RX_CAL_DM_3
-#define LPDDR4__DENALI_PHY_841_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_841_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_841_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_DQS_3__REG DENALI_PHY_841
#define LPDDR4__PHY_RX_CAL_DQS_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_DQS_3
#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_FDBK_3__REG DENALI_PHY_841
#define LPDDR4__PHY_RX_CAL_FDBK_3__FLD LPDDR4__DENALI_PHY_841__PHY_RX_CAL_FDBK_3
-#define LPDDR4__DENALI_PHY_842_READ_MASK 0x01FF07FFU
-#define LPDDR4__DENALI_PHY_842_WRITE_MASK 0x01FF07FFU
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_WIDTH 11U
+#define LPDDR4__DENALI_PHY_842_READ_MASK 0x01FF07FFU
+#define LPDDR4__DENALI_PHY_842_WRITE_MASK 0x01FF07FFU
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3_WIDTH 11U
#define LPDDR4__PHY_RX_CAL_OBS_3__REG DENALI_PHY_842
#define LPDDR4__PHY_RX_CAL_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_OBS_3
#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_MASK 0x01FF0000U
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_WIDTH 9U
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3_WIDTH 9U
#define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__REG DENALI_PHY_842
#define LPDDR4__PHY_RX_CAL_LOCK_OBS_3__FLD LPDDR4__DENALI_PHY_842__PHY_RX_CAL_LOCK_OBS_3
-#define LPDDR4__DENALI_PHY_843_READ_MASK 0x017F7F01U
-#define LPDDR4__DENALI_PHY_843_WRITE_MASK 0x017F7F01U
+#define LPDDR4__DENALI_PHY_843_READ_MASK 0x017F7F01U
+#define LPDDR4__DENALI_PHY_843_WRITE_MASK 0x017F7F01U
#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3_WOSET 0U
#define LPDDR4__PHY_RX_CAL_DISABLE_3__REG DENALI_PHY_843
#define LPDDR4__PHY_RX_CAL_DISABLE_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DISABLE_3
#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_MASK 0x00007F00U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_WIDTH 7U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3_WIDTH 7U
#define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__REG DENALI_PHY_843
#define LPDDR4__PHY_RX_CAL_SE_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_SE_ADJUST_3
#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_MASK 0x007F0000U
#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_WIDTH 7U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3_WIDTH 7U
#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__REG DENALI_PHY_843
#define LPDDR4__PHY_RX_CAL_DIFF_ADJUST_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_DIFF_ADJUST_3
#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3_WOSET 0U
#define LPDDR4__PHY_RX_CAL_COMP_VAL_3__REG DENALI_PHY_843
#define LPDDR4__PHY_RX_CAL_COMP_VAL_3__FLD LPDDR4__DENALI_PHY_843__PHY_RX_CAL_COMP_VAL_3
-#define LPDDR4__DENALI_PHY_844_READ_MASK 0x07FF0FFFU
-#define LPDDR4__DENALI_PHY_844_WRITE_MASK 0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_844_READ_MASK 0x07FF0FFFU
+#define LPDDR4__DENALI_PHY_844_WRITE_MASK 0x07FF0FFFU
#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_WIDTH 12U
+#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3_WIDTH 12U
#define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__REG DENALI_PHY_844
#define LPDDR4__PHY_RX_CAL_INDEX_MASK_3__FLD LPDDR4__DENALI_PHY_844__PHY_RX_CAL_INDEX_MASK_3
#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_WIDTH 11U
+#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3_WIDTH 11U
#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__REG DENALI_PHY_844
#define LPDDR4__PHY_PAD_RX_BIAS_EN_3__FLD LPDDR4__DENALI_PHY_844__PHY_PAD_RX_BIAS_EN_3
-#define LPDDR4__DENALI_PHY_845_READ_MASK 0x03FFFF1FU
-#define LPDDR4__DENALI_PHY_845_WRITE_MASK 0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_845_READ_MASK 0x03FFFF1FU
+#define LPDDR4__DENALI_PHY_845_WRITE_MASK 0x03FFFF1FU
#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3_WIDTH 5U
#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__REG DENALI_PHY_845
#define LPDDR4__PHY_STATIC_TOG_DISABLE_3__FLD LPDDR4__DENALI_PHY_845__PHY_STATIC_TOG_DISABLE_3
@@ -1205,13 +1204,13 @@
#define LPDDR4__PHY_DATA_DC_CAL_TIMEOUT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_CAL_TIMEOUT_3
#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_MASK 0x03000000U
-#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3_WIDTH 2U
#define LPDDR4__PHY_DATA_DC_WEIGHT_3__REG DENALI_PHY_845
#define LPDDR4__PHY_DATA_DC_WEIGHT_3__FLD LPDDR4__DENALI_PHY_845__PHY_DATA_DC_WEIGHT_3
-#define LPDDR4__DENALI_PHY_846_READ_MASK 0x01FFFF3FU
-#define LPDDR4__DENALI_PHY_846_WRITE_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_846_READ_MASK 0x01FFFF3FU
+#define LPDDR4__DENALI_PHY_846_WRITE_MASK 0x01FFFF3FU
#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_START_3_WIDTH 6U
@@ -1238,8 +1237,8 @@
#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__REG DENALI_PHY_846
#define LPDDR4__PHY_DATA_DC_ADJUST_DIRECT_3__FLD LPDDR4__DENALI_PHY_846__PHY_DATA_DC_ADJUST_DIRECT_3
-#define LPDDR4__DENALI_PHY_847_READ_MASK 0x07030101U
-#define LPDDR4__DENALI_PHY_847_WRITE_MASK 0x07030101U
+#define LPDDR4__DENALI_PHY_847_READ_MASK 0x07030101U
+#define LPDDR4__DENALI_PHY_847_WRITE_MASK 0x07030101U
#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3_WIDTH 1U
@@ -1249,27 +1248,27 @@
#define LPDDR4__PHY_DATA_DC_CAL_POLARITY_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_POLARITY_3
#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3_WOSET 0U
#define LPDDR4__PHY_DATA_DC_CAL_START_3__REG DENALI_PHY_847
#define LPDDR4__PHY_DATA_DC_CAL_START_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_CAL_START_3
#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3_WIDTH 2U
#define LPDDR4__PHY_DATA_DC_SW_RANK_3__REG DENALI_PHY_847
#define LPDDR4__PHY_DATA_DC_SW_RANK_3__FLD LPDDR4__DENALI_PHY_847__PHY_DATA_DC_SW_RANK_3
#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_WIDTH 3U
+#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3_WIDTH 3U
#define LPDDR4__PHY_FDBK_PWR_CTRL_3__REG DENALI_PHY_847
#define LPDDR4__PHY_FDBK_PWR_CTRL_3__FLD LPDDR4__DENALI_PHY_847__PHY_FDBK_PWR_CTRL_3
-#define LPDDR4__DENALI_PHY_848_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PHY_848_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_848_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PHY_848_WRITE_MASK 0x01010101U
#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_848__PHY_SLV_DLY_CTRL_GATE_DISABLE_3_WIDTH 1U
@@ -1302,22 +1301,22 @@
#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__REG DENALI_PHY_848
#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_3__FLD LPDDR4__DENALI_PHY_848__PHY_SLICE_PWR_RDC_DISABLE_3
-#define LPDDR4__DENALI_PHY_849_READ_MASK 0x3FFF07FFU
-#define LPDDR4__DENALI_PHY_849_WRITE_MASK 0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_849_READ_MASK 0x3FFF07FFU
+#define LPDDR4__DENALI_PHY_849_WRITE_MASK 0x3FFF07FFU
#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3_WIDTH 11U
#define LPDDR4__PHY_PARITY_ERROR_REGIF_3__REG DENALI_PHY_849
#define LPDDR4__PHY_PARITY_ERROR_REGIF_3__FLD LPDDR4__DENALI_PHY_849__PHY_PARITY_ERROR_REGIF_3
#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_MASK 0x3FFF0000U
-#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_WIDTH 14U
+#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3_WIDTH 14U
#define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__REG DENALI_PHY_849
#define LPDDR4__PHY_DS_FSM_ERROR_INFO_3__FLD LPDDR4__DENALI_PHY_849__PHY_DS_FSM_ERROR_INFO_3
-#define LPDDR4__DENALI_PHY_850_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_850_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_850_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_850_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_850__PHY_DS_FSM_ERROR_INFO_MASK_3_WIDTH 14U
@@ -1330,8 +1329,8 @@
#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__REG DENALI_PHY_850
#define LPDDR4__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_850__SC_PHY_DS_FSM_ERROR_INFO_WOCLR_3
-#define LPDDR4__DENALI_PHY_851_READ_MASK 0x00001F1FU
-#define LPDDR4__DENALI_PHY_851_WRITE_MASK 0x00001F1FU
+#define LPDDR4__DENALI_PHY_851_READ_MASK 0x00001F1FU
+#define LPDDR4__DENALI_PHY_851_WRITE_MASK 0x00001F1FU
#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_851__PHY_DS_TRAIN_CALIB_ERROR_INFO_3_WIDTH 5U
@@ -1350,37 +1349,37 @@
#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__REG DENALI_PHY_851
#define LPDDR4__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3__FLD LPDDR4__DENALI_PHY_851__SC_PHY_DS_TRAIN_CALIB_ERROR_INFO_WOCLR_3
-#define LPDDR4__DENALI_PHY_852_READ_MASK 0x07FFFF07U
-#define LPDDR4__DENALI_PHY_852_WRITE_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_852_READ_MASK 0x07FFFF07U
+#define LPDDR4__DENALI_PHY_852_WRITE_MASK 0x07FFFF07U
#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_WIDTH 3U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3_WIDTH 3U
#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__REG DENALI_PHY_852
#define LPDDR4__PHY_DQ_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_ENABLE_3
#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_WIDTH 16U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3_WIDTH 16U
#define LPDDR4__PHY_DQ_TSEL_SELECT_3__REG DENALI_PHY_852
#define LPDDR4__PHY_DQ_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQ_TSEL_SELECT_3
#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_WIDTH 3U
+#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3_WIDTH 3U
#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__REG DENALI_PHY_852
#define LPDDR4__PHY_DQS_TSEL_ENABLE_3__FLD LPDDR4__DENALI_PHY_852__PHY_DQS_TSEL_ENABLE_3
-#define LPDDR4__DENALI_PHY_853_READ_MASK 0x7F03FFFFU
-#define LPDDR4__DENALI_PHY_853_WRITE_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_853_READ_MASK 0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_853_WRITE_MASK 0x7F03FFFFU
#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_WIDTH 16U
+#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3_WIDTH 16U
#define LPDDR4__PHY_DQS_TSEL_SELECT_3__REG DENALI_PHY_853
#define LPDDR4__PHY_DQS_TSEL_SELECT_3__FLD LPDDR4__DENALI_PHY_853__PHY_DQS_TSEL_SELECT_3
#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3_WIDTH 2U
#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__REG DENALI_PHY_853
#define LPDDR4__PHY_TWO_CYC_PREAMBLE_3__FLD LPDDR4__DENALI_PHY_853__PHY_TWO_CYC_PREAMBLE_3
@@ -1390,8 +1389,8 @@
#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__REG DENALI_PHY_853
#define LPDDR4__PHY_VREF_INITIAL_START_POINT_3__FLD LPDDR4__DENALI_PHY_853__PHY_VREF_INITIAL_START_POINT_3
-#define LPDDR4__DENALI_PHY_854_READ_MASK 0xFF01037FU
-#define LPDDR4__DENALI_PHY_854_WRITE_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_854_READ_MASK 0xFF01037FU
+#define LPDDR4__DENALI_PHY_854_WRITE_MASK 0xFF01037FU
#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_MASK 0x0000007FU
#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3_WIDTH 7U
@@ -1399,50 +1398,50 @@
#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_INITIAL_STOP_POINT_3
#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3_WIDTH 2U
#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__REG DENALI_PHY_854
#define LPDDR4__PHY_VREF_TRAINING_CTRL_3__FLD LPDDR4__DENALI_PHY_854__PHY_VREF_TRAINING_CTRL_3
#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3_WOSET 0U
#define LPDDR4__PHY_NTP_TRAIN_EN_3__REG DENALI_PHY_854
#define LPDDR4__PHY_NTP_TRAIN_EN_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_TRAIN_EN_3
#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3_WIDTH 8U
#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__REG DENALI_PHY_854
#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_3__FLD LPDDR4__DENALI_PHY_854__PHY_NTP_WDQ_STEP_SIZE_3
-#define LPDDR4__DENALI_PHY_855_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_855_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_855_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_855_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_WIDTH 11U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3_WIDTH 11U
#define LPDDR4__PHY_NTP_WDQ_START_3__REG DENALI_PHY_855
#define LPDDR4__PHY_NTP_WDQ_START_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_START_3
#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_WIDTH 11U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3_WIDTH 11U
#define LPDDR4__PHY_NTP_WDQ_STOP_3__REG DENALI_PHY_855
#define LPDDR4__PHY_NTP_WDQ_STOP_3__FLD LPDDR4__DENALI_PHY_855__PHY_NTP_WDQ_STOP_3
-#define LPDDR4__DENALI_PHY_856_READ_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_PHY_856_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_856_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_856_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3_WIDTH 8U
#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__REG DENALI_PHY_856
#define LPDDR4__PHY_NTP_WDQ_BIT_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_NTP_WDQ_BIT_EN_3
#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_MASK 0x0003FF00U
-#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3_WIDTH 10U
#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__REG DENALI_PHY_856
#define LPDDR4__PHY_WDQLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_856__PHY_WDQLVL_DVW_MIN_3
@@ -1454,8 +1453,8 @@
#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__REG DENALI_PHY_856
#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_3__FLD LPDDR4__DENALI_PHY_856__PHY_SW_WDQLVL_DVW_MIN_EN_3
-#define LPDDR4__DENALI_PHY_857_READ_MASK 0x1F1F0F3FU
-#define LPDDR4__DENALI_PHY_857_WRITE_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_857_READ_MASK 0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_857_WRITE_MASK 0x1F1F0F3FU
#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3_WIDTH 6U
@@ -1463,156 +1462,156 @@
#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_857__PHY_WDQLVL_PER_START_OFFSET_3
#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_WIDTH 4U
+#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3_WIDTH 4U
#define LPDDR4__PHY_FAST_LVL_EN_3__REG DENALI_PHY_857
#define LPDDR4__PHY_FAST_LVL_EN_3__FLD LPDDR4__DENALI_PHY_857__PHY_FAST_LVL_EN_3
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3_WIDTH 5U
#define LPDDR4__PHY_PAD_TX_DCD_3__REG DENALI_PHY_857
#define LPDDR4__PHY_PAD_TX_DCD_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_TX_DCD_3
#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_0_3__REG DENALI_PHY_857
#define LPDDR4__PHY_PAD_RX_DCD_0_3__FLD LPDDR4__DENALI_PHY_857__PHY_PAD_RX_DCD_0_3
-#define LPDDR4__DENALI_PHY_858_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_858_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_858_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_858_WRITE_MASK 0x1F1F1F1FU
#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_1_3__REG DENALI_PHY_858
#define LPDDR4__PHY_PAD_RX_DCD_1_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_1_3
#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_2_3__REG DENALI_PHY_858
#define LPDDR4__PHY_PAD_RX_DCD_2_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_2_3
#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_3_3__REG DENALI_PHY_858
#define LPDDR4__PHY_PAD_RX_DCD_3_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_3_3
#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_4_3__REG DENALI_PHY_858
#define LPDDR4__PHY_PAD_RX_DCD_4_3__FLD LPDDR4__DENALI_PHY_858__PHY_PAD_RX_DCD_4_3
-#define LPDDR4__DENALI_PHY_859_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_859_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_859_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_859_WRITE_MASK 0x1F1F1F1FU
#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_5_3__REG DENALI_PHY_859
#define LPDDR4__PHY_PAD_RX_DCD_5_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_5_3
#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_6_3__REG DENALI_PHY_859
#define LPDDR4__PHY_PAD_RX_DCD_6_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_6_3
#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3_WIDTH 5U
#define LPDDR4__PHY_PAD_RX_DCD_7_3__REG DENALI_PHY_859
#define LPDDR4__PHY_PAD_RX_DCD_7_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_RX_DCD_7_3
#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3_WIDTH 5U
#define LPDDR4__PHY_PAD_DM_RX_DCD_3__REG DENALI_PHY_859
#define LPDDR4__PHY_PAD_DM_RX_DCD_3__FLD LPDDR4__DENALI_PHY_859__PHY_PAD_DM_RX_DCD_3
-#define LPDDR4__DENALI_PHY_860_READ_MASK 0x003F1F1FU
-#define LPDDR4__DENALI_PHY_860_WRITE_MASK 0x003F1F1FU
+#define LPDDR4__DENALI_PHY_860_READ_MASK 0x003F1F1FU
+#define LPDDR4__DENALI_PHY_860_WRITE_MASK 0x003F1F1FU
#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3_WIDTH 5U
#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__REG DENALI_PHY_860
#define LPDDR4__PHY_PAD_DQS_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DQS_RX_DCD_3
#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3_WIDTH 5U
#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__REG DENALI_PHY_860
#define LPDDR4__PHY_PAD_FDBK_RX_DCD_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_FDBK_RX_DCD_3
#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_MASK 0x003F0000U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3_WIDTH 6U
#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__REG DENALI_PHY_860
#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_3__FLD LPDDR4__DENALI_PHY_860__PHY_PAD_DSLICE_IO_CFG_3
-#define LPDDR4__DENALI_PHY_861_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_861_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_861_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_861_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3_WIDTH 10U
#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__REG DENALI_PHY_861
#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ0_SLAVE_DELAY_3
#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3_WIDTH 10U
#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__REG DENALI_PHY_861
#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_861__PHY_RDDQ1_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_862_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_862_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_862_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_862_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3_WIDTH 10U
#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__REG DENALI_PHY_862
#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ2_SLAVE_DELAY_3
#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3_WIDTH 10U
#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__REG DENALI_PHY_862
#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_862__PHY_RDDQ3_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_863_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_863_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_863_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_863_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3_WIDTH 10U
#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__REG DENALI_PHY_863
#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ4_SLAVE_DELAY_3
#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3_WIDTH 10U
#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__REG DENALI_PHY_863
#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_863__PHY_RDDQ5_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_864_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_864_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_864_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_864_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3_WIDTH 10U
#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__REG DENALI_PHY_864
#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ6_SLAVE_DELAY_3
#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3_WIDTH 10U
#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__REG DENALI_PHY_864
#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_864__PHY_RDDQ7_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_865_READ_MASK 0x000703FFU
-#define LPDDR4__DENALI_PHY_865_WRITE_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_865_READ_MASK 0x000703FFU
+#define LPDDR4__DENALI_PHY_865_WRITE_MASK 0x000703FFU
#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3_WIDTH 10U
#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__REG DENALI_PHY_865
#define LPDDR4__PHY_RDDM_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_865__PHY_RDDM_SLAVE_DELAY_3
@@ -1622,34 +1621,34 @@
#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__REG DENALI_PHY_865
#define LPDDR4__PHY_DATA_DC_CAL_CLK_SEL_3__FLD LPDDR4__DENALI_PHY_865__PHY_DATA_DC_CAL_CLK_SEL_3
-#define LPDDR4__DENALI_PHY_866_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_866_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_866_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_866_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3_WIDTH 8U
#define LPDDR4__PHY_DQ_OE_TIMING_3__REG DENALI_PHY_866
#define LPDDR4__PHY_DQ_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_OE_TIMING_3
#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3_WIDTH 8U
#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__REG DENALI_PHY_866
#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_RD_TIMING_3
#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3_WIDTH 8U
#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__REG DENALI_PHY_866
#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQ_TSEL_WR_TIMING_3
#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3_WIDTH 8U
#define LPDDR4__PHY_DQS_OE_TIMING_3__REG DENALI_PHY_866
#define LPDDR4__PHY_DQS_OE_TIMING_3__FLD LPDDR4__DENALI_PHY_866__PHY_DQS_OE_TIMING_3
-#define LPDDR4__DENALI_PHY_867_READ_MASK 0xFFFFFF0FU
-#define LPDDR4__DENALI_PHY_867_WRITE_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_867_READ_MASK 0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_867_WRITE_MASK 0xFFFFFF0FU
#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3_WIDTH 4U
@@ -1657,118 +1656,118 @@
#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_IO_PAD_DELAY_TIMING_3
#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3_WIDTH 8U
#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__REG DENALI_PHY_867
#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_RD_TIMING_3
#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3_WIDTH 8U
#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__REG DENALI_PHY_867
#define LPDDR4__PHY_DQS_OE_RD_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_OE_RD_TIMING_3
#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_MASK 0xFF000000U
#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3_WIDTH 8U
#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__REG DENALI_PHY_867
#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_3__FLD LPDDR4__DENALI_PHY_867__PHY_DQS_TSEL_WR_TIMING_3
-#define LPDDR4__DENALI_PHY_868_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_868_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_868_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_868_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_WIDTH 16U
+#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3_WIDTH 16U
#define LPDDR4__PHY_VREF_SETTING_TIME_3__REG DENALI_PHY_868
#define LPDDR4__PHY_VREF_SETTING_TIME_3__FLD LPDDR4__DENALI_PHY_868__PHY_VREF_SETTING_TIME_3
#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_WIDTH 12U
+#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3_WIDTH 12U
#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__REG DENALI_PHY_868
#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_3__FLD LPDDR4__DENALI_PHY_868__PHY_PAD_VREF_CTRL_DQ_3
-#define LPDDR4__DENALI_PHY_869_READ_MASK 0x03FFFF01U
-#define LPDDR4__DENALI_PHY_869_WRITE_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_869_READ_MASK 0x03FFFF01U
+#define LPDDR4__DENALI_PHY_869_WRITE_MASK 0x03FFFF01U
#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3_WOSET 0U
#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__REG DENALI_PHY_869
#define LPDDR4__PHY_PER_CS_TRAINING_EN_3__FLD LPDDR4__DENALI_PHY_869__PHY_PER_CS_TRAINING_EN_3
#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3_WIDTH 8U
#define LPDDR4__PHY_DQ_IE_TIMING_3__REG DENALI_PHY_869
#define LPDDR4__PHY_DQ_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQ_IE_TIMING_3
#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3_WIDTH 8U
#define LPDDR4__PHY_DQS_IE_TIMING_3__REG DENALI_PHY_869
#define LPDDR4__PHY_DQS_IE_TIMING_3__FLD LPDDR4__DENALI_PHY_869__PHY_DQS_IE_TIMING_3
#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_MASK 0x03000000U
-#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3_WIDTH 2U
#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__REG DENALI_PHY_869
#define LPDDR4__PHY_RDDATA_EN_IE_DLY_3__FLD LPDDR4__DENALI_PHY_869__PHY_RDDATA_EN_IE_DLY_3
-#define LPDDR4__DENALI_PHY_870_READ_MASK 0x1F1F0103U
-#define LPDDR4__DENALI_PHY_870_WRITE_MASK 0x1F1F0103U
-#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_870_READ_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_870_WRITE_MASK 0x1F1F0103U
+#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3_WIDTH 2U
#define LPDDR4__PHY_IE_MODE_3__REG DENALI_PHY_870
#define LPDDR4__PHY_IE_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_IE_MODE_3
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3_WOSET 0U
#define LPDDR4__PHY_DBI_MODE_3__REG DENALI_PHY_870
#define LPDDR4__PHY_DBI_MODE_3__FLD LPDDR4__DENALI_PHY_870__PHY_DBI_MODE_3
#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__REG DENALI_PHY_870
#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_TSEL_DLY_3
#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__REG DENALI_PHY_870
#define LPDDR4__PHY_RDDATA_EN_OE_DLY_3__FLD LPDDR4__DENALI_PHY_870__PHY_RDDATA_EN_OE_DLY_3
-#define LPDDR4__DENALI_PHY_871_READ_MASK 0x3F07FF0FU
-#define LPDDR4__DENALI_PHY_871_WRITE_MASK 0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_871_READ_MASK 0x3F07FF0FU
+#define LPDDR4__DENALI_PHY_871_WRITE_MASK 0x3F07FF0FU
#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_WIDTH 4U
+#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3_WIDTH 4U
#define LPDDR4__PHY_SW_MASTER_MODE_3__REG DENALI_PHY_871
#define LPDDR4__PHY_SW_MASTER_MODE_3__FLD LPDDR4__DENALI_PHY_871__PHY_SW_MASTER_MODE_3
#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_MASK 0x0007FF00U
-#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_SHIFT 8U
#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3_WIDTH 11U
#define LPDDR4__PHY_MASTER_DELAY_START_3__REG DENALI_PHY_871
#define LPDDR4__PHY_MASTER_DELAY_START_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_START_3
#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_MASK 0x3F000000U
-#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_WIDTH 6U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3_WIDTH 6U
#define LPDDR4__PHY_MASTER_DELAY_STEP_3__REG DENALI_PHY_871
#define LPDDR4__PHY_MASTER_DELAY_STEP_3__FLD LPDDR4__DENALI_PHY_871__PHY_MASTER_DELAY_STEP_3
-#define LPDDR4__DENALI_PHY_872_READ_MASK 0xFF0FFFFFU
-#define LPDDR4__DENALI_PHY_872_WRITE_MASK 0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_872_READ_MASK 0xFF0FFFFFU
+#define LPDDR4__DENALI_PHY_872_WRITE_MASK 0xFF0FFFFFU
#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3_WIDTH 8U
#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__REG DENALI_PHY_872
#define LPDDR4__PHY_MASTER_DELAY_WAIT_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_WAIT_3
@@ -1779,19 +1778,19 @@
#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_3__FLD LPDDR4__DENALI_PHY_872__PHY_MASTER_DELAY_HALF_MEASURE_3
#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_WIDTH 4U
+#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3_WIDTH 4U
#define LPDDR4__PHY_RPTR_UPDATE_3__REG DENALI_PHY_872
#define LPDDR4__PHY_RPTR_UPDATE_3__FLD LPDDR4__DENALI_PHY_872__PHY_RPTR_UPDATE_3
#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3_WIDTH 8U
#define LPDDR4__PHY_WRLVL_DLY_STEP_3__REG DENALI_PHY_872
#define LPDDR4__PHY_WRLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_872__PHY_WRLVL_DLY_STEP_3
-#define LPDDR4__DENALI_PHY_873_READ_MASK 0x1F0F3F0FU
-#define LPDDR4__DENALI_PHY_873_WRITE_MASK 0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_873_READ_MASK 0x1F0F3F0FU
+#define LPDDR4__DENALI_PHY_873_WRITE_MASK 0x1F0F3F0FU
#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_873__PHY_WRLVL_DLY_FINE_STEP_3_WIDTH 4U
@@ -1805,8 +1804,8 @@
#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_WRLVL_RESP_WAIT_CNT_3
#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_WIDTH 4U
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3_WIDTH 4U
#define LPDDR4__PHY_GTLVL_DLY_STEP_3__REG DENALI_PHY_873
#define LPDDR4__PHY_GTLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_DLY_STEP_3
@@ -1816,25 +1815,25 @@
#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__REG DENALI_PHY_873
#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_3__FLD LPDDR4__DENALI_PHY_873__PHY_GTLVL_RESP_WAIT_CNT_3
-#define LPDDR4__DENALI_PHY_874_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_874_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_874_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_874_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3_WIDTH 10U
#define LPDDR4__PHY_GTLVL_BACK_STEP_3__REG DENALI_PHY_874
#define LPDDR4__PHY_GTLVL_BACK_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_BACK_STEP_3
#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3_WIDTH 10U
#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__REG DENALI_PHY_874
#define LPDDR4__PHY_GTLVL_FINAL_STEP_3__FLD LPDDR4__DENALI_PHY_874__PHY_GTLVL_FINAL_STEP_3
-#define LPDDR4__DENALI_PHY_875_READ_MASK 0x0F010FFFU
-#define LPDDR4__DENALI_PHY_875_WRITE_MASK 0x0F010FFFU
+#define LPDDR4__DENALI_PHY_875_READ_MASK 0x0F010FFFU
+#define LPDDR4__DENALI_PHY_875_WRITE_MASK 0x0F010FFFU
#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_WIDTH 8U
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3_WIDTH 8U
#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__REG DENALI_PHY_875
#define LPDDR4__PHY_WDQLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_WDQLVL_DLY_STEP_3
@@ -1846,31 +1845,31 @@
#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3_WOSET 0U
#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__REG DENALI_PHY_875
#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_3__FLD LPDDR4__DENALI_PHY_875__PHY_TOGGLE_PRE_SUPPORT_3
#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_MASK 0x0F000000U
-#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_WIDTH 4U
+#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3_WIDTH 4U
#define LPDDR4__PHY_RDLVL_DLY_STEP_3__REG DENALI_PHY_875
#define LPDDR4__PHY_RDLVL_DLY_STEP_3__FLD LPDDR4__DENALI_PHY_875__PHY_RDLVL_DLY_STEP_3
-#define LPDDR4__DENALI_PHY_876_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_876_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_876_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_876_WRITE_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3_WIDTH 10U
#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__REG DENALI_PHY_876
#define LPDDR4__PHY_RDLVL_MAX_EDGE_3__FLD LPDDR4__DENALI_PHY_876__PHY_RDLVL_MAX_EDGE_3
-#define LPDDR4__DENALI_PHY_877_READ_MASK 0x3F0103FFU
-#define LPDDR4__DENALI_PHY_877_WRITE_MASK 0x3F0103FFU
+#define LPDDR4__DENALI_PHY_877_READ_MASK 0x3F0103FFU
+#define LPDDR4__DENALI_PHY_877_WRITE_MASK 0x3F0103FFU
#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_WIDTH 10U
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3_WIDTH 10U
#define LPDDR4__PHY_RDLVL_DVW_MIN_3__REG DENALI_PHY_877
#define LPDDR4__PHY_RDLVL_DVW_MIN_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_DVW_MIN_3
@@ -1888,8 +1887,8 @@
#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__REG DENALI_PHY_877
#define LPDDR4__PHY_RDLVL_PER_START_OFFSET_3__FLD LPDDR4__DENALI_PHY_877__PHY_RDLVL_PER_START_OFFSET_3
-#define LPDDR4__DENALI_PHY_878_READ_MASK 0x00030703U
-#define LPDDR4__DENALI_PHY_878_WRITE_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_878_READ_MASK 0x00030703U
+#define LPDDR4__DENALI_PHY_878_WRITE_MASK 0x00030703U
#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3_WIDTH 2U
@@ -1897,8 +1896,8 @@
#define LPDDR4__PHY_WRPATH_GATE_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_DISABLE_3
#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_MASK 0x00000700U
-#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_WIDTH 3U
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3_WIDTH 3U
#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__REG DENALI_PHY_878
#define LPDDR4__PHY_WRPATH_GATE_TIMING_3__FLD LPDDR4__DENALI_PHY_878__PHY_WRPATH_GATE_TIMING_3
@@ -1908,8 +1907,8 @@
#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__REG DENALI_PHY_878
#define LPDDR4__PHY_DATA_DC_INIT_DISABLE_3__FLD LPDDR4__DENALI_PHY_878__PHY_DATA_DC_INIT_DISABLE_3
-#define LPDDR4__DENALI_PHY_879_READ_MASK 0x07FF03FFU
-#define LPDDR4__DENALI_PHY_879_WRITE_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_879_READ_MASK 0x07FF03FFU
+#define LPDDR4__DENALI_PHY_879_WRITE_MASK 0x07FF03FFU
#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQS_INIT_SLV_DELAY_3_WIDTH 10U
@@ -1922,8 +1921,8 @@
#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__REG DENALI_PHY_879
#define LPDDR4__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3__FLD LPDDR4__DENALI_PHY_879__PHY_DATA_DC_DQ_INIT_SLV_DELAY_3
-#define LPDDR4__DENALI_PHY_880_READ_MASK 0xFFFF0101U
-#define LPDDR4__DENALI_PHY_880_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_880_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_880_WRITE_MASK 0xFFFF0101U
#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_880__PHY_DATA_DC_WRLVL_ENABLE_3_WIDTH 1U
@@ -1952,11 +1951,11 @@
#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__REG DENALI_PHY_880
#define LPDDR4__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3__FLD LPDDR4__DENALI_PHY_880__PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3
-#define LPDDR4__DENALI_PHY_881_READ_MASK 0x001F3F7FU
-#define LPDDR4__DENALI_PHY_881_WRITE_MASK 0x001F3F7FU
+#define LPDDR4__DENALI_PHY_881_READ_MASK 0x001F3F7FU
+#define LPDDR4__DENALI_PHY_881_WRITE_MASK 0x001F3F7FU
#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_WIDTH 7U
+#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3_WIDTH 7U
#define LPDDR4__PHY_WDQ_OSC_DELTA_3__REG DENALI_PHY_881
#define LPDDR4__PHY_WDQ_OSC_DELTA_3__FLD LPDDR4__DENALI_PHY_881__PHY_WDQ_OSC_DELTA_3
@@ -1967,29 +1966,29 @@
#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_3__FLD LPDDR4__DENALI_PHY_881__PHY_MEAS_DLY_STEP_ENABLE_3
#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_WIDTH 5U
+#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3_WIDTH 5U
#define LPDDR4__PHY_RDDATA_EN_DLY_3__REG DENALI_PHY_881
#define LPDDR4__PHY_RDDATA_EN_DLY_3__FLD LPDDR4__DENALI_PHY_881__PHY_RDDATA_EN_DLY_3
-#define LPDDR4__DENALI_PHY_882_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_882_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_882_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_882_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_WIDTH 32U
+#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3_WIDTH 32U
#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__REG DENALI_PHY_882
#define LPDDR4__PHY_DQ_DM_SWIZZLE0_3__FLD LPDDR4__DENALI_PHY_882__PHY_DQ_DM_SWIZZLE0_3
-#define LPDDR4__DENALI_PHY_883_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_883_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_883_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_883_WRITE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_SHIFT 0U
-#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_WIDTH 4U
+#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_SHIFT 0U
+#define LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3_WIDTH 4U
#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__REG DENALI_PHY_883
#define LPDDR4__PHY_DQ_DM_SWIZZLE1_3__FLD LPDDR4__DENALI_PHY_883__PHY_DQ_DM_SWIZZLE1_3
-#define LPDDR4__DENALI_PHY_884_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_884_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_884_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ0_SLAVE_DELAY_3_WIDTH 11U
@@ -2002,8 +2001,8 @@
#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__REG DENALI_PHY_884
#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_884__PHY_CLK_WRDQ1_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_885_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_885_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_885_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_885_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ2_SLAVE_DELAY_3_WIDTH 11U
@@ -2016,8 +2015,8 @@
#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__REG DENALI_PHY_885
#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_885__PHY_CLK_WRDQ3_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_886_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_886_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_886_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_886_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ4_SLAVE_DELAY_3_WIDTH 11U
@@ -2030,8 +2029,8 @@
#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__REG DENALI_PHY_886
#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_886__PHY_CLK_WRDQ5_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_887_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_887_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_887_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_887_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ6_SLAVE_DELAY_3_WIDTH 11U
@@ -2044,8 +2043,8 @@
#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__REG DENALI_PHY_887
#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_887__PHY_CLK_WRDQ7_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_888_READ_MASK 0x03FF07FFU
-#define LPDDR4__DENALI_PHY_888_WRITE_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_888_READ_MASK 0x03FF07FFU
+#define LPDDR4__DENALI_PHY_888_WRITE_MASK 0x03FF07FFU
#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_888__PHY_CLK_WRDM_SLAVE_DELAY_3_WIDTH 11U
@@ -2058,8 +2057,8 @@
#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__REG DENALI_PHY_888
#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_888__PHY_CLK_WRDQS_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_889_READ_MASK 0x0003FF03U
-#define LPDDR4__DENALI_PHY_889_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_889_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PHY_889_WRITE_MASK 0x0003FF03U
#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_889__PHY_WRLVL_THRESHOLD_ADJUST_3_WIDTH 2U
@@ -2072,8 +2071,8 @@
#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__REG DENALI_PHY_889
#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_889__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_890_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_890_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_890_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3_WIDTH 10U
@@ -2086,8 +2085,8 @@
#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__REG DENALI_PHY_890
#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_890__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_891_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_891_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_891_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3_WIDTH 10U
@@ -2100,8 +2099,8 @@
#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__REG DENALI_PHY_891
#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_891__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_892_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_892_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_892_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3_WIDTH 10U
@@ -2114,8 +2113,8 @@
#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__REG DENALI_PHY_892
#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_892__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_893_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_893_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_893_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3_WIDTH 10U
@@ -2128,8 +2127,8 @@
#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__REG DENALI_PHY_893
#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_893__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_894_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_894_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_894_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3_WIDTH 10U
@@ -2142,8 +2141,8 @@
#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__REG DENALI_PHY_894
#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_894__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_895_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_895_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_895_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3_WIDTH 10U
@@ -2156,8 +2155,8 @@
#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__REG DENALI_PHY_895
#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_895__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_896_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_896_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_896_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_896_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3_WIDTH 10U
@@ -2170,8 +2169,8 @@
#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__REG DENALI_PHY_896
#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_896__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_897_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_897_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_897_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_897_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_897__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3_WIDTH 10U
@@ -2184,8 +2183,8 @@
#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__REG DENALI_PHY_897
#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_897__PHY_RDDQS_DM_RISE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_898_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_898_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_898_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_898_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_898__PHY_RDDQS_DM_FALL_SLAVE_DELAY_3_WIDTH 10U
@@ -2198,8 +2197,8 @@
#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__REG DENALI_PHY_898
#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_898__PHY_RDDQS_GATE_SLAVE_DELAY_3
-#define LPDDR4__DENALI_PHY_899_READ_MASK 0x03FF070FU
-#define LPDDR4__DENALI_PHY_899_WRITE_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_899_READ_MASK 0x03FF070FU
+#define LPDDR4__DENALI_PHY_899_WRITE_MASK 0x03FF070FU
#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3_WIDTH 4U
@@ -2207,8 +2206,8 @@
#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_3__FLD LPDDR4__DENALI_PHY_899__PHY_RDDQS_LATENCY_ADJUST_3
#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_MASK 0x00000700U
-#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_WIDTH 3U
+#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3_WIDTH 3U
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__REG DENALI_PHY_899
#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRITE_PATH_LAT_ADD_3
@@ -2218,8 +2217,8 @@
#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__REG DENALI_PHY_899
#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3__FLD LPDDR4__DENALI_PHY_899__PHY_WRLVL_DELAY_EARLY_THRESHOLD_3
-#define LPDDR4__DENALI_PHY_900_READ_MASK 0x000103FFU
-#define LPDDR4__DENALI_PHY_900_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_900_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_900_WRITE_MASK 0x000103FFU
#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_900__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3_WIDTH 10U
@@ -2234,8 +2233,8 @@
#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__REG DENALI_PHY_900
#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_3__FLD LPDDR4__DENALI_PHY_900__PHY_WRLVL_EARLY_FORCE_ZERO_3
-#define LPDDR4__DENALI_PHY_901_READ_MASK 0x000F03FFU
-#define LPDDR4__DENALI_PHY_901_WRITE_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_901_READ_MASK 0x000F03FFU
+#define LPDDR4__DENALI_PHY_901_WRITE_MASK 0x000F03FFU
#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_901__PHY_GTLVL_RDDQS_SLV_DLY_START_3_WIDTH 10U
@@ -2248,8 +2247,8 @@
#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__REG DENALI_PHY_901
#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_3__FLD LPDDR4__DENALI_PHY_901__PHY_GTLVL_LAT_ADJ_START_3
-#define LPDDR4__DENALI_PHY_902_READ_MASK 0x010F07FFU
-#define LPDDR4__DENALI_PHY_902_WRITE_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_902_READ_MASK 0x010F07FFU
+#define LPDDR4__DENALI_PHY_902_WRITE_MASK 0x010F07FFU
#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3_WIDTH 11U
@@ -2257,29 +2256,29 @@
#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_WDQLVL_DQDM_SLV_DLY_START_3
#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_WIDTH 4U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3_WIDTH 4U
#define LPDDR4__PHY_NTP_WRLAT_START_3__REG DENALI_PHY_902
#define LPDDR4__PHY_NTP_WRLAT_START_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_WRLAT_START_3
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_SHIFT 24U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WIDTH 1U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOCLR 0U
-#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOSET 0U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_SHIFT 24U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WIDTH 1U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOCLR 0U
+#define LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3_WOSET 0U
#define LPDDR4__PHY_NTP_PASS_3__REG DENALI_PHY_902
#define LPDDR4__PHY_NTP_PASS_3__FLD LPDDR4__DENALI_PHY_902__PHY_NTP_PASS_3
-#define LPDDR4__DENALI_PHY_903_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_903_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_903_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_903_WRITE_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3_WIDTH 10U
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__REG DENALI_PHY_903
#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3__FLD LPDDR4__DENALI_PHY_903__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3
-#define LPDDR4__DENALI_PHY_904_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_904_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_904_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_904_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQS_CLK_ADJUST_3_WIDTH 8U
@@ -2304,8 +2303,8 @@
#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__REG DENALI_PHY_904
#define LPDDR4__PHY_DATA_DC_DQ2_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_904__PHY_DATA_DC_DQ2_CLK_ADJUST_3
-#define LPDDR4__DENALI_PHY_905_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_905_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_905_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_905_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ3_CLK_ADJUST_3_WIDTH 8U
@@ -2330,8 +2329,8 @@
#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__REG DENALI_PHY_905
#define LPDDR4__PHY_DATA_DC_DQ6_CLK_ADJUST_3__FLD LPDDR4__DENALI_PHY_905__PHY_DATA_DC_DQ6_CLK_ADJUST_3
-#define LPDDR4__DENALI_PHY_906_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_906_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_906_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_906_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_906__PHY_DATA_DC_DQ7_CLK_ADJUST_3_WIDTH 8U
@@ -2350,23 +2349,23 @@
#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__REG DENALI_PHY_906
#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_3__FLD LPDDR4__DENALI_PHY_906__PHY_DSLICE_PAD_BOOSTPN_SETTING_3
-#define LPDDR4__DENALI_PHY_907_READ_MASK 0x0003033FU
-#define LPDDR4__DENALI_PHY_907_WRITE_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_907_READ_MASK 0x0003033FU
+#define LPDDR4__DENALI_PHY_907_WRITE_MASK 0x0003033FU
#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_SHIFT 0U
#define LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3_WIDTH 6U
#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__REG DENALI_PHY_907
#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_3__FLD LPDDR4__DENALI_PHY_907__PHY_DSLICE_PAD_RX_CTLE_SETTING_3
-#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_MASK 0x00000300U
-#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_SHIFT 8U
-#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_MASK 0x00000300U
+#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_SHIFT 8U
+#define LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3_WIDTH 2U
#define LPDDR4__PHY_DQ_FFE_3__REG DENALI_PHY_907
#define LPDDR4__PHY_DQ_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQ_FFE_3
-#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_SHIFT 16U
-#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_WIDTH 2U
+#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_SHIFT 16U
+#define LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3_WIDTH 2U
#define LPDDR4__PHY_DQS_FFE_3__REG DENALI_PHY_907
#define LPDDR4__PHY_DQS_FFE_3__FLD LPDDR4__DENALI_PHY_907__PHY_DQS_FFE_3
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h
new file mode 100644
index 0000000..4e33d04
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h
@@ -0,0 +1,7792 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+
+#define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_0__START_SHIFT 0U
+#define LPDDR4__DENALI_CTL_0__START_WIDTH 1U
+#define LPDDR4__DENALI_CTL_0__START_WOCLR 0U
+#define LPDDR4__DENALI_CTL_0__START_WOSET 0U
+#define LPDDR4__START__REG DENALI_CTL_0
+#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
+
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U
+#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
+#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
+
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U
+#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
+#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
+
+#define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U
+#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
+#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
+
+#define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U
+#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
+#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
+
+#define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U
+#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U
+#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U
+#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
+
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U
+#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
+#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U
+#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
+#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
+
+#define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U
+#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
+#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
+
+#define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U
+#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
+#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
+
+#define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U
+#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
+#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
+
+#define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U
+#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
+#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
+
+#define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U
+#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
+#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
+
+#define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U
+#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
+#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
+
+#define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U
+#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
+#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
+
+#define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U
+#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
+#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
+
+#define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U
+#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
+#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
+
+#define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U
+#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
+#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
+
+#define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U
+#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
+#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
+
+#define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U
+#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
+#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
+
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U
+#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
+#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_CTL_19_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U
+#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
+#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET 0U
+#define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19
+#define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS
+
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET 0U
+#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19
+#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT
+
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET 0U
+#define LPDDR4__ODT_VALUE__REG DENALI_CTL_19
+#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE
+
+#define LPDDR4__DENALI_CTL_20_READ_MASK 0x03013F01U
+#define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x03013F01U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
+
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT 8U
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH 6U
+#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20
+#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR
+
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET 0U
+#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE
+
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH 2U
+#define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20
+#define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT
+
+#define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F1F03U
+#define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F1F03U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH 2U
+#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U
+#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U
+#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH 5U
+#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2
+
+#define LPDDR4__DENALI_CTL_22_READ_MASK 0x00030303U
+#define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x00030303U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
+
+#define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U
+#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
+#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
+
+#define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U
+#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
+#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
+
+#define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET 0U
+#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25
+#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0
+
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK 0xFFFFFF00U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH 24U
+#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25
+#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1
+
+#define LPDDR4__DENALI_CTL_26_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH 8U
+#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26
+#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2
+
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT 8U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH 8U
+#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26
+#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3
+
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET 0U
+#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26
+#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE
+
+#define LPDDR4__DENALI_CTL_27_READ_MASK 0xFF0F7FFFU
+#define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFF0F7FFFU
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK 0x00007FFFU
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH 15U
+#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD
+
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT 16U
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH 4U
+#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27
+#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES
+
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH 8U
+#define LPDDR4__TOSCO_F0__REG DENALI_CTL_27
+#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0
+
+#define LPDDR4__DENALI_CTL_28_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_28_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH 8U
+#define LPDDR4__TOSCO_F1__REG DENALI_CTL_28
+#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1
+
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH 8U
+#define LPDDR4__TOSCO_F2__REG DENALI_CTL_28
+#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH 8U
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH 8U
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_29_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_29_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH 8U
+#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 8U
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH 16U
+#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29
+#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT
+
+#define LPDDR4__DENALI_CTL_30_READ_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30_WRITE_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT 0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH 1U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR 0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET 0U
+#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30
+#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST
+
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH 16U
+#define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30
+#define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0
+
+#define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH 16U
+#define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31
+#define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0
+
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH 16U
+#define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31
+#define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0
+
+#define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH 16U
+#define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32
+#define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0
+
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH 16U
+#define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32
+#define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1
+
+#define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH 16U
+#define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33
+#define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1
+
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH 16U
+#define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33
+#define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1
+
+#define LPDDR4__DENALI_CTL_34_READ_MASK 0x7F7FFFFFU
+#define LPDDR4__DENALI_CTL_34_WRITE_MASK 0x7F7FFFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH 16U
+#define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34
+#define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1
+
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH 7U
+#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34
+#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH 7U
+#define LPDDR4__WRLAT_F0__REG DENALI_CTL_34
+#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_35_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_35_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH 7U
+#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35
+#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH 7U
+#define LPDDR4__WRLAT_F1__REG DENALI_CTL_35
+#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH 7U
+#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35
+#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH 7U
+#define LPDDR4__WRLAT_F2__REG DENALI_CTL_35
+#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_36_READ_MASK 0x00FF1F07U
+#define LPDDR4__DENALI_CTL_36_WRITE_MASK 0x00FF1F07U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH 3U
+#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36
+#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL
+
+#define LPDDR4__DENALI_CTL_36__TCCD_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH 5U
+#define LPDDR4__TCCD__REG DENALI_CTL_36
+#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD
+
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH 8U
+#define LPDDR4__TRRD_F0__REG DENALI_CTL_36
+#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0
+
+#define LPDDR4__DENALI_CTL_37_READ_MASK 0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_37_WRITE_MASK 0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK 0x000001FFU
+#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH 9U
+#define LPDDR4__TRC_F0__REG DENALI_CTL_37
+#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0
+
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH 8U
+#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37
+#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0
+
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH 6U
+#define LPDDR4__TWTR_F0__REG DENALI_CTL_37
+#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0
+
+#define LPDDR4__DENALI_CTL_38_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_38_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH 8U
+#define LPDDR4__TRP_F0__REG DENALI_CTL_38
+#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0
+
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH 9U
+#define LPDDR4__TFAW_F0__REG DENALI_CTL_38
+#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0
+
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH 8U
+#define LPDDR4__TRRD_F1__REG DENALI_CTL_38
+#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1
+
+#define LPDDR4__DENALI_CTL_39_READ_MASK 0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_39_WRITE_MASK 0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK 0x000001FFU
+#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH 9U
+#define LPDDR4__TRC_F1__REG DENALI_CTL_39
+#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1
+
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH 8U
+#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39
+#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1
+
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH 6U
+#define LPDDR4__TWTR_F1__REG DENALI_CTL_39
+#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1
+
+#define LPDDR4__DENALI_CTL_40_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_40_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH 8U
+#define LPDDR4__TRP_F1__REG DENALI_CTL_40
+#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1
+
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH 9U
+#define LPDDR4__TFAW_F1__REG DENALI_CTL_40
+#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1
+
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH 8U
+#define LPDDR4__TRRD_F2__REG DENALI_CTL_40
+#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2
+
+#define LPDDR4__DENALI_CTL_41_READ_MASK 0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_41_WRITE_MASK 0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK 0x000001FFU
+#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH 9U
+#define LPDDR4__TRC_F2__REG DENALI_CTL_41
+#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2
+
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH 8U
+#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41
+#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2
+
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH 6U
+#define LPDDR4__TWTR_F2__REG DENALI_CTL_41
+#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2
+
+#define LPDDR4__DENALI_CTL_42_READ_MASK 0x3F01FFFFU
+#define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x3F01FFFFU
+#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH 8U
+#define LPDDR4__TRP_F2__REG DENALI_CTL_42
+#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2
+
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK 0x0001FF00U
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH 9U
+#define LPDDR4__TFAW_F2__REG DENALI_CTL_42
+#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2
+
+#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT 24U
+#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH 6U
+#define LPDDR4__TCCDMW__REG DENALI_CTL_42
+#define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW
+
+#define LPDDR4__DENALI_CTL_43_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_43_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH 8U
+#define LPDDR4__TRTP_F0__REG DENALI_CTL_43
+#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0
+
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH 8U
+#define LPDDR4__TMRD_F0__REG DENALI_CTL_43
+#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0
+
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH 8U
+#define LPDDR4__TMOD_F0__REG DENALI_CTL_43
+#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0
+
+#define LPDDR4__DENALI_CTL_44_READ_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_44_WRITE_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH 17U
+#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44
+#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0
+
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH 5U
+#define LPDDR4__TCKE_F0__REG DENALI_CTL_44
+#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0
+
+#define LPDDR4__DENALI_CTL_45_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH 8U
+#define LPDDR4__TCKESR_F0__REG DENALI_CTL_45
+#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0
+
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH 8U
+#define LPDDR4__TRTP_F1__REG DENALI_CTL_45
+#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1
+
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH 8U
+#define LPDDR4__TMRD_F1__REG DENALI_CTL_45
+#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1
+
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH 8U
+#define LPDDR4__TMOD_F1__REG DENALI_CTL_45
+#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1
+
+#define LPDDR4__DENALI_CTL_46_READ_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_46_WRITE_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH 17U
+#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46
+#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1
+
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH 5U
+#define LPDDR4__TCKE_F1__REG DENALI_CTL_46
+#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1
+
+#define LPDDR4__DENALI_CTL_47_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_47_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH 8U
+#define LPDDR4__TCKESR_F1__REG DENALI_CTL_47
+#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1
+
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH 8U
+#define LPDDR4__TRTP_F2__REG DENALI_CTL_47
+#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2
+
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH 8U
+#define LPDDR4__TMRD_F2__REG DENALI_CTL_47
+#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2
+
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH 8U
+#define LPDDR4__TMOD_F2__REG DENALI_CTL_47
+#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2
+
+#define LPDDR4__DENALI_CTL_48_READ_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH 17U
+#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48
+#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2
+
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH 5U
+#define LPDDR4__TCKE_F2__REG DENALI_CTL_48
+#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2
+
+#define LPDDR4__DENALI_CTL_49_READ_MASK 0x070707FFU
+#define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x070707FFU
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH 8U
+#define LPDDR4__TCKESR_F2__REG DENALI_CTL_49
+#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2
+
+#define LPDDR4__DENALI_CTL_49__TPPD_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH 3U
+#define LPDDR4__TPPD__REG DENALI_CTL_49
+#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD
+
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT 16U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH 3U
+#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49
+#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4
+
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT 24U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH 3U
+#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49
+#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5
+
+#define LPDDR4__DENALI_CTL_50_READ_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_50_WRITE_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT 0U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET 0U
+#define LPDDR4__WRITEINTERP__REG DENALI_CTL_50
+#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP
+
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH 8U
+#define LPDDR4__TRCD_F0__REG DENALI_CTL_50
+#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0
+
+#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH 8U
+#define LPDDR4__TWR_F0__REG DENALI_CTL_50
+#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0
+
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH 8U
+#define LPDDR4__TRCD_F1__REG DENALI_CTL_50
+#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1
+
+#define LPDDR4__DENALI_CTL_51_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH 8U
+#define LPDDR4__TWR_F1__REG DENALI_CTL_51
+#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1
+
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH 8U
+#define LPDDR4__TRCD_F2__REG DENALI_CTL_51
+#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2
+
+#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH 8U
+#define LPDDR4__TWR_F2__REG DENALI_CTL_51
+#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2
+
+#define LPDDR4__DENALI_CTL_51__TMRR_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT 24U
+#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH 4U
+#define LPDDR4__TMRR__REG DENALI_CTL_51
+#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR
+
+#define LPDDR4__DENALI_CTL_52_READ_MASK 0x3F03FF1FU
+#define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x3F03FF1FU
+#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT 0U
+#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH 5U
+#define LPDDR4__TCACKEL__REG DENALI_CTL_52
+#define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL
+
+#define LPDDR4__DENALI_CTL_52__TCAENT_MASK 0x0003FF00U
+#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH 10U
+#define LPDDR4__TCAENT__REG DENALI_CTL_52
+#define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT
+
+#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH 6U
+#define LPDDR4__TCAMRD__REG DENALI_CTL_52
+#define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD
+
+#define LPDDR4__DENALI_CTL_53_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_53_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH 5U
+#define LPDDR4__TCAEXT__REG DENALI_CTL_53
+#define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT
+
+#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH 5U
+#define LPDDR4__TCACKEH__REG DENALI_CTL_53
+#define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH
+
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH 5U
+#define LPDDR4__TMRZ_F0__REG DENALI_CTL_53
+#define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0
+
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH 5U
+#define LPDDR4__TMRZ_F1__REG DENALI_CTL_53
+#define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1
+
+#define LPDDR4__DENALI_CTL_54_READ_MASK 0x0101011FU
+#define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x0101011FU
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH 5U
+#define LPDDR4__TMRZ_F2__REG DENALI_CTL_54
+#define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2
+
+#define LPDDR4__DENALI_CTL_54__AP_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_54__AP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_54__AP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_54__AP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_54__AP_WOSET 0U
+#define LPDDR4__AP__REG DENALI_CTL_54
+#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP
+
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT 16U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET 0U
+#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54
+#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP
+
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET 0U
+#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54
+#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT
+
+#define LPDDR4__DENALI_CTL_55_READ_MASK 0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_55_WRITE_MASK 0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH 8U
+#define LPDDR4__TDAL_F0__REG DENALI_CTL_55
+#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0
+
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH 8U
+#define LPDDR4__TDAL_F1__REG DENALI_CTL_55
+#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1
+
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH 8U
+#define LPDDR4__TDAL_F2__REG DENALI_CTL_55
+#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2
+
+#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH 5U
+#define LPDDR4__BSTLEN__REG DENALI_CTL_55
+#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN
+
+#define LPDDR4__DENALI_CTL_56_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_56_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH 8U
+#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0
+
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH 8U
+#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0
+
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH 8U
+#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0
+
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH 8U
+#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56
+#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1
+
+#define LPDDR4__DENALI_CTL_57_READ_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x0301FFFFU
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH 8U
+#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57
+#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1
+
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH 8U
+#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57
+#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1
+
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET 0U
+#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57
+#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT 24U
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH 2U
+#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57
+#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6
+
+#define LPDDR4__DENALI_CTL_58_READ_MASK 0x0101017FU
+#define LPDDR4__DENALI_CTL_58_WRITE_MASK 0x0101017FU
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT 0U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH 7U
+#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58
+#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7
+
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET 0U
+#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58
+#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN
+
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT 16U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH 1U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR 0U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET 0U
+#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58
+#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8
+
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT 24U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH 1U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR 0U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET 0U
+#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58
+#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM
+
+#define LPDDR4__DENALI_CTL_59_READ_MASK 0x07010100U
+#define LPDDR4__DENALI_CTL_59_WRITE_MASK 0x07010100U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH 1U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR 0U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET 0U
+#define LPDDR4__AREFRESH__REG DENALI_CTL_59
+#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH
+
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET 0U
+#define LPDDR4__AREF_STATUS__REG DENALI_CTL_59
+#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS
+
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET 0U
+#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59
+#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE
+
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT 24U
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH 3U
+#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59
+#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9
+
+#define LPDDR4__DENALI_CTL_60_READ_MASK 0x0003FF3FU
+#define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x0003FF3FU
+#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 0U
+#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH
+
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH 10U
+#define LPDDR4__TRFC_F0__REG DENALI_CTL_60
+#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0
+
+#define LPDDR4__DENALI_CTL_61_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH 20U
+#define LPDDR4__TREF_F0__REG DENALI_CTL_61
+#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0
+
+#define LPDDR4__DENALI_CTL_62_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH 10U
+#define LPDDR4__TRFC_F1__REG DENALI_CTL_62
+#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1
+
+#define LPDDR4__DENALI_CTL_63_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH 20U
+#define LPDDR4__TREF_F1__REG DENALI_CTL_63
+#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1
+
+#define LPDDR4__DENALI_CTL_64_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_64_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH 10U
+#define LPDDR4__TRFC_F2__REG DENALI_CTL_64
+#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2
+
+#define LPDDR4__DENALI_CTL_65_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH 20U
+#define LPDDR4__TREF_F2__REG DENALI_CTL_65
+#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2
+
+#define LPDDR4__DENALI_CTL_66_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH 20U
+#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66
+#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL
+
+#define LPDDR4__DENALI_CTL_67_READ_MASK 0x03FF0101U
+#define LPDDR4__DENALI_CTL_67_WRITE_MASK 0x03FF0101U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET 0U
+#define LPDDR4__PBR_EN__REG DENALI_CTL_67
+#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN
+
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT 8U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH 1U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR 0U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET 0U
+#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67
+#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER
+
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH 10U
+#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67
+#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0
+
+#define LPDDR4__DENALI_CTL_68_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH 16U
+#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68
+#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0
+
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH 10U
+#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68
+#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1
+
+#define LPDDR4__DENALI_CTL_69_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_69_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH 16U
+#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69
+#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1
+
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH 10U
+#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69
+#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2
+
+#define LPDDR4__DENALI_CTL_70_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_70_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH 16U
+#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70
+#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2
+
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH 16U
+#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70
+#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT
+
+#define LPDDR4__DENALI_CTL_71_READ_MASK 0x1F1F010FU
+#define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x1F1F010FU
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH 4U
+#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71
+#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY
+
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET 0U
+#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71
+#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN
+
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_71
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_72_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_72_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH 16U
+#define LPDDR4__TPDEX_F0__REG DENALI_CTL_72
+#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0
+
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH 16U
+#define LPDDR4__TPDEX_F1__REG DENALI_CTL_72
+#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1
+
+#define LPDDR4__DENALI_CTL_73_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_73_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH 16U
+#define LPDDR4__TPDEX_F2__REG DENALI_CTL_73
+#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2
+
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH 8U
+#define LPDDR4__TMRRI_F0__REG DENALI_CTL_73
+#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0
+
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH 8U
+#define LPDDR4__TMRRI_F1__REG DENALI_CTL_73
+#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1
+
+#define LPDDR4__DENALI_CTL_74_READ_MASK 0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH 8U
+#define LPDDR4__TMRRI_F2__REG DENALI_CTL_74
+#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2
+
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH 5U
+#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74
+#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0
+
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH 5U
+#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74
+#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0
+
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH 5U
+#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74
+#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0
+
+#define LPDDR4__DENALI_CTL_75_READ_MASK 0x1F010F1FU
+#define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x1F010F1FU
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH 5U
+#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75
+#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0
+
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH 4U
+#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75
+#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0
+
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET 0U
+#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75
+#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0
+
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH 5U
+#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75
+#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1
+
+#define LPDDR4__DENALI_CTL_76_READ_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH 5U
+#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76
+#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1
+
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH 5U
+#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76
+#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1
+
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH 5U
+#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76
+#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1
+
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH 4U
+#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76
+#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1
+
+#define LPDDR4__DENALI_CTL_77_READ_MASK 0x1F1F1F01U
+#define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x1F1F1F01U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET 0U
+#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77
+#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1
+
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH 5U
+#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77
+#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2
+
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH 5U
+#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77
+#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2
+
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH 5U
+#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77
+#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2
+
+#define LPDDR4__DENALI_CTL_78_READ_MASK 0x00010F1FU
+#define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x00010F1FU
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH 5U
+#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78
+#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2
+
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH 4U
+#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78
+#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2
+
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET 0U
+#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78
+#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2
+
+#define LPDDR4__DENALI_CTL_79_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_79_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH 16U
+#define LPDDR4__TXSR_F0__REG DENALI_CTL_79
+#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0
+
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH 16U
+#define LPDDR4__TXSNR_F0__REG DENALI_CTL_79
+#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0
+
+#define LPDDR4__DENALI_CTL_80_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_80_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH 16U
+#define LPDDR4__TXSR_F1__REG DENALI_CTL_80
+#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1
+
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH 16U
+#define LPDDR4__TXSNR_F1__REG DENALI_CTL_80
+#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1
+
+#define LPDDR4__DENALI_CTL_81_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_81_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH 16U
+#define LPDDR4__TXSR_F2__REG DENALI_CTL_81
+#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2
+
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH 16U
+#define LPDDR4__TXSNR_F2__REG DENALI_CTL_81
+#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2
+
+#define LPDDR4__DENALI_CTL_82_READ_MASK 0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_82_WRITE_MASK 0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH 5U
+#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82
+#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0
+
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH 5U
+#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82
+#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0
+
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH 5U
+#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82
+#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0
+
+#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH 8U
+#define LPDDR4__TSR_F0__REG DENALI_CTL_82
+#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0
+
+#define LPDDR4__DENALI_CTL_83_READ_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH 3U
+#define LPDDR4__TESCKE_F0__REG DENALI_CTL_83
+#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0
+
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH 5U
+#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83
+#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0
+
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH 5U
+#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83
+#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0
+
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH 5U
+#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83
+#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0
+
+#define LPDDR4__DENALI_CTL_84_READ_MASK 0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_84_WRITE_MASK 0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH 5U
+#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84
+#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1
+
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH 5U
+#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84
+#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1
+
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH 5U
+#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84
+#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1
+
+#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH 8U
+#define LPDDR4__TSR_F1__REG DENALI_CTL_84
+#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1
+
+#define LPDDR4__DENALI_CTL_85_READ_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH 3U
+#define LPDDR4__TESCKE_F1__REG DENALI_CTL_85
+#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1
+
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH 5U
+#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85
+#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1
+
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH 5U
+#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85
+#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1
+
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH 5U
+#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85
+#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1
+
+#define LPDDR4__DENALI_CTL_86_READ_MASK 0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_86_WRITE_MASK 0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH 5U
+#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86
+#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2
+
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH 5U
+#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86
+#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2
+
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH 5U
+#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86
+#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2
+
+#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH 8U
+#define LPDDR4__TSR_F2__REG DENALI_CTL_86
+#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2
+
+#define LPDDR4__DENALI_CTL_87_READ_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_87_WRITE_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH 3U
+#define LPDDR4__TESCKE_F2__REG DENALI_CTL_87
+#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2
+
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH 5U
+#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87
+#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2
+
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH 5U
+#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87
+#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2
+
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH 5U
+#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87
+#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2
+
+#define LPDDR4__DENALI_CTL_88_READ_MASK 0x07010101U
+#define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x07010101U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET 0U
+#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88
+#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT 8U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH 1U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR 0U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET 0U
+#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88
+#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10
+
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH 1U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR 0U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET 0U
+#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88
+#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH
+
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT 24U
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH 3U
+#define LPDDR4__CKE_DELAY__REG DENALI_CTL_88
+#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY
+
+#define LPDDR4__DENALI_CTL_89_READ_MASK 0x01010300U
+#define LPDDR4__DENALI_CTL_89_WRITE_MASK 0x01010300U
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT 0U
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH 5U
+#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89
+#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11
+
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH 2U
+#define LPDDR4__DFS_STATUS__REG DENALI_CTL_89
+#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS
+
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET 0U
+#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89
+#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET 0U
+#define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89
+#define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN
+
+#define LPDDR4__DENALI_CTL_90_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_90_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET 0U
+#define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90
+#define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN
+
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET 0U
+#define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90
+#define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN
+
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET 0U
+#define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90
+#define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN
+
+#define LPDDR4__DENALI_CTL_91_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_91_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_92_READ_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x0707FFFFU
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT 16U
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH 3U
+#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92
+#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG
+
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT 24U
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH 3U
+#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92
+#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12
+
+#define LPDDR4__DENALI_CTL_93_READ_MASK 0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_93_WRITE_MASK 0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT 0U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH 3U
+#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13
+
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT 8U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH 8U
+#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14
+
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT 16U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH 8U
+#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15
+
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT 24U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH 8U
+#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93
+#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16
+
+#define LPDDR4__DENALI_CTL_94_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_94_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_94
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_95_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_95_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_96
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_97
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_99
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_100_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_100_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_101_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_102_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0
+
+#define LPDDR4__DENALI_CTL_103_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_104_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_105_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_106_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_107_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_108_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH 20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0
+
+#define LPDDR4__DENALI_CTL_109_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1
+
+#define LPDDR4__DENALI_CTL_110_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_114_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_115_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH 20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1
+
+#define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2
+
+#define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_118_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_121_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_122_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_122_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH 20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2
+
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT 24U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH 1U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR 0U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET 0U
+#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122
+#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF
+
+#define LPDDR4__DENALI_CTL_123_READ_MASK 0x00010103U
+#define LPDDR4__DENALI_CTL_123_WRITE_MASK 0x00010103U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123
+#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_123
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1
+
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
+
+#define LPDDR4__DENALI_CTL_124_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_124_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_125_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_125_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_126
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_127
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_128_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_128_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT 16U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH 1U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR 0U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET 0U
+#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128
+#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL
+
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT 24U
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH 3U
+#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128
+#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND
+
+#define LPDDR4__DENALI_CTL_129_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_129_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT 0U
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH 8U
+#define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129
+#define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW
+
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH 17U
+#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129
+#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS
+
+#define LPDDR4__DENALI_CTL_130_READ_MASK 0x01030107U
+#define LPDDR4__DENALI_CTL_130_WRITE_MASK 0x01030107U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH 3U
+#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130
+#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS
+
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET 0U
+#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130
+#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS
+
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH 2U
+#define LPDDR4__PPR_STATUS__REG DENALI_CTL_130
+#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS
+
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT 24U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH 1U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR 0U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET 0U
+#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130
+#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL
+
+#define LPDDR4__DENALI_CTL_131_READ_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_CTL_131_WRITE_MASK 0xFFFFFF03U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH 2U
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE
+
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH 8U
+#define LPDDR4__CKSRE_F0__REG DENALI_CTL_131
+#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0
+
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH 8U
+#define LPDDR4__CKSRX_F0__REG DENALI_CTL_131
+#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0
+
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH 8U
+#define LPDDR4__CKSRE_F1__REG DENALI_CTL_131
+#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1
+
+#define LPDDR4__DENALI_CTL_132_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH 8U
+#define LPDDR4__CKSRX_F1__REG DENALI_CTL_132
+#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1
+
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH 8U
+#define LPDDR4__CKSRE_F2__REG DENALI_CTL_132
+#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2
+
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH 8U
+#define LPDDR4__CKSRX_F2__REG DENALI_CTL_132
+#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2
+
+#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH 7U
+#define LPDDR4__LP_CMD__REG DENALI_CTL_132
+#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD
+
+#define LPDDR4__DENALI_CTL_133_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_133_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_134_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_135_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_135_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH 4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_136_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_137_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_137_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_137
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH 4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137
+#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139_READ_MASK 0x3F0F0F0FU
+#define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x3F0F0F0FU
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_139
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH 4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH 6U
+#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139
+#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN
+
+#define LPDDR4__DENALI_CTL_140_READ_MASK 0x070FFF01U
+#define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x070FFF01U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET 0U
+#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140
+#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN
+
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH 12U
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT 24U
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH 3U
+#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140
+#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP
+
+#define LPDDR4__DENALI_CTL_141_READ_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH 7U
+#define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141
+#define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0
+
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH 7U
+#define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141
+#define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1
+
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH 4U
+#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141
+#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN
+
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH 4U
+#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141
+#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN
+
+#define LPDDR4__DENALI_CTL_142_READ_MASK 0x000FFF07U
+#define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x000FFF07U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH 3U
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN
+
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH 12U
+#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142
+#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE
+
+#define LPDDR4__DENALI_CTL_143_READ_MASK 0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_143_WRITE_MASK 0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE
+
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH 8U
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE
+
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE
+
+#define LPDDR4__DENALI_CTL_144_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_144_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_145_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_145_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_146_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_146_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_147_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET 0U
+#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147
+#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN
+
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET 0U
+#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147
+#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN
+
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET 0U
+#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147
+#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN
+
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT 24U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH 1U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR 0U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET 0U
+#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147
+#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17
+
+#define LPDDR4__DENALI_CTL_148_READ_MASK 0x3F3F0101U
+#define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x3F3F0101U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET 0U
+#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148
+#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET 0U
+#define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148
+#define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN
+
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT 16U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH 6U
+#define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148
+#define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH
+
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT 24U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH 6U
+#define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148
+#define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH
+
+#define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FF03FFU
+#define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FF03FFU
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT 0U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH 8U
+#define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149
+#define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER
+
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT 8U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH 2U
+#define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149
+#define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK
+
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT 16U
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH 8U
+#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149
+#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18
+
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET 0U
+#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149
+#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE
+
+#define LPDDR4__DENALI_CTL_150_READ_MASK 0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_150_WRITE_MASK 0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH 10U
+#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150
+#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH 16U
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_CTL_151_READ_MASK 0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_151_WRITE_MASK 0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH 10U
+#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151
+#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH 16U
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_CTL_152_READ_MASK 0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_152_WRITE_MASK 0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH 10U
+#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152
+#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH 16U
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000103U
+#define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000103U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH 2U
+#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153
+#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY
+
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET 0U
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN
+
+#define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR
+
+#define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0
+
+#define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1
+
+#define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2
+
+#define LPDDR4__DENALI_CTL_158_READ_MASK 0x00FFFF0FU
+#define LPDDR4__DENALI_CTL_158_WRITE_MASK 0x00FFFF0FU
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH 4U
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK
+
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT
+
+#define LPDDR4__DENALI_CTL_159_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH 27U
+#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159
+#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG
+
+#define LPDDR4__DENALI_CTL_160_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH 8U
+#define LPDDR4__MRW_STATUS__REG DENALI_CTL_160
+#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS
+
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT 8U
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH 17U
+#define LPDDR4__READ_MODEREG__REG DENALI_CTL_160
+#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG
+
+#define LPDDR4__DENALI_CTL_161_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH 32U
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161
+#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_CTL_162_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH 8U
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162
+#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1
+
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH 16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0
+
+#define LPDDR4__DENALI_CTL_163_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH 16U
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1
+
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT 16U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH 1U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR 0U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET 0U
+#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163
+#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG
+
+#define LPDDR4__DENALI_CTL_164_READ_MASK 0x03FF0003U
+#define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x03FF0003U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH 2U
+#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164
+#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC
+
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH 10U
+#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164
+#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0
+
+#define LPDDR4__DENALI_CTL_165_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH 10U
+#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165
+#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0
+
+#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH 10U
+#define LPDDR4__TFC_F0__REG DENALI_CTL_165
+#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0
+
+#define LPDDR4__DENALI_CTL_166_READ_MASK 0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_166_WRITE_MASK 0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH 5U
+#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166
+#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0
+
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH 5U
+#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166
+#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0
+
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH 16U
+#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166
+#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0
+
+#define LPDDR4__DENALI_CTL_167_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH 10U
+#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167
+#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1
+
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH 10U
+#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167
+#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1
+
+#define LPDDR4__DENALI_CTL_168_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH 10U
+#define LPDDR4__TFC_F1__REG DENALI_CTL_168
+#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1
+
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH 5U
+#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168
+#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1
+
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH 5U
+#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168
+#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1
+
+#define LPDDR4__DENALI_CTL_169_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_169_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH 16U
+#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169
+#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1
+
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH 10U
+#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169
+#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2
+
+#define LPDDR4__DENALI_CTL_170_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_170_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH 10U
+#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170
+#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2
+
+#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH 10U
+#define LPDDR4__TFC_F2__REG DENALI_CTL_170
+#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2
+
+#define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH 5U
+#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171
+#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2
+
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH 5U
+#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171
+#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2
+
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH 16U
+#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171
+#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2
+
+#define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_173_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_174_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_175_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_175_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175
+#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175
+#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175
+#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175
+#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_176_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176
+#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176
+#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH 8U
+#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176
+#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176
+#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_177_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_177_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177
+#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177
+#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177
+#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177
+#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_178_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178
+#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH 8U
+#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178
+#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0
+
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178
+#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178
+#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_179_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179
+#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179
+#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179
+#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179
+#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_180_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH 8U
+#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180
+#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0
+
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180
+#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180
+#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180
+#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH 8U
+#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181
+#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0
+
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH 8U
+#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181
+#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0
+
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH 8U
+#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181
+#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0
+
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH 8U
+#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181
+#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_182_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH 8U
+#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182
+#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH 8U
+#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182
+#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182
+#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182
+#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_183_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183
+#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183
+#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183
+#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183
+#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_184_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_184_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH 8U
+#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184
+#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184
+#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184
+#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184
+#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_185_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_185_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185
+#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185
+#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185
+#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH 8U
+#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185
+#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1
+
+#define LPDDR4__DENALI_CTL_186_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_186_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186
+#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186
+#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186
+#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186
+#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_187_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_187_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187
+#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187
+#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH 8U
+#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187
+#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1
+
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187
+#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_188_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_188_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188
+#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188
+#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH 8U
+#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188
+#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1
+
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH 8U
+#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188
+#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1
+
+#define LPDDR4__DENALI_CTL_189_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_189_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH 8U
+#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189
+#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1
+
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH 8U
+#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189
+#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH 8U
+#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189
+#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH 8U
+#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189
+#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_190_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_CTL_190_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT 0U
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH 8U
+#define LPDDR4__MR23_DATA__REG DENALI_CTL_190
+#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA
+
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET 0U
+#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190
+#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0
+
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET 0U
+#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190
+#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1
+
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET 0U
+#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190
+#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2
+
+#define LPDDR4__DENALI_CTL_191_READ_MASK 0x01010103U
+#define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x01010103U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH 2U
+#define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191
+#define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN
+
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT 8U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH 1U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR 0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET 0U
+#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191
+#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19
+
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT 16U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH 1U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR 0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET 0U
+#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191
+#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20
+
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT 24U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH 1U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR 0U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET 0U
+#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191
+#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW
+
+#define LPDDR4__DENALI_CTL_192_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_192_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT 0U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH 1U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR 0U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET 0U
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP
+
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET 0U
+#define LPDDR4__FSP_STATUS__REG DENALI_CTL_192
+#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS
+
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET 0U
+#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192
+#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT
+
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET 0U
+#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192
+#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT
+
+#define LPDDR4__DENALI_CTL_193_READ_MASK 0x03030101U
+#define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x03030101U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT 0U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH 1U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR 0U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET 0U
+#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193
+#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT 8U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH 1U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR 0U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET 0U
+#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193
+#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT 16U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH 2U
+#define LPDDR4__FSP0_FRC__REG DENALI_CTL_193
+#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC
+
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT 24U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH 2U
+#define LPDDR4__FSP1_FRC__REG DENALI_CTL_193
+#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC
+
+#define LPDDR4__DENALI_CTL_194_READ_MASK 0x013F0300U
+#define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x013F0300U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT 0U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH 1U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR 0U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET 0U
+#define LPDDR4__BIST_GO__REG DENALI_CTL_194
+#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO
+
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH 2U
+#define LPDDR4__BIST_RESULT__REG DENALI_CTL_194
+#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT
+
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH 6U
+#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194
+#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE
+
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT 24U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET 0U
+#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194
+#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_CTL_195_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET 0U
+#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195
+#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_CTL_196_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH 32U
+#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196
+#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_197_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH 3U
+#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197
+#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_198_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH 32U
+#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198
+#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0
+
+#define LPDDR4__DENALI_CTL_199_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH 32U
+#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199
+#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1
+
+#define LPDDR4__DENALI_CTL_200_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH 3U
+#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200
+#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE
+
+#define LPDDR4__DENALI_CTL_201_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201
+#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0
+
+#define LPDDR4__DENALI_CTL_202_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202
+#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1
+
+#define LPDDR4__DENALI_CTL_203_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203
+#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2
+
+#define LPDDR4__DENALI_CTL_204_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH 32U
+#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204
+#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3
+
+#define LPDDR4__DENALI_CTL_205_READ_MASK 0x0FFF0100U
+#define LPDDR4__DENALI_CTL_205_WRITE_MASK 0x0FFF0100U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET 0U
+#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205
+#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT
+
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET 0U
+#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205
+#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE
+
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT 16U
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH 12U
+#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205
+#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP
+
+#define LPDDR4__DENALI_CTL_206_READ_MASK 0x07030FFFU
+#define LPDDR4__DENALI_CTL_206_WRITE_MASK 0x07030FFFU
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH 12U
+#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206
+#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH 2U
+#define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206
+#define LPDDR4__ECC_ENABLE__FLD LPDDR4__DENALI_CTL_206__ECC_ENABLE
+
+#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT 24U
+#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH 3U
+#define LPDDR4__INLINE_ECC_BANK_OFFSET__REG DENALI_CTL_206
+#define LPDDR4__INLINE_ECC_BANK_OFFSET__FLD LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET
+
+#define LPDDR4__DENALI_CTL_207_READ_MASK 0x010F0101U
+#define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x010F0101U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET 0U
+#define LPDDR4__ECC_READ_CACHING_EN__REG DENALI_CTL_207
+#define LPDDR4__ECC_READ_CACHING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN
+
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET 0U
+#define LPDDR4__ECC_WRITE_COMBINING_EN__REG DENALI_CTL_207
+#define LPDDR4__ECC_WRITE_COMBINING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN
+
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT 16U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH 4U
+#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_207
+#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED21
+
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT 24U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH 1U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR 0U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET 0U
+#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_207
+#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED22
+
+#define LPDDR4__DENALI_CTL_208_READ_MASK 0x01FFFF01U
+#define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x01FFFF01U
+#define LPDDR4__DENALI_CTL_208__FWC_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_208__FWC_SHIFT 0U
+#define LPDDR4__DENALI_CTL_208__FWC_WIDTH 1U
+#define LPDDR4__DENALI_CTL_208__FWC_WOCLR 0U
+#define LPDDR4__DENALI_CTL_208__FWC_WOSET 0U
+#define LPDDR4__FWC__REG DENALI_CTL_208
+#define LPDDR4__FWC__FLD LPDDR4__DENALI_CTL_208__FWC
+
+#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH 16U
+#define LPDDR4__XOR_CHECK_BITS__REG DENALI_CTL_208
+#define LPDDR4__XOR_CHECK_BITS__FLD LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS
+
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET 0U
+#define LPDDR4__ECC_WRITEBACK_EN__REG DENALI_CTL_208
+#define LPDDR4__ECC_WRITEBACK_EN__FLD LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN
+
+#define LPDDR4__DENALI_CTL_209_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH 1U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR 0U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET 0U
+#define LPDDR4__ECC_DISABLE_W_UC_ERR__REG DENALI_CTL_209
+#define LPDDR4__ECC_DISABLE_W_UC_ERR__FLD LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR
+
+#define LPDDR4__DENALI_CTL_210_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_210_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH 32U
+#define LPDDR4__ECC_U_ADDR_0__REG DENALI_CTL_210
+#define LPDDR4__ECC_U_ADDR_0__FLD LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0
+
+#define LPDDR4__DENALI_CTL_211_READ_MASK 0x0000FF07U
+#define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0000FF07U
+#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH 3U
+#define LPDDR4__ECC_U_ADDR_1__REG DENALI_CTL_211
+#define LPDDR4__ECC_U_ADDR_1__FLD LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1
+
+#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT 8U
+#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH 8U
+#define LPDDR4__ECC_U_SYND__REG DENALI_CTL_211
+#define LPDDR4__ECC_U_SYND__FLD LPDDR4__DENALI_CTL_211__ECC_U_SYND
+
+#define LPDDR4__DENALI_CTL_212_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_212_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH 32U
+#define LPDDR4__ECC_U_DATA_0__REG DENALI_CTL_212
+#define LPDDR4__ECC_U_DATA_0__FLD LPDDR4__DENALI_CTL_212__ECC_U_DATA_0
+
+#define LPDDR4__DENALI_CTL_213_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_213_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH 32U
+#define LPDDR4__ECC_U_DATA_1__REG DENALI_CTL_213
+#define LPDDR4__ECC_U_DATA_1__FLD LPDDR4__DENALI_CTL_213__ECC_U_DATA_1
+
+#define LPDDR4__DENALI_CTL_214_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_214_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH 32U
+#define LPDDR4__ECC_C_ADDR_0__REG DENALI_CTL_214
+#define LPDDR4__ECC_C_ADDR_0__FLD LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0
+
+#define LPDDR4__DENALI_CTL_215_READ_MASK 0x0000FF07U
+#define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0000FF07U
+#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH 3U
+#define LPDDR4__ECC_C_ADDR_1__REG DENALI_CTL_215
+#define LPDDR4__ECC_C_ADDR_1__FLD LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1
+
+#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT 8U
+#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH 8U
+#define LPDDR4__ECC_C_SYND__REG DENALI_CTL_215
+#define LPDDR4__ECC_C_SYND__FLD LPDDR4__DENALI_CTL_215__ECC_C_SYND
+
+#define LPDDR4__DENALI_CTL_216_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_216_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH 32U
+#define LPDDR4__ECC_C_DATA_0__REG DENALI_CTL_216
+#define LPDDR4__ECC_C_DATA_0__FLD LPDDR4__DENALI_CTL_216__ECC_C_DATA_0
+
+#define LPDDR4__DENALI_CTL_217_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_217_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH 32U
+#define LPDDR4__ECC_C_DATA_1__REG DENALI_CTL_217
+#define LPDDR4__ECC_C_DATA_1__FLD LPDDR4__DENALI_CTL_217__ECC_C_DATA_1
+
+#define LPDDR4__DENALI_CTL_218_READ_MASK 0x7FFF3F3FU
+#define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x7FFF3F3FU
+#define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT 0U
+#define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH 6U
+#define LPDDR4__ECC_U_ID__REG DENALI_CTL_218
+#define LPDDR4__ECC_U_ID__FLD LPDDR4__DENALI_CTL_218__ECC_U_ID
+
+#define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT 8U
+#define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH 6U
+#define LPDDR4__ECC_C_ID__REG DENALI_CTL_218
+#define LPDDR4__ECC_C_ID__FLD LPDDR4__DENALI_CTL_218__ECC_C_ID
+
+#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_MASK 0x7FFF0000U
+#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_WIDTH 15U
+#define LPDDR4__NON_ECC_REGION_START_ADDR_0__REG DENALI_CTL_218
+#define LPDDR4__NON_ECC_REGION_START_ADDR_0__FLD LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0
+
+#define LPDDR4__DENALI_CTL_219_READ_MASK 0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_MASK 0x00007FFFU
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_WIDTH 15U
+#define LPDDR4__NON_ECC_REGION_END_ADDR_0__REG DENALI_CTL_219
+#define LPDDR4__NON_ECC_REGION_END_ADDR_0__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0
+
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_MASK 0x7FFF0000U
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_WIDTH 15U
+#define LPDDR4__NON_ECC_REGION_START_ADDR_1__REG DENALI_CTL_219
+#define LPDDR4__NON_ECC_REGION_START_ADDR_1__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1
+
+#define LPDDR4__DENALI_CTL_220_READ_MASK 0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_MASK 0x00007FFFU
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_WIDTH 15U
+#define LPDDR4__NON_ECC_REGION_END_ADDR_1__REG DENALI_CTL_220
+#define LPDDR4__NON_ECC_REGION_END_ADDR_1__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1
+
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_MASK 0x7FFF0000U
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_WIDTH 15U
+#define LPDDR4__NON_ECC_REGION_START_ADDR_2__REG DENALI_CTL_220
+#define LPDDR4__NON_ECC_REGION_START_ADDR_2__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2
+
+#define LPDDR4__DENALI_CTL_221_READ_MASK 0x00077FFFU
+#define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x00077FFFU
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_MASK 0x00007FFFU
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_WIDTH 15U
+#define LPDDR4__NON_ECC_REGION_END_ADDR_2__REG DENALI_CTL_221
+#define LPDDR4__NON_ECC_REGION_END_ADDR_2__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2
+
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH 3U
+#define LPDDR4__NON_ECC_REGION_ENABLE__REG DENALI_CTL_221
+#define LPDDR4__NON_ECC_REGION_ENABLE__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE
+
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT 24U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH 1U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR 0U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET 0U
+#define LPDDR4__ECC_SCRUB_START__REG DENALI_CTL_221
+#define LPDDR4__ECC_SCRUB_START__FLD LPDDR4__DENALI_CTL_221__ECC_SCRUB_START
+
+#define LPDDR4__DENALI_CTL_222_READ_MASK 0x010FFF01U
+#define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x010FFF01U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET 0U
+#define LPDDR4__ECC_SCRUB_IN_PROGRESS__REG DENALI_CTL_222
+#define LPDDR4__ECC_SCRUB_IN_PROGRESS__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS
+
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH 12U
+#define LPDDR4__ECC_SCRUB_LEN__REG DENALI_CTL_222
+#define LPDDR4__ECC_SCRUB_LEN__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN
+
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET 0U
+#define LPDDR4__ECC_SCRUB_MODE__REG DENALI_CTL_222
+#define LPDDR4__ECC_SCRUB_MODE__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE
+
+#define LPDDR4__DENALI_CTL_223_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_223_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH 16U
+#define LPDDR4__ECC_SCRUB_INTERVAL__REG DENALI_CTL_223
+#define LPDDR4__ECC_SCRUB_INTERVAL__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL
+
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH 16U
+#define LPDDR4__ECC_SCRUB_IDLE_CNT__REG DENALI_CTL_223
+#define LPDDR4__ECC_SCRUB_IDLE_CNT__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT
+
+#define LPDDR4__DENALI_CTL_224_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_224_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH 32U
+#define LPDDR4__ECC_SCRUB_START_ADDR_0__REG DENALI_CTL_224
+#define LPDDR4__ECC_SCRUB_START_ADDR_0__FLD LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0
+
+#define LPDDR4__DENALI_CTL_225_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH 3U
+#define LPDDR4__ECC_SCRUB_START_ADDR_1__REG DENALI_CTL_225
+#define LPDDR4__ECC_SCRUB_START_ADDR_1__FLD LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1
+
+#define LPDDR4__DENALI_CTL_226_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_226_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH 32U
+#define LPDDR4__ECC_SCRUB_END_ADDR_0__REG DENALI_CTL_226
+#define LPDDR4__ECC_SCRUB_END_ADDR_0__FLD LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0
+
+#define LPDDR4__DENALI_CTL_227_READ_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH 3U
+#define LPDDR4__ECC_SCRUB_END_ADDR_1__REG DENALI_CTL_227
+#define LPDDR4__ECC_SCRUB_END_ADDR_1__FLD LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1
+
+#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT 8U
+#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH 5U
+#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_227
+#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_227
+#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH 5U
+#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_227
+#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_228_READ_MASK 0x000F1F1FU
+#define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x000F1F1FU
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH 5U
+#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_228
+#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT
+
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH 5U
+#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_228
+#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT
+
+#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT 16U
+#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH 4U
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_228
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI
+
+#define LPDDR4__DENALI_CTL_229_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_229_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_229
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_229
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_230_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_230_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_230
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_230
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_231_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_231_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_231
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_231
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_232_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_232_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_232
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_232
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_233_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_233_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_233
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_233
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_234_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_234_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_235_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_235_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_235
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_235
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_236_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_236_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_236
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_236
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_237_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_237_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_237
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_237
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_238_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_238_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_238
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_238
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_239_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_239_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_239
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_239
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_240_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_240_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_240
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_240
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_241_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_241_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_241
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_241
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_242_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_242
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT 16U
+#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH 3U
+#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_242
+#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_242__MC_RESERVED23
+
+#define LPDDR4__DENALI_CTL_243_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_243_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__REG DENALI_CTL_243
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0
+
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__REG DENALI_CTL_243
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0
+
+#define LPDDR4__DENALI_CTL_244_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_244_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__REG DENALI_CTL_244
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0
+
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__REG DENALI_CTL_244
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0
+
+#define LPDDR4__DENALI_CTL_245_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_245_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__REG DENALI_CTL_245
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0
+
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__REG DENALI_CTL_245
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0
+
+#define LPDDR4__DENALI_CTL_246_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_246_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__REG DENALI_CTL_246
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0
+
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__REG DENALI_CTL_246
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0
+
+#define LPDDR4__DENALI_CTL_247_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_247_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__REG DENALI_CTL_247
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1
+
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__REG DENALI_CTL_247
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1
+
+#define LPDDR4__DENALI_CTL_248_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_248_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__REG DENALI_CTL_248
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1
+
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__REG DENALI_CTL_248
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1
+
+#define LPDDR4__DENALI_CTL_249_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_249_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__REG DENALI_CTL_249
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1
+
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__REG DENALI_CTL_249
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1
+
+#define LPDDR4__DENALI_CTL_250_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_250_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__REG DENALI_CTL_250
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1
+
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__REG DENALI_CTL_250
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1
+
+#define LPDDR4__DENALI_CTL_251_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_251_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__REG DENALI_CTL_251
+#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2
+
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__REG DENALI_CTL_251
+#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2
+
+#define LPDDR4__DENALI_CTL_252_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_252_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__REG DENALI_CTL_252
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2
+
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__REG DENALI_CTL_252
+#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2
+
+#define LPDDR4__DENALI_CTL_253_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_253_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__REG DENALI_CTL_253
+#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2
+
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__REG DENALI_CTL_253
+#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2
+
+#define LPDDR4__DENALI_CTL_254_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__REG DENALI_CTL_254
+#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2
+
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_WIDTH 16U
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__REG DENALI_CTL_254
+#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2
+
+#define LPDDR4__DENALI_CTL_255_READ_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT 0U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH 8U
+#define LPDDR4__WATCHDOG_RELOAD__REG DENALI_CTL_255
+#define LPDDR4__WATCHDOG_RELOAD__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD
+
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH 8U
+#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__REG DENALI_CTL_255
+#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE
+
+#define LPDDR4__DENALI_CTL_256_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_256_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT 0U
+#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH 20U
+#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_256
+#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG
+
+#define LPDDR4__DENALI_CTL_257_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_257_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH 12U
+#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_257
+#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_257__ZQINIT_F0
+
+#define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH 12U
+#define LPDDR4__ZQCL_F0__REG DENALI_CTL_257
+#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_257__ZQCL_F0
+
+#define LPDDR4__DENALI_CTL_258_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH 12U
+#define LPDDR4__ZQCS_F0__REG DENALI_CTL_258
+#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_258__ZQCS_F0
+
+#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH 12U
+#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_258
+#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_258__TZQCAL_F0
+
+#define LPDDR4__DENALI_CTL_259_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH 7U
+#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_259
+#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_259__TZQLAT_F0
+
+#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH 12U
+#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_259
+#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_259__ZQINIT_F1
+
+#define LPDDR4__DENALI_CTL_260_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH 12U
+#define LPDDR4__ZQCL_F1__REG DENALI_CTL_260
+#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_260__ZQCL_F1
+
+#define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH 12U
+#define LPDDR4__ZQCS_F1__REG DENALI_CTL_260
+#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_260__ZQCS_F1
+
+#define LPDDR4__DENALI_CTL_261_READ_MASK 0x007F0FFFU
+#define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x007F0FFFU
+#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH 12U
+#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_261
+#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_261__TZQCAL_F1
+
+#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH 7U
+#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_261
+#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_261__TZQLAT_F1
+
+#define LPDDR4__DENALI_CTL_262_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH 12U
+#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_262
+#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_262__ZQINIT_F2
+
+#define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH 12U
+#define LPDDR4__ZQCL_F2__REG DENALI_CTL_262
+#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_262__ZQCL_F2
+
+#define LPDDR4__DENALI_CTL_263_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH 12U
+#define LPDDR4__ZQCS_F2__REG DENALI_CTL_263
+#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_263__ZQCS_F2
+
+#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH 12U
+#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_263
+#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_263__TZQCAL_F2
+
+#define LPDDR4__DENALI_CTL_264_READ_MASK 0x0100037FU
+#define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0100037FU
+#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH 7U
+#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_264
+#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_264__TZQLAT_F2
+
+#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 8U
+#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_264
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP
+
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH 4U
+#define LPDDR4__ZQ_REQ__REG DENALI_CTL_264
+#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ
+
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT 24U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH 1U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR 0U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET 0U
+#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_264
+#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_CTL_265_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH 12U
+#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_265
+#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F0
+
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH 12U
+#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_265
+#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F1
+
+#define LPDDR4__DENALI_CTL_266_READ_MASK 0x01010FFFU
+#define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x01010FFFU
+#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH 12U
+#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_266
+#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_266__ZQRESET_F2
+
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET 0U
+#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_266
+#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_266__NO_ZQ_INIT
+
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET 0U
+#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_266
+#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_266__ZQCS_ROTATE
+
+#define LPDDR4__DENALI_CTL_267_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH 2U
+#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_267
+#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH 2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_267
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH 2U
+#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_267
+#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH 2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_267
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_CTL_268_READ_MASK 0x07070303U
+#define LPDDR4__DENALI_CTL_268_WRITE_MASK 0x07070303U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH 2U
+#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_268
+#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_0
+
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH 2U
+#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_268
+#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_1
+
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH 3U
+#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_268
+#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_0
+
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH 3U
+#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_268
+#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_1
+
+#define LPDDR4__DENALI_CTL_269_READ_MASK 0xFFFF0F0FU
+#define LPDDR4__DENALI_CTL_269_WRITE_MASK 0xFFFF0F0FU
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH 4U
+#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_269
+#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_0
+
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH 4U
+#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_269
+#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_1
+
+#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH 16U
+#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_269
+#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0
+
+#define LPDDR4__DENALI_CTL_270_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH 16U
+#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_270
+#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0
+
+#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH 3U
+#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_270
+#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_270__ROW_START_VAL_0
+
+#define LPDDR4__DENALI_CTL_271_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_271_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH 16U
+#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_271
+#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1
+
+#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH 16U
+#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_271
+#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1
+
+#define LPDDR4__DENALI_CTL_272_READ_MASK 0xFFFF0307U
+#define LPDDR4__DENALI_CTL_272_WRITE_MASK 0xFFFF0307U
+#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH 3U
+#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_272
+#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_272__ROW_START_VAL_1
+
+#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH 2U
+#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_272
+#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2
+
+#define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH 16U
+#define LPDDR4__CS_MSK_0__REG DENALI_CTL_272
+#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_272__CS_MSK_0
+
+#define LPDDR4__DENALI_CTL_273_READ_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH 16U
+#define LPDDR4__CS_MSK_1__REG DENALI_CTL_273
+#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_273__CS_MSK_1
+
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET 0U
+#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_273
+#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN
+
+#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT 24U
+#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH 5U
+#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_273
+#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_273__MC_RESERVED24
+
+#define LPDDR4__DENALI_CTL_274_READ_MASK 0xFFFF1F01U
+#define LPDDR4__DENALI_CTL_274_WRITE_MASK 0xFFFF1F01U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT 0U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH 1U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR 0U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET 0U
+#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_274
+#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_274__MC_RESERVED25
+
+#define LPDDR4__DENALI_CTL_274__APREBIT_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH 5U
+#define LPDDR4__APREBIT__REG DENALI_CTL_274
+#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_274__APREBIT
+
+#define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH 8U
+#define LPDDR4__AGE_COUNT__REG DENALI_CTL_274
+#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH 8U
+#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_274
+#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_275_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET 0U
+#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_275
+#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_275__ADDR_CMP_EN
+
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET 0U
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_275
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS
+
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET 0U
+#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_275
+#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET 0U
+#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_275
+#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_275__PLACEMENT_EN
+
+#define LPDDR4__DENALI_CTL_276_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET 0U
+#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_276
+#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_276__PRIORITY_EN
+
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET 0U
+#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_276
+#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_EN
+
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET 0U
+#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_276
+#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN
+
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET 0U
+#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_276
+#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_276__CS_SAME_EN
+
+#define LPDDR4__DENALI_CTL_277_READ_MASK 0x011F0301U
+#define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x011F0301U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET 0U
+#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_277
+#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_277
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT
+
+#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_277
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE
+
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET 0U
+#define LPDDR4__SWAP_EN__REG DENALI_CTL_277
+#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_277__SWAP_EN
+
+#define LPDDR4__DENALI_CTL_278_READ_MASK 0x01030301U
+#define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x01030301U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET 0U
+#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_278
+#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE
+
+#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT 8U
+#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH 2U
+#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_278
+#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD
+
+#define LPDDR4__DENALI_CTL_278__CS_MAP_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT 16U
+#define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH 2U
+#define LPDDR4__CS_MAP__REG DENALI_CTL_278
+#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_278__CS_MAP
+
+#define LPDDR4__DENALI_CTL_278__REDUC_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_278__REDUC_SHIFT 24U
+#define LPDDR4__DENALI_CTL_278__REDUC_WIDTH 1U
+#define LPDDR4__DENALI_CTL_278__REDUC_WOCLR 0U
+#define LPDDR4__DENALI_CTL_278__REDUC_WOSET 0U
+#define LPDDR4__REDUC__REG DENALI_CTL_278
+#define LPDDR4__REDUC__FLD LPDDR4__DENALI_CTL_278__REDUC
+
+#define LPDDR4__DENALI_CTL_279_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_WIDTH 18U
+#define LPDDR4__FAULT_FIFO_PROTECTION_EN__REG DENALI_CTL_279
+#define LPDDR4__FAULT_FIFO_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_280_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_WIDTH 18U
+#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__REG DENALI_CTL_280
+#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS
+
+#define LPDDR4__DENALI_CTL_281_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_WIDTH 18U
+#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__REG DENALI_CTL_281
+#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOSET 0U
+#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_281
+#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_282_READ_MASK 0x01010103U
+#define LPDDR4__DENALI_CTL_282_WRITE_MASK 0x01010103U
+#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_WIDTH 2U
+#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
+#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOSET 0U
+#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__REG DENALI_CTL_282
+#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET 0U
+#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_282
+#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET 0U
+#define LPDDR4__READ_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
+#define LPDDR4__READ_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_283_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT 0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH 1U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR 0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET 0U
+#define LPDDR4__MC_RESERVED26__REG DENALI_CTL_283
+#define LPDDR4__MC_RESERVED26__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED26
+
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT 8U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH 1U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR 0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET 0U
+#define LPDDR4__MC_RESERVED27__REG DENALI_CTL_283
+#define LPDDR4__MC_RESERVED27__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED27
+
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOSET 0U
+#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__REG DENALI_CTL_283
+#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__FLD LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN
+
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET 0U
+#define LPDDR4__READ_PARITY_ERR_RRESP_EN__REG DENALI_CTL_283
+#define LPDDR4__READ_PARITY_ERR_RRESP_EN__FLD LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN
+
+#define LPDDR4__DENALI_CTL_284_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_284_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U
+#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
+#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOSET 0U
+#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
+#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOSET 0U
+#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_284
+#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U
+#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
+#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_285_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_285_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOSET 0U
+#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_285
+#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN
+
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_SHIFT 8U
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOSET 0U
+#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__REG DENALI_CTL_285
+#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__FLD LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT
+
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOSET 0U
+#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__REG DENALI_CTL_285
+#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__FLD LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN
+
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOSET 0U
+#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__REG DENALI_CTL_285
+#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_286_READ_MASK 0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_286_WRITE_MASK 0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH 3U
+#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_286
+#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH 4U
+#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_286
+#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH 4U
+#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_286
+#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH 4U
+#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_286
+#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_287_READ_MASK 0x0F0F070FU
+#define LPDDR4__DENALI_CTL_287_WRITE_MASK 0x0F0F070FU
+#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH 4U
+#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_287
+#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH 3U
+#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_287
+#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH 4U
+#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_287
+#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH 4U
+#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_287
+#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_288_READ_MASK 0x011F0F0FU
+#define LPDDR4__DENALI_CTL_288_WRITE_MASK 0x011F0F0FU
+#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH 4U
+#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_288
+#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH 4U
+#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_288
+#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH 5U
+#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_288
+#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_288__Q_FULLNESS
+
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET 0U
+#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_288
+#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT
+
+#define LPDDR4__DENALI_CTL_289_READ_MASK 0x01000103U
+#define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x01000103U
+#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH 2U
+#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_289
+#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_289__WR_ORDER_REQ
+
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH 1U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR 0U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET 0U
+#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_289
+#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY
+
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH 1U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR 0U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET 0U
+#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_289
+#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ
+
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_289
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_CTL_290_READ_MASK 0x03030301U
+#define LPDDR4__DENALI_CTL_290_WRITE_MASK 0x03030301U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET 0U
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_290
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE
+
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH 2U
+#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_290
+#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH 2U
+#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_290
+#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH 2U
+#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_290
+#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_CTL_291_READ_MASK 0x1F010101U
+#define LPDDR4__DENALI_CTL_291_WRITE_MASK 0x1F010101U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET 0U
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_291
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET 0U
+#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_291
+#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_291__WR_DBI_EN
+
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET 0U
+#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_291
+#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_291__RD_DBI_EN
+
+#define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT 24U
+#define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH 5U
+#define LPDDR4__DFI_ERROR__REG DENALI_CTL_291
+#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_291__DFI_ERROR
+
+#define LPDDR4__DENALI_CTL_292_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_292_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT 0U
+#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH 20U
+#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_292
+#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO
+
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT 24U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH 1U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR 0U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET 0U
+#define LPDDR4__MC_RESERVED28__REG DENALI_CTL_292
+#define LPDDR4__MC_RESERVED28__FLD LPDDR4__DENALI_CTL_292__MC_RESERVED28
+
+#define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH 32U
+#define LPDDR4__INT_STATUS_0__REG DENALI_CTL_293
+#define LPDDR4__INT_STATUS_0__FLD LPDDR4__DENALI_CTL_293__INT_STATUS_0
+
+#define LPDDR4__DENALI_CTL_294_READ_MASK 0x00001FFFU
+#define LPDDR4__DENALI_CTL_294_WRITE_MASK 0x00001FFFU
+#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK 0x00001FFFU
+#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH 13U
+#define LPDDR4__INT_STATUS_1__REG DENALI_CTL_294
+#define LPDDR4__INT_STATUS_1__FLD LPDDR4__DENALI_CTL_294__INT_STATUS_1
+
+#define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH 32U
+#define LPDDR4__INT_ACK_0__REG DENALI_CTL_295
+#define LPDDR4__INT_ACK_0__FLD LPDDR4__DENALI_CTL_295__INT_ACK_0
+
+#define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH 12U
+#define LPDDR4__INT_ACK_1__REG DENALI_CTL_296
+#define LPDDR4__INT_ACK_1__FLD LPDDR4__DENALI_CTL_296__INT_ACK_1
+
+#define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH 32U
+#define LPDDR4__INT_MASK_0__REG DENALI_CTL_297
+#define LPDDR4__INT_MASK_0__FLD LPDDR4__DENALI_CTL_297__INT_MASK_0
+
+#define LPDDR4__DENALI_CTL_298_READ_MASK 0x00001FFFU
+#define LPDDR4__DENALI_CTL_298_WRITE_MASK 0x00001FFFU
+#define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK 0x00001FFFU
+#define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH 13U
+#define LPDDR4__INT_MASK_1__REG DENALI_CTL_298
+#define LPDDR4__INT_MASK_1__FLD LPDDR4__DENALI_CTL_298__INT_MASK_1
+
+#define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH 32U
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_299
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0
+
+#define LPDDR4__DENALI_CTL_300_READ_MASK 0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_300_WRITE_MASK 0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH 3U
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_300
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1
+
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_MASK 0x000FFF00U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT 8U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH 12U
+#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_300
+#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH
+
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH 7U
+#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_300
+#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE
+
+#define LPDDR4__DENALI_CTL_301_READ_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_301_WRITE_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U
+#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_301
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID
+
+#define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_302
+#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_303
+#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_304
+#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2
+
+#define LPDDR4__DENALI_CTL_305_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH 32U
+#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_305
+#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3
+
+#define LPDDR4__DENALI_CTL_306_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_306
+#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_CTL_307_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_307
+#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_CTL_308_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_308
+#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2
+
+#define LPDDR4__DENALI_CTL_309_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH 32U
+#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_309
+#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3
+
+#define LPDDR4__DENALI_CTL_310_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH 32U
+#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_310
+#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_CTL_311_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH 3U
+#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_311
+#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_CTL_312_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_312_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH 32U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_312
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0
+
+#define LPDDR4__DENALI_CTL_313_READ_MASK 0x03033F07U
+#define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x03033F07U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH 3U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_313
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1
+
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT 8U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH 6U
+#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_313
+#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID
+
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH 2U
+#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_313
+#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE
+
+#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH 2U
+#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_313
+#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_314_READ_MASK 0xFF030303U
+#define LPDDR4__DENALI_CTL_314_WRITE_MASK 0xFF030303U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK 0x00000003U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH 2U
+#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_314
+#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH 2U
+#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_314
+#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH 2U
+#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_314
+#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH 8U
+#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_314
+#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_CTL_315_READ_MASK 0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH 4U
+#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_315
+#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F0
+
+#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH 4U
+#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_315
+#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_RD_F0
+
+#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH 8U
+#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_315
+#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH 4U
+#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_315
+#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F1
+
+#define LPDDR4__DENALI_CTL_316_READ_MASK 0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH 4U
+#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_316
+#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F1
+
+#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH 8U
+#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_316
+#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH 4U
+#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_316
+#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_WR_F2
+
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH 4U
+#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_316
+#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F2
+
+#define LPDDR4__DENALI_CTL_317_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET 0U
+#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_317
+#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F0
+
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET 0U
+#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_317
+#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F1
+
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET 0U
+#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_317
+#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F2
+
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_317
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD
+
+#define LPDDR4__DENALI_CTL_318_READ_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_CTL_318_WRITE_MASK 0x3F3F3F3FU
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_318
+#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_318
+#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_318
+#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK 0x3F000000U
+#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH 6U
+#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_318
+#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_319_READ_MASK 0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK 0x0000003FU
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH 6U
+#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_319
+#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH 6U
+#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_319
+#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH 5U
+#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_319
+#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0
+
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH 5U
+#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_319
+#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1
+
+#define LPDDR4__DENALI_CTL_320_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_320_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH 5U
+#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_320
+#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2
+
+#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
+#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_320
+#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
+#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_321_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH 5U
+#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_321
+#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
+#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_321
+#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
+#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_322_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH 5U
+#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_322
+#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
+#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_322
+#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
+#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_323_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH 5U
+#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_323
+#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH 5U
+#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_323
+#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH 5U
+#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_323
+#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_MASK 0x1F000000U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH 5U
+#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_323
+#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_324_READ_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_324_WRITE_MASK 0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH 5U
+#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_324
+#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK 0x00001F00U
+#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH 5U
+#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_324
+#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT 16U
+#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH 5U
+#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_324
+#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH 4U
+#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_324
+#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_CTL_325_READ_MASK 0x0F070F07U
+#define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x0F070F07U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH 3U
+#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_325
+#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0
+
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH 4U
+#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_325
+#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH 3U
+#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_325
+#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1
+
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH 4U
+#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_325
+#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_CTL_326_READ_MASK 0x00000707U
+#define LPDDR4__DENALI_CTL_326_WRITE_MASK 0x00000707U
+#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH 3U
+#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_326
+#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2
+
+#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH 3U
+#define LPDDR4__SW_LEVELING_MODE__REG DENALI_CTL_326
+#define LPDDR4__SW_LEVELING_MODE__FLD LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE
+
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH 1U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR 0U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET 0U
+#define LPDDR4__SWLVL_LOAD__REG DENALI_CTL_326
+#define LPDDR4__SWLVL_LOAD__FLD LPDDR4__DENALI_CTL_326__SWLVL_LOAD
+
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT 24U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH 1U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR 0U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET 0U
+#define LPDDR4__SWLVL_START__REG DENALI_CTL_326
+#define LPDDR4__SWLVL_START__FLD LPDDR4__DENALI_CTL_326__SWLVL_START
+
+#define LPDDR4__DENALI_CTL_327_READ_MASK 0x01010100U
+#define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x01010100U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET 0U
+#define LPDDR4__SWLVL_EXIT__REG DENALI_CTL_327
+#define LPDDR4__SWLVL_EXIT__FLD LPDDR4__DENALI_CTL_327__SWLVL_EXIT
+
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET 0U
+#define LPDDR4__SWLVL_OP_DONE__REG DENALI_CTL_327
+#define LPDDR4__SWLVL_OP_DONE__FLD LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE
+
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH 1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR 0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET 0U
+#define LPDDR4__SWLVL_RESP_0__REG DENALI_CTL_327
+#define LPDDR4__SWLVL_RESP_0__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_0
+
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH 1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR 0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET 0U
+#define LPDDR4__SWLVL_RESP_1__REG DENALI_CTL_327
+#define LPDDR4__SWLVL_RESP_1__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_1
+
+#define LPDDR4__DENALI_CTL_328_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH 1U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR 0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET 0U
+#define LPDDR4__SWLVL_RESP_2__REG DENALI_CTL_328
+#define LPDDR4__SWLVL_RESP_2__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_2
+
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT 8U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH 1U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR 0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET 0U
+#define LPDDR4__SWLVL_RESP_3__REG DENALI_CTL_328
+#define LPDDR4__SWLVL_RESP_3__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_3
+
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET 0U
+#define LPDDR4__PHYUPD_APPEND_EN__REG DENALI_CTL_328
+#define LPDDR4__PHYUPD_APPEND_EN__FLD LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN
+
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET 0U
+#define LPDDR4__WRLVL_REQ__REG DENALI_CTL_328
+#define LPDDR4__WRLVL_REQ__FLD LPDDR4__DENALI_CTL_328__WRLVL_REQ
+
+#define LPDDR4__DENALI_CTL_329_READ_MASK 0x013F3F01U
+#define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x013F3F01U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET 0U
+#define LPDDR4__WRLVL_CS__REG DENALI_CTL_329
+#define LPDDR4__WRLVL_CS__FLD LPDDR4__DENALI_CTL_329__WRLVL_CS
+
+#define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH 6U
+#define LPDDR4__WLDQSEN__REG DENALI_CTL_329
+#define LPDDR4__WLDQSEN__FLD LPDDR4__DENALI_CTL_329__WLDQSEN
+
+#define LPDDR4__DENALI_CTL_329__WLMRD_MASK 0x003F0000U
+#define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT 16U
+#define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH 6U
+#define LPDDR4__WLMRD__REG DENALI_CTL_329
+#define LPDDR4__WLMRD__FLD LPDDR4__DENALI_CTL_329__WLMRD
+
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET 0U
+#define LPDDR4__WRLVL_EN__REG DENALI_CTL_329
+#define LPDDR4__WRLVL_EN__FLD LPDDR4__DENALI_CTL_329__WRLVL_EN
+
+#define LPDDR4__DENALI_CTL_330_READ_MASK 0x0F010101U
+#define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x0F010101U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET 0U
+#define LPDDR4__DFI_PHY_WRLVL_MODE__REG DENALI_CTL_330
+#define LPDDR4__DFI_PHY_WRLVL_MODE__FLD LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE
+
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT 8U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET 0U
+#define LPDDR4__WRLVL_PERIODIC__REG DENALI_CTL_330
+#define LPDDR4__WRLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC
+
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__WRLVL_ON_SREF_EXIT__REG DENALI_CTL_330
+#define LPDDR4__WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT 24U
+#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH 4U
+#define LPDDR4__WRLVL_RESP_MASK__REG DENALI_CTL_330
+#define LPDDR4__WRLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK
+
+#define LPDDR4__DENALI_CTL_331_READ_MASK 0x07030101U
+#define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x07030101U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET 0U
+#define LPDDR4__WRLVL_AREF_EN__REG DENALI_CTL_331
+#define LPDDR4__WRLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN
+
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET 0U
+#define LPDDR4__WRLVL_ROTATE__REG DENALI_CTL_331
+#define LPDDR4__WRLVL_ROTATE__FLD LPDDR4__DENALI_CTL_331__WRLVL_ROTATE
+
+#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT 16U
+#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH 2U
+#define LPDDR4__WRLVL_CS_MAP__REG DENALI_CTL_331
+#define LPDDR4__WRLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP
+
+#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH 3U
+#define LPDDR4__WRLVL_ERROR_STATUS__REG DENALI_CTL_331
+#define LPDDR4__WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_332_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_332_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_332
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_332
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_333_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_333_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__WRLVL_TIMEOUT_F0__REG DENALI_CTL_333
+#define LPDDR4__WRLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_333
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_334_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_334
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_334
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_335_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_335
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__WRLVL_TIMEOUT_F1__REG DENALI_CTL_335
+#define LPDDR4__WRLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_336_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_337_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_337
+#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_337
+#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_338_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__WRLVL_TIMEOUT_F2__REG DENALI_CTL_338
+#define LPDDR4__WRLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_338
+#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_339_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_339_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_339
+#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT 16U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET 0U
+#define LPDDR4__RDLVL_REQ__REG DENALI_CTL_339
+#define LPDDR4__RDLVL_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_REQ
+
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT 24U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH 1U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR 0U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET 0U
+#define LPDDR4__RDLVL_GATE_REQ__REG DENALI_CTL_339
+#define LPDDR4__RDLVL_GATE_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ
+
+#define LPDDR4__DENALI_CTL_340_READ_MASK 0x010F0F01U
+#define LPDDR4__DENALI_CTL_340_WRITE_MASK 0x010F0F01U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET 0U
+#define LPDDR4__RDLVL_CS__REG DENALI_CTL_340
+#define LPDDR4__RDLVL_CS__FLD LPDDR4__DENALI_CTL_340__RDLVL_CS
+
+#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH 4U
+#define LPDDR4__RDLVL_SEQ_EN__REG DENALI_CTL_340
+#define LPDDR4__RDLVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN
+
+#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH 4U
+#define LPDDR4__RDLVL_GATE_SEQ_EN__REG DENALI_CTL_340
+#define LPDDR4__RDLVL_GATE_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN
+
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET 0U
+#define LPDDR4__DFI_PHY_RDLVL_MODE__REG DENALI_CTL_340
+#define LPDDR4__DFI_PHY_RDLVL_MODE__FLD LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE
+
+#define LPDDR4__DENALI_CTL_341_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_341_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET 0U
+#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__REG DENALI_CTL_341
+#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__FLD LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE
+
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT 8U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET 0U
+#define LPDDR4__RDLVL_PERIODIC__REG DENALI_CTL_341
+#define LPDDR4__RDLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC
+
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__RDLVL_ON_SREF_EXIT__REG DENALI_CTL_341
+#define LPDDR4__RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT 24U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET 0U
+#define LPDDR4__RDLVL_GATE_PERIODIC__REG DENALI_CTL_341
+#define LPDDR4__RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC
+
+#define LPDDR4__DENALI_CTL_342_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_342_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__REG DENALI_CTL_342
+#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET 0U
+#define LPDDR4__RDLVL_AREF_EN__REG DENALI_CTL_342
+#define LPDDR4__RDLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN
+
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET 0U
+#define LPDDR4__RDLVL_GATE_AREF_EN__REG DENALI_CTL_342
+#define LPDDR4__RDLVL_GATE_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN
+
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT 24U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH 1U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR 0U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET 0U
+#define LPDDR4__MC_RESERVED29__REG DENALI_CTL_342
+#define LPDDR4__MC_RESERVED29__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED29
+
+#define LPDDR4__DENALI_CTL_343_READ_MASK 0x03030101U
+#define LPDDR4__DENALI_CTL_343_WRITE_MASK 0x03030101U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET 0U
+#define LPDDR4__RDLVL_ROTATE__REG DENALI_CTL_343
+#define LPDDR4__RDLVL_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_ROTATE
+
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET 0U
+#define LPDDR4__RDLVL_GATE_ROTATE__REG DENALI_CTL_343
+#define LPDDR4__RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE
+
+#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT 16U
+#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH 2U
+#define LPDDR4__RDLVL_CS_MAP__REG DENALI_CTL_343
+#define LPDDR4__RDLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP
+
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT 24U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH 2U
+#define LPDDR4__RDLVL_GATE_CS_MAP__REG DENALI_CTL_343
+#define LPDDR4__RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP
+
+#define LPDDR4__DENALI_CTL_344_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_344
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_344
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_345_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__RDLVL_TIMEOUT_F0__REG DENALI_CTL_345
+#define LPDDR4__RDLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_345
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_346_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_346
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__REG DENALI_CTL_346
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_347_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__REG DENALI_CTL_347
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__REG DENALI_CTL_347
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_348_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_349_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_349
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_349
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_350_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__RDLVL_TIMEOUT_F1__REG DENALI_CTL_350
+#define LPDDR4__RDLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_350
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_351_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_351_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_351
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__REG DENALI_CTL_351
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_352_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__REG DENALI_CTL_352
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__REG DENALI_CTL_352
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_353_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_354_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_354
+#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_354
+#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_355_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__RDLVL_TIMEOUT_F2__REG DENALI_CTL_355
+#define LPDDR4__RDLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_355
+#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_356_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_356
+#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__REG DENALI_CTL_356
+#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_357_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__REG DENALI_CTL_357
+#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__REG DENALI_CTL_357
+#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_358_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
+#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
+#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_359_READ_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_359_WRITE_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT 0U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET 0U
+#define LPDDR4__CALVL_REQ__REG DENALI_CTL_359
+#define LPDDR4__CALVL_REQ__FLD LPDDR4__DENALI_CTL_359__CALVL_REQ
+
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET 0U
+#define LPDDR4__CALVL_CS__REG DENALI_CTL_359
+#define LPDDR4__CALVL_CS__FLD LPDDR4__DENALI_CTL_359__CALVL_CS
+
+#define LPDDR4__DENALI_CTL_360_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_360_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH 20U
+#define LPDDR4__CALVL_PAT_0__REG DENALI_CTL_360
+#define LPDDR4__CALVL_PAT_0__FLD LPDDR4__DENALI_CTL_360__CALVL_PAT_0
+
+#define LPDDR4__DENALI_CTL_361_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_361_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH 20U
+#define LPDDR4__CALVL_BG_PAT_0__REG DENALI_CTL_361
+#define LPDDR4__CALVL_BG_PAT_0__FLD LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0
+
+#define LPDDR4__DENALI_CTL_362_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_362_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH 20U
+#define LPDDR4__CALVL_PAT_1__REG DENALI_CTL_362
+#define LPDDR4__CALVL_PAT_1__FLD LPDDR4__DENALI_CTL_362__CALVL_PAT_1
+
+#define LPDDR4__DENALI_CTL_363_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_363_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH 20U
+#define LPDDR4__CALVL_BG_PAT_1__REG DENALI_CTL_363
+#define LPDDR4__CALVL_BG_PAT_1__FLD LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1
+
+#define LPDDR4__DENALI_CTL_364_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_364_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH 20U
+#define LPDDR4__CALVL_PAT_2__REG DENALI_CTL_364
+#define LPDDR4__CALVL_PAT_2__FLD LPDDR4__DENALI_CTL_364__CALVL_PAT_2
+
+#define LPDDR4__DENALI_CTL_365_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_365_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH 20U
+#define LPDDR4__CALVL_BG_PAT_2__REG DENALI_CTL_365
+#define LPDDR4__CALVL_BG_PAT_2__FLD LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2
+
+#define LPDDR4__DENALI_CTL_366_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_366_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH 20U
+#define LPDDR4__CALVL_PAT_3__REG DENALI_CTL_366
+#define LPDDR4__CALVL_PAT_3__FLD LPDDR4__DENALI_CTL_366__CALVL_PAT_3
+
+#define LPDDR4__DENALI_CTL_367_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_367_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH 20U
+#define LPDDR4__CALVL_BG_PAT_3__REG DENALI_CTL_367
+#define LPDDR4__CALVL_BG_PAT_3__FLD LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3
+
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT 24U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH 1U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR 0U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET 0U
+#define LPDDR4__MC_RESERVED30__REG DENALI_CTL_367
+#define LPDDR4__MC_RESERVED30__FLD LPDDR4__DENALI_CTL_367__MC_RESERVED30
+
+#define LPDDR4__DENALI_CTL_368_READ_MASK 0x0101030FU
+#define LPDDR4__DENALI_CTL_368_WRITE_MASK 0x0101030FU
+#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT 0U
+#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH 4U
+#define LPDDR4__MC_RESERVED31__REG DENALI_CTL_368
+#define LPDDR4__MC_RESERVED31__FLD LPDDR4__DENALI_CTL_368__MC_RESERVED31
+
+#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH 2U
+#define LPDDR4__CALVL_SEQ_EN__REG DENALI_CTL_368
+#define LPDDR4__CALVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN
+
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET 0U
+#define LPDDR4__DFI_PHY_CALVL_MODE__REG DENALI_CTL_368
+#define LPDDR4__DFI_PHY_CALVL_MODE__FLD LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE
+
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT 24U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET 0U
+#define LPDDR4__CALVL_PERIODIC__REG DENALI_CTL_368
+#define LPDDR4__CALVL_PERIODIC__FLD LPDDR4__DENALI_CTL_368__CALVL_PERIODIC
+
+#define LPDDR4__DENALI_CTL_369_READ_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_369_WRITE_MASK 0x03010101U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__CALVL_ON_SREF_EXIT__REG DENALI_CTL_369
+#define LPDDR4__CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET 0U
+#define LPDDR4__CALVL_AREF_EN__REG DENALI_CTL_369
+#define LPDDR4__CALVL_AREF_EN__FLD LPDDR4__DENALI_CTL_369__CALVL_AREF_EN
+
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET 0U
+#define LPDDR4__CALVL_ROTATE__REG DENALI_CTL_369
+#define LPDDR4__CALVL_ROTATE__FLD LPDDR4__DENALI_CTL_369__CALVL_ROTATE
+
+#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT 24U
+#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH 2U
+#define LPDDR4__CALVL_CS_MAP__REG DENALI_CTL_369
+#define LPDDR4__CALVL_CS_MAP__FLD LPDDR4__DENALI_CTL_369__CALVL_CS_MAP
+
+#define LPDDR4__DENALI_CTL_370_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_370_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__CALVL_NORM_THRESHOLD_F0__REG DENALI_CTL_370
+#define LPDDR4__CALVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_370
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_371_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH 16U
+#define LPDDR4__CALVL_TIMEOUT_F0__REG DENALI_CTL_371
+#define LPDDR4__CALVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_371
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_372_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_372
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__CALVL_NORM_THRESHOLD_F1__REG DENALI_CTL_372
+#define LPDDR4__CALVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_373_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_373
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH 16U
+#define LPDDR4__CALVL_TIMEOUT_F1__REG DENALI_CTL_373
+#define LPDDR4__CALVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_374_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_375_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__CALVL_NORM_THRESHOLD_F2__REG DENALI_CTL_375
+#define LPDDR4__CALVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_375
+#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_376_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH 16U
+#define LPDDR4__CALVL_TIMEOUT_F2__REG DENALI_CTL_376
+#define LPDDR4__CALVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_376
+#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_377_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_377_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_377
+#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_377
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE
+
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_377
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE
+
+#define LPDDR4__DENALI_CTL_378_READ_MASK 0x00000707U
+#define LPDDR4__DENALI_CTL_378_WRITE_MASK 0x00000707U
+#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH 3U
+#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_378
+#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY
+
+#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT 8U
+#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH 3U
+#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_378
+#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY
+
+#define LPDDR4__DENALI_CTL_379_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH 32U
+#define LPDDR4__PARITY_ERROR_ADDRESS_0__REG DENALI_CTL_379
+#define LPDDR4__PARITY_ERROR_ADDRESS_0__FLD LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_380_READ_MASK 0x1FFF3F07U
+#define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x1FFF3F07U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH 3U
+#define LPDDR4__PARITY_ERROR_ADDRESS_1__REG DENALI_CTL_380
+#define LPDDR4__PARITY_ERROR_ADDRESS_1__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_MASK 0x00003F00U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT 8U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH 6U
+#define LPDDR4__PARITY_ERROR_MASTER_ID__REG DENALI_CTL_380
+#define LPDDR4__PARITY_ERROR_MASTER_ID__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID
+
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_MASK 0x1FFF0000U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_SHIFT 16U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_WIDTH 13U
+#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__REG DENALI_CTL_380
+#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL
+
+#define LPDDR4__DENALI_CTL_381_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_WIDTH 32U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__REG DENALI_CTL_381
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__FLD LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0
+
+#define LPDDR4__DENALI_CTL_382_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_382_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_WIDTH 32U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__REG DENALI_CTL_382
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__FLD LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1
+
+#define LPDDR4__DENALI_CTL_383_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_383_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_WIDTH 32U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__REG DENALI_CTL_383
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__FLD LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2
+
+#define LPDDR4__DENALI_CTL_384_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_384_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_WIDTH 32U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__REG DENALI_CTL_384
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__FLD LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3
+
+#define LPDDR4__DENALI_CTL_385_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_SHIFT 0U
+#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_WIDTH 16U
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__REG DENALI_CTL_385
+#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__FLD LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR
+
+#define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK 0x00030000U
+#define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH 2U
+#define LPDDR4__CKE_STATUS__REG DENALI_CTL_385
+#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_385__CKE_STATUS
+
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT 24U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH 1U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR 0U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET 0U
+#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_385
+#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_385__MEM_RST_VALID
+
+#define LPDDR4__DENALI_CTL_386_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_386_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH 16U
+#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_386
+#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_DELAY
+
+#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT 16U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH 8U
+#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_386
+#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT 24U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH 7U
+#define LPDDR4__TDFI_PHY_WRLAT__REG DENALI_CTL_386
+#define LPDDR4__TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT
+
+#define LPDDR4__DENALI_CTL_387_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_387_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH 7U
+#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_387
+#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH 7U
+#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_387
+#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0
+
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH 7U
+#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_387
+#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1
+
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH 7U
+#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_387
+#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2
+
+#define LPDDR4__DENALI_CTL_388_READ_MASK 0x00FF037FU
+#define LPDDR4__DENALI_CTL_388_WRITE_MASK 0x00FF037FU
+#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH 7U
+#define LPDDR4__TDFI_RDDATA_EN__REG DENALI_CTL_388
+#define LPDDR4__TDFI_RDDATA_EN__FLD LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN
+
+#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH 2U
+#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_388
+#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH 8U
+#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_388
+#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_CTL_389_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_389_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH 21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_389
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_CTL_390_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_390_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_390
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_391_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_391
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_392_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_392_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_393_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_393_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_393
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_394_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH 23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_394
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0
+
+#define LPDDR4__DENALI_CTL_395_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_395
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_CTL_396_READ_MASK 0x00007F7FU
+#define LPDDR4__DENALI_CTL_396_WRITE_MASK 0x00007F7FU
+#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH 7U
+#define LPDDR4__RDLAT_ADJ_F0__REG DENALI_CTL_396
+#define LPDDR4__RDLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT 8U
+#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH 7U
+#define LPDDR4__WRLAT_ADJ_F0__REG DENALI_CTL_396
+#define LPDDR4__WRLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_CTL_397_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH 21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_397
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_398
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_399_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_399
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_400
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_402_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH 23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1
+
+#define LPDDR4__DENALI_CTL_403_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_403
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_CTL_404_READ_MASK 0x00007F7FU
+#define LPDDR4__DENALI_CTL_404_WRITE_MASK 0x00007F7FU
+#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH 7U
+#define LPDDR4__RDLAT_ADJ_F1__REG DENALI_CTL_404
+#define LPDDR4__RDLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH 7U
+#define LPDDR4__WRLAT_ADJ_F1__REG DENALI_CTL_404
+#define LPDDR4__WRLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_CTL_405_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_405_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH 21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_405
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_CTL_406_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_406
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_407
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_408_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_408
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_409
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_410_READ_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_410_WRITE_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH 23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2
+
+#define LPDDR4__DENALI_CTL_411_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_411
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_CTL_412_READ_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_412_WRITE_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH 7U
+#define LPDDR4__RDLAT_ADJ_F2__REG DENALI_CTL_412
+#define LPDDR4__RDLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH 7U
+#define LPDDR4__WRLAT_ADJ_F2__REG DENALI_CTL_412
+#define LPDDR4__WRLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH 4U
+#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_412
+#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH 4U
+#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_412
+#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_CTL_413_READ_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_413_WRITE_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH 4U
+#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_413
+#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT 8U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH 4U
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH 4U
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE
+
+#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH 8U
+#define LPDDR4__TDFI_WRLVL_EN__REG DENALI_CTL_413
+#define LPDDR4__TDFI_WRLVL_EN__FLD LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN
+
+#define LPDDR4__DENALI_CTL_414_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_414_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT 0U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH 10U
+#define LPDDR4__TDFI_WRLVL_WW__REG DENALI_CTL_414
+#define LPDDR4__TDFI_WRLVL_WW__FLD LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW
+
+#define LPDDR4__DENALI_CTL_415_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_415_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH 32U
+#define LPDDR4__TDFI_WRLVL_RESP__REG DENALI_CTL_415
+#define LPDDR4__TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP
+
+#define LPDDR4__DENALI_CTL_416_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH 32U
+#define LPDDR4__TDFI_WRLVL_MAX__REG DENALI_CTL_416
+#define LPDDR4__TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX
+
+#define LPDDR4__DENALI_CTL_417_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_417_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH 8U
+#define LPDDR4__TDFI_RDLVL_EN__REG DENALI_CTL_417
+#define LPDDR4__TDFI_RDLVL_EN__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN
+
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK 0x0003FF00U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT 8U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH 10U
+#define LPDDR4__TDFI_RDLVL_RR__REG DENALI_CTL_417
+#define LPDDR4__TDFI_RDLVL_RR__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR
+
+#define LPDDR4__DENALI_CTL_418_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH 32U
+#define LPDDR4__TDFI_RDLVL_RESP__REG DENALI_CTL_418
+#define LPDDR4__TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP
+
+#define LPDDR4__DENALI_CTL_419_READ_MASK 0x000101FFU
+#define LPDDR4__DENALI_CTL_419_WRITE_MASK 0x000101FFU
+#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH 8U
+#define LPDDR4__RDLVL_RESP_MASK__REG DENALI_CTL_419
+#define LPDDR4__RDLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK
+
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET 0U
+#define LPDDR4__RDLVL_EN__REG DENALI_CTL_419
+#define LPDDR4__RDLVL_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_EN
+
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET 0U
+#define LPDDR4__RDLVL_GATE_EN__REG DENALI_CTL_419
+#define LPDDR4__RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN
+
+#define LPDDR4__DENALI_CTL_420_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_420_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH 32U
+#define LPDDR4__TDFI_RDLVL_MAX__REG DENALI_CTL_420
+#define LPDDR4__TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX
+
+#define LPDDR4__DENALI_CTL_421_READ_MASK 0x00FF0707U
+#define LPDDR4__DENALI_CTL_421_WRITE_MASK 0x00FF0707U
+#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH 3U
+#define LPDDR4__RDLVL_ERROR_STATUS__REG DENALI_CTL_421
+#define LPDDR4__RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH 3U
+#define LPDDR4__RDLVL_GATE_ERROR_STATUS__REG DENALI_CTL_421
+#define LPDDR4__RDLVL_GATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH 8U
+#define LPDDR4__TDFI_CALVL_EN__REG DENALI_CTL_421
+#define LPDDR4__TDFI_CALVL_EN__FLD LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN
+
+#define LPDDR4__DENALI_CTL_422_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_422_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH 10U
+#define LPDDR4__TDFI_CALVL_CC_F0__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0
+
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH 10U
+#define LPDDR4__TDFI_CALVL_CAPTURE_F0__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0
+
+#define LPDDR4__DENALI_CTL_423_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_423_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH 10U
+#define LPDDR4__TDFI_CALVL_CC_F1__REG DENALI_CTL_423
+#define LPDDR4__TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1
+
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT 16U
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH 10U
+#define LPDDR4__TDFI_CALVL_CAPTURE_F1__REG DENALI_CTL_423
+#define LPDDR4__TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1
+
+#define LPDDR4__DENALI_CTL_424_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_424_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH 10U
+#define LPDDR4__TDFI_CALVL_CC_F2__REG DENALI_CTL_424
+#define LPDDR4__TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2
+
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH 10U
+#define LPDDR4__TDFI_CALVL_CAPTURE_F2__REG DENALI_CTL_424
+#define LPDDR4__TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2
+
+#define LPDDR4__DENALI_CTL_425_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_425_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH 32U
+#define LPDDR4__TDFI_CALVL_RESP__REG DENALI_CTL_425
+#define LPDDR4__TDFI_CALVL_RESP__FLD LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP
+
+#define LPDDR4__DENALI_CTL_426_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_426_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH 32U
+#define LPDDR4__TDFI_CALVL_MAX__REG DENALI_CTL_426
+#define LPDDR4__TDFI_CALVL_MAX__FLD LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX
+
+#define LPDDR4__DENALI_CTL_427_READ_MASK 0x070F0101U
+#define LPDDR4__DENALI_CTL_427_WRITE_MASK 0x070F0101U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH 1U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR 0U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET 0U
+#define LPDDR4__CALVL_RESP_MASK__REG DENALI_CTL_427
+#define LPDDR4__CALVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK
+
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET 0U
+#define LPDDR4__CALVL_EN__REG DENALI_CTL_427
+#define LPDDR4__CALVL_EN__FLD LPDDR4__DENALI_CTL_427__CALVL_EN
+
+#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH 4U
+#define LPDDR4__CALVL_ERROR_STATUS__REG DENALI_CTL_427
+#define LPDDR4__CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH 3U
+#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_427
+#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_CTL_428_READ_MASK 0x7F7F0707U
+#define LPDDR4__DENALI_CTL_428_WRITE_MASK 0x7F7F0707U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH 3U
+#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_428
+#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT 8U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH 3U
+#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_428
+#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH 7U
+#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_428
+#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT 24U
+#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH 7U
+#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_428
+#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_429_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_429_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH 7U
+#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_429
+#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT 8U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH 7U
+#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_429
+#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT 16U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH 7U
+#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_429
+#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT 24U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH 7U
+#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_429
+#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_430_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_CTL_430_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT 0U
+#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH 8U
+#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_430
+#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY
+
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT 8U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH 1U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR 0U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET 0U
+#define LPDDR4__EN_1T_TIMING__REG DENALI_CTL_430
+#define LPDDR4__EN_1T_TIMING__FLD LPDDR4__DENALI_CTL_430__EN_1T_TIMING
+
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_SHIFT 16U
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_430
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE
+
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET 0U
+#define LPDDR4__BL_ON_FLY_ENABLE__REG DENALI_CTL_430
+#define LPDDR4__BL_ON_FLY_ENABLE__FLD LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE
+
+#define LPDDR4__DENALI_CTL_431_READ_MASK 0x07070701U
+#define LPDDR4__DENALI_CTL_431_WRITE_MASK 0x07070701U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT 0U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH 1U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR 0U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET 0U
+#define LPDDR4__MC_RESERVED32__REG DENALI_CTL_431
+#define LPDDR4__MC_RESERVED32__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED32
+
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT 8U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH 3U
+#define LPDDR4__MC_RESERVED33__REG DENALI_CTL_431
+#define LPDDR4__MC_RESERVED33__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED33
+
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT 16U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH 3U
+#define LPDDR4__MC_RESERVED34__REG DENALI_CTL_431
+#define LPDDR4__MC_RESERVED34__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED34
+
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK 0x07000000U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT 24U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH 3U
+#define LPDDR4__MC_RESERVED35__REG DENALI_CTL_431
+#define LPDDR4__MC_RESERVED35__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED35
+
+#define LPDDR4__DENALI_CTL_432_READ_MASK 0x0F070707U
+#define LPDDR4__DENALI_CTL_432_WRITE_MASK 0x0F070707U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT 0U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH 3U
+#define LPDDR4__MC_RESERVED36__REG DENALI_CTL_432
+#define LPDDR4__MC_RESERVED36__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED36
+
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK 0x00000700U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT 8U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH 3U
+#define LPDDR4__MC_RESERVED37__REG DENALI_CTL_432
+#define LPDDR4__MC_RESERVED37__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED37
+
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK 0x00070000U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT 16U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH 3U
+#define LPDDR4__MC_RESERVED38__REG DENALI_CTL_432
+#define LPDDR4__MC_RESERVED38__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED38
+
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT 24U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH 4U
+#define LPDDR4__MC_RESERVED39__REG DENALI_CTL_432
+#define LPDDR4__MC_RESERVED39__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED39
+
+#define LPDDR4__DENALI_CTL_433_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_433_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT 0U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH 4U
+#define LPDDR4__MC_RESERVED40__REG DENALI_CTL_433
+#define LPDDR4__MC_RESERVED40__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED40
+
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT 8U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH 4U
+#define LPDDR4__MC_RESERVED41__REG DENALI_CTL_433
+#define LPDDR4__MC_RESERVED41__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED41
+
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT 16U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH 4U
+#define LPDDR4__MC_RESERVED42__REG DENALI_CTL_433
+#define LPDDR4__MC_RESERVED42__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED42
+
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT 24U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH 4U
+#define LPDDR4__MC_RESERVED43__REG DENALI_CTL_433
+#define LPDDR4__MC_RESERVED43__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED43
+
+#define LPDDR4__DENALI_CTL_434_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_434_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT 0U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH 4U
+#define LPDDR4__MC_RESERVED44__REG DENALI_CTL_434
+#define LPDDR4__MC_RESERVED44__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED44
+
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT 8U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH 4U
+#define LPDDR4__MC_RESERVED45__REG DENALI_CTL_434
+#define LPDDR4__MC_RESERVED45__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED45
+
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT 16U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH 4U
+#define LPDDR4__MC_RESERVED46__REG DENALI_CTL_434
+#define LPDDR4__MC_RESERVED46__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED46
+
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT 24U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH 4U
+#define LPDDR4__MC_RESERVED47__REG DENALI_CTL_434
+#define LPDDR4__MC_RESERVED47__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED47
+
+#define LPDDR4__DENALI_CTL_435_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_435_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT 0U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH 4U
+#define LPDDR4__MC_RESERVED48__REG DENALI_CTL_435
+#define LPDDR4__MC_RESERVED48__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED48
+
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT 8U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH 4U
+#define LPDDR4__MC_RESERVED49__REG DENALI_CTL_435
+#define LPDDR4__MC_RESERVED49__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED49
+
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT 16U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH 4U
+#define LPDDR4__MC_RESERVED50__REG DENALI_CTL_435
+#define LPDDR4__MC_RESERVED50__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED50
+
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT 24U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH 4U
+#define LPDDR4__MC_RESERVED51__REG DENALI_CTL_435
+#define LPDDR4__MC_RESERVED51__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED51
+
+#define LPDDR4__DENALI_CTL_436_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_436_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT 0U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH 4U
+#define LPDDR4__MC_RESERVED52__REG DENALI_CTL_436
+#define LPDDR4__MC_RESERVED52__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED52
+
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT 8U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH 4U
+#define LPDDR4__MC_RESERVED53__REG DENALI_CTL_436
+#define LPDDR4__MC_RESERVED53__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED53
+
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT 16U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH 4U
+#define LPDDR4__MC_RESERVED54__REG DENALI_CTL_436
+#define LPDDR4__MC_RESERVED54__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED54
+
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT 24U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH 4U
+#define LPDDR4__MC_RESERVED55__REG DENALI_CTL_436
+#define LPDDR4__MC_RESERVED55__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED55
+
+#define LPDDR4__DENALI_CTL_437_READ_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_437_WRITE_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT 0U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH 4U
+#define LPDDR4__MC_RESERVED56__REG DENALI_CTL_437
+#define LPDDR4__MC_RESERVED56__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED56
+
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT 8U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH 4U
+#define LPDDR4__MC_RESERVED57__REG DENALI_CTL_437
+#define LPDDR4__MC_RESERVED57__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED57
+
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT 16U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH 4U
+#define LPDDR4__MC_RESERVED58__REG DENALI_CTL_437
+#define LPDDR4__MC_RESERVED58__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED58
+
+#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT 24U
+#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH 8U
+#define LPDDR4__GLOBAL_ERROR_INFO__REG DENALI_CTL_437
+#define LPDDR4__GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO
+
+#define LPDDR4__DENALI_CTL_438_READ_MASK 0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_438_WRITE_MASK 0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT 0U
+#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH 8U
+#define LPDDR4__GLOBAL_ERROR_MASK__REG DENALI_CTL_438
+#define LPDDR4__GLOBAL_ERROR_MASK__FLD LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK
+
+#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_MASK 0x00000300U
+#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__AXI_PARITY_ERROR_STATUS__REG DENALI_CTL_438
+#define LPDDR4__AXI_PARITY_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_438__NWR_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT 16U
+#define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH 8U
+#define LPDDR4__NWR_F0__REG DENALI_CTL_438
+#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_438__NWR_F0
+
+#define LPDDR4__DENALI_CTL_438__NWR_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT 24U
+#define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH 8U
+#define LPDDR4__NWR_F1__REG DENALI_CTL_438
+#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_438__NWR_F1
+
+#define LPDDR4__DENALI_CTL_439_READ_MASK 0x001F01FFU
+#define LPDDR4__DENALI_CTL_439_WRITE_MASK 0x001F01FFU
+#define LPDDR4__DENALI_CTL_439__NWR_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH 8U
+#define LPDDR4__NWR_F2__REG DENALI_CTL_439
+#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_439__NWR_F2
+
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT 8U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH 1U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR 0U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET 0U
+#define LPDDR4__MC_RESERVED59__REG DENALI_CTL_439
+#define LPDDR4__MC_RESERVED59__FLD LPDDR4__DENALI_CTL_439__MC_RESERVED59
+
+#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_MASK 0x001F0000U
+#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_WIDTH 5U
+#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__REG DENALI_CTL_439
+#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS
+
+#define LPDDR4__DENALI_CTL_440_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_440_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_WIDTH 32U
+#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__REG DENALI_CTL_440
+#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__FLD LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0
+
+#define LPDDR4__DENALI_CTL_441_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_441_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_WIDTH 32U
+#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__REG DENALI_CTL_441
+#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__FLD LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1
+
+#define LPDDR4__DENALI_CTL_442_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_442_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT 0U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH 1U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR 0U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET 0U
+#define LPDDR4__MC_PARITY_ERROR_TYPE__REG DENALI_CTL_442
+#define LPDDR4__MC_PARITY_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE
+
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__REG DENALI_CTL_442
+#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__REG DENALI_CTL_442
+#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__REG DENALI_CTL_442
+#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_443_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_443_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__REG DENALI_CTL_443
+#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOSET 0U
+#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__REG DENALI_CTL_443
+#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
+#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_SHIFT 24U
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
+#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_444_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_444_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_SHIFT 0U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
+#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
+#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
+#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
+#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN
+
+#define LPDDR4__DENALI_CTL_445_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_445_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH 32U
+#define LPDDR4__MC_RESERVED60_0__REG DENALI_CTL_445
+#define LPDDR4__MC_RESERVED60_0__FLD LPDDR4__DENALI_CTL_445__MC_RESERVED60_0
+
+#define LPDDR4__DENALI_CTL_446_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_446_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH 32U
+#define LPDDR4__MC_RESERVED60_1__REG DENALI_CTL_446
+#define LPDDR4__MC_RESERVED60_1__FLD LPDDR4__DENALI_CTL_446__MC_RESERVED60_1
+
+#define LPDDR4__DENALI_CTL_447_READ_MASK 0x00000107U
+#define LPDDR4__DENALI_CTL_447_WRITE_MASK 0x00000107U
+#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH 3U
+#define LPDDR4__MC_RESERVED60_2__REG DENALI_CTL_447
+#define LPDDR4__MC_RESERVED60_2__FLD LPDDR4__DENALI_CTL_447__MC_RESERVED60_2
+
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_SHIFT 8U
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WIDTH 1U
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOCLR 0U
+#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOSET 0U
+#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__REG DENALI_CTL_447
+#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN
+
+#define LPDDR4__DENALI_CTL_448_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_448_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_WIDTH 32U
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__REG DENALI_CTL_448
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__FLD LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0
+
+#define LPDDR4__DENALI_CTL_449_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_449_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_WIDTH 32U
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__REG DENALI_CTL_449
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__FLD LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1
+
+#define LPDDR4__DENALI_CTL_450_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_450_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_MASK 0x00000007U
+#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_WIDTH 3U
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__REG DENALI_CTL_450
+#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__FLD LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2
+
+#define LPDDR4__DENALI_CTL_451_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_451_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH 32U
+#define LPDDR4__MC_RESERVED61_0__REG DENALI_CTL_451
+#define LPDDR4__MC_RESERVED61_0__FLD LPDDR4__DENALI_CTL_451__MC_RESERVED61_0
+
+#define LPDDR4__DENALI_CTL_452_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_452_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH 32U
+#define LPDDR4__MC_RESERVED61_1__REG DENALI_CTL_452
+#define LPDDR4__MC_RESERVED61_1__FLD LPDDR4__DENALI_CTL_452__MC_RESERVED61_1
+
+#define LPDDR4__DENALI_CTL_453_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_453_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH 32U
+#define LPDDR4__MC_RESERVED61_2__REG DENALI_CTL_453
+#define LPDDR4__MC_RESERVED61_2__FLD LPDDR4__DENALI_CTL_453__MC_RESERVED61_2
+
+#define LPDDR4__DENALI_CTL_454_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_454_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH 4U
+#define LPDDR4__MC_RESERVED61_3__REG DENALI_CTL_454
+#define LPDDR4__MC_RESERVED61_3__FLD LPDDR4__DENALI_CTL_454__MC_RESERVED61_3
+
+#define LPDDR4__DENALI_CTL_455_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_455_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_SHIFT 0U
+#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_WIDTH 32U
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__REG DENALI_CTL_455
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__FLD LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0
+
+#define LPDDR4__DENALI_CTL_456_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_456_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_SHIFT 0U
+#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_WIDTH 32U
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__REG DENALI_CTL_456
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__FLD LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1
+
+#define LPDDR4__DENALI_CTL_457_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_457_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_SHIFT 0U
+#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_WIDTH 32U
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__REG DENALI_CTL_457
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__FLD LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2
+
+#define LPDDR4__DENALI_CTL_458_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_458_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_MASK 0x0000000FU
+#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_SHIFT 0U
+#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_WIDTH 4U
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__REG DENALI_CTL_458
+#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__FLD LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3
+
+#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
similarity index 60%
rename from drivers/ram/k3-j721e/lpddr4_phy_core_macros.h
rename to drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
index e8579ff..d8c7a52 100644
--- a/drivers/ram/k3-j721e/lpddr4_phy_core_macros.h
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
@@ -1,30 +1,29 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+/*
+ * Cadence DDR Driver
*
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
*/
#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
#define REG_LPDDR4_PHY_CORE_MACROS_H_
-#define LPDDR4__DENALI_PHY_1280_READ_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH 2U
+#define LPDDR4__DENALI_PHY_1280_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1280_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH 2U
#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1280
#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL
-#define LPDDR4__DENALI_PHY_1281_READ_MASK 0x1F030101U
-#define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0x1F030101U
+#define LPDDR4__DENALI_PHY_1281_READ_MASK 0x1F030101U
+#define LPDDR4__DENALI_PHY_1281_WRITE_MASK 0x1F030101U
#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET 0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET 0U
#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1281
#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF
@@ -37,65 +36,65 @@
#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN
#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH 2U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH 2U
#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1281
#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX
#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1281
#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0
-#define LPDDR4__DENALI_PHY_1282_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282_READ_MASK 0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282_WRITE_MASK 0x1F1F1F1FU
#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1282
#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0
#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1282
#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0
#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH 5U
#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1282
#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0
#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_MASK 0x1F000000U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1282
#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1
-#define LPDDR4__DENALI_PHY_1283_READ_MASK 0x001F1F1FU
-#define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1283_READ_MASK 0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1283_WRITE_MASK 0x001F1F1FU
#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_MASK 0x0000001FU
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1283
#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1
#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_MASK 0x00001F00U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1283
#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1
#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH 5U
#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1283
#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1
-#define LPDDR4__DENALI_PHY_1284_READ_MASK 0x011F07FFU
-#define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x011F07FFU
+#define LPDDR4__DENALI_PHY_1284_READ_MASK 0x011F07FFU
+#define LPDDR4__DENALI_PHY_1284_WRITE_MASK 0x011F07FFU
#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT 0U
#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH 11U
@@ -104,25 +103,25 @@
#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_MASK 0x001F0000U
#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT_WIDTH 5U
#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1284
#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP_BYPASS_SHIFT
#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE_WOSET 0U
#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1284
#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1284__PHY_GRP_BYPASS_OVERRIDE
-#define LPDDR4__DENALI_PHY_1285_READ_MASK 0x07FF0100U
-#define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x07FF0100U
+#define LPDDR4__DENALI_PHY_1285_READ_MASK 0x07FF0100U
+#define LPDDR4__DENALI_PHY_1285_WRITE_MASK 0x07FF0100U
#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE_WOSET 0U
#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1285
#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1285__SC_PHY_MANUAL_UPDATE
@@ -134,75 +133,75 @@
#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1285
#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1285__PHY_MANUAL_UPDATE_PHYUPD_ENABLE
-#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START_WIDTH 11U
#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1285
#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1285__PHY_CSLVL_START
-#define LPDDR4__DENALI_PHY_1286_READ_MASK 0x000107FFU
-#define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1286_READ_MASK 0x000107FFU
+#define LPDDR4__DENALI_PHY_1286_WRITE_MASK 0x000107FFU
#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY_WIDTH 11U
#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1286
#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_COARSE_DLY
#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE_WOSET 0U
#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1286
#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1286__PHY_CSLVL_DEBUG_MODE
#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOSET 0U
+#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT_WOSET 0U
#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1286
#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1286__SC_PHY_CSLVL_DEBUG_CONT
#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOSET 0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR_WOSET 0U
#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1287
#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1287__SC_PHY_CSLVL_ERROR_CLR
-#define LPDDR4__DENALI_PHY_1288_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1288_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1288_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0_WIDTH 32U
#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1288
#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_OBS0
-#define LPDDR4__DENALI_PHY_1289_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1289_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1289_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1_WIDTH 32U
#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1289
#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1289__PHY_CSLVL_OBS1
-#define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1290_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2_WIDTH 32U
#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1290
#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS2
-#define LPDDR4__DENALI_PHY_1291_READ_MASK 0x0101FF01U
-#define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0x0101FF01U
+#define LPDDR4__DENALI_PHY_1291_READ_MASK 0x0101FF01U
+#define LPDDR4__DENALI_PHY_1291_WRITE_MASK 0x0101FF01U
#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE_WOSET 0U
#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1291
#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_ENABLE
@@ -213,32 +212,32 @@
#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_PERIODIC_START_OFFSET
#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE_WOSET 0U
#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1291
#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1291__PHY_LP4_BOOT_DISABLE
-#define LPDDR4__DENALI_PHY_1292_READ_MASK 0x0007FF0FU
-#define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0x0007FF0FU
+#define LPDDR4__DENALI_PHY_1292_READ_MASK 0x0007FF0FU
+#define LPDDR4__DENALI_PHY_1292_WRITE_MASK 0x0007FF0FU
#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP_WIDTH 4U
#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1292
#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_CS_MAP
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_MASK 0x0007FF00U
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR_WIDTH 11U
#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1292
#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_QTR
-#define LPDDR4__DENALI_PHY_1293_READ_MASK 0xFF0F07FFU
-#define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0xFF0F07FFU
+#define LPDDR4__DENALI_PHY_1293_READ_MASK 0xFF0F07FFU
+#define LPDDR4__DENALI_PHY_1293_WRITE_MASK 0xFF0F07FFU
#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK_WIDTH 11U
#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1293
#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CHK
@@ -249,13 +248,13 @@
#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_COARSE_CAPTURE_CNT
#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP_WIDTH 8U
#define LPDDR4__PHY_CALVL_CS_MAP__REG DENALI_PHY_1293
#define LPDDR4__PHY_CALVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1293__PHY_CALVL_CS_MAP
-#define LPDDR4__DENALI_PHY_1294_READ_MASK 0x01030007U
-#define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x01030007U
+#define LPDDR4__DENALI_PHY_1294_READ_MASK 0x01030007U
+#define LPDDR4__DENALI_PHY_1294_WRITE_MASK 0x01030007U
#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH 3U
@@ -271,34 +270,34 @@
#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_SNAP_OBS_REGS
#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_MASK 0x00030000U
-#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_WIDTH 2U
+#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE_WIDTH 2U
#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1294
#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1294__PHY_DFI_PHYUPD_TYPE
#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOSET 0U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR_WOSET 0U
#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1294
#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1294__PHY_ADRCTL_LPDDR
-#define LPDDR4__DENALI_PHY_1295_READ_MASK 0xFFFF0101U
-#define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0xFFFF0101U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1295_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1295_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE_WOSET 0U
#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1295
#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1295__PHY_LP4_ACTIVE
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOSET 0U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS_WOSET 0U
#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1295
#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1295__PHY_LPDDR3_CS
@@ -309,30 +308,30 @@
#define LPDDR4__PHY_CLK_DC_CAL_SAMPLE_WAIT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_SAMPLE_WAIT
#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_MASK 0xFF000000U
-#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT_WIDTH 8U
#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__REG DENALI_PHY_1295
#define LPDDR4__PHY_CLK_DC_CAL_TIMEOUT__FLD LPDDR4__DENALI_PHY_1295__PHY_CLK_DC_CAL_TIMEOUT
-#define LPDDR4__DENALI_PHY_1296_READ_MASK 0xFF3F0103U
-#define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0xFF3F0103U
+#define LPDDR4__DENALI_PHY_1296_READ_MASK 0xFF3F0103U
+#define LPDDR4__DENALI_PHY_1296_WRITE_MASK 0xFF3F0103U
#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_WIDTH 2U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT_WIDTH 2U
#define LPDDR4__PHY_CLK_DC_WEIGHT__REG DENALI_PHY_1296
#define LPDDR4__PHY_CLK_DC_WEIGHT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_WEIGHT
#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET 0U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ_WOSET 0U
#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__REG DENALI_PHY_1296
#define LPDDR4__PHY_CLK_DC_FREQ_CHG_ADJ__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_FREQ_CHG_ADJ
#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_WIDTH 6U
+#define LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START_WIDTH 6U
#define LPDDR4__PHY_CLK_DC_ADJUST_START__REG DENALI_PHY_1296
#define LPDDR4__PHY_CLK_DC_ADJUST_START__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_START
@@ -342,8 +341,8 @@
#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__REG DENALI_PHY_1296
#define LPDDR4__PHY_CLK_DC_ADJUST_SAMPLE_CNT__FLD LPDDR4__DENALI_PHY_1296__PHY_CLK_DC_ADJUST_SAMPLE_CNT
-#define LPDDR4__DENALI_PHY_1297_READ_MASK 0x010101FFU
-#define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_1297_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_1297_WRITE_MASK 0x010101FFU
#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_SHIFT 0U
#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_ADJUST_THRSHLD_WIDTH 8U
@@ -360,22 +359,22 @@
#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOSET 0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY_WOSET 0U
#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__REG DENALI_PHY_1297
#define LPDDR4__PHY_CLK_DC_CAL_POLARITY__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_POLARITY
#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOSET 0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START_WOSET 0U
#define LPDDR4__PHY_CLK_DC_CAL_START__REG DENALI_PHY_1297
#define LPDDR4__PHY_CLK_DC_CAL_START__FLD LPDDR4__DENALI_PHY_1297__PHY_CLK_DC_CAL_START
-#define LPDDR4__DENALI_PHY_1298_READ_MASK 0x0F0F0100U
-#define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0x0F0F0100U
+#define LPDDR4__DENALI_PHY_1298_READ_MASK 0x0F0F0100U
+#define LPDDR4__DENALI_PHY_1298_WRITE_MASK 0x0F0F0100U
#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT 0U
#define LPDDR4__DENALI_PHY_1298__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH 1U
@@ -393,24 +392,24 @@
#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1298__PHY_CONTINUOUS_CLK_CAL_UPDATE
#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0_WIDTH 4U
#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1298
#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_0
#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_MASK 0x0F000000U
-#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH 4U
#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1298
#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1
-#define LPDDR4__DENALI_PHY_1299_READ_MASK 0x010F0F01U
-#define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0x010F0F01U
+#define LPDDR4__DENALI_PHY_1299_READ_MASK 0x010F0F01U
+#define LPDDR4__DENALI_PHY_1299_WRITE_MASK 0x010F0F01U
#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOSET 0U
+#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL_WOSET 0U
#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1299
#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXIO_CTRL
@@ -434,8 +433,8 @@
#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1299
#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1299__PHY_MEMCLK_SW_TXPWR_CTRL
-#define LPDDR4__DENALI_PHY_1300_READ_MASK 0xFFFF0101U
-#define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1300_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PHY_1300_WRITE_MASK 0xFFFF0101U
#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WIDTH 1U
@@ -453,13 +452,13 @@
#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE
#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_WIDTH 16U
+#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL_WIDTH 16U
#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1300
#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1300__PHY_STATIC_TOG_CONTROL
-#define LPDDR4__DENALI_PHY_1301_READ_MASK 0x0001010FU
-#define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x0001010FU
+#define LPDDR4__DENALI_PHY_1301_READ_MASK 0x0001010FU
+#define LPDDR4__DENALI_PHY_1301_WRITE_MASK 0x0001010FU
#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH 4U
@@ -476,49 +475,49 @@
#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOSET 0U
+#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS_WOSET 0U
#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1301
#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1301__PHY_LP4_BOOT_PLL_BYPASS
-#define LPDDR4__DENALI_PHY_1302_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1302_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1302_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS_WIDTH 32U
#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1302
#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1302__PHY_CLK_SWITCH_OBS
-#define LPDDR4__DENALI_PHY_1303_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_WIDTH 16U
+#define LPDDR4__DENALI_PHY_1303_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1303_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT_WIDTH 16U
#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1303
#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1303__PHY_PLL_WAIT
-#define LPDDR4__DENALI_PHY_1304_READ_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1304_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1304_WRITE_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOSET 0U
+#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS_WOSET 0U
#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1304
#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1304__PHY_SW_PLL_BYPASS
-#define LPDDR4__DENALI_PHY_1305_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1305_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1305_WRITE_MASK 0x0F0F0F0FU
#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0_WIDTH 4U
#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1305
#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_0
#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_MASK 0x00000F00U
-#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1_WIDTH 4U
#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1305
#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1305__PHY_SET_DFI_INPUT_1
@@ -534,8 +533,8 @@
#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1305
#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1305__PHY_CS_ACS_ALLOCATION_BIT1_0
-#define LPDDR4__DENALI_PHY_1306_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306_WRITE_MASK 0x0F0F0F0FU
#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH 4U
@@ -560,8 +559,8 @@
#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1306
#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1306__PHY_CS_ACS_ALLOCATION_BIT1_1
-#define LPDDR4__DENALI_PHY_1307_READ_MASK 0x01FF0F0FU
-#define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x01FF0F0FU
+#define LPDDR4__DENALI_PHY_1307_READ_MASK 0x01FF0F0FU
+#define LPDDR4__DENALI_PHY_1307_WRITE_MASK 0x01FF0F0FU
#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK 0x0000000FU
#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH 4U
@@ -575,38 +574,38 @@
#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_1
#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0_WIDTH 8U
#define LPDDR4__PHY_CLK_DC_ADJUST_0__REG DENALI_PHY_1307
#define LPDDR4__PHY_CLK_DC_ADJUST_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_ADJUST_0
#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE_WOSET 0U
#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__REG DENALI_PHY_1307
#define LPDDR4__PHY_CLK_DC_INIT_DISABLE__FLD LPDDR4__DENALI_PHY_1307__PHY_CLK_DC_INIT_DISABLE
-#define LPDDR4__DENALI_PHY_1308_READ_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_1308_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PHY_1308_WRITE_MASK 0x001FFFFFU
#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD_WIDTH 8U
#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__REG DENALI_PHY_1308
#define LPDDR4__PHY_CLK_DC_DM_THRSHLD__FLD LPDDR4__DENALI_PHY_1308__PHY_CLK_DC_DM_THRSHLD
#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_MASK 0x001FFF00U
-#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_WIDTH 13U
+#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL_WIDTH 13U
#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1308
#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1308__PHY_LP4_BOOT_PLL_CTRL
-#define LPDDR4__DENALI_PHY_1309_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1309_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1309_WRITE_MASK 0x0001FFFFU
#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_WIDTH 16U
+#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE_WIDTH 16U
#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1309
#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1309__PHY_PLL_CTRL_OVERRIDE
@@ -618,11 +617,11 @@
#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1309
#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1309__PHY_USE_PLL_DSKEWCALLOCK
-#define LPDDR4__DENALI_PHY_1310_READ_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1310_READ_MASK 0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1310_WRITE_MASK 0x0007FFFFU
#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_WIDTH 19U
+#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL_WIDTH 19U
#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1310
#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1310__PHY_PLL_SPO_CAL_CTRL
@@ -632,8 +631,8 @@
#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1310
#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1310__SC_PHY_PLL_SPO_CAL_SNAP_OBS
-#define LPDDR4__DENALI_PHY_1311_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1311_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_1311_WRITE_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_SHIFT 0U
#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CAL_CLK_MEAS_CYCLES_WIDTH 10U
@@ -642,52 +641,52 @@
#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_MASK 0x00030000U
#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_WIDTH 2U
+#define LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS_WIDTH 2U
#define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__REG DENALI_PHY_1311
#define LPDDR4__SC_PHY_PLL_CAL_CLK_MEAS__FLD LPDDR4__DENALI_PHY_1311__SC_PHY_PLL_CAL_CLK_MEAS
-#define LPDDR4__DENALI_PHY_1312_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_WIDTH 16U
+#define LPDDR4__DENALI_PHY_1312_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1312_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0_WIDTH 16U
#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1312
#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1312__PHY_PLL_OBS_0
-#define LPDDR4__DENALI_PHY_1313_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1313_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1313_WRITE_MASK 0x0001FFFFU
#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_WIDTH 17U
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0_WIDTH 17U
#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1313
#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1313__PHY_PLL_SPO_CAL_OBS_0
-#define LPDDR4__DENALI_PHY_1314_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1314_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1314_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0_WIDTH 18U
#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__REG DENALI_PHY_1314
#define LPDDR4__PHY_PLL_CAL_CLK_MEAS_OBS_0__FLD LPDDR4__DENALI_PHY_1314__PHY_PLL_CAL_CLK_MEAS_OBS_0
-#define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_WIDTH 16U
+#define LPDDR4__DENALI_PHY_1315_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1315_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1_WIDTH 16U
#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1315
#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1315__PHY_PLL_OBS_1
-#define LPDDR4__DENALI_PHY_1316_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1316_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1316_WRITE_MASK 0x0001FFFFU
#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_WIDTH 17U
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1_WIDTH 17U
#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1316
#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1316__PHY_PLL_SPO_CAL_OBS_1
-#define LPDDR4__DENALI_PHY_1317_READ_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1317_READ_MASK 0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1317_WRITE_MASK 0x0103FFFFU
#define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_1317__PHY_PLL_CAL_CLK_MEAS_OBS_1_WIDTH 18U
@@ -702,167 +701,167 @@
#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1317
#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1317__PHY_LP4_BOOT_LOW_FREQ_SEL
-#define LPDDR4__DENALI_PHY_1318_READ_MASK 0x0001FF0FU
-#define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x0001FF0FU
-#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_MASK 0x0000000FU
-#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1318_READ_MASK 0x0001FF0FU
+#define LPDDR4__DENALI_PHY_1318_WRITE_MASK 0x0001FF0FU
+#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT_WIDTH 4U
#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1318
#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1318__PHY_TCKSRE_WAIT
-#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP_WIDTH 8U
#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1318
#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1318__PHY_LP_WAKEUP
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOSET 0U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN_WOSET 0U
#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1318
#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1318__PHY_LS_IDLE_EN
-#define LPDDR4__DENALI_PHY_1319_READ_MASK 0x000103FFU
-#define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_1319_READ_MASK 0x000103FFU
+#define LPDDR4__DENALI_PHY_1319_WRITE_MASK 0x000103FFU
#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT 0U
#define LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH 10U
#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1319
#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1319__PHY_LP_CTRLUPD_CNTR_CFG
#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOSET 0U
+#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY_WOSET 0U
#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1319
#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1319__PHY_TDFI_PHY_WRDELAY
-#define LPDDR4__DENALI_PHY_1320_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1320_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1320_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM_WIDTH 18U
#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1320
#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1320__PHY_PAD_FDBK_TERM
-#define LPDDR4__DENALI_PHY_1321_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1321_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1321_WRITE_MASK 0x0001FFFFU
#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_WIDTH 17U
+#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM_WIDTH 17U
#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1321
#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1321__PHY_PAD_DATA_TERM
-#define LPDDR4__DENALI_PHY_1322_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1322_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1322_WRITE_MASK 0x0001FFFFU
#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_WIDTH 17U
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM_WIDTH 17U
#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1322
#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1322__PHY_PAD_DQS_TERM
-#define LPDDR4__DENALI_PHY_1323_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1323_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1323_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM_WIDTH 18U
#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1323
#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1323__PHY_PAD_ADDR_TERM
-#define LPDDR4__DENALI_PHY_1324_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1324_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1324_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM_WIDTH 18U
#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1324
#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1324__PHY_PAD_CLK_TERM
-#define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM_WIDTH 18U
#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1325
#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1325__PHY_PAD_CKE_TERM
-#define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM_WIDTH 18U
#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1326
#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1326__PHY_PAD_RST_TERM
-#define LPDDR4__DENALI_PHY_1327_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1327_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM_WIDTH 18U
#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1327
#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1327__PHY_PAD_CS_TERM
-#define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM_WIDTH 18U
#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1328
#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1328__PHY_PAD_ODT_TERM
-#define LPDDR4__DENALI_PHY_1329_READ_MASK 0x1FFF03FFU
-#define LPDDR4__DENALI_PHY_1329_WRITE_MASK 0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1329_READ_MASK 0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1329_WRITE_MASK 0x1FFF03FFU
#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_MASK 0x000003FFU
-#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_WIDTH 10U
+#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL_WIDTH 10U
#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1329
#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_RX_CAL
#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_MASK 0x1FFF0000U
-#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_WIDTH 13U
+#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL_WIDTH 13U
#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1329
#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1329__PHY_ADRCTL_LP3_RX_CAL
-#define LPDDR4__DENALI_PHY_1330_READ_MASK 0x00001FFFU
-#define LPDDR4__DENALI_PHY_1330_WRITE_MASK 0x00001FFFU
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_MASK 0x00001FFFU
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_WIDTH 13U
+#define LPDDR4__DENALI_PHY_1330_READ_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1330_WRITE_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0_WIDTH 13U
#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1330
#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_MODE_0
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0_WOSET 0U
#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1330
#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_CLEAR_0
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0_WOSET 0U
#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1330
#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1330__PHY_CAL_START_0
-#define LPDDR4__DENALI_PHY_1331_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1331_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1331_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1331_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0_WIDTH 32U
#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1331
#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1331__PHY_CAL_INTERVAL_COUNT_0
-#define LPDDR4__DENALI_PHY_1332_READ_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1332_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1332_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1332_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0_WIDTH 8U
#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1332
#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_CAL_SAMPLE_WAIT_0
@@ -872,139 +871,139 @@
#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1332
#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1332__PHY_LP4_BOOT_CAL_CLK_SELECT_0
-#define LPDDR4__DENALI_PHY_1333_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1333_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1333_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1333_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_WIDTH 24U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0_WIDTH 24U
#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1333
#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_RESULT_OBS_0
-#define LPDDR4__DENALI_PHY_1334_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1334_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1334_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1334_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_WIDTH 24U
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0_WIDTH 24U
#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1334
#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1334__PHY_CAL_RESULT2_OBS_0
-#define LPDDR4__DENALI_PHY_1335_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1335_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1335_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1335_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_WIDTH 24U
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0_WIDTH 24U
#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1335
#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1335__PHY_CAL_RESULT4_OBS_0
-#define LPDDR4__DENALI_PHY_1336_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1336_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_WIDTH 24U
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0_WIDTH 24U
#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1336
#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT5_OBS_0
-#define LPDDR4__DENALI_PHY_1337_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1337_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337_WRITE_MASK 0x00FFFFFFU
#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_WIDTH 24U
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0_WIDTH 24U
#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1337
#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT6_OBS_0
-#define LPDDR4__DENALI_PHY_1338_READ_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_1338_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1338_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1338_WRITE_MASK 0x7FFFFFFFU
#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_WIDTH 24U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0_WIDTH 24U
#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1338
#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT7_OBS_0
#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_MASK 0x7F000000U
-#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_WIDTH 7U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0_WIDTH 7U
#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1338
#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_CPTR_CNT_0
-#define LPDDR4__DENALI_PHY_1339_READ_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_PHY_1339_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1339_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1339_WRITE_MASK 0x01FFFFFFU
#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0_WIDTH 8U
#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1339
#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PU_FINE_ADJ_0
#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0_WIDTH 8U
#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1339
#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_PD_FINE_ADJ_0
#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_WIDTH 8U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0_WIDTH 8U
#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1339
#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_RCV_FINE_ADJ_0
#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0_WOSET 0U
#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1339
#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_DBG_CFG_0
#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOSET 0U
+#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0_WOSET 0U
#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1340
#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1340__SC_PHY_PAD_DBG_CONT_0
-#define LPDDR4__DENALI_PHY_1341_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1341_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1341_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1341_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0_WIDTH 32U
#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1341
#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT3_OBS_0
-#define LPDDR4__DENALI_PHY_1342_READ_MASK 0x0FFFFF7FU
-#define LPDDR4__DENALI_PHY_1342_WRITE_MASK 0x0FFFFF7FU
+#define LPDDR4__DENALI_PHY_1342_READ_MASK 0x0FFFFF7FU
+#define LPDDR4__DENALI_PHY_1342_WRITE_MASK 0x0FFFFF7FU
#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_WIDTH 7U
+#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0_WIDTH 7U
#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1342
#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1342__PHY_ADRCTL_PVT_MAP_0
#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_MASK 0x0FFFFF00U
-#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0_WIDTH 20U
#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1342
#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_SLOPE_ADJ_0
-#define LPDDR4__DENALI_PHY_1343_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1343_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1343_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1343_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH 20U
#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1343
#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1343__PHY_CAL_SLOPE_ADJ_PASS2_0
-#define LPDDR4__DENALI_PHY_1344_READ_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_PHY_1344_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1344_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1344_WRITE_MASK 0x01FFFFFFU
#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_WIDTH 25U
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0_WIDTH 25U
#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1344
#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1344__PHY_CAL_TWO_PASS_CFG_0
-#define LPDDR4__DENALI_PHY_1345_READ_MASK 0x3F7FFFFFU
-#define LPDDR4__DENALI_PHY_1345_WRITE_MASK 0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1345_READ_MASK 0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1345_WRITE_MASK 0x3F7FFFFFU
#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_WIDTH 23U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0_WIDTH 23U
#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1345
#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_SW_CAL_CFG_0
@@ -1014,8 +1013,8 @@
#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1345
#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0
-#define LPDDR4__DENALI_PHY_1346_READ_MASK 0x3F3F1F3FU
-#define LPDDR4__DENALI_PHY_1346_WRITE_MASK 0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1346_READ_MASK 0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1346_WRITE_MASK 0x3F3F1F3FU
#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH 6U
@@ -1040,8 +1039,8 @@
#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1346
#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0
-#define LPDDR4__DENALI_PHY_1347_READ_MASK 0x1F3F3F1FU
-#define LPDDR4__DENALI_PHY_1347_WRITE_MASK 0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1347_READ_MASK 0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1347_WRITE_MASK 0x1F3F3F1FU
#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU
#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH 5U
@@ -1066,8 +1065,8 @@
#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1347
#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0
-#define LPDDR4__DENALI_PHY_1348_READ_MASK 0x001F3F3FU
-#define LPDDR4__DENALI_PHY_1348_WRITE_MASK 0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1348_READ_MASK 0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1348_WRITE_MASK 0x001F3F3FU
#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH 6U
@@ -1086,11 +1085,11 @@
#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1348
#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0
-#define LPDDR4__DENALI_PHY_1349_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1349_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1349_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1349_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_WIDTH 16U
+#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL_WIDTH 16U
#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1349
#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1349__PHY_PAD_ATB_CTRL
@@ -1100,8 +1099,8 @@
#define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__REG DENALI_PHY_1349
#define LPDDR4__PHY_PARITY_ERROR_REGIF_AC__FLD LPDDR4__DENALI_PHY_1349__PHY_PARITY_ERROR_REGIF_AC
-#define LPDDR4__DENALI_PHY_1350_READ_MASK 0x03010000U
-#define LPDDR4__DENALI_PHY_1350_WRITE_MASK 0x03010000U
+#define LPDDR4__DENALI_PHY_1350_READ_MASK 0x03010000U
+#define LPDDR4__DENALI_PHY_1350_WRITE_MASK 0x03010000U
#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE_WIDTH 1U
@@ -1111,32 +1110,32 @@
#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1350__PHY_ADRCTL_MANUAL_UPDATE
#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOSET 0U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR_WOSET 0U
#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1350
#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ERR_CLEAR
#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOSET 0U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT_WOSET 0U
#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1350
#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_OBS_SELECT
#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_MASK 0x03000000U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_WIDTH 2U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE_WIDTH 2U
#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1350
#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1350__PHY_AC_LPBK_ENABLE
-#define LPDDR4__DENALI_PHY_1351_READ_MASK 0x0F7F01FFU
-#define LPDDR4__DENALI_PHY_1351_WRITE_MASK 0x0F7F01FFU
+#define LPDDR4__DENALI_PHY_1351_READ_MASK 0x0F7F01FFU
+#define LPDDR4__DENALI_PHY_1351_WRITE_MASK 0x0F7F01FFU
#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_WIDTH 9U
+#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL_WIDTH 9U
#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1351
#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_LPBK_CONTROL
@@ -1152,16 +1151,16 @@
#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1351
#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1351__PHY_AC_PRBS_PATTERN_MASK
-#define LPDDR4__DENALI_PHY_1352_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1352_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1352_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1352_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS_WIDTH 32U
#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1352
#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_RESULT_OBS
-#define LPDDR4__DENALI_PHY_1353_READ_MASK 0x003F0101U
-#define LPDDR4__DENALI_PHY_1353_WRITE_MASK 0x003F0101U
+#define LPDDR4__DENALI_PHY_1353_READ_MASK 0x003F0101U
+#define LPDDR4__DENALI_PHY_1353_WRITE_MASK 0x003F0101U
#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT 0U
#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH 1U
@@ -1171,21 +1170,21 @@
#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_OBS_SELECT
#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE_WOSET 0U
#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1353
#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_ENABLE
#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_MASK 0x003F0000U
#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_WIDTH 6U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL_WIDTH 6U
#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1353
#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_CLK_LPBK_CONTROL
-#define LPDDR4__DENALI_PHY_1354_READ_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_PHY_1354_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1354_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1354_WRITE_MASK 0x0101FFFFU
#define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT 0U
#define LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH 16U
@@ -1193,23 +1192,23 @@
#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_CLK_LPBK_RESULT_OBS
#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE_WOSET 0U
#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1354
#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PWR_RDC_DISABLE
#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_MASK 0x01000000U
#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOSET 0U
+#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE_WOSET 0U
#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1354
#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1354__PHY_TOP_PWR_RDC_DISABLE
-#define LPDDR4__DENALI_PHY_1355_READ_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1355_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1355_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1355_WRITE_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH 1U
@@ -1218,16 +1217,16 @@
#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1355
#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1355__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE
-#define LPDDR4__DENALI_PHY_1356_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1356_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1356_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1356_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_SHIFT 0U
#define LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL_WIDTH 32U
#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1356
#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1356__PHY_DATA_BYTE_ORDER_SEL
-#define LPDDR4__DENALI_PHY_1357_READ_MASK 0x031F01FFU
-#define LPDDR4__DENALI_PHY_1357_WRITE_MASK 0x031F01FFU
+#define LPDDR4__DENALI_PHY_1357_READ_MASK 0x031F01FFU
+#define LPDDR4__DENALI_PHY_1357_WRITE_MASK 0x031F01FFU
#define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK 0x000000FFU
#define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT 0U
#define LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH 8U
@@ -1235,16 +1234,16 @@
#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1357__PHY_DATA_BYTE_ORDER_SEL_HIGH
#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_MASK 0x00000100U
-#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOSET 0U
+#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT_WOSET 0U
#define LPDDR4__PHY_LPDDR4_CONNECT__REG DENALI_PHY_1357
#define LPDDR4__PHY_LPDDR4_CONNECT__FLD LPDDR4__DENALI_PHY_1357__PHY_LPDDR4_CONNECT
#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_MASK 0x001F0000U
-#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_WIDTH 5U
+#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP_WIDTH 5U
#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1357
#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1357__PHY_CALVL_DEVICE_MAP
@@ -1254,41 +1253,41 @@
#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1357
#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1357__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0
-#define LPDDR4__DENALI_PHY_1358_READ_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_1358_WRITE_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1358_READ_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1358_WRITE_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH 2U
#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1358
#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1358__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1
-#define LPDDR4__DENALI_PHY_1359_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1359_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE_WIDTH 32U
#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1359
#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1359__PHY_DDL_AC_ENABLE
-#define LPDDR4__DENALI_PHY_1360_READ_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PHY_1360_WRITE_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_WIDTH 26U
+#define LPDDR4__DENALI_PHY_1360_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1360_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE_WIDTH 26U
#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1360
#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1360__PHY_DDL_AC_MODE
-#define LPDDR4__DENALI_PHY_1361_READ_MASK 0x07FF073FU
-#define LPDDR4__DENALI_PHY_1361_WRITE_MASK 0x07FF073FU
-#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_WIDTH 6U
+#define LPDDR4__DENALI_PHY_1361_READ_MASK 0x07FF073FU
+#define LPDDR4__DENALI_PHY_1361_WRITE_MASK 0x07FF073FU
+#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK_WIDTH 6U
#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1361
#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_AC_MASK
#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_MASK 0x00000700U
-#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_WIDTH 3U
+#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG_WIDTH 3U
#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1361
#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1361__PHY_INIT_UPDATE_CONFIG
@@ -1298,57 +1297,57 @@
#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1361
#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1361__PHY_DDL_TRACK_UPD_THRESHOLD_AC
-#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_MASK 0x07000000U
-#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_WIDTH 3U
+#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN_WIDTH 3U
#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1361
#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1361__PHY_ERR_MASK_EN
-#define LPDDR4__DENALI_PHY_1362_READ_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_1362_WRITE_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_WIDTH 3U
+#define LPDDR4__DENALI_PHY_1362_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1362_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS_WIDTH 3U
#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1362
#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1362__PHY_ERR_STATUS
-#define LPDDR4__DENALI_PHY_1363_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1363_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1363_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1363_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_SHIFT 0U
#define LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER_WIDTH 32U
#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1363
#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1363__PHY_DS0_DQS_ERR_COUNTER
-#define LPDDR4__DENALI_PHY_1364_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1364_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1364_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1364_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_SHIFT 0U
#define LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER_WIDTH 32U
#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1364
#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1364__PHY_DS1_DQS_ERR_COUNTER
-#define LPDDR4__DENALI_PHY_1365_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1365_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1365_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1365_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_SHIFT 0U
#define LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER_WIDTH 32U
#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__REG DENALI_PHY_1365
#define LPDDR4__PHY_DS2_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1365__PHY_DS2_DQS_ERR_COUNTER
-#define LPDDR4__DENALI_PHY_1366_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1366_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_SHIFT 0U
#define LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER_WIDTH 32U
#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__REG DENALI_PHY_1366
#define LPDDR4__PHY_DS3_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1366__PHY_DS3_DQS_ERR_COUNTER
-#define LPDDR4__DENALI_PHY_1367_READ_MASK 0x0F03FF03U
-#define LPDDR4__DENALI_PHY_1367_WRITE_MASK 0x0F03FF03U
-#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_MASK 0x00000003U
-#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_WIDTH 2U
+#define LPDDR4__DENALI_PHY_1367_READ_MASK 0x0F03FF03U
+#define LPDDR4__DENALI_PHY_1367_WRITE_MASK 0x0F03FF03U
+#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN_WIDTH 2U
#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1367
#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1367__PHY_DLL_RST_EN
@@ -1364,13 +1363,13 @@
#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1367
#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1367__PHY_DS_INIT_COMPLETE_OBS
-#define LPDDR4__DENALI_PHY_1368_READ_MASK 0x070F0101U
-#define LPDDR4__DENALI_PHY_1368_WRITE_MASK 0x070F0101U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOSET 0U
+#define LPDDR4__DENALI_PHY_1368_READ_MASK 0x070F0101U
+#define LPDDR4__DENALI_PHY_1368_WRITE_MASK 0x070F0101U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK_WOSET 0U
#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1368
#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1368__PHY_UPDATE_MASK
@@ -1394,22 +1393,22 @@
#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1368
#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1368__PHY_GRP_SHIFT_OBS_SELECT
-#define LPDDR4__DENALI_PHY_1369_READ_MASK 0x000707FFU
-#define LPDDR4__DENALI_PHY_1369_WRITE_MASK 0x000707FFU
+#define LPDDR4__DENALI_PHY_1369_READ_MASK 0x000707FFU
+#define LPDDR4__DENALI_PHY_1369_WRITE_MASK 0x000707FFU
#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT 0U
#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH 11U
#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1369
#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS
#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_MASK 0x00070000U
-#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_WIDTH 3U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_WIDTH 3U
#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1369
#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS
-#define LPDDR4__DENALI_PHY_1370_READ_MASK 0x0707FF01U
-#define LPDDR4__DENALI_PHY_1370_WRITE_MASK 0x0707FF01U
+#define LPDDR4__DENALI_PHY_1370_READ_MASK 0x0707FF01U
+#define LPDDR4__DENALI_PHY_1370_WRITE_MASK 0x0707FF01U
#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_MASK 0x00000001U
#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1370__PHY_PARITY_ERROR_INJECTION_ENABLE_WIDTH 1U
@@ -1430,11 +1429,11 @@
#define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__REG DENALI_PHY_1370
#define LPDDR4__PHY_PLL_LOCK_DEASSERT_MASK__FLD LPDDR4__DENALI_PHY_1370__PHY_PLL_LOCK_DEASSERT_MASK
-#define LPDDR4__DENALI_PHY_1371_READ_MASK 0x00007F7FU
-#define LPDDR4__DENALI_PHY_1371_WRITE_MASK 0x00007F7FU
+#define LPDDR4__DENALI_PHY_1371_READ_MASK 0x00007F7FU
+#define LPDDR4__DENALI_PHY_1371_WRITE_MASK 0x00007F7FU
#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_MASK 0x0000007FU
-#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_WIDTH 7U
+#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO_WIDTH 7U
#define LPDDR4__PHY_PARITY_ERROR_INFO__REG DENALI_PHY_1371
#define LPDDR4__PHY_PARITY_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1371__PHY_PARITY_ERROR_INFO
@@ -1450,11 +1449,11 @@
#define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__REG DENALI_PHY_1371
#define LPDDR4__SC_PHY_PARITY_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1371__SC_PHY_PARITY_ERROR_INFO_WOCLR
-#define LPDDR4__DENALI_PHY_1372_READ_MASK 0x3FFF3FFFU
-#define LPDDR4__DENALI_PHY_1372_WRITE_MASK 0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_1372_READ_MASK 0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_1372_WRITE_MASK 0x3FFF3FFFU
#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_WIDTH 14U
+#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_WIDTH 14U
#define LPDDR4__PHY_TIMEOUT_ERROR_INFO__REG DENALI_PHY_1372
#define LPDDR4__PHY_TIMEOUT_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO
@@ -1464,8 +1463,8 @@
#define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__REG DENALI_PHY_1372
#define LPDDR4__PHY_TIMEOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1372__PHY_TIMEOUT_ERROR_INFO_MASK
-#define LPDDR4__DENALI_PHY_1373_READ_MASK 0x3F0F0000U
-#define LPDDR4__DENALI_PHY_1373_WRITE_MASK 0x3F0F0000U
+#define LPDDR4__DENALI_PHY_1373_READ_MASK 0x3F0F0000U
+#define LPDDR4__DENALI_PHY_1373_WRITE_MASK 0x3F0F0000U
#define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_SHIFT 0U
#define LPDDR4__DENALI_PHY_1373__SC_PHY_TIMEOUT_ERROR_INFO_WOCLR_WIDTH 14U
@@ -1474,7 +1473,7 @@
#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK 0x000F0000U
#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_WIDTH 4U
#define LPDDR4__PHY_PLL_FREQUENCY_ERROR__REG DENALI_PHY_1373
#define LPDDR4__PHY_PLL_FREQUENCY_ERROR__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR
@@ -1484,8 +1483,8 @@
#define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__REG DENALI_PHY_1373
#define LPDDR4__PHY_PLL_FREQUENCY_ERROR_MASK__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_FREQUENCY_ERROR_MASK
-#define LPDDR4__DENALI_PHY_1374_READ_MASK 0x000FFF00U
-#define LPDDR4__DENALI_PHY_1374_WRITE_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PHY_1374_READ_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PHY_1374_WRITE_MASK 0x000FFF00U
#define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_MASK 0x0000003FU
#define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_SHIFT 0U
#define LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR_WIDTH 6U
@@ -1493,15 +1492,15 @@
#define LPDDR4__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR__FLD LPDDR4__DENALI_PHY_1374__SC_PHY_PLL_FREQUENCY_ERROR_WOCLR
#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_MASK 0x000FFF00U
-#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_SHIFT 8U
#define LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN_WIDTH 12U
#define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__REG DENALI_PHY_1374
#define LPDDR4__PHY_PLL_DSKEWCALOUT_MIN__FLD LPDDR4__DENALI_PHY_1374__PHY_PLL_DSKEWCALOUT_MIN
-#define LPDDR4__DENALI_PHY_1375_READ_MASK 0x03030FFFU
-#define LPDDR4__DENALI_PHY_1375_WRITE_MASK 0x03030FFFU
+#define LPDDR4__DENALI_PHY_1375_READ_MASK 0x03030FFFU
+#define LPDDR4__DENALI_PHY_1375_WRITE_MASK 0x03030FFFU
#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_SHIFT 0U
#define LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX_WIDTH 12U
#define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__REG DENALI_PHY_1375
#define LPDDR4__PHY_PLL_DSKEWCALOUT_MAX__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_MAX
@@ -1518,8 +1517,8 @@
#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__REG DENALI_PHY_1375
#define LPDDR4__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1375__PHY_PLL_DSKEWCALOUT_ERROR_INFO_MASK
-#define LPDDR4__DENALI_PHY_1376_READ_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_1376_WRITE_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_1376_READ_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_1376_WRITE_MASK 0x0001FF00U
#define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_SHIFT 0U
#define LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR_WIDTH 2U
@@ -1527,13 +1526,13 @@
#define LPDDR4__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1376__SC_PHY_PLL_DSKEWCALOUT_ERROR_INFO_WOCLR
#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_SHIFT 8U
-#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_WIDTH 9U
+#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_SHIFT 8U
+#define LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO_WIDTH 9U
#define LPDDR4__PHY_TOP_FSM_ERROR_INFO__REG DENALI_PHY_1376
#define LPDDR4__PHY_TOP_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1376__PHY_TOP_FSM_ERROR_INFO
-#define LPDDR4__DENALI_PHY_1377_READ_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_1377_WRITE_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_1377_READ_MASK 0x000001FFU
+#define LPDDR4__DENALI_PHY_1377_WRITE_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_MASK 0x000001FFU
#define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_SHIFT 0U
#define LPDDR4__DENALI_PHY_1377__PHY_TOP_FSM_ERROR_INFO_MASK_WIDTH 9U
@@ -1546,8 +1545,8 @@
#define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__REG DENALI_PHY_1377
#define LPDDR4__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1377__SC_PHY_TOP_FSM_ERROR_INFO_WOCLR
-#define LPDDR4__DENALI_PHY_1378_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PHY_1378_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_1378_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PHY_1378_WRITE_MASK 0x03FF03FFU
#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_SHIFT 0U
#define LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_WIDTH 10U
@@ -1560,8 +1559,8 @@
#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__REG DENALI_PHY_1378
#define LPDDR4__PHY_FSM_TRANSIENT_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1378__PHY_FSM_TRANSIENT_ERROR_INFO_MASK
-#define LPDDR4__DENALI_PHY_1379_READ_MASK 0x03030000U
-#define LPDDR4__DENALI_PHY_1379_WRITE_MASK 0x03030000U
+#define LPDDR4__DENALI_PHY_1379_READ_MASK 0x03030000U
+#define LPDDR4__DENALI_PHY_1379_WRITE_MASK 0x03030000U
#define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_MASK 0x000003FFU
#define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_SHIFT 0U
#define LPDDR4__DENALI_PHY_1379__SC_PHY_FSM_TRANSIENT_ERROR_INFO_WOCLR_WIDTH 10U
@@ -1580,8 +1579,8 @@
#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__REG DENALI_PHY_1379
#define LPDDR4__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1379__PHY_TOP_TRAIN_CALIB_ERROR_INFO_MASK
-#define LPDDR4__DENALI_PHY_1380_READ_MASK 0x007F7F00U
-#define LPDDR4__DENALI_PHY_1380_WRITE_MASK 0x007F7F00U
+#define LPDDR4__DENALI_PHY_1380_READ_MASK 0x007F7F00U
+#define LPDDR4__DENALI_PHY_1380_WRITE_MASK 0x007F7F00U
#define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_MASK 0x00000003U
#define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_SHIFT 0U
#define LPDDR4__DENALI_PHY_1380__SC_PHY_TOP_TRAIN_CALIB_ERROR_INFO_WOCLR_WIDTH 2U
@@ -1606,11 +1605,11 @@
#define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__REG DENALI_PHY_1380
#define LPDDR4__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PHY_1380__SC_PHY_TRAIN_CALIB_ERROR_INFO_WOCLR
-#define LPDDR4__DENALI_PHY_1381_READ_MASK 0x00003F3FU
-#define LPDDR4__DENALI_PHY_1381_WRITE_MASK 0x00003F3FU
+#define LPDDR4__DENALI_PHY_1381_READ_MASK 0x00003F3FU
+#define LPDDR4__DENALI_PHY_1381_WRITE_MASK 0x00003F3FU
#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK 0x0000003FU
-#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_WIDTH 6U
+#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_WIDTH 6U
#define LPDDR4__PHY_GLOBAL_ERROR_INFO__REG DENALI_PHY_1381
#define LPDDR4__PHY_GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO
@@ -1620,40 +1619,40 @@
#define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__REG DENALI_PHY_1381
#define LPDDR4__PHY_GLOBAL_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PHY_1381__PHY_GLOBAL_ERROR_INFO_MASK
-#define LPDDR4__DENALI_PHY_1382_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1382_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1382_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1382_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE_WIDTH 20U
#define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__REG DENALI_PHY_1382
#define LPDDR4__PHY_TRAINING_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1382__PHY_TRAINING_TIMEOUT_VALUE
-#define LPDDR4__DENALI_PHY_1383_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1383_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1383_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1383_WRITE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_WIDTH 20U
+#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE_WIDTH 20U
#define LPDDR4__PHY_INIT_TIMEOUT_VALUE__REG DENALI_PHY_1383
#define LPDDR4__PHY_INIT_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1383__PHY_INIT_TIMEOUT_VALUE
-#define LPDDR4__DENALI_PHY_1384_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1384_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1384_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1384_WRITE_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_WIDTH 16U
+#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE_WIDTH 16U
#define LPDDR4__PHY_LP_TIMEOUT_VALUE__REG DENALI_PHY_1384
#define LPDDR4__PHY_LP_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1384__PHY_LP_TIMEOUT_VALUE
-#define LPDDR4__DENALI_PHY_1385_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1385_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1385_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1385_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE_WIDTH 32U
#define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__REG DENALI_PHY_1385
#define LPDDR4__PHY_PHYUPD_TIMEOUT_VALUE__FLD LPDDR4__DENALI_PHY_1385__PHY_PHYUPD_TIMEOUT_VALUE
-#define LPDDR4__DENALI_PHY_1386_READ_MASK 0x1F0FFFFFU
-#define LPDDR4__DENALI_PHY_1386_WRITE_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_PHY_1386_READ_MASK 0x1F0FFFFFU
+#define LPDDR4__DENALI_PHY_1386_WRITE_MASK 0x1F0FFFFFU
#define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_MASK 0x000FFFFFU
#define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1386__PHY_PHYMSTR_TIMEOUT_VALUE_WIDTH 20U
@@ -1666,8 +1665,8 @@
#define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__REG DENALI_PHY_1386
#define LPDDR4__PHY_PLL_LOCK_0_MIN_VALUE__FLD LPDDR4__DENALI_PHY_1386__PHY_PLL_LOCK_0_MIN_VALUE
-#define LPDDR4__DENALI_PHY_1387_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PHY_1387_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387_WRITE_MASK 0x0FFFFFFFU
#define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_SHIFT 0U
#define LPDDR4__DENALI_PHY_1387__PHY_PLL_LOCK_TIMEOUT_VALUE_WIDTH 16U
@@ -1682,12 +1681,12 @@
#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_MASK 0x0F000000U
#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA_WIDTH 4U
#define LPDDR4__PHY_PLL_FREQUENCY_DELTA__REG DENALI_PHY_1387
#define LPDDR4__PHY_PLL_FREQUENCY_DELTA__FLD LPDDR4__DENALI_PHY_1387__PHY_PLL_FREQUENCY_DELTA
-#define LPDDR4__DENALI_PHY_1388_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1388_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1388_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1388_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_MASK 0x0000FFFFU
#define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_SHIFT 0U
#define LPDDR4__DENALI_PHY_1388__PHY_PLL_FREQUENCY_COMPARE_INTERVAL_WIDTH 16U
@@ -1700,8 +1699,8 @@
#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__REG DENALI_PHY_1388
#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1388__PHY_ADRCTL_FSM_ERROR_INFO_0
-#define LPDDR4__DENALI_PHY_1389_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_1389_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_1389_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_1389_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1389__PHY_ADRCTL_FSM_ERROR_INFO_MASK_0_WIDTH 14U
@@ -1714,8 +1713,8 @@
#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1389
#define LPDDR4__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1389__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_0
-#define LPDDR4__DENALI_PHY_1390_READ_MASK 0x3FFF3FFFU
-#define LPDDR4__DENALI_PHY_1390_WRITE_MASK 0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_1390_READ_MASK 0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_1390_WRITE_MASK 0x3FFF3FFFU
#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_1_WIDTH 14U
@@ -1728,8 +1727,8 @@
#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__REG DENALI_PHY_1390
#define LPDDR4__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1__FLD LPDDR4__DENALI_PHY_1390__PHY_ADRCTL_FSM_ERROR_INFO_MASK_1
-#define LPDDR4__DENALI_PHY_1391_READ_MASK 0x3FFF0000U
-#define LPDDR4__DENALI_PHY_1391_WRITE_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_1391_READ_MASK 0x3FFF0000U
+#define LPDDR4__DENALI_PHY_1391_WRITE_MASK 0x3FFF0000U
#define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_SHIFT 0U
#define LPDDR4__DENALI_PHY_1391__SC_PHY_ADRCTL_FSM_ERROR_INFO_WOCLR_1_WIDTH 14U
@@ -1742,8 +1741,8 @@
#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__REG DENALI_PHY_1391
#define LPDDR4__PHY_MEMCLK_FSM_ERROR_INFO_0__FLD LPDDR4__DENALI_PHY_1391__PHY_MEMCLK_FSM_ERROR_INFO_0
-#define LPDDR4__DENALI_PHY_1392_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_1392_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_1392_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_1392_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_SHIFT 0U
#define LPDDR4__DENALI_PHY_1392__PHY_MEMCLK_FSM_ERROR_INFO_MASK_0_WIDTH 14U
@@ -1756,81 +1755,81 @@
#define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__REG DENALI_PHY_1392
#define LPDDR4__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0__FLD LPDDR4__DENALI_PHY_1392__SC_PHY_MEMCLK_FSM_ERROR_INFO_WOCLR_0
-#define LPDDR4__DENALI_PHY_1393_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1393_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1393_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1393_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0_WIDTH 18U
#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1393
#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1393__PHY_PAD_CAL_IO_CFG_0
-#define LPDDR4__DENALI_PHY_1394_READ_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_1394_WRITE_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_1394_READ_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PHY_1394_WRITE_MASK 0x00003FFFU
#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_WIDTH 14U
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG_WIDTH 14U
#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1394
#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1394__PHY_PAD_ACS_IO_CFG
-#define LPDDR4__DENALI_PHY_1395_READ_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1395_WRITE_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_MASK 0x00000001U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOSET 0U
+#define LPDDR4__DENALI_PHY_1395_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1395_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS_WOSET 0U
#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1395
#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1395__PHY_PLL_BYPASS
-#define LPDDR4__DENALI_PHY_1396_READ_MASK 0x00011FFFU
-#define LPDDR4__DENALI_PHY_1396_WRITE_MASK 0x00011FFFU
-#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_MASK 0x00001FFFU
-#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_WIDTH 13U
+#define LPDDR4__DENALI_PHY_1396_READ_MASK 0x00011FFFU
+#define LPDDR4__DENALI_PHY_1396_WRITE_MASK 0x00011FFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_MASK 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL_WIDTH 13U
#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1396
#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1396__PHY_PLL_CTRL
#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_MASK 0x00010000U
-#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOSET 0U
+#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL_WOSET 0U
#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1396
#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1396__PHY_LOW_FREQ_SEL
-#define LPDDR4__DENALI_PHY_1397_READ_MASK 0x0F0F0FFFU
-#define LPDDR4__DENALI_PHY_1397_WRITE_MASK 0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1397_READ_MASK 0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1397_WRITE_MASK 0x0F0F0FFFU
#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_WIDTH 12U
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC_WIDTH 12U
#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1397
#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1397__PHY_PAD_VREF_CTRL_AC
#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_MASK 0x000F0000U
-#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT_WIDTH 4U
#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1397
#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_CAPTURE_CNT
#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_MASK 0x0F000000U
-#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_WIDTH 4U
+#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP_WIDTH 4U
#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1397
#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1397__PHY_CSLVL_DLY_STEP
-#define LPDDR4__DENALI_PHY_1398_READ_MASK 0x010101FFU
-#define LPDDR4__DENALI_PHY_1398_WRITE_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_1398_READ_MASK 0x010101FFU
+#define LPDDR4__DENALI_PHY_1398_WRITE_MASK 0x010101FFU
#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_MASK 0x000001FFU
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_WIDTH 9U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_WIDTH 9U
#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1398
#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN
#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_MASK 0x00010000U
#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH 1U
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR 0U
-#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOSET 0U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH 1U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR 0U
+#define LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN_WOSET 0U
#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1398
#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1398__PHY_SW_CSLVL_DVW_MIN_EN
@@ -1842,207 +1841,207 @@
#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1398
#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1398__PHY_LVL_MEAS_DLY_STEP_ENABLE
-#define LPDDR4__DENALI_PHY_1399_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1399_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1399_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1399_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1399
#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP0_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1399
#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1399__PHY_GRP1_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_1400_READ_MASK 0x07FF07FFU
-#define LPDDR4__DENALI_PHY_1400_WRITE_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1400_READ_MASK 0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1400_WRITE_MASK 0x07FF07FFU
#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1400
#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP2_SLAVE_DELAY_0
#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_MASK 0x07FF0000U
-#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_SHIFT 16U
-#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0_WIDTH 11U
#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1400
#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1400__PHY_GRP3_SLAVE_DELAY_0
-#define LPDDR4__DENALI_PHY_1401_READ_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1401_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1401_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1401_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1401
#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1401__PHY_GRP0_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_1402_READ_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1402_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1402_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1402_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1402
#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1402__PHY_GRP1_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_1403_READ_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1403_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1403_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1403_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1403
#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1403__PHY_GRP2_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_1404_READ_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1404_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1404_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1404_WRITE_MASK 0x000007FFU
#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_MASK 0x000007FFU
-#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_WIDTH 11U
+#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1_WIDTH 11U
#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1404
#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1404__PHY_GRP3_SLAVE_DELAY_1
-#define LPDDR4__DENALI_PHY_1405_READ_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_1405_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1405_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1405_WRITE_MASK 0x00000007U
#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_WIDTH 3U
+#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL_WIDTH 3U
#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__REG DENALI_PHY_1405
#define LPDDR4__PHY_CLK_DC_CAL_CLK_SEL__FLD LPDDR4__DENALI_PHY_1405__PHY_CLK_DC_CAL_CLK_SEL
-#define LPDDR4__DENALI_PHY_1406_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1406_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1406_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1406_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_WIDTH 30U
+#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE_WIDTH 30U
#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1406
#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1406__PHY_PAD_FDBK_DRIVE
-#define LPDDR4__DENALI_PHY_1407_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1407_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1407_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1407_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2_WIDTH 18U
#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1407
#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1407__PHY_PAD_FDBK_DRIVE2
-#define LPDDR4__DENALI_PHY_1408_READ_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_1408_WRITE_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1408_READ_MASK 0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1408_WRITE_MASK 0x7FFFFFFFU
#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_WIDTH 31U
+#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE_WIDTH 31U
#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1408
#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1408__PHY_PAD_DATA_DRIVE
-#define LPDDR4__DENALI_PHY_1409_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1409_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1409_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1409_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE_WIDTH 32U
#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1409
#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1409__PHY_PAD_DQS_DRIVE
-#define LPDDR4__DENALI_PHY_1410_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1410_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1410_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1410_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_WIDTH 30U
+#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE_WIDTH 30U
#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1410
#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1410__PHY_PAD_ADDR_DRIVE
-#define LPDDR4__DENALI_PHY_1411_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1411_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1411_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1411_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_WIDTH 27U
+#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2_WIDTH 27U
#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1411
#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1411__PHY_PAD_ADDR_DRIVE2
-#define LPDDR4__DENALI_PHY_1412_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1412_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1412_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1412_WRITE_MASK 0xFFFFFFFFU
#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_WIDTH 32U
+#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE_WIDTH 32U
#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1412
#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1412__PHY_PAD_CLK_DRIVE
-#define LPDDR4__DENALI_PHY_1413_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1413_WRITE_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1413_READ_MASK 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1413_WRITE_MASK 0x0003FFFFU
#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_WIDTH 18U
+#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2_WIDTH 18U
#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1413
#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1413__PHY_PAD_CLK_DRIVE2
-#define LPDDR4__DENALI_PHY_1414_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1414_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1414_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1414_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_WIDTH 30U
+#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE_WIDTH 30U
#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1414
#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1414__PHY_PAD_CKE_DRIVE
-#define LPDDR4__DENALI_PHY_1415_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1415_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1415_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1415_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_WIDTH 27U
+#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2_WIDTH 27U
#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1415
#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1415__PHY_PAD_CKE_DRIVE2
-#define LPDDR4__DENALI_PHY_1416_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1416_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1416_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1416_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_WIDTH 30U
+#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE_WIDTH 30U
#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1416
#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1416__PHY_PAD_RST_DRIVE
-#define LPDDR4__DENALI_PHY_1417_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1417_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1417_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1417_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_WIDTH 27U
+#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2_WIDTH 27U
#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1417
#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1417__PHY_PAD_RST_DRIVE2
-#define LPDDR4__DENALI_PHY_1418_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1418_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1418_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1418_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_WIDTH 30U
+#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE_WIDTH 30U
#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1418
#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1418__PHY_PAD_CS_DRIVE
-#define LPDDR4__DENALI_PHY_1419_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1419_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1419_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1419_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_WIDTH 27U
+#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2_WIDTH 27U
#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1419
#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1419__PHY_PAD_CS_DRIVE2
-#define LPDDR4__DENALI_PHY_1420_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1420_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1420_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1420_WRITE_MASK 0x3FFFFFFFU
#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_WIDTH 30U
+#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE_WIDTH 30U
#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1420
#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1420__PHY_PAD_ODT_DRIVE
-#define LPDDR4__DENALI_PHY_1421_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1421_WRITE_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1421_READ_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1421_WRITE_MASK 0x07FFFFFFU
#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_WIDTH 27U
+#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2_WIDTH 27U
#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1421
#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1421__PHY_PAD_ODT_DRIVE2
-#define LPDDR4__DENALI_PHY_1422_READ_MASK 0x7FFFFF07U
-#define LPDDR4__DENALI_PHY_1422_WRITE_MASK 0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1422_READ_MASK 0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1422_WRITE_MASK 0x7FFFFF07U
#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_MASK 0x00000007U
-#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_SHIFT 0U
-#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_WIDTH 3U
+#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0_WIDTH 3U
#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1422
#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_CLK_SELECT_0
@@ -2053,8 +2052,8 @@
#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_VREF_SWITCH_TIMER_0
#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_MASK 0x7F000000U
-#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_SHIFT 24U
-#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_WIDTH 7U
+#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0_WIDTH 7U
#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1422
#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1422__PHY_CAL_SETTLING_PRD_0
diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h
new file mode 100644
index 0000000..7f1754a
--- /dev/null
+++ b/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h
@@ -0,0 +1,5396 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PI_MACROS_H_
+#define REG_LPDDR4_PI_MACROS_H_
+
+#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U
+#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U
+#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U
+#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U
+#define LPDDR4__PI_START__REG DENALI_PI_0
+#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
+
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U
+#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
+#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
+
+#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U
+#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
+#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
+
+#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U
+#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
+#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
+
+#define LPDDR4__DENALI_PI_3_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U
+#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U
+#define LPDDR4__PI_ID__REG DENALI_PI_3
+#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
+
+#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_WIDTH 32U
+#define LPDDR4__DENALI_PI_UNUSED_REG_0__REG DENALI_PI_4
+#define LPDDR4__DENALI_PI_UNUSED_REG_0__FLD LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0
+
+#define LPDDR4__DENALI_PI_5_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_SHIFT 0U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOSET 0U
+#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_5
+#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ
+
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOSET 0U
+#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_5
+#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN
+
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_SHIFT 16U
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WIDTH 1U
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOCLR 0U
+#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOSET 0U
+#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_5
+#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD
+
+#define LPDDR4__DENALI_PI_6_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_SHIFT 0U
+#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_WIDTH 16U
+#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_6
+#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_6__PI_TCMD_GAP
+
+#define LPDDR4__DENALI_PI_6__PI_RESERVED0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_6__PI_RESERVED0_SHIFT 16U
+#define LPDDR4__DENALI_PI_6__PI_RESERVED0_WIDTH 8U
+#define LPDDR4__PI_RESERVED0__REG DENALI_PI_6
+#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_6__PI_RESERVED0
+
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_6
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ
+
+#define LPDDR4__DENALI_PI_7_READ_MASK 0x01010301U
+#define LPDDR4__DENALI_PI_7_WRITE_MASK 0x01010301U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_SHIFT 0U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WIDTH 1U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOCLR 0U
+#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOSET 0U
+#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_7
+#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_7__PI_DFI_VERSION
+
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_SHIFT 8U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_WIDTH 2U
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_7
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 16U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_7
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R
+
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 24U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U
+#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_7
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R
+
+#define LPDDR4__DENALI_PI_8_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_8_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_8
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX
+
+#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_WIDTH 20U
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_9
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP
+
+#define LPDDR4__DENALI_PI_10_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_10_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_WIDTH 20U
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_10
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP
+
+#define LPDDR4__DENALI_PI_11_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_11_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_11
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX
+
+#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U
+#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
+#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
+
+#define LPDDR4__DENALI_PI_13_READ_MASK 0x0101011FU
+#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x0101011FU
+#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_SHIFT 0U
+#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_WIDTH 5U
+#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_13
+#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ
+
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U
+#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOSET 0U
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_13
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY
+
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 16U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U
+#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
+#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
+
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 24U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U
+#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
+#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
+
+#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F0FU
+#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F0FU
+#define LPDDR4__DENALI_PI_14__PI_CS_MAP_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_14__PI_CS_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PI_14__PI_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_CS_MAP__REG DENALI_PI_14
+#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_14__PI_CS_MAP
+
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U
+#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
+#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
+
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
+
+#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U
+#define LPDDR4__PI_TMRR__REG DENALI_PI_14
+#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
+
+#define LPDDR4__DENALI_PI_15_READ_MASK 0x00010103U
+#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x00010103U
+#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_SHIFT 0U
+#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_WIDTH 2U
+#define LPDDR4__PI_PREAMBLE_SUPPORT__REG DENALI_PI_15
+#define LPDDR4__PI_PREAMBLE_SUPPORT__FLD LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT
+
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 8U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
+
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 16U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U
+#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
+#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
+
+#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U
+#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
+#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
+
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U
+#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
+#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
+
+#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U
+#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U
+#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
+#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U
+#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U
+#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
+
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
+#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18_READ_MASK 0x03010101U
+#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03010101U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET 0U
+#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_19_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH 2U
+#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19
+#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH 2U
+#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19
+#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0
+
+#define LPDDR4__DENALI_PI_20_READ_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT 0U
+#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH 3U
+#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20
+#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT 8U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET 0U
+#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET 0U
+#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT
+
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20
+#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0
+
+#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0
+
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21
+#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21
+#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1
+
+#define LPDDR4__DENALI_PI_22_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1
+
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22
+#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22
+#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2
+
+#define LPDDR4__DENALI_PI_23_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2
+
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2
+
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23
+#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2
+
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET 0U
+#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23
+#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3
+
+#define LPDDR4__DENALI_PI_24_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET 0U
+#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3
+
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET 0U
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3
+
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH 2U
+#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24
+#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3
+
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT 24U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24
+#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START
+
+#define LPDDR4__DENALI_PI_25_READ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT 0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25
+#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR
+
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT 8U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET 0U
+#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25
+#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD
+
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET 0U
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25
+#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ
+
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25
+#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26_READ_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x00010101U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26
+#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT 8U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET 0U
+#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26
+#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY
+
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT 16U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET 0U
+#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26
+#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT
+
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_SHIFT 24U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOSET 0U
+#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_26
+#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_REQ
+
+#define LPDDR4__DENALI_PI_27_READ_MASK 0x003F3F03U
+#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x003F3F03U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT 0U
+#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH 2U
+#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27
+#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS
+
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT 8U
+#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH 6U
+#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27
+#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN
+
+#define LPDDR4__DENALI_PI_27__PI_WLMRD_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_27__PI_WLMRD_SHIFT 16U
+#define LPDDR4__DENALI_PI_27__PI_WLMRD_WIDTH 6U
+#define LPDDR4__PI_WLMRD__REG DENALI_PI_27
+#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_27__PI_WLMRD
+
+#define LPDDR4__DENALI_PI_28_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_28_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_SHIFT 16U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOSET 0U
+#define LPDDR4__PI_WRLVL_PERIODIC__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_PERIODIC__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28
+#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_29_READ_MASK 0x0F010F01U
+#define LPDDR4__DENALI_PI_29_WRITE_MASK 0x0F010F01U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT 0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT 8U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH 4U
+#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT 16U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT 24U
+#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29
+#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_30_READ_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x0000FF01U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET 0U
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30
+#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30
+#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN
+
+#define LPDDR4__DENALI_PI_31_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31
+#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP
+
+#define LPDDR4__DENALI_PI_32_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32
+#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX
+
+#define LPDDR4__DENALI_PI_33_READ_MASK 0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x0F0F0F1FU
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT 0U
+#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33
+#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT 8U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH 4U
+#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33
+#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR
+
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT 16U
+#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH 4U
+#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33
+#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD
+
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT 24U
+#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH 4U
+#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33
+#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE
+
+#define LPDDR4__DENALI_PI_34_READ_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_SHIFT 0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOSET 0U
+#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_REQ
+
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_SHIFT 8U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ
+
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT 16U
+#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH 2U
+#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34
+#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS
+
+#define LPDDR4__DENALI_PI_35_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35
+#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0
+
+#define LPDDR4__DENALI_PI_36_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36
+#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1
+
+#define LPDDR4__DENALI_PI_37_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37
+#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2
+
+#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38
+#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3
+
+#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT 0U
+#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39
+#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4
+
+#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT 0U
+#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40
+#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5
+
+#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT 0U
+#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41
+#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6
+
+#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT 0U
+#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH 32U
+#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42
+#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7
+
+#define LPDDR4__DENALI_PI_43_READ_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_43_WRITE_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH 4U
+#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_SHIFT 8U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOSET 0U
+#define LPDDR4__PI_RDLVL_PERIODIC__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_PERIODIC__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT 24U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43
+#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_44_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_44_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_SHIFT 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_PERIODIC__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 16U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT 24U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44
+#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_45_READ_MASK 0x000F0F01U
+#define LPDDR4__DENALI_PI_45_WRITE_MASK 0x000F0F01U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT 0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET 0U
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE
+
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT 8U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT 16U
+#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45
+#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP
+
+#define LPDDR4__DENALI_PI_46_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT 0U
+#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH 10U
+#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46
+#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR
+
+#define LPDDR4__DENALI_PI_47_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47
+#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP
+
+#define LPDDR4__DENALI_PI_48_READ_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x0000FF0FU
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH 4U
+#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48
+#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48
+#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN
+
+#define LPDDR4__DENALI_PI_49_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49
+#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX
+
+#define LPDDR4__DENALI_PI_50_READ_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_PI_50_WRITE_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET 0U
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50
+#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT 8U
+#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50
+#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_51_READ_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL
+
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT 16U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH 4U
+#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START
+
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT 24U
+#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH 4U
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51
+#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM
+
+#define LPDDR4__DENALI_PI_52_READ_MASK 0x01011F1FU
+#define LPDDR4__DENALI_PI_52_WRITE_MASK 0x01011F1FU
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT 0U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52
+#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U
+#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52
+#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52
+#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT 24U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET 0U
+#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52
+#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_PI_53_READ_MASK 0x03007F7FU
+#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x03007F7FU
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH 7U
+#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53
+#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN
+
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT 8U
+#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH 7U
+#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53
+#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT
+
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT 16U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET 0U
+#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53
+#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ
+
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SHIFT 24U
+#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_WIDTH 2U
+#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_53
+#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS
+
+#define LPDDR4__DENALI_PI_54_READ_MASK 0x01030F01U
+#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x01030F01U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_SHIFT 0U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WIDTH 1U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOCLR 0U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOSET 0U
+#define LPDDR4__PI_RESERVED3__REG DENALI_PI_54
+#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_54__PI_RESERVED3
+
+#define LPDDR4__DENALI_PI_54__PI_RESERVED4_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED4_SHIFT 8U
+#define LPDDR4__DENALI_PI_54__PI_RESERVED4_WIDTH 4U
+#define LPDDR4__PI_RESERVED4__REG DENALI_PI_54
+#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_54__PI_RESERVED4
+
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH 2U
+#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54
+#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN
+
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_SHIFT 24U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOSET 0U
+#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_54
+#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_55_READ_MASK 0x0F010101U
+#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x0F010101U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT 0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT 8U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT 16U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE
+
+#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_SHIFT 24U
+#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_55
+#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_56_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56
+#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN
+
+#define LPDDR4__DENALI_PI_57_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57
+#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP
+
+#define LPDDR4__DENALI_PI_58_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58
+#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX
+
+#define LPDDR4__DENALI_PI_59_READ_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_59_WRITE_MASK 0xFFFF0301U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH 1U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR 0U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET 0U
+#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT 16U
+#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59
+#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_60_READ_MASK 0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_60_WRITE_MASK 0x1F1F3F1FU
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT 0U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH 5U
+#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60
+#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL
+
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT 8U
+#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH 6U
+#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60
+#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD
+
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT 16U
+#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH 5U
+#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60
+#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH
+
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT 24U
+#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH 5U
+#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60
+#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT
+
+#define LPDDR4__DENALI_PI_61_READ_MASK 0xFF0F0F01U
+#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFF0F0F01U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET 0U
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61
+#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN
+
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U
+#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61
+#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT 24U
+#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH 8U
+#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61
+#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN
+
+#define LPDDR4__DENALI_PI_62_READ_MASK 0x7F1F0FFFU
+#define LPDDR4__DENALI_PI_62_WRITE_MASK 0x7F1F0FFFU
+#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 0U
+#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_62
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN
+
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT 8U
+#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH 4U
+#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62
+#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH
+
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT 16U
+#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH 5U
+#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62
+#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM
+
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT 24U
+#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH 7U
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62
+#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF
+
+#define LPDDR4__DENALI_PI_63_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_63_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT 0U
+#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH 8U
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63
+#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START
+
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U
+#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63
+#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
+
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U
+#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63
+#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL
+
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U
+#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_63
+#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE
+
+#define LPDDR4__DENALI_PI_64_READ_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_PI_64_WRITE_MASK 0x00FFFF01U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 0U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U
+#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64
+#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE
+
+#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_MASK 0x00FFFF00U
+#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_SHIFT 8U
+#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_WIDTH 16U
+#define LPDDR4__PI_FSM_ERROR_INFO_MASK__REG DENALI_PI_64
+#define LPDDR4__PI_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK
+
+#define LPDDR4__DENALI_PI_65_READ_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_65_WRITE_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_SHIFT 0U
+#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_WIDTH 16U
+#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__REG DENALI_PI_65
+#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR
+
+#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_SHIFT 16U
+#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_WIDTH 16U
+#define LPDDR4__PI_FSM_ERROR_INFO__REG DENALI_PI_65
+#define LPDDR4__PI_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO
+
+#define LPDDR4__DENALI_PI_66_READ_MASK 0x010F0701U
+#define LPDDR4__DENALI_PI_66_WRITE_MASK 0x010F0701U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_SHIFT 8U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_WIDTH 3U
+#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_SHIFT 16U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK
+
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT 24U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH 1U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR 0U
+#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET 0U
+#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66
+#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE
+
+#define LPDDR4__DENALI_PI_67_READ_MASK 0x011F1F0FU
+#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x011F1F0FU
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_SHIFT 0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 8U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 16U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE
+
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT 24U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH 1U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR 0U
+#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET 0U
+#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67
+#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC
+
+#define LPDDR4__DENALI_PI_68_READ_MASK 0x00FF0300U
+#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x00FF0300U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_SHIFT 0U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOSET 0U
+#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ
+
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_SHIFT 8U
+#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_68
+#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_CS
+
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH 8U
+#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68
+#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_69_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT 0U
+#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH 32U
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69
+#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP
+
+#define LPDDR4__DENALI_PI_70_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT 0U
+#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH 32U
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70
+#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX
+
+#define LPDDR4__DENALI_PI_71_READ_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x0101FFFFU
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT 0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH 16U
+#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL
+
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT
+
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_SHIFT 24U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WIDTH 1U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOCLR 0U
+#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOSET 0U
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_71
+#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS
+
+#define LPDDR4__DENALI_PI_72_READ_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_72_WRITE_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOSET 0U
+#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_72
+#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN
+
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOSET 0U
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_72
+#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN
+
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOSET 0U
+#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_72
+#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN
+
+#define LPDDR4__DENALI_PI_73_READ_MASK 0x0F1F0703U
+#define LPDDR4__DENALI_PI_73_WRITE_MASK 0x0F1F0703U
+#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_SHIFT 0U
+#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_WIDTH 2U
+#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_73
+#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_73__PI_BANK_DIFF
+
+#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_SHIFT 8U
+#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_WIDTH 3U
+#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_73
+#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_73__PI_ROW_DIFF
+
+#define LPDDR4__DENALI_PI_73__PI_TCCD_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_73__PI_TCCD_SHIFT 16U
+#define LPDDR4__DENALI_PI_73__PI_TCCD_WIDTH 5U
+#define LPDDR4__PI_TCCD__REG DENALI_PI_73
+#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_73__PI_TCCD
+
+#define LPDDR4__DENALI_PI_73__PI_RESERVED5_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_73__PI_RESERVED5_SHIFT 24U
+#define LPDDR4__DENALI_PI_73__PI_RESERVED5_WIDTH 4U
+#define LPDDR4__PI_RESERVED5__REG DENALI_PI_73
+#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_73__PI_RESERVED5
+
+#define LPDDR4__DENALI_PI_74_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_74__PI_RESERVED6_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_74__PI_RESERVED6_SHIFT 0U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED6_WIDTH 4U
+#define LPDDR4__PI_RESERVED6__REG DENALI_PI_74
+#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_74__PI_RESERVED6
+
+#define LPDDR4__DENALI_PI_74__PI_RESERVED7_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED7_SHIFT 8U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED7_WIDTH 4U
+#define LPDDR4__PI_RESERVED7__REG DENALI_PI_74
+#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_74__PI_RESERVED7
+
+#define LPDDR4__DENALI_PI_74__PI_RESERVED8_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED8_SHIFT 16U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED8_WIDTH 4U
+#define LPDDR4__PI_RESERVED8__REG DENALI_PI_74
+#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_74__PI_RESERVED8
+
+#define LPDDR4__DENALI_PI_74__PI_RESERVED9_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED9_SHIFT 24U
+#define LPDDR4__DENALI_PI_74__PI_RESERVED9_WIDTH 4U
+#define LPDDR4__PI_RESERVED9__REG DENALI_PI_74
+#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_74__PI_RESERVED9
+
+#define LPDDR4__DENALI_PI_75_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_75__PI_RESERVED10_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_75__PI_RESERVED10_SHIFT 0U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED10_WIDTH 4U
+#define LPDDR4__PI_RESERVED10__REG DENALI_PI_75
+#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_75__PI_RESERVED10
+
+#define LPDDR4__DENALI_PI_75__PI_RESERVED11_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED11_SHIFT 8U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED11_WIDTH 4U
+#define LPDDR4__PI_RESERVED11__REG DENALI_PI_75
+#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_75__PI_RESERVED11
+
+#define LPDDR4__DENALI_PI_75__PI_RESERVED12_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED12_SHIFT 16U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED12_WIDTH 4U
+#define LPDDR4__PI_RESERVED12__REG DENALI_PI_75
+#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_75__PI_RESERVED12
+
+#define LPDDR4__DENALI_PI_75__PI_RESERVED13_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED13_SHIFT 24U
+#define LPDDR4__DENALI_PI_75__PI_RESERVED13_WIDTH 4U
+#define LPDDR4__PI_RESERVED13__REG DENALI_PI_75
+#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_75__PI_RESERVED13
+
+#define LPDDR4__DENALI_PI_76_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_76_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_76__PI_RESERVED14_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_76__PI_RESERVED14_SHIFT 0U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED14_WIDTH 4U
+#define LPDDR4__PI_RESERVED14__REG DENALI_PI_76
+#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_76__PI_RESERVED14
+
+#define LPDDR4__DENALI_PI_76__PI_RESERVED15_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED15_SHIFT 8U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED15_WIDTH 4U
+#define LPDDR4__PI_RESERVED15__REG DENALI_PI_76
+#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_76__PI_RESERVED15
+
+#define LPDDR4__DENALI_PI_76__PI_RESERVED16_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED16_SHIFT 16U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED16_WIDTH 4U
+#define LPDDR4__PI_RESERVED16__REG DENALI_PI_76
+#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_76__PI_RESERVED16
+
+#define LPDDR4__DENALI_PI_76__PI_RESERVED17_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED17_SHIFT 24U
+#define LPDDR4__DENALI_PI_76__PI_RESERVED17_WIDTH 4U
+#define LPDDR4__PI_RESERVED17__REG DENALI_PI_76
+#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_76__PI_RESERVED17
+
+#define LPDDR4__DENALI_PI_77_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_77__PI_RESERVED18_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_77__PI_RESERVED18_SHIFT 0U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED18_WIDTH 4U
+#define LPDDR4__PI_RESERVED18__REG DENALI_PI_77
+#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_77__PI_RESERVED18
+
+#define LPDDR4__DENALI_PI_77__PI_RESERVED19_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED19_SHIFT 8U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED19_WIDTH 4U
+#define LPDDR4__PI_RESERVED19__REG DENALI_PI_77
+#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_77__PI_RESERVED19
+
+#define LPDDR4__DENALI_PI_77__PI_RESERVED20_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED20_SHIFT 16U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED20_WIDTH 4U
+#define LPDDR4__PI_RESERVED20__REG DENALI_PI_77
+#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_77__PI_RESERVED20
+
+#define LPDDR4__DENALI_PI_77__PI_RESERVED21_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED21_SHIFT 24U
+#define LPDDR4__DENALI_PI_77__PI_RESERVED21_WIDTH 4U
+#define LPDDR4__PI_RESERVED21__REG DENALI_PI_77
+#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_77__PI_RESERVED21
+
+#define LPDDR4__DENALI_PI_78_READ_MASK 0x000F0F0FU
+#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x000F0F0FU
+#define LPDDR4__DENALI_PI_78__PI_RESERVED22_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_78__PI_RESERVED22_SHIFT 0U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED22_WIDTH 4U
+#define LPDDR4__PI_RESERVED22__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_78__PI_RESERVED22
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED23_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED23_SHIFT 8U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED23_WIDTH 4U
+#define LPDDR4__PI_RESERVED23__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_78__PI_RESERVED23
+
+#define LPDDR4__DENALI_PI_78__PI_RESERVED24_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED24_SHIFT 16U
+#define LPDDR4__DENALI_PI_78__PI_RESERVED24_WIDTH 4U
+#define LPDDR4__PI_RESERVED24__REG DENALI_PI_78
+#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_78__PI_RESERVED24
+
+#define LPDDR4__DENALI_PI_79_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_WIDTH 28U
+#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_79
+#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_79__PI_INT_STATUS
+
+#define LPDDR4__DENALI_PI_80__PI_INT_ACK_MASK 0x07FFFFFFU
+#define LPDDR4__DENALI_PI_80__PI_INT_ACK_SHIFT 0U
+#define LPDDR4__DENALI_PI_80__PI_INT_ACK_WIDTH 27U
+#define LPDDR4__PI_INT_ACK__REG DENALI_PI_80
+#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_80__PI_INT_ACK
+
+#define LPDDR4__DENALI_PI_81_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_81__PI_INT_MASK_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_81__PI_INT_MASK_SHIFT 0U
+#define LPDDR4__DENALI_PI_81__PI_INT_MASK_WIDTH 28U
+#define LPDDR4__PI_INT_MASK__REG DENALI_PI_81
+#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_81__PI_INT_MASK
+
+#define LPDDR4__DENALI_PI_82_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_82_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_82
+#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_PI_83_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_83_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_83
+#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_PI_84_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_84_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_84
+#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2
+
+#define LPDDR4__DENALI_PI_85_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_85_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_WIDTH 32U
+#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_85
+#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3
+
+#define LPDDR4__DENALI_PI_86_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_86
+#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_PI_87_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_87
+#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_PI_88_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_88
+#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2
+
+#define LPDDR4__DENALI_PI_89_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_89
+#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3
+
+#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH 32U
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90
+#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_PI_91_READ_MASK 0x011F1F07U
+#define LPDDR4__DENALI_PI_91_WRITE_MASK 0x011F1F07U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH 3U
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91
+#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT 8U
+#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH 5U
+#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91
+#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN
+
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT 16U
+#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH 5U
+#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91
+#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT 24U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET 0U
+#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91
+#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN
+
+#define LPDDR4__DENALI_PI_92_READ_MASK 0x03030301U
+#define LPDDR4__DENALI_PI_92_WRITE_MASK 0x03030301U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_SHIFT 0U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOSET 0U
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_92
+#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN
+
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 8U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_92
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0
+
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 16U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_92
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1
+
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_SHIFT 24U
+#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_WIDTH 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_92
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2
+
+#define LPDDR4__DENALI_PI_93_READ_MASK 0x03FF0103U
+#define LPDDR4__DENALI_PI_93_WRITE_MASK 0x03FF0103U
+#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_SHIFT 0U
+#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_WIDTH 2U
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_93
+#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3
+
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_93
+#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_SHIFT 16U
+#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_WIDTH 8U
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_93
+#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_SHIFT 24U
+#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_WIDTH 2U
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_93
+#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_PI_94_READ_MASK 0x013F0301U
+#define LPDDR4__DENALI_PI_94_WRITE_MASK 0x013F0301U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_SHIFT 0U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WIDTH 1U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOCLR 0U
+#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOSET 0U
+#define LPDDR4__PI_BIST_GO__REG DENALI_PI_94
+#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_94__PI_BIST_GO
+
+#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_SHIFT 8U
+#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_WIDTH 2U
+#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_94
+#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_94__PI_BIST_RESULT
+
+#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_SHIFT 16U
+#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_WIDTH 6U
+#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_94
+#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_94__PI_ADDR_SPACE
+
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_SHIFT 24U
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOSET 0U
+#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_94
+#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_PI_95_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_95_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_SHIFT 0U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WIDTH 1U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOCLR 0U
+#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOSET 0U
+#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_95
+#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_PI_96_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_WIDTH 32U
+#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_96
+#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_PI_97_READ_MASK 0x0000FF07U
+#define LPDDR4__DENALI_PI_97_WRITE_MASK 0x0000FF07U
+#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_WIDTH 3U
+#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_97
+#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_SHIFT 8U
+#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_WIDTH 8U
+#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_97
+#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN
+
+#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_WIDTH 32U
+#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_98
+#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0
+
+#define LPDDR4__DENALI_PI_99_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_99_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_WIDTH 32U
+#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_99
+#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1
+
+#define LPDDR4__DENALI_PI_100_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_100_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_SHIFT 0U
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_WIDTH 12U
+#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_100
+#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_SHIFT 16U
+#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_WIDTH 12U
+#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_100
+#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP
+
+#define LPDDR4__DENALI_PI_101_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_101_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_101
+#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0
+
+#define LPDDR4__DENALI_PI_102_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_102_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_102
+#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1
+
+#define LPDDR4__DENALI_PI_103_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_103_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_103
+#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0
+
+#define LPDDR4__DENALI_PI_104_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_104_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_104
+#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1
+
+#define LPDDR4__DENALI_PI_105_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_105_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_105
+#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0
+
+#define LPDDR4__DENALI_PI_106_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_106_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_106
+#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1
+
+#define LPDDR4__DENALI_PI_107_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_107
+#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0
+
+#define LPDDR4__DENALI_PI_108_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_108_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_108
+#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1
+
+#define LPDDR4__DENALI_PI_109_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_109
+#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0
+
+#define LPDDR4__DENALI_PI_110_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_110_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_110
+#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1
+
+#define LPDDR4__DENALI_PI_111_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_111_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_111
+#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0
+
+#define LPDDR4__DENALI_PI_112_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_112_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_112
+#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1
+
+#define LPDDR4__DENALI_PI_113_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_113_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_113
+#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0
+
+#define LPDDR4__DENALI_PI_114_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_114_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_114
+#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1
+
+#define LPDDR4__DENALI_PI_115_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_115_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_115
+#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0
+
+#define LPDDR4__DENALI_PI_116_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_116_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_116
+#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1
+
+#define LPDDR4__DENALI_PI_117_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_117_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_117
+#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0
+
+#define LPDDR4__DENALI_PI_118_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_118_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_118
+#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1
+
+#define LPDDR4__DENALI_PI_119_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_119_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_WIDTH 32U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_119
+#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0
+
+#define LPDDR4__DENALI_PI_120_READ_MASK 0x0303070FU
+#define LPDDR4__DENALI_PI_120_WRITE_MASK 0x0303070FU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_WIDTH 4U
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1
+
+#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_SHIFT 8U
+#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_WIDTH 3U
+#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_MODE
+
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_SHIFT 16U
+#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_WIDTH 2U
+#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE
+
+#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_SHIFT 24U
+#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_WIDTH 2U
+#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_120
+#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE
+
+#define LPDDR4__DENALI_PI_121_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_121_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_121
+#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0
+
+#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_122
+#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1
+
+#define LPDDR4__DENALI_PI_123_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_123
+#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2
+
+#define LPDDR4__DENALI_PI_124_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_WIDTH 32U
+#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_124
+#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3
+
+#define LPDDR4__DENALI_PI_125_READ_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_SHIFT 0U
+#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_WIDTH 4U
+#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_125
+#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM
+
+#define LPDDR4__DENALI_PI_126_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_126
+#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0
+
+#define LPDDR4__DENALI_PI_127_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_127
+#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1
+
+#define LPDDR4__DENALI_PI_128_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_128
+#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2
+
+#define LPDDR4__DENALI_PI_129_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_129
+#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3
+
+#define LPDDR4__DENALI_PI_130_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_SHIFT 0U
+#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_130
+#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4
+
+#define LPDDR4__DENALI_PI_131_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_SHIFT 0U
+#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_131
+#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5
+
+#define LPDDR4__DENALI_PI_132_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_SHIFT 0U
+#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_132
+#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6
+
+#define LPDDR4__DENALI_PI_133_READ_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_133_WRITE_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU
+#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_SHIFT 0U
+#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_WIDTH 30U
+#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_133
+#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7
+
+#define LPDDR4__DENALI_PI_134_READ_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_134_WRITE_MASK 0x0101010FU
+#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_SHIFT 0U
+#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_WIDTH 4U
+#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_134
+#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_134__PI_COL_DIFF
+
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOSET 0U
+#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_134
+#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN
+
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET 0U
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134
+#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 24U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U
+#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134
+#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_PI_135_READ_MASK 0x01010100U
+#define LPDDR4__DENALI_PI_135_WRITE_MASK 0x01010100U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_SHIFT 0U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WIDTH 1U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOCLR 0U
+#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOSET 0U
+#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_135
+#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ
+
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT 8U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET 0U
+#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT 16U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET 0U
+#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT
+
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135
+#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT
+
+#define LPDDR4__DENALI_PI_136_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_136_WRITE_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_SHIFT 0U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOSET 0U
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_136
+#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_PI_137_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_SHIFT 0U
+#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_WIDTH 32U
+#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_137
+#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_137__PI_TRST_PWRON
+
+#define LPDDR4__DENALI_PI_138_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_138_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_SHIFT 0U
+#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_WIDTH 32U
+#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_138
+#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE
+
+#define LPDDR4__DENALI_PI_139_READ_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PI_139_WRITE_MASK 0xFFFF0101U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_SHIFT 0U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WIDTH 1U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOCLR 0U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOSET 0U
+#define LPDDR4__PI_DLL_RST__REG DENALI_PI_139
+#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST
+
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_SHIFT 8U
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOSET 0U
+#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_139
+#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN
+
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_SHIFT 16U
+#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_WIDTH 16U
+#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_139
+#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY
+
+#define LPDDR4__DENALI_PI_140_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_SHIFT 0U
+#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_WIDTH 8U
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_140
+#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_PI_141_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_SHIFT 0U
+#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_WIDTH 26U
+#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_141
+#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG
+
+#define LPDDR4__DENALI_PI_142_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_SHIFT 0U
+#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_WIDTH 8U
+#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_142
+#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_142__PI_MRW_STATUS
+
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK 0x01FFFF00U
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT 8U
+#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH 17U
+#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142
+#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG
+
+#define LPDDR4__DENALI_PI_143_READ_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x01FFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143
+#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0
+
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT 24U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH 1U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR 0U
+#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET 0U
+#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143
+#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT
+
+#define LPDDR4__DENALI_PI_144_READ_MASK 0x0101000FU
+#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x0101000FU
+#define LPDDR4__DENALI_PI_144__PI_RESERVED25_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_144__PI_RESERVED25_SHIFT 0U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED25_WIDTH 4U
+#define LPDDR4__PI_RESERVED25__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_144__PI_RESERVED25
+
+#define LPDDR4__DENALI_PI_144__PI_RESERVED26_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED26_SHIFT 8U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED26_WIDTH 4U
+#define LPDDR4__PI_RESERVED26__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_144__PI_RESERVED26
+
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT 16U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH 1U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR 0U
+#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET 0U
+#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144
+#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_SHIFT 24U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WIDTH 1U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOCLR 0U
+#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOSET 0U
+#define LPDDR4__PI_RESERVED27__REG DENALI_PI_144
+#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_144__PI_RESERVED27
+
+#define LPDDR4__DENALI_PI_145_READ_MASK 0xFF010F07U
+#define LPDDR4__DENALI_PI_145_WRITE_MASK 0xFF010F07U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED28_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED28_SHIFT 0U
+#define LPDDR4__DENALI_PI_145__PI_RESERVED28_WIDTH 3U
+#define LPDDR4__PI_RESERVED28__REG DENALI_PI_145
+#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_145__PI_RESERVED28
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH 1U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR 0U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0
+
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH 8U
+#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145
+#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0
+
+#define LPDDR4__DENALI_PI_146_READ_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH 1U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR 0U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH 8U
+#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1
+
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146
+#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2
+
+#define LPDDR4__DENALI_PI_147_READ_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH 1U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR 0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH 8U
+#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3
+
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH 1U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR 0U
+#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147
+#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3
+
+#define LPDDR4__DENALI_PI_148_READ_MASK 0xFF010FFFU
+#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFF010FFFU
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH 8U
+#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT 8U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT 16U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH 1U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR 0U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4
+
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT 24U
+#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH 8U
+#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148
+#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4
+
+#define LPDDR4__DENALI_PI_149_READ_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_149_WRITE_MASK 0x0FFF010FU
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT 0U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT 8U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH 1U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR 0U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT 16U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH 8U
+#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5
+
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT 24U
+#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149
+#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6
+
+#define LPDDR4__DENALI_PI_150_READ_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_150_WRITE_MASK 0x010FFF01U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT 0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH 1U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR 0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT 8U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH 8U
+#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT 16U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH 4U
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7
+
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT 24U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH 1U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR 0U
+#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET 0U
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150
+#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7
+
+#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT 0U
+#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH 8U
+#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151
+#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7
+
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT 0U
+#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH 8U
+#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152
+#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE
+
+#define LPDDR4__DENALI_PI_153_READ_MASK 0x011F1F01U
+#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x011F1F01U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT 0U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH 1U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR 0U
+#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET 0U
+#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153
+#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK
+
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT 8U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH 5U
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153
+#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS
+
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT 16U
+#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH 5U
+#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153
+#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM
+
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_SHIFT 24U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WIDTH 1U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOCLR 0U
+#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOSET 0U
+#define LPDDR4__PI_RESERVED29__REG DENALI_PI_153
+#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_153__PI_RESERVED29
+
+#define LPDDR4__DENALI_PI_154_READ_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x01010103U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT 0U
+#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH 2U
+#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154
+#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_SHIFT 8U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WIDTH 1U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOCLR 0U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOSET 0U
+#define LPDDR4__PI_RESERVED30__REG DENALI_PI_154
+#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_154__PI_RESERVED30
+
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET 0U
+#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154
+#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN
+
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_SHIFT 24U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WIDTH 1U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOCLR 0U
+#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOSET 0U
+#define LPDDR4__PI_RESERVED31__REG DENALI_PI_154
+#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_154__PI_RESERVED31
+
+#define LPDDR4__DENALI_PI_155_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_SHIFT 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WIDTH 1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOCLR 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOSET 0U
+#define LPDDR4__PI_RESERVED32__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_155__PI_RESERVED32
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_SHIFT 8U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WIDTH 1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOCLR 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOSET 0U
+#define LPDDR4__PI_RESERVED33__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_155__PI_RESERVED33
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_SHIFT 16U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WIDTH 1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOCLR 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOSET 0U
+#define LPDDR4__PI_RESERVED34__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_155__PI_RESERVED34
+
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT 24U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH 1U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR 0U
+#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET 0U
+#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155
+#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35
+
+#define LPDDR4__DENALI_PI_156_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_SHIFT 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOSET 0U
+#define LPDDR4__PI_RESERVED36__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_156__PI_RESERVED36
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_SHIFT 8U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOSET 0U
+#define LPDDR4__PI_RESERVED37__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_156__PI_RESERVED37
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_SHIFT 16U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOSET 0U
+#define LPDDR4__PI_RESERVED38__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_156__PI_RESERVED38
+
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT 24U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH 1U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR 0U
+#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET 0U
+#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156
+#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39
+
+#define LPDDR4__DENALI_PI_157_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_157_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_SHIFT 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WIDTH 1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOCLR 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOSET 0U
+#define LPDDR4__PI_RESERVED40__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_157__PI_RESERVED40
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_SHIFT 8U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WIDTH 1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOCLR 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOSET 0U
+#define LPDDR4__PI_RESERVED41__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_157__PI_RESERVED41
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_SHIFT 16U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WIDTH 1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOCLR 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOSET 0U
+#define LPDDR4__PI_RESERVED42__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_157__PI_RESERVED42
+
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT 24U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH 1U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR 0U
+#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET 0U
+#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157
+#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43
+
+#define LPDDR4__DENALI_PI_158_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_SHIFT 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WIDTH 1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOCLR 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOSET 0U
+#define LPDDR4__PI_RESERVED44__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_158__PI_RESERVED44
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_SHIFT 8U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WIDTH 1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOCLR 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOSET 0U
+#define LPDDR4__PI_RESERVED45__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_158__PI_RESERVED45
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_SHIFT 16U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WIDTH 1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOCLR 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOSET 0U
+#define LPDDR4__PI_RESERVED46__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_158__PI_RESERVED46
+
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT 24U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH 1U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR 0U
+#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET 0U
+#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158
+#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47
+
+#define LPDDR4__DENALI_PI_159_READ_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT 0U
+#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159
+#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND
+
+#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_SHIFT 8U
+#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_WIDTH 9U
+#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_159
+#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_159__PI_TREFBW_THR
+
+#define LPDDR4__DENALI_PI_160_READ_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_160_WRITE_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U
+#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_160
+#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY
+
+#define LPDDR4__DENALI_PI_161_READ_MASK 0x0F011F01U
+#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0F011F01U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U
+#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOSET 0U
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_161
+#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PI_161__PI_RESERVED48_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_161__PI_RESERVED48_SHIFT 8U
+#define LPDDR4__DENALI_PI_161__PI_RESERVED48_WIDTH 5U
+#define LPDDR4__PI_RESERVED48__REG DENALI_PI_161
+#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_161__PI_RESERVED48
+
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_SHIFT 16U
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WIDTH 1U
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOCLR 0U
+#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOSET 0U
+#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_161
+#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN
+
+#define LPDDR4__DENALI_PI_161__PI_CATR_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_161__PI_CATR_SHIFT 24U
+#define LPDDR4__DENALI_PI_161__PI_CATR_WIDTH 4U
+#define LPDDR4__PI_CATR__REG DENALI_PI_161
+#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_161__PI_CATR
+
+#define LPDDR4__DENALI_PI_162_READ_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x01010101U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT 0U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH 1U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR 0U
+#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET 0U
+#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162
+#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ
+
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_SHIFT 8U
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WIDTH 1U
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOCLR 0U
+#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOSET 0U
+#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_162
+#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE
+
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_MASK 0x00010000U
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_SHIFT 16U
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WIDTH 1U
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOCLR 0U
+#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOSET 0U
+#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_162
+#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC
+
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_SHIFT 24U
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WIDTH 1U
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOCLR 0U
+#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOSET 0U
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_162
+#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START
+
+#define LPDDR4__DENALI_PI_163_READ_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_PI_163_WRITE_MASK 0xFFFFFF01U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_MASK 0x00000001U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_SHIFT 0U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WIDTH 1U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOCLR 0U
+#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOSET 0U
+#define LPDDR4__PI_TRACE_MC_MR13__REG DENALI_PI_163
+#define LPDDR4__PI_TRACE_MC_MR13__FLD LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13
+
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_WIDTH 8U
+#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_163
+#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F0
+
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_WIDTH 8U
+#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_163
+#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F1
+
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_WIDTH 8U
+#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_163
+#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F2
+
+#define LPDDR4__DENALI_PI_164_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_164_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_164
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0
+
+#define LPDDR4__DENALI_PI_165_READ_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_165_WRITE_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_165
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1
+
+#define LPDDR4__DENALI_PI_166_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_166
+#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2
+
+#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_WIDTH 12U
+#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_166
+#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_166__PI_ZQINIT_F0
+
+#define LPDDR4__DENALI_PI_167_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_WIDTH 12U
+#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_167
+#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F1
+
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_WIDTH 12U
+#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_167
+#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F2
+
+#define LPDDR4__DENALI_PI_168_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_WIDTH 7U
+#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_168
+#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F0
+
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_WIDTH 7U
+#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_168
+#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_WIDTH 7U
+#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_168
+#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F1
+
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_WIDTH 7U
+#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_168
+#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_PI_169_READ_MASK 0x03FF7F7FU
+#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x03FF7F7FU
+#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_WIDTH 7U
+#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_169
+#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_169__PI_WRLAT_F2
+
+#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_WIDTH 7U
+#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_169
+#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_WIDTH 10U
+#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_169
+#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_169__PI_TRFC_F0
+
+#define LPDDR4__DENALI_PI_170_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_170__PI_TREF_F0_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_170__PI_TREF_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_170__PI_TREF_F0_WIDTH 20U
+#define LPDDR4__PI_TREF_F0__REG DENALI_PI_170
+#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_170__PI_TREF_F0
+
+#define LPDDR4__DENALI_PI_171_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_171_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_WIDTH 10U
+#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_171
+#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_171__PI_TRFC_F1
+
+#define LPDDR4__DENALI_PI_172_READ_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_172__PI_TREF_F1_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_172__PI_TREF_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_172__PI_TREF_F1_WIDTH 20U
+#define LPDDR4__PI_TREF_F1__REG DENALI_PI_172
+#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_172__PI_TREF_F1
+
+#define LPDDR4__DENALI_PI_173_READ_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_WIDTH 10U
+#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_173
+#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_173__PI_TRFC_F2
+
+#define LPDDR4__DENALI_PI_174_READ_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x0F0FFFFFU
+#define LPDDR4__DENALI_PI_174__PI_TREF_F2_MASK 0x000FFFFFU
+#define LPDDR4__DENALI_PI_174__PI_TREF_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_174__PI_TREF_F2_WIDTH 20U
+#define LPDDR4__PI_TREF_F2__REG DENALI_PI_174
+#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_174__PI_TREF_F2
+
+#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_174
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_PI_175_READ_MASK 0x03030F0FU
+#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x03030F0FU
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_175
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_175
+#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_175
+#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_175
+#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_176_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_176_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_176
+#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_176
+#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0
+
+#define LPDDR4__DENALI_PI_177_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_177_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_177
+#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1
+
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_177
+#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2
+
+#define LPDDR4__DENALI_PI_178_READ_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x01FF01FFU
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_WIDTH 8U
+#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_178
+#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WIDTH 1U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOCLR 0U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOSET 0U
+#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_178
+#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F0
+
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_WIDTH 8U
+#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_178
+#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_MASK 0x01000000U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WIDTH 1U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOCLR 0U
+#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOSET 0U
+#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_178
+#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F1
+
+#define LPDDR4__DENALI_PI_179_READ_MASK 0x0F0F01FFU
+#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x0F0F01FFU
+#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_WIDTH 8U
+#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_179
+#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_MASK 0x00000100U
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WIDTH 1U
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOCLR 0U
+#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOSET 0U
+#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_179
+#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_179__PI_ODT_EN_F2
+
+#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_WIDTH 4U
+#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_179
+#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_179__PI_ODTLON_F0
+
+#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_WIDTH 4U
+#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_179
+#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0
+
+#define LPDDR4__DENALI_PI_180_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_WIDTH 4U
+#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_180
+#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F1
+
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_WIDTH 4U
+#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_180
+#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1
+
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_WIDTH 4U
+#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_180
+#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F2
+
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_WIDTH 4U
+#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_180
+#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2
+
+#define LPDDR4__DENALI_PI_181_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_181
+#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_181
+#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0
+
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_181
+#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_181
+#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1
+
+#define LPDDR4__DENALI_PI_182_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_182
+#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_182
+#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2
+
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_182
+#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0
+
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_182
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0
+
+#define LPDDR4__DENALI_PI_183_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_183_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_183
+#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0
+
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_WIDTH 2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_183
+#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0
+
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_183
+#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1
+
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_183
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1
+
+#define LPDDR4__DENALI_PI_184_READ_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x03030303U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_184
+#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1
+
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_WIDTH 2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_184
+#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1
+
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_184
+#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2
+
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_184
+#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2
+
+#define LPDDR4__DENALI_PI_185_READ_MASK 0x7F7F0303U
+#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x7F7F0303U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_185
+#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2
+
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_WIDTH 2U
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_185
+#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2
+
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_WIDTH 7U
+#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_185
+#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_WIDTH 7U
+#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_185
+#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_186_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_WIDTH 7U
+#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_186
+#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_WIDTH 7U
+#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_186
+#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0
+
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_WIDTH 7U
+#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_186
+#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1
+
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_WIDTH 7U
+#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_186
+#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2
+
+#define LPDDR4__DENALI_PI_187_READ_MASK 0x00070707U
+#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x00070707U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000007U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_187
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_MASK 0x00000700U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_187
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_MASK 0x00070000U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_187
+#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_PI_188_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_188
+#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0
+
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_188
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0
+
+#define LPDDR4__DENALI_PI_189_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_189
+#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1
+
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_189
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1
+
+#define LPDDR4__DENALI_PI_190_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_190
+#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2
+
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_190
+#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2
+
+#define LPDDR4__DENALI_PI_191_READ_MASK 0x1F030303U
+#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x1F030303U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_191
+#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0
+
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_191
+#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1
+
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_191
+#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2
+
+#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_WIDTH 5U
+#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_191
+#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_191__PI_TMRZ_F0
+
+#define LPDDR4__DENALI_PI_192_READ_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_WIDTH 14U
+#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_192
+#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_192__PI_TCAENT_F0
+
+#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_WIDTH 5U
+#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_192
+#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_192__PI_TMRZ_F1
+
+#define LPDDR4__DENALI_PI_193_READ_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_193_WRITE_MASK 0x001F3FFFU
+#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_WIDTH 14U
+#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_193
+#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_193__PI_TCAENT_F1
+
+#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_WIDTH 5U
+#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_193
+#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_193__PI_TMRZ_F2
+
+#define LPDDR4__DENALI_PI_194_READ_MASK 0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_194_WRITE_MASK 0x1F1F3FFFU
+#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_MASK 0x00003FFFU
+#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_WIDTH 14U
+#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_194
+#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_194__PI_TCAENT_F2
+
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_WIDTH 5U
+#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_194
+#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0
+
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_WIDTH 5U
+#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_194
+#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0
+
+#define LPDDR4__DENALI_PI_195_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_WIDTH 10U
+#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_195
+#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0
+
+#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_WIDTH 10U
+#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_195
+#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0
+
+#define LPDDR4__DENALI_PI_196_READ_MASK 0x03FF1F1FU
+#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x03FF1F1FU
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_WIDTH 5U
+#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_196
+#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1
+
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_MASK 0x00001F00U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_WIDTH 5U
+#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_196
+#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1
+
+#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_WIDTH 10U
+#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_196
+#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1
+
+#define LPDDR4__DENALI_PI_197_READ_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x1F1F03FFU
+#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_WIDTH 10U
+#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_197
+#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1
+
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_WIDTH 5U
+#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_197
+#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2
+
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_MASK 0x1F000000U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_WIDTH 5U
+#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_197
+#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2
+
+#define LPDDR4__DENALI_PI_198_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_WIDTH 10U
+#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2
+
+#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_WIDTH 10U
+#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_198
+#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2
+
+#define LPDDR4__DENALI_PI_199_READ_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x7F7F7F7FU
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_199
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_200_READ_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x0F0F7F7FU
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_200
+#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_200
+#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_200
+#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_200
+#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_201_READ_MASK 0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_201_WRITE_MASK 0xFF1F0F0FU
+#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_WIDTH 4U
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_201
+#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_201
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0
+
+#define LPDDR4__DENALI_PI_201__PI_TXP_F0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_201__PI_TXP_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_201__PI_TXP_F0_WIDTH 5U
+#define LPDDR4__PI_TXP_F0__REG DENALI_PI_201
+#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_201__PI_TXP_F0
+
+#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_WIDTH 8U
+#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_201
+#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0
+
+#define LPDDR4__DENALI_PI_202_READ_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_202_WRITE_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_WIDTH 5U
+#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_202
+#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_202__PI_TCKELCK_F0
+
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_202
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1
+
+#define LPDDR4__DENALI_PI_202__PI_TXP_F1_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_202__PI_TXP_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_202__PI_TXP_F1_WIDTH 5U
+#define LPDDR4__PI_TXP_F1__REG DENALI_PI_202
+#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_202__PI_TXP_F1
+
+#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_WIDTH 8U
+#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_202
+#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1
+
+#define LPDDR4__DENALI_PI_203_READ_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_203_WRITE_MASK 0xFF1F0F1FU
+#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_WIDTH 5U
+#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_203
+#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_203__PI_TCKELCK_F1
+
+#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_203
+#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2
+
+#define LPDDR4__DENALI_PI_203__PI_TXP_F2_MASK 0x001F0000U
+#define LPDDR4__DENALI_PI_203__PI_TXP_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_203__PI_TXP_F2_WIDTH 5U
+#define LPDDR4__PI_TXP_F2__REG DENALI_PI_203
+#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_203__PI_TXP_F2
+
+#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_WIDTH 8U
+#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_203
+#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2
+
+#define LPDDR4__DENALI_PI_204_READ_MASK 0x0003FF1FU
+#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x0003FF1FU
+#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_MASK 0x0000001FU
+#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_WIDTH 5U
+#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_204
+#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_204__PI_TCKELCK_F2
+
+#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_204
+#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_PI_205_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_205_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_WIDTH 16U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_205
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_205
+#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_PI_206_READ_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_206_WRITE_MASK 0x03FFFFFFU
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_WIDTH 16U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_206
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_206
+#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_PI_207_READ_MASK 0x003FFFFFU
+#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x003FFFFFU
+#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_WIDTH 16U
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_207
+#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_WIDTH 6U
+#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_207
+#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0
+
+#define LPDDR4__DENALI_PI_208_READ_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_208__PI_TFC_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_208__PI_TFC_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_208__PI_TFC_F0_WIDTH 10U
+#define LPDDR4__PI_TFC_F0__REG DENALI_PI_208
+#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_208__PI_TFC_F0
+
+#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_WIDTH 6U
+#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_208
+#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1
+
+#define LPDDR4__DENALI_PI_209_READ_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_209_WRITE_MASK 0x003F03FFU
+#define LPDDR4__DENALI_PI_209__PI_TFC_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_209__PI_TFC_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_209__PI_TFC_F1_WIDTH 10U
+#define LPDDR4__PI_TFC_F1__REG DENALI_PI_209
+#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_209__PI_TFC_F1
+
+#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_WIDTH 6U
+#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_209
+#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2
+
+#define LPDDR4__DENALI_PI_210_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_210_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_210__PI_TFC_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_210__PI_TFC_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_210__PI_TFC_F2_WIDTH 10U
+#define LPDDR4__PI_TFC_F2__REG DENALI_PI_210
+#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_210__PI_TFC_F2
+
+#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_210
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0
+
+#define LPDDR4__DENALI_PI_211_READ_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_211_WRITE_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_211
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0
+
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_211
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0
+
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_211
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
+
+#define LPDDR4__DENALI_PI_212_READ_MASK 0x0003030FU
+#define LPDDR4__DENALI_PI_212_WRITE_MASK 0x0003030FU
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_212
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0
+
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_212
+#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0
+
+#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_WIDTH 2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_212
+#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0
+
+#define LPDDR4__DENALI_PI_213_READ_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x03FF03FFU
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_213
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1
+
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_213
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1
+
+#define LPDDR4__DENALI_PI_214_READ_MASK 0x030F7F7FU
+#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x030F7F7FU
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_214
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1
+
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_214
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
+
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_214
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1
+
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_MASK 0x03000000U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_214
+#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1
+
+#define LPDDR4__DENALI_PI_215_READ_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x0003FF03U
+#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_MASK 0x00000003U
+#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_WIDTH 2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_215
+#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1
+
+#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_215
+#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2
+
+#define LPDDR4__DENALI_PI_216_READ_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x7F7F03FFU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU
+#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_216
+#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2
+
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_216
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2
+
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_216
+#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
+
+#define LPDDR4__DENALI_PI_217_READ_MASK 0xFF03030FU
+#define LPDDR4__DENALI_PI_217_WRITE_MASK 0xFF03030FU
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_217
+#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2
+
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_MASK 0x00000300U
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_WIDTH 2U
+#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_217
+#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2
+
+#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U
+#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_WIDTH 2U
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_217
+#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2
+
+#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_WIDTH 8U
+#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_217
+#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_217__PI_TRTP_F0
+
+#define LPDDR4__DENALI_PI_218_READ_MASK 0xFF3FFFFFU
+#define LPDDR4__DENALI_PI_218_WRITE_MASK 0xFF3FFFFFU
+#define LPDDR4__DENALI_PI_218__PI_TRP_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_218__PI_TRP_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_218__PI_TRP_F0_WIDTH 8U
+#define LPDDR4__PI_TRP_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_218__PI_TRP_F0
+
+#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_WIDTH 8U
+#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_218__PI_TRCD_F0
+
+#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_WIDTH 6U
+#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWTR_F0
+
+#define LPDDR4__DENALI_PI_218__PI_TWR_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_218__PI_TWR_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_218__PI_TWR_F0_WIDTH 8U
+#define LPDDR4__PI_TWR_F0__REG DENALI_PI_218
+#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWR_F0
+
+#define LPDDR4__DENALI_PI_219_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_219_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_WIDTH 17U
+#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_219
+#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0
+
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_WIDTH 8U
+#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_219
+#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0
+
+#define LPDDR4__DENALI_PI_220_READ_MASK 0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_220_WRITE_MASK 0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_WIDTH 4U
+#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_220
+#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_WIDTH 6U
+#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_220
+#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_220__PI_TCCDMW_F0
+
+#define LPDDR4__DENALI_PI_220__PI_TSR_F0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_220__PI_TSR_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_220__PI_TSR_F0_WIDTH 8U
+#define LPDDR4__PI_TSR_F0__REG DENALI_PI_220
+#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_220__PI_TSR_F0
+
+#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_SHIFT 24U
+#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_WIDTH 8U
+#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_220
+#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_220__PI_TMRD_F0
+
+#define LPDDR4__DENALI_PI_221_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_221_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_WIDTH 8U
+#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_221
+#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRW_F0
+
+#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_WIDTH 8U
+#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_221
+#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRTP_F1
+
+#define LPDDR4__DENALI_PI_221__PI_TRP_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_221__PI_TRP_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_221__PI_TRP_F1_WIDTH 8U
+#define LPDDR4__PI_TRP_F1__REG DENALI_PI_221
+#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRP_F1
+
+#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_WIDTH 8U
+#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_221
+#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_221__PI_TRCD_F1
+
+#define LPDDR4__DENALI_PI_222_READ_MASK 0x0000FF3FU
+#define LPDDR4__DENALI_PI_222_WRITE_MASK 0x0000FF3FU
+#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_WIDTH 6U
+#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWTR_F1
+
+#define LPDDR4__DENALI_PI_222__PI_TWR_F1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_222__PI_TWR_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_222__PI_TWR_F1_WIDTH 8U
+#define LPDDR4__PI_TWR_F1__REG DENALI_PI_222
+#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWR_F1
+
+#define LPDDR4__DENALI_PI_223_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_223_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_WIDTH 17U
+#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_223
+#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1
+
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_WIDTH 8U
+#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_223
+#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1
+
+#define LPDDR4__DENALI_PI_224_READ_MASK 0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_224_WRITE_MASK 0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_WIDTH 4U
+#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_WIDTH 6U
+#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_224__PI_TCCDMW_F1
+
+#define LPDDR4__DENALI_PI_224__PI_TSR_F1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_224__PI_TSR_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_224__PI_TSR_F1_WIDTH 8U
+#define LPDDR4__PI_TSR_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_224__PI_TSR_F1
+
+#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_WIDTH 8U
+#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_224
+#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_224__PI_TMRD_F1
+
+#define LPDDR4__DENALI_PI_225_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_225_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_WIDTH 8U
+#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_225
+#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_225__PI_TMRW_F1
+
+#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_WIDTH 8U
+#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_225
+#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRTP_F2
+
+#define LPDDR4__DENALI_PI_225__PI_TRP_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_225__PI_TRP_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_225__PI_TRP_F2_WIDTH 8U
+#define LPDDR4__PI_TRP_F2__REG DENALI_PI_225
+#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRP_F2
+
+#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_WIDTH 8U
+#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_225
+#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_225__PI_TRCD_F2
+
+#define LPDDR4__DENALI_PI_226_READ_MASK 0x0000FF3FU
+#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x0000FF3FU
+#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_WIDTH 6U
+#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_226
+#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWTR_F2
+
+#define LPDDR4__DENALI_PI_226__PI_TWR_F2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_226__PI_TWR_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_226__PI_TWR_F2_WIDTH 8U
+#define LPDDR4__PI_TWR_F2__REG DENALI_PI_226
+#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWR_F2
+
+#define LPDDR4__DENALI_PI_227_READ_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_227_WRITE_MASK 0xFF01FFFFU
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_MASK 0x0001FFFFU
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_WIDTH 17U
+#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_227
+#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2
+
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_WIDTH 8U
+#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_227
+#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2
+
+#define LPDDR4__DENALI_PI_228_READ_MASK 0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_228_WRITE_MASK 0xFFFF3F0FU
+#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_WIDTH 4U
+#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_MASK 0x00003F00U
+#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_SHIFT 8U
+#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_WIDTH 6U
+#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_228__PI_TCCDMW_F2
+
+#define LPDDR4__DENALI_PI_228__PI_TSR_F2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_228__PI_TSR_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_228__PI_TSR_F2_WIDTH 8U
+#define LPDDR4__PI_TSR_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_228__PI_TSR_F2
+
+#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_SHIFT 24U
+#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_WIDTH 8U
+#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_228
+#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_228__PI_TMRD_F2
+
+#define LPDDR4__DENALI_PI_229_READ_MASK 0x1FFFFFFFU
+#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x1FFFFFFFU
+#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_WIDTH 8U
+#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_229
+#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_229__PI_TMRW_F2
+
+#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x1FFFFF00U
+#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_229
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_PI_230_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_230_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_230
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_PI_231_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_231_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_231
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_PI_232_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_232_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_232
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_PI_233_READ_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
+#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_233
+#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_PI_234_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_234_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_234
+#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_PI_235_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_235_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_WIDTH 16U
+#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_235
+#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F0
+
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_WIDTH 16U
+#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_235
+#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F1
+
+#define LPDDR4__DENALI_PI_236_READ_MASK 0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_236_WRITE_MASK 0x3F3FFFFFU
+#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_WIDTH 16U
+#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_236
+#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_236__PI_TXSR_F2
+
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_WIDTH 6U
+#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_236
+#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F0
+
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_MASK 0x3F000000U
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_SHIFT 24U
+#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_WIDTH 6U
+#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_236
+#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F1
+
+#define LPDDR4__DENALI_PI_237_READ_MASK 0xFFFFFF3FU
+#define LPDDR4__DENALI_PI_237_WRITE_MASK 0xFFFFFF3FU
+#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_MASK 0x0000003FU
+#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_WIDTH 6U
+#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_237
+#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_237__PI_TEXCKE_F2
+
+#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_MASK 0xFFFFFF00U
+#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_SHIFT 8U
+#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_237
+#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_237__PI_TINIT_F0
+
+#define LPDDR4__DENALI_PI_238_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_238
+#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_238__PI_TINIT3_F0
+
+#define LPDDR4__DENALI_PI_239_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_239
+#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_239__PI_TINIT4_F0
+
+#define LPDDR4__DENALI_PI_240_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_240_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_WIDTH 24U
+#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_240
+#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_240__PI_TINIT5_F0
+
+#define LPDDR4__DENALI_PI_241_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_241_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_WIDTH 16U
+#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_241
+#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_241__PI_TXSNR_F0
+
+#define LPDDR4__DENALI_PI_242_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_242_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_242
+#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_242__PI_TINIT_F1
+
+#define LPDDR4__DENALI_PI_243_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_243_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_243
+#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_243__PI_TINIT3_F1
+
+#define LPDDR4__DENALI_PI_244_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_244
+#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_244__PI_TINIT4_F1
+
+#define LPDDR4__DENALI_PI_245_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_245_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_WIDTH 24U
+#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_245
+#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_245__PI_TINIT5_F1
+
+#define LPDDR4__DENALI_PI_246_READ_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_WIDTH 16U
+#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_246
+#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_246__PI_TXSNR_F1
+
+#define LPDDR4__DENALI_PI_247_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_247_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_247
+#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_247__PI_TINIT_F2
+
+#define LPDDR4__DENALI_PI_248_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_248_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_248
+#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_248__PI_TINIT3_F2
+
+#define LPDDR4__DENALI_PI_249_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_249_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_249
+#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_249__PI_TINIT4_F2
+
+#define LPDDR4__DENALI_PI_250_READ_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_250_WRITE_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_MASK 0x00FFFFFFU
+#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_WIDTH 24U
+#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_250
+#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_250__PI_TINIT5_F2
+
+#define LPDDR4__DENALI_PI_251_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_WIDTH 16U
+#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_251
+#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_251__PI_TXSNR_F2
+
+#define LPDDR4__DENALI_PI_251__PI_RESERVED49_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_251__PI_RESERVED49_SHIFT 16U
+#define LPDDR4__DENALI_PI_251__PI_RESERVED49_WIDTH 12U
+#define LPDDR4__PI_RESERVED49__REG DENALI_PI_251
+#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_251__PI_RESERVED49
+
+#define LPDDR4__DENALI_PI_252_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_252_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_252__PI_RESERVED50_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_252__PI_RESERVED50_SHIFT 0U
+#define LPDDR4__DENALI_PI_252__PI_RESERVED50_WIDTH 12U
+#define LPDDR4__PI_RESERVED50__REG DENALI_PI_252
+#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_252__PI_RESERVED50
+
+#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_SHIFT 16U
+#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_WIDTH 12U
+#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_252
+#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_252__PI_TZQCAL_F0
+
+#define LPDDR4__DENALI_PI_253_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_253_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_WIDTH 7U
+#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_253
+#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_253__PI_TZQLAT_F0
+
+#define LPDDR4__DENALI_PI_253__PI_RESERVED51_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_253__PI_RESERVED51_SHIFT 8U
+#define LPDDR4__DENALI_PI_253__PI_RESERVED51_WIDTH 12U
+#define LPDDR4__PI_RESERVED51__REG DENALI_PI_253
+#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_253__PI_RESERVED51
+
+#define LPDDR4__DENALI_PI_254_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_254_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_254__PI_RESERVED52_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_254__PI_RESERVED52_SHIFT 0U
+#define LPDDR4__DENALI_PI_254__PI_RESERVED52_WIDTH 12U
+#define LPDDR4__PI_RESERVED52__REG DENALI_PI_254
+#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_254__PI_RESERVED52
+
+#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_SHIFT 16U
+#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_WIDTH 12U
+#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_254
+#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_254__PI_TZQCAL_F1
+
+#define LPDDR4__DENALI_PI_255_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_SHIFT 0U
+#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_WIDTH 7U
+#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_255
+#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_255__PI_TZQLAT_F1
+
+#define LPDDR4__DENALI_PI_255__PI_RESERVED53_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_255__PI_RESERVED53_SHIFT 8U
+#define LPDDR4__DENALI_PI_255__PI_RESERVED53_WIDTH 12U
+#define LPDDR4__PI_RESERVED53__REG DENALI_PI_255
+#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_255__PI_RESERVED53
+
+#define LPDDR4__DENALI_PI_256_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_256_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_256__PI_RESERVED54_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_256__PI_RESERVED54_SHIFT 0U
+#define LPDDR4__DENALI_PI_256__PI_RESERVED54_WIDTH 12U
+#define LPDDR4__PI_RESERVED54__REG DENALI_PI_256
+#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_256__PI_RESERVED54
+
+#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_WIDTH 12U
+#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_256
+#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_256__PI_TZQCAL_F2
+
+#define LPDDR4__DENALI_PI_257_READ_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_257_WRITE_MASK 0x000FFF7FU
+#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_MASK 0x0000007FU
+#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_SHIFT 0U
+#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_WIDTH 7U
+#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_257
+#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_257__PI_TZQLAT_F2
+
+#define LPDDR4__DENALI_PI_257__PI_RESERVED55_MASK 0x000FFF00U
+#define LPDDR4__DENALI_PI_257__PI_RESERVED55_SHIFT 8U
+#define LPDDR4__DENALI_PI_257__PI_RESERVED55_WIDTH 12U
+#define LPDDR4__PI_RESERVED55__REG DENALI_PI_257
+#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_257__PI_RESERVED55
+
+#define LPDDR4__DENALI_PI_258_READ_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0FFF0FFFU
+#define LPDDR4__DENALI_PI_258__PI_RESERVED56_MASK 0x00000FFFU
+#define LPDDR4__DENALI_PI_258__PI_RESERVED56_SHIFT 0U
+#define LPDDR4__DENALI_PI_258__PI_RESERVED56_WIDTH 12U
+#define LPDDR4__PI_RESERVED56__REG DENALI_PI_258
+#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_258__PI_RESERVED56
+
+#define LPDDR4__DENALI_PI_258__PI_RESERVED57_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PI_258__PI_RESERVED57_SHIFT 16U
+#define LPDDR4__DENALI_PI_258__PI_RESERVED57_WIDTH 12U
+#define LPDDR4__PI_RESERVED57__REG DENALI_PI_258
+#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_258__PI_RESERVED57
+
+#define LPDDR4__DENALI_PI_259_READ_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_PI_259_WRITE_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_259
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0
+
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_259
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1
+
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U
+#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_259
+#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2
+
+#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_259
+#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_259__PI_MR13_DATA_0
+
+#define LPDDR4__DENALI_PI_260_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_260
+#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR15_DATA_0
+
+#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_260
+#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR16_DATA_0
+
+#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_260
+#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR17_DATA_0
+
+#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_260
+#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR20_DATA_0
+
+#define LPDDR4__DENALI_PI_261_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_261_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_261
+#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR32_DATA_0
+
+#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_261
+#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR40_DATA_0
+
+#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_261
+#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR13_DATA_1
+
+#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_261
+#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR15_DATA_1
+
+#define LPDDR4__DENALI_PI_262_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_262
+#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR16_DATA_1
+
+#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_262
+#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR17_DATA_1
+
+#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_262
+#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR20_DATA_1
+
+#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_262
+#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR32_DATA_1
+
+#define LPDDR4__DENALI_PI_263_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_263_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_263
+#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_263__PI_MR40_DATA_1
+
+#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_263
+#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR13_DATA_2
+
+#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_263
+#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR15_DATA_2
+
+#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_263
+#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR16_DATA_2
+
+#define LPDDR4__DENALI_PI_264_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_264
+#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR17_DATA_2
+
+#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_264
+#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR20_DATA_2
+
+#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_264
+#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR32_DATA_2
+
+#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_264
+#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR40_DATA_2
+
+#define LPDDR4__DENALI_PI_265_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_265_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_265
+#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR13_DATA_3
+
+#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_265
+#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR15_DATA_3
+
+#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_265
+#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR16_DATA_3
+
+#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_265
+#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR17_DATA_3
+
+#define LPDDR4__DENALI_PI_266_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_266
+#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR20_DATA_3
+
+#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_266
+#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR32_DATA_3
+
+#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_266
+#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR40_DATA_3
+
+#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_WIDTH 4U
+#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_266
+#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_266__PI_CKE_MUX_0
+
+#define LPDDR4__DENALI_PI_267_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_WIDTH 4U
+#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_267
+#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_1
+
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_WIDTH 4U
+#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_267
+#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_2
+
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_WIDTH 4U
+#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_267
+#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_3
+
+#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_WIDTH 4U
+#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_267
+#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_267__PI_CS_MUX_0
+
+#define LPDDR4__DENALI_PI_268_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_268_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_WIDTH 4U
+#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_268
+#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_1
+
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_WIDTH 4U
+#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_268
+#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_2
+
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_WIDTH 4U
+#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_268
+#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_3
+
+#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_WIDTH 4U
+#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_268
+#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0
+
+#define LPDDR4__DENALI_PI_269_READ_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_PI_269_WRITE_MASK 0xFF0F0F0FU
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_WIDTH 4U
+#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_269
+#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1
+
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_WIDTH 4U
+#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_269
+#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2
+
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_WIDTH 4U
+#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_269
+#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3
+
+#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_WIDTH 8U
+#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_269
+#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_PI_270_READ_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x0FFFFFFFU
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_WIDTH 8U
+#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_270
+#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_WIDTH 8U
+#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_270
+#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2
+
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_WIDTH 8U
+#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_270
+#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3
+
+#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_270
+#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_PI_271_READ_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x0F0F0F0FU
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_271
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_271
+#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_271
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_271
+#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2
+
+#define LPDDR4__DENALI_PI_272_READ_MASK 0x000F0F0FU
+#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x000F0F0FU
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_MASK 0x0000000FU
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_272
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2
+
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_MASK 0x00000F00U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_272
+#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3
+
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_MASK 0x000F0000U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_WIDTH 4U
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_272
+#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3
+
+#define LPDDR4__DENALI_PI_273_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_273_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_273
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0
+
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_273
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0
+
+#define LPDDR4__DENALI_PI_274_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_274_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_274
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1
+
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH 16U
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_274
+#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1
+
+#define LPDDR4__DENALI_PI_275_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_275_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_275
+#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_275
+#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_275
+#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_275
+#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_276_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_276_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_276
+#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_276
+#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_276
+#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_276
+#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0
+
+#define LPDDR4__DENALI_PI_277_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_277_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_277
+#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_277
+#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_277
+#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_277
+#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_278_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_278_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_278
+#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_278
+#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_278
+#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_278
+#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0
+
+#define LPDDR4__DENALI_PI_279_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_279_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_279
+#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_279
+#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_279
+#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_279
+#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_280_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_280_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_SHIFT 0U
+#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_280
+#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_SHIFT 8U
+#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_280
+#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_SHIFT 16U
+#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_280
+#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_SHIFT 24U
+#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_280
+#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0
+
+#define LPDDR4__DENALI_PI_281_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_281_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_281
+#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_281
+#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_281
+#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_281
+#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_282_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_282_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_282
+#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_282
+#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_282
+#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_282
+#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1
+
+#define LPDDR4__DENALI_PI_283_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_283_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_283
+#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_283
+#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_283
+#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_283
+#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_284_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_284_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_284
+#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_284
+#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_284
+#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_284
+#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1
+
+#define LPDDR4__DENALI_PI_285_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_285_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_285
+#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_286_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_286_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_SHIFT 0U
+#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_SHIFT 8U
+#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_SHIFT 16U
+#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_SHIFT 24U
+#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_286
+#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1
+
+#define LPDDR4__DENALI_PI_287_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_287_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_287
+#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_287
+#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_287
+#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_287
+#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_288_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_288_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_288
+#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_288
+#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_288
+#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_288
+#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2
+
+#define LPDDR4__DENALI_PI_289_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_289_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_289
+#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_289
+#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_289
+#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_289
+#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_290_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_290_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_290
+#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_290
+#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_290
+#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_290
+#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2
+
+#define LPDDR4__DENALI_PI_291_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_291_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_291
+#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_291
+#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_291
+#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_291
+#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_292_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_292_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_SHIFT 0U
+#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_292
+#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_SHIFT 8U
+#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_292
+#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_SHIFT 16U
+#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_292
+#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_SHIFT 24U
+#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_292
+#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2
+
+#define LPDDR4__DENALI_PI_293_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_293_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_293
+#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_293
+#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_293
+#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_293
+#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_294_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_294_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_294
+#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_294
+#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_294
+#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_294
+#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3
+
+#define LPDDR4__DENALI_PI_295_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_295_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_295
+#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_295
+#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_295
+#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_295
+#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_296_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_296_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_296
+#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_296
+#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_296
+#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_296
+#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3
+
+#define LPDDR4__DENALI_PI_297_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_297_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_297
+#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_297
+#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_297
+#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_297
+#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_298_READ_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_298_WRITE_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_MASK 0x000000FFU
+#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_SHIFT 0U
+#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_298
+#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_MASK 0x0000FF00U
+#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_SHIFT 8U
+#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_298
+#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_SHIFT 16U
+#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_298
+#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_MASK 0xFF000000U
+#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_SHIFT 24U
+#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_WIDTH 8U
+#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_298
+#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3
+
+#define LPDDR4__DENALI_PI_299_READ_MASK 0x000007FFU
+#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x000007FFU
+#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_MASK 0x000007FFU
+#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_SHIFT 0U
+#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_WIDTH 11U
+#define LPDDR4__PI_PARITY_ERROR_REGIF__REG DENALI_PI_299
+#define LPDDR4__PI_PARITY_ERROR_REGIF__FLD LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF
+
+#endif /* REG_LPDDR4_PI_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
new file mode 100644
index 0000000..8be0011
--- /dev/null
+++ b/drivers/ram/k3-ddrss/Makefile
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+
+obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o
+obj-$(CONFIG_K3_DDRSS) += lpddr4_obj_if.o
+obj-$(CONFIG_K3_DDRSS) += lpddr4.o
+ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/
+
+obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit.o
+obj-$(CONFIG_K3_AM64_DDRSS) += lpddr4_16bit_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
+
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
+obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
diff --git a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
new file mode 100644
index 0000000..298aa5e
--- /dev/null
+++ b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef CPS_DRV_H_
+#define CPS_DRV_H_
+
+#ifdef DEMO_TB
+#include <cdn_demo.h>
+#else
+#include <asm/io.h>
+#endif
+
+#define CPS_REG_READ(reg) (cps_regread((volatile u32 *)(reg)))
+
+#define CPS_REG_WRITE(reg, value) (cps_regwrite((volatile u32 *)(reg), (u32)(value)))
+
+#define CPS_FLD_MASK(fld) (fld ## _MASK)
+#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
+#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
+#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
+#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
+
+#define CPS_FLD_READ(fld, reg_value) (cps_fldread((u32)(CPS_FLD_MASK(fld)), \
+ (u32)(CPS_FLD_SHIFT(fld)), \
+ (u32)(reg_value)))
+
+#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((u32)(CPS_FLD_MASK(fld)), \
+ (u32)(CPS_FLD_SHIFT(fld)), \
+ (u32)(reg_value), (u32)(value)))
+
+#define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \
+ (u32)(CPS_FLD_MASK(fld)), \
+ (u32)(CPS_FLD_WOCLR(fld)), \
+ (u32)(reg_value)))
+
+#ifdef CLR_USED
+#define CPS_FLD_CLEAR(reg, fld, reg_value) (cps_fldclear((u32)(CPS_FLD_WIDTH(fld)), \
+ (u32)(CPS_FLD_MASK(fld)), \
+ (u32)(CPS_FLD_WOSET(fld)), \
+ (u32)(CPS_FLD_WOCLR(fld)), \
+ (u32)(reg_value)))
+
+#endif
+static inline u32 cps_regread(volatile u32 *reg);
+static inline u32 cps_regread(volatile u32 *reg)
+{
+ return readl(reg);
+}
+
+static inline void cps_regwrite(volatile u32 *reg, u32 value);
+static inline void cps_regwrite(volatile u32 *reg, u32 value)
+{
+ writel(value, reg);
+}
+
+static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value);
+static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value)
+{
+ u32 result = (reg_value & mask) >> shift;
+
+ return result;
+}
+
+static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value);
+static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value)
+{
+ u32 new_value = (value << shift) & mask;
+
+ new_value = (reg_value & ~mask) | new_value;
+ return new_value;
+}
+
+static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value);
+static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value)
+{
+ u32 new_value = reg_value;
+
+ if ((width == 1U) && (is_woclr == 0U))
+ new_value |= mask;
+
+ return new_value;
+}
+
+#ifdef CLR_USED
+static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value);
+static inline u32 cps_fldclear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value)
+{
+ u32 new_value = reg_value;
+
+ if ((width == 1U) && (is_woset == 0U))
+ new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
+
+ return new_value;
+}
+#endif /* CLR_USED */
+
+#endif /* CPS_DRV_H_ */
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
new file mode 100644
index 0000000..cb8edcb
--- /dev/null
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Texas Instruments' K3 DDRSS driver
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <dm/device_compat.h>
+#include <ram.h>
+#include <hang.h>
+#include <log.h>
+#include <asm/io.h>
+#include <power-domain.h>
+#include <wait_bit.h>
+#include <power/regulator.h>
+
+#include "lpddr4_obj_if.h"
+#include "lpddr4_if.h"
+#include "lpddr4_structs_if.h"
+#include "lpddr4_ctl_regs.h"
+
+#define SRAM_MAX 512
+
+#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
+#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
+
+#define DDRSS_V2A_R1_MAT_REG 0x0020
+#define DDRSS_ECC_CTRL_REG 0x0120
+
+struct k3_ddrss_desc {
+ struct udevice *dev;
+ void __iomem *ddrss_ss_cfg;
+ void __iomem *ddrss_ctrl_mmr;
+ struct power_domain ddrcfg_pwrdmn;
+ struct power_domain ddrdata_pwrdmn;
+ struct clk ddr_clk;
+ struct clk osc_clk;
+ u32 ddr_freq1;
+ u32 ddr_freq2;
+ u32 ddr_fhs_cnt;
+ struct udevice *vtt_supply;
+};
+
+static lpddr4_obj *driverdt;
+static lpddr4_config config;
+static lpddr4_privatedata pd;
+
+static struct k3_ddrss_desc *ddrss;
+
+struct reginitdata {
+ u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
+ u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
+ u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
+ u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
+ u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT];
+ u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT];
+};
+
+#define TH_MACRO_EXP(fld, str) (fld##str)
+
+#define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK)
+#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
+#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
+#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
+#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
+
+#define str(s) #s
+#define xstr(s) str(s)
+
+#define CTL_SHIFT 11
+#define PHY_SHIFT 11
+#define PI_SHIFT 10
+
+#define DENALI_CTL_0_DRAM_CLASS_DDR4 0xA
+#define DENALI_CTL_0_DRAM_CLASS_LPDDR4 0xB
+
+#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
+ char *i, *pstr = xstr(REG); offset = 0;\
+ for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
+ offset = offset * 10 + (*i - '0'); } \
+ } while (0)
+
+static u32 k3_lpddr4_read_ddr_type(void)
+{
+ u32 status = 0U;
+ u32 offset = 0U;
+ u32 regval = 0U;
+ u32 dram_class = 0U;
+
+ TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
+ status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
+ if (status > 0U) {
+ printf("%s: Failed to read DRAM_CLASS\n", __func__);
+ hang();
+ }
+
+ dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >>
+ TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD));
+ return dram_class;
+}
+
+static void k3_lpddr4_freq_update(void)
+{
+ unsigned int req_type, counter;
+
+ for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
+ if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ true, 10000, false)) {
+ printf("Timeout during frequency handshake\n");
+ hang();
+ }
+
+ req_type = readl(ddrss->ddrss_ctrl_mmr +
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
+
+ debug("%s: received freq change req: req type = %d, req no. = %d\n",
+ __func__, req_type, counter);
+
+ if (req_type == 1)
+ clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
+ else if (req_type == 2)
+ clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
+ else if (req_type == 0)
+ /* Put DDR pll in bypass mode */
+ clk_set_rate(&ddrss->ddr_clk,
+ clk_get_rate(&ddrss->osc_clk));
+ else
+ printf("%s: Invalid freq request type\n", __func__);
+
+ writel(0x1, ddrss->ddrss_ctrl_mmr +
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ false, 10, false)) {
+ printf("Timeout during frequency handshake\n");
+ hang();
+ }
+ writel(0x0, ddrss->ddrss_ctrl_mmr +
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ }
+}
+
+static void k3_lpddr4_ack_freq_upd_req(void)
+{
+ u32 dram_class;
+
+ debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
+
+ dram_class = k3_lpddr4_read_ddr_type();
+
+ switch (dram_class) {
+ case DENALI_CTL_0_DRAM_CLASS_DDR4:
+ break;
+ case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
+ k3_lpddr4_freq_update();
+ break;
+ default:
+ printf("Unrecognized dram_class cannot update frequency!\n");
+ }
+}
+
+static int k3_ddrss_init_freq(struct k3_ddrss_desc *ddrss)
+{
+ u32 dram_class;
+ int ret;
+
+ dram_class = k3_lpddr4_read_ddr_type();
+
+ switch (dram_class) {
+ case DENALI_CTL_0_DRAM_CLASS_DDR4:
+ /* Set to ddr_freq1 from DT for DDR4 */
+ ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
+ break;
+ case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
+ /* Set to bypass frequency for LPDDR4*/
+ ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
+ break;
+ default:
+ ret = -EINVAL;
+ printf("Unrecognized dram_class cannot init frequency!\n");
+ }
+
+ if (ret < 0)
+ dev_err(ddrss->dev, "ddr clk init failed: %d\n", ret);
+ else
+ ret = 0;
+
+ return ret;
+}
+
+static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
+ lpddr4_infotype infotype)
+{
+ if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
+ k3_lpddr4_ack_freq_upd_req();
+}
+
+static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
+{
+ int ret;
+
+ debug("%s(ddrss=%p)\n", __func__, ddrss);
+
+ ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
+ if (ret) {
+ dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
+ if (ret) {
+ dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = device_get_supply_regulator(ddrss->dev, "vtt-supply",
+ &ddrss->vtt_supply);
+ if (ret) {
+ dev_dbg(ddrss->dev, "vtt-supply not found.\n");
+ } else {
+ ret = regulator_set_value(ddrss->vtt_supply, 3300000);
+ if (ret)
+ return ret;
+ dev_dbg(ddrss->dev, "VTT regulator enabled, volt = %d\n",
+ regulator_get_value(ddrss->vtt_supply));
+ }
+
+ return 0;
+}
+
+static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
+{
+ struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
+ phys_addr_t reg;
+ int ret;
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ reg = dev_read_addr_name(dev, "cfg");
+ if (reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "No reg property for DDRSS wrapper logic\n");
+ return -EINVAL;
+ }
+ ddrss->ddrss_ss_cfg = (void *)reg;
+
+ reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
+ if (reg == FDT_ADDR_T_NONE) {
+ dev_err(dev, "No reg property for CTRL MMR\n");
+ return -EINVAL;
+ }
+ ddrss->ddrss_ctrl_mmr = (void *)reg;
+
+ ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
+ if (ret) {
+ dev_err(dev, "power_domain_get() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
+ if (ret) {
+ dev_err(dev, "power_domain_get() failed: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
+ if (ret)
+ dev_err(dev, "clk get failed%d\n", ret);
+
+ ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
+ if (ret)
+ dev_err(dev, "clk get failed for osc clk %d\n", ret);
+
+ ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
+ if (ret)
+ dev_err(dev, "ddr freq1 not populated %d\n", ret);
+
+ ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
+ if (ret)
+ dev_err(dev, "ddr freq2 not populated %d\n", ret);
+
+ ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
+ if (ret)
+ dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
+
+ return ret;
+}
+
+void k3_lpddr4_probe(void)
+{
+ u32 status = 0U;
+ u16 configsize = 0U;
+
+ status = driverdt->probe(&config, &configsize);
+
+ if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
+ || (configsize > SRAM_MAX)) {
+ printf("%s: FAIL\n", __func__);
+ hang();
+ } else {
+ debug("%s: PASS\n", __func__);
+ }
+}
+
+void k3_lpddr4_init(void)
+{
+ u32 status = 0U;
+
+ if ((sizeof(pd) != sizeof(lpddr4_privatedata))
+ || (sizeof(pd) > SRAM_MAX)) {
+ printf("%s: FAIL\n", __func__);
+ hang();
+ }
+
+ config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
+ config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
+
+ status = driverdt->init(&pd, &config);
+
+ if ((status > 0U) ||
+ (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
+ (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
+ (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
+ printf("%s: FAIL\n", __func__);
+ hang();
+ } else {
+ debug("%s: PASS\n", __func__);
+ }
+}
+
+void populate_data_array_from_dt(struct reginitdata *reginit_data)
+{
+ int ret, i;
+
+ ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
+ (u32 *)reginit_data->ctl_regs,
+ LPDDR4_INTR_CTL_REG_COUNT);
+ if (ret)
+ printf("Error reading ctrl data %d\n", ret);
+
+ for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
+ reginit_data->ctl_regs_offs[i] = i;
+
+ ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
+ (u32 *)reginit_data->pi_regs,
+ LPDDR4_INTR_PHY_INDEP_REG_COUNT);
+ if (ret)
+ printf("Error reading PI data\n");
+
+ for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
+ reginit_data->pi_regs_offs[i] = i;
+
+ ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
+ (u32 *)reginit_data->phy_regs,
+ LPDDR4_INTR_PHY_REG_COUNT);
+ if (ret)
+ printf("Error reading PHY data %d\n", ret);
+
+ for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
+ reginit_data->phy_regs_offs[i] = i;
+}
+
+void k3_lpddr4_hardware_reg_init(void)
+{
+ u32 status = 0U;
+ struct reginitdata reginitdata;
+
+ populate_data_array_from_dt(®initdata);
+
+ status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs,
+ reginitdata.ctl_regs_offs,
+ LPDDR4_INTR_CTL_REG_COUNT);
+ if (!status)
+ status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs,
+ reginitdata.pi_regs_offs,
+ LPDDR4_INTR_PHY_INDEP_REG_COUNT);
+ if (!status)
+ status = driverdt->writephyconfig(&pd, reginitdata.phy_regs,
+ reginitdata.phy_regs_offs,
+ LPDDR4_INTR_PHY_REG_COUNT);
+ if (status) {
+ printf("%s: FAIL\n", __func__);
+ hang();
+ }
+}
+
+void k3_lpddr4_start(void)
+{
+ u32 status = 0U;
+ u32 regval = 0U;
+ u32 offset = 0U;
+
+ TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
+
+ status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
+ if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
+ printf("%s: Pre start FAIL\n", __func__);
+ hang();
+ }
+
+ status = driverdt->start(&pd);
+ if (status > 0U) {
+ printf("%s: FAIL\n", __func__);
+ hang();
+ }
+
+ status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
+ if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
+ printf("%s: Post start FAIL\n", __func__);
+ hang();
+ } else {
+ debug("%s: Post start PASS\n", __func__);
+ }
+}
+
+static int k3_ddrss_probe(struct udevice *dev)
+{
+ int ret;
+
+ ddrss = dev_get_priv(dev);
+
+ debug("%s(dev=%p)\n", __func__, dev);
+
+ ret = k3_ddrss_ofdata_to_priv(dev);
+ if (ret)
+ return ret;
+
+ ddrss->dev = dev;
+ ret = k3_ddrss_power_on(ddrss);
+ if (ret)
+ return ret;
+
+#ifdef CONFIG_K3_AM64_DDRSS
+
+ writel(0x000001EF, ddrss->ddrss_ss_cfg + DDRSS_V2A_R1_MAT_REG);
+ writel(0x0, ddrss->ddrss_ss_cfg + DDRSS_ECC_CTRL_REG);
+#endif
+
+ driverdt = lpddr4_getinstance();
+ k3_lpddr4_probe();
+ k3_lpddr4_init();
+ k3_lpddr4_hardware_reg_init();
+
+ ret = k3_ddrss_init_freq(ddrss);
+ if (ret)
+ return ret;
+
+ k3_lpddr4_start();
+
+ return ret;
+}
+
+static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
+{
+ return 0;
+}
+
+static struct ram_ops k3_ddrss_ops = {
+ .get_info = k3_ddrss_get_info,
+};
+
+static const struct udevice_id k3_ddrss_ids[] = {
+ {.compatible = "ti,am64-ddrss"},
+ {.compatible = "ti,j721e-ddrss"},
+ {}
+};
+
+U_BOOT_DRIVER(k3_ddrss) = {
+ .name = "k3_ddrss",
+ .id = UCLASS_RAM,
+ .of_match = k3_ddrss_ids,
+ .ops = &k3_ddrss_ops,
+ .probe = k3_ddrss_probe,
+ .priv_auto = sizeof(struct k3_ddrss_desc),
+};
diff --git a/drivers/ram/k3-ddrss/lpddr4.c b/drivers/ram/k3-ddrss/lpddr4.c
new file mode 100644
index 0000000..78ad966
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4.c
@@ -0,0 +1,1079 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <errno.h>
+
+#include "cps_drv_lpddr4.h"
+#include "lpddr4_if.h"
+#include "lpddr4.h"
+#include "lpddr4_structs_if.h"
+
+#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
+#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
+#endif
+
+#ifndef LPDDR4_CPS_NS_DELAY_TIME
+#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
+#endif
+
+static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay);
+static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd);
+static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd);
+static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval);
+static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits);
+static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
+static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
+static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
+static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
+static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
+static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
+static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
+static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
+static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
+#ifdef REG_WRITE_VERIF
+static u32 lpddr4_getphyrwmask(u32 regoffset);
+static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
+#endif
+
+u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay)
+{
+ u32 result = 0U;
+ u32 timeout = 0U;
+ bool irqstatus = false;
+
+ do {
+ if (++timeout == delay) {
+ result = (u32)EIO;
+ break;
+ }
+ result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
+ } while ((irqstatus == (bool)false) && (result == (u32)0));
+
+ return result;
+}
+
+static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay)
+{
+ u32 result = 0U;
+ u32 timeout = 0U;
+ bool irqstatus = false;
+
+ do {
+ if (++timeout == delay) {
+ result = (u32)EIO;
+ break;
+ }
+ result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
+ } while ((irqstatus == (bool)false) && (result == (u32)0));
+
+ return result;
+}
+
+static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd)
+{
+ u32 result = 0U;
+
+ result = lpddr4_pollphyindepirq(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT, LPDDR4_CUSTOM_TIMEOUT_DELAY);
+
+ if (result == (u32)0)
+ result = lpddr4_ackphyindepinterrupt(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT);
+ if (result == (u32)0)
+ result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MC_INIT_DONE, LPDDR4_CUSTOM_TIMEOUT_DELAY);
+ if (result == (u32)0)
+ result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MC_INIT_DONE);
+ return result;
+}
+
+static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd)
+{
+ u32 result = 0U;
+ u32 regval = 0U;
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ lpddr4_infotype infotype;
+
+ regval = CPS_FLD_SET(LPDDR4__PI_START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
+ CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);
+
+ regval = CPS_FLD_SET(LPDDR4__START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);
+
+ if (pd->infohandler != (lpddr4_infocallback)NULL) {
+ infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
+ pd->infohandler(pd, infotype);
+ }
+
+ result = lpddr4_pollandackirq(pd);
+
+ return result;
+}
+
+volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset)
+{
+ volatile u32 *local_addr = addr;
+ volatile u32 *regaddr = &local_addr[regoffset];
+
+ return regaddr;
+}
+
+u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize)
+{
+ u32 result;
+
+ result = (u32)(lpddr4_probesf(config, configsize));
+ if (result == (u32)0)
+ *configsize = (u16)(sizeof(lpddr4_privatedata));
+ return result;
+}
+
+u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg)
+{
+ u32 result = 0U;
+
+ result = lpddr4_initsf(pd, cfg);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)cfg->ctlbase;
+ pd->ctlbase = ctlregbase;
+ pd->infohandler = (lpddr4_infocallback)cfg->infohandler;
+ pd->ctlinterrupthandler = (lpddr4_ctlcallback)cfg->ctlinterrupthandler;
+ pd->phyindepinterrupthandler = (lpddr4_phyindepcallback)cfg->phyindepinterrupthandler;
+ }
+ return result;
+}
+
+u32 lpddr4_start(const lpddr4_privatedata *pd)
+{
+ u32 result = 0U;
+
+ result = lpddr4_startsf(pd);
+ if (result == (u32)0) {
+ result = lpddr4_enablepiinitiator(pd);
+ result = lpddr4_startsequencecontroller(pd);
+ }
+ return result;
+}
+
+u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue)
+{
+ u32 result = 0U;
+
+ result = lpddr4_readregsf(pd, cpp, regvalue);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ if (cpp == LPDDR4_CTL_REGS) {
+ if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
+ result = (u32)EINVAL;
+ else
+ *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset));
+ } else if (cpp == LPDDR4_PHY_REGS) {
+ if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
+ result = (u32)EINVAL;
+ else
+ *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset));
+
+ } else {
+ if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
+ result = (u32)EINVAL;
+ else
+ *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset));
+ }
+ }
+ return result;
+}
+
+#ifdef REG_WRITE_VERIF
+
+static u32 lpddr4_getphyrwmask(u32 regoffset)
+{
+ u32 rwmask = 0U;
+ u32 arrayoffset = 0U;
+ u32 slicenum, sliceoffset = 0U;
+
+ for (slicenum = (u32)0U; slicenum <= (DSLICE_NUM + ASLICE_NUM); slicenum++) {
+ sliceoffset = sliceoffset + (u32)SLICE_WIDTH;
+ if (regoffset < sliceoffset)
+ break;
+ }
+ arrayoffset = regoffset - (sliceoffset - (u32)SLICE_WIDTH);
+
+ if (slicenum < DSLICE_NUM) {
+ rwmask = lpddr4_getdslicemask(slicenum, arrayoffset);
+ } else {
+ if (slicenum == DSLICE_NUM) {
+ if (arrayoffset < ASLICE0_REG_COUNT)
+ rwmask = g_lpddr4_address_slice_0_rw_mask[arrayoffset];
+ } else {
+ if (arrayoffset < PHY_CORE_REG_COUNT)
+ rwmask = g_lpddr4_phy_core_rw_mask[arrayoffset];
+ }
+ }
+ return rwmask;
+}
+
+static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
+{
+ u32 result = (u32)0;
+ u32 regreadval = 0U;
+ u32 rwmask = 0U;
+
+ result = lpddr4_readreg(pd, cpp, regoffset, ®readval);
+
+ if (result == (u32)0) {
+ switch (cpp) {
+ case LPDDR4_PHY_INDEP_REGS:
+ rwmask = g_lpddr4_pi_rw_mask[regoffset];
+ break;
+ case LPDDR4_PHY_REGS:
+ rwmask = lpddr4_getphyrwmask(regoffset);
+ break;
+ default:
+ rwmask = g_lpddr4_ddr_controller_rw_mask[regoffset];
+ break;
+ }
+
+ if ((rwmask & regreadval) != (regvalue & rwmask))
+ result = EIO;
+ }
+ return result;
+}
+#endif
+
+u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
+{
+ u32 result = 0U;
+
+ result = lpddr4_writeregsf(pd, cpp);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ if (cpp == LPDDR4_CTL_REGS) {
+ if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
+ result = (u32)EINVAL;
+ else
+ CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset), regvalue);
+ } else if (cpp == LPDDR4_PHY_REGS) {
+ if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
+ result = (u32)EINVAL;
+ else
+ CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset), regvalue);
+ } else {
+ if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
+ result = (u32)EINVAL;
+ else
+ CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue);
+ }
+ }
+#ifdef REG_WRITE_VERIF
+ if (result == (u32)0)
+ result = lpddr4_verifyregwrite(pd, cpp, regoffset, regvalue);
+
+#endif
+
+ return result;
+}
+
+u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus)
+{
+ u32 result = 0U;
+ u32 tdelay = 1000U;
+ u32 regval = 0U;
+
+ result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__READ_MODEREG__REG)), readmoderegval);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval);
+
+ result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_READ_DONE, tdelay);
+ }
+ if (result == (u32)0)
+ result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus);
+ return result;
+}
+
+static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval)
+{
+ u32 result = (u32)0;
+ u32 tdelay = 1000U;
+ u32 regval = 0U;
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG)), writemoderegval);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval);
+
+ result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_WRITE_DONE, tdelay);
+
+ return result;
+}
+
+u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus)
+{
+ u32 result = 0U;
+
+ result = lpddr4_setmmrregistersf(pd, mrwstatus);
+ if (result == (u32)0) {
+ result = lpddr4_writemmrregister(pd, writemoderegval);
+
+ if (result == (u32)0)
+ result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_WRITE_DONE);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ *mrwstatus = (u8)CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRW_STATUS__REG)));
+ if ((*mrwstatus) != 0U)
+ result = (u32)EIO;
+ }
+ }
+
+#ifdef ASILC
+#endif
+
+ return result;
+}
+
+u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+ u32 result;
+ u32 aindex;
+
+ result = lpddr4_writectlconfigsf(pd);
+ if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+ result = EINVAL;
+
+ if (result == (u32)0) {
+ for (aindex = 0; aindex < regcount; aindex++)
+ result = (u32)lpddr4_writereg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
+ (u32)regvalues[aindex]);
+ }
+ return result;
+}
+
+u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+ u32 result;
+ u32 aindex;
+
+ result = lpddr4_writephyindepconfigsf(pd);
+ if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+ result = EINVAL;
+ if (result == (u32)0) {
+ for (aindex = 0; aindex < regcount; aindex++)
+ result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
+ (u32)regvalues[aindex]);
+ }
+ return result;
+}
+
+u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+ u32 result;
+ u32 aindex;
+
+ result = lpddr4_writephyconfigsf(pd);
+ if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+ result = EINVAL;
+ if (result == (u32)0) {
+ for (aindex = 0; aindex < regcount; aindex++)
+ result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
+ (u32)regvalues[aindex]);
+ }
+ return result;
+}
+
+u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+ u32 result;
+ u32 aindex;
+
+ result = lpddr4_readctlconfigsf(pd);
+ if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+ result = EINVAL;
+ if (result == (u32)0) {
+ for (aindex = 0; aindex < regcount; aindex++)
+ result = (u32)lpddr4_readreg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
+ (u32 *)(®values[aindex]));
+ }
+ return result;
+}
+
+u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+ u32 result;
+ u32 aindex;
+
+ result = lpddr4_readphyindepconfigsf(pd);
+ if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+ result = EINVAL;
+ if (result == (u32)0) {
+ for (aindex = 0; aindex < regcount; aindex++)
+ result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
+ (u32 *)(®values[aindex]));
+ }
+ return result;
+}
+
+u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
+{
+ u32 result;
+ u32 aindex;
+
+ result = lpddr4_readphyconfigsf(pd);
+ if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
+ result = EINVAL;
+ if (result == (u32)0) {
+ for (aindex = 0; aindex < regcount; aindex++)
+ result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
+ (u32 *)(®values[aindex]));
+ }
+ return result;
+}
+
+u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask)
+{
+ u32 result;
+
+ result = lpddr4_getphyindepinterruptmsf(pd, mask);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ *mask = CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)));
+ }
+ return result;
+}
+
+u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask)
+{
+ u32 result;
+ u32 regval = 0;
+ const u32 ui32irqcount = (u32)LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
+
+ result = lpddr4_setphyindepinterruptmsf(pd, mask);
+ if ((result == (u32)0) && (ui32irqcount < WORD_SHIFT)) {
+ if (*mask >= (1U << ui32irqcount))
+ result = (u32)EINVAL;
+ }
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)), *mask);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval);
+ }
+ return result;
+}
+
+u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus)
+{
+ u32 result = 0;
+ u32 phyindepirqstatus = 0;
+
+ result = LPDDR4_INTR_CheckPhyIndepIntSF(pd, intr, irqstatus);
+ if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ phyindepirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
+ *irqstatus = (bool)(((phyindepirqstatus >> (u32)intr) & LPDDR4_BIT_MASK) > 0U);
+ }
+ return result;
+}
+
+u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr)
+{
+ u32 result = 0U;
+ u32 regval = 0U;
+
+ result = LPDDR4_INTR_AckPhyIndepIntSF(pd, intr);
+ if ((result == (u32)0) && ((u32)intr < WORD_SHIFT)) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = ((u32)LPDDR4_BIT_MASK << (u32)intr);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
+ }
+
+ return result;
+}
+
+static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+ u32 regval;
+ u32 errbitmask = 0U;
+ u32 snum;
+ volatile u32 *regaddress;
+
+ regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
+ errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK);
+ for (snum = 0U; snum < ASLICE_NUM; snum++) {
+ regval = CPS_REG_READ(regaddress);
+ if ((regval & errbitmask) != CA_TRAIN_RL) {
+ debuginfo->catraingerror = CDN_TRUE;
+ *errfoundptr = true;
+ }
+ regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+ }
+}
+
+static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+ u32 regval;
+ u32 errbitmask = 0U;
+ u32 snum;
+ volatile u32 *regaddress;
+
+ regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
+ errbitmask = GATE_LVL_ERROR_FIELDS;
+ for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+ regval = CPS_REG_READ(regaddress);
+ if ((regval & errbitmask) != 0U) {
+ debuginfo->gatelvlerror = CDN_TRUE;
+ *errfoundptr = true;
+ }
+ regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+ }
+}
+
+static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+ u32 regval;
+ u32 errbitmask = 0U;
+ u32 snum;
+ volatile u32 *regaddress;
+
+ regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
+ errbitmask = READ_LVL_ERROR_FIELDS;
+ for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+ regval = CPS_REG_READ(regaddress);
+ if ((regval & errbitmask) != 0U) {
+ debuginfo->readlvlerror = CDN_TRUE;
+ *errfoundptr = true;
+ }
+ regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+ }
+}
+
+static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+ u32 regval;
+ u32 errbitmask = 0U;
+ u32 snum;
+ volatile u32 *regaddress;
+
+ regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
+ errbitmask = DQ_LVL_STATUS;
+ for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+ regval = CPS_REG_READ(regaddress);
+ if ((regval & errbitmask) != 0U) {
+ debuginfo->dqtrainingerror = CDN_TRUE;
+ *errfoundptr = true;
+ }
+ regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+ }
+}
+
+bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound)
+{
+ bool localerrfound = errfound;
+
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ if (localerrfound == (bool)false)
+ lpddr4_checkcatrainingerror(ctlregbase, debuginfo, &localerrfound);
+
+ if (localerrfound == (bool)false)
+ lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound);
+
+ if (localerrfound == (bool)false)
+ lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound);
+
+ if (localerrfound == (bool)false)
+ lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound);
+
+ if (localerrfound == (bool)false)
+ lpddr4_checkdqtrainingerror(ctlregbase, debuginfo, &localerrfound);
+ return localerrfound;
+}
+
+static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits)
+{
+ u32 regval = 0U;
+
+ regval = CPS_REG_READ(reg);
+ if ((regval & errbitmask) != errorinfobits)
+ *errfoundptr = CDN_TRUE;
+ return *errfoundptr;
+}
+
+void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr)
+{
+ u32 errbitmask = (LPDDR4_BIT_MASK << 0x1U) | (LPDDR4_BIT_MASK);
+
+ debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
+ errbitmask, errfoundptr, PLL_READY);
+ if (*errfoundptr == CDN_FALSE)
+ debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
+ errbitmask, errfoundptr, PLL_READY);
+
+ if (*errfoundptr == CDN_FALSE)
+ debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
+ IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
+ if (*errfoundptr == CDN_FALSE)
+ debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
+ IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
+ if (*errfoundptr == CDN_FALSE)
+ debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
+ IO_CALIB_FIELD, errfoundptr, IO_CALIB_STATE);
+}
+
+static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
+{
+ u32 snum = 0U;
+ volatile u32 *regaddress;
+ u32 regval = 0U;
+
+ if (errorfound == (bool)false) {
+ regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
+ for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+ regval = CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
+ CPS_REG_WRITE(regaddress, regval);
+ regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+ }
+ }
+}
+
+static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
+{
+ u32 snum = 0U;
+ volatile u32 *regaddress;
+ u32 regval = 0U;
+
+ if (errorfound == (bool)false) {
+ regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
+ for (snum = (u32)0U; snum < ASLICE_NUM; snum++) {
+ regval = CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
+ CPS_REG_WRITE(regaddress, regval);
+ regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+ }
+ }
+}
+
+void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
+{
+ lpddr4_setphysnapsettings(ctlregbase, errorfound);
+ lpddr4_setphyadrsnapsettings(ctlregbase, errorfound);
+}
+
+static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+ if (*fspnum == LPDDR4_FSP_0)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)));
+ else if (*fspnum == LPDDR4_FSP_1)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)));
+ else
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)));
+}
+
+static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+ if (*fspnum == LPDDR4_FSP_0)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
+ else if (*fspnum == LPDDR4_FSP_1)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
+ else
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
+}
+
+static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+ if (*fspnum == LPDDR4_FSP_0)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
+ else if (*fspnum == LPDDR4_FSP_1)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
+ else
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
+}
+
+static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+ if (*fspnum == LPDDR4_FSP_0)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
+ else if (*fspnum == LPDDR4_FSP_1)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
+ else
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
+}
+
+static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+ if (*fspnum == LPDDR4_FSP_0)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
+ else if (*fspnum == LPDDR4_FSP_1)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
+ else
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
+}
+
+static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+ if (*fspnum == LPDDR4_FSP_0)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
+ else if (*fspnum == LPDDR4_FSP_1)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
+ else
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
+}
+
+static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
+{
+ if (*fspnum == LPDDR4_FSP_0)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
+ else if (*fspnum == LPDDR4_FSP_1)
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
+ else
+ *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
+
+}
+
+static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
+{
+ if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
+ readpdwakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
+ readsrshortwakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
+ readsrlongwakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
+ readsrlonggatewakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
+ readsrdpshortwakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
+ readsrdplongwakeup(fspnum, ctlregbase, cycles);
+ else
+ readsrdplonggatewakeup(fspnum, ctlregbase, cycles);
+}
+
+u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
+{
+ u32 result = 0U;
+
+ result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
+ }
+ return result;
+}
+
+static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+ u32 regval = 0U;
+
+ if (*fspnum == LPDDR4_FSP_0) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG), regval);
+ } else if (*fspnum == LPDDR4_FSP_1) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG), regval);
+ } else {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG), regval);
+ }
+}
+
+static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+ u32 regval = 0U;
+
+ if (*fspnum == LPDDR4_FSP_0) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG), regval);
+ } else if (*fspnum == LPDDR4_FSP_1) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG), regval);
+ } else {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG), regval);
+ }
+}
+
+static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+ u32 regval = 0U;
+
+ if (*fspnum == LPDDR4_FSP_0) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG), regval);
+ } else if (*fspnum == LPDDR4_FSP_1) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG), regval);
+ } else {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG), regval);
+ }
+}
+
+static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+ u32 regval = 0U;
+
+ if (*fspnum == LPDDR4_FSP_0) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
+ } else if (*fspnum == LPDDR4_FSP_1) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
+ } else {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
+ }
+}
+
+static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+ u32 regval = 0U;
+
+ if (*fspnum == LPDDR4_FSP_0) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
+ } else if (*fspnum == LPDDR4_FSP_1) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
+ } else {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
+ }
+}
+
+static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+ u32 regval = 0U;
+
+ if (*fspnum == LPDDR4_FSP_0) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
+ } else if (*fspnum == LPDDR4_FSP_1) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
+ } else {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
+ }
+}
+static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
+{
+ u32 regval = 0U;
+
+ if (*fspnum == LPDDR4_FSP_0) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
+ } else if (*fspnum == LPDDR4_FSP_1) {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
+ } else {
+ regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
+ }
+}
+
+static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
+{
+ if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
+ writepdwakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
+ writesrshortwakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
+ writesrlongwakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
+ writesrlonggatewakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
+ writesrdpshortwakeup(fspnum, ctlregbase, cycles);
+ else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
+ writesrdplongwakeup(fspnum, ctlregbase, cycles);
+ else
+ writesrdplonggatewakeup(fspnum, ctlregbase, cycles);
+}
+
+u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
+{
+ u32 result = 0U;
+
+ result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
+ if (result == (u32)0) {
+ if (*cycles > NIBBLE_MASK)
+ result = (u32)EINVAL;
+ }
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
+ }
+ return result;
+}
+
+u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off)
+{
+ u32 result = 0U;
+
+ result = lpddr4_getdbireadmodesf(pd, on_off);
+
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ if (CPS_FLD_READ(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) == 0U)
+ *on_off = false;
+ else
+ *on_off = true;
+ }
+ return result;
+}
+
+u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off)
+{
+ u32 result = 0U;
+
+ result = lpddr4_getdbireadmodesf(pd, on_off);
+
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ if (CPS_FLD_READ(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) == 0U)
+ *on_off = false;
+ else
+ *on_off = true;
+ }
+ return result;
+}
+
+u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
+{
+ u32 result = 0U;
+ u32 regval = 0U;
+
+ result = lpddr4_setdbimodesf(pd, mode);
+
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ if (*mode == LPDDR4_DBI_RD_ON)
+ regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 1U);
+ else if (*mode == LPDDR4_DBI_RD_OFF)
+ regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 0U);
+ else if (*mode == LPDDR4_DBI_WR_ON)
+ regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 1U);
+ else
+ regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 0U);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval);
+ }
+ return result;
+}
+
+u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max)
+{
+ u32 result = 0U;
+
+ result = lpddr4_getrefreshratesf(pd, fspnum, tref, tras_max);
+
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ switch (*fspnum) {
+ case LPDDR4_FSP_2:
+ *tref = CPS_FLD_READ(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)));
+ *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)));
+ break;
+ case LPDDR4_FSP_1:
+ *tref = CPS_FLD_READ(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)));
+ *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)));
+ break;
+ default:
+ *tref = CPS_FLD_READ(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)));
+ *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)));
+ break;
+ }
+ }
+ return result;
+}
+
+static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
+{
+ u32 regval = 0U;
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)), *tref);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG), regval);
+ regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)), *tras_max);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG), regval);
+}
+
+static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
+{
+ u32 regval = 0U;
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)), *tref);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG), regval);
+ regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)), *tras_max);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG), regval);;
+}
+
+static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
+{
+ u32 regval = 0U;
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)), *tref);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG), regval);
+ regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)), *tras_max);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG), regval);
+}
+
+u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
+{
+ u32 result = 0U;
+
+ result = lpddr4_setrefreshratesf(pd, fspnum, tref, tras_max);
+
+ if (result == (u32)0) {
+ switch (*fspnum) {
+ case LPDDR4_FSP_2:
+ lpddr4_updatefsp2refrateparams(pd, tref, tras_max);
+ break;
+ case LPDDR4_FSP_1:
+ lpddr4_updatefsp1refrateparams(pd, tref, tras_max);
+ break;
+ default:
+ lpddr4_updatefsp0refrateparams(pd, tref, tras_max);
+ break;
+ }
+ }
+ return result;
+}
+
+u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval)
+{
+ u32 result = 0U;
+ u32 regval = 0U;
+
+ result = lpddr4_refreshperchipselectsf(pd);
+
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ regval = CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG)), trefinterval);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG), regval);
+ }
+ return result;
+}
diff --git a/drivers/ram/k3-ddrss/lpddr4.h b/drivers/ram/k3-ddrss/lpddr4.h
new file mode 100644
index 0000000..5b77ea9
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_H
+#define LPDDR4_H
+
+#include "lpddr4_ctl_regs.h"
+#include "lpddr4_sanity.h"
+#ifdef CONFIG_K3_AM64_DDRSS
+#include "lpddr4_16bit.h"
+#include "lpddr4_16bit_sanity.h"
+#else
+#include "lpddr4_32bit.h"
+#include "lpddr4_32bit_sanity.h"
+#endif
+
+#ifdef REG_WRITE_VERIF
+#include "lpddr4_ctl_regs_rw_masks.h"
+#endif
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PRODUCT_ID (0x1046U)
+
+#define LPDDR4_BIT_MASK (0x1U)
+#define BYTE_MASK (0xffU)
+#define NIBBLE_MASK (0xfU)
+
+#define WORD_SHIFT (32U)
+#define WORD_MASK (0xffffffffU)
+#define SLICE_WIDTH (0x100)
+
+#define CTL_OFFSET 0
+#define PI_OFFSET (((u32)1) << 11)
+#define PHY_OFFSET (((u32)1) << 12)
+
+#define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT)
+
+#define PLL_READY (0x3U)
+#define IO_CALIB_DONE ((u32)0x1U << 23U)
+#define IO_CALIB_FIELD ((u32)NIBBLE_MASK << 28U)
+#define IO_CALIB_STATE ((u32)0xBU << 28U)
+#define RX_CAL_DONE ((u32)LPDDR4_BIT_MASK << 4U)
+#define CA_TRAIN_RL (((u32)LPDDR4_BIT_MASK << 5U) | ((u32)LPDDR4_BIT_MASK << 4U))
+#define WR_LVL_STATE (((u32)NIBBLE_MASK) << 13U)
+#define GATE_LVL_ERROR_FIELDS (((u32)LPDDR4_BIT_MASK << 7U) | ((u32)LPDDR4_BIT_MASK << 6U))
+#define READ_LVL_ERROR_FIELDS ((((u32)NIBBLE_MASK) << 28U) | (((u32)BYTE_MASK) << 16U))
+#define DQ_LVL_STATUS (((u32)LPDDR4_BIT_MASK << 26U) | (((u32)BYTE_MASK) << 18U))
+
+#define CDN_TRUE 1U
+#define CDN_FALSE 0U
+
+void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
+volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset);
+u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay);
+bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound);
+void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr);
+
+u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd);
+void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
+u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus);
+u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPDDR4_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.c b/drivers/ram/k3-ddrss/lpddr4_16bit.c
new file mode 100644
index 0000000..b749b74
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_16bit.c
@@ -0,0 +1,396 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <errno.h>
+
+#include "cps_drv_lpddr4.h"
+#include "lpddr4_ctl_regs.h"
+#include "lpddr4_if.h"
+#include "lpddr4.h"
+#include "lpddr4_structs_if.h"
+
+static u32 ctlintmap[51][3] = {
+ { 0, 0, 7 },
+ { 1, 0, 8 },
+ { 2, 0, 9 },
+ { 3, 0, 14 },
+ { 4, 0, 15 },
+ { 5, 0, 16 },
+ { 6, 0, 17 },
+ { 7, 0, 19 },
+ { 8, 1, 0 },
+ { 9, 2, 0 },
+ { 10, 2, 3 },
+ { 11, 3, 0 },
+ { 12, 4, 0 },
+ { 13, 5, 11 },
+ { 14, 5, 12 },
+ { 15, 5, 13 },
+ { 16, 5, 14 },
+ { 17, 5, 15 },
+ { 18, 6, 0 },
+ { 19, 6, 1 },
+ { 20, 6, 2 },
+ { 21, 6, 6 },
+ { 22, 6, 7 },
+ { 23, 7, 3 },
+ { 24, 7, 4 },
+ { 25, 7, 5 },
+ { 26, 7, 6 },
+ { 27, 7, 7 },
+ { 28, 8, 0 },
+ { 29, 9, 0 },
+ { 30, 10, 0 },
+ { 31, 10, 1 },
+ { 32, 10, 2 },
+ { 33, 10, 3 },
+ { 34, 10, 4 },
+ { 35, 10, 5 },
+ { 36, 11, 0 },
+ { 37, 12, 0 },
+ { 38, 12, 1 },
+ { 39, 12, 2 },
+ { 40, 12, 3 },
+ { 41, 12, 4 },
+ { 42, 12, 5 },
+ { 43, 13, 0 },
+ { 44, 13, 1 },
+ { 45, 13, 3 },
+ { 46, 14, 0 },
+ { 47, 14, 2 },
+ { 48, 14, 3 },
+ { 49, 15, 2 },
+ { 50, 16, 0 },
+};
+
+static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
+static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
+static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr, u32 *ctlgrpirqstatus, u32 *ctlmasterintflag);
+static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
+static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
+static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr);
+
+u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
+{
+ u32 result = 0U;
+ u32 regval = 0U;
+
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)));
+ CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_NORMAL_LVL_SEQ__REG)), regval);
+ regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
+ CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
+ return result;
+}
+
+u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
+{
+ u32 result = 0U;
+
+ result = lpddr4_getctlinterruptmasksf(pd, mask);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ *mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG))));
+ }
+ return result;
+}
+
+u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
+{
+ u32 result;
+ u32 regval = 0;
+ const u64 ui64one = 1ULL;
+ const u32 ui32irqcount = (u32)32U;
+
+ result = lpddr4_setctlinterruptmasksf(pd, mask);
+ if ((result == (u32)0) && (ui32irqcount < 64U)) {
+ if (*mask >= (ui64one << ui32irqcount))
+ result = (u32)EINVAL;
+ }
+
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_MASTER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG)), *mask);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_MASTER__REG), regval);
+ }
+ return result;
+}
+
+static void lpddr4_checkctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
+ u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
+{
+ if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE))
+ *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_INIT__REG)));
+ else if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE))
+ *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MODE__REG));
+ else if (intr == LPDDR4_INTR_BIST_DONE)
+ *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_BIST__REG)));
+ else if (intr == LPDDR4_INTR_PARITY_ERROR)
+ *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_PARITY__REG)));
+ else
+ *ctlmasterintflag = (u32)1U;
+}
+
+static void lpddr4_checkctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
+ u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
+{
+ if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE))
+ *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_FREQ__REG)));
+ else if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT))
+ *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_LOWPOWER__REG)));
+ else
+ lpddr4_checkctlinterrupt_4(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
+}
+
+static void lpddr4_checkctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr,
+ u32 *ctlgrpirqstatus, u32 *ctlmasterintflag)
+{
+ if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
+ *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TIMEOUT__REG));
+ else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
+ *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_TRAINING__REG));
+ else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
+ *ctlgrpirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_USERIF__REG));
+ else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
+ *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_MISC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MISC__REG)));
+ else if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT))
+ *ctlgrpirqstatus = CPS_FLD_READ(LPDDR4__INT_STATUS_DFI__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_DFI__REG)));
+ else
+ lpddr4_checkctlinterrupt_3(ctlregbase, intr, ctlgrpirqstatus, ctlmasterintflag);
+}
+
+u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
+{
+ u32 result;
+ u32 ctlmasterirqstatus = 0U;
+ u32 ctlgrpirqstatus = 0U;
+ u32 ctlmasterintflag = 0U;
+
+ result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ ctlmasterirqstatus = (CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_MASTER__REG)) & (~((u32)1 << 31)));
+
+ lpddr4_checkctlinterrupt_2(ctlregbase, intr, &ctlgrpirqstatus, &ctlmasterintflag);
+
+ if ((ctlintmap[intr][INT_SHIFT] < WORD_SHIFT) && (ctlintmap[intr][GRP_SHIFT] < WORD_SHIFT)) {
+ if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
+ (((ctlgrpirqstatus >> ctlintmap[intr][INT_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
+ (ctlmasterintflag == (u32)0))
+ *irqstatus = true;
+ else if ((((ctlmasterirqstatus >> ctlintmap[intr][GRP_SHIFT]) & LPDDR4_BIT_MASK) > 0U) &&
+ (ctlmasterintflag == (u32)1U))
+ *irqstatus = true;
+ else
+ *irqstatus = false;
+ }
+ }
+ return result;
+}
+
+static void lpddr4_ackctlinterrupt_4(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
+{
+ u32 regval = 0;
+
+ if ((intr >= LPDDR4_INTR_MRR_ERROR) && (intr <= LPDDR4_INTR_MR_WRITE_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MODE__REG), (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
+ } else if ((intr == LPDDR4_INTR_BIST_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+ regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_BIST__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG)),
+ (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_BIST__REG), regval);
+ } else if ((intr == LPDDR4_INTR_PARITY_ERROR) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+ regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_PARITY__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG)),
+ (u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_PARITY__REG), regval);
+ } else {
+ }
+}
+
+static void lpddr4_ackctlinterrupt_3(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
+{
+ u32 regval = 0;
+
+ if ((intr >= LPDDR4_INTR_LP_DONE) && (intr <= LPDDR4_INTR_LP_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+ regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_LOWPOWER__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG)),
+ (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_LOWPOWER__REG), regval);
+ } else if ((intr >= LPDDR4_INTR_INIT_MEM_RESET_DONE) && (intr <= LPDDR4_INTR_INIT_POWER_ON_STATE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+ regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_INIT__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG)),
+ (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_INIT__REG), regval);
+ } else {
+ lpddr4_ackctlinterrupt_4(ctlregbase, intr);
+ }
+}
+
+static void lpddr4_ackctlinterrupt_2(lpddr4_ctlregs *ctlregbase, lpddr4_intr_ctlinterrupt intr)
+{
+ u32 regval = 0;
+
+ if ((intr >= LPDDR4_INTR_DFI_UPDATE_ERROR) && (intr <= LPDDR4_INTR_DFI_TIMEOUT) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_DFI__REG), (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+ } else if ((intr >= LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) && (intr <= LPDDR4_INTR_FREQ_DFS_SW_DONE) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+ regval = CPS_FLD_WRITE(LPDDR4__INT_ACK_FREQ__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG)),
+ (u32)((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_FREQ__REG), regval);
+ } else {
+ lpddr4_ackctlinterrupt_3(ctlregbase, intr);
+ }
+}
+
+u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
+{
+ u32 result;
+
+ result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
+ if ((result == (u32)0) && ((u32)ctlintmap[intr][INT_SHIFT] < WORD_SHIFT)) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ if (intr <= LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX)
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TIMEOUT__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+ else if ((intr >= LPDDR4_INTR_TRAINING_ZQ_STATUS) && (intr <= LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT))
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_TRAINING__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+ else if ((intr >= LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) && (intr <= LPDDR4_INTR_USERIF_INVAL_SETTING))
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_USERIF__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+ else if ((intr >= LPDDR4_INTR_MISC_MRR_TRAFFIC) && (intr <= LPDDR4_INTR_MISC_REFRESH_STATUS))
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_MISC__REG), ((u32)LPDDR4_BIT_MASK << (u32)ctlintmap[intr][INT_SHIFT]));
+ else
+ lpddr4_ackctlinterrupt_2(ctlregbase, intr);
+ }
+
+ return result;
+}
+
+void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+ u32 regval;
+ u32 errbitmask = 0U;
+ u32 snum;
+ volatile u32 *regaddress;
+
+ regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG));
+ errbitmask = ((u32)LPDDR4_BIT_MASK << (u32)12U);
+ for (snum = 0U; snum < DSLICE_NUM; snum++) {
+ regval = CPS_REG_READ(regaddress);
+ if ((regval & errbitmask) != 0U) {
+ debuginfo->wrlvlerror = CDN_TRUE;
+ *errfoundptr = true;
+ }
+ regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+ }
+}
+
+u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
+{
+ u32 result = 0U;
+ bool errorfound = false;
+
+ result = lpddr4_getdebuginitinfosf(pd, debuginfo);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
+ lpddr4_setsettings(ctlregbase, errorfound);
+ errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
+ }
+
+ if (errorfound == (bool)true)
+ result = (u32)EPROTO;
+
+ return result;
+}
+
+u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
+{
+ u32 result = 0U;
+
+ result = lpddr4_getreducmodesf(pd, mode);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ if (CPS_FLD_READ(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG))) == 0U)
+ *mode = LPDDR4_REDUC_ON;
+ else
+ *mode = LPDDR4_REDUC_OFF;
+ }
+ return result;
+}
+
+u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
+{
+ u32 result = 0U;
+ u32 regval = 0U;
+
+ result = lpddr4_setreducmodesf(pd, mode);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ regval = (u32)CPS_FLD_WRITE(LPDDR4__MEM_DP_REDUCTION__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG)), *mode);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__MEM_DP_REDUCTION__REG), regval);
+ }
+ return result;
+}
+
+u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
+{
+ u32 lowerdata;
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ u32 result = (u32)0;
+
+ if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
+ *mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
+ *mmrvalue = (u64)0;
+ result = (u32)EIO;
+ } else {
+ *mrrstatus = (u8)0;
+ lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA__REG));
+ *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
+ result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
+ }
+ return result;
+}
+
+#ifdef REG_WRITE_VERIF
+
+u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
+{
+ u32 rwmask = 0U;
+
+ switch (dslicenum) {
+ case 0:
+ if (arrayoffset < DSLICE0_REG_COUNT)
+ rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
+ break;
+ default:
+ if (arrayoffset < DSLICE1_REG_COUNT)
+ rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
+ break;
+ }
+ return rwmask;
+}
+#endif
+
+u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
+{
+ u32 result = 0U;
+
+ result = lpddr4_geteccenablesf(pd, eccparam);
+ if (result == (u32)0) {
+ *eccparam = LPDDR4_ECC_DISABLED;
+ result = (u32)EOPNOTSUPP;
+ }
+
+ return result;
+}
+u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
+{
+ u32 result = 0U;
+
+ result = lpddr4_seteccenablesf(pd, eccparam);
+ if (result == (u32)0)
+ result = (u32)EOPNOTSUPP;
+
+ return result;
+}
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit.h b/drivers/ram/k3-ddrss/lpddr4_16bit.h
new file mode 100644
index 0000000..d663389
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_16bit.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_H
+#define LPDDR4_16BIT_H
+
+#define DSLICE_NUM (2U)
+#define ASLICE_NUM (3U)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DSLICE0_REG_COUNT (126U)
+#define DSLICE1_REG_COUNT (126U)
+#define ASLICE0_REG_COUNT (42U)
+#define ASLICE1_REG_COUNT (42U)
+#define ASLICE2_REG_COUNT (42U)
+#define PHY_CORE_REG_COUNT (126U)
+
+#define GRP_SHIFT 1
+#define INT_SHIFT 2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPDDR4_16BIT_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
new file mode 100644
index 0000000..09b0e3c
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
@@ -0,0 +1,1309 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/types.h>
+#include "lpddr4_ctl_regs_rw_masks.h"
+
+u32 g_lpddr4_ddr_controller_rw_mask[] = {
+ 0x00000F01U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x01FFFFFFU,
+ 0x03030300U,
+ 0x01030100U,
+ 0x1F1F013FU,
+ 0x0303031FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0xFFFFFF01U,
+ 0x0001FFFFU,
+ 0x000F7FFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFF00FFFFU,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0F3F7F7FU,
+ 0xFFFFFFFFU,
+ 0x0F3F7F7FU,
+ 0xFFFFFFFFU,
+ 0x0F3F7F7FU,
+ 0xFFFFFFFFU,
+ 0xFF1F1F07U,
+ 0x0001FFFFU,
+ 0x3F3F01FFU,
+ 0x1F01FFFFU,
+ 0x01FFFFFFU,
+ 0x3F3F01FFU,
+ 0x1F01FFFFU,
+ 0x01FFFFFFU,
+ 0x3F3F01FFU,
+ 0xFF01FFFFU,
+ 0x00FFFFFFU,
+ 0x1F0FFFFFU,
+ 0xFFFF3FFFU,
+ 0x0000FFFFU,
+ 0x1F0FFFFFU,
+ 0xFFFF3FFFU,
+ 0x0000FFFFU,
+ 0x1F0FFFFFU,
+ 0x07073FFFU,
+ 0xFFFF0107U,
+ 0xFFFFFFFFU,
+ 0x0101010FU,
+ 0x3FFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0301FFFFU,
+ 0x00010101U,
+ 0x03FFFFFFU,
+ 0x01000000U,
+ 0x03FF3F07U,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x010FFFFFU,
+ 0x0FFFFF01U,
+ 0x001F1F01U,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x1FFFFFFFU,
+ 0x1F0F1F1FU,
+ 0x1F0F1F1FU,
+ 0x1F0F1F1FU,
+ 0x1F011F01U,
+ 0x00FFFF01U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x1F1F07FFU,
+ 0xFF1F1F1FU,
+ 0x1F1F1F07U,
+ 0x07FF1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x07010101U,
+ 0x00017F00U,
+ 0xFFFFFFFFU,
+ 0x0700FFFFU,
+ 0xFFFFFF07U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x000FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x000FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x010FFFFFU,
+ 0x00010100U,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x01FFFFFFU,
+ 0x0000FF00U,
+ 0x0001FFFFU,
+ 0x0F01FFFFU,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF0100U,
+ 0xFFFFFFFFU,
+ 0x0F0F0003U,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x00013F0FU,
+ 0x0FFF0FFFU,
+ 0x0F0F0007U,
+ 0x000FFF07U,
+ 0xFFFF0FFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x01010101U,
+ 0x0101FF01U,
+ 0x00000107U,
+ 0xFFFFFFFFU,
+ 0x00FFFF0FU,
+ 0x00000303U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x07FFFFFFU,
+ 0x01FFFF00U,
+ 0x00000000U,
+ 0x00030100U,
+ 0x03FF03FFU,
+ 0x1F1F03FFU,
+ 0x000FFFFFU,
+ 0x03FF03FFU,
+ 0x1F1F03FFU,
+ 0x000FFFFFU,
+ 0x03FF03FFU,
+ 0x1F1F03FFU,
+ 0x000FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x01FFFF01U,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x01FFFF00U,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x01FFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x01FFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0101FFFFU,
+ 0x00000101U,
+ 0x01010101U,
+ 0x03010101U,
+ 0x3F000003U,
+ 0x00000101U,
+ 0xFFFFFFFFU,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x000FFF00U,
+ 0x1F000000U,
+ 0x1F1F1F1FU,
+ 0xFFFF070FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x000FFF00U,
+ 0x0FFF0FFFU,
+ 0x007F0FFFU,
+ 0x0FFF0FFFU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x037F0FFFU,
+ 0x0FFF0000U,
+ 0x0FFF0FFFU,
+ 0x03030101U,
+ 0x03030303U,
+ 0x0F0F0707U,
+ 0xFFFFFFFFU,
+ 0x00FFFF03U,
+ 0xFFFFFFFFU,
+ 0x03FFFF03U,
+ 0x1F011F01U,
+ 0x0101FFFFU,
+ 0x01010101U,
+ 0x03010101U,
+ 0x0301011FU,
+ 0x07010F03U,
+ 0x03030307U,
+ 0x03011F03U,
+ 0x01010000U,
+ 0x01030303U,
+ 0x00000101U,
+ 0x00010000U,
+ 0x00000000U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0xFF000000U,
+ 0x0FFF0F0FU,
+ 0x0F0FFF0FU,
+ 0x01010101U,
+ 0x033F3F3FU,
+ 0x3F030303U,
+ 0x1F1F3F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x0F1F1F1FU,
+ 0x0F070F07U,
+ 0x07010107U,
+ 0xFF000007U,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x007FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF070FU,
+ 0x00FFFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x007FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF070FU,
+ 0x00FFFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x007FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF070FU,
+ 0xFFFFFFFFU,
+ 0x000300FFU,
+ 0x0F0FFFFFU,
+ 0x0701FF07U,
+ 0x07070707U,
+ 0x0F0F0F07U,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0xFFFFFF0FU,
+ 0x007F7F7FU
+};
+
+u32 g_lpddr4_pi_rw_mask[] = {
+ 0x00000F01U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0xFFFF0301U,
+ 0x030100FFU,
+ 0x00000101U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0000011FU,
+ 0xFFFFFFFFU,
+ 0x01030101U,
+ 0x0F011F03U,
+ 0x0101070FU,
+ 0x000FFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000007U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00010101U,
+ 0x3F3F0103U,
+ 0x0101FFFFU,
+ 0x01030103U,
+ 0x0000FF00U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x030F0F1FU,
+ 0x00000003U,
+ 0x03FFFFFFU,
+ 0x00000F07U,
+ 0x00000103U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0101010FU,
+ 0x01010101U,
+ 0x00030301U,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0x0000FF03U,
+ 0xFFFFFFFFU,
+ 0x00FFFF00U,
+ 0x0F0FFFFFU,
+ 0x01011F1FU,
+ 0x03000000U,
+ 0x030F0101U,
+ 0x01010101U,
+ 0x0000FF03U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF0001U,
+ 0x1F1F3F1FU,
+ 0xFF0F0F01U,
+ 0x017F1FFFU,
+ 0xFF01FFFFU,
+ 0x01010101U,
+ 0x030701FFU,
+ 0x1F1F0301U,
+ 0x01030001U,
+ 0x000000FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0101FFFFU,
+ 0x00030001U,
+ 0xFFFFFFFFU,
+ 0x00010101U,
+ 0x010003FFU,
+ 0x01010101U,
+ 0x1F070303U,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x3FFFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x011F3F00U,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x0101011FU,
+ 0x00FFFF01U,
+ 0x00000107U,
+ 0x000101FFU,
+ 0xFFFFFFFFU,
+ 0x0000FF01U,
+ 0xFFFFFFFFU,
+ 0x0FFF0000U,
+ 0xFFFFFFFFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x03030703U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000003FU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0101010FU,
+ 0x00010101U,
+ 0x01010101U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF0101U,
+ 0x000000FFU,
+ 0x03FFFFFFU,
+ 0x00000100U,
+ 0x0001FFFFU,
+ 0x01000000U,
+ 0x01000003U,
+ 0x00010F07U,
+ 0x0F00010FU,
+ 0x010F0001U,
+ 0x00010F00U,
+ 0x0F00010FU,
+ 0x010F0001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x011F0000U,
+ 0x01010103U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x00FF0101U,
+ 0x000001FFU,
+ 0x0000001FU,
+ 0x01031F01U,
+ 0x01010101U,
+ 0x00FFFF07U,
+ 0xFFFFFFFFU,
+ 0x00FFFFFFU,
+ 0x000000FFU,
+ 0x000000FFU,
+ 0x000FFFFFU,
+ 0x0FFF0FFFU,
+ 0xFF0F3F7FU,
+ 0x0F3F7F7FU,
+ 0x3F7F7FFFU,
+ 0x007FFF0FU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x0F0FFFFFU,
+ 0x03030F0FU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x01FF01FFU,
+ 0x0F0F01FFU,
+ 0x0F0F0F0FU,
+ 0x3F3F3F3FU,
+ 0x03033F3FU,
+ 0x03030303U,
+ 0x03FFFFFFU,
+ 0x03030303U,
+ 0x03030303U,
+ 0xFF030303U,
+ 0xFFFFFFFFU,
+ 0x070707FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x1F030303U,
+ 0x001F3FFFU,
+ 0x001F3FFFU,
+ 0x1F1F3FFFU,
+ 0x03FF03FFU,
+ 0x03FF1F1FU,
+ 0x1F1F03FFU,
+ 0x03FF03FFU,
+ 0x7F7F7F7FU,
+ 0x0F0F7F7FU,
+ 0xFF1F0F0FU,
+ 0xFF1F0F1FU,
+ 0xFF1F0F1FU,
+ 0xFFFFFF1FU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x3FFFFFFFU,
+ 0x003F03FFU,
+ 0x003F03FFU,
+ 0x030303FFU,
+ 0x0003FF03U,
+ 0x7F7F03FFU,
+ 0x1F03030FU,
+ 0x03FFFFFFU,
+ 0x7F7F03FFU,
+ 0x1F03030FU,
+ 0x03FFFFFFU,
+ 0x7F7F03FFU,
+ 0x1F03030FU,
+ 0x0303FFFFU,
+ 0xFFFFFF03U,
+ 0x00FF3F1FU,
+ 0x000FFFFFU,
+ 0x3F0F01FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFF3F1FFFU,
+ 0x000FFFFFU,
+ 0x3F0F01FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFF3F1FFFU,
+ 0x000FFFFFU,
+ 0x3F0F01FFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x3F3FFFFFU,
+ 0x00FFFF3FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x0000FFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x0000FFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x0FFFFFFFU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x030F0F0FU,
+ 0x07070303U,
+ 0x03030303U,
+ 0x7F7F7F7FU,
+ 0x00000303U,
+ 0xFFFF0000U,
+ 0x00FFFFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x01FFFFFFU,
+ 0x1F1F1FFFU,
+ 0x1F1F1F1FU,
+ 0x01FFFF1FU,
+ 0x0301FFFFU,
+ 0x00030303U,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0xFF01FFFFU,
+ 0xFFFFFFFFU
+};
+
+u32 g_lpddr4_data_slice_0_rw_mask[] = {
+ 0x07FF7F07U,
+ 0x0703FF0FU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x1F030F3FU,
+ 0x030F0F1FU,
+ 0x01FF031FU,
+ 0x00000101U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x7F0101FFU,
+ 0x010101FFU,
+ 0x03FF003FU,
+ 0x01FF000FU,
+ 0x01FF0701U,
+ 0x00000003U,
+ 0x00000000U,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0x3F030001U,
+ 0x0F3FFF0FU,
+ 0x1F030F3FU,
+ 0x03FFFFFFU,
+ 0x00073FFFU,
+ 0x0F0F07FFU,
+ 0x000FFFFFU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0x071F07FFU,
+ 0x01010101U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x007F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x1F0703FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x0303FFFFU,
+ 0x1F1F0103U,
+ 0x000F1F1FU,
+ 0xFF3F07FFU,
+ 0x0FFF0FFFU,
+ 0x001F0F3FU,
+ 0x03FF03FFU,
+ 0x01FF0FFFU,
+ 0x00000F01U,
+ 0x000003FFU,
+ 0x7F7F0703U,
+ 0x0000001FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0x003FFFFFU
+};
+
+u32 g_lpddr4_data_slice_1_rw_mask[] = {
+ 0x07FF7F07U,
+ 0x0703FF0FU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x1F030F3FU,
+ 0x030F0F1FU,
+ 0x01FF031FU,
+ 0x00000101U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x7F0101FFU,
+ 0x010101FFU,
+ 0x03FF003FU,
+ 0x01FF000FU,
+ 0x01FF0701U,
+ 0x00000003U,
+ 0x00000000U,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0x3F030001U,
+ 0x0F3FFF0FU,
+ 0x1F030F3FU,
+ 0x03FFFFFFU,
+ 0x00073FFFU,
+ 0x0F0F07FFU,
+ 0x000FFFFFU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0x071F07FFU,
+ 0x01010101U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x007F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x1F0703FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x0303FFFFU,
+ 0x1F1F0103U,
+ 0x000F1F1FU,
+ 0xFF3F07FFU,
+ 0x0FFF0FFFU,
+ 0x001F0F3FU,
+ 0x03FF03FFU,
+ 0x01FF0FFFU,
+ 0x00000F01U,
+ 0x000003FFU,
+ 0x7F7F0703U,
+ 0x0000001FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0x003FFFFFU
+};
+
+u32 g_lpddr4_address_slice_0_rw_mask[] = {
+ 0x000107FFU,
+ 0x00000000U,
+ 0x0F000000U,
+ 0x00000000U,
+ 0x01000707U,
+ 0x011F7F7FU,
+ 0x01000301U,
+ 0x07FFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x00FFFFFFU,
+ 0x03FFFFFFU,
+ 0x01FF0F03U,
+ 0x07000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x3FFFFFFFU,
+ 0x3F3F03FFU,
+ 0x3F0F3F3FU,
+ 0x0000003FU,
+ 0x0707FFFFU,
+ 0x1F07FF1FU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x000F07FFU,
+ 0xFF3F07FFU,
+ 0x0103FFFFU,
+ 0x0000000FU,
+ 0x0000010FU
+};
+
+u32 g_lpddr4_address_slice_1_rw_mask[] = {
+ 0x000107FFU,
+ 0x00000000U,
+ 0x0F000000U,
+ 0x00000000U,
+ 0x01000707U,
+ 0x011F7F7FU,
+ 0x01000301U,
+ 0x07FFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x00FFFFFFU,
+ 0x03FFFFFFU,
+ 0x01FF0F03U,
+ 0x07000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x3FFFFFFFU,
+ 0x3F3F03FFU,
+ 0x3F0F3F3FU,
+ 0x0000003FU,
+ 0x0707FFFFU,
+ 0x1F07FF1FU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x000F07FFU,
+ 0xFF3F07FFU,
+ 0x0103FFFFU,
+ 0x0000000FU,
+ 0x0000010FU
+};
+
+u32 g_lpddr4_address_slice_2_rw_mask[] = {
+ 0x000107FFU,
+ 0x00000000U,
+ 0x0F000000U,
+ 0x00000000U,
+ 0x01000707U,
+ 0x011F7F7FU,
+ 0x01000301U,
+ 0x07FFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x00FFFFFFU,
+ 0x03FFFFFFU,
+ 0x01FF0F03U,
+ 0x07000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x3FFFFFFFU,
+ 0x3F3F03FFU,
+ 0x3F0F3F3FU,
+ 0x0000003FU,
+ 0x0707FFFFU,
+ 0x1F07FF1FU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x000F07FFU,
+ 0xFF3F07FFU,
+ 0x0103FFFFU,
+ 0x0000000FU,
+ 0x0000010FU
+};
+
+u32 g_lpddr4_phy_core_rw_mask[] = {
+ 0x00000003U,
+ 0x1F030101U,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x001F1F1FU,
+ 0x011F07FFU,
+ 0x07FF0100U,
+ 0x000107FFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0101FF01U,
+ 0x0007FF03U,
+ 0x070F07FFU,
+ 0x01010300U,
+ 0x0F010001U,
+ 0x010F0F0FU,
+ 0x0F0F0F0FU,
+ 0x00010101U,
+ 0x010FFFFFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x0000FFFFU,
+ 0x00000001U,
+ 0x0F0F0F0FU,
+ 0x03030303U,
+ 0x03030303U,
+ 0x03030303U,
+ 0x03030303U,
+ 0xFFFF1FFFU,
+ 0x0000FF01U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0FFF0FFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0FFF0FFFU,
+ 0xFF0F0101U,
+ 0x0003FF01U,
+ 0x0101FFFFU,
+ 0x0003FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x1FFF03FFU,
+ 0x00001FFFU,
+ 0xFFFFFFFFU,
+ 0x000007FFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7F000000U,
+ 0x01FFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0FFFFFFFU,
+ 0x000FFFFFU,
+ 0x01FFFFFFU,
+ 0x3F7FFFFFU,
+ 0x3F3F1F3FU,
+ 0x1F3F3F1FU,
+ 0x001F3F3FU,
+ 0x0000FFFFU,
+ 0x01FF0F03U,
+ 0x00000F7FU,
+ 0x00000000U,
+ 0x003F0101U,
+ 0x01010000U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x03071FFFU,
+ 0x00030303U,
+ 0xFFFFFFFFU,
+ 0x03FFFFFFU,
+ 0x00FF073FU,
+ 0x0707FFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000003U,
+ 0x0F1F0101U,
+ 0x00000000U,
+ 0x0003FFFFU,
+ 0x0007FFFFU,
+ 0x00000001U,
+ 0x00011FFFU,
+ 0x0F0F0FFFU,
+ 0x010103FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x000007FFU,
+ 0x000007FFU,
+ 0x000007FFU,
+ 0x3FFFFFFFU,
+ 0x0003FFFFU,
+ 0x7FFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0007FFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x7FFFFF07U
+};
diff --git a/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h
new file mode 100644
index 0000000..fde05ce
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h
@@ -0,0 +1,257 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_SANITY_H
+#define LPDDR4_16BIT_SANITY_H
+
+#include <errno.h>
+#include <linux/types.h>
+#include <lpddr4_if.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
+static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
+static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
+static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
+
+#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1
+#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2
+#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3
+#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4
+
+static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus)
+{
+ u32 ret = 0;
+
+ if (pd == NULL) {
+ ret = EINVAL;
+ } else if (irqstatus == NULL) {
+ ret = EINVAL;
+ } else if (
+ (intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) &&
+ (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) &&
+ (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) &&
+ (intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) &&
+ (intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) &&
+ (intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) &&
+ (intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) &&
+ (intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) &&
+ (intr != LPDDR4_INTR_ECC_ERROR) &&
+ (intr != LPDDR4_INTR_LP_DONE) &&
+ (intr != LPDDR4_INTR_LP_TIMEOUT) &&
+ (intr != LPDDR4_INTR_PORT_TIMEOUT) &&
+ (intr != LPDDR4_INTR_RFIFO_TIMEOUT) &&
+ (intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) &&
+ (intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) &&
+ (intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) &&
+ (intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) &&
+ (intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) &&
+ (intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) &&
+ (intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) &&
+ (intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) &&
+ (intr != LPDDR4_INTR_USERIF_WRAP) &&
+ (intr != LPDDR4_INTR_USERIF_INVAL_SETTING) &&
+ (intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) &&
+ (intr != LPDDR4_INTR_MISC_SW_REQ_MODE) &&
+ (intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) &&
+ (intr != LPDDR4_INTR_MISC_TEMP_ALERT) &&
+ (intr != LPDDR4_INTR_MISC_REFRESH_STATUS) &&
+ (intr != LPDDR4_INTR_BIST_DONE) &&
+ (intr != LPDDR4_INTR_CRC) &&
+ (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
+ (intr != LPDDR4_INTR_DFI_PHY_ERROR) &&
+ (intr != LPDDR4_INTR_DFI_BUS_ERROR) &&
+ (intr != LPDDR4_INTR_DFI_STATE_CHANGE) &&
+ (intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) &&
+ (intr != LPDDR4_INTR_DFI_TIMEOUT) &&
+ (intr != LPDDR4_INTR_DIMM) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) &&
+ (intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) &&
+ (intr != LPDDR4_INTR_MC_INIT_DONE) &&
+ (intr != LPDDR4_INTR_INIT_POWER_ON_STATE) &&
+ (intr != LPDDR4_INTR_MRR_ERROR) &&
+ (intr != LPDDR4_INTR_MR_READ_DONE) &&
+ (intr != LPDDR4_INTR_MR_WRITE_DONE) &&
+ (intr != LPDDR4_INTR_PARITY_ERROR) &&
+ (intr != LPDDR4_INTR_LOR_BITS)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr)
+{
+ u32 ret = 0;
+
+ if (pd == NULL) {
+ ret = EINVAL;
+ } else if (
+ (intr != LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT) &&
+ (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH) &&
+ (intr != LPDDR4_INTR_TIMEOUT_ZQ_CALSTART) &&
+ (intr != LPDDR4_INTR_TIMEOUT_MRR_TEMP) &&
+ (intr != LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ) &&
+ (intr != LPDDR4_INTR_TIMEOUT_DFI_UPDATE) &&
+ (intr != LPDDR4_INTR_TIMEOUT_LP_WAKEUP) &&
+ (intr != LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX) &&
+ (intr != LPDDR4_INTR_ECC_ERROR) &&
+ (intr != LPDDR4_INTR_LP_DONE) &&
+ (intr != LPDDR4_INTR_LP_TIMEOUT) &&
+ (intr != LPDDR4_INTR_PORT_TIMEOUT) &&
+ (intr != LPDDR4_INTR_RFIFO_TIMEOUT) &&
+ (intr != LPDDR4_INTR_TRAINING_ZQ_STATUS) &&
+ (intr != LPDDR4_INTR_TRAINING_DQS_OSC_DONE) &&
+ (intr != LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE) &&
+ (intr != LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW) &&
+ (intr != LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT) &&
+ (intr != LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS) &&
+ (intr != LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS) &&
+ (intr != LPDDR4_INTR_USERIF_PORT_CMD_ERROR) &&
+ (intr != LPDDR4_INTR_USERIF_WRAP) &&
+ (intr != LPDDR4_INTR_USERIF_INVAL_SETTING) &&
+ (intr != LPDDR4_INTR_MISC_MRR_TRAFFIC) &&
+ (intr != LPDDR4_INTR_MISC_SW_REQ_MODE) &&
+ (intr != LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH) &&
+ (intr != LPDDR4_INTR_MISC_TEMP_ALERT) &&
+ (intr != LPDDR4_INTR_MISC_REFRESH_STATUS) &&
+ (intr != LPDDR4_INTR_BIST_DONE) &&
+ (intr != LPDDR4_INTR_CRC) &&
+ (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
+ (intr != LPDDR4_INTR_DFI_PHY_ERROR) &&
+ (intr != LPDDR4_INTR_DFI_BUS_ERROR) &&
+ (intr != LPDDR4_INTR_DFI_STATE_CHANGE) &&
+ (intr != LPDDR4_INTR_DFI_DLL_SYNC_DONE) &&
+ (intr != LPDDR4_INTR_DFI_TIMEOUT) &&
+ (intr != LPDDR4_INTR_DIMM) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_HW_TERMINATE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_HW_DONE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_SW_TERMINATE) &&
+ (intr != LPDDR4_INTR_FREQ_DFS_SW_DONE) &&
+ (intr != LPDDR4_INTR_INIT_MEM_RESET_DONE) &&
+ (intr != LPDDR4_INTR_MC_INIT_DONE) &&
+ (intr != LPDDR4_INTR_INIT_POWER_ON_STATE) &&
+ (intr != LPDDR4_INTR_MRR_ERROR) &&
+ (intr != LPDDR4_INTR_MR_READ_DONE) &&
+ (intr != LPDDR4_INTR_MR_WRITE_DONE) &&
+ (intr != LPDDR4_INTR_PARITY_ERROR) &&
+ (intr != LPDDR4_INTR_LOR_BITS)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus)
+{
+ u32 ret = 0;
+
+ if (pd == NULL) {
+ ret = EINVAL;
+ } else if (irqstatus == NULL) {
+ ret = EINVAL;
+ } else if (
+ (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr)
+{
+ u32 ret = 0;
+
+ if (pd == NULL) {
+ ret = EINVAL;
+ } else if (
+ (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPDDR4_16BIT_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.c b/drivers/ram/k3-ddrss/lpddr4_32bit.c
new file mode 100644
index 0000000..ab2e448
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_32bit.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <errno.h>
+
+#include "cps_drv_lpddr4.h"
+#include "lpddr4_ctl_regs.h"
+#include "lpddr4_if.h"
+#include "lpddr4.h"
+#include "lpddr4_structs_if.h"
+
+static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound);
+
+u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
+{
+ u32 result = 0U;
+ u32 regval = 0U;
+
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
+ regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
+ CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
+ return result;
+}
+
+u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
+{
+ u32 result = 0U;
+ u32 lowermask = 0U;
+
+ result = lpddr4_getctlinterruptmasksf(pd, mask);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ lowermask = (u32)(CPS_FLD_READ(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG))));
+ *mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG))));
+ *mask = (u64)((*mask << WORD_SHIFT) | lowermask);
+ }
+ return result;
+}
+
+u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
+{
+ u32 result;
+ u32 regval = 0;
+ const u64 ui64one = 1ULL;
+ const u32 ui32irqcount = (u32)LPDDR4_INTR_LOR_BITS + 1U;
+
+ result = lpddr4_setctlinterruptmasksf(pd, mask);
+ if ((result == (u32)0) && (ui32irqcount < 64U)) {
+ if (*mask >= (ui64one << ui32irqcount))
+ result = (u32)EINVAL;
+ }
+
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = (u32)(*mask & WORD_MASK);
+ regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG)), regval);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
+
+ regval = (u32)((*mask >> WORD_SHIFT) & WORD_MASK);
+ regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG)), regval);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
+ }
+ return result;
+}
+
+u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
+{
+ u32 result;
+ u32 ctlirqstatus = 0;
+ u32 fieldshift = 0;
+
+ result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ if ((u32)intr >= (u32)WORD_SHIFT) {
+ ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_1__REG));
+ fieldshift = (u32)intr - ((u32)WORD_SHIFT);
+ } else {
+ ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_0__REG));
+ fieldshift = (u32)intr;
+ }
+
+ if (fieldshift < WORD_SHIFT) {
+ if (((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) > 0U)
+ *irqstatus = true;
+ else
+ *irqstatus = false;
+ }
+ }
+ return result;
+}
+
+u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
+{
+ u32 result = 0;
+ u32 regval = 0;
+ u32 localinterrupt = (u32)intr;
+
+ result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ if (localinterrupt > WORD_SHIFT) {
+ localinterrupt = (localinterrupt - (u32)WORD_SHIFT);
+ regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval);
+ } else {
+ regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval);
+ }
+ }
+
+ return result;
+}
+
+void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
+{
+ u32 regval;
+ u32 errbitmask = 0U;
+ u32 snum;
+ volatile u32 *regaddress;
+
+ regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
+ errbitmask = (LPDDR4_BIT_MASK << 1) | (LPDDR4_BIT_MASK);
+ for (snum = 0U; snum < DSLICE_NUM; snum++) {
+ regval = CPS_REG_READ(regaddress);
+ if ((regval & errbitmask) != 0U) {
+ debuginfo->wrlvlerror = CDN_TRUE;
+ *errfoundptr = true;
+ }
+ regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+ }
+}
+
+static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound)
+{
+ volatile u32 *regaddress;
+ u32 snum = 0U;
+ u32 errbitmask = 0U;
+ u32 regval = 0U;
+
+ if (*errorfound == (bool)false) {
+ regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
+ errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
+ for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
+ regval = CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD, CPS_REG_READ(regaddress));
+ if ((regval & errbitmask) != RX_CAL_DONE) {
+ debuginfo->rxoffseterror = (u8)true;
+ *errorfound = true;
+ }
+ regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
+ }
+ }
+}
+
+u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
+{
+ u32 result = 0U;
+ bool errorfound = false;
+
+ result = lpddr4_getdebuginitinfosf(pd, debuginfo);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
+ lpddr4_setsettings(ctlregbase, errorfound);
+ lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
+ errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
+ }
+
+ if (errorfound == (bool)true)
+ result = (u32)EPROTO;
+
+ return result;
+}
+
+u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
+{
+ u32 result = 0U;
+ u32 fldval = 0U;
+
+ result = lpddr4_geteccenablesf(pd, eccparam);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ fldval = CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)));
+ switch (fldval) {
+ case 3:
+ *eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
+ break;
+ case 2:
+ *eccparam = LPDDR4_ECC_ERR_DETECT;
+ break;
+ case 1:
+ *eccparam = LPDDR4_ECC_ENABLED;
+ break;
+ default:
+ *eccparam = LPDDR4_ECC_DISABLED;
+ break;
+ }
+ }
+ return result;
+}
+
+u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
+{
+ u32 result = 0U;
+ u32 regval = 0U;
+
+ result = lpddr4_seteccenablesf(pd, eccparam);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+
+ regval = CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)), *eccparam);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
+ }
+ return result;
+}
+
+u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
+{
+ u32 result = 0U;
+
+ result = lpddr4_getreducmodesf(pd, mode);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ if (CPS_FLD_READ(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U)
+ *mode = LPDDR4_REDUC_ON;
+ else
+ *mode = LPDDR4_REDUC_OFF;
+ }
+ return result;
+}
+u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
+{
+ u32 result = 0U;
+ u32 regval = 0U;
+
+ result = lpddr4_setreducmodesf(pd, mode);
+ if (result == (u32)0) {
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ regval = (u32)CPS_FLD_WRITE(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG)), *mode);
+ CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
+ }
+ return result;
+}
+
+u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
+{
+ u32 lowerdata;
+ lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
+ u32 result = (u32)0;
+
+ if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
+ *mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
+ *mmrvalue = (u64)0;
+ result = (u32)EIO;
+ } else {
+ *mrrstatus = (u8)0;
+ lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
+ *mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
+ *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
+ result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
+ }
+ return result;
+}
+
+#ifdef REG_WRITE_VERIF
+
+u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
+{
+ u32 rwmask = 0U;
+
+ switch (dslicenum) {
+ case 0:
+ if (arrayoffset < DSLICE0_REG_COUNT)
+ rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
+ break;
+ case 1:
+ if (arrayoffset < DSLICE1_REG_COUNT)
+ rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
+ break;
+ case 2:
+ if (arrayoffset < DSLICE2_REG_COUNT)
+ rwmask = g_lpddr4_data_slice_2_rw_mask[arrayoffset];
+ break;
+ default:
+ if (arrayoffset < DSLICE3_REG_COUNT)
+ rwmask = g_lpddr4_data_slice_3_rw_mask[arrayoffset];
+ break;
+ }
+ return rwmask;
+}
+#endif
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.h b/drivers/ram/k3-ddrss/lpddr4_32bit.h
new file mode 100644
index 0000000..1f7fe65
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_32bit.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_H
+#define LPDDR4_32BIT_H
+
+#define DSLICE_NUM (4U)
+#define ASLICE_NUM (1U)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DSLICE0_REG_COUNT (140U)
+#define DSLICE1_REG_COUNT (140U)
+#define DSLICE2_REG_COUNT (140U)
+#define DSLICE3_REG_COUNT (140U)
+#define ASLICE0_REG_COUNT (52U)
+#define PHY_CORE_REG_COUNT (140U)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPDDR4_32BIT_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
new file mode 100644
index 0000000..70f0ef5
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
@@ -0,0 +1,1548 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <linux/types.h>
+#include "lpddr4_ctl_regs_rw_masks.h"
+
+u32 g_lpddr4_ddr_controller_rw_mask[] = {
+ 0x00000F01U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x01FFFFFFU,
+ 0x01010100U,
+ 0x03013F01U,
+ 0x1F1F1F03U,
+ 0x00030303U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFF01U,
+ 0x0001FFFFU,
+ 0xFF0F7FFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7F7F0000U,
+ 0x7F7F7F7FU,
+ 0x00FF1F07U,
+ 0x3FFF01FFU,
+ 0xFF01FFFFU,
+ 0x3FFF01FFU,
+ 0xFF01FFFFU,
+ 0x3FFF01FFU,
+ 0x3F01FFFFU,
+ 0x00FFFFFFU,
+ 0x1F01FFFFU,
+ 0xFFFFFFFFU,
+ 0x1F01FFFFU,
+ 0xFFFFFFFFU,
+ 0x1F01FFFFU,
+ 0x070707FFU,
+ 0xFFFFFF01U,
+ 0x0FFFFFFFU,
+ 0x3F03FF1FU,
+ 0x1F1F1F1FU,
+ 0x0101011FU,
+ 0x1FFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0301FFFFU,
+ 0x0101017FU,
+ 0x07010000U,
+ 0x0003FF3FU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x03FF0101U,
+ 0x03FFFFFFU,
+ 0x03FFFFFFU,
+ 0xFFFFFFFFU,
+ 0x1F1F010FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x1F1F1FFFU,
+ 0x1F010F1FU,
+ 0x0F1F1F1FU,
+ 0x1F1F1F01U,
+ 0x00010F1FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFF1F1F1FU,
+ 0x1F1F1F07U,
+ 0xFF1F1F1FU,
+ 0x1F1F1F07U,
+ 0xFF1F1F1FU,
+ 0x1F1F1F07U,
+ 0x07010101U,
+ 0x01010000U,
+ 0x00010101U,
+ 0xFFFFFFFFU,
+ 0x0700FFFFU,
+ 0xFFFFFF07U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x000FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x000FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x010FFFFFU,
+ 0x00010100U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x01FFFFFFU,
+ 0x01000107U,
+ 0xFFFFFF03U,
+ 0x00FFFFFFU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x3F0F0F0FU,
+ 0x070FFF01U,
+ 0x0F0F0000U,
+ 0x000FFF07U,
+ 0xFFFF0FFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x01010101U,
+ 0x3F3F0101U,
+ 0x01FF03FFU,
+ 0xFFFF03FFU,
+ 0xFFFF03FFU,
+ 0xFFFF03FFU,
+ 0x00000100U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00FFFF0FU,
+ 0x07FFFFFFU,
+ 0x01FFFF00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x03FF0003U,
+ 0x03FF03FFU,
+ 0xFFFF1F1FU,
+ 0x03FF03FFU,
+ 0x1F1F03FFU,
+ 0x03FFFFFFU,
+ 0x03FF03FFU,
+ 0xFFFF1F1FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF00FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFF00FFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00FFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFF00U,
+ 0x010101FFU,
+ 0x01000000U,
+ 0x01010101U,
+ 0x03030101U,
+ 0x013F0000U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0FFF0000U,
+ 0x07030000U,
+ 0x010F0101U,
+ 0x01FFFF01U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFF0000U,
+ 0x7FFF7FFFU,
+ 0x7FFF7FFFU,
+ 0x00077FFFU,
+ 0x010FFF00U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00000007U,
+ 0xFFFFFFFFU,
+ 0x1F1F1F07U,
+ 0x000F1F1FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0007FFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FF00U,
+ 0x00000000U,
+ 0x0FFF0FFFU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x007F0FFFU,
+ 0x0FFF0FFFU,
+ 0x0FFF0FFFU,
+ 0x0000037FU,
+ 0x0FFF0FFFU,
+ 0x01010FFFU,
+ 0x03030303U,
+ 0x07070303U,
+ 0xFFFF0F0FU,
+ 0x0007FFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF0307U,
+ 0x1F01FFFFU,
+ 0xFFFF1F01U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x011F0301U,
+ 0x01030301U,
+ 0x0003FFFFU,
+ 0x00000000U,
+ 0x0103FFFFU,
+ 0x01010103U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x0F0F0F07U,
+ 0x0F0F070FU,
+ 0x011F0F0FU,
+ 0x01000003U,
+ 0x03030301U,
+ 0x00010101U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0xFFFFFFFFU,
+ 0x00001FFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x03000000U,
+ 0xFF030303U,
+ 0x0FFF0F0FU,
+ 0x0F0FFF0FU,
+ 0x01010101U,
+ 0x3F3F3F3FU,
+ 0x1F1F3F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x0F1F1F1FU,
+ 0x0F070F07U,
+ 0x00000707U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x013F3F01U,
+ 0x0F010101U,
+ 0x00030101U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000FFFFU,
+ 0x010F0F01U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x03030101U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00000100U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x010FFFFFU,
+ 0x0101030FU,
+ 0x03010101U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0101FFFFU,
+ 0x00000707U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00FFFFFFU,
+ 0x7F7F7F00U,
+ 0x00FF0300U,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x007FFFFFU,
+ 0xFFFFFFFFU,
+ 0x00007F7FU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x007FFFFFU,
+ 0xFFFFFFFFU,
+ 0x00007F7FU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x007FFFFFU,
+ 0xFFFFFFFFU,
+ 0x0F0F7F7FU,
+ 0xFF0F0F0FU,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003FFFFU,
+ 0xFFFFFFFFU,
+ 0x000101FFU,
+ 0xFFFFFFFFU,
+ 0x00FF0000U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x07000101U,
+ 0x7F7F0707U,
+ 0x7F7F7F7FU,
+ 0x010101FFU,
+ 0x07070701U,
+ 0x0F070707U,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0xFF0F0F0FU,
+ 0xFFFF00FFU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x01010101U,
+ 0x01010101U,
+ 0x00010101U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000100U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00000007U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000000FU
+};
+
+u32 g_lpddr4_pi_rw_mask[] = {
+ 0x00000F01U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010101U,
+ 0x00FFFFFFU,
+ 0x01010301U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0xFFFFFFFFU,
+ 0x0101011FU,
+ 0x0F011F0FU,
+ 0x00010103U,
+ 0x000FFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000007U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00010101U,
+ 0x003F3F03U,
+ 0x0101FFFFU,
+ 0x0F010F01U,
+ 0x0000FF00U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0F0F0F1FU,
+ 0x00030000U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0101010FU,
+ 0x01010101U,
+ 0x000F0F01U,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0x0000FF0FU,
+ 0xFFFFFFFFU,
+ 0x00FFFF00U,
+ 0x0F0FFFFFU,
+ 0x01011F1FU,
+ 0x03000000U,
+ 0x01030F01U,
+ 0x0F010101U,
+ 0x000000FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF0001U,
+ 0x1F1F3F1FU,
+ 0xFF0F0F01U,
+ 0x7F1F0FFFU,
+ 0x0101FFFFU,
+ 0x00FFFF01U,
+ 0x00000000U,
+ 0x010F0701U,
+ 0x011F1F0FU,
+ 0x00FF0300U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0101FFFFU,
+ 0x01010100U,
+ 0x0F1F0703U,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x000F0F0FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0FFFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x011F1F00U,
+ 0x03030301U,
+ 0x00FF0103U,
+ 0x013F0001U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x0000FF07U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0FFF0000U,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0xFFFFFFFFU,
+ 0x0303070FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x0101010FU,
+ 0x01010100U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFF0101U,
+ 0x000000FFU,
+ 0x03FFFFFFU,
+ 0x01FFFF00U,
+ 0x01000000U,
+ 0x0100000FU,
+ 0x00010F07U,
+ 0x0F00010FU,
+ 0x010F0001U,
+ 0x00010F00U,
+ 0x0F00010FU,
+ 0x010F0001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x011F0000U,
+ 0x01010103U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x01010101U,
+ 0x0001FFFFU,
+ 0x0000001FU,
+ 0x0F011F01U,
+ 0x01010101U,
+ 0xFFFFFF01U,
+ 0x000000FFU,
+ 0x000000FFU,
+ 0x000FFFFFU,
+ 0x0FFF0FFFU,
+ 0x7F7F7F7FU,
+ 0x03FF7F7FU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x000FFFFFU,
+ 0x000003FFU,
+ 0x0F0FFFFFU,
+ 0x03030F0FU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x01FF01FFU,
+ 0x0F0F01FFU,
+ 0x0F0F0F0FU,
+ 0x03030303U,
+ 0x03030303U,
+ 0x03030303U,
+ 0x03030303U,
+ 0x7F7F0303U,
+ 0x7F7F7F7FU,
+ 0x00070707U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x1F030303U,
+ 0x001F3FFFU,
+ 0x001F3FFFU,
+ 0x1F1F3FFFU,
+ 0x03FF03FFU,
+ 0x03FF1F1FU,
+ 0x1F1F03FFU,
+ 0x03FF03FFU,
+ 0x7F7F7F7FU,
+ 0x0F0F7F7FU,
+ 0xFF1F0F0FU,
+ 0xFF1F0F1FU,
+ 0xFF1F0F1FU,
+ 0x0003FF1FU,
+ 0x03FFFFFFU,
+ 0x03FFFFFFU,
+ 0x003FFFFFU,
+ 0x003F03FFU,
+ 0x003F03FFU,
+ 0x03FF03FFU,
+ 0x7F7F03FFU,
+ 0x0003030FU,
+ 0x03FF03FFU,
+ 0x030F7F7FU,
+ 0x0003FF03U,
+ 0x7F7F03FFU,
+ 0xFF03030FU,
+ 0xFF3FFFFFU,
+ 0xFF01FFFFU,
+ 0xFFFF3F0FU,
+ 0xFFFFFFFFU,
+ 0x0000FF3FU,
+ 0xFF01FFFFU,
+ 0xFFFF3F0FU,
+ 0xFFFFFFFFU,
+ 0x0000FF3FU,
+ 0xFF01FFFFU,
+ 0xFFFF3F0FU,
+ 0x1FFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0x001FFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x3F3FFFFFU,
+ 0xFFFFFF3FU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x0000FFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x0000FFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x00FFFFFFU,
+ 0x0FFFFFFFU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0x000FFF7FU,
+ 0x0FFF0FFFU,
+ 0xFF0F0F0FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0FFFFFFFU,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0xFF0F0F0FU,
+ 0x0FFFFFFFU,
+ 0x0F0F0F0FU,
+ 0x000F0F0FU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x000007FFU
+};
+
+u32 g_lpddr4_data_slice_0_rw_mask[] = {
+ 0x000F07FFU,
+ 0x000703FFU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x01030F3FU,
+ 0x1F1F0301U,
+ 0x1F030F0FU,
+ 0x0101FF03U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x0101FF7FU,
+ 0x00003F01U,
+ 0x000F03FFU,
+ 0x070101FFU,
+ 0x000301FFU,
+ 0x00000000U,
+ 0x00000301U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0xFF030001U,
+ 0x00FF0F3FU,
+ 0x0F3F03FFU,
+ 0x1F030F3FU,
+ 0x3FFFFFFFU,
+ 0x0F07FF07U,
+ 0x0000FF0FU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x010001FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0x00000000U,
+ 0x017F7F01U,
+ 0x07FF0FFFU,
+ 0x03FFFF1FU,
+ 0x01FFFF3FU,
+ 0x07030101U,
+ 0x01010101U,
+ 0x000007FFU,
+ 0x00003FFFU,
+ 0x00001F00U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x003F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x000703FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x03FFFF01U,
+ 0x1F1F0103U,
+ 0x3F07FF0FU,
+ 0xFF0FFFFFU,
+ 0x1F0F3F0FU,
+ 0x03FF03FFU,
+ 0x0F010FFFU,
+ 0x000003FFU,
+ 0x3F0103FFU,
+ 0x00030703U,
+ 0x07FF03FFU,
+ 0xFFFF0101U,
+ 0x001F3F7FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_1_rw_mask[] = {
+ 0x000F07FFU,
+ 0x000703FFU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x01030F3FU,
+ 0x1F1F0301U,
+ 0x1F030F0FU,
+ 0x0101FF03U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x0101FF7FU,
+ 0x00003F01U,
+ 0x000F03FFU,
+ 0x070101FFU,
+ 0x000301FFU,
+ 0x00000000U,
+ 0x00000301U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0xFF030001U,
+ 0x00FF0F3FU,
+ 0x0F3F03FFU,
+ 0x1F030F3FU,
+ 0x3FFFFFFFU,
+ 0x0F07FF07U,
+ 0x0000FF0FU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x010001FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0x00000000U,
+ 0x017F7F01U,
+ 0x07FF0FFFU,
+ 0x03FFFF1FU,
+ 0x01FFFF3FU,
+ 0x07030101U,
+ 0x01010101U,
+ 0x000007FFU,
+ 0x00003FFFU,
+ 0x00001F00U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x003F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x000703FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x03FFFF01U,
+ 0x1F1F0103U,
+ 0x3F07FF0FU,
+ 0xFF0FFFFFU,
+ 0x1F0F3F0FU,
+ 0x03FF03FFU,
+ 0x0F010FFFU,
+ 0x000003FFU,
+ 0x3F0103FFU,
+ 0x00030703U,
+ 0x07FF03FFU,
+ 0xFFFF0101U,
+ 0x001F3F7FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_2_rw_mask[] = {
+ 0x000F07FFU,
+ 0x000703FFU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x01030F3FU,
+ 0x1F1F0301U,
+ 0x1F030F0FU,
+ 0x0101FF03U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x0101FF7FU,
+ 0x00003F01U,
+ 0x000F03FFU,
+ 0x070101FFU,
+ 0x000301FFU,
+ 0x00000000U,
+ 0x00000301U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0xFF030001U,
+ 0x00FF0F3FU,
+ 0x0F3F03FFU,
+ 0x1F030F3FU,
+ 0x3FFFFFFFU,
+ 0x0F07FF07U,
+ 0x0000FF0FU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x010001FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0x00000000U,
+ 0x017F7F01U,
+ 0x07FF0FFFU,
+ 0x03FFFF1FU,
+ 0x01FFFF3FU,
+ 0x07030101U,
+ 0x01010101U,
+ 0x000007FFU,
+ 0x00003FFFU,
+ 0x00001F00U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x003F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x000703FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x03FFFF01U,
+ 0x1F1F0103U,
+ 0x3F07FF0FU,
+ 0xFF0FFFFFU,
+ 0x1F0F3F0FU,
+ 0x03FF03FFU,
+ 0x0F010FFFU,
+ 0x000003FFU,
+ 0x3F0103FFU,
+ 0x00030703U,
+ 0x07FF03FFU,
+ 0xFFFF0101U,
+ 0x001F3F7FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003033FU
+};
+
+u32 g_lpddr4_data_slice_3_rw_mask[] = {
+ 0x000F07FFU,
+ 0x000703FFU,
+ 0x010303FFU,
+ 0x3F3F3F3FU,
+ 0x3F3F3F3FU,
+ 0x01030F3FU,
+ 0x1F1F0301U,
+ 0x1F030F0FU,
+ 0x0101FF03U,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x0101FF7FU,
+ 0x00003F01U,
+ 0x000F03FFU,
+ 0x070101FFU,
+ 0x000301FFU,
+ 0x00000000U,
+ 0x00000301U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x070F0107U,
+ 0x0F0F0F0FU,
+ 0xFF030001U,
+ 0x00FF0F3FU,
+ 0x0F3F03FFU,
+ 0x1F030F3FU,
+ 0x3FFFFFFFU,
+ 0x0F07FF07U,
+ 0x0000FF0FU,
+ 0x000001FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0001FFFFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7FFFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x010001FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x01FF01FFU,
+ 0x000001FFU,
+ 0x0003FFFFU,
+ 0x01FF01FFU,
+ 0x00000000U,
+ 0x017F7F01U,
+ 0x07FF0FFFU,
+ 0x03FFFF1FU,
+ 0x01FFFF3FU,
+ 0x07030101U,
+ 0x01010101U,
+ 0x000007FFU,
+ 0x00003FFFU,
+ 0x00001F00U,
+ 0x07FFFF07U,
+ 0x7F03FFFFU,
+ 0xFF01037FU,
+ 0x07FF07FFU,
+ 0x0103FFFFU,
+ 0x1F1F0F3FU,
+ 0x1F1F1F1FU,
+ 0x1F1F1F1FU,
+ 0x003F1F1FU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x000703FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFF0FU,
+ 0x0FFFFFFFU,
+ 0x03FFFF01U,
+ 0x1F1F0103U,
+ 0x3F07FF0FU,
+ 0xFF0FFFFFU,
+ 0x1F0F3F0FU,
+ 0x03FF03FFU,
+ 0x0F010FFFU,
+ 0x000003FFU,
+ 0x3F0103FFU,
+ 0x00030703U,
+ 0x07FF03FFU,
+ 0xFFFF0101U,
+ 0x001F3F7FU,
+ 0xFFFFFFFFU,
+ 0x0000000FU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x03FF07FFU,
+ 0x0003FF03U,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF03FFU,
+ 0x03FF070FU,
+ 0x000103FFU,
+ 0x000F03FFU,
+ 0x010F07FFU,
+ 0x000003FFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003033FU
+};
+
+u32 g_lpddr4_address_slice_0_rw_mask[] = {
+ 0x000107FFU,
+ 0x00000000U,
+ 0x0F000000U,
+ 0x00000000U,
+ 0x01000707U,
+ 0x011F7F7FU,
+ 0x01000301U,
+ 0x07FFFFFFU,
+ 0x0000003FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x00FFFFFFU,
+ 0x03FFFFFFU,
+ 0x01FF0F03U,
+ 0x07000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x00FFFFFFU,
+ 0x3F3F03FFU,
+ 0x3F0F3F3FU,
+ 0xFFFFFF03U,
+ 0x01FFFFFFU,
+ 0x3F03FFFFU,
+ 0x0101FFFFU,
+ 0x07FF3F01U,
+ 0x01FF0000U,
+ 0x01000000U,
+ 0x00000000U,
+ 0x07FF07FFU,
+ 0x1F07FF1FU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x001F07FFU,
+ 0x000F07FFU,
+ 0xFF3F07FFU,
+ 0x0103FFFFU,
+ 0x0000000FU,
+ 0x03FF010FU,
+ 0x0000FF01U
+};
+
+u32 g_lpddr4_phy_core_rw_mask[] = {
+ 0x00000003U,
+ 0x1F030101U,
+ 0x1F1F1F1FU,
+ 0x001F1F1FU,
+ 0x011F07FFU,
+ 0x07FF0100U,
+ 0x000107FFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0101FF01U,
+ 0x0007FF0FU,
+ 0xFF0F07FFU,
+ 0x01030007U,
+ 0xFFFF0101U,
+ 0xFF3F0103U,
+ 0x010101FFU,
+ 0x0F0F0100U,
+ 0x010F0F01U,
+ 0xFFFF0101U,
+ 0x0001010FU,
+ 0x00000000U,
+ 0x0000FFFFU,
+ 0x00000001U,
+ 0x0F0F0F0FU,
+ 0x0F0F0F0FU,
+ 0x01FF0F0FU,
+ 0x001FFFFFU,
+ 0x0001FFFFU,
+ 0x0007FFFFU,
+ 0x000003FFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x0001FF0FU,
+ 0x000103FFU,
+ 0x0003FFFFU,
+ 0x0001FFFFU,
+ 0x0001FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x0003FFFFU,
+ 0x1FFF03FFU,
+ 0x00001FFFU,
+ 0xFFFFFFFFU,
+ 0x000007FFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x7F000000U,
+ 0x01FFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0FFFFF7FU,
+ 0x000FFFFFU,
+ 0x01FFFFFFU,
+ 0x3F7FFFFFU,
+ 0x3F3F1F3FU,
+ 0x1F3F3F1FU,
+ 0x001F3F3FU,
+ 0x07FFFFFFU,
+ 0x03010000U,
+ 0x0F7F01FFU,
+ 0x00000000U,
+ 0x003F0101U,
+ 0x01010000U,
+ 0x00000001U,
+ 0xFFFFFFFFU,
+ 0x031F01FFU,
+ 0x00000003U,
+ 0xFFFFFFFFU,
+ 0x03FFFFFFU,
+ 0x07FF073FU,
+ 0x00000007U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000003U,
+ 0x070F0101U,
+ 0x00000000U,
+ 0x0707FF01U,
+ 0x00007F00U,
+ 0x3FFF0000U,
+ 0x3F000000U,
+ 0x000FFF00U,
+ 0x03000FFFU,
+ 0x00000000U,
+ 0x000001FFU,
+ 0x03FF0000U,
+ 0x03000000U,
+ 0x007F0000U,
+ 0x00003F00U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x0000FFFFU,
+ 0xFFFFFFFFU,
+ 0x1F0FFFFFU,
+ 0x0FFFFFFFU,
+ 0x0000FFFFU,
+ 0x00003FFFU,
+ 0x3FFF0000U,
+ 0x00000000U,
+ 0x00003FFFU,
+ 0x0003FFFFU,
+ 0x00003FFFU,
+ 0x00000001U,
+ 0x00011FFFU,
+ 0x0F0F0FFFU,
+ 0x010101FFU,
+ 0x07FF07FFU,
+ 0x07FF07FFU,
+ 0x000007FFU,
+ 0x000007FFU,
+ 0x000007FFU,
+ 0x000007FFU,
+ 0x00000007U,
+ 0x3FFFFFFFU,
+ 0x0003FFFFU,
+ 0x7FFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x3FFFFFFFU,
+ 0x07FFFFFFU,
+ 0xFFFFFFFFU,
+ 0x0003FFFFU,
+ 0x3FFFFFFFU,
+ 0x07FFFFFFU,
+ 0x3FFFFFFFU,
+ 0x07FFFFFFU,
+ 0x3FFFFFFFU,
+ 0x07FFFFFFU,
+ 0x3FFFFFFFU,
+ 0x07FFFFFFU,
+ 0x7FFFFF07U
+};
diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
new file mode 100644
index 0000000..334eecc
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
@@ -0,0 +1,223 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_32BIT_SANITY_H
+#define LPDDR4_32BIT_SANITY_H
+
+#include <errno.h>
+#include <linux/types.h>
+#include <lpddr4_if.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
+static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
+static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
+static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
+
+#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1
+#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2
+#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3
+#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4
+
+static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus)
+{
+ u32 ret = 0;
+
+ if (pd == NULL) {
+ ret = EINVAL;
+ } else if (irqstatus == NULL) {
+ ret = EINVAL;
+ } else if (
+ (intr != LPDDR4_INTR_RESET_DONE) &&
+ (intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
+ (intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
+ (intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
+ (intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
+ (intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
+ (intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
+ (intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
+ (intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
+ (intr != LPDDR4_INTR_MC_INIT_DONE) &&
+ (intr != LPDDR4_INTR_LP_DONE) &&
+ (intr != LPDDR4_INTR_BIST_DONE) &&
+ (intr != LPDDR4_INTR_WRAP_ERROR) &&
+ (intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
+ (intr != LPDDR4_INTR_RDLVL_ERROR) &&
+ (intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
+ (intr != LPDDR4_INTR_WRLVL_ERROR) &&
+ (intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
+ (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
+ (intr != LPDDR4_INTR_MRR_ERROR) &&
+ (intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
+ (intr != LPDDR4_INTR_WRLVL_REQ) &&
+ (intr != LPDDR4_INTR_RDLVL_REQ) &&
+ (intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
+ (intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
+ (intr != LPDDR4_INTR_LEVELING_DONE) &&
+ (intr != LPDDR4_INTR_PHY_ERROR) &&
+ (intr != LPDDR4_INTR_MR_READ_DONE) &&
+ (intr != LPDDR4_INTR_TEMP_CHANGE) &&
+ (intr != LPDDR4_INTR_TEMP_ALERT) &&
+ (intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
+ (intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
+ (intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
+ (intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
+ (intr != LPDDR4_INTR_MR_WRITE_DONE) &&
+ (intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
+ (intr != LPDDR4_INTR_DFI_INIT_STATE) &&
+ (intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
+ (intr != LPDDR4_INTR_TDFI_TO) &&
+ (intr != LPDDR4_INTR_DFS_DONE) &&
+ (intr != LPDDR4_INTR_DFS_STATUS) &&
+ (intr != LPDDR4_INTR_REFRESH_STATUS) &&
+ (intr != LPDDR4_INTR_ZQ_STATUS) &&
+ (intr != LPDDR4_INTR_SW_REQ_MODE) &&
+ (intr != LPDDR4_INTR_LOR_BITS)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr)
+{
+ u32 ret = 0;
+
+ if (pd == NULL) {
+ ret = EINVAL;
+ } else if (
+ (intr != LPDDR4_INTR_RESET_DONE) &&
+ (intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
+ (intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
+ (intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
+ (intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
+ (intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
+ (intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
+ (intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
+ (intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
+ (intr != LPDDR4_INTR_MC_INIT_DONE) &&
+ (intr != LPDDR4_INTR_LP_DONE) &&
+ (intr != LPDDR4_INTR_BIST_DONE) &&
+ (intr != LPDDR4_INTR_WRAP_ERROR) &&
+ (intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
+ (intr != LPDDR4_INTR_RDLVL_ERROR) &&
+ (intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
+ (intr != LPDDR4_INTR_WRLVL_ERROR) &&
+ (intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
+ (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
+ (intr != LPDDR4_INTR_MRR_ERROR) &&
+ (intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
+ (intr != LPDDR4_INTR_WRLVL_REQ) &&
+ (intr != LPDDR4_INTR_RDLVL_REQ) &&
+ (intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
+ (intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
+ (intr != LPDDR4_INTR_LEVELING_DONE) &&
+ (intr != LPDDR4_INTR_PHY_ERROR) &&
+ (intr != LPDDR4_INTR_MR_READ_DONE) &&
+ (intr != LPDDR4_INTR_TEMP_CHANGE) &&
+ (intr != LPDDR4_INTR_TEMP_ALERT) &&
+ (intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
+ (intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
+ (intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
+ (intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
+ (intr != LPDDR4_INTR_MR_WRITE_DONE) &&
+ (intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
+ (intr != LPDDR4_INTR_DFI_INIT_STATE) &&
+ (intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
+ (intr != LPDDR4_INTR_TDFI_TO) &&
+ (intr != LPDDR4_INTR_DFS_DONE) &&
+ (intr != LPDDR4_INTR_DFS_STATUS) &&
+ (intr != LPDDR4_INTR_REFRESH_STATUS) &&
+ (intr != LPDDR4_INTR_ZQ_STATUS) &&
+ (intr != LPDDR4_INTR_SW_REQ_MODE) &&
+ (intr != LPDDR4_INTR_LOR_BITS)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus)
+{
+ u32 ret = 0;
+
+ if (pd == NULL) {
+ ret = EINVAL;
+ } else if (irqstatus == NULL) {
+ ret = EINVAL;
+ } else if (
+ (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr)
+{
+ u32 ret = 0;
+
+ if (pd == NULL) {
+ ret = EINVAL;
+ } else if (
+ (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
+ (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPDDR4_32BIT_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_if.h b/drivers/ram/k3-ddrss/lpddr4_if.h
new file mode 100644
index 0000000..7562989
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_if.h
@@ -0,0 +1,144 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_IF_H
+#define LPDDR4_IF_H
+
+#include <linux/types.h>
+#ifdef CONFIG_K3_AM64_DDRSS
+#include <lpddr4_16bit_if.h>
+#else
+#include <lpddr4_32bit_if.h>
+#endif
+
+typedef struct lpddr4_config_s lpddr4_config;
+typedef struct lpddr4_privatedata_s lpddr4_privatedata;
+typedef struct lpddr4_debuginfo_s lpddr4_debuginfo;
+typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs;
+
+typedef enum {
+ LPDDR4_CTL_REGS = 0U,
+ LPDDR4_PHY_REGS = 1U,
+ LPDDR4_PHY_INDEP_REGS = 2U
+} lpddr4_regblock;
+
+typedef enum {
+ LPDDR4_DRV_NONE = 0U,
+ LPDDR4_DRV_SOC_PLL_UPDATE = 1U
+} lpddr4_infotype;
+
+typedef enum {
+ LPDDR4_LPI_PD_WAKEUP_FN = 0U,
+ LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U,
+ LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U,
+ LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U,
+ LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U,
+ LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U,
+ LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U
+} lpddr4_lpiwakeupparam;
+
+typedef enum {
+ LPDDR4_REDUC_ON = 0U,
+ LPDDR4_REDUC_OFF = 1U
+} lpddr4_reducmode;
+
+typedef enum {
+ LPDDR4_ECC_DISABLED = 0U,
+ LPDDR4_ECC_ENABLED = 1U,
+ LPDDR4_ECC_ERR_DETECT = 2U,
+ LPDDR4_ECC_ERR_DETECT_CORRECT = 3U
+} lpddr4_eccenable;
+
+typedef enum {
+ LPDDR4_DBI_RD_ON = 0U,
+ LPDDR4_DBI_RD_OFF = 1U,
+ LPDDR4_DBI_WR_ON = 2U,
+ LPDDR4_DBI_WR_OFF = 3U
+} lpddr4_dbimode;
+
+typedef enum {
+ LPDDR4_FSP_0 = 0U,
+ LPDDR4_FSP_1 = 1U,
+ LPDDR4_FSP_2 = 2U
+} lpddr4_ctlfspnum;
+
+typedef void (*lpddr4_infocallback)(const lpddr4_privatedata *pd, lpddr4_infotype infotype);
+
+typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt ctlinterrupt, u8 chipselect);
+
+typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt phyindepinterrupt, u8 chipselect);
+
+u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize);
+
+u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg);
+
+u32 lpddr4_start(const lpddr4_privatedata *pd);
+
+u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
+
+u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
+
+u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
+
+u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
+
+u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask);
+
+u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask);
+
+u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
+
+u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
+
+u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask);
+
+u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask);
+
+u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
+
+u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
+
+u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
+
+u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
+
+u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
+
+u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
+
+u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
+
+u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
+
+u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
+
+u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off);
+
+u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off);
+
+u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
+
+u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
+
+u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+
+u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval);
+
+#endif /* LPDDR4_IF_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.c b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
new file mode 100644
index 0000000..370242f
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include "lpddr4_obj_if.h"
+
+lpddr4_obj *lpddr4_getinstance(void)
+{
+ static lpddr4_obj driver = {
+ .probe = lpddr4_probe,
+ .init = lpddr4_init,
+ .start = lpddr4_start,
+ .readreg = lpddr4_readreg,
+ .writereg = lpddr4_writereg,
+ .getmmrregister = lpddr4_getmmrregister,
+ .setmmrregister = lpddr4_setmmrregister,
+ .writectlconfig = lpddr4_writectlconfig,
+ .writephyconfig = lpddr4_writephyconfig,
+ .writephyindepconfig = lpddr4_writephyindepconfig,
+ .readctlconfig = lpddr4_readctlconfig,
+ .readphyconfig = lpddr4_readphyconfig,
+ .readphyindepconfig = lpddr4_readphyindepconfig,
+ .getctlinterruptmask = lpddr4_getctlinterruptmask,
+ .setctlinterruptmask = lpddr4_setctlinterruptmask,
+ .checkctlinterrupt = lpddr4_checkctlinterrupt,
+ .ackctlinterrupt = lpddr4_ackctlinterrupt,
+ .getphyindepinterruptmask = lpddr4_getphyindepinterruptmask,
+ .setphyindepinterruptmask = lpddr4_setphyindepinterruptmask,
+ .checkphyindepinterrupt = lpddr4_checkphyindepinterrupt,
+ .ackphyindepinterrupt = lpddr4_ackphyindepinterrupt,
+ .getdebuginitinfo = lpddr4_getdebuginitinfo,
+ .getlpiwakeuptime = lpddr4_getlpiwakeuptime,
+ .setlpiwakeuptime = lpddr4_setlpiwakeuptime,
+ .geteccenable = lpddr4_geteccenable,
+ .seteccenable = lpddr4_seteccenable,
+ .getreducmode = lpddr4_getreducmode,
+ .setreducmode = lpddr4_setreducmode,
+ .getdbireadmode = lpddr4_getdbireadmode,
+ .getdbiwritemode = lpddr4_getdbiwritemode,
+ .setdbimode = lpddr4_setdbimode,
+ .getrefreshrate = lpddr4_getrefreshrate,
+ .setrefreshrate = lpddr4_setrefreshrate,
+ .refreshperchipselect = lpddr4_refreshperchipselect,
+ };
+
+ return &driver;
+}
diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.h b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
new file mode 100644
index 0000000..d538e61
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef lpddr4_obj_if_h
+#define lpddr4_obj_if_h
+
+#include "lpddr4_if.h"
+
+typedef struct lpddr4_obj_s {
+ u32 (*probe)(const lpddr4_config *config, u16 *configsize);
+
+ u32 (*init)(lpddr4_privatedata *pd, const lpddr4_config *cfg);
+
+ u32 (*start)(const lpddr4_privatedata *pd);
+
+ u32 (*readreg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
+
+ u32 (*writereg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
+
+ u32 (*getmmrregister)(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
+
+ u32 (*setmmrregister)(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
+
+ u32 (*writectlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+ u32 (*writephyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+ u32 (*writephyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+ u32 (*readctlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+ u32 (*readphyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+ u32 (*readphyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
+
+ u32 (*getctlinterruptmask)(const lpddr4_privatedata *pd, u64 *mask);
+
+ u32 (*setctlinterruptmask)(const lpddr4_privatedata *pd, const u64 *mask);
+
+ u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
+
+ u32 (*ackctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
+
+ u32 (*getphyindepinterruptmask)(const lpddr4_privatedata *pd, u32 *mask);
+
+ u32 (*setphyindepinterruptmask)(const lpddr4_privatedata *pd, const u32 *mask);
+
+ u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
+
+ u32 (*ackphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
+
+ u32 (*getdebuginitinfo)(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
+
+ u32 (*getlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
+
+ u32 (*setlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
+
+ u32 (*geteccenable)(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
+
+ u32 (*seteccenable)(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
+
+ u32 (*getreducmode)(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
+
+ u32 (*setreducmode)(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
+
+ u32 (*getdbireadmode)(const lpddr4_privatedata *pd, bool *on_off);
+
+ u32 (*getdbiwritemode)(const lpddr4_privatedata *pd, bool *on_off);
+
+ u32 (*setdbimode)(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
+
+ u32 (*getrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
+
+ u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+
+ u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval);
+} lpddr4_obj;
+
+extern lpddr4_obj *lpddr4_getinstance(void);
+
+#endif /* lpddr4_obj_if_h */
diff --git a/drivers/ram/k3-j721e/lpddr4_private.h b/drivers/ram/k3-ddrss/lpddr4_private.h
similarity index 100%
rename from drivers/ram/k3-j721e/lpddr4_private.h
rename to drivers/ram/k3-ddrss/lpddr4_private.h
diff --git a/drivers/ram/k3-ddrss/lpddr4_sanity.h b/drivers/ram/k3-ddrss/lpddr4_sanity.h
new file mode 100644
index 0000000..750e00d
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_sanity.h
@@ -0,0 +1,445 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_SANITY_H
+#define LPDDR4_SANITY_H
+
+#include <errno.h>
+#include <linux/types.h>
+#include "lpddr4_if.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static inline u32 lpddr4_configsf(const lpddr4_config *obj);
+static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj);
+
+static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize);
+static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg);
+static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd);
+static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue);
+static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp);
+static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus);
+static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus);
+static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask);
+static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask);
+static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask);
+static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo);
+static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
+static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
+static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
+static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
+static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
+static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off);
+static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
+static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
+
+#define lpddr4_probesf lpddr4_sanityfunction1
+#define lpddr4_initsf lpddr4_sanityfunction2
+#define lpddr4_startsf lpddr4_sanityfunction3
+#define lpddr4_readregsf lpddr4_sanityfunction4
+#define lpddr4_writeregsf lpddr4_sanityfunction5
+#define lpddr4_getmmrregistersf lpddr4_sanityfunction6
+#define lpddr4_setmmrregistersf lpddr4_sanityfunction7
+#define lpddr4_writectlconfigsf lpddr4_sanityfunction3
+#define lpddr4_writephyconfigsf lpddr4_sanityfunction3
+#define lpddr4_writephyindepconfigsf lpddr4_sanityfunction3
+#define lpddr4_readctlconfigsf lpddr4_sanityfunction3
+#define lpddr4_readphyconfigsf lpddr4_sanityfunction3
+#define lpddr4_readphyindepconfigsf lpddr4_sanityfunction3
+#define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14
+#define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15
+#define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction16
+#define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction16
+#define lpddr4_getdebuginitinfosf lpddr4_sanityfunction18
+#define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction19
+#define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction19
+#define lpddr4_geteccenablesf lpddr4_sanityfunction21
+#define lpddr4_seteccenablesf lpddr4_sanityfunction22
+#define lpddr4_getreducmodesf lpddr4_sanityfunction23
+#define lpddr4_setreducmodesf lpddr4_sanityfunction24
+#define lpddr4_getdbireadmodesf lpddr4_sanityfunction25
+#define lpddr4_getdbiwritemodesf lpddr4_sanityfunction25
+#define lpddr4_setdbimodesf lpddr4_sanityfunction27
+#define lpddr4_getrefreshratesf lpddr4_sanityfunction28
+#define lpddr4_setrefreshratesf lpddr4_sanityfunction29
+#define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
+
+static inline u32 lpddr4_configsf(const lpddr4_config *obj)
+{
+ u32 ret = 0;
+
+ if (obj == NULL)
+ ret = EINVAL;
+
+ return ret;
+}
+
+static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj)
+{
+ u32 ret = 0;
+
+ if (obj == NULL)
+ ret = EINVAL;
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize)
+{
+ u32 ret = 0;
+
+ if (configsize == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_configsf(config) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg)
+{
+ u32 ret = 0;
+
+ if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else if (lpddr4_configsf(cfg) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd)
+{
+ u32 ret = 0;
+
+ if (lpddr4_privatedatasf(pd) == EINVAL)
+ ret = EINVAL;
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue)
+{
+ u32 ret = 0;
+
+ if (regvalue == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else if (
+ (cpp != LPDDR4_CTL_REGS) &&
+ (cpp != LPDDR4_PHY_REGS) &&
+ (cpp != LPDDR4_PHY_INDEP_REGS)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp)
+{
+ u32 ret = 0;
+
+ if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else if (
+ (cpp != LPDDR4_CTL_REGS) &&
+ (cpp != LPDDR4_PHY_REGS) &&
+ (cpp != LPDDR4_PHY_INDEP_REGS)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus)
+{
+ u32 ret = 0;
+
+ if (mmrvalue == NULL) {
+ ret = EINVAL;
+ } else if (mmrstatus == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus)
+{
+ u32 ret = 0;
+
+ if (mrwstatus == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask)
+{
+ u32 ret = 0;
+
+ if (mask == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask)
+{
+ u32 ret = 0;
+
+ if (mask == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask)
+{
+ u32 ret = 0;
+
+ if (mask == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo)
+{
+ u32 ret = 0;
+
+ if (debuginfo == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
+{
+ u32 ret = 0;
+
+ if (lpiwakeupparam == NULL) {
+ ret = EINVAL;
+ } else if (fspnum == NULL) {
+ ret = EINVAL;
+ } else if (cycles == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else if (
+ (*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) &&
+ (*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) &&
+ (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) &&
+ (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) &&
+ (*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) &&
+ (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) &&
+ (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN)
+ ) {
+ ret = EINVAL;
+ } else if (
+ (*fspnum != LPDDR4_FSP_0) &&
+ (*fspnum != LPDDR4_FSP_1) &&
+ (*fspnum != LPDDR4_FSP_2)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
+{
+ u32 ret = 0;
+
+ if (eccparam == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
+{
+ u32 ret = 0;
+
+ if (eccparam == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else if (
+ (*eccparam != LPDDR4_ECC_DISABLED) &&
+ (*eccparam != LPDDR4_ECC_ENABLED) &&
+ (*eccparam != LPDDR4_ECC_ERR_DETECT) &&
+ (*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
+{
+ u32 ret = 0;
+
+ if (mode == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
+{
+ u32 ret = 0;
+
+ if (mode == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else if (
+ (*mode != LPDDR4_REDUC_ON) &&
+ (*mode != LPDDR4_REDUC_OFF)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off)
+{
+ u32 ret = 0;
+
+ if (on_off == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
+{
+ u32 ret = 0;
+
+ if (mode == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else if (
+ (*mode != LPDDR4_DBI_RD_ON) &&
+ (*mode != LPDDR4_DBI_RD_OFF) &&
+ (*mode != LPDDR4_DBI_WR_ON) &&
+ (*mode != LPDDR4_DBI_WR_OFF)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
+{
+ u32 ret = 0;
+
+ if (fspnum == NULL) {
+ ret = EINVAL;
+ } else if (tref == NULL) {
+ ret = EINVAL;
+ } else if (tras_max == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else if (
+ (*fspnum != LPDDR4_FSP_0) &&
+ (*fspnum != LPDDR4_FSP_1) &&
+ (*fspnum != LPDDR4_FSP_2)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
+{
+ u32 ret = 0;
+
+ if (fspnum == NULL) {
+ ret = EINVAL;
+ } else if (tref == NULL) {
+ ret = EINVAL;
+ } else if (tras_max == NULL) {
+ ret = EINVAL;
+ } else if (lpddr4_privatedatasf(pd) == EINVAL) {
+ ret = EINVAL;
+ } else if (
+ (*fspnum != LPDDR4_FSP_0) &&
+ (*fspnum != LPDDR4_FSP_1) &&
+ (*fspnum != LPDDR4_FSP_2)
+ ) {
+ ret = EINVAL;
+ } else {
+ }
+
+ return ret;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* LPDDR4_SANITY_H */
diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
new file mode 100644
index 0000000..e41cbb7
--- /dev/null
+++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_STRUCTS_IF_H
+#define LPDDR4_STRUCTS_IF_H
+
+#include <linux/types.h>
+#include "lpddr4_if.h"
+
+struct lpddr4_config_s {
+ struct lpddr4_ctlregs_s *ctlbase;
+ lpddr4_infocallback infohandler;
+ lpddr4_ctlcallback ctlinterrupthandler;
+ lpddr4_phyindepcallback phyindepinterrupthandler;
+};
+
+struct lpddr4_privatedata_s {
+ struct lpddr4_ctlregs_s *ctlbase;
+ lpddr4_infocallback infohandler;
+ lpddr4_ctlcallback ctlinterrupthandler;
+ lpddr4_phyindepcallback phyindepinterrupthandler;
+};
+
+struct lpddr4_debuginfo_s {
+ u8 pllerror;
+ u8 iocaliberror;
+ u8 rxoffseterror;
+ u8 catraingerror;
+ u8 wrlvlerror;
+ u8 gatelvlerror;
+ u8 readlvlerror;
+ u8 dqtrainingerror;
+};
+
+struct lpddr4_fspmoderegs_s {
+ u8 mr1data_fn[LPDDR4_INTR_MAX_CS];
+ u8 mr2data_fn[LPDDR4_INTR_MAX_CS];
+ u8 mr3data_fn[LPDDR4_INTR_MAX_CS];
+ u8 mr11data_fn[LPDDR4_INTR_MAX_CS];
+ u8 mr12data_fn[LPDDR4_INTR_MAX_CS];
+ u8 mr13data_fn[LPDDR4_INTR_MAX_CS];
+ u8 mr14data_fn[LPDDR4_INTR_MAX_CS];
+ u8 mr22data_fn[LPDDR4_INTR_MAX_CS];
+};
+
+#endif /* LPDDR4_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-j721e/Makefile b/drivers/ram/k3-j721e/Makefile
deleted file mode 100644
index d60cc62..0000000
--- a/drivers/ram/k3-j721e/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
-#
-
-obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e-ddrss.o
-obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_obj_if.o
-obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4.o
diff --git a/drivers/ram/k3-j721e/cps_drv_lpddr4.h b/drivers/ram/k3-j721e/cps_drv_lpddr4.h
deleted file mode 100644
index 706a5cd..0000000
--- a/drivers/ram/k3-j721e/cps_drv_lpddr4.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/******************************************************************************
- *
- * Copyright (C) 2017-2018 Cadence Design Systems, Inc.
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- * cps_drv_lpddr4.h
- * Interface for the Register Accaess Layer of Cadence Platform Service (CPS)
- *****************************************************************************
- */
-
-#ifndef CPS_DRV_H_
-#define CPS_DRV_H_
-
-#include <stddef.h>
-#include <inttypes.h>
-#include <asm/io.h>
-
-/**
- * \brief Read a 32-bit value from memory.
- * \param reg address of the memory mapped hardware register
- * \return the value at the given address
- */
-#define CPS_REG_READ(reg) (readl((volatile uint32_t*)(reg)))
-
-/**
- * \brief Write a 32-bit address value to memory.
- * \param reg address of the memory mapped hardware register
- * \param value unsigned 32-bit value to write
- */
-#define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg)))
-
-/**
- * \brief Subtitue the value of fld macro and concatinate with required string
- * \param fld field name
- */
-#define CPS_FLD_MASK(fld) (fld ## _MASK)
-#define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
-#define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
-#define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
-#define CPS_FLD_WOSET(fld) (fld ## _WOSET)
-
-/**
- * \brief Read a value of bit-field from the register value.
- * \param reg register name
- * \param fld field name
- * \param reg_value register value
- * \return bit-field value
- */
-#define CPS_FLD_READ(fld, reg_value) (cps_fldread((uint32_t)(CPS_FLD_MASK(fld)), \
- (uint32_t)(CPS_FLD_SHIFT(fld)), \
- (uint32_t)(reg_value)))
-
-/**
- * \brief Write a value of the bit-field into the register value.
- * \param reg register name
- * \param fld field name
- * \param reg_value register value
- * \param value value to be written to bit-field
- * \return modified register value
- */
-#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((uint32_t)(CPS_FLD_MASK(fld)), \
- (uint32_t)(CPS_FLD_SHIFT(fld)), \
- (uint32_t)(reg_value), (uint32_t)(value)))
-
-/**
- * \brief Set bit within the register value.
- * \param reg register name
- * \param fld field name
- * \param reg_value register value
- * \return modified register value
- */
-#define CPS_FLD_SET(fld, reg_value) (cps_fldset((uint32_t)(CPS_FLD_WIDTH(fld)), \
- (uint32_t)(CPS_FLD_MASK(fld)), \
- (uint32_t)(CPS_FLD_WOCLR(fld)), \
- (uint32_t)(reg_value)))
-
-static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value)
-{
- uint32_t result = (reg_value & mask) >> shift;
-
- return (result);
-}
-
-/**
- * \brief Write a value of the bit-field into the register value.
- * \param mask mask for the bit-field
- * \param shift bit-field shift from LSB
- * \param reg_value register value
- * \param value value to be written to bit-field
- * \return modified register value
- */
-static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
-{
- uint32_t new_value = (value << shift) & mask;
-
- new_value = (reg_value & ~mask) | new_value;
- return (new_value);
-}
-
-/**
- * \brief Set bit within the register value.
- * \param width width of the bit-field
- * \param mask mask for the bit-field
- * \param is_woclr is bit-field has 'write one to clear' flag set
- * \param reg_value register value
- * \return modified register value
- */
-static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
-{
- uint32_t new_value = reg_value;
- /* Confirm the field to be bit and not write to clear type */
- if ((width == 1U) && (is_woclr == 0U)) {
- new_value |= mask;
- }
-
- return (new_value);
-}
-#endif /* CPS_DRV_H_ */
diff --git a/drivers/ram/k3-j721e/k3-j721e-ddrss.c b/drivers/ram/k3-j721e/k3-j721e-ddrss.c
deleted file mode 100644
index 9fb1eee..0000000
--- a/drivers/ram/k3-j721e/k3-j721e-ddrss.c
+++ /dev/null
@@ -1,375 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Texas Instruments' J721E DDRSS driver
- *
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <hang.h>
-#include <log.h>
-#include <ram.h>
-#include <asm/io.h>
-#include <power-domain.h>
-#include <wait_bit.h>
-#include <dm/device_compat.h>
-
-#include "lpddr4_obj_if.h"
-#include "lpddr4_if.h"
-#include "lpddr4_structs_if.h"
-#include "lpddr4_ctl_regs.h"
-
-#define SRAM_MAX 512
-
-#define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
-#define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
-
-struct j721e_ddrss_desc {
- struct udevice *dev;
- void __iomem *ddrss_ss_cfg;
- void __iomem *ddrss_ctrl_mmr;
- struct power_domain ddrcfg_pwrdmn;
- struct power_domain ddrdata_pwrdmn;
- struct clk ddr_clk;
- struct clk osc_clk;
- u32 ddr_freq1;
- u32 ddr_freq2;
- u32 ddr_fhs_cnt;
-};
-
-static LPDDR4_OBJ *driverdt;
-static lpddr4_config config;
-static lpddr4_privatedata pd;
-
-static struct j721e_ddrss_desc *ddrss;
-
-#define TH_MACRO_EXP(fld, str) (fld##str)
-
-#define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK)
-#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)
-#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)
-#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)
-#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)
-
-#define str(s) #s
-#define xstr(s) str(s)
-
-#define CTL_SHIFT 11
-#define PHY_SHIFT 11
-#define PI_SHIFT 10
-
-#define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
- char *i, *pstr= xstr(REG); offset = 0;\
- for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
- offset = offset * 10 + (*i - '0'); }\
- } while (0)
-
-static void j721e_lpddr4_ack_freq_upd_req(void)
-{
- unsigned int req_type, counter;
-
- debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
-
- for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
- if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
- true, 10000, false)) {
- printf("Timeout during frequency handshake\n");
- hang();
- }
-
- req_type = readl(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
-
- debug("%s: received freq change req: req type = %d, req no. = %d \n",
- __func__, req_type, counter);
-
- if (req_type == 1)
- clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
- else if (req_type == 2)
- clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
- else if (req_type == 0)
- /* Put DDR pll in bypass mode */
- clk_set_rate(&ddrss->ddr_clk,
- clk_get_rate(&ddrss->osc_clk));
- else
- printf("%s: Invalid freq request type\n", __func__);
-
- writel(0x1, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
- if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
- false, 10, false)) {
- printf("Timeout during frequency handshake\n");
- hang();
- }
- writel(0x0, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
- }
-}
-
-static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
- lpddr4_infotype infotype)
-{
- if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
- j721e_lpddr4_ack_freq_upd_req();
- }
-}
-
-static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
-{
- int ret;
-
- debug("%s(ddrss=%p)\n", __func__, ddrss);
-
- ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
- if (ret) {
- dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
- return ret;
- }
-
- ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
- if (ret) {
- dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
- return ret;
- }
-
- return 0;
-}
-
-static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
-{
- struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
- phys_addr_t reg;
- int ret;
-
- debug("%s(dev=%p)\n", __func__, dev);
-
- reg = dev_read_addr_name(dev, "cfg");
- if (reg == FDT_ADDR_T_NONE) {
- dev_err(dev, "No reg property for DDRSS wrapper logic\n");
- return -EINVAL;
- }
- ddrss->ddrss_ss_cfg = (void *)reg;
-
- reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
- if (reg == FDT_ADDR_T_NONE) {
- dev_err(dev, "No reg property for CTRL MMR\n");
- return -EINVAL;
- }
- ddrss->ddrss_ctrl_mmr = (void *)reg;
-
- ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
- if (ret) {
- dev_err(dev, "power_domain_get() failed: %d\n", ret);
- return ret;
- }
-
- ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
- if (ret) {
- dev_err(dev, "power_domain_get() failed: %d\n", ret);
- return ret;
- }
-
- ret = clk_get_by_index(dev, 0, &ddrss->ddr_clk);
- if (ret)
- dev_err(dev, "clk get failed%d\n", ret);
-
- ret = clk_get_by_index(dev, 1, &ddrss->osc_clk);
- if (ret)
- dev_err(dev, "clk get failed for osc clk %d\n", ret);
-
- ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
- if (ret)
- dev_err(dev, "ddr freq1 not populated %d\n", ret);
-
- ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2);
- if (ret)
- dev_err(dev, "ddr freq2 not populated %d\n", ret);
-
- ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt);
- if (ret)
- dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
-
- /* Put DDR pll in bypass mode */
- ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
- if (ret)
- dev_err(dev, "ddr clk bypass failed\n");
-
- return ret;
-}
-
-void j721e_lpddr4_probe(void)
-{
- uint32_t status = 0U;
- uint16_t configsize = 0U;
-
- status = driverdt->probe(&config, &configsize);
-
- if ((status != 0) || (configsize != sizeof(lpddr4_privatedata))
- || (configsize > SRAM_MAX)) {
- printf("LPDDR4_Probe: FAIL\n");
- hang();
- } else {
- debug("LPDDR4_Probe: PASS\n");
- }
-}
-
-void j721e_lpddr4_init(void)
-{
- uint32_t status = 0U;
-
- if ((sizeof(pd) != sizeof(lpddr4_privatedata))
- || (sizeof(pd) > SRAM_MAX)) {
- printf("LPDDR4_Init: FAIL\n");
- hang();
- }
-
- config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
- config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
-
- status = driverdt->init(&pd, &config);
-
- if ((status > 0U) ||
- (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
- (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
- (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
- printf("LPDDR4_Init: FAIL\n");
- hang();
- } else {
- debug("LPDDR4_Init: PASS\n");
- }
-}
-
-void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
-{
- int ret, i;
-
- ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
- (u32 *) reginit_data->denalictlreg,
- LPDDR4_CTL_REG_COUNT);
- if (ret)
- printf("Error reading ctrl data\n");
-
- for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
- reginit_data->updatectlreg[i] = true;
-
- ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
- (u32 *) reginit_data->denaliphyindepreg,
- LPDDR4_PHY_INDEP_REG_COUNT);
- if (ret)
- printf("Error reading PI data\n");
-
- for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
- reginit_data->updatephyindepreg[i] = true;
-
- ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
- (u32 *) reginit_data->denaliphyreg,
- LPDDR4_PHY_REG_COUNT);
- if (ret)
- printf("Error reading PHY data\n");
-
- for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
- reginit_data->updatephyreg[i] = true;
-}
-
-void j721e_lpddr4_hardware_reg_init(void)
-{
- uint32_t status = 0U;
- lpddr4_reginitdata reginitdata;
-
- populate_data_array_from_dt(®initdata);
-
- status = driverdt->writectlconfig(&pd, ®initdata);
- if (!status) {
- status = driverdt->writephyindepconfig(&pd, ®initdata);
- }
- if (!status) {
- status = driverdt->writephyconfig(&pd, ®initdata);
- }
- if (status) {
- printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
- hang();
- }
-
- return;
-}
-
-void j721e_lpddr4_start(void)
-{
- uint32_t status = 0U;
- uint32_t regval = 0U;
- uint32_t offset = 0U;
-
- TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
-
- status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
- if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 0U)) {
- printf("LPDDR4_StartTest: FAIL\n");
- hang();
- }
-
- status = driverdt->start(&pd);
- if (status > 0U) {
- printf("LPDDR4_StartTest: FAIL\n");
- hang();
- }
-
- status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
- if ((status > 0U) || ((regval & TH_FLD_MASK(LPDDR4__START__FLD)) != 1U)) {
- printf("LPDDR4_Start: FAIL\n");
- hang();
- } else {
- debug("LPDDR4_Start: PASS\n");
- }
-}
-
-static int j721e_ddrss_probe(struct udevice *dev)
-{
- int ret;
- ddrss = dev_get_priv(dev);
-
- debug("%s(dev=%p)\n", __func__, dev);
-
- ret = j721e_ddrss_ofdata_to_priv(dev);
- if (ret)
- return ret;
-
- ddrss->dev = dev;
- ret = j721e_ddrss_power_on(ddrss);
- if (ret)
- return ret;
-
- driverdt = lpddr4_getinstance();
- j721e_lpddr4_probe();
- j721e_lpddr4_init();
- j721e_lpddr4_hardware_reg_init();
- j721e_lpddr4_start();
-
- return ret;
-}
-
-static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
-{
- return 0;
-}
-
-static struct ram_ops j721e_ddrss_ops = {
- .get_info = j721e_ddrss_get_info,
-};
-
-static const struct udevice_id j721e_ddrss_ids[] = {
- {.compatible = "ti,j721e-ddrss"},
- {}
-};
-
-U_BOOT_DRIVER(j721e_ddrss) = {
- .name = "j721e_ddrss",
- .id = UCLASS_RAM,
- .of_match = j721e_ddrss_ids,
- .ops = &j721e_ddrss_ops,
- .probe = j721e_ddrss_probe,
- .priv_auto = sizeof(struct j721e_ddrss_desc),
-};
diff --git a/drivers/ram/k3-j721e/lpddr4.c b/drivers/ram/k3-j721e/lpddr4.c
deleted file mode 100644
index 68043d7..0000000
--- a/drivers/ram/k3-j721e/lpddr4.c
+++ /dev/null
@@ -1,2105 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/******************************************************************************
- * Copyright (C) 2012-2018 Cadence Design Systems, Inc.
- * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- *
- * lpddr4.c
- *
- *****************************************************************************
- */
-#include "cps_drv_lpddr4.h"
-#include "lpddr4_ctl_regs.h"
-#include "lpddr4_if.h"
-#include "lpddr4_private.h"
-#include "lpddr4_sanity.h"
-#include "lpddr4_structs_if.h"
-
-#define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
-
-/**
- * Internal Function:Poll for status of interrupt received by the Controller.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] irqBit Interrupt status bit to be checked.
- * @param[in] delay time delay.
- * @return CDN_EOK on success (Interrupt status high).
- * @return EIO on poll time out.
- * @return EINVAL checking status was not successful.
- */
-static uint32_t lpddr4_pollctlirq(const lpddr4_privatedata * pd,
- lpddr4_ctlinterrupt irqbit, uint32_t delay)
-{
-
- uint32_t result = 0U;
- uint32_t timeout = 0U;
- bool irqstatus = false;
-
- /* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
- do {
- if (++timeout == delay) {
- result = EIO;
- break;
- }
- /* cps_delayns(10000000U); */
- result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
- } while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
-
- return result;
-}
-
-/**
- * Internal Function:Poll for status of interrupt received by the PHY Independent Module.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] irqBit Interrupt status bit to be checked.
- * @param[in] delay time delay.
- * @return CDN_EOK on success (Interrupt status high).
- * @return EIO on poll time out.
- * @return EINVAL checking status was not successful.
- */
-static uint32_t lpddr4_pollphyindepirq(const lpddr4_privatedata * pd,
- lpddr4_phyindepinterrupt irqbit,
- uint32_t delay)
-{
-
- uint32_t result = 0U;
- uint32_t timeout = 0U;
- bool irqstatus = false;
-
- /* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
- do {
- if (++timeout == delay) {
- result = EIO;
- break;
- }
- /* cps_delayns(10000000U); */
- result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
- } while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
-
- return result;
-}
-
-/**
- * Internal Function:Trigger function to poll and Ack IRQs
- * @param[in] pD Driver state info specific to this instance.
- * @return CDN_EOK on success (Interrupt status high).
- * @return EIO on poll time out.
- * @return EINVAL checking status was not successful.
- */
-static uint32_t lpddr4_pollandackirq(const lpddr4_privatedata * pd)
-{
- uint32_t result = 0U;
-
- /* Wait for PhyIndependent module to finish up ctl init sequence */
- result =
- lpddr4_pollphyindepirq(pd, LPDDR4_PHY_INDEP_INIT_DONE_BIT,
- LPDDR4_CUSTOM_TIMEOUT_DELAY);
-
- /* Ack to clear the PhyIndependent interrupt bit */
- if (result == (uint32_t) CDN_EOK) {
- result =
- lpddr4_ackphyindepinterrupt(pd,
- LPDDR4_PHY_INDEP_INIT_DONE_BIT);
- }
- /* Wait for the CTL end of initialization */
- if (result == (uint32_t) CDN_EOK) {
- result =
- lpddr4_pollctlirq(pd, LPDDR4_MC_INIT_DONE,
- LPDDR4_CUSTOM_TIMEOUT_DELAY);
- }
- /* Ack to clear the Ctl interrupt bit */
- if (result == (uint32_t) CDN_EOK) {
- result = lpddr4_ackctlinterrupt(pd, LPDDR4_MC_INIT_DONE);
- }
- return result;
-}
-
-/**
- * Internal Function: Controller start sequence.
- * @param[in] pD Driver state info specific to this instance.
- * @return CDN_EOK on success.
- * @return EINVAL starting controller was not successful.
- */
-static uint32_t lpddr4_startsequencecontroller(const lpddr4_privatedata * pd)
-{
- uint32_t result = 0U;
- uint32_t regval = 0U;
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- lpddr4_infotype infotype;
-
- /* Set the PI_start to initiate leveling procedure */
- regval =
- CPS_FLD_SET(LPDDR4__PI_START__FLD,
- CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
- CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);
-
- /* Set the Ctl_start */
- regval =
- CPS_FLD_SET(LPDDR4__START__FLD,
- CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);
-
- if (pd->infohandler != NULL) {
- /* If a handler is registered, call it with the relevant information type */
- infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
- pd->infohandler(pd, infotype);
- }
-
- result = lpddr4_pollandackirq(pd);
-
- return result;
-}
-
-/**
- * Internal Function: To add the offset to given address.
- * @param[in] addr Address to which the offset has to be added.
- * @param[in] regOffset The offset
- * @return regAddr The address value after the summation.
- */
-static volatile uint32_t *lpddr4_addoffset(volatile uint32_t * addr,
- uint32_t regoffset)
-{
-
- volatile uint32_t *local_addr = addr;
- /* Declaring as array to add the offset value. */
- volatile uint32_t *regaddr = &local_addr[regoffset];
- return regaddr;
-}
-
-/**
- * Checks configuration object.
- * @param[in] config Driver/hardware configuration required.
- * @param[out] configSize Size of memory allocations required.
- * @return CDN_EOK on success (requirements structure filled).
- * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
- */
-uint32_t lpddr4_probe(const lpddr4_config * config, uint16_t * configsize)
-{
- uint32_t result;
-
- result = (uint32_t) (lpddr4_probesf(config, configsize));
- if (result == (uint32_t) CDN_EOK) {
- *configsize = (uint16_t) (sizeof(lpddr4_privatedata));
- }
- return result;
-}
-
-/**
- * Init function to be called after LPDDR4_probe() to set up the driver configuration.
- * Memory should be allocated for drv_data (using the size determined using LPDDR4_probe) before
- * calling this API, init_settings should be initialized with base addresses for PHY Independent Module,
- * Controller and PHY before calling this function.
- * If callbacks are required for interrupt handling, these should also be configured in init_settings.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cfg Specifies driver/hardware configuration.
- * @return CDN_EOK on success
- * @return EINVAL if illegal/inconsistent values in cfg.
- * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s)
- * required by 'config' parameters.
- */
-uint32_t lpddr4_init(lpddr4_privatedata * pd, const lpddr4_config * cfg)
-{
- uint32_t result = 0U;
- uint16_t productid = 0U;
-
- result = lpddr4_initsf(pd, cfg);
- if (result == (uint32_t) CDN_EOK) {
- /* Validate Magic number */
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) cfg->ctlbase;
- productid = (uint16_t) (CPS_FLD_READ(LPDDR4__CONTROLLER_ID__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__CONTROLLER_ID__REG))));
- if (productid == PRODUCT_ID) {
- /* Populating configuration data to pD */
- pd->ctlbase = ctlregbase;
- pd->infohandler =
- (lpddr4_infocallback) cfg->infohandler;
- pd->ctlinterrupthandler =
- (lpddr4_ctlcallback) cfg->ctlinterrupthandler;
- pd->phyindepinterrupthandler =
- (lpddr4_phyindepcallback) cfg->
- phyindepinterrupthandler;
- } else {
- /* Magic number validation failed - Driver doesn't support given IP version */
- result = (uint32_t) EOPNOTSUPP;
- }
- }
- return result;
-}
-
-/**
- * Start the driver.
- * @param[in] pD Driver state info specific to this instance.
- */
-uint32_t lpddr4_start(const lpddr4_privatedata * pd)
-{
- uint32_t result = 0U;
- uint32_t regval = 0U;
-
- result = lpddr4_startsf(pd);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Enable PI as the initiator for DRAM */
- regval =
- CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__PI_INIT_LVL_EN__REG)));
- regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
- CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)),
- regval);
-
- /* Start PI init sequence. */
- result = lpddr4_startsequencecontroller(pd);
- }
- return result;
-}
-
-/**
- * Read a register from the controller, PHY or PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[in] regOffset Register offset
- * @param[out] regValue Register value read
- * @return CDN_EOK on success.
- * @return EINVAL if regOffset if out of range or regValue is NULL
- */
-uint32_t lpddr4_readreg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
- uint32_t regoffset, uint32_t * regvalue)
-{
- uint32_t result = 0U;
-
- result = lpddr4_readregsf(pd, cpp, regvalue);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- if (cpp == LPDDR4_CTL_REGS) {
- if (regoffset >= LPDDR4_CTL_REG_COUNT) {
- /* Return if user provider invalid register number */
- result = EINVAL;
- } else {
- *regvalue =
- CPS_REG_READ(lpddr4_addoffset
- (&(ctlregbase->DENALI_CTL_0),
- regoffset));
- }
- } else if (cpp == LPDDR4_PHY_REGS) {
- if (regoffset >= LPDDR4_PHY_REG_COUNT) {
- /* Return if user provider invalid register number */
- result = EINVAL;
- } else {
- *regvalue =
- CPS_REG_READ(lpddr4_addoffset
- (&(ctlregbase->DENALI_PHY_0),
- regoffset));
- }
-
- } else {
- if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
- /* Return if user provider invalid register number */
- result = EINVAL;
- } else {
- *regvalue =
- CPS_REG_READ(lpddr4_addoffset
- (&(ctlregbase->DENALI_PI_0),
- regoffset));
- }
- }
- }
- return result;
-}
-
-uint32_t lpddr4_writereg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
- uint32_t regoffset, uint32_t regvalue)
-{
- uint32_t result = 0U;
-
- result = lpddr4_writeregsf(pd, cpp);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- if (cpp == LPDDR4_CTL_REGS) {
- if (regoffset >= LPDDR4_CTL_REG_COUNT) {
- /* Return if user provider invalid register number */
- result = EINVAL;
- } else {
- CPS_REG_WRITE(lpddr4_addoffset
- (&(ctlregbase->DENALI_CTL_0),
- regoffset), regvalue);
- }
- } else if (cpp == LPDDR4_PHY_REGS) {
- if (regoffset >= LPDDR4_PHY_REG_COUNT) {
- /* Return if user provider invalid register number */
- result = EINVAL;
- } else {
- CPS_REG_WRITE(lpddr4_addoffset
- (&(ctlregbase->DENALI_PHY_0),
- regoffset), regvalue);
- }
- } else {
- if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
- /* Return if user provider invalid register number */
- result = EINVAL;
- } else {
- CPS_REG_WRITE(lpddr4_addoffset
- (&(ctlregbase->DENALI_PI_0),
- regoffset), regvalue);
- }
- }
- }
-
- return result;
-}
-
-static uint32_t lpddr4_checkmmrreaderror(const lpddr4_privatedata * pd,
- uint64_t * mmrvalue,
- uint8_t * mrrstatus)
-{
-
- uint64_t lowerdata;
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- uint32_t result = (uint32_t) CDN_EOK;
-
- /* Check if mode register read error interrupt occurred */
- if (lpddr4_pollctlirq(pd, LPDDR4_MRR_ERROR, 100) == 0U) {
- /* Mode register read error interrupt, read MRR status register and return. */
- *mrrstatus =
- (uint8_t) CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__MRR_ERROR_STATUS__REG)));
- *mmrvalue = 0;
- result = EIO;
- } else {
- *mrrstatus = 0;
- /* Mode register read was successful, read DATA */
- lowerdata =
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
- *mmrvalue =
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
- *mmrvalue = (uint64_t) ((*mmrvalue << WORD_SHIFT) | lowerdata);
- /* Acknowledge MR_READ_DONE interrupt to clear it */
- result = lpddr4_ackctlinterrupt(pd, LPDDR4_MR_READ_DONE);
- }
- return result;
-}
-
-uint32_t lpddr4_getmmrregister(const lpddr4_privatedata * pd,
- uint32_t readmoderegval, uint64_t * mmrvalue,
- uint8_t * mmrstatus)
-{
-
- uint32_t result = 0U;
- uint32_t tdelay = 1000U;
- uint32_t regval = 0U;
-
- result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus);
- if (result == (uint32_t) CDN_EOK) {
-
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Populate the calculated value to the register */
- regval =
- CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__READ_MODEREG__REG)),
- readmoderegval);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval);
-
- /* Wait until the Read is done */
- result = lpddr4_pollctlirq(pd, LPDDR4_MR_READ_DONE, tdelay);
- }
- if (result == (uint32_t) CDN_EOK) {
- result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus);
- }
- return result;
-}
-
-static uint32_t lpddr4_writemmrregister(const lpddr4_privatedata * pd,
- uint32_t writemoderegval)
-{
-
- uint32_t result = (uint32_t) CDN_EOK;
- uint32_t tdelay = 1000U;
- uint32_t regval = 0U;
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Populate the calculated value to the register */
- regval =
- CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__WRITE_MODEREG__REG)),
- writemoderegval);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval);
-
- result = lpddr4_pollctlirq(pd, LPDDR4_MR_WRITE_DONE, tdelay);
-
- return result;
-}
-
-uint32_t lpddr4_setmmrregister(const lpddr4_privatedata * pd,
- uint32_t writemoderegval, uint8_t * mrwstatus)
-{
- uint32_t result = 0U;
-
- result = lpddr4_setmmrregistersf(pd, mrwstatus);
- if (result == (uint32_t) CDN_EOK) {
-
- /* Function call to trigger Mode register write */
- result = lpddr4_writemmrregister(pd, writemoderegval);
-
- if (result == (uint32_t) CDN_EOK) {
- result =
- lpddr4_ackctlinterrupt(pd, LPDDR4_MR_WRITE_DONE);
- }
- /* Read the status of mode register write */
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase =
- (lpddr4_ctlregs *) pd->ctlbase;
- *mrwstatus =
- (uint8_t) CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__MRW_STATUS__REG)));
- if ((*mrwstatus) != 0U) {
- result = EIO;
- }
- }
- }
-
- return result;
-}
-
-uint32_t lpddr4_writectlconfig(const lpddr4_privatedata * pd,
- const lpddr4_reginitdata * regvalues)
-{
- uint32_t result;
- uint32_t regnum;
-
- result = lpddr4_writectlconfigsf(pd, regvalues);
- if (result == (uint32_t) CDN_EOK) {
-
- /* Iterate through CTL register numbers. */
- for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
- /* Check if the user has requested update */
- if (regvalues->updatectlreg[regnum]) {
- result =
- lpddr4_writereg(pd, LPDDR4_CTL_REGS, regnum,
- (uint32_t) (regvalues->
- denalictlreg
- [regnum]));
- }
- }
- }
- return result;
-}
-
-uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata * pd,
- const lpddr4_reginitdata * regvalues)
-{
- uint32_t result;
- uint32_t regnum;
-
- result = lpddr4_writephyindepconfigsf(pd, regvalues);
- if (result == (uint32_t) CDN_EOK) {
-
- /* Iterate through PHY Independent module register numbers. */
- for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
- /* Check if the user has requested update */
- if (regvalues->updatephyindepreg[regnum]) {
- result =
- lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS,
- regnum,
- (uint32_t) (regvalues->
- denaliphyindepreg
- [regnum]));
- }
- }
- }
- return result;
-}
-
-uint32_t lpddr4_writephyconfig(const lpddr4_privatedata * pd,
- const lpddr4_reginitdata * regvalues)
-{
- uint32_t result;
- uint32_t regnum;
-
- result = lpddr4_writephyconfigsf(pd, regvalues);
- if (result == (uint32_t) CDN_EOK) {
-
- /* Iterate through PHY register numbers. */
- for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
- /* Check if the user has requested update */
- if (regvalues->updatephyreg[regnum]) {
- result =
- lpddr4_writereg(pd, LPDDR4_PHY_REGS, regnum,
- (uint32_t) (regvalues->
- denaliphyreg
- [regnum]));
- }
- }
- }
- return result;
-}
-
-uint32_t lpddr4_readctlconfig(const lpddr4_privatedata * pd,
- lpddr4_reginitdata * regvalues)
-{
- uint32_t result;
- uint32_t regnum;
- result = lpddr4_readctlconfigsf(pd, regvalues);
- if (result == (uint32_t) CDN_EOK) {
- /* Iterate through CTL register numbers. */
- for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
- /* Check if the user has requested read (updateCtlReg=1) */
- if (regvalues->updatectlreg[regnum]) {
- result =
- lpddr4_readreg(pd, LPDDR4_CTL_REGS, regnum,
- (uint32_t *) (®values->
- denalictlreg
- [regnum]));
- }
- }
- }
- return result;
-}
-
-uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata * pd,
- lpddr4_reginitdata * regvalues)
-{
- uint32_t result;
- uint32_t regnum;
-
- result = lpddr4_readphyindepconfigsf(pd, regvalues);
- if (result == (uint32_t) CDN_EOK) {
- /* Iterate through PHY Independent module register numbers. */
- for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
- /* Check if the user has requested read (updateCtlReg=1) */
- if (regvalues->updatephyindepreg[regnum]) {
- result =
- lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS,
- regnum,
- (uint32_t *) (®values->
- denaliphyindepreg
- [regnum]));
- }
- }
- }
- return result;
-}
-
-uint32_t lpddr4_readphyconfig(const lpddr4_privatedata * pd,
- lpddr4_reginitdata * regvalues)
-{
- uint32_t result;
- uint32_t regnum;
-
- result = lpddr4_readphyconfigsf(pd, regvalues);
- if (result == (uint32_t) CDN_EOK) {
- /* Iterate through PHY register numbers. */
- for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
- /* Check if the user has requested read (updateCtlReg=1) */
- if (regvalues->updatephyreg[regnum]) {
- result =
- lpddr4_readreg(pd, LPDDR4_PHY_REGS, regnum,
- (uint32_t *) (®values->
- denaliphyreg
- [regnum]));
- }
- }
- }
- return result;
-}
-
-uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata * pd,
- uint64_t * mask)
-{
- uint32_t result = 0U;
- uint64_t lowermask = 0U;
-
- result = lpddr4_getctlinterruptmasksf(pd, mask);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- /* Reading the lower mask register */
- lowermask =
- (uint64_t) (CPS_FLD_READ
- (LPDDR4__INT_MASK_0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__INT_MASK_0__REG))));
- /* Reading the upper mask register */
- *mask =
- (uint64_t) (CPS_FLD_READ
- (LPDDR4__INT_MASK_1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__INT_MASK_1__REG))));
- /* Concatenate both register informations */
- *mask = (uint64_t) ((*mask << WORD_SHIFT) | lowermask);
- }
- return result;
-}
-
-uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata * pd,
- const uint64_t * mask)
-{
- uint32_t result;
- uint32_t regval = 0;
- const uint64_t ui64one = 1ULL;
- const uint32_t ui32irqcount = (uint32_t) LPDDR4_LOR_BITS + 1U;
-
- result = lpddr4_setctlinterruptmasksf(pd, mask);
- if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < 64U)) {
- /* Return if the user given value is higher than the field width */
- if (*mask >= (ui64one << ui32irqcount)) {
- result = EINVAL;
- }
- }
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Extracting the lower 32 bits and writing to lower mask register */
- regval = (uint32_t) (*mask & WORD_MASK);
- regval =
- CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__INT_MASK_0__REG)),
- regval);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
-
- /* Extracting the upper 32 bits and writing to upper mask register */
- regval = (uint32_t) ((*mask >> WORD_SHIFT) & WORD_MASK);
- regval =
- CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__INT_MASK_1__REG)),
- regval);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
- }
- return result;
-}
-
-uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd,
- lpddr4_ctlinterrupt intr, bool * irqstatus)
-{
- uint32_t result;
- uint32_t ctlirqstatus = 0;
- uint32_t fieldshift = 0;
-
- /* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
- * Value of 'interrupt' should be less than 64 */
- result = lpddr4_checkctlinterruptsf(pd, intr, irqstatus);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- if ((uint32_t) intr >= WORD_SHIFT) {
- ctlirqstatus =
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__INT_STATUS_1__REG));
- /* Reduce the shift value as we are considering upper register */
- fieldshift = (uint32_t) intr - ((uint32_t) WORD_SHIFT);
- } else {
- ctlirqstatus =
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__INT_STATUS_0__REG));
- /* The shift value remains same for lower interrupt register */
- fieldshift = (uint32_t) intr;
- }
-
- /* MISRA compliance (Shifting operation) check */
- if (fieldshift < WORD_SHIFT) {
- if ((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) {
- *irqstatus = true;
- } else {
- *irqstatus = false;
- }
- }
- }
- return result;
-}
-
-uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd,
- lpddr4_ctlinterrupt intr)
-{
- uint32_t result = 0;
- uint32_t regval = 0;
- uint32_t localinterrupt = (uint32_t) intr;
-
- /* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
- * Value of 'interrupt' should be less than 64 */
- result = lpddr4_ackctlinterruptsf(pd, intr);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Check if the requested bit is in upper register */
- if (localinterrupt > WORD_SHIFT) {
- localinterrupt =
- (localinterrupt - (uint32_t) WORD_SHIFT);
- regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG),
- regval);
- } else {
- regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG),
- regval);
- }
- }
-
- return result;
-}
-
-uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata * pd,
- uint32_t * mask)
-{
- uint32_t result;
-
- result = lpddr4_getphyindepinterruptmsf(pd, mask);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- /* Reading mask register */
- *mask =
- CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__PI_INT_MASK__REG)));
- }
- return result;
-}
-
-uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata * pd,
- const uint32_t * mask)
-{
- uint32_t result;
- uint32_t regval = 0;
- const uint32_t ui32irqcount =
- (uint32_t) LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
-
- result = lpddr4_setphyindepinterruptmsf(pd, mask);
- if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < WORD_SHIFT)) {
- /* Return if the user given value is higher than the field width */
- if (*mask >= (1U << ui32irqcount)) {
- result = EINVAL;
- }
- }
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Writing to the user requested interrupt mask */
- regval =
- CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__PI_INT_MASK__REG)),
- *mask);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval);
- }
- return result;
-}
-
-uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd,
- lpddr4_phyindepinterrupt intr,
- bool * irqstatus)
-{
- uint32_t result = 0;
- uint32_t phyindepirqstatus = 0;
-
- result = lpddr4_checkphyindepinterrupsf(pd, intr, irqstatus);
- /* Confirming that the value of interrupt is less than register width */
- if ((result == (uint32_t) CDN_EOK) && ((uint32_t) intr < WORD_SHIFT)) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Reading the requested bit to check interrupt status */
- phyindepirqstatus =
- CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
- *irqstatus =
- !!((phyindepirqstatus >> (uint32_t)intr) & LPDDR4_BIT_MASK);
- }
- return result;
-}
-
-uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd,
- lpddr4_phyindepinterrupt intr)
-{
- uint32_t result = 0U;
- uint32_t regval = 0U;
- uint32_t ui32shiftinterrupt = (uint32_t) intr;
-
- result = lpddr4_ackphyindepinterruptsf(pd, intr);
- /* Confirming that the value of interrupt is less than register width */
- if ((result == (uint32_t) CDN_EOK) && (ui32shiftinterrupt < WORD_SHIFT)) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Write 1 to the requested bit to ACk the interrupt */
- regval = (uint32_t)LPDDR4_BIT_MASK << ui32shiftinterrupt;
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
- }
-
- return result;
-}
-
-/* Check for caTrainingError */
-static void lpddr4_checkcatrainingerror(lpddr4_ctlregs * ctlregbase,
- lpddr4_debuginfo * debuginfo,
- bool * errfoundptr)
-{
-
- uint32_t regval;
- uint32_t errbitmask = 0U;
- uint32_t snum;
- volatile uint32_t *regaddress;
-
- regaddress =
- (volatile uint32_t
- *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
- errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK);
- /* PHY_ADR_CALVL_OBS1[4] – Right found
- PHY_ADR_CALVL_OBS1[5] – left found
- both the above fields should be high and below field should be zero.
- PHY_ADR_CALVL_OBS1[3:0] – calvl_state
- */
- for (snum = 0U; snum < ASLICE_NUM; snum++) {
- regval = CPS_REG_READ(regaddress);
- if ((regval & errbitmask) != CA_TRAIN_RL) {
- debuginfo->catraingerror = true;
- *errfoundptr = true;
- }
- regaddress =
- lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
- }
-}
-
-/* Check for wrLvlError */
-static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase,
- lpddr4_debuginfo * debuginfo,
- bool * errfoundptr)
-{
-
- uint32_t regval;
- uint32_t errbitmask = 0U;
- uint32_t snum;
- volatile uint32_t *regaddress;
-
- regaddress =
- (volatile uint32_t
- *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
- /* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */
- errbitmask = (LPDDR4_BIT_MASK << 1) | LPDDR4_BIT_MASK;
- for (snum = 0U; snum < DSLICE_NUM; snum++) {
- regval = CPS_REG_READ(regaddress);
- if ((regval & errbitmask) != 0U) {
- debuginfo->wrlvlerror = true;
- *errfoundptr = true;
- }
- regaddress =
- lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
- }
-}
-
-/* Check for GateLvlError */
-static void lpddr4_checkgatelvlerror(lpddr4_ctlregs * ctlregbase,
- lpddr4_debuginfo * debuginfo,
- bool * errfoundptr)
-{
-
- uint32_t regval;
- uint32_t errbitmask = 0U;
- uint32_t snum;
- volatile uint32_t *regaddress;
-
- regaddress =
- (volatile uint32_t
- *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
- /* PHY_GTLVL_STATUS_OBS[6] – gate_level min error
- * PHY_GTLVL_STATUS_OBS[7] – gate_level max error
- * All the above bit fields should be zero */
- errbitmask = GATE_LVL_ERROR_FIELDS;
- for (snum = 0U; snum < DSLICE_NUM; snum++) {
- regval = CPS_REG_READ(regaddress);
- if ((regval & errbitmask) != 0U) {
- debuginfo->gatelvlerror = true;
- *errfoundptr = true;
- }
- regaddress =
- lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
- }
-}
-
-/* Check for ReadLvlError */
-static void lpddr4_checkreadlvlerror(lpddr4_ctlregs * ctlregbase,
- lpddr4_debuginfo * debuginfo,
- bool * errfoundptr)
-{
-
- uint32_t regval;
- uint32_t errbitmask = 0U;
- uint32_t snum;
- volatile uint32_t *regaddress;
-
- regaddress =
- (volatile uint32_t
- *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
- /* PHY_RDLVL_STATUS_OBS[23:16] – failed bits : should be zero.
- PHY_RDLVL_STATUS_OBS[31:28] – rdlvl_state : should be zero */
- errbitmask = READ_LVL_ERROR_FIELDS;
- for (snum = 0U; snum < DSLICE_NUM; snum++) {
- regval = CPS_REG_READ(regaddress);
- if ((regval & errbitmask) != 0U) {
- debuginfo->readlvlerror = true;
- *errfoundptr = true;
- }
- regaddress =
- lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
- }
-}
-
-/* Check for DqTrainingError */
-static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs * ctlregbase,
- lpddr4_debuginfo * debuginfo,
- bool * errfoundptr)
-{
-
- uint32_t regval;
- uint32_t errbitmask = 0U;
- uint32_t snum;
- volatile uint32_t *regaddress;
-
- regaddress =
- (volatile uint32_t
- *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
- /* PHY_WDQLVL_STATUS_OBS[26:18] should all be zero. */
- errbitmask = DQ_LVL_STATUS;
- for (snum = 0U; snum < DSLICE_NUM; snum++) {
- regval = CPS_REG_READ(regaddress);
- if ((regval & errbitmask) != 0U) {
- debuginfo->dqtrainingerror = true;
- *errfoundptr = true;
- }
- regaddress =
- lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
- }
-}
-
-/**
- * Internal Function:For checking errors in training/levelling sequence.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] debugInfo pointer to debug information.
- * @param[out] errFoundPtr pointer to return if error found.
- * @return CDN_EOK on success (Interrupt status high).
- * @return EINVAL checking or unmasking was not successful.
- */
-static bool lpddr4_checklvlerrors(const lpddr4_privatedata * pd,
- lpddr4_debuginfo * debuginfo, bool errfound)
-{
-
- bool localerrfound = errfound;
-
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- if (localerrfound == false) {
- /* Check for ca training error */
- lpddr4_checkcatrainingerror(ctlregbase, debuginfo,
- &localerrfound);
- }
-
- if (localerrfound == false) {
- /* Check for Write leveling error */
- lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound);
- }
-
- if (localerrfound == false) {
- /* Check for Gate leveling error */
- lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound);
- }
-
- if (localerrfound == false) {
- /* Check for Read leveling error */
- lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound);
- }
-
- if (localerrfound == false) {
- /* Check for DQ training error */
- lpddr4_checkdqtrainingerror(ctlregbase, debuginfo,
- &localerrfound);
- }
- return localerrfound;
-}
-
-static bool lpddr4_seterror(volatile uint32_t * reg, uint32_t errbitmask,
- bool * errfoundptr, const uint32_t errorinfobits)
-{
-
- uint32_t regval = 0U;
-
- /* Read the respective observation register */
- regval = CPS_REG_READ(reg);
- /* Compare the error bit values */
- if ((regval & errbitmask) != errorinfobits) {
- *errfoundptr = true;
- }
- return *errfoundptr;
-}
-
-static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase,
- lpddr4_debuginfo * debuginfo, bool * errfoundptr)
-{
-
- uint32_t errbitmask = (LPDDR4_BIT_MASK << 0x1U) | LPDDR4_BIT_MASK;
- /* Check PLL observation registers for PLL lock errors */
-
- debuginfo->pllerror =
- lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
- errbitmask, errfoundptr, PLL_READY);
- if (*errfoundptr == false) {
- debuginfo->pllerror =
- lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
- errbitmask, errfoundptr, PLL_READY);
- }
-
- /* Check for IO Calibration errors */
- if (*errfoundptr == false) {
- debuginfo->iocaliberror =
- lpddr4_seterror(&
- (ctlregbase->
- LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
- IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
- }
- if (*errfoundptr == false) {
- debuginfo->iocaliberror =
- lpddr4_seterror(&
- (ctlregbase->
- LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
- IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
- }
- if (*errfoundptr == false) {
- debuginfo->iocaliberror =
- lpddr4_seterror(&
- (ctlregbase->
- LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
- IO_CALIB_FIELD, errfoundptr,
- IO_CALIB_STATE);
- }
-}
-
-static void lpddr4_setphysnapsettings(lpddr4_ctlregs * ctlregbase,
- const bool errorfound)
-{
-
- uint32_t snum = 0U;
- volatile uint32_t *regaddress;
- uint32_t regval = 0U;
-
- /* Setting SC_PHY_SNAP_OBS_REGS_x to get a snapshot */
- if (errorfound == false) {
- regaddress =
- (volatile uint32_t
- *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
- /* Iterate through each PHY Data Slice */
- for (snum = 0U; snum < DSLICE_NUM; snum++) {
- regval =
- CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD,
- CPS_REG_READ(regaddress));
- CPS_REG_WRITE(regaddress, regval);
- regaddress =
- lpddr4_addoffset(regaddress,
- (uint32_t) SLICE_WIDTH);
- }
- }
-}
-
-static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs * ctlregbase,
- const bool errorfound)
-{
-
- uint32_t snum = 0U;
- volatile uint32_t *regaddress;
- uint32_t regval = 0U;
-
- /* Setting SC_PHY ADR_SNAP_OBS_REGS_x to get a snapshot */
- if (errorfound == false) {
- regaddress =
- (volatile uint32_t
- *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
- /* Iterate through each PHY Address Slice */
- for (snum = 0U; snum < ASLICE_NUM; snum++) {
- regval =
- CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD,
- CPS_REG_READ(regaddress));
- CPS_REG_WRITE(regaddress, regval);
- regaddress =
- lpddr4_addoffset(regaddress,
- (uint32_t) SLICE_WIDTH);
- }
- }
-}
-
-static void lpddr4_setsettings(lpddr4_ctlregs * ctlregbase,
- const bool errorfound)
-{
-
- /* Calling functions to enable snap shots of OBS registers */
- lpddr4_setphysnapsettings(ctlregbase, errorfound);
- lpddr4_setphyadrsnapsettings(ctlregbase, errorfound);
-}
-
-static void lpddr4_setrxoffseterror(lpddr4_ctlregs * ctlregbase,
- lpddr4_debuginfo * debuginfo,
- bool * errorfound)
-{
-
- volatile uint32_t *regaddress;
- uint32_t snum = 0U;
- uint32_t errbitmask = 0U;
- uint32_t regval = 0U;
-
- /* Check for rxOffsetError */
- if (*errorfound == false) {
- regaddress =
- (volatile uint32_t
- *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
- errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
- /* PHY_RX_CAL_LOCK_OBS_x[4] – RX_CAL_DONE : should be high
- phy_rx_cal_lock_obs_x[3:0] – RX_CAL_STATE : should be zero. */
- for (snum = 0U; snum < DSLICE_NUM; snum++) {
- regval =
- CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD,
- CPS_REG_READ(regaddress));
- if ((regval & errbitmask) != RX_CAL_DONE) {
- debuginfo->rxoffseterror = true;
- *errorfound = true;
- }
- regaddress =
- lpddr4_addoffset(regaddress,
- (uint32_t) SLICE_WIDTH);
- }
- }
-}
-
-uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata * pd,
- lpddr4_debuginfo * debuginfo)
-{
-
- uint32_t result = 0U;
- bool errorfound = false;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_getdebuginitinfosf(pd, debuginfo);
- if (result == (uint32_t) CDN_EOK) {
-
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- lpddr4_seterrors(ctlregbase, debuginfo, &errorfound);
- /* Function to setup Snap for OBS registers */
- lpddr4_setsettings(ctlregbase, errorfound);
- /* Function to check for Rx offset error */
- lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
- /* Function Check various levelling errors */
- errorfound = lpddr4_checklvlerrors(pd, debuginfo, errorfound);
- }
-
- if (errorfound == true) {
- result = (uint32_t) EPROTO;
- }
-
- return result;
-}
-
-static void readpdwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
- /* Read the appropriate register, based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_PD_WAKEUP_F0__REG)));
- } else if (*fspnum == LPDDR4_FSP_1) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_PD_WAKEUP_F1__REG)));
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_PD_WAKEUP_F2__REG)));
- }
-}
-
-static void readsrshortwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
- /* Read the appropriate register, based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
- } else if (*fspnum == LPDDR4_FSP_1) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
- }
-}
-
-static void readsrlongwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
- /* Read the appropriate register, based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
- } else if (*fspnum == LPDDR4_FSP_1) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
- }
-}
-
-static void readsrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
- /* Read the appropriate register, based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
- } else if (*fspnum == LPDDR4_FSP_1) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
- }
-}
-
-static void readsrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
- /* Read the appropriate register, based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
- } else if (*fspnum == LPDDR4_FSP_1) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
- }
-}
-
-static void readsrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
-{
-
- /* Read the appropriate register, based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
- } else if (*fspnum == LPDDR4_FSP_1) {
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- *cycles =
- CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
- }
-}
-
-static void readsrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase,
- uint32_t * cycles)
-{
-
- /* Read the appropriate register, based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- *cycles =
- CPS_FLD_READ
- (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
- } else if (*fspnum == LPDDR4_FSP_1) {
- *cycles =
- CPS_FLD_READ
- (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- *cycles =
- CPS_FLD_READ
- (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
- }
-
-}
-
-static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs * ctlregbase,
- const lpddr4_lpiwakeupparam *
- lpiwakeupparam,
- const lpddr4_ctlfspnum * fspnum,
- uint32_t * cycles)
-{
-
- /* Iterate through each of the Wake up parameter type */
- if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
- /* Calling appropriate function for register read */
- readpdwakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
- readsrshortwakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
- readsrlongwakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
- readsrlonggatewakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
- readsrdpshortwakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
- readsrdplongwakeup(fspnum, ctlregbase, cycles);
- } else {
- /* Default function (sanity function already confirmed the variable value) */
- readsrdplonggatewakeup(fspnum, ctlregbase, cycles);
- }
-}
-
-uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata * pd,
- const lpddr4_lpiwakeupparam * lpiwakeupparam,
- const lpddr4_ctlfspnum * fspnum,
- uint32_t * cycles)
-{
-
- uint32_t result = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
- cycles);
- }
- return result;
-}
-
-static void writepdwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase, const uint32_t * cycles)
-{
-
- uint32_t regval = 0U;
- /* Write to appropriate register ,based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_PD_WAKEUP_F0__REG)),
- *cycles);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG),
- regval);
- } else if (*fspnum == LPDDR4_FSP_1) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_PD_WAKEUP_F1__REG)),
- *cycles);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG),
- regval);
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_PD_WAKEUP_F2__REG)),
- *cycles);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG),
- regval);
- }
-}
-
-static void writesrshortwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase,
- const uint32_t * cycles)
-{
-
- uint32_t regval = 0U;
- /* Write to appropriate register ,based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG),
- regval);
- } else if (*fspnum == LPDDR4_FSP_1) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG),
- regval);
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG),
- regval);
- }
-}
-
-static void writesrlongwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase,
- const uint32_t * cycles)
-{
-
- uint32_t regval = 0U;
- /* Write to appropriate register ,based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)),
- *cycles);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG),
- regval);
- } else if (*fspnum == LPDDR4_FSP_1) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)),
- *cycles);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG),
- regval);
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)),
- *cycles);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG),
- regval);
- }
-}
-
-static void writesrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase,
- const uint32_t * cycles)
-{
-
- uint32_t regval = 0U;
- /* Write to appropriate register ,based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG),
- regval);
- } else if (*fspnum == LPDDR4_FSP_1) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG),
- regval);
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG),
- regval);
- }
-}
-
-static void writesrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase,
- const uint32_t * cycles)
-{
-
- uint32_t regval = 0U;
- /* Write to appropriate register ,based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
- } else if (*fspnum == LPDDR4_FSP_1) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
- }
-}
-
-static void writesrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase,
- const uint32_t * cycles)
-{
-
- uint32_t regval = 0U;
- /* Write to appropriate register ,based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
- } else if (*fspnum == LPDDR4_FSP_1) {
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- regval =
- CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
- }
-}
-
-static void writesrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
- lpddr4_ctlregs * ctlregbase,
- const uint32_t * cycles)
-{
-
- uint32_t regval = 0U;
- /* Write to appropriate register ,based on user given frequency. */
- if (*fspnum == LPDDR4_FSP_0) {
- regval =
- CPS_FLD_WRITE
- (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG),
- regval);
- } else if (*fspnum == LPDDR4_FSP_1) {
- regval =
- CPS_FLD_WRITE
- (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG),
- regval);
- } else {
- /* Default register (sanity function already confirmed the variable value) */
- regval =
- CPS_FLD_WRITE
- (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
- *cycles);
- CPS_REG_WRITE(&
- (ctlregbase->
- LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG),
- regval);
- }
-}
-
-static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs * ctlregbase,
- const lpddr4_lpiwakeupparam *
- lpiwakeupparam,
- const lpddr4_ctlfspnum * fspnum,
- const uint32_t * cycles)
-{
-
- /* Iterate through each of the Wake up parameter type */
- if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
- /* Calling appropriate function for register write */
- writepdwakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
- writesrshortwakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
- writesrlongwakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
- writesrlonggatewakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
- writesrdpshortwakeup(fspnum, ctlregbase, cycles);
- } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
- writesrdplongwakeup(fspnum, ctlregbase, cycles);
- } else {
- /* Default function (sanity function already confirmed the variable value) */
- writesrdplonggatewakeup(fspnum, ctlregbase, cycles);
- }
-}
-
-uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata * pd,
- const lpddr4_lpiwakeupparam * lpiwakeupparam,
- const lpddr4_ctlfspnum * fspnum,
- const uint32_t * cycles)
-{
- uint32_t result = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
- if (result == (uint32_t) CDN_EOK) {
- /* Return if the user given value is higher than the field width */
- if (*cycles > NIBBLE_MASK) {
- result = EINVAL;
- }
- }
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
- cycles);
- }
- return result;
-}
-
-uint32_t lpddr4_geteccenable(const lpddr4_privatedata * pd,
- lpddr4_eccenable * eccparam)
-{
- uint32_t result = 0U;
- uint32_t fldval = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_geteccenablesf(pd, eccparam);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Reading the ECC_Enable field from the register. */
- fldval =
- CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__ECC_ENABLE__REG)));
- switch (fldval) {
- case 3:
- *eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
- break;
- case 2:
- *eccparam = LPDDR4_ECC_ERR_DETECT;
- break;
- case 1:
- *eccparam = LPDDR4_ECC_ENABLED;
- break;
- default:
- /* Default ECC (Sanity function already confirmed the value to be in expected range.) */
- *eccparam = LPDDR4_ECC_DISABLED;
- break;
- }
- }
- return result;
-}
-
-uint32_t lpddr4_seteccenable(const lpddr4_privatedata * pd,
- const lpddr4_eccenable * eccparam)
-{
-
- uint32_t result = 0U;
- uint32_t regval = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_seteccenablesf(pd, eccparam);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Updating the ECC_Enable field based on the user given value. */
- regval =
- CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__ECC_ENABLE__REG)),
- *eccparam);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
- }
- return result;
-}
-
-uint32_t lpddr4_getreducmode(const lpddr4_privatedata * pd,
- lpddr4_reducmode * mode)
-{
- uint32_t result = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_getreducmodesf(pd, mode);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- /* Read the value of reduc parameter. */
- if (CPS_FLD_READ
- (LPDDR4__REDUC__FLD,
- CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U) {
- *mode = LPDDR4_REDUC_ON;
- } else {
- *mode = LPDDR4_REDUC_OFF;
- }
- }
- return result;
-}
-
-uint32_t lpddr4_setreducmode(const lpddr4_privatedata * pd,
- const lpddr4_reducmode * mode)
-{
- uint32_t result = 0U;
- uint32_t regval = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_setreducmodesf(pd, mode);
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- /* Setting to enable Half data path. */
- regval =
- CPS_FLD_WRITE(LPDDR4__REDUC__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__REDUC__REG)), *mode);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
- }
- return result;
-}
-
-uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata * pd, bool * on_off)
-{
-
- uint32_t result = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_getdbireadmodesf(pd, on_off);
-
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- /* Reading the field value from the register. */
- if (CPS_FLD_READ
- (LPDDR4__RD_DBI_EN__FLD,
- CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) ==
- 0U) {
- *on_off = false;
- } else {
- *on_off = true;
- }
- }
- return result;
-}
-
-uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata * pd, bool * on_off)
-{
-
- uint32_t result = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_getdbireadmodesf(pd, on_off);
-
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- /* Reading the field value from the register. */
- if (CPS_FLD_READ
- (LPDDR4__WR_DBI_EN__FLD,
- CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) ==
- 0U) {
- *on_off = false;
- } else {
- *on_off = true;
- }
- }
- return result;
-}
-
-uint32_t lpddr4_setdbimode(const lpddr4_privatedata * pd,
- const lpddr4_dbimode * mode)
-{
-
- uint32_t result = 0U;
- uint32_t regval = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_setdbimodesf(pd, mode);
-
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Updating the appropriate field value based on the user given mode */
- if (*mode == LPDDR4_DBI_RD_ON) {
- regval =
- CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__RD_DBI_EN__REG)),
- 1U);
- } else if (*mode == LPDDR4_DBI_RD_OFF) {
- regval =
- CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__RD_DBI_EN__REG)),
- 0U);
- } else if (*mode == LPDDR4_DBI_WR_ON) {
- regval =
- CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__WR_DBI_EN__REG)),
- 1U);
- } else {
- /* Default field (Sanity function already confirmed the value to be in expected range.) */
- regval =
- CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__WR_DBI_EN__REG)),
- 0U);
- }
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval);
- }
- return result;
-}
-
-uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata * pd,
- const lpddr4_ctlfspnum * fspnum,
- uint32_t * cycles)
-{
- uint32_t result = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_getrefreshratesf(pd, fspnum, cycles);
-
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Selecting the appropriate register for the user requested Frequency */
- switch (*fspnum) {
- case LPDDR4_FSP_2:
- *cycles =
- CPS_FLD_READ(LPDDR4__TREF_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__TREF_F2__REG)));
- break;
- case LPDDR4_FSP_1:
- *cycles =
- CPS_FLD_READ(LPDDR4__TREF_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__TREF_F1__REG)));
- break;
- default:
- /* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
- *cycles =
- CPS_FLD_READ(LPDDR4__TREF_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__TREF_F0__REG)));
- break;
- }
- }
- return result;
-}
-
-uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata * pd,
- const lpddr4_ctlfspnum * fspnum,
- const uint32_t * cycles)
-{
- uint32_t result = 0U;
- uint32_t regval = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_setrefreshratesf(pd, fspnum, cycles);
-
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
-
- /* Selecting the appropriate register for the user requested Frequency */
- switch (*fspnum) {
- case LPDDR4_FSP_2:
- regval =
- CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__TREF_F2__REG)),
- *cycles);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG),
- regval);
- break;
- case LPDDR4_FSP_1:
- regval =
- CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__TREF_F1__REG)),
- *cycles);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG),
- regval);
- break;
- default:
- /* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
- regval =
- CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__TREF_F0__REG)),
- *cycles);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG),
- regval);
- break;
- }
- }
- return result;
-}
-
-uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata * pd,
- const uint32_t trefinterval)
-{
- uint32_t result = 0U;
- uint32_t regval = 0U;
-
- /* Calling Sanity Function to verify the input variables */
- result = lpddr4_refreshperchipselectsf(pd);
-
- if (result == (uint32_t) CDN_EOK) {
- lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
- /* Setting tref_interval parameter to enable/disable Refresh per chip select. */
- regval =
- CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD,
- CPS_REG_READ(&
- (ctlregbase->
- LPDDR4__TREF_INTERVAL__REG)),
- trefinterval);
- CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG),
- regval);
- }
- return result;
-}
diff --git a/drivers/ram/k3-j721e/lpddr4_ctl_regs.h b/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
deleted file mode 100644
index 213e569..0000000
--- a/drivers/ram/k3-j721e/lpddr4_ctl_regs.h
+++ /dev/null
@@ -1,1546 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
- */
-
-#ifndef REG_LPDDR4_CTL_REGS_H_
-#define REG_LPDDR4_CTL_REGS_H_
-
-#include "lpddr4_ddr_controller_macros.h"
-#include "lpddr4_pi_macros.h"
-#include "lpddr4_data_slice_0_macros.h"
-#include "lpddr4_data_slice_1_macros.h"
-#include "lpddr4_data_slice_2_macros.h"
-#include "lpddr4_data_slice_3_macros.h"
-#include "lpddr4_address_slice_0_macros.h"
-#include "lpddr4_phy_core_macros.h"
-
-typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
- volatile uint32_t DENALI_CTL_0;
- volatile uint32_t DENALI_CTL_1;
- volatile uint32_t DENALI_CTL_2;
- volatile uint32_t DENALI_CTL_3;
- volatile uint32_t DENALI_CTL_4;
- volatile uint32_t DENALI_CTL_5;
- volatile uint32_t DENALI_CTL_6;
- volatile uint32_t DENALI_CTL_7;
- volatile uint32_t DENALI_CTL_8;
- volatile uint32_t DENALI_CTL_9;
- volatile uint32_t DENALI_CTL_10;
- volatile uint32_t DENALI_CTL_11;
- volatile uint32_t DENALI_CTL_12;
- volatile uint32_t DENALI_CTL_13;
- volatile uint32_t DENALI_CTL_14;
- volatile uint32_t DENALI_CTL_15;
- volatile uint32_t DENALI_CTL_16;
- volatile uint32_t DENALI_CTL_17;
- volatile uint32_t DENALI_CTL_18;
- volatile uint32_t DENALI_CTL_19;
- volatile uint32_t DENALI_CTL_20;
- volatile uint32_t DENALI_CTL_21;
- volatile uint32_t DENALI_CTL_22;
- volatile uint32_t DENALI_CTL_23;
- volatile uint32_t DENALI_CTL_24;
- volatile uint32_t DENALI_CTL_25;
- volatile uint32_t DENALI_CTL_26;
- volatile uint32_t DENALI_CTL_27;
- volatile uint32_t DENALI_CTL_28;
- volatile uint32_t DENALI_CTL_29;
- volatile uint32_t DENALI_CTL_30;
- volatile uint32_t DENALI_CTL_31;
- volatile uint32_t DENALI_CTL_32;
- volatile uint32_t DENALI_CTL_33;
- volatile uint32_t DENALI_CTL_34;
- volatile uint32_t DENALI_CTL_35;
- volatile uint32_t DENALI_CTL_36;
- volatile uint32_t DENALI_CTL_37;
- volatile uint32_t DENALI_CTL_38;
- volatile uint32_t DENALI_CTL_39;
- volatile uint32_t DENALI_CTL_40;
- volatile uint32_t DENALI_CTL_41;
- volatile uint32_t DENALI_CTL_42;
- volatile uint32_t DENALI_CTL_43;
- volatile uint32_t DENALI_CTL_44;
- volatile uint32_t DENALI_CTL_45;
- volatile uint32_t DENALI_CTL_46;
- volatile uint32_t DENALI_CTL_47;
- volatile uint32_t DENALI_CTL_48;
- volatile uint32_t DENALI_CTL_49;
- volatile uint32_t DENALI_CTL_50;
- volatile uint32_t DENALI_CTL_51;
- volatile uint32_t DENALI_CTL_52;
- volatile uint32_t DENALI_CTL_53;
- volatile uint32_t DENALI_CTL_54;
- volatile uint32_t DENALI_CTL_55;
- volatile uint32_t DENALI_CTL_56;
- volatile uint32_t DENALI_CTL_57;
- volatile uint32_t DENALI_CTL_58;
- volatile uint32_t DENALI_CTL_59;
- volatile uint32_t DENALI_CTL_60;
- volatile uint32_t DENALI_CTL_61;
- volatile uint32_t DENALI_CTL_62;
- volatile uint32_t DENALI_CTL_63;
- volatile uint32_t DENALI_CTL_64;
- volatile uint32_t DENALI_CTL_65;
- volatile uint32_t DENALI_CTL_66;
- volatile uint32_t DENALI_CTL_67;
- volatile uint32_t DENALI_CTL_68;
- volatile uint32_t DENALI_CTL_69;
- volatile uint32_t DENALI_CTL_70;
- volatile uint32_t DENALI_CTL_71;
- volatile uint32_t DENALI_CTL_72;
- volatile uint32_t DENALI_CTL_73;
- volatile uint32_t DENALI_CTL_74;
- volatile uint32_t DENALI_CTL_75;
- volatile uint32_t DENALI_CTL_76;
- volatile uint32_t DENALI_CTL_77;
- volatile uint32_t DENALI_CTL_78;
- volatile uint32_t DENALI_CTL_79;
- volatile uint32_t DENALI_CTL_80;
- volatile uint32_t DENALI_CTL_81;
- volatile uint32_t DENALI_CTL_82;
- volatile uint32_t DENALI_CTL_83;
- volatile uint32_t DENALI_CTL_84;
- volatile uint32_t DENALI_CTL_85;
- volatile uint32_t DENALI_CTL_86;
- volatile uint32_t DENALI_CTL_87;
- volatile uint32_t DENALI_CTL_88;
- volatile uint32_t DENALI_CTL_89;
- volatile uint32_t DENALI_CTL_90;
- volatile uint32_t DENALI_CTL_91;
- volatile uint32_t DENALI_CTL_92;
- volatile uint32_t DENALI_CTL_93;
- volatile uint32_t DENALI_CTL_94;
- volatile uint32_t DENALI_CTL_95;
- volatile uint32_t DENALI_CTL_96;
- volatile uint32_t DENALI_CTL_97;
- volatile uint32_t DENALI_CTL_98;
- volatile uint32_t DENALI_CTL_99;
- volatile uint32_t DENALI_CTL_100;
- volatile uint32_t DENALI_CTL_101;
- volatile uint32_t DENALI_CTL_102;
- volatile uint32_t DENALI_CTL_103;
- volatile uint32_t DENALI_CTL_104;
- volatile uint32_t DENALI_CTL_105;
- volatile uint32_t DENALI_CTL_106;
- volatile uint32_t DENALI_CTL_107;
- volatile uint32_t DENALI_CTL_108;
- volatile uint32_t DENALI_CTL_109;
- volatile uint32_t DENALI_CTL_110;
- volatile uint32_t DENALI_CTL_111;
- volatile uint32_t DENALI_CTL_112;
- volatile uint32_t DENALI_CTL_113;
- volatile uint32_t DENALI_CTL_114;
- volatile uint32_t DENALI_CTL_115;
- volatile uint32_t DENALI_CTL_116;
- volatile uint32_t DENALI_CTL_117;
- volatile uint32_t DENALI_CTL_118;
- volatile uint32_t DENALI_CTL_119;
- volatile uint32_t DENALI_CTL_120;
- volatile uint32_t DENALI_CTL_121;
- volatile uint32_t DENALI_CTL_122;
- volatile uint32_t DENALI_CTL_123;
- volatile uint32_t DENALI_CTL_124;
- volatile uint32_t DENALI_CTL_125;
- volatile uint32_t DENALI_CTL_126;
- volatile uint32_t DENALI_CTL_127;
- volatile uint32_t DENALI_CTL_128;
- volatile uint32_t DENALI_CTL_129;
- volatile uint32_t DENALI_CTL_130;
- volatile uint32_t DENALI_CTL_131;
- volatile uint32_t DENALI_CTL_132;
- volatile uint32_t DENALI_CTL_133;
- volatile uint32_t DENALI_CTL_134;
- volatile uint32_t DENALI_CTL_135;
- volatile uint32_t DENALI_CTL_136;
- volatile uint32_t DENALI_CTL_137;
- volatile uint32_t DENALI_CTL_138;
- volatile uint32_t DENALI_CTL_139;
- volatile uint32_t DENALI_CTL_140;
- volatile uint32_t DENALI_CTL_141;
- volatile uint32_t DENALI_CTL_142;
- volatile uint32_t DENALI_CTL_143;
- volatile uint32_t DENALI_CTL_144;
- volatile uint32_t DENALI_CTL_145;
- volatile uint32_t DENALI_CTL_146;
- volatile uint32_t DENALI_CTL_147;
- volatile uint32_t DENALI_CTL_148;
- volatile uint32_t DENALI_CTL_149;
- volatile uint32_t DENALI_CTL_150;
- volatile uint32_t DENALI_CTL_151;
- volatile uint32_t DENALI_CTL_152;
- volatile uint32_t DENALI_CTL_153;
- volatile uint32_t DENALI_CTL_154;
- volatile uint32_t DENALI_CTL_155;
- volatile uint32_t DENALI_CTL_156;
- volatile uint32_t DENALI_CTL_157;
- volatile uint32_t DENALI_CTL_158;
- volatile uint32_t DENALI_CTL_159;
- volatile uint32_t DENALI_CTL_160;
- volatile uint32_t DENALI_CTL_161;
- volatile uint32_t DENALI_CTL_162;
- volatile uint32_t DENALI_CTL_163;
- volatile uint32_t DENALI_CTL_164;
- volatile uint32_t DENALI_CTL_165;
- volatile uint32_t DENALI_CTL_166;
- volatile uint32_t DENALI_CTL_167;
- volatile uint32_t DENALI_CTL_168;
- volatile uint32_t DENALI_CTL_169;
- volatile uint32_t DENALI_CTL_170;
- volatile uint32_t DENALI_CTL_171;
- volatile uint32_t DENALI_CTL_172;
- volatile uint32_t DENALI_CTL_173;
- volatile uint32_t DENALI_CTL_174;
- volatile uint32_t DENALI_CTL_175;
- volatile uint32_t DENALI_CTL_176;
- volatile uint32_t DENALI_CTL_177;
- volatile uint32_t DENALI_CTL_178;
- volatile uint32_t DENALI_CTL_179;
- volatile uint32_t DENALI_CTL_180;
- volatile uint32_t DENALI_CTL_181;
- volatile uint32_t DENALI_CTL_182;
- volatile uint32_t DENALI_CTL_183;
- volatile uint32_t DENALI_CTL_184;
- volatile uint32_t DENALI_CTL_185;
- volatile uint32_t DENALI_CTL_186;
- volatile uint32_t DENALI_CTL_187;
- volatile uint32_t DENALI_CTL_188;
- volatile uint32_t DENALI_CTL_189;
- volatile uint32_t DENALI_CTL_190;
- volatile uint32_t DENALI_CTL_191;
- volatile uint32_t DENALI_CTL_192;
- volatile uint32_t DENALI_CTL_193;
- volatile uint32_t DENALI_CTL_194;
- volatile uint32_t DENALI_CTL_195;
- volatile uint32_t DENALI_CTL_196;
- volatile uint32_t DENALI_CTL_197;
- volatile uint32_t DENALI_CTL_198;
- volatile uint32_t DENALI_CTL_199;
- volatile uint32_t DENALI_CTL_200;
- volatile uint32_t DENALI_CTL_201;
- volatile uint32_t DENALI_CTL_202;
- volatile uint32_t DENALI_CTL_203;
- volatile uint32_t DENALI_CTL_204;
- volatile uint32_t DENALI_CTL_205;
- volatile uint32_t DENALI_CTL_206;
- volatile uint32_t DENALI_CTL_207;
- volatile uint32_t DENALI_CTL_208;
- volatile uint32_t DENALI_CTL_209;
- volatile uint32_t DENALI_CTL_210;
- volatile uint32_t DENALI_CTL_211;
- volatile uint32_t DENALI_CTL_212;
- volatile uint32_t DENALI_CTL_213;
- volatile uint32_t DENALI_CTL_214;
- volatile uint32_t DENALI_CTL_215;
- volatile uint32_t DENALI_CTL_216;
- volatile uint32_t DENALI_CTL_217;
- volatile uint32_t DENALI_CTL_218;
- volatile uint32_t DENALI_CTL_219;
- volatile uint32_t DENALI_CTL_220;
- volatile uint32_t DENALI_CTL_221;
- volatile uint32_t DENALI_CTL_222;
- volatile uint32_t DENALI_CTL_223;
- volatile uint32_t DENALI_CTL_224;
- volatile uint32_t DENALI_CTL_225;
- volatile uint32_t DENALI_CTL_226;
- volatile uint32_t DENALI_CTL_227;
- volatile uint32_t DENALI_CTL_228;
- volatile uint32_t DENALI_CTL_229;
- volatile uint32_t DENALI_CTL_230;
- volatile uint32_t DENALI_CTL_231;
- volatile uint32_t DENALI_CTL_232;
- volatile uint32_t DENALI_CTL_233;
- volatile uint32_t DENALI_CTL_234;
- volatile uint32_t DENALI_CTL_235;
- volatile uint32_t DENALI_CTL_236;
- volatile uint32_t DENALI_CTL_237;
- volatile uint32_t DENALI_CTL_238;
- volatile uint32_t DENALI_CTL_239;
- volatile uint32_t DENALI_CTL_240;
- volatile uint32_t DENALI_CTL_241;
- volatile uint32_t DENALI_CTL_242;
- volatile uint32_t DENALI_CTL_243;
- volatile uint32_t DENALI_CTL_244;
- volatile uint32_t DENALI_CTL_245;
- volatile uint32_t DENALI_CTL_246;
- volatile uint32_t DENALI_CTL_247;
- volatile uint32_t DENALI_CTL_248;
- volatile uint32_t DENALI_CTL_249;
- volatile uint32_t DENALI_CTL_250;
- volatile uint32_t DENALI_CTL_251;
- volatile uint32_t DENALI_CTL_252;
- volatile uint32_t DENALI_CTL_253;
- volatile uint32_t DENALI_CTL_254;
- volatile uint32_t DENALI_CTL_255;
- volatile uint32_t DENALI_CTL_256;
- volatile uint32_t DENALI_CTL_257;
- volatile uint32_t DENALI_CTL_258;
- volatile uint32_t DENALI_CTL_259;
- volatile uint32_t DENALI_CTL_260;
- volatile uint32_t DENALI_CTL_261;
- volatile uint32_t DENALI_CTL_262;
- volatile uint32_t DENALI_CTL_263;
- volatile uint32_t DENALI_CTL_264;
- volatile uint32_t DENALI_CTL_265;
- volatile uint32_t DENALI_CTL_266;
- volatile uint32_t DENALI_CTL_267;
- volatile uint32_t DENALI_CTL_268;
- volatile uint32_t DENALI_CTL_269;
- volatile uint32_t DENALI_CTL_270;
- volatile uint32_t DENALI_CTL_271;
- volatile uint32_t DENALI_CTL_272;
- volatile uint32_t DENALI_CTL_273;
- volatile uint32_t DENALI_CTL_274;
- volatile uint32_t DENALI_CTL_275;
- volatile uint32_t DENALI_CTL_276;
- volatile uint32_t DENALI_CTL_277;
- volatile uint32_t DENALI_CTL_278;
- volatile uint32_t DENALI_CTL_279;
- volatile uint32_t DENALI_CTL_280;
- volatile uint32_t DENALI_CTL_281;
- volatile uint32_t DENALI_CTL_282;
- volatile uint32_t DENALI_CTL_283;
- volatile uint32_t DENALI_CTL_284;
- volatile uint32_t DENALI_CTL_285;
- volatile uint32_t DENALI_CTL_286;
- volatile uint32_t DENALI_CTL_287;
- volatile uint32_t DENALI_CTL_288;
- volatile uint32_t DENALI_CTL_289;
- volatile uint32_t DENALI_CTL_290;
- volatile uint32_t DENALI_CTL_291;
- volatile uint32_t DENALI_CTL_292;
- volatile uint32_t DENALI_CTL_293;
- volatile uint32_t DENALI_CTL_294;
- volatile uint32_t DENALI_CTL_295;
- volatile uint32_t DENALI_CTL_296;
- volatile uint32_t DENALI_CTL_297;
- volatile uint32_t DENALI_CTL_298;
- volatile uint32_t DENALI_CTL_299;
- volatile uint32_t DENALI_CTL_300;
- volatile uint32_t DENALI_CTL_301;
- volatile uint32_t DENALI_CTL_302;
- volatile uint32_t DENALI_CTL_303;
- volatile uint32_t DENALI_CTL_304;
- volatile uint32_t DENALI_CTL_305;
- volatile uint32_t DENALI_CTL_306;
- volatile uint32_t DENALI_CTL_307;
- volatile uint32_t DENALI_CTL_308;
- volatile uint32_t DENALI_CTL_309;
- volatile uint32_t DENALI_CTL_310;
- volatile uint32_t DENALI_CTL_311;
- volatile uint32_t DENALI_CTL_312;
- volatile uint32_t DENALI_CTL_313;
- volatile uint32_t DENALI_CTL_314;
- volatile uint32_t DENALI_CTL_315;
- volatile uint32_t DENALI_CTL_316;
- volatile uint32_t DENALI_CTL_317;
- volatile uint32_t DENALI_CTL_318;
- volatile uint32_t DENALI_CTL_319;
- volatile uint32_t DENALI_CTL_320;
- volatile uint32_t DENALI_CTL_321;
- volatile uint32_t DENALI_CTL_322;
- volatile uint32_t DENALI_CTL_323;
- volatile uint32_t DENALI_CTL_324;
- volatile uint32_t DENALI_CTL_325;
- volatile uint32_t DENALI_CTL_326;
- volatile uint32_t DENALI_CTL_327;
- volatile uint32_t DENALI_CTL_328;
- volatile uint32_t DENALI_CTL_329;
- volatile uint32_t DENALI_CTL_330;
- volatile uint32_t DENALI_CTL_331;
- volatile uint32_t DENALI_CTL_332;
- volatile uint32_t DENALI_CTL_333;
- volatile uint32_t DENALI_CTL_334;
- volatile uint32_t DENALI_CTL_335;
- volatile uint32_t DENALI_CTL_336;
- volatile uint32_t DENALI_CTL_337;
- volatile uint32_t DENALI_CTL_338;
- volatile uint32_t DENALI_CTL_339;
- volatile uint32_t DENALI_CTL_340;
- volatile uint32_t DENALI_CTL_341;
- volatile uint32_t DENALI_CTL_342;
- volatile uint32_t DENALI_CTL_343;
- volatile uint32_t DENALI_CTL_344;
- volatile uint32_t DENALI_CTL_345;
- volatile uint32_t DENALI_CTL_346;
- volatile uint32_t DENALI_CTL_347;
- volatile uint32_t DENALI_CTL_348;
- volatile uint32_t DENALI_CTL_349;
- volatile uint32_t DENALI_CTL_350;
- volatile uint32_t DENALI_CTL_351;
- volatile uint32_t DENALI_CTL_352;
- volatile uint32_t DENALI_CTL_353;
- volatile uint32_t DENALI_CTL_354;
- volatile uint32_t DENALI_CTL_355;
- volatile uint32_t DENALI_CTL_356;
- volatile uint32_t DENALI_CTL_357;
- volatile uint32_t DENALI_CTL_358;
- volatile uint32_t DENALI_CTL_359;
- volatile uint32_t DENALI_CTL_360;
- volatile uint32_t DENALI_CTL_361;
- volatile uint32_t DENALI_CTL_362;
- volatile uint32_t DENALI_CTL_363;
- volatile uint32_t DENALI_CTL_364;
- volatile uint32_t DENALI_CTL_365;
- volatile uint32_t DENALI_CTL_366;
- volatile uint32_t DENALI_CTL_367;
- volatile uint32_t DENALI_CTL_368;
- volatile uint32_t DENALI_CTL_369;
- volatile uint32_t DENALI_CTL_370;
- volatile uint32_t DENALI_CTL_371;
- volatile uint32_t DENALI_CTL_372;
- volatile uint32_t DENALI_CTL_373;
- volatile uint32_t DENALI_CTL_374;
- volatile uint32_t DENALI_CTL_375;
- volatile uint32_t DENALI_CTL_376;
- volatile uint32_t DENALI_CTL_377;
- volatile uint32_t DENALI_CTL_378;
- volatile uint32_t DENALI_CTL_379;
- volatile uint32_t DENALI_CTL_380;
- volatile uint32_t DENALI_CTL_381;
- volatile uint32_t DENALI_CTL_382;
- volatile uint32_t DENALI_CTL_383;
- volatile uint32_t DENALI_CTL_384;
- volatile uint32_t DENALI_CTL_385;
- volatile uint32_t DENALI_CTL_386;
- volatile uint32_t DENALI_CTL_387;
- volatile uint32_t DENALI_CTL_388;
- volatile uint32_t DENALI_CTL_389;
- volatile uint32_t DENALI_CTL_390;
- volatile uint32_t DENALI_CTL_391;
- volatile uint32_t DENALI_CTL_392;
- volatile uint32_t DENALI_CTL_393;
- volatile uint32_t DENALI_CTL_394;
- volatile uint32_t DENALI_CTL_395;
- volatile uint32_t DENALI_CTL_396;
- volatile uint32_t DENALI_CTL_397;
- volatile uint32_t DENALI_CTL_398;
- volatile uint32_t DENALI_CTL_399;
- volatile uint32_t DENALI_CTL_400;
- volatile uint32_t DENALI_CTL_401;
- volatile uint32_t DENALI_CTL_402;
- volatile uint32_t DENALI_CTL_403;
- volatile uint32_t DENALI_CTL_404;
- volatile uint32_t DENALI_CTL_405;
- volatile uint32_t DENALI_CTL_406;
- volatile uint32_t DENALI_CTL_407;
- volatile uint32_t DENALI_CTL_408;
- volatile uint32_t DENALI_CTL_409;
- volatile uint32_t DENALI_CTL_410;
- volatile uint32_t DENALI_CTL_411;
- volatile uint32_t DENALI_CTL_412;
- volatile uint32_t DENALI_CTL_413;
- volatile uint32_t DENALI_CTL_414;
- volatile uint32_t DENALI_CTL_415;
- volatile uint32_t DENALI_CTL_416;
- volatile uint32_t DENALI_CTL_417;
- volatile uint32_t DENALI_CTL_418;
- volatile uint32_t DENALI_CTL_419;
- volatile uint32_t DENALI_CTL_420;
- volatile uint32_t DENALI_CTL_421;
- volatile uint32_t DENALI_CTL_422;
- volatile uint32_t DENALI_CTL_423;
- volatile uint32_t DENALI_CTL_424;
- volatile uint32_t DENALI_CTL_425;
- volatile uint32_t DENALI_CTL_426;
- volatile uint32_t DENALI_CTL_427;
- volatile uint32_t DENALI_CTL_428;
- volatile uint32_t DENALI_CTL_429;
- volatile uint32_t DENALI_CTL_430;
- volatile uint32_t DENALI_CTL_431;
- volatile uint32_t DENALI_CTL_432;
- volatile uint32_t DENALI_CTL_433;
- volatile uint32_t DENALI_CTL_434;
- volatile uint32_t DENALI_CTL_435;
- volatile uint32_t DENALI_CTL_436;
- volatile uint32_t DENALI_CTL_437;
- volatile uint32_t DENALI_CTL_438;
- volatile uint32_t DENALI_CTL_439;
- volatile uint32_t DENALI_CTL_440;
- volatile uint32_t DENALI_CTL_441;
- volatile uint32_t DENALI_CTL_442;
- volatile uint32_t DENALI_CTL_443;
- volatile uint32_t DENALI_CTL_444;
- volatile uint32_t DENALI_CTL_445;
- volatile uint32_t DENALI_CTL_446;
- volatile uint32_t DENALI_CTL_447;
- volatile uint32_t DENALI_CTL_448;
- volatile uint32_t DENALI_CTL_449;
- volatile uint32_t DENALI_CTL_450;
- volatile uint32_t DENALI_CTL_451;
- volatile uint32_t DENALI_CTL_452;
- volatile uint32_t DENALI_CTL_453;
- volatile uint32_t DENALI_CTL_454;
- volatile uint32_t DENALI_CTL_455;
- volatile uint32_t DENALI_CTL_456;
- volatile uint32_t DENALI_CTL_457;
- volatile uint32_t DENALI_CTL_458;
- volatile char pad__0[0x18D4U];
- volatile uint32_t DENALI_PI_0;
- volatile uint32_t DENALI_PI_1;
- volatile uint32_t DENALI_PI_2;
- volatile uint32_t DENALI_PI_3;
- volatile uint32_t DENALI_PI_4;
- volatile uint32_t DENALI_PI_5;
- volatile uint32_t DENALI_PI_6;
- volatile uint32_t DENALI_PI_7;
- volatile uint32_t DENALI_PI_8;
- volatile uint32_t DENALI_PI_9;
- volatile uint32_t DENALI_PI_10;
- volatile uint32_t DENALI_PI_11;
- volatile uint32_t DENALI_PI_12;
- volatile uint32_t DENALI_PI_13;
- volatile uint32_t DENALI_PI_14;
- volatile uint32_t DENALI_PI_15;
- volatile uint32_t DENALI_PI_16;
- volatile uint32_t DENALI_PI_17;
- volatile uint32_t DENALI_PI_18;
- volatile uint32_t DENALI_PI_19;
- volatile uint32_t DENALI_PI_20;
- volatile uint32_t DENALI_PI_21;
- volatile uint32_t DENALI_PI_22;
- volatile uint32_t DENALI_PI_23;
- volatile uint32_t DENALI_PI_24;
- volatile uint32_t DENALI_PI_25;
- volatile uint32_t DENALI_PI_26;
- volatile uint32_t DENALI_PI_27;
- volatile uint32_t DENALI_PI_28;
- volatile uint32_t DENALI_PI_29;
- volatile uint32_t DENALI_PI_30;
- volatile uint32_t DENALI_PI_31;
- volatile uint32_t DENALI_PI_32;
- volatile uint32_t DENALI_PI_33;
- volatile uint32_t DENALI_PI_34;
- volatile uint32_t DENALI_PI_35;
- volatile uint32_t DENALI_PI_36;
- volatile uint32_t DENALI_PI_37;
- volatile uint32_t DENALI_PI_38;
- volatile uint32_t DENALI_PI_39;
- volatile uint32_t DENALI_PI_40;
- volatile uint32_t DENALI_PI_41;
- volatile uint32_t DENALI_PI_42;
- volatile uint32_t DENALI_PI_43;
- volatile uint32_t DENALI_PI_44;
- volatile uint32_t DENALI_PI_45;
- volatile uint32_t DENALI_PI_46;
- volatile uint32_t DENALI_PI_47;
- volatile uint32_t DENALI_PI_48;
- volatile uint32_t DENALI_PI_49;
- volatile uint32_t DENALI_PI_50;
- volatile uint32_t DENALI_PI_51;
- volatile uint32_t DENALI_PI_52;
- volatile uint32_t DENALI_PI_53;
- volatile uint32_t DENALI_PI_54;
- volatile uint32_t DENALI_PI_55;
- volatile uint32_t DENALI_PI_56;
- volatile uint32_t DENALI_PI_57;
- volatile uint32_t DENALI_PI_58;
- volatile uint32_t DENALI_PI_59;
- volatile uint32_t DENALI_PI_60;
- volatile uint32_t DENALI_PI_61;
- volatile uint32_t DENALI_PI_62;
- volatile uint32_t DENALI_PI_63;
- volatile uint32_t DENALI_PI_64;
- volatile uint32_t DENALI_PI_65;
- volatile uint32_t DENALI_PI_66;
- volatile uint32_t DENALI_PI_67;
- volatile uint32_t DENALI_PI_68;
- volatile uint32_t DENALI_PI_69;
- volatile uint32_t DENALI_PI_70;
- volatile uint32_t DENALI_PI_71;
- volatile uint32_t DENALI_PI_72;
- volatile uint32_t DENALI_PI_73;
- volatile uint32_t DENALI_PI_74;
- volatile uint32_t DENALI_PI_75;
- volatile uint32_t DENALI_PI_76;
- volatile uint32_t DENALI_PI_77;
- volatile uint32_t DENALI_PI_78;
- volatile uint32_t DENALI_PI_79;
- volatile uint32_t DENALI_PI_80;
- volatile uint32_t DENALI_PI_81;
- volatile uint32_t DENALI_PI_82;
- volatile uint32_t DENALI_PI_83;
- volatile uint32_t DENALI_PI_84;
- volatile uint32_t DENALI_PI_85;
- volatile uint32_t DENALI_PI_86;
- volatile uint32_t DENALI_PI_87;
- volatile uint32_t DENALI_PI_88;
- volatile uint32_t DENALI_PI_89;
- volatile uint32_t DENALI_PI_90;
- volatile uint32_t DENALI_PI_91;
- volatile uint32_t DENALI_PI_92;
- volatile uint32_t DENALI_PI_93;
- volatile uint32_t DENALI_PI_94;
- volatile uint32_t DENALI_PI_95;
- volatile uint32_t DENALI_PI_96;
- volatile uint32_t DENALI_PI_97;
- volatile uint32_t DENALI_PI_98;
- volatile uint32_t DENALI_PI_99;
- volatile uint32_t DENALI_PI_100;
- volatile uint32_t DENALI_PI_101;
- volatile uint32_t DENALI_PI_102;
- volatile uint32_t DENALI_PI_103;
- volatile uint32_t DENALI_PI_104;
- volatile uint32_t DENALI_PI_105;
- volatile uint32_t DENALI_PI_106;
- volatile uint32_t DENALI_PI_107;
- volatile uint32_t DENALI_PI_108;
- volatile uint32_t DENALI_PI_109;
- volatile uint32_t DENALI_PI_110;
- volatile uint32_t DENALI_PI_111;
- volatile uint32_t DENALI_PI_112;
- volatile uint32_t DENALI_PI_113;
- volatile uint32_t DENALI_PI_114;
- volatile uint32_t DENALI_PI_115;
- volatile uint32_t DENALI_PI_116;
- volatile uint32_t DENALI_PI_117;
- volatile uint32_t DENALI_PI_118;
- volatile uint32_t DENALI_PI_119;
- volatile uint32_t DENALI_PI_120;
- volatile uint32_t DENALI_PI_121;
- volatile uint32_t DENALI_PI_122;
- volatile uint32_t DENALI_PI_123;
- volatile uint32_t DENALI_PI_124;
- volatile uint32_t DENALI_PI_125;
- volatile uint32_t DENALI_PI_126;
- volatile uint32_t DENALI_PI_127;
- volatile uint32_t DENALI_PI_128;
- volatile uint32_t DENALI_PI_129;
- volatile uint32_t DENALI_PI_130;
- volatile uint32_t DENALI_PI_131;
- volatile uint32_t DENALI_PI_132;
- volatile uint32_t DENALI_PI_133;
- volatile uint32_t DENALI_PI_134;
- volatile uint32_t DENALI_PI_135;
- volatile uint32_t DENALI_PI_136;
- volatile uint32_t DENALI_PI_137;
- volatile uint32_t DENALI_PI_138;
- volatile uint32_t DENALI_PI_139;
- volatile uint32_t DENALI_PI_140;
- volatile uint32_t DENALI_PI_141;
- volatile uint32_t DENALI_PI_142;
- volatile uint32_t DENALI_PI_143;
- volatile uint32_t DENALI_PI_144;
- volatile uint32_t DENALI_PI_145;
- volatile uint32_t DENALI_PI_146;
- volatile uint32_t DENALI_PI_147;
- volatile uint32_t DENALI_PI_148;
- volatile uint32_t DENALI_PI_149;
- volatile uint32_t DENALI_PI_150;
- volatile uint32_t DENALI_PI_151;
- volatile uint32_t DENALI_PI_152;
- volatile uint32_t DENALI_PI_153;
- volatile uint32_t DENALI_PI_154;
- volatile uint32_t DENALI_PI_155;
- volatile uint32_t DENALI_PI_156;
- volatile uint32_t DENALI_PI_157;
- volatile uint32_t DENALI_PI_158;
- volatile uint32_t DENALI_PI_159;
- volatile uint32_t DENALI_PI_160;
- volatile uint32_t DENALI_PI_161;
- volatile uint32_t DENALI_PI_162;
- volatile uint32_t DENALI_PI_163;
- volatile uint32_t DENALI_PI_164;
- volatile uint32_t DENALI_PI_165;
- volatile uint32_t DENALI_PI_166;
- volatile uint32_t DENALI_PI_167;
- volatile uint32_t DENALI_PI_168;
- volatile uint32_t DENALI_PI_169;
- volatile uint32_t DENALI_PI_170;
- volatile uint32_t DENALI_PI_171;
- volatile uint32_t DENALI_PI_172;
- volatile uint32_t DENALI_PI_173;
- volatile uint32_t DENALI_PI_174;
- volatile uint32_t DENALI_PI_175;
- volatile uint32_t DENALI_PI_176;
- volatile uint32_t DENALI_PI_177;
- volatile uint32_t DENALI_PI_178;
- volatile uint32_t DENALI_PI_179;
- volatile uint32_t DENALI_PI_180;
- volatile uint32_t DENALI_PI_181;
- volatile uint32_t DENALI_PI_182;
- volatile uint32_t DENALI_PI_183;
- volatile uint32_t DENALI_PI_184;
- volatile uint32_t DENALI_PI_185;
- volatile uint32_t DENALI_PI_186;
- volatile uint32_t DENALI_PI_187;
- volatile uint32_t DENALI_PI_188;
- volatile uint32_t DENALI_PI_189;
- volatile uint32_t DENALI_PI_190;
- volatile uint32_t DENALI_PI_191;
- volatile uint32_t DENALI_PI_192;
- volatile uint32_t DENALI_PI_193;
- volatile uint32_t DENALI_PI_194;
- volatile uint32_t DENALI_PI_195;
- volatile uint32_t DENALI_PI_196;
- volatile uint32_t DENALI_PI_197;
- volatile uint32_t DENALI_PI_198;
- volatile uint32_t DENALI_PI_199;
- volatile uint32_t DENALI_PI_200;
- volatile uint32_t DENALI_PI_201;
- volatile uint32_t DENALI_PI_202;
- volatile uint32_t DENALI_PI_203;
- volatile uint32_t DENALI_PI_204;
- volatile uint32_t DENALI_PI_205;
- volatile uint32_t DENALI_PI_206;
- volatile uint32_t DENALI_PI_207;
- volatile uint32_t DENALI_PI_208;
- volatile uint32_t DENALI_PI_209;
- volatile uint32_t DENALI_PI_210;
- volatile uint32_t DENALI_PI_211;
- volatile uint32_t DENALI_PI_212;
- volatile uint32_t DENALI_PI_213;
- volatile uint32_t DENALI_PI_214;
- volatile uint32_t DENALI_PI_215;
- volatile uint32_t DENALI_PI_216;
- volatile uint32_t DENALI_PI_217;
- volatile uint32_t DENALI_PI_218;
- volatile uint32_t DENALI_PI_219;
- volatile uint32_t DENALI_PI_220;
- volatile uint32_t DENALI_PI_221;
- volatile uint32_t DENALI_PI_222;
- volatile uint32_t DENALI_PI_223;
- volatile uint32_t DENALI_PI_224;
- volatile uint32_t DENALI_PI_225;
- volatile uint32_t DENALI_PI_226;
- volatile uint32_t DENALI_PI_227;
- volatile uint32_t DENALI_PI_228;
- volatile uint32_t DENALI_PI_229;
- volatile uint32_t DENALI_PI_230;
- volatile uint32_t DENALI_PI_231;
- volatile uint32_t DENALI_PI_232;
- volatile uint32_t DENALI_PI_233;
- volatile uint32_t DENALI_PI_234;
- volatile uint32_t DENALI_PI_235;
- volatile uint32_t DENALI_PI_236;
- volatile uint32_t DENALI_PI_237;
- volatile uint32_t DENALI_PI_238;
- volatile uint32_t DENALI_PI_239;
- volatile uint32_t DENALI_PI_240;
- volatile uint32_t DENALI_PI_241;
- volatile uint32_t DENALI_PI_242;
- volatile uint32_t DENALI_PI_243;
- volatile uint32_t DENALI_PI_244;
- volatile uint32_t DENALI_PI_245;
- volatile uint32_t DENALI_PI_246;
- volatile uint32_t DENALI_PI_247;
- volatile uint32_t DENALI_PI_248;
- volatile uint32_t DENALI_PI_249;
- volatile uint32_t DENALI_PI_250;
- volatile uint32_t DENALI_PI_251;
- volatile uint32_t DENALI_PI_252;
- volatile uint32_t DENALI_PI_253;
- volatile uint32_t DENALI_PI_254;
- volatile uint32_t DENALI_PI_255;
- volatile uint32_t DENALI_PI_256;
- volatile uint32_t DENALI_PI_257;
- volatile uint32_t DENALI_PI_258;
- volatile uint32_t DENALI_PI_259;
- volatile uint32_t DENALI_PI_260;
- volatile uint32_t DENALI_PI_261;
- volatile uint32_t DENALI_PI_262;
- volatile uint32_t DENALI_PI_263;
- volatile uint32_t DENALI_PI_264;
- volatile uint32_t DENALI_PI_265;
- volatile uint32_t DENALI_PI_266;
- volatile uint32_t DENALI_PI_267;
- volatile uint32_t DENALI_PI_268;
- volatile uint32_t DENALI_PI_269;
- volatile uint32_t DENALI_PI_270;
- volatile uint32_t DENALI_PI_271;
- volatile uint32_t DENALI_PI_272;
- volatile uint32_t DENALI_PI_273;
- volatile uint32_t DENALI_PI_274;
- volatile uint32_t DENALI_PI_275;
- volatile uint32_t DENALI_PI_276;
- volatile uint32_t DENALI_PI_277;
- volatile uint32_t DENALI_PI_278;
- volatile uint32_t DENALI_PI_279;
- volatile uint32_t DENALI_PI_280;
- volatile uint32_t DENALI_PI_281;
- volatile uint32_t DENALI_PI_282;
- volatile uint32_t DENALI_PI_283;
- volatile uint32_t DENALI_PI_284;
- volatile uint32_t DENALI_PI_285;
- volatile uint32_t DENALI_PI_286;
- volatile uint32_t DENALI_PI_287;
- volatile uint32_t DENALI_PI_288;
- volatile uint32_t DENALI_PI_289;
- volatile uint32_t DENALI_PI_290;
- volatile uint32_t DENALI_PI_291;
- volatile uint32_t DENALI_PI_292;
- volatile uint32_t DENALI_PI_293;
- volatile uint32_t DENALI_PI_294;
- volatile uint32_t DENALI_PI_295;
- volatile uint32_t DENALI_PI_296;
- volatile uint32_t DENALI_PI_297;
- volatile uint32_t DENALI_PI_298;
- volatile uint32_t DENALI_PI_299;
- volatile char pad__1[0x1B50U];
- volatile uint32_t DENALI_PHY_0;
- volatile uint32_t DENALI_PHY_1;
- volatile uint32_t DENALI_PHY_2;
- volatile uint32_t DENALI_PHY_3;
- volatile uint32_t DENALI_PHY_4;
- volatile uint32_t DENALI_PHY_5;
- volatile uint32_t DENALI_PHY_6;
- volatile uint32_t DENALI_PHY_7;
- volatile uint32_t DENALI_PHY_8;
- volatile uint32_t DENALI_PHY_9;
- volatile uint32_t DENALI_PHY_10;
- volatile uint32_t DENALI_PHY_11;
- volatile uint32_t DENALI_PHY_12;
- volatile uint32_t DENALI_PHY_13;
- volatile uint32_t DENALI_PHY_14;
- volatile uint32_t DENALI_PHY_15;
- volatile uint32_t DENALI_PHY_16;
- volatile uint32_t DENALI_PHY_17;
- volatile uint32_t DENALI_PHY_18;
- volatile uint32_t DENALI_PHY_19;
- volatile uint32_t DENALI_PHY_20;
- volatile uint32_t DENALI_PHY_21;
- volatile uint32_t DENALI_PHY_22;
- volatile uint32_t DENALI_PHY_23;
- volatile uint32_t DENALI_PHY_24;
- volatile uint32_t DENALI_PHY_25;
- volatile uint32_t DENALI_PHY_26;
- volatile uint32_t DENALI_PHY_27;
- volatile uint32_t DENALI_PHY_28;
- volatile uint32_t DENALI_PHY_29;
- volatile uint32_t DENALI_PHY_30;
- volatile uint32_t DENALI_PHY_31;
- volatile uint32_t DENALI_PHY_32;
- volatile uint32_t DENALI_PHY_33;
- volatile uint32_t DENALI_PHY_34;
- volatile uint32_t DENALI_PHY_35;
- volatile uint32_t DENALI_PHY_36;
- volatile uint32_t DENALI_PHY_37;
- volatile uint32_t DENALI_PHY_38;
- volatile uint32_t DENALI_PHY_39;
- volatile uint32_t DENALI_PHY_40;
- volatile uint32_t DENALI_PHY_41;
- volatile uint32_t DENALI_PHY_42;
- volatile uint32_t DENALI_PHY_43;
- volatile uint32_t DENALI_PHY_44;
- volatile uint32_t DENALI_PHY_45;
- volatile uint32_t DENALI_PHY_46;
- volatile uint32_t DENALI_PHY_47;
- volatile uint32_t DENALI_PHY_48;
- volatile uint32_t DENALI_PHY_49;
- volatile uint32_t DENALI_PHY_50;
- volatile uint32_t DENALI_PHY_51;
- volatile uint32_t DENALI_PHY_52;
- volatile uint32_t DENALI_PHY_53;
- volatile uint32_t DENALI_PHY_54;
- volatile uint32_t DENALI_PHY_55;
- volatile uint32_t DENALI_PHY_56;
- volatile uint32_t DENALI_PHY_57;
- volatile uint32_t DENALI_PHY_58;
- volatile uint32_t DENALI_PHY_59;
- volatile uint32_t DENALI_PHY_60;
- volatile uint32_t DENALI_PHY_61;
- volatile uint32_t DENALI_PHY_62;
- volatile uint32_t DENALI_PHY_63;
- volatile uint32_t DENALI_PHY_64;
- volatile uint32_t DENALI_PHY_65;
- volatile uint32_t DENALI_PHY_66;
- volatile uint32_t DENALI_PHY_67;
- volatile uint32_t DENALI_PHY_68;
- volatile uint32_t DENALI_PHY_69;
- volatile uint32_t DENALI_PHY_70;
- volatile uint32_t DENALI_PHY_71;
- volatile uint32_t DENALI_PHY_72;
- volatile uint32_t DENALI_PHY_73;
- volatile uint32_t DENALI_PHY_74;
- volatile uint32_t DENALI_PHY_75;
- volatile uint32_t DENALI_PHY_76;
- volatile uint32_t DENALI_PHY_77;
- volatile uint32_t DENALI_PHY_78;
- volatile uint32_t DENALI_PHY_79;
- volatile uint32_t DENALI_PHY_80;
- volatile uint32_t DENALI_PHY_81;
- volatile uint32_t DENALI_PHY_82;
- volatile uint32_t DENALI_PHY_83;
- volatile uint32_t DENALI_PHY_84;
- volatile uint32_t DENALI_PHY_85;
- volatile uint32_t DENALI_PHY_86;
- volatile uint32_t DENALI_PHY_87;
- volatile uint32_t DENALI_PHY_88;
- volatile uint32_t DENALI_PHY_89;
- volatile uint32_t DENALI_PHY_90;
- volatile uint32_t DENALI_PHY_91;
- volatile uint32_t DENALI_PHY_92;
- volatile uint32_t DENALI_PHY_93;
- volatile uint32_t DENALI_PHY_94;
- volatile uint32_t DENALI_PHY_95;
- volatile uint32_t DENALI_PHY_96;
- volatile uint32_t DENALI_PHY_97;
- volatile uint32_t DENALI_PHY_98;
- volatile uint32_t DENALI_PHY_99;
- volatile uint32_t DENALI_PHY_100;
- volatile uint32_t DENALI_PHY_101;
- volatile uint32_t DENALI_PHY_102;
- volatile uint32_t DENALI_PHY_103;
- volatile uint32_t DENALI_PHY_104;
- volatile uint32_t DENALI_PHY_105;
- volatile uint32_t DENALI_PHY_106;
- volatile uint32_t DENALI_PHY_107;
- volatile uint32_t DENALI_PHY_108;
- volatile uint32_t DENALI_PHY_109;
- volatile uint32_t DENALI_PHY_110;
- volatile uint32_t DENALI_PHY_111;
- volatile uint32_t DENALI_PHY_112;
- volatile uint32_t DENALI_PHY_113;
- volatile uint32_t DENALI_PHY_114;
- volatile uint32_t DENALI_PHY_115;
- volatile uint32_t DENALI_PHY_116;
- volatile uint32_t DENALI_PHY_117;
- volatile uint32_t DENALI_PHY_118;
- volatile uint32_t DENALI_PHY_119;
- volatile uint32_t DENALI_PHY_120;
- volatile uint32_t DENALI_PHY_121;
- volatile uint32_t DENALI_PHY_122;
- volatile uint32_t DENALI_PHY_123;
- volatile uint32_t DENALI_PHY_124;
- volatile uint32_t DENALI_PHY_125;
- volatile uint32_t DENALI_PHY_126;
- volatile uint32_t DENALI_PHY_127;
- volatile uint32_t DENALI_PHY_128;
- volatile uint32_t DENALI_PHY_129;
- volatile uint32_t DENALI_PHY_130;
- volatile uint32_t DENALI_PHY_131;
- volatile uint32_t DENALI_PHY_132;
- volatile uint32_t DENALI_PHY_133;
- volatile uint32_t DENALI_PHY_134;
- volatile uint32_t DENALI_PHY_135;
- volatile uint32_t DENALI_PHY_136;
- volatile uint32_t DENALI_PHY_137;
- volatile uint32_t DENALI_PHY_138;
- volatile uint32_t DENALI_PHY_139;
- volatile char pad__2[0x1D0U];
- volatile uint32_t DENALI_PHY_256;
- volatile uint32_t DENALI_PHY_257;
- volatile uint32_t DENALI_PHY_258;
- volatile uint32_t DENALI_PHY_259;
- volatile uint32_t DENALI_PHY_260;
- volatile uint32_t DENALI_PHY_261;
- volatile uint32_t DENALI_PHY_262;
- volatile uint32_t DENALI_PHY_263;
- volatile uint32_t DENALI_PHY_264;
- volatile uint32_t DENALI_PHY_265;
- volatile uint32_t DENALI_PHY_266;
- volatile uint32_t DENALI_PHY_267;
- volatile uint32_t DENALI_PHY_268;
- volatile uint32_t DENALI_PHY_269;
- volatile uint32_t DENALI_PHY_270;
- volatile uint32_t DENALI_PHY_271;
- volatile uint32_t DENALI_PHY_272;
- volatile uint32_t DENALI_PHY_273;
- volatile uint32_t DENALI_PHY_274;
- volatile uint32_t DENALI_PHY_275;
- volatile uint32_t DENALI_PHY_276;
- volatile uint32_t DENALI_PHY_277;
- volatile uint32_t DENALI_PHY_278;
- volatile uint32_t DENALI_PHY_279;
- volatile uint32_t DENALI_PHY_280;
- volatile uint32_t DENALI_PHY_281;
- volatile uint32_t DENALI_PHY_282;
- volatile uint32_t DENALI_PHY_283;
- volatile uint32_t DENALI_PHY_284;
- volatile uint32_t DENALI_PHY_285;
- volatile uint32_t DENALI_PHY_286;
- volatile uint32_t DENALI_PHY_287;
- volatile uint32_t DENALI_PHY_288;
- volatile uint32_t DENALI_PHY_289;
- volatile uint32_t DENALI_PHY_290;
- volatile uint32_t DENALI_PHY_291;
- volatile uint32_t DENALI_PHY_292;
- volatile uint32_t DENALI_PHY_293;
- volatile uint32_t DENALI_PHY_294;
- volatile uint32_t DENALI_PHY_295;
- volatile uint32_t DENALI_PHY_296;
- volatile uint32_t DENALI_PHY_297;
- volatile uint32_t DENALI_PHY_298;
- volatile uint32_t DENALI_PHY_299;
- volatile uint32_t DENALI_PHY_300;
- volatile uint32_t DENALI_PHY_301;
- volatile uint32_t DENALI_PHY_302;
- volatile uint32_t DENALI_PHY_303;
- volatile uint32_t DENALI_PHY_304;
- volatile uint32_t DENALI_PHY_305;
- volatile uint32_t DENALI_PHY_306;
- volatile uint32_t DENALI_PHY_307;
- volatile uint32_t DENALI_PHY_308;
- volatile uint32_t DENALI_PHY_309;
- volatile uint32_t DENALI_PHY_310;
- volatile uint32_t DENALI_PHY_311;
- volatile uint32_t DENALI_PHY_312;
- volatile uint32_t DENALI_PHY_313;
- volatile uint32_t DENALI_PHY_314;
- volatile uint32_t DENALI_PHY_315;
- volatile uint32_t DENALI_PHY_316;
- volatile uint32_t DENALI_PHY_317;
- volatile uint32_t DENALI_PHY_318;
- volatile uint32_t DENALI_PHY_319;
- volatile uint32_t DENALI_PHY_320;
- volatile uint32_t DENALI_PHY_321;
- volatile uint32_t DENALI_PHY_322;
- volatile uint32_t DENALI_PHY_323;
- volatile uint32_t DENALI_PHY_324;
- volatile uint32_t DENALI_PHY_325;
- volatile uint32_t DENALI_PHY_326;
- volatile uint32_t DENALI_PHY_327;
- volatile uint32_t DENALI_PHY_328;
- volatile uint32_t DENALI_PHY_329;
- volatile uint32_t DENALI_PHY_330;
- volatile uint32_t DENALI_PHY_331;
- volatile uint32_t DENALI_PHY_332;
- volatile uint32_t DENALI_PHY_333;
- volatile uint32_t DENALI_PHY_334;
- volatile uint32_t DENALI_PHY_335;
- volatile uint32_t DENALI_PHY_336;
- volatile uint32_t DENALI_PHY_337;
- volatile uint32_t DENALI_PHY_338;
- volatile uint32_t DENALI_PHY_339;
- volatile uint32_t DENALI_PHY_340;
- volatile uint32_t DENALI_PHY_341;
- volatile uint32_t DENALI_PHY_342;
- volatile uint32_t DENALI_PHY_343;
- volatile uint32_t DENALI_PHY_344;
- volatile uint32_t DENALI_PHY_345;
- volatile uint32_t DENALI_PHY_346;
- volatile uint32_t DENALI_PHY_347;
- volatile uint32_t DENALI_PHY_348;
- volatile uint32_t DENALI_PHY_349;
- volatile uint32_t DENALI_PHY_350;
- volatile uint32_t DENALI_PHY_351;
- volatile uint32_t DENALI_PHY_352;
- volatile uint32_t DENALI_PHY_353;
- volatile uint32_t DENALI_PHY_354;
- volatile uint32_t DENALI_PHY_355;
- volatile uint32_t DENALI_PHY_356;
- volatile uint32_t DENALI_PHY_357;
- volatile uint32_t DENALI_PHY_358;
- volatile uint32_t DENALI_PHY_359;
- volatile uint32_t DENALI_PHY_360;
- volatile uint32_t DENALI_PHY_361;
- volatile uint32_t DENALI_PHY_362;
- volatile uint32_t DENALI_PHY_363;
- volatile uint32_t DENALI_PHY_364;
- volatile uint32_t DENALI_PHY_365;
- volatile uint32_t DENALI_PHY_366;
- volatile uint32_t DENALI_PHY_367;
- volatile uint32_t DENALI_PHY_368;
- volatile uint32_t DENALI_PHY_369;
- volatile uint32_t DENALI_PHY_370;
- volatile uint32_t DENALI_PHY_371;
- volatile uint32_t DENALI_PHY_372;
- volatile uint32_t DENALI_PHY_373;
- volatile uint32_t DENALI_PHY_374;
- volatile uint32_t DENALI_PHY_375;
- volatile uint32_t DENALI_PHY_376;
- volatile uint32_t DENALI_PHY_377;
- volatile uint32_t DENALI_PHY_378;
- volatile uint32_t DENALI_PHY_379;
- volatile uint32_t DENALI_PHY_380;
- volatile uint32_t DENALI_PHY_381;
- volatile uint32_t DENALI_PHY_382;
- volatile uint32_t DENALI_PHY_383;
- volatile uint32_t DENALI_PHY_384;
- volatile uint32_t DENALI_PHY_385;
- volatile uint32_t DENALI_PHY_386;
- volatile uint32_t DENALI_PHY_387;
- volatile uint32_t DENALI_PHY_388;
- volatile uint32_t DENALI_PHY_389;
- volatile uint32_t DENALI_PHY_390;
- volatile uint32_t DENALI_PHY_391;
- volatile uint32_t DENALI_PHY_392;
- volatile uint32_t DENALI_PHY_393;
- volatile uint32_t DENALI_PHY_394;
- volatile uint32_t DENALI_PHY_395;
- volatile char pad__3[0x1D0U];
- volatile uint32_t DENALI_PHY_512;
- volatile uint32_t DENALI_PHY_513;
- volatile uint32_t DENALI_PHY_514;
- volatile uint32_t DENALI_PHY_515;
- volatile uint32_t DENALI_PHY_516;
- volatile uint32_t DENALI_PHY_517;
- volatile uint32_t DENALI_PHY_518;
- volatile uint32_t DENALI_PHY_519;
- volatile uint32_t DENALI_PHY_520;
- volatile uint32_t DENALI_PHY_521;
- volatile uint32_t DENALI_PHY_522;
- volatile uint32_t DENALI_PHY_523;
- volatile uint32_t DENALI_PHY_524;
- volatile uint32_t DENALI_PHY_525;
- volatile uint32_t DENALI_PHY_526;
- volatile uint32_t DENALI_PHY_527;
- volatile uint32_t DENALI_PHY_528;
- volatile uint32_t DENALI_PHY_529;
- volatile uint32_t DENALI_PHY_530;
- volatile uint32_t DENALI_PHY_531;
- volatile uint32_t DENALI_PHY_532;
- volatile uint32_t DENALI_PHY_533;
- volatile uint32_t DENALI_PHY_534;
- volatile uint32_t DENALI_PHY_535;
- volatile uint32_t DENALI_PHY_536;
- volatile uint32_t DENALI_PHY_537;
- volatile uint32_t DENALI_PHY_538;
- volatile uint32_t DENALI_PHY_539;
- volatile uint32_t DENALI_PHY_540;
- volatile uint32_t DENALI_PHY_541;
- volatile uint32_t DENALI_PHY_542;
- volatile uint32_t DENALI_PHY_543;
- volatile uint32_t DENALI_PHY_544;
- volatile uint32_t DENALI_PHY_545;
- volatile uint32_t DENALI_PHY_546;
- volatile uint32_t DENALI_PHY_547;
- volatile uint32_t DENALI_PHY_548;
- volatile uint32_t DENALI_PHY_549;
- volatile uint32_t DENALI_PHY_550;
- volatile uint32_t DENALI_PHY_551;
- volatile uint32_t DENALI_PHY_552;
- volatile uint32_t DENALI_PHY_553;
- volatile uint32_t DENALI_PHY_554;
- volatile uint32_t DENALI_PHY_555;
- volatile uint32_t DENALI_PHY_556;
- volatile uint32_t DENALI_PHY_557;
- volatile uint32_t DENALI_PHY_558;
- volatile uint32_t DENALI_PHY_559;
- volatile uint32_t DENALI_PHY_560;
- volatile uint32_t DENALI_PHY_561;
- volatile uint32_t DENALI_PHY_562;
- volatile uint32_t DENALI_PHY_563;
- volatile uint32_t DENALI_PHY_564;
- volatile uint32_t DENALI_PHY_565;
- volatile uint32_t DENALI_PHY_566;
- volatile uint32_t DENALI_PHY_567;
- volatile uint32_t DENALI_PHY_568;
- volatile uint32_t DENALI_PHY_569;
- volatile uint32_t DENALI_PHY_570;
- volatile uint32_t DENALI_PHY_571;
- volatile uint32_t DENALI_PHY_572;
- volatile uint32_t DENALI_PHY_573;
- volatile uint32_t DENALI_PHY_574;
- volatile uint32_t DENALI_PHY_575;
- volatile uint32_t DENALI_PHY_576;
- volatile uint32_t DENALI_PHY_577;
- volatile uint32_t DENALI_PHY_578;
- volatile uint32_t DENALI_PHY_579;
- volatile uint32_t DENALI_PHY_580;
- volatile uint32_t DENALI_PHY_581;
- volatile uint32_t DENALI_PHY_582;
- volatile uint32_t DENALI_PHY_583;
- volatile uint32_t DENALI_PHY_584;
- volatile uint32_t DENALI_PHY_585;
- volatile uint32_t DENALI_PHY_586;
- volatile uint32_t DENALI_PHY_587;
- volatile uint32_t DENALI_PHY_588;
- volatile uint32_t DENALI_PHY_589;
- volatile uint32_t DENALI_PHY_590;
- volatile uint32_t DENALI_PHY_591;
- volatile uint32_t DENALI_PHY_592;
- volatile uint32_t DENALI_PHY_593;
- volatile uint32_t DENALI_PHY_594;
- volatile uint32_t DENALI_PHY_595;
- volatile uint32_t DENALI_PHY_596;
- volatile uint32_t DENALI_PHY_597;
- volatile uint32_t DENALI_PHY_598;
- volatile uint32_t DENALI_PHY_599;
- volatile uint32_t DENALI_PHY_600;
- volatile uint32_t DENALI_PHY_601;
- volatile uint32_t DENALI_PHY_602;
- volatile uint32_t DENALI_PHY_603;
- volatile uint32_t DENALI_PHY_604;
- volatile uint32_t DENALI_PHY_605;
- volatile uint32_t DENALI_PHY_606;
- volatile uint32_t DENALI_PHY_607;
- volatile uint32_t DENALI_PHY_608;
- volatile uint32_t DENALI_PHY_609;
- volatile uint32_t DENALI_PHY_610;
- volatile uint32_t DENALI_PHY_611;
- volatile uint32_t DENALI_PHY_612;
- volatile uint32_t DENALI_PHY_613;
- volatile uint32_t DENALI_PHY_614;
- volatile uint32_t DENALI_PHY_615;
- volatile uint32_t DENALI_PHY_616;
- volatile uint32_t DENALI_PHY_617;
- volatile uint32_t DENALI_PHY_618;
- volatile uint32_t DENALI_PHY_619;
- volatile uint32_t DENALI_PHY_620;
- volatile uint32_t DENALI_PHY_621;
- volatile uint32_t DENALI_PHY_622;
- volatile uint32_t DENALI_PHY_623;
- volatile uint32_t DENALI_PHY_624;
- volatile uint32_t DENALI_PHY_625;
- volatile uint32_t DENALI_PHY_626;
- volatile uint32_t DENALI_PHY_627;
- volatile uint32_t DENALI_PHY_628;
- volatile uint32_t DENALI_PHY_629;
- volatile uint32_t DENALI_PHY_630;
- volatile uint32_t DENALI_PHY_631;
- volatile uint32_t DENALI_PHY_632;
- volatile uint32_t DENALI_PHY_633;
- volatile uint32_t DENALI_PHY_634;
- volatile uint32_t DENALI_PHY_635;
- volatile uint32_t DENALI_PHY_636;
- volatile uint32_t DENALI_PHY_637;
- volatile uint32_t DENALI_PHY_638;
- volatile uint32_t DENALI_PHY_639;
- volatile uint32_t DENALI_PHY_640;
- volatile uint32_t DENALI_PHY_641;
- volatile uint32_t DENALI_PHY_642;
- volatile uint32_t DENALI_PHY_643;
- volatile uint32_t DENALI_PHY_644;
- volatile uint32_t DENALI_PHY_645;
- volatile uint32_t DENALI_PHY_646;
- volatile uint32_t DENALI_PHY_647;
- volatile uint32_t DENALI_PHY_648;
- volatile uint32_t DENALI_PHY_649;
- volatile uint32_t DENALI_PHY_650;
- volatile uint32_t DENALI_PHY_651;
- volatile char pad__4[0x1D0U];
- volatile uint32_t DENALI_PHY_768;
- volatile uint32_t DENALI_PHY_769;
- volatile uint32_t DENALI_PHY_770;
- volatile uint32_t DENALI_PHY_771;
- volatile uint32_t DENALI_PHY_772;
- volatile uint32_t DENALI_PHY_773;
- volatile uint32_t DENALI_PHY_774;
- volatile uint32_t DENALI_PHY_775;
- volatile uint32_t DENALI_PHY_776;
- volatile uint32_t DENALI_PHY_777;
- volatile uint32_t DENALI_PHY_778;
- volatile uint32_t DENALI_PHY_779;
- volatile uint32_t DENALI_PHY_780;
- volatile uint32_t DENALI_PHY_781;
- volatile uint32_t DENALI_PHY_782;
- volatile uint32_t DENALI_PHY_783;
- volatile uint32_t DENALI_PHY_784;
- volatile uint32_t DENALI_PHY_785;
- volatile uint32_t DENALI_PHY_786;
- volatile uint32_t DENALI_PHY_787;
- volatile uint32_t DENALI_PHY_788;
- volatile uint32_t DENALI_PHY_789;
- volatile uint32_t DENALI_PHY_790;
- volatile uint32_t DENALI_PHY_791;
- volatile uint32_t DENALI_PHY_792;
- volatile uint32_t DENALI_PHY_793;
- volatile uint32_t DENALI_PHY_794;
- volatile uint32_t DENALI_PHY_795;
- volatile uint32_t DENALI_PHY_796;
- volatile uint32_t DENALI_PHY_797;
- volatile uint32_t DENALI_PHY_798;
- volatile uint32_t DENALI_PHY_799;
- volatile uint32_t DENALI_PHY_800;
- volatile uint32_t DENALI_PHY_801;
- volatile uint32_t DENALI_PHY_802;
- volatile uint32_t DENALI_PHY_803;
- volatile uint32_t DENALI_PHY_804;
- volatile uint32_t DENALI_PHY_805;
- volatile uint32_t DENALI_PHY_806;
- volatile uint32_t DENALI_PHY_807;
- volatile uint32_t DENALI_PHY_808;
- volatile uint32_t DENALI_PHY_809;
- volatile uint32_t DENALI_PHY_810;
- volatile uint32_t DENALI_PHY_811;
- volatile uint32_t DENALI_PHY_812;
- volatile uint32_t DENALI_PHY_813;
- volatile uint32_t DENALI_PHY_814;
- volatile uint32_t DENALI_PHY_815;
- volatile uint32_t DENALI_PHY_816;
- volatile uint32_t DENALI_PHY_817;
- volatile uint32_t DENALI_PHY_818;
- volatile uint32_t DENALI_PHY_819;
- volatile uint32_t DENALI_PHY_820;
- volatile uint32_t DENALI_PHY_821;
- volatile uint32_t DENALI_PHY_822;
- volatile uint32_t DENALI_PHY_823;
- volatile uint32_t DENALI_PHY_824;
- volatile uint32_t DENALI_PHY_825;
- volatile uint32_t DENALI_PHY_826;
- volatile uint32_t DENALI_PHY_827;
- volatile uint32_t DENALI_PHY_828;
- volatile uint32_t DENALI_PHY_829;
- volatile uint32_t DENALI_PHY_830;
- volatile uint32_t DENALI_PHY_831;
- volatile uint32_t DENALI_PHY_832;
- volatile uint32_t DENALI_PHY_833;
- volatile uint32_t DENALI_PHY_834;
- volatile uint32_t DENALI_PHY_835;
- volatile uint32_t DENALI_PHY_836;
- volatile uint32_t DENALI_PHY_837;
- volatile uint32_t DENALI_PHY_838;
- volatile uint32_t DENALI_PHY_839;
- volatile uint32_t DENALI_PHY_840;
- volatile uint32_t DENALI_PHY_841;
- volatile uint32_t DENALI_PHY_842;
- volatile uint32_t DENALI_PHY_843;
- volatile uint32_t DENALI_PHY_844;
- volatile uint32_t DENALI_PHY_845;
- volatile uint32_t DENALI_PHY_846;
- volatile uint32_t DENALI_PHY_847;
- volatile uint32_t DENALI_PHY_848;
- volatile uint32_t DENALI_PHY_849;
- volatile uint32_t DENALI_PHY_850;
- volatile uint32_t DENALI_PHY_851;
- volatile uint32_t DENALI_PHY_852;
- volatile uint32_t DENALI_PHY_853;
- volatile uint32_t DENALI_PHY_854;
- volatile uint32_t DENALI_PHY_855;
- volatile uint32_t DENALI_PHY_856;
- volatile uint32_t DENALI_PHY_857;
- volatile uint32_t DENALI_PHY_858;
- volatile uint32_t DENALI_PHY_859;
- volatile uint32_t DENALI_PHY_860;
- volatile uint32_t DENALI_PHY_861;
- volatile uint32_t DENALI_PHY_862;
- volatile uint32_t DENALI_PHY_863;
- volatile uint32_t DENALI_PHY_864;
- volatile uint32_t DENALI_PHY_865;
- volatile uint32_t DENALI_PHY_866;
- volatile uint32_t DENALI_PHY_867;
- volatile uint32_t DENALI_PHY_868;
- volatile uint32_t DENALI_PHY_869;
- volatile uint32_t DENALI_PHY_870;
- volatile uint32_t DENALI_PHY_871;
- volatile uint32_t DENALI_PHY_872;
- volatile uint32_t DENALI_PHY_873;
- volatile uint32_t DENALI_PHY_874;
- volatile uint32_t DENALI_PHY_875;
- volatile uint32_t DENALI_PHY_876;
- volatile uint32_t DENALI_PHY_877;
- volatile uint32_t DENALI_PHY_878;
- volatile uint32_t DENALI_PHY_879;
- volatile uint32_t DENALI_PHY_880;
- volatile uint32_t DENALI_PHY_881;
- volatile uint32_t DENALI_PHY_882;
- volatile uint32_t DENALI_PHY_883;
- volatile uint32_t DENALI_PHY_884;
- volatile uint32_t DENALI_PHY_885;
- volatile uint32_t DENALI_PHY_886;
- volatile uint32_t DENALI_PHY_887;
- volatile uint32_t DENALI_PHY_888;
- volatile uint32_t DENALI_PHY_889;
- volatile uint32_t DENALI_PHY_890;
- volatile uint32_t DENALI_PHY_891;
- volatile uint32_t DENALI_PHY_892;
- volatile uint32_t DENALI_PHY_893;
- volatile uint32_t DENALI_PHY_894;
- volatile uint32_t DENALI_PHY_895;
- volatile uint32_t DENALI_PHY_896;
- volatile uint32_t DENALI_PHY_897;
- volatile uint32_t DENALI_PHY_898;
- volatile uint32_t DENALI_PHY_899;
- volatile uint32_t DENALI_PHY_900;
- volatile uint32_t DENALI_PHY_901;
- volatile uint32_t DENALI_PHY_902;
- volatile uint32_t DENALI_PHY_903;
- volatile uint32_t DENALI_PHY_904;
- volatile uint32_t DENALI_PHY_905;
- volatile uint32_t DENALI_PHY_906;
- volatile uint32_t DENALI_PHY_907;
- volatile char pad__5[0x1D0U];
- volatile uint32_t DENALI_PHY_1024;
- volatile uint32_t DENALI_PHY_1025;
- volatile uint32_t DENALI_PHY_1026;
- volatile uint32_t DENALI_PHY_1027;
- volatile uint32_t DENALI_PHY_1028;
- volatile uint32_t DENALI_PHY_1029;
- volatile uint32_t DENALI_PHY_1030;
- volatile uint32_t DENALI_PHY_1031;
- volatile uint32_t DENALI_PHY_1032;
- volatile uint32_t DENALI_PHY_1033;
- volatile uint32_t DENALI_PHY_1034;
- volatile uint32_t DENALI_PHY_1035;
- volatile uint32_t DENALI_PHY_1036;
- volatile uint32_t DENALI_PHY_1037;
- volatile uint32_t DENALI_PHY_1038;
- volatile uint32_t DENALI_PHY_1039;
- volatile uint32_t DENALI_PHY_1040;
- volatile uint32_t DENALI_PHY_1041;
- volatile uint32_t DENALI_PHY_1042;
- volatile uint32_t DENALI_PHY_1043;
- volatile uint32_t DENALI_PHY_1044;
- volatile uint32_t DENALI_PHY_1045;
- volatile uint32_t DENALI_PHY_1046;
- volatile uint32_t DENALI_PHY_1047;
- volatile uint32_t DENALI_PHY_1048;
- volatile uint32_t DENALI_PHY_1049;
- volatile uint32_t DENALI_PHY_1050;
- volatile uint32_t DENALI_PHY_1051;
- volatile uint32_t DENALI_PHY_1052;
- volatile uint32_t DENALI_PHY_1053;
- volatile uint32_t DENALI_PHY_1054;
- volatile uint32_t DENALI_PHY_1055;
- volatile uint32_t DENALI_PHY_1056;
- volatile uint32_t DENALI_PHY_1057;
- volatile uint32_t DENALI_PHY_1058;
- volatile uint32_t DENALI_PHY_1059;
- volatile uint32_t DENALI_PHY_1060;
- volatile uint32_t DENALI_PHY_1061;
- volatile uint32_t DENALI_PHY_1062;
- volatile uint32_t DENALI_PHY_1063;
- volatile uint32_t DENALI_PHY_1064;
- volatile uint32_t DENALI_PHY_1065;
- volatile uint32_t DENALI_PHY_1066;
- volatile uint32_t DENALI_PHY_1067;
- volatile uint32_t DENALI_PHY_1068;
- volatile uint32_t DENALI_PHY_1069;
- volatile uint32_t DENALI_PHY_1070;
- volatile uint32_t DENALI_PHY_1071;
- volatile uint32_t DENALI_PHY_1072;
- volatile uint32_t DENALI_PHY_1073;
- volatile uint32_t DENALI_PHY_1074;
- volatile uint32_t DENALI_PHY_1075;
- volatile char pad__6[0x330U];
- volatile uint32_t DENALI_PHY_1280;
- volatile uint32_t DENALI_PHY_1281;
- volatile uint32_t DENALI_PHY_1282;
- volatile uint32_t DENALI_PHY_1283;
- volatile uint32_t DENALI_PHY_1284;
- volatile uint32_t DENALI_PHY_1285;
- volatile uint32_t DENALI_PHY_1286;
- volatile uint32_t DENALI_PHY_1287;
- volatile uint32_t DENALI_PHY_1288;
- volatile uint32_t DENALI_PHY_1289;
- volatile uint32_t DENALI_PHY_1290;
- volatile uint32_t DENALI_PHY_1291;
- volatile uint32_t DENALI_PHY_1292;
- volatile uint32_t DENALI_PHY_1293;
- volatile uint32_t DENALI_PHY_1294;
- volatile uint32_t DENALI_PHY_1295;
- volatile uint32_t DENALI_PHY_1296;
- volatile uint32_t DENALI_PHY_1297;
- volatile uint32_t DENALI_PHY_1298;
- volatile uint32_t DENALI_PHY_1299;
- volatile uint32_t DENALI_PHY_1300;
- volatile uint32_t DENALI_PHY_1301;
- volatile uint32_t DENALI_PHY_1302;
- volatile uint32_t DENALI_PHY_1303;
- volatile uint32_t DENALI_PHY_1304;
- volatile uint32_t DENALI_PHY_1305;
- volatile uint32_t DENALI_PHY_1306;
- volatile uint32_t DENALI_PHY_1307;
- volatile uint32_t DENALI_PHY_1308;
- volatile uint32_t DENALI_PHY_1309;
- volatile uint32_t DENALI_PHY_1310;
- volatile uint32_t DENALI_PHY_1311;
- volatile uint32_t DENALI_PHY_1312;
- volatile uint32_t DENALI_PHY_1313;
- volatile uint32_t DENALI_PHY_1314;
- volatile uint32_t DENALI_PHY_1315;
- volatile uint32_t DENALI_PHY_1316;
- volatile uint32_t DENALI_PHY_1317;
- volatile uint32_t DENALI_PHY_1318;
- volatile uint32_t DENALI_PHY_1319;
- volatile uint32_t DENALI_PHY_1320;
- volatile uint32_t DENALI_PHY_1321;
- volatile uint32_t DENALI_PHY_1322;
- volatile uint32_t DENALI_PHY_1323;
- volatile uint32_t DENALI_PHY_1324;
- volatile uint32_t DENALI_PHY_1325;
- volatile uint32_t DENALI_PHY_1326;
- volatile uint32_t DENALI_PHY_1327;
- volatile uint32_t DENALI_PHY_1328;
- volatile uint32_t DENALI_PHY_1329;
- volatile uint32_t DENALI_PHY_1330;
- volatile uint32_t DENALI_PHY_1331;
- volatile uint32_t DENALI_PHY_1332;
- volatile uint32_t DENALI_PHY_1333;
- volatile uint32_t DENALI_PHY_1334;
- volatile uint32_t DENALI_PHY_1335;
- volatile uint32_t DENALI_PHY_1336;
- volatile uint32_t DENALI_PHY_1337;
- volatile uint32_t DENALI_PHY_1338;
- volatile uint32_t DENALI_PHY_1339;
- volatile uint32_t DENALI_PHY_1340;
- volatile uint32_t DENALI_PHY_1341;
- volatile uint32_t DENALI_PHY_1342;
- volatile uint32_t DENALI_PHY_1343;
- volatile uint32_t DENALI_PHY_1344;
- volatile uint32_t DENALI_PHY_1345;
- volatile uint32_t DENALI_PHY_1346;
- volatile uint32_t DENALI_PHY_1347;
- volatile uint32_t DENALI_PHY_1348;
- volatile uint32_t DENALI_PHY_1349;
- volatile uint32_t DENALI_PHY_1350;
- volatile uint32_t DENALI_PHY_1351;
- volatile uint32_t DENALI_PHY_1352;
- volatile uint32_t DENALI_PHY_1353;
- volatile uint32_t DENALI_PHY_1354;
- volatile uint32_t DENALI_PHY_1355;
- volatile uint32_t DENALI_PHY_1356;
- volatile uint32_t DENALI_PHY_1357;
- volatile uint32_t DENALI_PHY_1358;
- volatile uint32_t DENALI_PHY_1359;
- volatile uint32_t DENALI_PHY_1360;
- volatile uint32_t DENALI_PHY_1361;
- volatile uint32_t DENALI_PHY_1362;
- volatile uint32_t DENALI_PHY_1363;
- volatile uint32_t DENALI_PHY_1364;
- volatile uint32_t DENALI_PHY_1365;
- volatile uint32_t DENALI_PHY_1366;
- volatile uint32_t DENALI_PHY_1367;
- volatile uint32_t DENALI_PHY_1368;
- volatile uint32_t DENALI_PHY_1369;
- volatile uint32_t DENALI_PHY_1370;
- volatile uint32_t DENALI_PHY_1371;
- volatile uint32_t DENALI_PHY_1372;
- volatile uint32_t DENALI_PHY_1373;
- volatile uint32_t DENALI_PHY_1374;
- volatile uint32_t DENALI_PHY_1375;
- volatile uint32_t DENALI_PHY_1376;
- volatile uint32_t DENALI_PHY_1377;
- volatile uint32_t DENALI_PHY_1378;
- volatile uint32_t DENALI_PHY_1379;
- volatile uint32_t DENALI_PHY_1380;
- volatile uint32_t DENALI_PHY_1381;
- volatile uint32_t DENALI_PHY_1382;
- volatile uint32_t DENALI_PHY_1383;
- volatile uint32_t DENALI_PHY_1384;
- volatile uint32_t DENALI_PHY_1385;
- volatile uint32_t DENALI_PHY_1386;
- volatile uint32_t DENALI_PHY_1387;
- volatile uint32_t DENALI_PHY_1388;
- volatile uint32_t DENALI_PHY_1389;
- volatile uint32_t DENALI_PHY_1390;
- volatile uint32_t DENALI_PHY_1391;
- volatile uint32_t DENALI_PHY_1392;
- volatile uint32_t DENALI_PHY_1393;
- volatile uint32_t DENALI_PHY_1394;
- volatile uint32_t DENALI_PHY_1395;
- volatile uint32_t DENALI_PHY_1396;
- volatile uint32_t DENALI_PHY_1397;
- volatile uint32_t DENALI_PHY_1398;
- volatile uint32_t DENALI_PHY_1399;
- volatile uint32_t DENALI_PHY_1400;
- volatile uint32_t DENALI_PHY_1401;
- volatile uint32_t DENALI_PHY_1402;
- volatile uint32_t DENALI_PHY_1403;
- volatile uint32_t DENALI_PHY_1404;
- volatile uint32_t DENALI_PHY_1405;
- volatile uint32_t DENALI_PHY_1406;
- volatile uint32_t DENALI_PHY_1407;
- volatile uint32_t DENALI_PHY_1408;
- volatile uint32_t DENALI_PHY_1409;
- volatile uint32_t DENALI_PHY_1410;
- volatile uint32_t DENALI_PHY_1411;
- volatile uint32_t DENALI_PHY_1412;
- volatile uint32_t DENALI_PHY_1413;
- volatile uint32_t DENALI_PHY_1414;
- volatile uint32_t DENALI_PHY_1415;
- volatile uint32_t DENALI_PHY_1416;
- volatile uint32_t DENALI_PHY_1417;
- volatile uint32_t DENALI_PHY_1418;
- volatile uint32_t DENALI_PHY_1419;
- volatile uint32_t DENALI_PHY_1420;
- volatile uint32_t DENALI_PHY_1421;
- volatile uint32_t DENALI_PHY_1422;
-} lpddr4_ctlregs;
-
-#endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
deleted file mode 100644
index 274a976..0000000
--- a/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
+++ /dev/null
@@ -1,7793 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
- */
-
-#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
-#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
-
-#define LPDDR4__DENALI_CTL_0_READ_MASK 0xFFFF0F01U
-#define LPDDR4__DENALI_CTL_0_WRITE_MASK 0xFFFF0F01U
-#define LPDDR4__DENALI_CTL_0__START_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_0__START_SHIFT 0U
-#define LPDDR4__DENALI_CTL_0__START_WIDTH 1U
-#define LPDDR4__DENALI_CTL_0__START_WOCLR 0U
-#define LPDDR4__DENALI_CTL_0__START_WOSET 0U
-#define LPDDR4__START__REG DENALI_CTL_0
-#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
-
-#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH 4U
-#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
-#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
-
-#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT 16U
-#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH 16U
-#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
-#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
-
-#define LPDDR4__DENALI_CTL_1_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_1_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH 32U
-#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
-#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
-
-#define LPDDR4__DENALI_CTL_2_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_2_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH 32U
-#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
-#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
-
-#define LPDDR4__DENALI_CTL_3_READ_MASK 0xFF030F1FU
-#define LPDDR4__DENALI_CTL_3_WRITE_MASK 0xFF030F1FU
-#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT 0U
-#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH 5U
-#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
-#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
-
-#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT 8U
-#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH 4U
-#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
-#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
-
-#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT 16U
-#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH 2U
-#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
-#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
-
-#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT 24U
-#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH 8U
-#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
-#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
-
-#define LPDDR4__DENALI_CTL_4_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_4_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT 0U
-#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH 8U
-#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
-#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
-
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT 8U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH 8U
-#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
-#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
-
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT 16U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH 8U
-#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
-#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
-
-#define LPDDR4__DENALI_CTL_5_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_5_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT 0U
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH 16U
-#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
-#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
-
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT 16U
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH 8U
-#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
-#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
-
-#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT 24U
-#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH 8U
-#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
-#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
-
-#define LPDDR4__DENALI_CTL_6_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_6_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT 0U
-#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH 8U
-#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
-#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
-
-#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT 8U
-#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH 8U
-#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
-#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
-
-#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT 16U
-#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH 8U
-#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
-#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
-
-#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT 24U
-#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH 8U
-#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
-#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
-
-#define LPDDR4__DENALI_CTL_7_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_7_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH 24U
-#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
-#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
-
-#define LPDDR4__DENALI_CTL_8_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_8_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH 24U
-#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
-#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
-
-#define LPDDR4__DENALI_CTL_9_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_9_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH 24U
-#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
-#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
-
-#define LPDDR4__DENALI_CTL_10_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_10_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH 24U
-#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
-#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
-
-#define LPDDR4__DENALI_CTL_11_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_11_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH 24U
-#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
-#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
-
-#define LPDDR4__DENALI_CTL_12_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_12_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH 24U
-#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
-#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
-
-#define LPDDR4__DENALI_CTL_13_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_13_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH 24U
-#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
-#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
-
-#define LPDDR4__DENALI_CTL_14_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_14_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH 24U
-#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
-#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
-
-#define LPDDR4__DENALI_CTL_15_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_15_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH 24U
-#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
-#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
-
-#define LPDDR4__DENALI_CTL_16_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_16_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH 24U
-#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
-#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
-
-#define LPDDR4__DENALI_CTL_17_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_17_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH 24U
-#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
-#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
-
-#define LPDDR4__DENALI_CTL_18_READ_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_18_WRITE_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH 24U
-#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
-#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
-
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT 24U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET 0U
-#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
-#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
-
-#define LPDDR4__DENALI_CTL_19_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_19_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET 0U
-#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
-#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET 0U
-#define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19
-#define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS
-
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT 16U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET 0U
-#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19
-#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT
-
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT 24U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET 0U
-#define LPDDR4__ODT_VALUE__REG DENALI_CTL_19
-#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE
-
-#define LPDDR4__DENALI_CTL_20_READ_MASK 0x03013F01U
-#define LPDDR4__DENALI_CTL_20_WRITE_MASK 0x03013F01U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET 0U
-#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
-#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
-
-#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK 0x00003F00U
-#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT 8U
-#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH 6U
-#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20
-#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR
-
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET 0U
-#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20
-#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE
-
-#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK 0x03000000U
-#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT 24U
-#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH 2U
-#define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20
-#define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT
-
-#define LPDDR4__DENALI_CTL_21_READ_MASK 0x1F1F1F03U
-#define LPDDR4__DENALI_CTL_21_WRITE_MASK 0x1F1F1F03U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT 0U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH 2U
-#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21
-#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ
-
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH 5U
-#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
-#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
-
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH 5U
-#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
-#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
-
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH 5U
-#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21
-#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2
-
-#define LPDDR4__DENALI_CTL_22_READ_MASK 0x00030303U
-#define LPDDR4__DENALI_CTL_22_WRITE_MASK 0x00030303U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH 2U
-#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
-#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
-
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH 2U
-#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
-#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
-
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH 2U
-#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
-#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
-
-#define LPDDR4__DENALI_CTL_23_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_23_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT 0U
-#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH 32U
-#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
-#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
-
-#define LPDDR4__DENALI_CTL_24_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_24_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH 32U
-#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
-#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
-
-#define LPDDR4__DENALI_CTL_25_READ_MASK 0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_25_WRITE_MASK 0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH 1U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR 0U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET 0U
-#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25
-#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0
-
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK 0xFFFFFF00U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH 24U
-#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25
-#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1
-
-#define LPDDR4__DENALI_CTL_26_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_CTL_26_WRITE_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH 8U
-#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26
-#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2
-
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT 8U
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH 8U
-#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26
-#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3
-
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET 0U
-#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26
-#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE
-
-#define LPDDR4__DENALI_CTL_27_READ_MASK 0xFF0F7FFFU
-#define LPDDR4__DENALI_CTL_27_WRITE_MASK 0xFF0F7FFFU
-#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK 0x00007FFFU
-#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT 0U
-#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH 15U
-#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27
-#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD
-
-#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT 16U
-#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH 4U
-#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27
-#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES
-
-#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH 8U
-#define LPDDR4__TOSCO_F0__REG DENALI_CTL_27
-#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0
-
-#define LPDDR4__DENALI_CTL_28_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_28_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH 8U
-#define LPDDR4__TOSCO_F1__REG DENALI_CTL_28
-#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1
-
-#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH 8U
-#define LPDDR4__TOSCO_F2__REG DENALI_CTL_28
-#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2
-
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT 16U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH 8U
-#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28
-#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT 24U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH 8U
-#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28
-#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_29_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_29_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT 0U
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH 8U
-#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29
-#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT
-
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT 8U
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH 8U
-#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29
-#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT 16U
-#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH 16U
-#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29
-#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT
-
-#define LPDDR4__DENALI_CTL_30_READ_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_CTL_30_WRITE_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT 0U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH 1U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR 0U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET 0U
-#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30
-#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST
-
-#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH 16U
-#define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30
-#define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0
-
-#define LPDDR4__DENALI_CTL_31_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_31_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH 16U
-#define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31
-#define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0
-
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH 16U
-#define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31
-#define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0
-
-#define LPDDR4__DENALI_CTL_32_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_32_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH 16U
-#define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32
-#define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0
-
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH 16U
-#define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32
-#define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1
-
-#define LPDDR4__DENALI_CTL_33_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_33_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH 16U
-#define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33
-#define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1
-
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH 16U
-#define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33
-#define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1
-
-#define LPDDR4__DENALI_CTL_34_READ_MASK 0x7F7FFFFFU
-#define LPDDR4__DENALI_CTL_34_WRITE_MASK 0x7F7FFFFFU
-#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH 16U
-#define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34
-#define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1
-
-#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK 0x007F0000U
-#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH 7U
-#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34
-#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0
-
-#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK 0x7F000000U
-#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH 7U
-#define LPDDR4__WRLAT_F0__REG DENALI_CTL_34
-#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0
-
-#define LPDDR4__DENALI_CTL_35_READ_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_35_WRITE_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH 7U
-#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35
-#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1
-
-#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK 0x00007F00U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH 7U
-#define LPDDR4__WRLAT_F1__REG DENALI_CTL_35
-#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1
-
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK 0x007F0000U
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH 7U
-#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35
-#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2
-
-#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK 0x7F000000U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH 7U
-#define LPDDR4__WRLAT_F2__REG DENALI_CTL_35
-#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2
-
-#define LPDDR4__DENALI_CTL_36_READ_MASK 0x00FF1F07U
-#define LPDDR4__DENALI_CTL_36_WRITE_MASK 0x00FF1F07U
-#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT 0U
-#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH 3U
-#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36
-#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL
-
-#define LPDDR4__DENALI_CTL_36__TCCD_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT 8U
-#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH 5U
-#define LPDDR4__TCCD__REG DENALI_CTL_36
-#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD
-
-#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH 8U
-#define LPDDR4__TRRD_F0__REG DENALI_CTL_36
-#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0
-
-#define LPDDR4__DENALI_CTL_37_READ_MASK 0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_37_WRITE_MASK 0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK 0x000001FFU
-#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH 9U
-#define LPDDR4__TRC_F0__REG DENALI_CTL_37
-#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0
-
-#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH 8U
-#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37
-#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0
-
-#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK 0x3F000000U
-#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH 6U
-#define LPDDR4__TWTR_F0__REG DENALI_CTL_37
-#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0
-
-#define LPDDR4__DENALI_CTL_38_READ_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_38_WRITE_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH 8U
-#define LPDDR4__TRP_F0__REG DENALI_CTL_38
-#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0
-
-#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK 0x0001FF00U
-#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH 9U
-#define LPDDR4__TFAW_F0__REG DENALI_CTL_38
-#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0
-
-#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH 8U
-#define LPDDR4__TRRD_F1__REG DENALI_CTL_38
-#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1
-
-#define LPDDR4__DENALI_CTL_39_READ_MASK 0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_39_WRITE_MASK 0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK 0x000001FFU
-#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH 9U
-#define LPDDR4__TRC_F1__REG DENALI_CTL_39
-#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1
-
-#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH 8U
-#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39
-#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1
-
-#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK 0x3F000000U
-#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH 6U
-#define LPDDR4__TWTR_F1__REG DENALI_CTL_39
-#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1
-
-#define LPDDR4__DENALI_CTL_40_READ_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_40_WRITE_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH 8U
-#define LPDDR4__TRP_F1__REG DENALI_CTL_40
-#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1
-
-#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK 0x0001FF00U
-#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH 9U
-#define LPDDR4__TFAW_F1__REG DENALI_CTL_40
-#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1
-
-#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH 8U
-#define LPDDR4__TRRD_F2__REG DENALI_CTL_40
-#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2
-
-#define LPDDR4__DENALI_CTL_41_READ_MASK 0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_41_WRITE_MASK 0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK 0x000001FFU
-#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH 9U
-#define LPDDR4__TRC_F2__REG DENALI_CTL_41
-#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2
-
-#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH 8U
-#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41
-#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2
-
-#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK 0x3F000000U
-#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH 6U
-#define LPDDR4__TWTR_F2__REG DENALI_CTL_41
-#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2
-
-#define LPDDR4__DENALI_CTL_42_READ_MASK 0x3F01FFFFU
-#define LPDDR4__DENALI_CTL_42_WRITE_MASK 0x3F01FFFFU
-#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH 8U
-#define LPDDR4__TRP_F2__REG DENALI_CTL_42
-#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2
-
-#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK 0x0001FF00U
-#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH 9U
-#define LPDDR4__TFAW_F2__REG DENALI_CTL_42
-#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2
-
-#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK 0x3F000000U
-#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT 24U
-#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH 6U
-#define LPDDR4__TCCDMW__REG DENALI_CTL_42
-#define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW
-
-#define LPDDR4__DENALI_CTL_43_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_43_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH 8U
-#define LPDDR4__TRTP_F0__REG DENALI_CTL_43
-#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0
-
-#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH 8U
-#define LPDDR4__TMRD_F0__REG DENALI_CTL_43
-#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0
-
-#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH 8U
-#define LPDDR4__TMOD_F0__REG DENALI_CTL_43
-#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0
-
-#define LPDDR4__DENALI_CTL_44_READ_MASK 0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_44_WRITE_MASK 0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH 17U
-#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44
-#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0
-
-#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH 5U
-#define LPDDR4__TCKE_F0__REG DENALI_CTL_44
-#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0
-
-#define LPDDR4__DENALI_CTL_45_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_45_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH 8U
-#define LPDDR4__TCKESR_F0__REG DENALI_CTL_45
-#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0
-
-#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH 8U
-#define LPDDR4__TRTP_F1__REG DENALI_CTL_45
-#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1
-
-#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH 8U
-#define LPDDR4__TMRD_F1__REG DENALI_CTL_45
-#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1
-
-#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH 8U
-#define LPDDR4__TMOD_F1__REG DENALI_CTL_45
-#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1
-
-#define LPDDR4__DENALI_CTL_46_READ_MASK 0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_46_WRITE_MASK 0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH 17U
-#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46
-#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1
-
-#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH 5U
-#define LPDDR4__TCKE_F1__REG DENALI_CTL_46
-#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1
-
-#define LPDDR4__DENALI_CTL_47_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_47_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH 8U
-#define LPDDR4__TCKESR_F1__REG DENALI_CTL_47
-#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1
-
-#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH 8U
-#define LPDDR4__TRTP_F2__REG DENALI_CTL_47
-#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2
-
-#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH 8U
-#define LPDDR4__TMRD_F2__REG DENALI_CTL_47
-#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2
-
-#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH 8U
-#define LPDDR4__TMOD_F2__REG DENALI_CTL_47
-#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2
-
-#define LPDDR4__DENALI_CTL_48_READ_MASK 0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_48_WRITE_MASK 0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH 17U
-#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48
-#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2
-
-#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH 5U
-#define LPDDR4__TCKE_F2__REG DENALI_CTL_48
-#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2
-
-#define LPDDR4__DENALI_CTL_49_READ_MASK 0x070707FFU
-#define LPDDR4__DENALI_CTL_49_WRITE_MASK 0x070707FFU
-#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH 8U
-#define LPDDR4__TCKESR_F2__REG DENALI_CTL_49
-#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2
-
-#define LPDDR4__DENALI_CTL_49__TPPD_MASK 0x00000700U
-#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT 8U
-#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH 3U
-#define LPDDR4__TPPD__REG DENALI_CTL_49
-#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD
-
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK 0x00070000U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT 16U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH 3U
-#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49
-#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4
-
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT 24U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH 3U
-#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49
-#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5
-
-#define LPDDR4__DENALI_CTL_50_READ_MASK 0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_50_WRITE_MASK 0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT 0U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH 1U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR 0U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET 0U
-#define LPDDR4__WRITEINTERP__REG DENALI_CTL_50
-#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP
-
-#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH 8U
-#define LPDDR4__TRCD_F0__REG DENALI_CTL_50
-#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0
-
-#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH 8U
-#define LPDDR4__TWR_F0__REG DENALI_CTL_50
-#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0
-
-#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH 8U
-#define LPDDR4__TRCD_F1__REG DENALI_CTL_50
-#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1
-
-#define LPDDR4__DENALI_CTL_51_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_CTL_51_WRITE_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH 8U
-#define LPDDR4__TWR_F1__REG DENALI_CTL_51
-#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1
-
-#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH 8U
-#define LPDDR4__TRCD_F2__REG DENALI_CTL_51
-#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2
-
-#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH 8U
-#define LPDDR4__TWR_F2__REG DENALI_CTL_51
-#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2
-
-#define LPDDR4__DENALI_CTL_51__TMRR_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT 24U
-#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH 4U
-#define LPDDR4__TMRR__REG DENALI_CTL_51
-#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR
-
-#define LPDDR4__DENALI_CTL_52_READ_MASK 0x3F03FF1FU
-#define LPDDR4__DENALI_CTL_52_WRITE_MASK 0x3F03FF1FU
-#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT 0U
-#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH 5U
-#define LPDDR4__TCACKEL__REG DENALI_CTL_52
-#define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL
-
-#define LPDDR4__DENALI_CTL_52__TCAENT_MASK 0x0003FF00U
-#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT 8U
-#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH 10U
-#define LPDDR4__TCAENT__REG DENALI_CTL_52
-#define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT
-
-#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK 0x3F000000U
-#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT 24U
-#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH 6U
-#define LPDDR4__TCAMRD__REG DENALI_CTL_52
-#define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD
-
-#define LPDDR4__DENALI_CTL_53_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_53_WRITE_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT 0U
-#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH 5U
-#define LPDDR4__TCAEXT__REG DENALI_CTL_53
-#define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT
-
-#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT 8U
-#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH 5U
-#define LPDDR4__TCACKEH__REG DENALI_CTL_53
-#define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH
-
-#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH 5U
-#define LPDDR4__TMRZ_F0__REG DENALI_CTL_53
-#define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0
-
-#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH 5U
-#define LPDDR4__TMRZ_F1__REG DENALI_CTL_53
-#define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1
-
-#define LPDDR4__DENALI_CTL_54_READ_MASK 0x0101011FU
-#define LPDDR4__DENALI_CTL_54_WRITE_MASK 0x0101011FU
-#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH 5U
-#define LPDDR4__TMRZ_F2__REG DENALI_CTL_54
-#define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2
-
-#define LPDDR4__DENALI_CTL_54__AP_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_54__AP_SHIFT 8U
-#define LPDDR4__DENALI_CTL_54__AP_WIDTH 1U
-#define LPDDR4__DENALI_CTL_54__AP_WOCLR 0U
-#define LPDDR4__DENALI_CTL_54__AP_WOSET 0U
-#define LPDDR4__AP__REG DENALI_CTL_54
-#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP
-
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT 16U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH 1U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR 0U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET 0U
-#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54
-#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP
-
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT 24U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET 0U
-#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54
-#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT
-
-#define LPDDR4__DENALI_CTL_55_READ_MASK 0x1FFFFFFFU
-#define LPDDR4__DENALI_CTL_55_WRITE_MASK 0x1FFFFFFFU
-#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH 8U
-#define LPDDR4__TDAL_F0__REG DENALI_CTL_55
-#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0
-
-#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH 8U
-#define LPDDR4__TDAL_F1__REG DENALI_CTL_55
-#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1
-
-#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH 8U
-#define LPDDR4__TDAL_F2__REG DENALI_CTL_55
-#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2
-
-#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH 5U
-#define LPDDR4__BSTLEN__REG DENALI_CTL_55
-#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN
-
-#define LPDDR4__DENALI_CTL_56_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_56_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH 8U
-#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56
-#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0
-
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH 8U
-#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56
-#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0
-
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH 8U
-#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56
-#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0
-
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH 8U
-#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56
-#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1
-
-#define LPDDR4__DENALI_CTL_57_READ_MASK 0x0301FFFFU
-#define LPDDR4__DENALI_CTL_57_WRITE_MASK 0x0301FFFFU
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH 8U
-#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57
-#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1
-
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH 8U
-#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57
-#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1
-
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET 0U
-#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57
-#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE
-
-#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK 0x03000000U
-#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT 24U
-#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH 2U
-#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57
-#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6
-
-#define LPDDR4__DENALI_CTL_58_READ_MASK 0x0101017FU
-#define LPDDR4__DENALI_CTL_58_WRITE_MASK 0x0101017FU
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT 0U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH 7U
-#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58
-#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7
-
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET 0U
-#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58
-#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN
-
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT 16U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH 1U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR 0U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET 0U
-#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58
-#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8
-
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT 24U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH 1U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR 0U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET 0U
-#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58
-#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM
-
-#define LPDDR4__DENALI_CTL_59_READ_MASK 0x07010100U
-#define LPDDR4__DENALI_CTL_59_WRITE_MASK 0x07010100U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT 0U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH 1U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR 0U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET 0U
-#define LPDDR4__AREFRESH__REG DENALI_CTL_59
-#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH
-
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET 0U
-#define LPDDR4__AREF_STATUS__REG DENALI_CTL_59
-#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS
-
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET 0U
-#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59
-#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE
-
-#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT 24U
-#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH 3U
-#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59
-#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9
-
-#define LPDDR4__DENALI_CTL_60_READ_MASK 0x0003FF3FU
-#define LPDDR4__DENALI_CTL_60_WRITE_MASK 0x0003FF3FU
-#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK 0x0000003FU
-#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT 0U
-#define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH 6U
-#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60
-#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH
-
-#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK 0x0003FF00U
-#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH 10U
-#define LPDDR4__TRFC_F0__REG DENALI_CTL_60
-#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0
-
-#define LPDDR4__DENALI_CTL_61_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_61_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH 20U
-#define LPDDR4__TREF_F0__REG DENALI_CTL_61
-#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0
-
-#define LPDDR4__DENALI_CTL_62_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_62_WRITE_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH 10U
-#define LPDDR4__TRFC_F1__REG DENALI_CTL_62
-#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1
-
-#define LPDDR4__DENALI_CTL_63_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_63_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH 20U
-#define LPDDR4__TREF_F1__REG DENALI_CTL_63
-#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1
-
-#define LPDDR4__DENALI_CTL_64_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_64_WRITE_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH 10U
-#define LPDDR4__TRFC_F2__REG DENALI_CTL_64
-#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2
-
-#define LPDDR4__DENALI_CTL_65_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_65_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH 20U
-#define LPDDR4__TREF_F2__REG DENALI_CTL_65
-#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2
-
-#define LPDDR4__DENALI_CTL_66_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_66_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT 0U
-#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH 20U
-#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66
-#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL
-
-#define LPDDR4__DENALI_CTL_67_READ_MASK 0x03FF0101U
-#define LPDDR4__DENALI_CTL_67_WRITE_MASK 0x03FF0101U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET 0U
-#define LPDDR4__PBR_EN__REG DENALI_CTL_67
-#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN
-
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT 8U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH 1U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR 0U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET 0U
-#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67
-#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER
-
-#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH 10U
-#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67
-#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0
-
-#define LPDDR4__DENALI_CTL_68_READ_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_68_WRITE_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH 16U
-#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68
-#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0
-
-#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH 10U
-#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68
-#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1
-
-#define LPDDR4__DENALI_CTL_69_READ_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_69_WRITE_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH 16U
-#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69
-#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1
-
-#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH 10U
-#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69
-#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2
-
-#define LPDDR4__DENALI_CTL_70_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_70_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH 16U
-#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70
-#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2
-
-#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT 16U
-#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH 16U
-#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70
-#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT
-
-#define LPDDR4__DENALI_CTL_71_READ_MASK 0x1F1F010FU
-#define LPDDR4__DENALI_CTL_71_WRITE_MASK 0x1F1F010FU
-#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT 0U
-#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH 4U
-#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71
-#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY
-
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET 0U
-#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71
-#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN
-
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_SHIFT 16U
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD_WIDTH 5U
-#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_71
-#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_EN_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT 24U
-#define LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH 5U
-#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71
-#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_72_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_72_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH 16U
-#define LPDDR4__TPDEX_F0__REG DENALI_CTL_72
-#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0
-
-#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH 16U
-#define LPDDR4__TPDEX_F1__REG DENALI_CTL_72
-#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1
-
-#define LPDDR4__DENALI_CTL_73_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_73_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH 16U
-#define LPDDR4__TPDEX_F2__REG DENALI_CTL_73
-#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2
-
-#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH 8U
-#define LPDDR4__TMRRI_F0__REG DENALI_CTL_73
-#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0
-
-#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH 8U
-#define LPDDR4__TMRRI_F1__REG DENALI_CTL_73
-#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1
-
-#define LPDDR4__DENALI_CTL_74_READ_MASK 0x1F1F1FFFU
-#define LPDDR4__DENALI_CTL_74_WRITE_MASK 0x1F1F1FFFU
-#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH 8U
-#define LPDDR4__TMRRI_F2__REG DENALI_CTL_74
-#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2
-
-#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH 5U
-#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74
-#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0
-
-#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH 5U
-#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74
-#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0
-
-#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH 5U
-#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74
-#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0
-
-#define LPDDR4__DENALI_CTL_75_READ_MASK 0x1F010F1FU
-#define LPDDR4__DENALI_CTL_75_WRITE_MASK 0x1F010F1FU
-#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH 5U
-#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75
-#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0
-
-#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH 4U
-#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75
-#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0
-
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH 1U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR 0U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET 0U
-#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75
-#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0
-
-#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH 5U
-#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75
-#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1
-
-#define LPDDR4__DENALI_CTL_76_READ_MASK 0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_76_WRITE_MASK 0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH 5U
-#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76
-#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1
-
-#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH 5U
-#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76
-#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1
-
-#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH 5U
-#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76
-#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1
-
-#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH 4U
-#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76
-#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1
-
-#define LPDDR4__DENALI_CTL_77_READ_MASK 0x1F1F1F01U
-#define LPDDR4__DENALI_CTL_77_WRITE_MASK 0x1F1F1F01U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH 1U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR 0U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET 0U
-#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77
-#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1
-
-#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH 5U
-#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77
-#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2
-
-#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH 5U
-#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77
-#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2
-
-#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH 5U
-#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77
-#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2
-
-#define LPDDR4__DENALI_CTL_78_READ_MASK 0x00010F1FU
-#define LPDDR4__DENALI_CTL_78_WRITE_MASK 0x00010F1FU
-#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH 5U
-#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78
-#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2
-
-#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH 4U
-#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78
-#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2
-
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH 1U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR 0U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET 0U
-#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78
-#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2
-
-#define LPDDR4__DENALI_CTL_79_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_79_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH 16U
-#define LPDDR4__TXSR_F0__REG DENALI_CTL_79
-#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0
-
-#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH 16U
-#define LPDDR4__TXSNR_F0__REG DENALI_CTL_79
-#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0
-
-#define LPDDR4__DENALI_CTL_80_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_80_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH 16U
-#define LPDDR4__TXSR_F1__REG DENALI_CTL_80
-#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1
-
-#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH 16U
-#define LPDDR4__TXSNR_F1__REG DENALI_CTL_80
-#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1
-
-#define LPDDR4__DENALI_CTL_81_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_81_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH 16U
-#define LPDDR4__TXSR_F2__REG DENALI_CTL_81
-#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2
-
-#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH 16U
-#define LPDDR4__TXSNR_F2__REG DENALI_CTL_81
-#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2
-
-#define LPDDR4__DENALI_CTL_82_READ_MASK 0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_82_WRITE_MASK 0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH 5U
-#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82
-#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0
-
-#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH 5U
-#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82
-#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0
-
-#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH 5U
-#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82
-#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0
-
-#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH 8U
-#define LPDDR4__TSR_F0__REG DENALI_CTL_82
-#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0
-
-#define LPDDR4__DENALI_CTL_83_READ_MASK 0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_83_WRITE_MASK 0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH 3U
-#define LPDDR4__TESCKE_F0__REG DENALI_CTL_83
-#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0
-
-#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH 5U
-#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83
-#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0
-
-#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH 5U
-#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83
-#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0
-
-#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH 5U
-#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83
-#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0
-
-#define LPDDR4__DENALI_CTL_84_READ_MASK 0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_84_WRITE_MASK 0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH 5U
-#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84
-#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1
-
-#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH 5U
-#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84
-#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1
-
-#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH 5U
-#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84
-#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1
-
-#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH 8U
-#define LPDDR4__TSR_F1__REG DENALI_CTL_84
-#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1
-
-#define LPDDR4__DENALI_CTL_85_READ_MASK 0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_85_WRITE_MASK 0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH 3U
-#define LPDDR4__TESCKE_F1__REG DENALI_CTL_85
-#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1
-
-#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH 5U
-#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85
-#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1
-
-#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH 5U
-#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85
-#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1
-
-#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH 5U
-#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85
-#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1
-
-#define LPDDR4__DENALI_CTL_86_READ_MASK 0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_86_WRITE_MASK 0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH 5U
-#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86
-#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2
-
-#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH 5U
-#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86
-#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2
-
-#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH 5U
-#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86
-#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2
-
-#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH 8U
-#define LPDDR4__TSR_F2__REG DENALI_CTL_86
-#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2
-
-#define LPDDR4__DENALI_CTL_87_READ_MASK 0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_87_WRITE_MASK 0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH 3U
-#define LPDDR4__TESCKE_F2__REG DENALI_CTL_87
-#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2
-
-#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH 5U
-#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87
-#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2
-
-#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH 5U
-#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87
-#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2
-
-#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH 5U
-#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87
-#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2
-
-#define LPDDR4__DENALI_CTL_88_READ_MASK 0x07010101U
-#define LPDDR4__DENALI_CTL_88_WRITE_MASK 0x07010101U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT 0U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET 0U
-#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88
-#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT
-
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT 8U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH 1U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR 0U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET 0U
-#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88
-#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10
-
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT 16U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH 1U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR 0U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET 0U
-#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88
-#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH
-
-#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT 24U
-#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH 3U
-#define LPDDR4__CKE_DELAY__REG DENALI_CTL_88
-#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY
-
-#define LPDDR4__DENALI_CTL_89_READ_MASK 0x01010300U
-#define LPDDR4__DENALI_CTL_89_WRITE_MASK 0x01010300U
-#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT 0U
-#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH 5U
-#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89
-#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11
-
-#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH 2U
-#define LPDDR4__DFS_STATUS__REG DENALI_CTL_89
-#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS
-
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET 0U
-#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89
-#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN
-
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET 0U
-#define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89
-#define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN
-
-#define LPDDR4__DENALI_CTL_90_READ_MASK 0x00010101U
-#define LPDDR4__DENALI_CTL_90_WRITE_MASK 0x00010101U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET 0U
-#define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90
-#define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN
-
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET 0U
-#define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90
-#define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN
-
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET 0U
-#define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90
-#define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN
-
-#define LPDDR4__DENALI_CTL_91_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_91_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_92_READ_MASK 0x0707FFFFU
-#define LPDDR4__DENALI_CTL_92_WRITE_MASK 0x0707FFFFU
-#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92
-#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK 0x00070000U
-#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT 16U
-#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH 3U
-#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92
-#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG
-
-#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT 24U
-#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH 3U
-#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92
-#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12
-
-#define LPDDR4__DENALI_CTL_93_READ_MASK 0xFFFFFF07U
-#define LPDDR4__DENALI_CTL_93_WRITE_MASK 0xFFFFFF07U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT 0U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH 3U
-#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93
-#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13
-
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT 8U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH 8U
-#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93
-#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14
-
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT 16U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH 8U
-#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93
-#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15
-
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT 24U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH 8U
-#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93
-#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16
-
-#define LPDDR4__DENALI_CTL_94_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_94_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_94
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_95_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_95_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_96_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_96_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_96
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_97_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_97_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_97
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_98_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_98_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_99_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_99_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_99
-#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99
-#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_100_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_100_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100
-#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100
-#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_101_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_101_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101
-#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_102_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_102_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102
-#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0
-
-#define LPDDR4__DENALI_CTL_103_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_103_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0
-
-#define LPDDR4__DENALI_CTL_104_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_104_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0
-
-#define LPDDR4__DENALI_CTL_105_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_105_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0
-
-#define LPDDR4__DENALI_CTL_106_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_106_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0
-
-#define LPDDR4__DENALI_CTL_107_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_107_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_108_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_108_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH 20U
-#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108
-#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0
-
-#define LPDDR4__DENALI_CTL_109_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_109_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109
-#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1
-
-#define LPDDR4__DENALI_CTL_110_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_110_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1
-
-#define LPDDR4__DENALI_CTL_111_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_111_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1
-
-#define LPDDR4__DENALI_CTL_112_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_112_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1
-
-#define LPDDR4__DENALI_CTL_113_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_113_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1
-
-#define LPDDR4__DENALI_CTL_114_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_114_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_115_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_115_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH 20U
-#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115
-#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1
-
-#define LPDDR4__DENALI_CTL_116_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_116_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116
-#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2
-
-#define LPDDR4__DENALI_CTL_117_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_117_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2
-
-#define LPDDR4__DENALI_CTL_118_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_118_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2
-
-#define LPDDR4__DENALI_CTL_119_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_119_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2
-
-#define LPDDR4__DENALI_CTL_120_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_120_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH 32U
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120
-#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2
-
-#define LPDDR4__DENALI_CTL_121_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_121_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121
-#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_122_READ_MASK 0x010FFFFFU
-#define LPDDR4__DENALI_CTL_122_WRITE_MASK 0x010FFFFFU
-#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH 20U
-#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122
-#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2
-
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT 24U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH 1U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR 0U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET 0U
-#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122
-#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF
-
-#define LPDDR4__DENALI_CTL_123_READ_MASK 0x00010103U
-#define LPDDR4__DENALI_CTL_123_WRITE_MASK 0x00010103U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH 2U
-#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123
-#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WIDTH 1U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOCLR 0U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1_WOSET 0U
-#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_123
-#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_DFI_VERSION_4P0V1
-
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET 0U
-#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123
-#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
-
-#define LPDDR4__DENALI_CTL_124_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_124_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_124
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_125_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_125_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH 16U
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_126_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_126_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_126
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH 16U
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_127_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_127_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_127
-#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127
-#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_128_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_CTL_128_WRITE_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH 16U
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128
-#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT 16U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH 1U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR 0U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET 0U
-#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128
-#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL
-
-#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT 24U
-#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH 3U
-#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128
-#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND
-
-#define LPDDR4__DENALI_CTL_129_READ_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_129_WRITE_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT 0U
-#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH 8U
-#define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129
-#define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW
-
-#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK 0x01FFFF00U
-#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH 17U
-#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129
-#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS
-
-#define LPDDR4__DENALI_CTL_130_READ_MASK 0x01030107U
-#define LPDDR4__DENALI_CTL_130_WRITE_MASK 0x01030107U
-#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH 3U
-#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130
-#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS
-
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET 0U
-#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130
-#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS
-
-#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT 16U
-#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH 2U
-#define LPDDR4__PPR_STATUS__REG DENALI_CTL_130
-#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS
-
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT 24U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH 1U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR 0U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET 0U
-#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130
-#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL
-
-#define LPDDR4__DENALI_CTL_131_READ_MASK 0xFFFFFF03U
-#define LPDDR4__DENALI_CTL_131_WRITE_MASK 0xFFFFFF03U
-#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH 2U
-#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131
-#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE
-
-#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH 8U
-#define LPDDR4__CKSRE_F0__REG DENALI_CTL_131
-#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0
-
-#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH 8U
-#define LPDDR4__CKSRX_F0__REG DENALI_CTL_131
-#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0
-
-#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH 8U
-#define LPDDR4__CKSRE_F1__REG DENALI_CTL_131
-#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1
-
-#define LPDDR4__DENALI_CTL_132_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_132_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH 8U
-#define LPDDR4__CKSRX_F1__REG DENALI_CTL_132
-#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1
-
-#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH 8U
-#define LPDDR4__CKSRE_F2__REG DENALI_CTL_132
-#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2
-
-#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH 8U
-#define LPDDR4__CKSRX_F2__REG DENALI_CTL_132
-#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2
-
-#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK 0x7F000000U
-#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT 24U
-#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH 7U
-#define LPDDR4__LP_CMD__REG DENALI_CTL_132
-#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD
-
-#define LPDDR4__DENALI_CTL_133_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_133_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH 4U
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH 4U
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH 4U
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_134_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_134_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH 4U
-#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134
-#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH 4U
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH 4U
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH 4U
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_135_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_135_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH 4U
-#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135
-#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0
-
-#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH 4U
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH 4U
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH 4U
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_136_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_136_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH 4U
-#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136
-#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH 4U
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH 4U
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_137_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_137_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH 4U
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_137
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH 4U
-#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137
-#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1
-
-#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH 4U
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137
-#define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH 4U
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137
-#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_138_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_138_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH 4U
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138
-#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138
-#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH 4U
-#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138
-#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH 4U
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138
-#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_139_READ_MASK 0x3F0F0F0FU
-#define LPDDR4__DENALI_CTL_139_WRITE_MASK 0x3F0F0F0FU
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH 4U
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139
-#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH 4U
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_139
-#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH 4U
-#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139
-#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2
-
-#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK 0x3F000000U
-#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH 6U
-#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139
-#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN
-
-#define LPDDR4__DENALI_CTL_140_READ_MASK 0x070FFF01U
-#define LPDDR4__DENALI_CTL_140_WRITE_MASK 0x070FFF01U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET 0U
-#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140
-#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN
-
-#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK 0x000FFF00U
-#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT 8U
-#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH 12U
-#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140
-#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT
-
-#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT 24U
-#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH 3U
-#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140
-#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP
-
-#define LPDDR4__DENALI_CTL_141_READ_MASK 0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_141_WRITE_MASK 0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH 7U
-#define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141
-#define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0
-
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK 0x00007F00U
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH 7U
-#define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141
-#define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1
-
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH 4U
-#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141
-#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN
-
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH 4U
-#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141
-#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN
-
-#define LPDDR4__DENALI_CTL_142_READ_MASK 0x000FFF07U
-#define LPDDR4__DENALI_CTL_142_WRITE_MASK 0x000FFF07U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH 3U
-#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142
-#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN
-
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK 0x000FFF00U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT 8U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH 12U
-#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142
-#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE
-
-#define LPDDR4__DENALI_CTL_143_READ_MASK 0xFFFF0FFFU
-#define LPDDR4__DENALI_CTL_143_WRITE_MASK 0xFFFF0FFFU
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH 12U
-#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143
-#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE
-
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH 8U
-#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143
-#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE
-
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT 24U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH 8U
-#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143
-#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE
-
-#define LPDDR4__DENALI_CTL_144_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_144_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_145_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_145_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145
-#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_146_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_146_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146
-#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_147_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_147_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET 0U
-#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147
-#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN
-
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET 0U
-#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147
-#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN
-
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET 0U
-#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147
-#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN
-
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT 24U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH 1U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR 0U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET 0U
-#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147
-#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17
-
-#define LPDDR4__DENALI_CTL_148_READ_MASK 0x3F3F0101U
-#define LPDDR4__DENALI_CTL_148_WRITE_MASK 0x3F3F0101U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET 0U
-#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148
-#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN
-
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET 0U
-#define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148
-#define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN
-
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK 0x003F0000U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT 16U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH 6U
-#define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148
-#define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH
-
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK 0x3F000000U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT 24U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH 6U
-#define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148
-#define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH
-
-#define LPDDR4__DENALI_CTL_149_READ_MASK 0x01FF03FFU
-#define LPDDR4__DENALI_CTL_149_WRITE_MASK 0x01FF03FFU
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT 0U
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH 8U
-#define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149
-#define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER
-
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT 8U
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH 2U
-#define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149
-#define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK
-
-#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT 16U
-#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH 8U
-#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149
-#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18
-
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT 24U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET 0U
-#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149
-#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE
-
-#define LPDDR4__DENALI_CTL_150_READ_MASK 0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_150_WRITE_MASK 0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH 10U
-#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150
-#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0
-
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH 16U
-#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150
-#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0
-
-#define LPDDR4__DENALI_CTL_151_READ_MASK 0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_151_WRITE_MASK 0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH 10U
-#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151
-#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1
-
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH 16U
-#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151
-#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1
-
-#define LPDDR4__DENALI_CTL_152_READ_MASK 0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_152_WRITE_MASK 0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH 10U
-#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152
-#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2
-
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH 16U
-#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152
-#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2
-
-#define LPDDR4__DENALI_CTL_153_READ_MASK 0x00000103U
-#define LPDDR4__DENALI_CTL_153_WRITE_MASK 0x00000103U
-#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT 0U
-#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH 2U
-#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153
-#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY
-
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET 0U
-#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153
-#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN
-
-#define LPDDR4__DENALI_CTL_154_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_154_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT 0U
-#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH 32U
-#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154
-#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR
-
-#define LPDDR4__DENALI_CTL_155_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_155_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH 32U
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0
-
-#define LPDDR4__DENALI_CTL_156_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_156_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH 32U
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1
-
-#define LPDDR4__DENALI_CTL_157_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_157_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH 32U
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157
-#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2
-
-#define LPDDR4__DENALI_CTL_158_READ_MASK 0x00FFFF0FU
-#define LPDDR4__DENALI_CTL_158_WRITE_MASK 0x00FFFF0FU
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT 0U
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH 4U
-#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158
-#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK
-
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT 8U
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH 16U
-#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158
-#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT
-
-#define LPDDR4__DENALI_CTL_159_READ_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_CTL_159_WRITE_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT 0U
-#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH 27U
-#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159
-#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG
-
-#define LPDDR4__DENALI_CTL_160_READ_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_160_WRITE_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH 8U
-#define LPDDR4__MRW_STATUS__REG DENALI_CTL_160
-#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS
-
-#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK 0x01FFFF00U
-#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT 8U
-#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH 17U
-#define LPDDR4__READ_MODEREG__REG DENALI_CTL_160
-#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG
-
-#define LPDDR4__DENALI_CTL_161_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_161_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH 32U
-#define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161
-#define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0
-
-#define LPDDR4__DENALI_CTL_162_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_162_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH 8U
-#define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162
-#define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1
-
-#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH 16U
-#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162
-#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0
-
-#define LPDDR4__DENALI_CTL_163_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_CTL_163_WRITE_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH 16U
-#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163
-#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1
-
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT 16U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH 1U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR 0U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET 0U
-#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163
-#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG
-
-#define LPDDR4__DENALI_CTL_164_READ_MASK 0x03FF0003U
-#define LPDDR4__DENALI_CTL_164_WRITE_MASK 0x03FF0003U
-#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT 0U
-#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH 2U
-#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164
-#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC
-
-#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH 10U
-#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164
-#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0
-
-#define LPDDR4__DENALI_CTL_165_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_165_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH 10U
-#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165
-#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0
-
-#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH 10U
-#define LPDDR4__TFC_F0__REG DENALI_CTL_165
-#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0
-
-#define LPDDR4__DENALI_CTL_166_READ_MASK 0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_166_WRITE_MASK 0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH 5U
-#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166
-#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0
-
-#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH 5U
-#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166
-#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0
-
-#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH 16U
-#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166
-#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0
-
-#define LPDDR4__DENALI_CTL_167_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_167_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH 10U
-#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167
-#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1
-
-#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH 10U
-#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167
-#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1
-
-#define LPDDR4__DENALI_CTL_168_READ_MASK 0x1F1F03FFU
-#define LPDDR4__DENALI_CTL_168_WRITE_MASK 0x1F1F03FFU
-#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH 10U
-#define LPDDR4__TFC_F1__REG DENALI_CTL_168
-#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1
-
-#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH 5U
-#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168
-#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1
-
-#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH 5U
-#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168
-#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1
-
-#define LPDDR4__DENALI_CTL_169_READ_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_169_WRITE_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH 16U
-#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169
-#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1
-
-#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH 10U
-#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169
-#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2
-
-#define LPDDR4__DENALI_CTL_170_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_170_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH 10U
-#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170
-#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2
-
-#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH 10U
-#define LPDDR4__TFC_F2__REG DENALI_CTL_170
-#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2
-
-#define LPDDR4__DENALI_CTL_171_READ_MASK 0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_171_WRITE_MASK 0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH 5U
-#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171
-#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2
-
-#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH 5U
-#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171
-#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2
-
-#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH 16U
-#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171
-#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2
-
-#define LPDDR4__DENALI_CTL_172_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_172_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_173_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_173_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173
-#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_174_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_174_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174
-#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_175_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_175_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH 8U
-#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175
-#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH 8U
-#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175
-#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH 8U
-#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175
-#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH 8U
-#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175
-#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_176_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_176_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH 8U
-#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176
-#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH 8U
-#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176
-#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH 8U
-#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176
-#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0
-
-#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH 8U
-#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176
-#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_177_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_177_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH 8U
-#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177
-#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH 8U
-#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177
-#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH 8U
-#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177
-#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH 8U
-#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177
-#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_178_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_178_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH 8U
-#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178
-#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH 8U
-#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178
-#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0
-
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH 8U
-#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178
-#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH 8U
-#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178
-#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_179_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_179_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH 8U
-#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179
-#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH 8U
-#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179
-#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH 8U
-#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179
-#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH 8U
-#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179
-#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_180_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_180_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH 8U
-#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180
-#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0
-
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH 8U
-#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180
-#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH 8U
-#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180
-#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH 8U
-#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180
-#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_181_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_181_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH 8U
-#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181
-#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0
-
-#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH 8U
-#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181
-#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0
-
-#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH 8U
-#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181
-#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0
-
-#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH 8U
-#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181
-#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0
-
-#define LPDDR4__DENALI_CTL_182_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_182_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH 8U
-#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182
-#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0
-
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH 8U
-#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182
-#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0
-
-#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH 8U
-#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182
-#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH 8U
-#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182
-#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_183_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_183_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH 8U
-#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183
-#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH 8U
-#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183
-#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH 8U
-#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183
-#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH 8U
-#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183
-#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_184_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_184_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH 8U
-#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184
-#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1
-
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH 8U
-#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184
-#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH 8U
-#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184
-#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH 8U
-#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184
-#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_185_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_185_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH 8U
-#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185
-#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH 8U
-#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185
-#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH 8U
-#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185
-#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH 8U
-#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185
-#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1
-
-#define LPDDR4__DENALI_CTL_186_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_186_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH 8U
-#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186
-#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH 8U
-#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186
-#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH 8U
-#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186
-#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH 8U
-#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186
-#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_187_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_187_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH 8U
-#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187
-#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH 8U
-#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187
-#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH 8U
-#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187
-#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1
-
-#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH 8U
-#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187
-#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_188_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_188_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH 8U
-#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188
-#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH 8U
-#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188
-#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH 8U
-#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188
-#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1
-
-#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH 8U
-#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188
-#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1
-
-#define LPDDR4__DENALI_CTL_189_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_189_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH 8U
-#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189
-#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1
-
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH 8U
-#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189
-#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1
-
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH 8U
-#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189
-#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1
-
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH 8U
-#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189
-#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1
-
-#define LPDDR4__DENALI_CTL_190_READ_MASK 0x010101FFU
-#define LPDDR4__DENALI_CTL_190_WRITE_MASK 0x010101FFU
-#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT 0U
-#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH 8U
-#define LPDDR4__MR23_DATA__REG DENALI_CTL_190
-#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA
-
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH 1U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR 0U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET 0U
-#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190
-#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0
-
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH 1U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR 0U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET 0U
-#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190
-#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1
-
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH 1U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR 0U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET 0U
-#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190
-#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2
-
-#define LPDDR4__DENALI_CTL_191_READ_MASK 0x01010103U
-#define LPDDR4__DENALI_CTL_191_WRITE_MASK 0x01010103U
-#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH 2U
-#define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191
-#define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN
-
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT 8U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH 1U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR 0U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET 0U
-#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191
-#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19
-
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT 16U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH 1U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR 0U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET 0U
-#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191
-#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20
-
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT 24U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH 1U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR 0U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET 0U
-#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191
-#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW
-
-#define LPDDR4__DENALI_CTL_192_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_192_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT 0U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH 1U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR 0U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET 0U
-#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192
-#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP
-
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET 0U
-#define LPDDR4__FSP_STATUS__REG DENALI_CTL_192
-#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS
-
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT 16U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET 0U
-#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192
-#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT
-
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT 24U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET 0U
-#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192
-#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT
-
-#define LPDDR4__DENALI_CTL_193_READ_MASK 0x03030101U
-#define LPDDR4__DENALI_CTL_193_WRITE_MASK 0x03030101U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT 0U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH 1U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR 0U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET 0U
-#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193
-#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID
-
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT 8U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH 1U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR 0U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET 0U
-#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193
-#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID
-
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT 16U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH 2U
-#define LPDDR4__FSP0_FRC__REG DENALI_CTL_193
-#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC
-
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK 0x03000000U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT 24U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH 2U
-#define LPDDR4__FSP1_FRC__REG DENALI_CTL_193
-#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC
-
-#define LPDDR4__DENALI_CTL_194_READ_MASK 0x013F0300U
-#define LPDDR4__DENALI_CTL_194_WRITE_MASK 0x013F0300U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT 0U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH 1U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR 0U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET 0U
-#define LPDDR4__BIST_GO__REG DENALI_CTL_194
-#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO
-
-#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT 8U
-#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH 2U
-#define LPDDR4__BIST_RESULT__REG DENALI_CTL_194
-#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT
-
-#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK 0x003F0000U
-#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH 6U
-#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194
-#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE
-
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT 24U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH 1U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR 0U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET 0U
-#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194
-#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK
-
-#define LPDDR4__DENALI_CTL_195_READ_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_195_WRITE_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT 0U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH 1U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR 0U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET 0U
-#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195
-#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK
-
-#define LPDDR4__DENALI_CTL_196_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_196_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH 32U
-#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196
-#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0
-
-#define LPDDR4__DENALI_CTL_197_READ_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_197_WRITE_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH 3U
-#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197
-#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1
-
-#define LPDDR4__DENALI_CTL_198_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_198_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH 32U
-#define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198
-#define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0
-
-#define LPDDR4__DENALI_CTL_199_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_199_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH 32U
-#define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199
-#define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1
-
-#define LPDDR4__DENALI_CTL_200_READ_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_200_WRITE_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH 3U
-#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200
-#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE
-
-#define LPDDR4__DENALI_CTL_201_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_201_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH 32U
-#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201
-#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0
-
-#define LPDDR4__DENALI_CTL_202_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_202_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH 32U
-#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202
-#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1
-
-#define LPDDR4__DENALI_CTL_203_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_203_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH 32U
-#define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203
-#define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2
-
-#define LPDDR4__DENALI_CTL_204_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_204_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT 0U
-#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH 32U
-#define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204
-#define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3
-
-#define LPDDR4__DENALI_CTL_205_READ_MASK 0x0FFF0100U
-#define LPDDR4__DENALI_CTL_205_WRITE_MASK 0x0FFF0100U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT 0U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET 0U
-#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205
-#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT
-
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT 8U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET 0U
-#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205
-#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE
-
-#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT 16U
-#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH 12U
-#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205
-#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP
-
-#define LPDDR4__DENALI_CTL_206_READ_MASK 0x07030FFFU
-#define LPDDR4__DENALI_CTL_206_WRITE_MASK 0x07030FFFU
-#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT 0U
-#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH 12U
-#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206
-#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT
-
-#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH 2U
-#define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206
-#define LPDDR4__ECC_ENABLE__FLD LPDDR4__DENALI_CTL_206__ECC_ENABLE
-
-#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT 24U
-#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH 3U
-#define LPDDR4__INLINE_ECC_BANK_OFFSET__REG DENALI_CTL_206
-#define LPDDR4__INLINE_ECC_BANK_OFFSET__FLD LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET
-
-#define LPDDR4__DENALI_CTL_207_READ_MASK 0x010F0101U
-#define LPDDR4__DENALI_CTL_207_WRITE_MASK 0x010F0101U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET 0U
-#define LPDDR4__ECC_READ_CACHING_EN__REG DENALI_CTL_207
-#define LPDDR4__ECC_READ_CACHING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN
-
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET 0U
-#define LPDDR4__ECC_WRITE_COMBINING_EN__REG DENALI_CTL_207
-#define LPDDR4__ECC_WRITE_COMBINING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN
-
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT 16U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH 4U
-#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_207
-#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED21
-
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT 24U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH 1U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR 0U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET 0U
-#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_207
-#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED22
-
-#define LPDDR4__DENALI_CTL_208_READ_MASK 0x01FFFF01U
-#define LPDDR4__DENALI_CTL_208_WRITE_MASK 0x01FFFF01U
-#define LPDDR4__DENALI_CTL_208__FWC_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_208__FWC_SHIFT 0U
-#define LPDDR4__DENALI_CTL_208__FWC_WIDTH 1U
-#define LPDDR4__DENALI_CTL_208__FWC_WOCLR 0U
-#define LPDDR4__DENALI_CTL_208__FWC_WOSET 0U
-#define LPDDR4__FWC__REG DENALI_CTL_208
-#define LPDDR4__FWC__FLD LPDDR4__DENALI_CTL_208__FWC
-
-#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH 16U
-#define LPDDR4__XOR_CHECK_BITS__REG DENALI_CTL_208
-#define LPDDR4__XOR_CHECK_BITS__FLD LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS
-
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET 0U
-#define LPDDR4__ECC_WRITEBACK_EN__REG DENALI_CTL_208
-#define LPDDR4__ECC_WRITEBACK_EN__FLD LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN
-
-#define LPDDR4__DENALI_CTL_209_READ_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_209_WRITE_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT 0U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH 1U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR 0U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET 0U
-#define LPDDR4__ECC_DISABLE_W_UC_ERR__REG DENALI_CTL_209
-#define LPDDR4__ECC_DISABLE_W_UC_ERR__FLD LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR
-
-#define LPDDR4__DENALI_CTL_210_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_210_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH 32U
-#define LPDDR4__ECC_U_ADDR_0__REG DENALI_CTL_210
-#define LPDDR4__ECC_U_ADDR_0__FLD LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0
-
-#define LPDDR4__DENALI_CTL_211_READ_MASK 0x0000FF07U
-#define LPDDR4__DENALI_CTL_211_WRITE_MASK 0x0000FF07U
-#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH 3U
-#define LPDDR4__ECC_U_ADDR_1__REG DENALI_CTL_211
-#define LPDDR4__ECC_U_ADDR_1__FLD LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1
-
-#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT 8U
-#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH 8U
-#define LPDDR4__ECC_U_SYND__REG DENALI_CTL_211
-#define LPDDR4__ECC_U_SYND__FLD LPDDR4__DENALI_CTL_211__ECC_U_SYND
-
-#define LPDDR4__DENALI_CTL_212_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_212_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH 32U
-#define LPDDR4__ECC_U_DATA_0__REG DENALI_CTL_212
-#define LPDDR4__ECC_U_DATA_0__FLD LPDDR4__DENALI_CTL_212__ECC_U_DATA_0
-
-#define LPDDR4__DENALI_CTL_213_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_213_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH 32U
-#define LPDDR4__ECC_U_DATA_1__REG DENALI_CTL_213
-#define LPDDR4__ECC_U_DATA_1__FLD LPDDR4__DENALI_CTL_213__ECC_U_DATA_1
-
-#define LPDDR4__DENALI_CTL_214_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_214_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH 32U
-#define LPDDR4__ECC_C_ADDR_0__REG DENALI_CTL_214
-#define LPDDR4__ECC_C_ADDR_0__FLD LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0
-
-#define LPDDR4__DENALI_CTL_215_READ_MASK 0x0000FF07U
-#define LPDDR4__DENALI_CTL_215_WRITE_MASK 0x0000FF07U
-#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH 3U
-#define LPDDR4__ECC_C_ADDR_1__REG DENALI_CTL_215
-#define LPDDR4__ECC_C_ADDR_1__FLD LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1
-
-#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT 8U
-#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH 8U
-#define LPDDR4__ECC_C_SYND__REG DENALI_CTL_215
-#define LPDDR4__ECC_C_SYND__FLD LPDDR4__DENALI_CTL_215__ECC_C_SYND
-
-#define LPDDR4__DENALI_CTL_216_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_216_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH 32U
-#define LPDDR4__ECC_C_DATA_0__REG DENALI_CTL_216
-#define LPDDR4__ECC_C_DATA_0__FLD LPDDR4__DENALI_CTL_216__ECC_C_DATA_0
-
-#define LPDDR4__DENALI_CTL_217_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_217_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH 32U
-#define LPDDR4__ECC_C_DATA_1__REG DENALI_CTL_217
-#define LPDDR4__ECC_C_DATA_1__FLD LPDDR4__DENALI_CTL_217__ECC_C_DATA_1
-
-#define LPDDR4__DENALI_CTL_218_READ_MASK 0x7FFF3F3FU
-#define LPDDR4__DENALI_CTL_218_WRITE_MASK 0x7FFF3F3FU
-#define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK 0x0000003FU
-#define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT 0U
-#define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH 6U
-#define LPDDR4__ECC_U_ID__REG DENALI_CTL_218
-#define LPDDR4__ECC_U_ID__FLD LPDDR4__DENALI_CTL_218__ECC_U_ID
-
-#define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK 0x00003F00U
-#define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT 8U
-#define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH 6U
-#define LPDDR4__ECC_C_ID__REG DENALI_CTL_218
-#define LPDDR4__ECC_C_ID__FLD LPDDR4__DENALI_CTL_218__ECC_C_ID
-
-#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_MASK 0x7FFF0000U
-#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0_WIDTH 15U
-#define LPDDR4__NON_ECC_REGION_START_ADDR_0__REG DENALI_CTL_218
-#define LPDDR4__NON_ECC_REGION_START_ADDR_0__FLD LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0
-
-#define LPDDR4__DENALI_CTL_219_READ_MASK 0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_219_WRITE_MASK 0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_MASK 0x00007FFFU
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_WIDTH 15U
-#define LPDDR4__NON_ECC_REGION_END_ADDR_0__REG DENALI_CTL_219
-#define LPDDR4__NON_ECC_REGION_END_ADDR_0__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0
-
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_MASK 0x7FFF0000U
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1_WIDTH 15U
-#define LPDDR4__NON_ECC_REGION_START_ADDR_1__REG DENALI_CTL_219
-#define LPDDR4__NON_ECC_REGION_START_ADDR_1__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1
-
-#define LPDDR4__DENALI_CTL_220_READ_MASK 0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_220_WRITE_MASK 0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_MASK 0x00007FFFU
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_WIDTH 15U
-#define LPDDR4__NON_ECC_REGION_END_ADDR_1__REG DENALI_CTL_220
-#define LPDDR4__NON_ECC_REGION_END_ADDR_1__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1
-
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_MASK 0x7FFF0000U
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2_WIDTH 15U
-#define LPDDR4__NON_ECC_REGION_START_ADDR_2__REG DENALI_CTL_220
-#define LPDDR4__NON_ECC_REGION_START_ADDR_2__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2
-
-#define LPDDR4__DENALI_CTL_221_READ_MASK 0x00077FFFU
-#define LPDDR4__DENALI_CTL_221_WRITE_MASK 0x00077FFFU
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_MASK 0x00007FFFU
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_WIDTH 15U
-#define LPDDR4__NON_ECC_REGION_END_ADDR_2__REG DENALI_CTL_221
-#define LPDDR4__NON_ECC_REGION_END_ADDR_2__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2
-
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_MASK 0x00070000U
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH 3U
-#define LPDDR4__NON_ECC_REGION_ENABLE__REG DENALI_CTL_221
-#define LPDDR4__NON_ECC_REGION_ENABLE__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE
-
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT 24U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH 1U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR 0U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET 0U
-#define LPDDR4__ECC_SCRUB_START__REG DENALI_CTL_221
-#define LPDDR4__ECC_SCRUB_START__FLD LPDDR4__DENALI_CTL_221__ECC_SCRUB_START
-
-#define LPDDR4__DENALI_CTL_222_READ_MASK 0x010FFF01U
-#define LPDDR4__DENALI_CTL_222_WRITE_MASK 0x010FFF01U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET 0U
-#define LPDDR4__ECC_SCRUB_IN_PROGRESS__REG DENALI_CTL_222
-#define LPDDR4__ECC_SCRUB_IN_PROGRESS__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS
-
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK 0x000FFF00U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH 12U
-#define LPDDR4__ECC_SCRUB_LEN__REG DENALI_CTL_222
-#define LPDDR4__ECC_SCRUB_LEN__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN
-
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT 24U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET 0U
-#define LPDDR4__ECC_SCRUB_MODE__REG DENALI_CTL_222
-#define LPDDR4__ECC_SCRUB_MODE__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE
-
-#define LPDDR4__DENALI_CTL_223_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_223_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT 0U
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH 16U
-#define LPDDR4__ECC_SCRUB_INTERVAL__REG DENALI_CTL_223
-#define LPDDR4__ECC_SCRUB_INTERVAL__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL
-
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT 16U
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH 16U
-#define LPDDR4__ECC_SCRUB_IDLE_CNT__REG DENALI_CTL_223
-#define LPDDR4__ECC_SCRUB_IDLE_CNT__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT
-
-#define LPDDR4__DENALI_CTL_224_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_224_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH 32U
-#define LPDDR4__ECC_SCRUB_START_ADDR_0__REG DENALI_CTL_224
-#define LPDDR4__ECC_SCRUB_START_ADDR_0__FLD LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0
-
-#define LPDDR4__DENALI_CTL_225_READ_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_225_WRITE_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH 3U
-#define LPDDR4__ECC_SCRUB_START_ADDR_1__REG DENALI_CTL_225
-#define LPDDR4__ECC_SCRUB_START_ADDR_1__FLD LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1
-
-#define LPDDR4__DENALI_CTL_226_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_226_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH 32U
-#define LPDDR4__ECC_SCRUB_END_ADDR_0__REG DENALI_CTL_226
-#define LPDDR4__ECC_SCRUB_END_ADDR_0__FLD LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0
-
-#define LPDDR4__DENALI_CTL_227_READ_MASK 0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_227_WRITE_MASK 0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH 3U
-#define LPDDR4__ECC_SCRUB_END_ADDR_1__REG DENALI_CTL_227
-#define LPDDR4__ECC_SCRUB_END_ADDR_1__FLD LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1
-
-#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT 8U
-#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH 5U
-#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_227
-#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK
-
-#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT 16U
-#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH 5U
-#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_227
-#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT 24U
-#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH 5U
-#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_227
-#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD
-
-#define LPDDR4__DENALI_CTL_228_READ_MASK 0x000F1F1FU
-#define LPDDR4__DENALI_CTL_228_WRITE_MASK 0x000F1F1FU
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT 0U
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH 5U
-#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_228
-#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT
-
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT 8U
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH 5U
-#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_228
-#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT
-
-#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT 16U
-#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH 4U
-#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_228
-#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI
-
-#define LPDDR4__DENALI_CTL_229_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_229_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_229
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_229
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_230_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_230_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_230
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_230
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_231_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_231_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_231
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH 16U
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_231
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_232_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_232_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH 16U
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_232
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH 16U
-#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_232
-#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_233_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_233_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_233
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_233
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_234_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_234_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_235_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_235_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_235
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_235
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_236_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_236_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH 16U
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_236
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH 16U
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_236
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_237_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_237_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH 16U
-#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_237
-#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_237
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_238_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_238_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_238
-#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_238
-#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_239_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_239_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_239
-#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_239
-#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_240_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_240_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_240
-#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH 16U
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_240
-#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_241_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_241_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH 16U
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_241
-#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH 16U
-#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_241
-#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_242_READ_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_CTL_242_WRITE_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_242
-#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK 0x00070000U
-#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT 16U
-#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH 3U
-#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_242
-#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_242__MC_RESERVED23
-
-#define LPDDR4__DENALI_CTL_243_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_243_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__REG DENALI_CTL_243
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0
-
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__REG DENALI_CTL_243
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0
-
-#define LPDDR4__DENALI_CTL_244_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_244_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__REG DENALI_CTL_244
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0
-
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__REG DENALI_CTL_244
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0
-
-#define LPDDR4__DENALI_CTL_245_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_245_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__REG DENALI_CTL_245
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0
-
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__REG DENALI_CTL_245
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0
-
-#define LPDDR4__DENALI_CTL_246_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_246_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__REG DENALI_CTL_246
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0
-
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__REG DENALI_CTL_246
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0
-
-#define LPDDR4__DENALI_CTL_247_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_247_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__REG DENALI_CTL_247
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1
-
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__REG DENALI_CTL_247
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1
-
-#define LPDDR4__DENALI_CTL_248_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_248_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__REG DENALI_CTL_248
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1
-
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__REG DENALI_CTL_248
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1
-
-#define LPDDR4__DENALI_CTL_249_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_249_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__REG DENALI_CTL_249
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1
-
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__REG DENALI_CTL_249
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1
-
-#define LPDDR4__DENALI_CTL_250_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_250_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__REG DENALI_CTL_250
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1
-
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__REG DENALI_CTL_250
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1
-
-#define LPDDR4__DENALI_CTL_251_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_251_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__REG DENALI_CTL_251
-#define LPDDR4__WATCHDOG_THRESHOLD_TASK_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2
-
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__REG DENALI_CTL_251
-#define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2
-
-#define LPDDR4__DENALI_CTL_252_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_252_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__REG DENALI_CTL_252
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2
-
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__REG DENALI_CTL_252
-#define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2
-
-#define LPDDR4__DENALI_CTL_253_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_253_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__REG DENALI_CTL_253
-#define LPDDR4__WATCHDOG_THRESHOLD_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2
-
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__REG DENALI_CTL_253
-#define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2
-
-#define LPDDR4__DENALI_CTL_254_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_254_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__REG DENALI_CTL_254
-#define LPDDR4__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2
-
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2_WIDTH 16U
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__REG DENALI_CTL_254
-#define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2
-
-#define LPDDR4__DENALI_CTL_255_READ_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_255_WRITE_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT 0U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH 8U
-#define LPDDR4__WATCHDOG_RELOAD__REG DENALI_CTL_255
-#define LPDDR4__WATCHDOG_RELOAD__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD
-
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT 8U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH 8U
-#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__REG DENALI_CTL_255
-#define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE
-
-#define LPDDR4__DENALI_CTL_256_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_256_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT 0U
-#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH 20U
-#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_256
-#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG
-
-#define LPDDR4__DENALI_CTL_257_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_257_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH 12U
-#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_257
-#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_257__ZQINIT_F0
-
-#define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH 12U
-#define LPDDR4__ZQCL_F0__REG DENALI_CTL_257
-#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_257__ZQCL_F0
-
-#define LPDDR4__DENALI_CTL_258_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_258_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH 12U
-#define LPDDR4__ZQCS_F0__REG DENALI_CTL_258
-#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_258__ZQCS_F0
-
-#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH 12U
-#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_258
-#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_258__TZQCAL_F0
-
-#define LPDDR4__DENALI_CTL_259_READ_MASK 0x000FFF7FU
-#define LPDDR4__DENALI_CTL_259_WRITE_MASK 0x000FFF7FU
-#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH 7U
-#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_259
-#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_259__TZQLAT_F0
-
-#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK 0x000FFF00U
-#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH 12U
-#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_259
-#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_259__ZQINIT_F1
-
-#define LPDDR4__DENALI_CTL_260_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_260_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH 12U
-#define LPDDR4__ZQCL_F1__REG DENALI_CTL_260
-#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_260__ZQCL_F1
-
-#define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH 12U
-#define LPDDR4__ZQCS_F1__REG DENALI_CTL_260
-#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_260__ZQCS_F1
-
-#define LPDDR4__DENALI_CTL_261_READ_MASK 0x007F0FFFU
-#define LPDDR4__DENALI_CTL_261_WRITE_MASK 0x007F0FFFU
-#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH 12U
-#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_261
-#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_261__TZQCAL_F1
-
-#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK 0x007F0000U
-#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH 7U
-#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_261
-#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_261__TZQLAT_F1
-
-#define LPDDR4__DENALI_CTL_262_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_262_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH 12U
-#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_262
-#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_262__ZQINIT_F2
-
-#define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH 12U
-#define LPDDR4__ZQCL_F2__REG DENALI_CTL_262
-#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_262__ZQCL_F2
-
-#define LPDDR4__DENALI_CTL_263_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_263_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH 12U
-#define LPDDR4__ZQCS_F2__REG DENALI_CTL_263
-#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_263__ZQCS_F2
-
-#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH 12U
-#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_263
-#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_263__TZQCAL_F2
-
-#define LPDDR4__DENALI_CTL_264_READ_MASK 0x0100037FU
-#define LPDDR4__DENALI_CTL_264_WRITE_MASK 0x0100037FU
-#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH 7U
-#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_264
-#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_264__TZQLAT_F2
-
-#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_SHIFT 8U
-#define LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP_WIDTH 2U
-#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_264
-#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP
-
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT 16U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH 4U
-#define LPDDR4__ZQ_REQ__REG DENALI_CTL_264
-#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ
-
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT 24U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH 1U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR 0U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET 0U
-#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_264
-#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING
-
-#define LPDDR4__DENALI_CTL_265_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_265_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH 12U
-#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_265
-#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F0
-
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH 12U
-#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_265
-#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F1
-
-#define LPDDR4__DENALI_CTL_266_READ_MASK 0x01010FFFU
-#define LPDDR4__DENALI_CTL_266_WRITE_MASK 0x01010FFFU
-#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH 12U
-#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_266
-#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_266__ZQRESET_F2
-
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT 16U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET 0U
-#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_266
-#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_266__NO_ZQ_INIT
-
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT 24U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET 0U
-#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_266
-#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_266__ZQCS_ROTATE
-
-#define LPDDR4__DENALI_CTL_267_READ_MASK 0x03030303U
-#define LPDDR4__DENALI_CTL_267_WRITE_MASK 0x03030303U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH 2U
-#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_267
-#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0
-
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH 2U
-#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_267
-#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0
-
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH 2U
-#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_267
-#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1
-
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_MASK 0x03000000U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH 2U
-#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_267
-#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1
-
-#define LPDDR4__DENALI_CTL_268_READ_MASK 0x07070303U
-#define LPDDR4__DENALI_CTL_268_WRITE_MASK 0x07070303U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH 2U
-#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_268
-#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_0
-
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH 2U
-#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_268
-#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_1
-
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK 0x00070000U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH 3U
-#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_268
-#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_0
-
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH 3U
-#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_268
-#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_1
-
-#define LPDDR4__DENALI_CTL_269_READ_MASK 0xFFFF0F0FU
-#define LPDDR4__DENALI_CTL_269_WRITE_MASK 0xFFFF0F0FU
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH 4U
-#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_269
-#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_0
-
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH 4U
-#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_269
-#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_1
-
-#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH 16U
-#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_269
-#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0
-
-#define LPDDR4__DENALI_CTL_270_READ_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_CTL_270_WRITE_MASK 0x0007FFFFU
-#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH 16U
-#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_270
-#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0
-
-#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK 0x00070000U
-#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH 3U
-#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_270
-#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_270__ROW_START_VAL_0
-
-#define LPDDR4__DENALI_CTL_271_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_271_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH 16U
-#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_271
-#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1
-
-#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH 16U
-#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_271
-#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1
-
-#define LPDDR4__DENALI_CTL_272_READ_MASK 0xFFFF0307U
-#define LPDDR4__DENALI_CTL_272_WRITE_MASK 0xFFFF0307U
-#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH 3U
-#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_272
-#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_272__ROW_START_VAL_1
-
-#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH 2U
-#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_272
-#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2
-
-#define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH 16U
-#define LPDDR4__CS_MSK_0__REG DENALI_CTL_272
-#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_272__CS_MSK_0
-
-#define LPDDR4__DENALI_CTL_273_READ_MASK 0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_273_WRITE_MASK 0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH 16U
-#define LPDDR4__CS_MSK_1__REG DENALI_CTL_273
-#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_273__CS_MSK_1
-
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET 0U
-#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_273
-#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN
-
-#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT 24U
-#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH 5U
-#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_273
-#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_273__MC_RESERVED24
-
-#define LPDDR4__DENALI_CTL_274_READ_MASK 0xFFFF1F01U
-#define LPDDR4__DENALI_CTL_274_WRITE_MASK 0xFFFF1F01U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT 0U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH 1U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR 0U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET 0U
-#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_274
-#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_274__MC_RESERVED25
-
-#define LPDDR4__DENALI_CTL_274__APREBIT_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT 8U
-#define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH 5U
-#define LPDDR4__APREBIT__REG DENALI_CTL_274
-#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_274__APREBIT
-
-#define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT 16U
-#define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH 8U
-#define LPDDR4__AGE_COUNT__REG DENALI_CTL_274
-#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__AGE_COUNT
-
-#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT 24U
-#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH 8U
-#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_274
-#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT
-
-#define LPDDR4__DENALI_CTL_275_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_275_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET 0U
-#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_275
-#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_275__ADDR_CMP_EN
-
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET 0U
-#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_275
-#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS
-
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET 0U
-#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_275
-#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN
-
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET 0U
-#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_275
-#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_275__PLACEMENT_EN
-
-#define LPDDR4__DENALI_CTL_276_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_276_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET 0U
-#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_276
-#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_276__PRIORITY_EN
-
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET 0U
-#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_276
-#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_EN
-
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET 0U
-#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_276
-#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN
-
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET 0U
-#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_276
-#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_276__CS_SAME_EN
-
-#define LPDDR4__DENALI_CTL_277_READ_MASK 0x011F0301U
-#define LPDDR4__DENALI_CTL_277_WRITE_MASK 0x011F0301U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET 0U
-#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_277
-#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN
-
-#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT 8U
-#define LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH 2U
-#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_277
-#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_277__DISABLE_RW_GROUP_W_BNK_CONFLICT
-
-#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH 5U
-#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_277
-#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE
-
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET 0U
-#define LPDDR4__SWAP_EN__REG DENALI_CTL_277
-#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_277__SWAP_EN
-
-#define LPDDR4__DENALI_CTL_278_READ_MASK 0x01030301U
-#define LPDDR4__DENALI_CTL_278_WRITE_MASK 0x01030301U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET 0U
-#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_278
-#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE
-
-#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT 8U
-#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH 2U
-#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_278
-#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD
-
-#define LPDDR4__DENALI_CTL_278__CS_MAP_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT 16U
-#define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH 2U
-#define LPDDR4__CS_MAP__REG DENALI_CTL_278
-#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_278__CS_MAP
-
-#define LPDDR4__DENALI_CTL_278__REDUC_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_278__REDUC_SHIFT 24U
-#define LPDDR4__DENALI_CTL_278__REDUC_WIDTH 1U
-#define LPDDR4__DENALI_CTL_278__REDUC_WOCLR 0U
-#define LPDDR4__DENALI_CTL_278__REDUC_WOSET 0U
-#define LPDDR4__REDUC__REG DENALI_CTL_278
-#define LPDDR4__REDUC__FLD LPDDR4__DENALI_CTL_278__REDUC
-
-#define LPDDR4__DENALI_CTL_279_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_279_WRITE_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_WIDTH 18U
-#define LPDDR4__FAULT_FIFO_PROTECTION_EN__REG DENALI_CTL_279
-#define LPDDR4__FAULT_FIFO_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_280_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_280_WRITE_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_WIDTH 18U
-#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__REG DENALI_CTL_280
-#define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS
-
-#define LPDDR4__DENALI_CTL_281_READ_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_CTL_281_WRITE_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_WIDTH 18U
-#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__REG DENALI_CTL_281
-#define LPDDR4__FAULT_FIFO_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN_WOSET 0U
-#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_281
-#define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_282_READ_MASK 0x01010103U
-#define LPDDR4__DENALI_CTL_282_WRITE_MASK 0x01010103U
-#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_WIDTH 2U
-#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
-#define LPDDR4__WRITE_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN_WOSET 0U
-#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__REG DENALI_CTL_282
-#define LPDDR4__WRITE_RESP_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__WRITE_RESP_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET 0U
-#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_282
-#define LPDDR4__READ_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET 0U
-#define LPDDR4__READ_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
-#define LPDDR4__READ_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_283_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_283_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT 0U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH 1U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR 0U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET 0U
-#define LPDDR4__MC_RESERVED26__REG DENALI_CTL_283
-#define LPDDR4__MC_RESERVED26__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED26
-
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT 8U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH 1U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR 0U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET 0U
-#define LPDDR4__MC_RESERVED27__REG DENALI_CTL_283
-#define LPDDR4__MC_RESERVED27__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED27
-
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN_WOSET 0U
-#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__REG DENALI_CTL_283
-#define LPDDR4__WRITE_PARITY_ERR_BRESP_EN__FLD LPDDR4__DENALI_CTL_283__WRITE_PARITY_ERR_BRESP_EN
-
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET 0U
-#define LPDDR4__READ_PARITY_ERR_RRESP_EN__REG DENALI_CTL_283
-#define LPDDR4__READ_PARITY_ERR_RRESP_EN__FLD LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN
-
-#define LPDDR4__DENALI_CTL_284_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_284_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U
-#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
-#define LPDDR4__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN_WOSET 0U
-#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
-#define LPDDR4__WRITE_DATA_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_DATA_CHAN_TRIGGER_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN_WOSET 0U
-#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_284
-#define LPDDR4__WRITE_RESP_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__WRITE_RESP_CHAN_CORRUPT_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN_WOSET 0U
-#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
-#define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_285_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_285_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WOSET 0U
-#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__REG DENALI_CTL_285
-#define LPDDR4__READ_DATA_CHAN_CORRUPT_PARITY_EN__FLD LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN
-
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_SHIFT 8U
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT_WOSET 0U
-#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__REG DENALI_CTL_285
-#define LPDDR4__ECC_AXI_ERROR_RESPONSE_INHIBIT__FLD LPDDR4__DENALI_CTL_285__ECC_AXI_ERROR_RESPONSE_INHIBIT
-
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN_WOSET 0U
-#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__REG DENALI_CTL_285
-#define LPDDR4__WRITE_PARITY_ERR_CORRUPT_ECC_EN__FLD LPDDR4__DENALI_CTL_285__WRITE_PARITY_ERR_CORRUPT_ECC_EN
-
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN_WOSET 0U
-#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__REG DENALI_CTL_285
-#define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_286_READ_MASK 0x0F0F0F07U
-#define LPDDR4__DENALI_CTL_286_WRITE_MASK 0x0F0F0F07U
-#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH 3U
-#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_286
-#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0
-
-#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH 4U
-#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_286
-#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0
-
-#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH 4U
-#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_286
-#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0
-
-#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH 4U
-#define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_286
-#define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0
-
-#define LPDDR4__DENALI_CTL_287_READ_MASK 0x0F0F070FU
-#define LPDDR4__DENALI_CTL_287_WRITE_MASK 0x0F0F070FU
-#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH 4U
-#define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_287
-#define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0
-
-#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK 0x00000700U
-#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH 3U
-#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_287
-#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1
-
-#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH 4U
-#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_287
-#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1
-
-#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH 4U
-#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_287
-#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1
-
-#define LPDDR4__DENALI_CTL_288_READ_MASK 0x011F0F0FU
-#define LPDDR4__DENALI_CTL_288_WRITE_MASK 0x011F0F0FU
-#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH 4U
-#define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_288
-#define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1
-
-#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH 4U
-#define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_288
-#define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1
-
-#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT 16U
-#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH 5U
-#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_288
-#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_288__Q_FULLNESS
-
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT 24U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET 0U
-#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_288
-#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT
-
-#define LPDDR4__DENALI_CTL_289_READ_MASK 0x01000103U
-#define LPDDR4__DENALI_CTL_289_WRITE_MASK 0x01000103U
-#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT 0U
-#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH 2U
-#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_289
-#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_289__WR_ORDER_REQ
-
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT 8U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH 1U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR 0U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET 0U
-#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_289
-#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY
-
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT 16U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH 1U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR 0U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET 0U
-#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_289
-#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ
-
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
-#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_289
-#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN
-
-#define LPDDR4__DENALI_CTL_290_READ_MASK 0x03030301U
-#define LPDDR4__DENALI_CTL_290_WRITE_MASK 0x03030301U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET 0U
-#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_290
-#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE
-
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH 2U
-#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_290
-#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0
-
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH 2U
-#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_290
-#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1
-
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_MASK 0x03000000U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH 2U
-#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_290
-#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2
-
-#define LPDDR4__DENALI_CTL_291_READ_MASK 0x1F010101U
-#define LPDDR4__DENALI_CTL_291_WRITE_MASK 0x1F010101U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET 0U
-#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_291
-#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN
-
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET 0U
-#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_291
-#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_291__WR_DBI_EN
-
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET 0U
-#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_291
-#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_291__RD_DBI_EN
-
-#define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT 24U
-#define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH 5U
-#define LPDDR4__DFI_ERROR__REG DENALI_CTL_291
-#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_291__DFI_ERROR
-
-#define LPDDR4__DENALI_CTL_292_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_292_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT 0U
-#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH 20U
-#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_292
-#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO
-
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT 24U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH 1U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR 0U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET 0U
-#define LPDDR4__MC_RESERVED28__REG DENALI_CTL_292
-#define LPDDR4__MC_RESERVED28__FLD LPDDR4__DENALI_CTL_292__MC_RESERVED28
-
-#define LPDDR4__DENALI_CTL_293_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_293_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH 32U
-#define LPDDR4__INT_STATUS_0__REG DENALI_CTL_293
-#define LPDDR4__INT_STATUS_0__FLD LPDDR4__DENALI_CTL_293__INT_STATUS_0
-
-#define LPDDR4__DENALI_CTL_294_READ_MASK 0x00001FFFU
-#define LPDDR4__DENALI_CTL_294_WRITE_MASK 0x00001FFFU
-#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK 0x00001FFFU
-#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH 13U
-#define LPDDR4__INT_STATUS_1__REG DENALI_CTL_294
-#define LPDDR4__INT_STATUS_1__FLD LPDDR4__DENALI_CTL_294__INT_STATUS_1
-
-#define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH 32U
-#define LPDDR4__INT_ACK_0__REG DENALI_CTL_295
-#define LPDDR4__INT_ACK_0__FLD LPDDR4__DENALI_CTL_295__INT_ACK_0
-
-#define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK 0x00000FFFU
-#define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH 12U
-#define LPDDR4__INT_ACK_1__REG DENALI_CTL_296
-#define LPDDR4__INT_ACK_1__FLD LPDDR4__DENALI_CTL_296__INT_ACK_1
-
-#define LPDDR4__DENALI_CTL_297_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_297_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH 32U
-#define LPDDR4__INT_MASK_0__REG DENALI_CTL_297
-#define LPDDR4__INT_MASK_0__FLD LPDDR4__DENALI_CTL_297__INT_MASK_0
-
-#define LPDDR4__DENALI_CTL_298_READ_MASK 0x00001FFFU
-#define LPDDR4__DENALI_CTL_298_WRITE_MASK 0x00001FFFU
-#define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK 0x00001FFFU
-#define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH 13U
-#define LPDDR4__INT_MASK_1__REG DENALI_CTL_298
-#define LPDDR4__INT_MASK_1__FLD LPDDR4__DENALI_CTL_298__INT_MASK_1
-
-#define LPDDR4__DENALI_CTL_299_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_299_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH 32U
-#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_299
-#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0
-
-#define LPDDR4__DENALI_CTL_300_READ_MASK 0x7F0FFF07U
-#define LPDDR4__DENALI_CTL_300_WRITE_MASK 0x7F0FFF07U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH 3U
-#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_300
-#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1
-
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_MASK 0x000FFF00U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT 8U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH 12U
-#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_300
-#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH
-
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_MASK 0x7F000000U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT 24U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH 7U
-#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_300
-#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE
-
-#define LPDDR4__DENALI_CTL_301_READ_MASK 0x0000003FU
-#define LPDDR4__DENALI_CTL_301_WRITE_MASK 0x0000003FU
-#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_MASK 0x0000003FU
-#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT 0U
-#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH 6U
-#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_301
-#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID
-
-#define LPDDR4__DENALI_CTL_302_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_302_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH 32U
-#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_302
-#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0
-
-#define LPDDR4__DENALI_CTL_303_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_303_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH 32U
-#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_303
-#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1
-
-#define LPDDR4__DENALI_CTL_304_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_304_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH 32U
-#define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_304
-#define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2
-
-#define LPDDR4__DENALI_CTL_305_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_305_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT 0U
-#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH 32U
-#define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_305
-#define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3
-
-#define LPDDR4__DENALI_CTL_306_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_306_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH 32U
-#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_306
-#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0
-
-#define LPDDR4__DENALI_CTL_307_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_307_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH 32U
-#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_307
-#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1
-
-#define LPDDR4__DENALI_CTL_308_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_308_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH 32U
-#define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_308
-#define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2
-
-#define LPDDR4__DENALI_CTL_309_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_309_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT 0U
-#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH 32U
-#define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_309
-#define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3
-
-#define LPDDR4__DENALI_CTL_310_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_310_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH 32U
-#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_310
-#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0
-
-#define LPDDR4__DENALI_CTL_311_READ_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_311_WRITE_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH 3U
-#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_311
-#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1
-
-#define LPDDR4__DENALI_CTL_312_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_312_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH 32U
-#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_312
-#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0
-
-#define LPDDR4__DENALI_CTL_313_READ_MASK 0x03033F07U
-#define LPDDR4__DENALI_CTL_313_WRITE_MASK 0x03033F07U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH 3U
-#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_313
-#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1
-
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_MASK 0x00003F00U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT 8U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH 6U
-#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_313
-#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID
-
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH 2U
-#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_313
-#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE
-
-#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK 0x03000000U
-#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH 2U
-#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_313
-#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0
-
-#define LPDDR4__DENALI_CTL_314_READ_MASK 0xFF030303U
-#define LPDDR4__DENALI_CTL_314_WRITE_MASK 0xFF030303U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK 0x00000003U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH 2U
-#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_314
-#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0
-
-#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH 2U
-#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_314
-#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1
-
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH 2U
-#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_314
-#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1
-
-#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH 8U
-#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_314
-#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0
-
-#define LPDDR4__DENALI_CTL_315_READ_MASK 0x0FFF0F0FU
-#define LPDDR4__DENALI_CTL_315_WRITE_MASK 0x0FFF0F0FU
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH 4U
-#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_315
-#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F0
-
-#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH 4U
-#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_315
-#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_RD_F0
-
-#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH 8U
-#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_315
-#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1
-
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH 4U
-#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_315
-#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F1
-
-#define LPDDR4__DENALI_CTL_316_READ_MASK 0x0F0FFF0FU
-#define LPDDR4__DENALI_CTL_316_WRITE_MASK 0x0F0FFF0FU
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH 4U
-#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_316
-#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F1
-
-#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH 8U
-#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_316
-#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2
-
-#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH 4U
-#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_316
-#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_WR_F2
-
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH 4U
-#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_316
-#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F2
-
-#define LPDDR4__DENALI_CTL_317_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_317_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH 1U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR 0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET 0U
-#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_317
-#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F0
-
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH 1U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR 0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET 0U
-#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_317
-#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F1
-
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH 1U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR 0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET 0U
-#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_317
-#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F2
-
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT 24U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH 1U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR 0U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET 0U
-#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_317
-#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD
-
-#define LPDDR4__DENALI_CTL_318_READ_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_CTL_318_WRITE_MASK 0x3F3F3F3FU
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK 0x0000003FU
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH 6U
-#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_318
-#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0
-
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK 0x00003F00U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH 6U
-#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_318
-#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1
-
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK 0x003F0000U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH 6U
-#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_318
-#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2
-
-#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK 0x3F000000U
-#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH 6U
-#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_318
-#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0
-
-#define LPDDR4__DENALI_CTL_319_READ_MASK 0x1F1F3F3FU
-#define LPDDR4__DENALI_CTL_319_WRITE_MASK 0x1F1F3F3FU
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK 0x0000003FU
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH 6U
-#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_319
-#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1
-
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK 0x00003F00U
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH 6U
-#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_319
-#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2
-
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH 5U
-#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_319
-#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0
-
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH 5U
-#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_319
-#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1
-
-#define LPDDR4__DENALI_CTL_320_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_320_WRITE_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH 5U
-#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_320
-#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2
-
-#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH 5U
-#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
-#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH 5U
-#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_320
-#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH 5U
-#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
-#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_321_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_321_WRITE_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH 5U
-#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_321
-#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH 5U
-#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
-#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH 5U
-#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_321
-#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH 5U
-#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
-#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_322_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_322_WRITE_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH 5U
-#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_322
-#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH 5U
-#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
-#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH 5U
-#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_322
-#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH 5U
-#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
-#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_323_READ_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_323_WRITE_MASK 0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH 5U
-#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_323
-#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT 8U
-#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH 5U
-#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_323
-#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY
-
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH 5U
-#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_323
-#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0
-
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_MASK 0x1F000000U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH 5U
-#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_323
-#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1
-
-#define LPDDR4__DENALI_CTL_324_READ_MASK 0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_324_WRITE_MASK 0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_MASK 0x0000001FU
-#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH 5U
-#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_324
-#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2
-
-#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK 0x00001F00U
-#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT 8U
-#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH 5U
-#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_324
-#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY
-
-#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT 16U
-#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH 5U
-#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_324
-#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY
-
-#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH 4U
-#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_324
-#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0
-
-#define LPDDR4__DENALI_CTL_325_READ_MASK 0x0F070F07U
-#define LPDDR4__DENALI_CTL_325_WRITE_MASK 0x0F070F07U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH 3U
-#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_325
-#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0
-
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH 4U
-#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_325
-#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1
-
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK 0x00070000U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH 3U
-#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_325
-#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1
-
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH 4U
-#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_325
-#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2
-
-#define LPDDR4__DENALI_CTL_326_READ_MASK 0x00000707U
-#define LPDDR4__DENALI_CTL_326_WRITE_MASK 0x00000707U
-#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH 3U
-#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_326
-#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2
-
-#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK 0x00000700U
-#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT 8U
-#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH 3U
-#define LPDDR4__SW_LEVELING_MODE__REG DENALI_CTL_326
-#define LPDDR4__SW_LEVELING_MODE__FLD LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE
-
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT 16U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH 1U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR 0U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET 0U
-#define LPDDR4__SWLVL_LOAD__REG DENALI_CTL_326
-#define LPDDR4__SWLVL_LOAD__FLD LPDDR4__DENALI_CTL_326__SWLVL_LOAD
-
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT 24U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH 1U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR 0U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET 0U
-#define LPDDR4__SWLVL_START__REG DENALI_CTL_326
-#define LPDDR4__SWLVL_START__FLD LPDDR4__DENALI_CTL_326__SWLVL_START
-
-#define LPDDR4__DENALI_CTL_327_READ_MASK 0x01010100U
-#define LPDDR4__DENALI_CTL_327_WRITE_MASK 0x01010100U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT 0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET 0U
-#define LPDDR4__SWLVL_EXIT__REG DENALI_CTL_327
-#define LPDDR4__SWLVL_EXIT__FLD LPDDR4__DENALI_CTL_327__SWLVL_EXIT
-
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT 8U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET 0U
-#define LPDDR4__SWLVL_OP_DONE__REG DENALI_CTL_327
-#define LPDDR4__SWLVL_OP_DONE__FLD LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE
-
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH 1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR 0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET 0U
-#define LPDDR4__SWLVL_RESP_0__REG DENALI_CTL_327
-#define LPDDR4__SWLVL_RESP_0__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_0
-
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH 1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR 0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET 0U
-#define LPDDR4__SWLVL_RESP_1__REG DENALI_CTL_327
-#define LPDDR4__SWLVL_RESP_1__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_1
-
-#define LPDDR4__DENALI_CTL_328_READ_MASK 0x00010101U
-#define LPDDR4__DENALI_CTL_328_WRITE_MASK 0x00010101U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH 1U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR 0U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET 0U
-#define LPDDR4__SWLVL_RESP_2__REG DENALI_CTL_328
-#define LPDDR4__SWLVL_RESP_2__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_2
-
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT 8U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH 1U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR 0U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET 0U
-#define LPDDR4__SWLVL_RESP_3__REG DENALI_CTL_328
-#define LPDDR4__SWLVL_RESP_3__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_3
-
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET 0U
-#define LPDDR4__PHYUPD_APPEND_EN__REG DENALI_CTL_328
-#define LPDDR4__PHYUPD_APPEND_EN__FLD LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN
-
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT 24U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH 1U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR 0U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET 0U
-#define LPDDR4__WRLVL_REQ__REG DENALI_CTL_328
-#define LPDDR4__WRLVL_REQ__FLD LPDDR4__DENALI_CTL_328__WRLVL_REQ
-
-#define LPDDR4__DENALI_CTL_329_READ_MASK 0x013F3F01U
-#define LPDDR4__DENALI_CTL_329_WRITE_MASK 0x013F3F01U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET 0U
-#define LPDDR4__WRLVL_CS__REG DENALI_CTL_329
-#define LPDDR4__WRLVL_CS__FLD LPDDR4__DENALI_CTL_329__WRLVL_CS
-
-#define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK 0x00003F00U
-#define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH 6U
-#define LPDDR4__WLDQSEN__REG DENALI_CTL_329
-#define LPDDR4__WLDQSEN__FLD LPDDR4__DENALI_CTL_329__WLDQSEN
-
-#define LPDDR4__DENALI_CTL_329__WLMRD_MASK 0x003F0000U
-#define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT 16U
-#define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH 6U
-#define LPDDR4__WLMRD__REG DENALI_CTL_329
-#define LPDDR4__WLMRD__FLD LPDDR4__DENALI_CTL_329__WLMRD
-
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET 0U
-#define LPDDR4__WRLVL_EN__REG DENALI_CTL_329
-#define LPDDR4__WRLVL_EN__FLD LPDDR4__DENALI_CTL_329__WRLVL_EN
-
-#define LPDDR4__DENALI_CTL_330_READ_MASK 0x0F010101U
-#define LPDDR4__DENALI_CTL_330_WRITE_MASK 0x0F010101U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET 0U
-#define LPDDR4__DFI_PHY_WRLVL_MODE__REG DENALI_CTL_330
-#define LPDDR4__DFI_PHY_WRLVL_MODE__FLD LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE
-
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT 8U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH 1U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR 0U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET 0U
-#define LPDDR4__WRLVL_PERIODIC__REG DENALI_CTL_330
-#define LPDDR4__WRLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC
-
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT 16U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET 0U
-#define LPDDR4__WRLVL_ON_SREF_EXIT__REG DENALI_CTL_330
-#define LPDDR4__WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT 24U
-#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH 4U
-#define LPDDR4__WRLVL_RESP_MASK__REG DENALI_CTL_330
-#define LPDDR4__WRLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK
-
-#define LPDDR4__DENALI_CTL_331_READ_MASK 0x07030101U
-#define LPDDR4__DENALI_CTL_331_WRITE_MASK 0x07030101U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET 0U
-#define LPDDR4__WRLVL_AREF_EN__REG DENALI_CTL_331
-#define LPDDR4__WRLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN
-
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT 8U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET 0U
-#define LPDDR4__WRLVL_ROTATE__REG DENALI_CTL_331
-#define LPDDR4__WRLVL_ROTATE__FLD LPDDR4__DENALI_CTL_331__WRLVL_ROTATE
-
-#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT 16U
-#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH 2U
-#define LPDDR4__WRLVL_CS_MAP__REG DENALI_CTL_331
-#define LPDDR4__WRLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP
-
-#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT 24U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH 3U
-#define LPDDR4__WRLVL_ERROR_STATUS__REG DENALI_CTL_331
-#define LPDDR4__WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_332_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_332_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_332
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_332
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_333_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_333_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH 16U
-#define LPDDR4__WRLVL_TIMEOUT_F0__REG DENALI_CTL_333
-#define LPDDR4__WRLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_333
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_334_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_334_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_334
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_334
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_335_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_335_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_335
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH 16U
-#define LPDDR4__WRLVL_TIMEOUT_F1__REG DENALI_CTL_335
-#define LPDDR4__WRLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_336_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_336_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_337_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_337_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_337
-#define LPDDR4__WRLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_337
-#define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_338_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_338_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH 16U
-#define LPDDR4__WRLVL_TIMEOUT_F2__REG DENALI_CTL_338
-#define LPDDR4__WRLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_338
-#define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_339_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_339_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_339
-#define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT 16U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH 1U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR 0U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET 0U
-#define LPDDR4__RDLVL_REQ__REG DENALI_CTL_339
-#define LPDDR4__RDLVL_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_REQ
-
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT 24U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH 1U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR 0U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET 0U
-#define LPDDR4__RDLVL_GATE_REQ__REG DENALI_CTL_339
-#define LPDDR4__RDLVL_GATE_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ
-
-#define LPDDR4__DENALI_CTL_340_READ_MASK 0x010F0F01U
-#define LPDDR4__DENALI_CTL_340_WRITE_MASK 0x010F0F01U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET 0U
-#define LPDDR4__RDLVL_CS__REG DENALI_CTL_340
-#define LPDDR4__RDLVL_CS__FLD LPDDR4__DENALI_CTL_340__RDLVL_CS
-
-#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH 4U
-#define LPDDR4__RDLVL_SEQ_EN__REG DENALI_CTL_340
-#define LPDDR4__RDLVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN
-
-#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH 4U
-#define LPDDR4__RDLVL_GATE_SEQ_EN__REG DENALI_CTL_340
-#define LPDDR4__RDLVL_GATE_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN
-
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT 24U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET 0U
-#define LPDDR4__DFI_PHY_RDLVL_MODE__REG DENALI_CTL_340
-#define LPDDR4__DFI_PHY_RDLVL_MODE__FLD LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE
-
-#define LPDDR4__DENALI_CTL_341_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_341_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET 0U
-#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__REG DENALI_CTL_341
-#define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__FLD LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE
-
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT 8U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH 1U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR 0U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET 0U
-#define LPDDR4__RDLVL_PERIODIC__REG DENALI_CTL_341
-#define LPDDR4__RDLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC
-
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT 16U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET 0U
-#define LPDDR4__RDLVL_ON_SREF_EXIT__REG DENALI_CTL_341
-#define LPDDR4__RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT 24U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH 1U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR 0U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET 0U
-#define LPDDR4__RDLVL_GATE_PERIODIC__REG DENALI_CTL_341
-#define LPDDR4__RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC
-
-#define LPDDR4__DENALI_CTL_342_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_342_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT 0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET 0U
-#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__REG DENALI_CTL_342
-#define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET 0U
-#define LPDDR4__RDLVL_AREF_EN__REG DENALI_CTL_342
-#define LPDDR4__RDLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN
-
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET 0U
-#define LPDDR4__RDLVL_GATE_AREF_EN__REG DENALI_CTL_342
-#define LPDDR4__RDLVL_GATE_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN
-
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT 24U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH 1U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR 0U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET 0U
-#define LPDDR4__MC_RESERVED29__REG DENALI_CTL_342
-#define LPDDR4__MC_RESERVED29__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED29
-
-#define LPDDR4__DENALI_CTL_343_READ_MASK 0x03030101U
-#define LPDDR4__DENALI_CTL_343_WRITE_MASK 0x03030101U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET 0U
-#define LPDDR4__RDLVL_ROTATE__REG DENALI_CTL_343
-#define LPDDR4__RDLVL_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_ROTATE
-
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT 8U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET 0U
-#define LPDDR4__RDLVL_GATE_ROTATE__REG DENALI_CTL_343
-#define LPDDR4__RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE
-
-#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT 16U
-#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH 2U
-#define LPDDR4__RDLVL_CS_MAP__REG DENALI_CTL_343
-#define LPDDR4__RDLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP
-
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_MASK 0x03000000U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT 24U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH 2U
-#define LPDDR4__RDLVL_GATE_CS_MAP__REG DENALI_CTL_343
-#define LPDDR4__RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP
-
-#define LPDDR4__DENALI_CTL_344_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_344_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_344
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_344
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_345_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_345_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH 16U
-#define LPDDR4__RDLVL_TIMEOUT_F0__REG DENALI_CTL_345
-#define LPDDR4__RDLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_345
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_346_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_346_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_346
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__REG DENALI_CTL_346
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_347_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_347_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__REG DENALI_CTL_347
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__REG DENALI_CTL_347
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_348_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_348_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_349_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_349_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_349
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_349
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_350_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_350_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH 16U
-#define LPDDR4__RDLVL_TIMEOUT_F1__REG DENALI_CTL_350
-#define LPDDR4__RDLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_350
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_351_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_351_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_351
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__REG DENALI_CTL_351
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_352_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_352_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__REG DENALI_CTL_352
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__REG DENALI_CTL_352
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_353_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_353_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_354_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_354_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_354
-#define LPDDR4__RDLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_354
-#define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_355_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_355_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH 16U
-#define LPDDR4__RDLVL_TIMEOUT_F2__REG DENALI_CTL_355
-#define LPDDR4__RDLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_355
-#define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_356_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_356_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_356
-#define LPDDR4__RDLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__REG DENALI_CTL_356
-#define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_357_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_357_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__REG DENALI_CTL_357
-#define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__REG DENALI_CTL_357
-#define LPDDR4__RDLVL_GATE_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_358_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_358_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
-#define LPDDR4__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
-#define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_359_READ_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_359_WRITE_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT 0U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH 1U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR 0U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET 0U
-#define LPDDR4__CALVL_REQ__REG DENALI_CTL_359
-#define LPDDR4__CALVL_REQ__FLD LPDDR4__DENALI_CTL_359__CALVL_REQ
-
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH 1U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR 0U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET 0U
-#define LPDDR4__CALVL_CS__REG DENALI_CTL_359
-#define LPDDR4__CALVL_CS__FLD LPDDR4__DENALI_CTL_359__CALVL_CS
-
-#define LPDDR4__DENALI_CTL_360_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_360_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH 20U
-#define LPDDR4__CALVL_PAT_0__REG DENALI_CTL_360
-#define LPDDR4__CALVL_PAT_0__FLD LPDDR4__DENALI_CTL_360__CALVL_PAT_0
-
-#define LPDDR4__DENALI_CTL_361_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_361_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH 20U
-#define LPDDR4__CALVL_BG_PAT_0__REG DENALI_CTL_361
-#define LPDDR4__CALVL_BG_PAT_0__FLD LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0
-
-#define LPDDR4__DENALI_CTL_362_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_362_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH 20U
-#define LPDDR4__CALVL_PAT_1__REG DENALI_CTL_362
-#define LPDDR4__CALVL_PAT_1__FLD LPDDR4__DENALI_CTL_362__CALVL_PAT_1
-
-#define LPDDR4__DENALI_CTL_363_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_363_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH 20U
-#define LPDDR4__CALVL_BG_PAT_1__REG DENALI_CTL_363
-#define LPDDR4__CALVL_BG_PAT_1__FLD LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1
-
-#define LPDDR4__DENALI_CTL_364_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_364_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH 20U
-#define LPDDR4__CALVL_PAT_2__REG DENALI_CTL_364
-#define LPDDR4__CALVL_PAT_2__FLD LPDDR4__DENALI_CTL_364__CALVL_PAT_2
-
-#define LPDDR4__DENALI_CTL_365_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_365_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH 20U
-#define LPDDR4__CALVL_BG_PAT_2__REG DENALI_CTL_365
-#define LPDDR4__CALVL_BG_PAT_2__FLD LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2
-
-#define LPDDR4__DENALI_CTL_366_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_366_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT 0U
-#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH 20U
-#define LPDDR4__CALVL_PAT_3__REG DENALI_CTL_366
-#define LPDDR4__CALVL_PAT_3__FLD LPDDR4__DENALI_CTL_366__CALVL_PAT_3
-
-#define LPDDR4__DENALI_CTL_367_READ_MASK 0x010FFFFFU
-#define LPDDR4__DENALI_CTL_367_WRITE_MASK 0x010FFFFFU
-#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT 0U
-#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH 20U
-#define LPDDR4__CALVL_BG_PAT_3__REG DENALI_CTL_367
-#define LPDDR4__CALVL_BG_PAT_3__FLD LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3
-
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT 24U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH 1U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR 0U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET 0U
-#define LPDDR4__MC_RESERVED30__REG DENALI_CTL_367
-#define LPDDR4__MC_RESERVED30__FLD LPDDR4__DENALI_CTL_367__MC_RESERVED30
-
-#define LPDDR4__DENALI_CTL_368_READ_MASK 0x0101030FU
-#define LPDDR4__DENALI_CTL_368_WRITE_MASK 0x0101030FU
-#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT 0U
-#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH 4U
-#define LPDDR4__MC_RESERVED31__REG DENALI_CTL_368
-#define LPDDR4__MC_RESERVED31__FLD LPDDR4__DENALI_CTL_368__MC_RESERVED31
-
-#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH 2U
-#define LPDDR4__CALVL_SEQ_EN__REG DENALI_CTL_368
-#define LPDDR4__CALVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN
-
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET 0U
-#define LPDDR4__DFI_PHY_CALVL_MODE__REG DENALI_CTL_368
-#define LPDDR4__DFI_PHY_CALVL_MODE__FLD LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE
-
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT 24U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH 1U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR 0U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET 0U
-#define LPDDR4__CALVL_PERIODIC__REG DENALI_CTL_368
-#define LPDDR4__CALVL_PERIODIC__FLD LPDDR4__DENALI_CTL_368__CALVL_PERIODIC
-
-#define LPDDR4__DENALI_CTL_369_READ_MASK 0x03010101U
-#define LPDDR4__DENALI_CTL_369_WRITE_MASK 0x03010101U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT 0U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET 0U
-#define LPDDR4__CALVL_ON_SREF_EXIT__REG DENALI_CTL_369
-#define LPDDR4__CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET 0U
-#define LPDDR4__CALVL_AREF_EN__REG DENALI_CTL_369
-#define LPDDR4__CALVL_AREF_EN__FLD LPDDR4__DENALI_CTL_369__CALVL_AREF_EN
-
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET 0U
-#define LPDDR4__CALVL_ROTATE__REG DENALI_CTL_369
-#define LPDDR4__CALVL_ROTATE__FLD LPDDR4__DENALI_CTL_369__CALVL_ROTATE
-
-#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK 0x03000000U
-#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT 24U
-#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH 2U
-#define LPDDR4__CALVL_CS_MAP__REG DENALI_CTL_369
-#define LPDDR4__CALVL_CS_MAP__FLD LPDDR4__DENALI_CTL_369__CALVL_CS_MAP
-
-#define LPDDR4__DENALI_CTL_370_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_370_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__CALVL_NORM_THRESHOLD_F0__REG DENALI_CTL_370
-#define LPDDR4__CALVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_370
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_371_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_371_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH 16U
-#define LPDDR4__CALVL_TIMEOUT_F0__REG DENALI_CTL_371
-#define LPDDR4__CALVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0
-
-#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_371
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_372_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_372_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH 16U
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_372
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0
-
-#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__CALVL_NORM_THRESHOLD_F1__REG DENALI_CTL_372
-#define LPDDR4__CALVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_373_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_373_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_373
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH 16U
-#define LPDDR4__CALVL_TIMEOUT_F1__REG DENALI_CTL_373
-#define LPDDR4__CALVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1
-
-#define LPDDR4__DENALI_CTL_374_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_374_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH 16U
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1
-
-#define LPDDR4__DENALI_CTL_375_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_375_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__CALVL_NORM_THRESHOLD_F2__REG DENALI_CTL_375
-#define LPDDR4__CALVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_375
-#define LPDDR4__CALVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_376_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_376_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH 16U
-#define LPDDR4__CALVL_TIMEOUT_F2__REG DENALI_CTL_376
-#define LPDDR4__CALVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2
-
-#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_376
-#define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_377_READ_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_CTL_377_WRITE_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH 16U
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_377
-#define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2
-
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE_WOSET 0U
-#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_377
-#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_ALL_STROBES_USED_ENABLE
-
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT 24U
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET 0U
-#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_377
-#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE
-
-#define LPDDR4__DENALI_CTL_378_READ_MASK 0x00000707U
-#define LPDDR4__DENALI_CTL_378_WRITE_MASK 0x00000707U
-#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT 0U
-#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH 3U
-#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_378
-#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY
-
-#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK 0x00000700U
-#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT 8U
-#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH 3U
-#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_378
-#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY
-
-#define LPDDR4__DENALI_CTL_379_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_379_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH 32U
-#define LPDDR4__PARITY_ERROR_ADDRESS_0__REG DENALI_CTL_379
-#define LPDDR4__PARITY_ERROR_ADDRESS_0__FLD LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0
-
-#define LPDDR4__DENALI_CTL_380_READ_MASK 0x1FFF3F07U
-#define LPDDR4__DENALI_CTL_380_WRITE_MASK 0x1FFF3F07U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH 3U
-#define LPDDR4__PARITY_ERROR_ADDRESS_1__REG DENALI_CTL_380
-#define LPDDR4__PARITY_ERROR_ADDRESS_1__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1
-
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_MASK 0x00003F00U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT 8U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH 6U
-#define LPDDR4__PARITY_ERROR_MASTER_ID__REG DENALI_CTL_380
-#define LPDDR4__PARITY_ERROR_MASTER_ID__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID
-
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_MASK 0x1FFF0000U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_SHIFT 16U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL_WIDTH 13U
-#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__REG DENALI_CTL_380
-#define LPDDR4__PARITY_ERROR_BUS_CHANNEL__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL
-
-#define LPDDR4__DENALI_CTL_381_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_381_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_WIDTH 32U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__REG DENALI_CTL_381
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_0__FLD LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0
-
-#define LPDDR4__DENALI_CTL_382_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_382_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_WIDTH 32U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__REG DENALI_CTL_382
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_1__FLD LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1
-
-#define LPDDR4__DENALI_CTL_383_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_383_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_WIDTH 32U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__REG DENALI_CTL_383
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_2__FLD LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2
-
-#define LPDDR4__DENALI_CTL_384_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_384_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_SHIFT 0U
-#define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_WIDTH 32U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__REG DENALI_CTL_384
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_3__FLD LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3
-
-#define LPDDR4__DENALI_CTL_385_READ_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_CTL_385_WRITE_MASK 0x0103FFFFU
-#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_SHIFT 0U
-#define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_WIDTH 16U
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__REG DENALI_CTL_385
-#define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__FLD LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR
-
-#define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK 0x00030000U
-#define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT 16U
-#define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH 2U
-#define LPDDR4__CKE_STATUS__REG DENALI_CTL_385
-#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_385__CKE_STATUS
-
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT 24U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH 1U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR 0U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET 0U
-#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_385
-#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_385__MEM_RST_VALID
-
-#define LPDDR4__DENALI_CTL_386_READ_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_CTL_386_WRITE_MASK 0x7FFFFFFFU
-#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT 0U
-#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH 16U
-#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_386
-#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_DELAY
-
-#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT 16U
-#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH 8U
-#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_386
-#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY
-
-#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK 0x7F000000U
-#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT 24U
-#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH 7U
-#define LPDDR4__TDFI_PHY_WRLAT__REG DENALI_CTL_386
-#define LPDDR4__TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT
-
-#define LPDDR4__DENALI_CTL_387_READ_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_387_WRITE_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH 7U
-#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_387
-#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_MASK 0x00007F00U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH 7U
-#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_387
-#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0
-
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_MASK 0x007F0000U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH 7U
-#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_387
-#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1
-
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_MASK 0x7F000000U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH 7U
-#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_387
-#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2
-
-#define LPDDR4__DENALI_CTL_388_READ_MASK 0x00FF037FU
-#define LPDDR4__DENALI_CTL_388_WRITE_MASK 0x00FF037FU
-#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH 7U
-#define LPDDR4__TDFI_RDDATA_EN__REG DENALI_CTL_388
-#define LPDDR4__TDFI_RDDATA_EN__FLD LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN
-
-#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT 8U
-#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH 2U
-#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_388
-#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE
-
-#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH 8U
-#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_388
-#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN
-
-#define LPDDR4__DENALI_CTL_389_READ_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_CTL_389_WRITE_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH 21U
-#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_389
-#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0
-
-#define LPDDR4__DENALI_CTL_390_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_390_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_390
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0
-
-#define LPDDR4__DENALI_CTL_391_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_391_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_391
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0
-
-#define LPDDR4__DENALI_CTL_392_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_392_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_392
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0
-
-#define LPDDR4__DENALI_CTL_393_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_393_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_393
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0
-
-#define LPDDR4__DENALI_CTL_394_READ_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_CTL_394_WRITE_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH 23U
-#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_394
-#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0
-
-#define LPDDR4__DENALI_CTL_395_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_395_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_395
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0
-
-#define LPDDR4__DENALI_CTL_396_READ_MASK 0x00007F7FU
-#define LPDDR4__DENALI_CTL_396_WRITE_MASK 0x00007F7FU
-#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH 7U
-#define LPDDR4__RDLAT_ADJ_F0__REG DENALI_CTL_396
-#define LPDDR4__RDLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0
-
-#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK 0x00007F00U
-#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT 8U
-#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH 7U
-#define LPDDR4__WRLAT_ADJ_F0__REG DENALI_CTL_396
-#define LPDDR4__WRLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0
-
-#define LPDDR4__DENALI_CTL_397_READ_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_CTL_397_WRITE_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH 21U
-#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_397
-#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1
-
-#define LPDDR4__DENALI_CTL_398_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_398_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_398
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1
-
-#define LPDDR4__DENALI_CTL_399_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_399_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_399
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1
-
-#define LPDDR4__DENALI_CTL_400_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_400_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_400
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1
-
-#define LPDDR4__DENALI_CTL_401_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_401_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_401
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1
-
-#define LPDDR4__DENALI_CTL_402_READ_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_CTL_402_WRITE_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH 23U
-#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_402
-#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1
-
-#define LPDDR4__DENALI_CTL_403_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_403_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_403
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1
-
-#define LPDDR4__DENALI_CTL_404_READ_MASK 0x00007F7FU
-#define LPDDR4__DENALI_CTL_404_WRITE_MASK 0x00007F7FU
-#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH 7U
-#define LPDDR4__RDLAT_ADJ_F1__REG DENALI_CTL_404
-#define LPDDR4__RDLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1
-
-#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK 0x00007F00U
-#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH 7U
-#define LPDDR4__WRLAT_ADJ_F1__REG DENALI_CTL_404
-#define LPDDR4__WRLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1
-
-#define LPDDR4__DENALI_CTL_405_READ_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_CTL_405_WRITE_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH 21U
-#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_405
-#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2
-
-#define LPDDR4__DENALI_CTL_406_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_406_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_406
-#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2
-
-#define LPDDR4__DENALI_CTL_407_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_407_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_407
-#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2
-
-#define LPDDR4__DENALI_CTL_408_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_408_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_408
-#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2
-
-#define LPDDR4__DENALI_CTL_409_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_409_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH 32U
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_409
-#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2
-
-#define LPDDR4__DENALI_CTL_410_READ_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_CTL_410_WRITE_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_MASK 0x007FFFFFU
-#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH 23U
-#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_410
-#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2
-
-#define LPDDR4__DENALI_CTL_411_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_411_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_411
-#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2
-
-#define LPDDR4__DENALI_CTL_412_READ_MASK 0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_412_WRITE_MASK 0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH 7U
-#define LPDDR4__RDLAT_ADJ_F2__REG DENALI_CTL_412
-#define LPDDR4__RDLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2
-
-#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK 0x00007F00U
-#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH 7U
-#define LPDDR4__WRLAT_ADJ_F2__REG DENALI_CTL_412
-#define LPDDR4__WRLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2
-
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH 4U
-#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_412
-#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0
-
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH 4U
-#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_412
-#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1
-
-#define LPDDR4__DENALI_CTL_413_READ_MASK 0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_413_WRITE_MASK 0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH 4U
-#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_413
-#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2
-
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT 8U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH 4U
-#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413
-#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE
-
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH 4U
-#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413
-#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE
-
-#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH 8U
-#define LPDDR4__TDFI_WRLVL_EN__REG DENALI_CTL_413
-#define LPDDR4__TDFI_WRLVL_EN__FLD LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN
-
-#define LPDDR4__DENALI_CTL_414_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_414_WRITE_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT 0U
-#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH 10U
-#define LPDDR4__TDFI_WRLVL_WW__REG DENALI_CTL_414
-#define LPDDR4__TDFI_WRLVL_WW__FLD LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW
-
-#define LPDDR4__DENALI_CTL_415_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_415_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT 0U
-#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH 32U
-#define LPDDR4__TDFI_WRLVL_RESP__REG DENALI_CTL_415
-#define LPDDR4__TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP
-
-#define LPDDR4__DENALI_CTL_416_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_416_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT 0U
-#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH 32U
-#define LPDDR4__TDFI_WRLVL_MAX__REG DENALI_CTL_416
-#define LPDDR4__TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX
-
-#define LPDDR4__DENALI_CTL_417_READ_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_417_WRITE_MASK 0x0003FFFFU
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH 8U
-#define LPDDR4__TDFI_RDLVL_EN__REG DENALI_CTL_417
-#define LPDDR4__TDFI_RDLVL_EN__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN
-
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK 0x0003FF00U
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT 8U
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH 10U
-#define LPDDR4__TDFI_RDLVL_RR__REG DENALI_CTL_417
-#define LPDDR4__TDFI_RDLVL_RR__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR
-
-#define LPDDR4__DENALI_CTL_418_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_418_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT 0U
-#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH 32U
-#define LPDDR4__TDFI_RDLVL_RESP__REG DENALI_CTL_418
-#define LPDDR4__TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP
-
-#define LPDDR4__DENALI_CTL_419_READ_MASK 0x000101FFU
-#define LPDDR4__DENALI_CTL_419_WRITE_MASK 0x000101FFU
-#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT 0U
-#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH 8U
-#define LPDDR4__RDLVL_RESP_MASK__REG DENALI_CTL_419
-#define LPDDR4__RDLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK
-
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET 0U
-#define LPDDR4__RDLVL_EN__REG DENALI_CTL_419
-#define LPDDR4__RDLVL_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_EN
-
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET 0U
-#define LPDDR4__RDLVL_GATE_EN__REG DENALI_CTL_419
-#define LPDDR4__RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN
-
-#define LPDDR4__DENALI_CTL_420_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_420_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT 0U
-#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH 32U
-#define LPDDR4__TDFI_RDLVL_MAX__REG DENALI_CTL_420
-#define LPDDR4__TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX
-
-#define LPDDR4__DENALI_CTL_421_READ_MASK 0x00FF0707U
-#define LPDDR4__DENALI_CTL_421_WRITE_MASK 0x00FF0707U
-#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH 3U
-#define LPDDR4__RDLVL_ERROR_STATUS__REG DENALI_CTL_421
-#define LPDDR4__RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_MASK 0x00000700U
-#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH 3U
-#define LPDDR4__RDLVL_GATE_ERROR_STATUS__REG DENALI_CTL_421
-#define LPDDR4__RDLVL_GATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH 8U
-#define LPDDR4__TDFI_CALVL_EN__REG DENALI_CTL_421
-#define LPDDR4__TDFI_CALVL_EN__FLD LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN
-
-#define LPDDR4__DENALI_CTL_422_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_422_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH 10U
-#define LPDDR4__TDFI_CALVL_CC_F0__REG DENALI_CTL_422
-#define LPDDR4__TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0
-
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH 10U
-#define LPDDR4__TDFI_CALVL_CAPTURE_F0__REG DENALI_CTL_422
-#define LPDDR4__TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0
-
-#define LPDDR4__DENALI_CTL_423_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_423_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH 10U
-#define LPDDR4__TDFI_CALVL_CC_F1__REG DENALI_CTL_423
-#define LPDDR4__TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1
-
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT 16U
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH 10U
-#define LPDDR4__TDFI_CALVL_CAPTURE_F1__REG DENALI_CTL_423
-#define LPDDR4__TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1
-
-#define LPDDR4__DENALI_CTL_424_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_424_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK 0x000003FFU
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH 10U
-#define LPDDR4__TDFI_CALVL_CC_F2__REG DENALI_CTL_424
-#define LPDDR4__TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2
-
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH 10U
-#define LPDDR4__TDFI_CALVL_CAPTURE_F2__REG DENALI_CTL_424
-#define LPDDR4__TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2
-
-#define LPDDR4__DENALI_CTL_425_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_425_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT 0U
-#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH 32U
-#define LPDDR4__TDFI_CALVL_RESP__REG DENALI_CTL_425
-#define LPDDR4__TDFI_CALVL_RESP__FLD LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP
-
-#define LPDDR4__DENALI_CTL_426_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_426_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT 0U
-#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH 32U
-#define LPDDR4__TDFI_CALVL_MAX__REG DENALI_CTL_426
-#define LPDDR4__TDFI_CALVL_MAX__FLD LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX
-
-#define LPDDR4__DENALI_CTL_427_READ_MASK 0x070F0101U
-#define LPDDR4__DENALI_CTL_427_WRITE_MASK 0x070F0101U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT 0U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH 1U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR 0U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET 0U
-#define LPDDR4__CALVL_RESP_MASK__REG DENALI_CTL_427
-#define LPDDR4__CALVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK
-
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET 0U
-#define LPDDR4__CALVL_EN__REG DENALI_CTL_427
-#define LPDDR4__CALVL_EN__FLD LPDDR4__DENALI_CTL_427__CALVL_EN
-
-#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT 16U
-#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH 4U
-#define LPDDR4__CALVL_ERROR_STATUS__REG DENALI_CTL_427
-#define LPDDR4__CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH 3U
-#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_427
-#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0
-
-#define LPDDR4__DENALI_CTL_428_READ_MASK 0x7F7F0707U
-#define LPDDR4__DENALI_CTL_428_WRITE_MASK 0x7F7F0707U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH 3U
-#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_428
-#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1
-
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_MASK 0x00000700U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT 8U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH 3U
-#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_428
-#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2
-
-#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK 0x007F0000U
-#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH 7U
-#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_428
-#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0
-
-#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK 0x7F000000U
-#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT 24U
-#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH 7U
-#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_428
-#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0
-
-#define LPDDR4__DENALI_CTL_429_READ_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_429_WRITE_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK 0x0000007FU
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH 7U
-#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_429
-#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1
-
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK 0x00007F00U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT 8U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH 7U
-#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_429
-#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1
-
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK 0x007F0000U
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT 16U
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH 7U
-#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_429
-#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2
-
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK 0x7F000000U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT 24U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH 7U
-#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_429
-#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2
-
-#define LPDDR4__DENALI_CTL_430_READ_MASK 0x010101FFU
-#define LPDDR4__DENALI_CTL_430_WRITE_MASK 0x010101FFU
-#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT 0U
-#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH 8U
-#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_430
-#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY
-
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT 8U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH 1U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR 0U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET 0U
-#define LPDDR4__EN_1T_TIMING__REG DENALI_CTL_430
-#define LPDDR4__EN_1T_TIMING__FLD LPDDR4__DENALI_CTL_430__EN_1T_TIMING
-
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_SHIFT 16U
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE_WOSET 0U
-#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_430
-#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE
-
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT 24U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET 0U
-#define LPDDR4__BL_ON_FLY_ENABLE__REG DENALI_CTL_430
-#define LPDDR4__BL_ON_FLY_ENABLE__FLD LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE
-
-#define LPDDR4__DENALI_CTL_431_READ_MASK 0x07070701U
-#define LPDDR4__DENALI_CTL_431_WRITE_MASK 0x07070701U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT 0U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH 1U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR 0U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET 0U
-#define LPDDR4__MC_RESERVED32__REG DENALI_CTL_431
-#define LPDDR4__MC_RESERVED32__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED32
-
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK 0x00000700U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT 8U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH 3U
-#define LPDDR4__MC_RESERVED33__REG DENALI_CTL_431
-#define LPDDR4__MC_RESERVED33__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED33
-
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK 0x00070000U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT 16U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH 3U
-#define LPDDR4__MC_RESERVED34__REG DENALI_CTL_431
-#define LPDDR4__MC_RESERVED34__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED34
-
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK 0x07000000U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT 24U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH 3U
-#define LPDDR4__MC_RESERVED35__REG DENALI_CTL_431
-#define LPDDR4__MC_RESERVED35__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED35
-
-#define LPDDR4__DENALI_CTL_432_READ_MASK 0x0F070707U
-#define LPDDR4__DENALI_CTL_432_WRITE_MASK 0x0F070707U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT 0U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH 3U
-#define LPDDR4__MC_RESERVED36__REG DENALI_CTL_432
-#define LPDDR4__MC_RESERVED36__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED36
-
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK 0x00000700U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT 8U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH 3U
-#define LPDDR4__MC_RESERVED37__REG DENALI_CTL_432
-#define LPDDR4__MC_RESERVED37__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED37
-
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK 0x00070000U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT 16U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH 3U
-#define LPDDR4__MC_RESERVED38__REG DENALI_CTL_432
-#define LPDDR4__MC_RESERVED38__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED38
-
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT 24U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH 4U
-#define LPDDR4__MC_RESERVED39__REG DENALI_CTL_432
-#define LPDDR4__MC_RESERVED39__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED39
-
-#define LPDDR4__DENALI_CTL_433_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_433_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT 0U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH 4U
-#define LPDDR4__MC_RESERVED40__REG DENALI_CTL_433
-#define LPDDR4__MC_RESERVED40__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED40
-
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT 8U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH 4U
-#define LPDDR4__MC_RESERVED41__REG DENALI_CTL_433
-#define LPDDR4__MC_RESERVED41__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED41
-
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT 16U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH 4U
-#define LPDDR4__MC_RESERVED42__REG DENALI_CTL_433
-#define LPDDR4__MC_RESERVED42__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED42
-
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT 24U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH 4U
-#define LPDDR4__MC_RESERVED43__REG DENALI_CTL_433
-#define LPDDR4__MC_RESERVED43__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED43
-
-#define LPDDR4__DENALI_CTL_434_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_434_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT 0U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH 4U
-#define LPDDR4__MC_RESERVED44__REG DENALI_CTL_434
-#define LPDDR4__MC_RESERVED44__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED44
-
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT 8U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH 4U
-#define LPDDR4__MC_RESERVED45__REG DENALI_CTL_434
-#define LPDDR4__MC_RESERVED45__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED45
-
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT 16U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH 4U
-#define LPDDR4__MC_RESERVED46__REG DENALI_CTL_434
-#define LPDDR4__MC_RESERVED46__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED46
-
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT 24U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH 4U
-#define LPDDR4__MC_RESERVED47__REG DENALI_CTL_434
-#define LPDDR4__MC_RESERVED47__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED47
-
-#define LPDDR4__DENALI_CTL_435_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_435_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT 0U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH 4U
-#define LPDDR4__MC_RESERVED48__REG DENALI_CTL_435
-#define LPDDR4__MC_RESERVED48__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED48
-
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT 8U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH 4U
-#define LPDDR4__MC_RESERVED49__REG DENALI_CTL_435
-#define LPDDR4__MC_RESERVED49__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED49
-
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT 16U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH 4U
-#define LPDDR4__MC_RESERVED50__REG DENALI_CTL_435
-#define LPDDR4__MC_RESERVED50__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED50
-
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT 24U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH 4U
-#define LPDDR4__MC_RESERVED51__REG DENALI_CTL_435
-#define LPDDR4__MC_RESERVED51__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED51
-
-#define LPDDR4__DENALI_CTL_436_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_436_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT 0U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH 4U
-#define LPDDR4__MC_RESERVED52__REG DENALI_CTL_436
-#define LPDDR4__MC_RESERVED52__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED52
-
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT 8U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH 4U
-#define LPDDR4__MC_RESERVED53__REG DENALI_CTL_436
-#define LPDDR4__MC_RESERVED53__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED53
-
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT 16U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH 4U
-#define LPDDR4__MC_RESERVED54__REG DENALI_CTL_436
-#define LPDDR4__MC_RESERVED54__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED54
-
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK 0x0F000000U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT 24U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH 4U
-#define LPDDR4__MC_RESERVED55__REG DENALI_CTL_436
-#define LPDDR4__MC_RESERVED55__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED55
-
-#define LPDDR4__DENALI_CTL_437_READ_MASK 0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_437_WRITE_MASK 0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT 0U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH 4U
-#define LPDDR4__MC_RESERVED56__REG DENALI_CTL_437
-#define LPDDR4__MC_RESERVED56__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED56
-
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK 0x00000F00U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT 8U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH 4U
-#define LPDDR4__MC_RESERVED57__REG DENALI_CTL_437
-#define LPDDR4__MC_RESERVED57__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED57
-
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK 0x000F0000U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT 16U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH 4U
-#define LPDDR4__MC_RESERVED58__REG DENALI_CTL_437
-#define LPDDR4__MC_RESERVED58__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED58
-
-#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT 24U
-#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH 8U
-#define LPDDR4__GLOBAL_ERROR_INFO__REG DENALI_CTL_437
-#define LPDDR4__GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO
-
-#define LPDDR4__DENALI_CTL_438_READ_MASK 0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_438_WRITE_MASK 0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT 0U
-#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH 8U
-#define LPDDR4__GLOBAL_ERROR_MASK__REG DENALI_CTL_438
-#define LPDDR4__GLOBAL_ERROR_MASK__FLD LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK
-
-#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_MASK 0x00000300U
-#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT 8U
-#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH 2U
-#define LPDDR4__AXI_PARITY_ERROR_STATUS__REG DENALI_CTL_438
-#define LPDDR4__AXI_PARITY_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS
-
-#define LPDDR4__DENALI_CTL_438__NWR_F0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT 16U
-#define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH 8U
-#define LPDDR4__NWR_F0__REG DENALI_CTL_438
-#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_438__NWR_F0
-
-#define LPDDR4__DENALI_CTL_438__NWR_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT 24U
-#define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH 8U
-#define LPDDR4__NWR_F1__REG DENALI_CTL_438
-#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_438__NWR_F1
-
-#define LPDDR4__DENALI_CTL_439_READ_MASK 0x001F01FFU
-#define LPDDR4__DENALI_CTL_439_WRITE_MASK 0x001F01FFU
-#define LPDDR4__DENALI_CTL_439__NWR_F2_MASK 0x000000FFU
-#define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH 8U
-#define LPDDR4__NWR_F2__REG DENALI_CTL_439
-#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_439__NWR_F2
-
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT 8U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH 1U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR 0U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET 0U
-#define LPDDR4__MC_RESERVED59__REG DENALI_CTL_439
-#define LPDDR4__MC_RESERVED59__FLD LPDDR4__DENALI_CTL_439__MC_RESERVED59
-
-#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_MASK 0x001F0000U
-#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_SHIFT 16U
-#define LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS_WIDTH 5U
-#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__REG DENALI_CTL_439
-#define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS
-
-#define LPDDR4__DENALI_CTL_440_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_440_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_WIDTH 32U
-#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__REG DENALI_CTL_440
-#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__FLD LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0
-
-#define LPDDR4__DENALI_CTL_441_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_441_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_WIDTH 32U
-#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__REG DENALI_CTL_441
-#define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__FLD LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1
-
-#define LPDDR4__DENALI_CTL_442_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_442_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT 0U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH 1U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR 0U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET 0U
-#define LPDDR4__MC_PARITY_ERROR_TYPE__REG DENALI_CTL_442
-#define LPDDR4__MC_PARITY_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE
-
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__REG DENALI_CTL_442
-#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_ADDR_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__REG DENALI_CTL_442
-#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITEMASK_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__REG DENALI_CTL_442
-#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_443_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_443_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__REG DENALI_CTL_443
-#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN_WOSET 0U
-#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__REG DENALI_CTL_443
-#define LPDDR4__PARAMREG_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_443__PARAMREG_PARITY_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
-#define LPDDR4__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_ADDR_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_SHIFT 24U
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
-#define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_444_READ_MASK 0x00010101U
-#define LPDDR4__DENALI_CTL_444_WRITE_MASK 0x00010101U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_SHIFT 0U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
-#define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
-#define LPDDR4__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__REGPORT_READ_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_SHIFT 16U
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN_WOSET 0U
-#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
-#define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN
-
-#define LPDDR4__DENALI_CTL_445_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_445_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH 32U
-#define LPDDR4__MC_RESERVED60_0__REG DENALI_CTL_445
-#define LPDDR4__MC_RESERVED60_0__FLD LPDDR4__DENALI_CTL_445__MC_RESERVED60_0
-
-#define LPDDR4__DENALI_CTL_446_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_446_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH 32U
-#define LPDDR4__MC_RESERVED60_1__REG DENALI_CTL_446
-#define LPDDR4__MC_RESERVED60_1__FLD LPDDR4__DENALI_CTL_446__MC_RESERVED60_1
-
-#define LPDDR4__DENALI_CTL_447_READ_MASK 0x00000107U
-#define LPDDR4__DENALI_CTL_447_WRITE_MASK 0x00000107U
-#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH 3U
-#define LPDDR4__MC_RESERVED60_2__REG DENALI_CTL_447
-#define LPDDR4__MC_RESERVED60_2__FLD LPDDR4__DENALI_CTL_447__MC_RESERVED60_2
-
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_SHIFT 8U
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WIDTH 1U
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOCLR 0U
-#define LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN_WOSET 0U
-#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__REG DENALI_CTL_447
-#define LPDDR4__PORT_TO_CORE_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN
-
-#define LPDDR4__DENALI_CTL_448_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_448_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_WIDTH 32U
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__REG DENALI_CTL_448
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__FLD LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0
-
-#define LPDDR4__DENALI_CTL_449_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_449_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_WIDTH 32U
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__REG DENALI_CTL_449
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__FLD LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1
-
-#define LPDDR4__DENALI_CTL_450_READ_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_450_WRITE_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_MASK 0x00000007U
-#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_WIDTH 3U
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__REG DENALI_CTL_450
-#define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__FLD LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2
-
-#define LPDDR4__DENALI_CTL_451_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_451_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH 32U
-#define LPDDR4__MC_RESERVED61_0__REG DENALI_CTL_451
-#define LPDDR4__MC_RESERVED61_0__FLD LPDDR4__DENALI_CTL_451__MC_RESERVED61_0
-
-#define LPDDR4__DENALI_CTL_452_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_452_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH 32U
-#define LPDDR4__MC_RESERVED61_1__REG DENALI_CTL_452
-#define LPDDR4__MC_RESERVED61_1__FLD LPDDR4__DENALI_CTL_452__MC_RESERVED61_1
-
-#define LPDDR4__DENALI_CTL_453_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_453_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH 32U
-#define LPDDR4__MC_RESERVED61_2__REG DENALI_CTL_453
-#define LPDDR4__MC_RESERVED61_2__FLD LPDDR4__DENALI_CTL_453__MC_RESERVED61_2
-
-#define LPDDR4__DENALI_CTL_454_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_454_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT 0U
-#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH 4U
-#define LPDDR4__MC_RESERVED61_3__REG DENALI_CTL_454
-#define LPDDR4__MC_RESERVED61_3__FLD LPDDR4__DENALI_CTL_454__MC_RESERVED61_3
-
-#define LPDDR4__DENALI_CTL_455_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_455_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_SHIFT 0U
-#define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_WIDTH 32U
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__REG DENALI_CTL_455
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__FLD LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0
-
-#define LPDDR4__DENALI_CTL_456_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_456_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_SHIFT 0U
-#define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_WIDTH 32U
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__REG DENALI_CTL_456
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__FLD LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1
-
-#define LPDDR4__DENALI_CTL_457_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_457_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_SHIFT 0U
-#define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_WIDTH 32U
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__REG DENALI_CTL_457
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__FLD LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2
-
-#define LPDDR4__DENALI_CTL_458_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_458_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_MASK 0x0000000FU
-#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_SHIFT 0U
-#define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_WIDTH 4U
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__REG DENALI_CTL_458
-#define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_3__FLD LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3
-
-#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_if.h b/drivers/ram/k3-j721e/lpddr4_if.h
deleted file mode 100644
index 66ec3c5..0000000
--- a/drivers/ram/k3-j721e/lpddr4_if.h
+++ /dev/null
@@ -1,578 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- * api-generator: 12.02.13bb8d5
- * Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-
-#ifndef LPDDR4_IF_H
-#define LPDDR4_IF_H
-
-#include <linux/types.h>
-
-/** @defgroup ConfigInfo Configuration and Hardware Operation Information
- * The following definitions specify the driver operation environment that
- * is defined by hardware configuration or client code. These defines are
- * located in the header file of the core driver.
- * @{
- */
-
-/**********************************************************************
-* Defines
-**********************************************************************/
-/** Number of chip-selects */
-#define LPDDR4_MAX_CS (2U)
-
-/** Number of accessible registers for controller. */
-#define LPDDR4_CTL_REG_COUNT (459U)
-
-/** Number of accessible registers for PHY Independent Module. */
-#define LPDDR4_PHY_INDEP_REG_COUNT (300U)
-
-/** Number of accessible registers for PHY. */
-#define LPDDR4_PHY_REG_COUNT (1423U)
-
-/**
- * @}
- */
-
-/** @defgroup DataStructure Dynamic Data Structures
- * This section defines the data structures used by the driver to provide
- * hardware information, modification and dynamic operation of the driver.
- * These data structures are defined in the header file of the core driver
- * and utilized by the API.
- * @{
- */
-
-/**********************************************************************
-* Forward declarations
-**********************************************************************/
-typedef struct lpddr4_config_s lpddr4_config;
-typedef struct lpddr4_privatedata_s lpddr4_privatedata;
-typedef struct lpddr4_debuginfo_s lpddr4_debuginfo;
-typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs;
-typedef struct lpddr4_reginitdata_s lpddr4_reginitdata;
-
-/**********************************************************************
-* Enumerations
-**********************************************************************/
-/** This is used to indicate whether the Controller, PHY, or PHY Independent module is addressed. */
-typedef enum
-{
- LPDDR4_CTL_REGS = 0U,
- LPDDR4_PHY_REGS = 1U,
- LPDDR4_PHY_INDEP_REGS = 2U
-} lpddr4_regblock;
-
-/** Controller status or error interrupts. */
-typedef enum
-{
- LPDDR4_RESET_DONE = 0U,
- LPDDR4_BUS_ACCESS_ERROR = 1U,
- LPDDR4_MULTIPLE_BUS_ACCESS_ERROR = 2U,
- LPDDR4_ECC_MULTIPLE_CORR_ERROR = 3U,
- LPDDR4_ECC_MULTIPLE_UNCORR_ERROR = 4U,
- LPDDR4_ECC_WRITEBACK_EXEC_ERROR = 5U,
- LPDDR4_ECC_SCRUB_DONE = 6U,
- LPDDR4_ECC_SCRUB_ERROR = 7U,
- LPDDR4_PORT_COMMAND_ERROR = 8U,
- LPDDR4_MC_INIT_DONE = 9U,
- LPDDR4_LP_DONE = 10U,
- LPDDR4_BIST_DONE = 11U,
- LPDDR4_WRAP_ERROR = 12U,
- LPDDR4_INVALID_BURST_ERROR = 13U,
- LPDDR4_RDLVL_ERROR = 14U,
- LPDDR4_RDLVL_GATE_ERROR = 15U,
- LPDDR4_WRLVL_ERROR = 16U,
- LPDDR4_CA_TRAINING_ERROR = 17U,
- LPDDR4_DFI_UPDATE_ERROR = 18U,
- LPDDR4_MRR_ERROR = 19U,
- LPDDR4_PHY_MASTER_ERROR = 20U,
- LPDDR4_WRLVL_REQ = 21U,
- LPDDR4_RDLVL_REQ = 22U,
- LPDDR4_RDLVL_GATE_REQ = 23U,
- LPDDR4_CA_TRAINING_REQ = 24U,
- LPDDR4_LEVELING_DONE = 25U,
- LPDDR4_PHY_ERROR = 26U,
- LPDDR4_MR_READ_DONE = 27U,
- LPDDR4_TEMP_CHANGE = 28U,
- LPDDR4_TEMP_ALERT = 29U,
- LPDDR4_SW_DQS_COMPLETE = 30U,
- LPDDR4_DQS_OSC_BV_UPDATED = 31U,
- LPDDR4_DQS_OSC_OVERFLOW = 32U,
- LPDDR4_DQS_OSC_VAR_OUT = 33U,
- LPDDR4_MR_WRITE_DONE = 34U,
- LPDDR4_INHIBIT_DRAM_DONE = 35U,
- LPDDR4_DFI_INIT_STATE = 36U,
- LPDDR4_DLL_RESYNC_DONE = 37U,
- LPDDR4_TDFI_TO = 38U,
- LPDDR4_DFS_DONE = 39U,
- LPDDR4_DFS_STATUS = 40U,
- LPDDR4_REFRESH_STATUS = 41U,
- LPDDR4_ZQ_STATUS = 42U,
- LPDDR4_SW_REQ_MODE = 43U,
- LPDDR4_LOR_BITS = 44U
-} lpddr4_ctlinterrupt;
-
-/** PHY Independent Module status or error interrupts. */
-typedef enum
-{
- LPDDR4_PHY_INDEP_INIT_DONE_BIT = 0U,
- LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
- LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
- LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
- LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT = 4U,
- LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
- LPDDR4_PHY_INDEP_CALVL_ERROR_BIT = 6U,
- LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
- LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
- LPDDR4_PHY_INDEP_RDLVL_REQ_BIT = 9U,
- LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
- LPDDR4_PHY_INDEP_WRLVL_REQ_BIT = 11U,
- LPDDR4_PHY_INDEP_CALVL_REQ_BIT = 12U,
- LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
- LPDDR4_PHY_INDEP_LVL_DONE_BIT = 14U,
- LPDDR4_PHY_INDEP_BIST_DONE_BIT = 15U,
- LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
- LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
-} lpddr4_phyindepinterrupt;
-
-/** List of informations and warnings from driver. */
-typedef enum
-{
- LPDDR4_DRV_NONE = 0U,
- LPDDR4_DRV_SOC_PLL_UPDATE = 1U
-} lpddr4_infotype;
-
-/** Low power interface wake up timing parameters */
-typedef enum
-{
- LPDDR4_LPI_PD_WAKEUP_FN = 0U,
- LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U,
- LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U,
- LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U,
- LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U,
- LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U,
- LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U
-} lpddr4_lpiwakeupparam;
-
-/** Half Datapath mode setting */
-typedef enum
-{
- LPDDR4_REDUC_ON = 0U,
- LPDDR4_REDUC_OFF = 1U
-} lpddr4_reducmode;
-
-/** ECC Control parameter setting */
-typedef enum
-{
- LPDDR4_ECC_DISABLED = 0U,
- LPDDR4_ECC_ENABLED = 1U,
- LPDDR4_ECC_ERR_DETECT = 2U,
- LPDDR4_ECC_ERR_DETECT_CORRECT = 3U
-} lpddr4_eccenable;
-
-/** Data Byte Inversion mode setting */
-typedef enum
-{
- LPDDR4_DBI_RD_ON = 0U,
- LPDDR4_DBI_RD_OFF = 1U,
- LPDDR4_DBI_WR_ON = 2U,
- LPDDR4_DBI_WR_OFF = 3U
-} lpddr4_dbimode;
-
-/** Controller Frequency Set Point number */
-typedef enum
-{
- LPDDR4_FSP_0 = 0U,
- LPDDR4_FSP_1 = 1U,
- LPDDR4_FSP_2 = 2U
-} lpddr4_ctlfspnum;
-
-/**********************************************************************
-* Callbacks
-**********************************************************************/
-/**
- * Reports informations and warnings that need to be communicated.
- * Params:
- * pD - driver state info specific to this instance.
- * infoType - Type of information.
- */
-typedef void (*lpddr4_infocallback)(const lpddr4_privatedata* pd, lpddr4_infotype infotype);
-
-/**
- * Reports interrupts received by the controller.
- * Params:
- * pD - driver state info specific to this instance.
- * ctlInterrupt - Interrupt raised
- * chipSelect - Chip for which interrupt raised
- */
-typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt ctlinterrupt, uint8_t chipselect);
-
-/**
- * Reports interrupts received by the PHY Independent Module.
- * Params:
- * privateData - driver state info specific to this instance.
- * phyIndepInterrupt - Interrupt raised
- * chipSelect - Chip for which interrupt raised
- */
-typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt phyindepinterrupt, uint8_t chipselect);
-
-/**
- * @}
- */
-
-/** @defgroup DriverFunctionAPI Driver Function API
- * Prototypes for the driver API functions. The user application can link statically to the
- * necessary API functions and call them directly.
- * @{
- */
-
-/**********************************************************************
-* API methods
-**********************************************************************/
-
-/**
- * Checks configuration object.
- * @param[in] config Driver/hardware configuration required.
- * @param[out] configSize Size of memory allocations required.
- * @return CDN_EOK on success (requirements structure filled).
- * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
- */
-uint32_t lpddr4_probe(const lpddr4_config* config, uint16_t* configsize);
-
-/**
- * Init function to be called after LPDDR4_probe() to set up the
- * driver configuration. Memory should be allocated for drv_data
- * (using the size determined using LPDDR4_probe) before calling this
- * API. init_settings should be initialised with base addresses for
- * PHY Indepenent Module, Controller and PHY before calling this
- * function. If callbacks are required for interrupt handling, these
- * should also be configured in init_settings.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cfg Specifies driver/hardware configuration.
- * @return CDN_EOK on success
- * @return EINVAL if illegal/inconsistent values in cfg.
- * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
- */
-uint32_t lpddr4_init(lpddr4_privatedata* pd, const lpddr4_config* cfg);
-
-/**
- * Start the driver.
- * @param[in] pD Driver state info specific to this instance.
- */
-uint32_t lpddr4_start(const lpddr4_privatedata* pd);
-
-/**
- * Read a register from the controller, PHY or PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[in] regOffset Register offset
- * @param[out] regValue Register value read
- * @return CDN_EOK on success.
- * @return EINVAL if regOffset if out of range or regValue is NULL
- */
-uint32_t lpddr4_readreg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
-
-/**
- * Write a register in the controller, PHY or PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[in] regOffset Register offset
- * @param[in] regValue Register value to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regOffset is out of range or regValue is NULL
- */
-uint32_t lpddr4_writereg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
-
-/**
- * Read a memory mode register from DRAM
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
- * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
- * @param[out] mmrStatus Status of mode register read(mrr) instruction.
- * @return CDN_EOK on success.
- * @return EINVAL if regNumber is out of range or regValue is NULL
- */
-uint32_t lpddr4_getmmrregister(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
-
-/**
- * Write a memory mode register in DRAM
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
- * @param[out] mrwStatus Status of mode register write(mrw) instruction.
- * @return CDN_EOK on success.
- * @return EINVAL if regNumber is out of range or regValue is NULL
- */
-uint32_t lpddr4_setmmrregister(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
-
-/**
- * Write a set of initialisation values to the controller registers
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_writectlconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
-/**
- * Write a set of initialisation values to the PHY registers
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_writephyconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
-/**
- * Write a set of initialisation values to the PHY Independent Module
- * registers
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
-/**
- * Read values of the controller registers in bulk (Set 'updateCtlReg'
- * to read) and store in memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_readctlconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
-/**
- * Read the values of the PHY module registers in bulk (Set
- * 'updatePhyReg' to read) and store in memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_readphyconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
-/**
- * Read the values of the PHY Independent module registers in bulk(Set
- * 'updatePhyIndepReg' to read) and store in memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
-uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
-/**
- * Read the current interrupt mask for the controller
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
-uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata* pd, uint64_t* mask);
-
-/**
- * Sets the interrupt mask for the controller
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mask Value of interrupt mask to be written
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
-uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata* pd, const uint64_t* mask);
-
-/**
- * Check whether a specific controller interrupt is active
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
-uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
-
-/**
- * Acknowledge a specific controller interrupt
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
-uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
-
-/**
- * Read the current interrupt mask for the PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
-uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata* pd, uint32_t* mask);
-
-/**
- * Sets the interrupt mask for the PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mask Value of interrupt mask to be written
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
-uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata* pd, const uint32_t* mask);
-
-/**
- * Check whether a specific PHY Independent Module interrupt is active
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
-uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
-
-/**
- * Acknowledge a specific PHY Independent Module interrupt
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
-uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
-
-/**
- * Retrieve status information after a failed init. The
- * DebugStructInfo will be filled in with error codes which can be
- * referenced against the driver documentation for further details.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] debugInfo status
- * @return CDN_EOK on success.
- * @return EINVAL if debugInfo is NULL
- */
-uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
-
-/**
- * Get the current value of Low power Interface wake up time.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] lpiWakeUpParam LPI timing parameter
- * @param[in] fspNum Frequency copy
- * @param[out] cycles Timing value(in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if powerMode is NULL
- */
-uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
-
-/**
- * Set the current value of Low power Interface wake up time.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] lpiWakeUpParam LPI timing parameter
- * @param[in] fspNum Frequency copy
- * @param[in] cycles Timing value(in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if powerMode is NULL
- */
-uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
-/**
- * Get the current value for ECC auto correction
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] eccParam ECC parameter setting
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
-uint32_t lpddr4_geteccenable(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
-
-/**
- * Set the value for ECC auto correction. This API must be called
- * before startup of memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] eccParam ECC control parameter setting
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
-uint32_t lpddr4_seteccenable(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
-
-/**
- * Get the current value for the Half Datapath option
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mode Half Datapath setting
- * @return CDN_EOK on success.
- * @return EINVAL if mode is NULL
- */
-uint32_t lpddr4_getreducmode(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
-
-/**
- * Set the value for the Half Datapath option. This API must be
- * called before startup of memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode Half Datapath setting
- * @return CDN_EOK on success.
- * @return EINVAL if mode is NULL
- */
-uint32_t lpddr4_setreducmode(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
-
-/**
- * Get the current value for Data Bus Inversion setting. This will be
- * compared with the current DRAM setting using the MR3 register.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] on_off DBI read value
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
-uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata* pd, bool* on_off);
-
-/**
- * Get the current value for Data Bus Inversion setting. This will be
- * compared with the current DRAM setting using the MR3 register.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] on_off DBI write value
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
-uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata* pd, bool* on_off);
-
-/**
- * Set the mode for Data Bus Inversion. This will also be set in DRAM
- * using the MR3 controller register. This API must be called before
- * startup of memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode status
- * @return CDN_EOK on success.
- * @return EINVAL if mode is NULL
- */
-uint32_t lpddr4_setdbimode(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
-
-/**
- * Get the current value for the refresh rate (reading Refresh per
- * command timing).
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] fspNum Frequency set number
- * @param[out] cycles Refresh rate (in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if rate is NULL
- */
-uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
-
-/**
- * Set the refresh rate (writing Refresh per command timing).
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] fspNum Frequency set number
- * @param[in] cycles Refresh rate (in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if rate is NULL
- */
-uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
-/**
- * Handle Refreshing per chip select
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] trefInterval status
- * @return CDN_EOK on success.
- * @return EINVAL if chipSelect is invalid
- */
-uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata* pd, const uint32_t trefinterval);
-
-#endif /* LPDDR4_IF_H */
diff --git a/drivers/ram/k3-j721e/lpddr4_obj_if.c b/drivers/ram/k3-j721e/lpddr4_obj_if.c
deleted file mode 100644
index 35b3db6..0000000
--- a/drivers/ram/k3-j721e/lpddr4_obj_if.c
+++ /dev/null
@@ -1,55 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- * api-generator: 12.02.13bb8d5
- * Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-
-#include "lpddr4_obj_if.h"
-
-LPDDR4_OBJ *lpddr4_getinstance(void)
-{
- static LPDDR4_OBJ driver = {
- .probe = lpddr4_probe,
- .init = lpddr4_init,
- .start = lpddr4_start,
- .readreg = lpddr4_readreg,
- .writereg = lpddr4_writereg,
- .getmmrregister = lpddr4_getmmrregister,
- .setmmrregister = lpddr4_setmmrregister,
- .writectlconfig = lpddr4_writectlconfig,
- .writephyconfig = lpddr4_writephyconfig,
- .writephyindepconfig = lpddr4_writephyindepconfig,
- .readctlconfig = lpddr4_readctlconfig,
- .readphyconfig = lpddr4_readphyconfig,
- .readphyindepconfig = lpddr4_readphyindepconfig,
- .getctlinterruptmask = lpddr4_getctlinterruptmask,
- .setctlinterruptmask = lpddr4_setctlinterruptmask,
- .checkctlinterrupt = lpddr4_checkctlinterrupt,
- .ackctlinterrupt = lpddr4_ackctlinterrupt,
- .getphyindepinterruptmask = lpddr4_getphyindepinterruptmask,
- .setphyindepinterruptmask = lpddr4_setphyindepinterruptmask,
- .checkphyindepinterrupt = lpddr4_checkphyindepinterrupt,
- .ackphyindepinterrupt = lpddr4_ackphyindepinterrupt,
- .getdebuginitinfo = lpddr4_getdebuginitinfo,
- .getlpiwakeuptime = lpddr4_getlpiwakeuptime,
- .setlpiwakeuptime = lpddr4_setlpiwakeuptime,
- .geteccenable = lpddr4_geteccenable,
- .seteccenable = lpddr4_seteccenable,
- .getreducmode = lpddr4_getreducmode,
- .setreducmode = lpddr4_setreducmode,
- .getdbireadmode = lpddr4_getdbireadmode,
- .getdbiwritemode = lpddr4_getdbiwritemode,
- .setdbimode = lpddr4_setdbimode,
- .getrefreshrate = lpddr4_getrefreshrate,
- .setrefreshrate = lpddr4_setrefreshrate,
- .refreshperchipselect = lpddr4_refreshperchipselect,
- };
-
- return &driver;
-}
diff --git a/drivers/ram/k3-j721e/lpddr4_obj_if.h b/drivers/ram/k3-j721e/lpddr4_obj_if.h
deleted file mode 100644
index 33dae6f..0000000
--- a/drivers/ram/k3-j721e/lpddr4_obj_if.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- * api-generator: 12.02.13bb8d5
- * Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-#ifndef LPDDR4_OBJ_IF_H
-#define LPDDR4_OBJ_IF_H
-
-#include "lpddr4_if.h"
-
-/** @defgroup DriverObject Driver API Object
- * API listing for the driver. The API is contained in the object as
- * function pointers in the object structure. As the actual functions
- * resides in the Driver Object, the client software must first use the
- * global GetInstance function to obtain the Driver Object Pointer.
- * The actual APIs then can be invoked using obj->(api_name)() syntax.
- * These functions are defined in the header file of the core driver
- * and utilized by the API.
- * @{
- */
-
-/**********************************************************************
-* API methods
-**********************************************************************/
-typedef struct lpddr4_obj_s
-{
- /**
- * Checks configuration object.
- * @param[in] config Driver/hardware configuration required.
- * @param[out] configSize Size of memory allocations required.
- * @return CDN_EOK on success (requirements structure filled).
- * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
- */
- uint32_t (*probe)(const lpddr4_config* config, uint16_t* configsize);
-
- /**
- * Init function to be called after LPDDR4_probe() to set up the
- * driver configuration. Memory should be allocated for drv_data
- * (using the size determined using LPDDR4_probe) before calling
- * this API. init_settings should be initialised with base addresses
- * for PHY Indepenent Module, Controller and PHY before calling this
- * function. If callbacks are required for interrupt handling, these
- * should also be configured in init_settings.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cfg Specifies driver/hardware configuration.
- * @return CDN_EOK on success
- * @return EINVAL if illegal/inconsistent values in cfg.
- * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
- */
- uint32_t (*init)(lpddr4_privatedata* pd, const lpddr4_config* cfg);
-
- /**
- * Start the driver.
- * @param[in] pD Driver state info specific to this instance.
- */
- uint32_t (*start)(const lpddr4_privatedata* pd);
-
- /**
- * Read a register from the controller, PHY or PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[in] regOffset Register offset
- * @param[out] regValue Register value read
- * @return CDN_EOK on success.
- * @return EINVAL if regOffset if out of range or regValue is NULL
- */
- uint32_t (*readreg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
-
- /**
- * Write a register in the controller, PHY or PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[in] regOffset Register offset
- * @param[in] regValue Register value to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regOffset is out of range or regValue is NULL
- */
- uint32_t (*writereg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
-
- /**
- * Read a memory mode register from DRAM
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
- * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
- * @param[out] mmrStatus Status of mode register read(mrr) instruction.
- * @return CDN_EOK on success.
- * @return EINVAL if regNumber is out of range or regValue is NULL
- */
- uint32_t (*getmmrregister)(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
-
- /**
- * Write a memory mode register in DRAM
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
- * @param[out] mrwStatus Status of mode register write(mrw) instruction.
- * @return CDN_EOK on success.
- * @return EINVAL if regNumber is out of range or regValue is NULL
- */
- uint32_t (*setmmrregister)(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
-
- /**
- * Write a set of initialisation values to the controller registers
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
- uint32_t (*writectlconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
- /**
- * Write a set of initialisation values to the PHY registers
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
- uint32_t (*writephyconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
- /**
- * Write a set of initialisation values to the PHY Independent Module
- * registers
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
- uint32_t (*writephyindepconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-
- /**
- * Read values of the controller registers in bulk (Set
- * 'updateCtlReg' to read) and store in memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
- uint32_t (*readctlconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
- /**
- * Read the values of the PHY module registers in bulk (Set
- * 'updatePhyReg' to read) and store in memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
- uint32_t (*readphyconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
- /**
- * Read the values of the PHY Independent module registers in
- * bulk(Set 'updatePhyIndepReg' to read) and store in memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return CDN_EOK on success.
- * @return EINVAL if regValues is NULL
- */
- uint32_t (*readphyindepconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
-
- /**
- * Read the current interrupt mask for the controller
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
- uint32_t (*getctlinterruptmask)(const lpddr4_privatedata* pd, uint64_t* mask);
-
- /**
- * Sets the interrupt mask for the controller
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mask Value of interrupt mask to be written
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
- uint32_t (*setctlinterruptmask)(const lpddr4_privatedata* pd, const uint64_t* mask);
-
- /**
- * Check whether a specific controller interrupt is active
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
- uint32_t (*checkctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
-
- /**
- * Acknowledge a specific controller interrupt
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
- uint32_t (*ackctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
-
- /**
- * Read the current interrupt mask for the PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
- uint32_t (*getphyindepinterruptmask)(const lpddr4_privatedata* pd, uint32_t* mask);
-
- /**
- * Sets the interrupt mask for the PHY Independent Module
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mask Value of interrupt mask to be written
- * @return CDN_EOK on success.
- * @return EINVAL if mask pointer is NULL
- */
- uint32_t (*setphyindepinterruptmask)(const lpddr4_privatedata* pd, const uint32_t* mask);
-
- /**
- * Check whether a specific PHY Independent Module interrupt is
- * active
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
- uint32_t (*checkphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
-
- /**
- * Acknowledge a specific PHY Independent Module interrupt
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return CDN_EOK on success.
- * @return EINVAL if intr is not valid
- */
- uint32_t (*ackphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
-
- /**
- * Retrieve status information after a failed init. The
- * DebugStructInfo will be filled in with error codes which can be
- * referenced against the driver documentation for further details.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] debugInfo status
- * @return CDN_EOK on success.
- * @return EINVAL if debugInfo is NULL
- */
- uint32_t (*getdebuginitinfo)(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
-
- /**
- * Get the current value of Low power Interface wake up time.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] lpiWakeUpParam LPI timing parameter
- * @param[in] fspNum Frequency copy
- * @param[out] cycles Timing value(in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if powerMode is NULL
- */
- uint32_t (*getlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
-
- /**
- * Set the current value of Low power Interface wake up time.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] lpiWakeUpParam LPI timing parameter
- * @param[in] fspNum Frequency copy
- * @param[in] cycles Timing value(in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if powerMode is NULL
- */
- uint32_t (*setlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
- /**
- * Get the current value for ECC auto correction
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] eccParam ECC parameter setting
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
- uint32_t (*geteccenable)(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
-
- /**
- * Set the value for ECC auto correction. This API must be called
- * before startup of memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] eccParam ECC control parameter setting
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
- uint32_t (*seteccenable)(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
-
- /**
- * Get the current value for the Half Datapath option
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mode Half Datapath setting
- * @return CDN_EOK on success.
- * @return EINVAL if mode is NULL
- */
- uint32_t (*getreducmode)(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
-
- /**
- * Set the value for the Half Datapath option. This API must be
- * called before startup of memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode Half Datapath setting
- * @return CDN_EOK on success.
- * @return EINVAL if mode is NULL
- */
- uint32_t (*setreducmode)(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
-
- /**
- * Get the current value for Data Bus Inversion setting. This will
- * be compared with the current DRAM setting using the MR3
- * register.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] on_off DBI read value
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
- uint32_t (*getdbireadmode)(const lpddr4_privatedata* pd, bool* on_off);
-
- /**
- * Get the current value for Data Bus Inversion setting. This will
- * be compared with the current DRAM setting using the MR3
- * register.
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] on_off DBI write value
- * @return CDN_EOK on success.
- * @return EINVAL if on_off is NULL
- */
- uint32_t (*getdbiwritemode)(const lpddr4_privatedata* pd, bool* on_off);
-
- /**
- * Set the mode for Data Bus Inversion. This will also be set in DRAM
- * using the MR3 controller register. This API must be called
- * before startup of memory.
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode status
- * @return CDN_EOK on success.
- * @return EINVAL if mode is NULL
- */
- uint32_t (*setdbimode)(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
-
- /**
- * Get the current value for the refresh rate (reading Refresh per
- * command timing).
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] fspNum Frequency set number
- * @param[out] cycles Refresh rate (in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if rate is NULL
- */
- uint32_t (*getrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
-
- /**
- * Set the refresh rate (writing Refresh per command timing).
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] fspNum Frequency set number
- * @param[in] cycles Refresh rate (in cycles)
- * @return CDN_EOK on success.
- * @return EINVAL if rate is NULL
- */
- uint32_t (*setrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
- /**
- * Handle Refreshing per chip select
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] trefInterval status
- * @return CDN_EOK on success.
- * @return EINVAL if chipSelect is invalid
- */
- uint32_t (*refreshperchipselect)(const lpddr4_privatedata* pd, const uint32_t trefinterval);
-
-} LPDDR4_OBJ;
-
-/**
- * In order to access the LPDDR4 APIs, the upper layer software must call
- * this global function to obtain the pointer to the driver object.
- * @return LPDDR4_OBJ* Driver Object Pointer
- */
-extern LPDDR4_OBJ *lpddr4_getinstance(void);
-
-#endif /* LPDDR4_OBJ_IF_H */
diff --git a/drivers/ram/k3-j721e/lpddr4_pi_macros.h b/drivers/ram/k3-j721e/lpddr4_pi_macros.h
deleted file mode 100644
index 23b31f2..0000000
--- a/drivers/ram/k3-j721e/lpddr4_pi_macros.h
+++ /dev/null
@@ -1,5397 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- *
- * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
- *
- **********************************************************************
- */
-
-#ifndef REG_LPDDR4_PI_MACROS_H_
-#define REG_LPDDR4_PI_MACROS_H_
-
-#define LPDDR4__DENALI_PI_0_READ_MASK 0x00000F01U
-#define LPDDR4__DENALI_PI_0_WRITE_MASK 0x00000F01U
-#define LPDDR4__DENALI_PI_0__PI_START_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_0__PI_START_SHIFT 0U
-#define LPDDR4__DENALI_PI_0__PI_START_WIDTH 1U
-#define LPDDR4__DENALI_PI_0__PI_START_WOCLR 0U
-#define LPDDR4__DENALI_PI_0__PI_START_WOSET 0U
-#define LPDDR4__PI_START__REG DENALI_PI_0
-#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
-
-#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT 8U
-#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH 4U
-#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
-#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
-
-#define LPDDR4__DENALI_PI_1_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_1_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH 32U
-#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
-#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
-
-#define LPDDR4__DENALI_PI_2_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_2_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH 32U
-#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
-#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
-
-#define LPDDR4__DENALI_PI_3_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_3_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_3__PI_ID_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT 0U
-#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH 16U
-#define LPDDR4__PI_ID__REG DENALI_PI_3
-#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
-
-#define LPDDR4__DENALI_PI_4_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_4_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0_WIDTH 32U
-#define LPDDR4__DENALI_PI_UNUSED_REG_0__REG DENALI_PI_4
-#define LPDDR4__DENALI_PI_UNUSED_REG_0__FLD LPDDR4__DENALI_PI_4__DENALI_PI_UNUSED_REG_0
-
-#define LPDDR4__DENALI_PI_5_READ_MASK 0x00010101U
-#define LPDDR4__DENALI_PI_5_WRITE_MASK 0x00010101U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_SHIFT 0U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WIDTH 1U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOCLR 0U
-#define LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ_WOSET 0U
-#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_5
-#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_5__PI_NORMAL_LVL_SEQ
-
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_SHIFT 8U
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN_WOSET 0U
-#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_5
-#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_5__PI_INIT_LVL_EN
-
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_SHIFT 16U
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WIDTH 1U
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOCLR 0U
-#define LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD_WOSET 0U
-#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_5
-#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_5__PI_NOTCARE_PHYUPD
-
-#define LPDDR4__DENALI_PI_6_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_6_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_SHIFT 0U
-#define LPDDR4__DENALI_PI_6__PI_TCMD_GAP_WIDTH 16U
-#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_6
-#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_6__PI_TCMD_GAP
-
-#define LPDDR4__DENALI_PI_6__PI_RESERVED0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_6__PI_RESERVED0_SHIFT 16U
-#define LPDDR4__DENALI_PI_6__PI_RESERVED0_WIDTH 8U
-#define LPDDR4__PI_RESERVED0__REG DENALI_PI_6
-#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_6__PI_RESERVED0
-
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_SHIFT 24U
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WIDTH 1U
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOCLR 0U
-#define LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ_WOSET 0U
-#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_6
-#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_6__PI_TRAIN_ALL_FREQ_REQ
-
-#define LPDDR4__DENALI_PI_7_READ_MASK 0x01010301U
-#define LPDDR4__DENALI_PI_7_WRITE_MASK 0x01010301U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_SHIFT 0U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WIDTH 1U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOCLR 0U
-#define LPDDR4__DENALI_PI_7__PI_DFI_VERSION_WOSET 0U
-#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_7
-#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_7__PI_DFI_VERSION
-
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_SHIFT 8U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE_WIDTH 2U
-#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_7
-#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_TYPE
-
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT 16U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH 1U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR 0U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R_WOSET 0U
-#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_7
-#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_CS_STATE_R
-
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT 24U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH 1U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR 0U
-#define LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET 0U
-#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_7
-#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_7__PI_DFI_PHYMSTR_STATE_SEL_R
-
-#define LPDDR4__DENALI_PI_8_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_8_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_SHIFT 0U
-#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX_WIDTH 32U
-#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_8
-#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_MAX
-
-#define LPDDR4__DENALI_PI_9_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_9_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_SHIFT 0U
-#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP_WIDTH 20U
-#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_9
-#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYMSTR_RESP
-
-#define LPDDR4__DENALI_PI_10_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_10_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_SHIFT 0U
-#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP_WIDTH 20U
-#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_10
-#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_RESP
-
-#define LPDDR4__DENALI_PI_11_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_11_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_SHIFT 0U
-#define LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX_WIDTH 32U
-#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_11
-#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_11__PI_TDFI_PHYUPD_MAX
-
-#define LPDDR4__DENALI_PI_12_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_12_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT 0U
-#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH 32U
-#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
-#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
-
-#define LPDDR4__DENALI_PI_13_READ_MASK 0x0101011FU
-#define LPDDR4__DENALI_PI_13_WRITE_MASK 0x0101011FU
-#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_SHIFT 0U
-#define LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ_WIDTH 5U
-#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_13
-#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_13__PI_INIT_WORK_FREQ
-
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_SHIFT 8U
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WIDTH 1U
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOCLR 0U
-#define LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY_WOSET 0U
-#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_13
-#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_13__PI_INIT_DFS_CALVL_ONLY
-
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT 16U
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH 1U
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR 0U
-#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET 0U
-#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
-#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
-
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT 24U
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH 1U
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR 0U
-#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET 0U
-#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
-#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
-
-#define LPDDR4__DENALI_PI_14_READ_MASK 0x0F011F0FU
-#define LPDDR4__DENALI_PI_14_WRITE_MASK 0x0F011F0FU
-#define LPDDR4__DENALI_PI_14__PI_CS_MAP_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_14__PI_CS_MAP_SHIFT 0U
-#define LPDDR4__DENALI_PI_14__PI_CS_MAP_WIDTH 4U
-#define LPDDR4__PI_CS_MAP__REG DENALI_PI_14
-#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_14__PI_CS_MAP
-
-#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK 0x00001F00U
-#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT 8U
-#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH 5U
-#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
-#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
-
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT 16U
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET 0U
-#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
-#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
-
-#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT 24U
-#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH 4U
-#define LPDDR4__PI_TMRR__REG DENALI_PI_14
-#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
-
-#define LPDDR4__DENALI_PI_15_READ_MASK 0x00010103U
-#define LPDDR4__DENALI_PI_15_WRITE_MASK 0x00010103U
-#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_SHIFT 0U
-#define LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT_WIDTH 2U
-#define LPDDR4__PI_PREAMBLE_SUPPORT__REG DENALI_PI_15
-#define LPDDR4__PI_PREAMBLE_SUPPORT__FLD LPDDR4__DENALI_PI_15__PI_PREAMBLE_SUPPORT
-
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT 8U
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH 1U
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR 0U
-#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET 0U
-#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
-#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
-
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT 16U
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH 1U
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR 0U
-#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET 0U
-#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
-#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
-
-#define LPDDR4__DENALI_PI_16_READ_MASK 0x010FFFFFU
-#define LPDDR4__DENALI_PI_16_WRITE_MASK 0x010FFFFFU
-#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT 0U
-#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH 20U
-#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
-#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
-
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT 24U
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH 1U
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR 0U
-#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET 0U
-#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
-#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
-
-#define LPDDR4__DENALI_PI_17_READ_MASK 0x01010001U
-#define LPDDR4__DENALI_PI_17_WRITE_MASK 0x01010001U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT 0U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH 1U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR 0U
-#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET 0U
-#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
-#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
-
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT 8U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH 1U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR 0U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET 0U
-#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
-#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
-
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT 16U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH 1U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR 0U
-#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET 0U
-#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
-#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
-
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH 1U
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR 0U
-#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET 0U
-#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
-#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
-
-#define LPDDR4__DENALI_PI_18_READ_MASK 0x03010101U
-#define LPDDR4__DENALI_PI_18_WRITE_MASK 0x03010101U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH 1U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR 0U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET 0U
-#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
-#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
-
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WIDTH 1U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOCLR 0U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2_WOSET 0U
-#define LPDDR4__PI_SW_WRLVL_RESP_2__REG DENALI_PI_18
-#define LPDDR4__PI_SW_WRLVL_RESP_2__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_2
-
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WIDTH 1U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOCLR 0U
-#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3_WOSET 0U
-#define LPDDR4__PI_SW_WRLVL_RESP_3__REG DENALI_PI_18
-#define LPDDR4__PI_SW_WRLVL_RESP_3__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_3
-
-#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH 2U
-#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
-#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
-
-#define LPDDR4__DENALI_PI_19_READ_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_19_WRITE_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1_WIDTH 2U
-#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_19
-#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_1
-
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2_WIDTH 2U
-#define LPDDR4__PI_SW_RDLVL_RESP_2__REG DENALI_PI_19
-#define LPDDR4__PI_SW_RDLVL_RESP_2__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_2
-
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3_WIDTH 2U
-#define LPDDR4__PI_SW_RDLVL_RESP_3__REG DENALI_PI_19
-#define LPDDR4__PI_SW_RDLVL_RESP_3__FLD LPDDR4__DENALI_PI_19__PI_SW_RDLVL_RESP_3
-
-#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0_WIDTH 2U
-#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_19
-#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_19__PI_SW_CALVL_RESP_0
-
-#define LPDDR4__DENALI_PI_20_READ_MASK 0x00000007U
-#define LPDDR4__DENALI_PI_20_WRITE_MASK 0x00000007U
-#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_MASK 0x00000007U
-#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_SHIFT 0U
-#define LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE_WIDTH 3U
-#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_20
-#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_20__PI_SW_LEVELING_MODE
-
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_SHIFT 8U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WIDTH 1U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOCLR 0U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_START_WOSET 0U
-#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_20
-#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_START
-
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_SHIFT 16U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT_WOSET 0U
-#define LPDDR4__PI_SWLVL_EXIT__REG DENALI_PI_20
-#define LPDDR4__PI_SWLVL_EXIT__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_EXIT
-
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WIDTH 1U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOCLR 0U
-#define LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0_WOSET 0U
-#define LPDDR4__PI_SWLVL_WR_SLICE_0__REG DENALI_PI_20
-#define LPDDR4__PI_SWLVL_WR_SLICE_0__FLD LPDDR4__DENALI_PI_20__PI_SWLVL_WR_SLICE_0
-
-#define LPDDR4__DENALI_PI_21_READ_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_21_WRITE_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WIDTH 1U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOCLR 0U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0_WOSET 0U
-#define LPDDR4__PI_SWLVL_RD_SLICE_0__REG DENALI_PI_21
-#define LPDDR4__PI_SWLVL_RD_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_RD_SLICE_0
-
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WIDTH 1U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOCLR 0U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0_WOSET 0U
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__REG DENALI_PI_21
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_0__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_VREF_UPDATE_SLICE_0
-
-#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0_WIDTH 2U
-#define LPDDR4__PI_SW_WDQLVL_RESP_0__REG DENALI_PI_21
-#define LPDDR4__PI_SW_WDQLVL_RESP_0__FLD LPDDR4__DENALI_PI_21__PI_SW_WDQLVL_RESP_0
-
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_SHIFT 24U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WIDTH 1U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOCLR 0U
-#define LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1_WOSET 0U
-#define LPDDR4__PI_SWLVL_WR_SLICE_1__REG DENALI_PI_21
-#define LPDDR4__PI_SWLVL_WR_SLICE_1__FLD LPDDR4__DENALI_PI_21__PI_SWLVL_WR_SLICE_1
-
-#define LPDDR4__DENALI_PI_22_READ_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_22_WRITE_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WIDTH 1U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOCLR 0U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1_WOSET 0U
-#define LPDDR4__PI_SWLVL_RD_SLICE_1__REG DENALI_PI_22
-#define LPDDR4__PI_SWLVL_RD_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_RD_SLICE_1
-
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WIDTH 1U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOCLR 0U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1_WOSET 0U
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__REG DENALI_PI_22
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_1__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_VREF_UPDATE_SLICE_1
-
-#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1_WIDTH 2U
-#define LPDDR4__PI_SW_WDQLVL_RESP_1__REG DENALI_PI_22
-#define LPDDR4__PI_SW_WDQLVL_RESP_1__FLD LPDDR4__DENALI_PI_22__PI_SW_WDQLVL_RESP_1
-
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WIDTH 1U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOCLR 0U
-#define LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2_WOSET 0U
-#define LPDDR4__PI_SWLVL_WR_SLICE_2__REG DENALI_PI_22
-#define LPDDR4__PI_SWLVL_WR_SLICE_2__FLD LPDDR4__DENALI_PI_22__PI_SWLVL_WR_SLICE_2
-
-#define LPDDR4__DENALI_PI_23_READ_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_23_WRITE_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WIDTH 1U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOCLR 0U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2_WOSET 0U
-#define LPDDR4__PI_SWLVL_RD_SLICE_2__REG DENALI_PI_23
-#define LPDDR4__PI_SWLVL_RD_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_RD_SLICE_2
-
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WIDTH 1U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOCLR 0U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2_WOSET 0U
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__REG DENALI_PI_23
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_2__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_VREF_UPDATE_SLICE_2
-
-#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_SHIFT 16U
-#define LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2_WIDTH 2U
-#define LPDDR4__PI_SW_WDQLVL_RESP_2__REG DENALI_PI_23
-#define LPDDR4__PI_SW_WDQLVL_RESP_2__FLD LPDDR4__DENALI_PI_23__PI_SW_WDQLVL_RESP_2
-
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_SHIFT 24U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WIDTH 1U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOCLR 0U
-#define LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3_WOSET 0U
-#define LPDDR4__PI_SWLVL_WR_SLICE_3__REG DENALI_PI_23
-#define LPDDR4__PI_SWLVL_WR_SLICE_3__FLD LPDDR4__DENALI_PI_23__PI_SWLVL_WR_SLICE_3
-
-#define LPDDR4__DENALI_PI_24_READ_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_24_WRITE_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WIDTH 1U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOCLR 0U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3_WOSET 0U
-#define LPDDR4__PI_SWLVL_RD_SLICE_3__REG DENALI_PI_24
-#define LPDDR4__PI_SWLVL_RD_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_RD_SLICE_3
-
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WIDTH 1U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOCLR 0U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3_WOSET 0U
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__REG DENALI_PI_24
-#define LPDDR4__PI_SWLVL_VREF_UPDATE_SLICE_3__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_VREF_UPDATE_SLICE_3
-
-#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3_WIDTH 2U
-#define LPDDR4__PI_SW_WDQLVL_RESP_3__REG DENALI_PI_24
-#define LPDDR4__PI_SW_WDQLVL_RESP_3__FLD LPDDR4__DENALI_PI_24__PI_SW_WDQLVL_RESP_3
-
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_SHIFT 24U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WIDTH 1U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOCLR 0U
-#define LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START_WOSET 0U
-#define LPDDR4__PI_SWLVL_SM2_START__REG DENALI_PI_24
-#define LPDDR4__PI_SWLVL_SM2_START__FLD LPDDR4__DENALI_PI_24__PI_SWLVL_SM2_START
-
-#define LPDDR4__DENALI_PI_25_READ_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_25_WRITE_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_SHIFT 0U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WIDTH 1U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOCLR 0U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR_WOSET 0U
-#define LPDDR4__PI_SWLVL_SM2_WR__REG DENALI_PI_25
-#define LPDDR4__PI_SWLVL_SM2_WR__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_WR
-
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_SHIFT 8U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WIDTH 1U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOCLR 0U
-#define LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD_WOSET 0U
-#define LPDDR4__PI_SWLVL_SM2_RD__REG DENALI_PI_25
-#define LPDDR4__PI_SWLVL_SM2_RD__FLD LPDDR4__DENALI_PI_25__PI_SWLVL_SM2_RD
-
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_SHIFT 16U
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WIDTH 1U
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOCLR 0U
-#define LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ_WOSET 0U
-#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__REG DENALI_PI_25
-#define LPDDR4__PI_SEQUENTIAL_LVL_REQ__FLD LPDDR4__DENALI_PI_25__PI_SEQUENTIAL_LVL_REQ
-
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_SHIFT 24U
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN_WOSET 0U
-#define LPDDR4__PI_DFS_PERIOD_EN__REG DENALI_PI_25
-#define LPDDR4__PI_DFS_PERIOD_EN__FLD LPDDR4__DENALI_PI_25__PI_DFS_PERIOD_EN
-
-#define LPDDR4__DENALI_PI_26_READ_MASK 0x00010101U
-#define LPDDR4__DENALI_PI_26_WRITE_MASK 0x00010101U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_SHIFT 0U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN_WOSET 0U
-#define LPDDR4__PI_SRE_PERIOD_EN__REG DENALI_PI_26
-#define LPDDR4__PI_SRE_PERIOD_EN__FLD LPDDR4__DENALI_PI_26__PI_SRE_PERIOD_EN
-
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_SHIFT 8U
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WIDTH 1U
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOCLR 0U
-#define LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY_WOSET 0U
-#define LPDDR4__PI_DFI40_POLARITY__REG DENALI_PI_26
-#define LPDDR4__PI_DFI40_POLARITY__FLD LPDDR4__DENALI_PI_26__PI_DFI40_POLARITY
-
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_SHIFT 16U
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WIDTH 1U
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOCLR 0U
-#define LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT_WOSET 0U
-#define LPDDR4__PI_16BIT_DRAM_CONNECT__REG DENALI_PI_26
-#define LPDDR4__PI_16BIT_DRAM_CONNECT__FLD LPDDR4__DENALI_PI_26__PI_16BIT_DRAM_CONNECT
-
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_SHIFT 24U
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WIDTH 1U
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOCLR 0U
-#define LPDDR4__DENALI_PI_26__PI_WRLVL_REQ_WOSET 0U
-#define LPDDR4__PI_WRLVL_REQ__REG DENALI_PI_26
-#define LPDDR4__PI_WRLVL_REQ__FLD LPDDR4__DENALI_PI_26__PI_WRLVL_REQ
-
-#define LPDDR4__DENALI_PI_27_READ_MASK 0x003F3F03U
-#define LPDDR4__DENALI_PI_27_WRITE_MASK 0x003F3F03U
-#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_SHIFT 0U
-#define LPDDR4__DENALI_PI_27__PI_WRLVL_CS_WIDTH 2U
-#define LPDDR4__PI_WRLVL_CS__REG DENALI_PI_27
-#define LPDDR4__PI_WRLVL_CS__FLD LPDDR4__DENALI_PI_27__PI_WRLVL_CS
-
-#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_MASK 0x00003F00U
-#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_SHIFT 8U
-#define LPDDR4__DENALI_PI_27__PI_WLDQSEN_WIDTH 6U
-#define LPDDR4__PI_WLDQSEN__REG DENALI_PI_27
-#define LPDDR4__PI_WLDQSEN__FLD LPDDR4__DENALI_PI_27__PI_WLDQSEN
-
-#define LPDDR4__DENALI_PI_27__PI_WLMRD_MASK 0x003F0000U
-#define LPDDR4__DENALI_PI_27__PI_WLMRD_SHIFT 16U
-#define LPDDR4__DENALI_PI_27__PI_WLMRD_WIDTH 6U
-#define LPDDR4__PI_WLMRD__REG DENALI_PI_27
-#define LPDDR4__PI_WLMRD__FLD LPDDR4__DENALI_PI_27__PI_WLMRD
-
-#define LPDDR4__DENALI_PI_28_READ_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_PI_28_WRITE_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_SHIFT 0U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL_WIDTH 16U
-#define LPDDR4__PI_WRLVL_INTERVAL__REG DENALI_PI_28
-#define LPDDR4__PI_WRLVL_INTERVAL__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_INTERVAL
-
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_SHIFT 16U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WIDTH 1U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOCLR 0U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC_WOSET 0U
-#define LPDDR4__PI_WRLVL_PERIODIC__REG DENALI_PI_28
-#define LPDDR4__PI_WRLVL_PERIODIC__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_PERIODIC
-
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_SHIFT 24U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT_WOSET 0U
-#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__REG DENALI_PI_28
-#define LPDDR4__PI_WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_28__PI_WRLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_29_READ_MASK 0x0F010F01U
-#define LPDDR4__DENALI_PI_29_WRITE_MASK 0x0F010F01U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_SHIFT 0U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WIDTH 1U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOCLR 0U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS_WOSET 0U
-#define LPDDR4__PI_WRLVL_DISABLE_DFS__REG DENALI_PI_29
-#define LPDDR4__PI_WRLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_SHIFT 8U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK_WIDTH 4U
-#define LPDDR4__PI_WRLVL_RESP_MASK__REG DENALI_PI_29
-#define LPDDR4__PI_WRLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_RESP_MASK
-
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_SHIFT 16U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE_WOSET 0U
-#define LPDDR4__PI_WRLVL_ROTATE__REG DENALI_PI_29
-#define LPDDR4__PI_WRLVL_ROTATE__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_ROTATE
-
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_SHIFT 24U
-#define LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP_WIDTH 4U
-#define LPDDR4__PI_WRLVL_CS_MAP__REG DENALI_PI_29
-#define LPDDR4__PI_WRLVL_CS_MAP__FLD LPDDR4__DENALI_PI_29__PI_WRLVL_CS_MAP
-
-#define LPDDR4__DENALI_PI_30_READ_MASK 0x0000FF01U
-#define LPDDR4__DENALI_PI_30_WRITE_MASK 0x0000FF01U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WIDTH 1U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOCLR 0U
-#define LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS_WOSET 0U
-#define LPDDR4__PI_WRLVL_ERROR_STATUS__REG DENALI_PI_30
-#define LPDDR4__PI_WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_30__PI_WRLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_SHIFT 8U
-#define LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN_WIDTH 8U
-#define LPDDR4__PI_TDFI_WRLVL_EN__REG DENALI_PI_30
-#define LPDDR4__PI_TDFI_WRLVL_EN__FLD LPDDR4__DENALI_PI_30__PI_TDFI_WRLVL_EN
-
-#define LPDDR4__DENALI_PI_31_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_31_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_SHIFT 0U
-#define LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP_WIDTH 32U
-#define LPDDR4__PI_TDFI_WRLVL_RESP__REG DENALI_PI_31
-#define LPDDR4__PI_TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_PI_31__PI_TDFI_WRLVL_RESP
-
-#define LPDDR4__DENALI_PI_32_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_32_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_SHIFT 0U
-#define LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX_WIDTH 32U
-#define LPDDR4__PI_TDFI_WRLVL_MAX__REG DENALI_PI_32
-#define LPDDR4__PI_TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_PI_32__PI_TDFI_WRLVL_MAX
-
-#define LPDDR4__DENALI_PI_33_READ_MASK 0x0F0F0F1FU
-#define LPDDR4__DENALI_PI_33_WRITE_MASK 0x0F0F0F1FU
-#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_SHIFT 0U
-#define LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM_WIDTH 5U
-#define LPDDR4__PI_WRLVL_STROBE_NUM__REG DENALI_PI_33
-#define LPDDR4__PI_WRLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_33__PI_WRLVL_STROBE_NUM
-
-#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_SHIFT 8U
-#define LPDDR4__DENALI_PI_33__PI_TODTH_WR_WIDTH 4U
-#define LPDDR4__PI_TODTH_WR__REG DENALI_PI_33
-#define LPDDR4__PI_TODTH_WR__FLD LPDDR4__DENALI_PI_33__PI_TODTH_WR
-
-#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_SHIFT 16U
-#define LPDDR4__DENALI_PI_33__PI_TODTH_RD_WIDTH 4U
-#define LPDDR4__PI_TODTH_RD__REG DENALI_PI_33
-#define LPDDR4__PI_TODTH_RD__FLD LPDDR4__DENALI_PI_33__PI_TODTH_RD
-
-#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_SHIFT 24U
-#define LPDDR4__DENALI_PI_33__PI_ODT_VALUE_WIDTH 4U
-#define LPDDR4__PI_ODT_VALUE__REG DENALI_PI_33
-#define LPDDR4__PI_ODT_VALUE__FLD LPDDR4__DENALI_PI_33__PI_ODT_VALUE
-
-#define LPDDR4__DENALI_PI_34_READ_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_34_WRITE_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_SHIFT 0U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WIDTH 1U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOCLR 0U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_REQ_WOSET 0U
-#define LPDDR4__PI_RDLVL_REQ__REG DENALI_PI_34
-#define LPDDR4__PI_RDLVL_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_REQ
-
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_SHIFT 8U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WIDTH 1U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOCLR 0U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ_WOSET 0U
-#define LPDDR4__PI_RDLVL_GATE_REQ__REG DENALI_PI_34
-#define LPDDR4__PI_RDLVL_GATE_REQ__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_GATE_REQ
-
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_SHIFT 16U
-#define LPDDR4__DENALI_PI_34__PI_RDLVL_CS_WIDTH 2U
-#define LPDDR4__PI_RDLVL_CS__REG DENALI_PI_34
-#define LPDDR4__PI_RDLVL_CS__FLD LPDDR4__DENALI_PI_34__PI_RDLVL_CS
-
-#define LPDDR4__DENALI_PI_35_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_35_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0_WIDTH 32U
-#define LPDDR4__PI_RDLVL_PAT_0__REG DENALI_PI_35
-#define LPDDR4__PI_RDLVL_PAT_0__FLD LPDDR4__DENALI_PI_35__PI_RDLVL_PAT_0
-
-#define LPDDR4__DENALI_PI_36_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_36_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1_WIDTH 32U
-#define LPDDR4__PI_RDLVL_PAT_1__REG DENALI_PI_36
-#define LPDDR4__PI_RDLVL_PAT_1__FLD LPDDR4__DENALI_PI_36__PI_RDLVL_PAT_1
-
-#define LPDDR4__DENALI_PI_37_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_37_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2_WIDTH 32U
-#define LPDDR4__PI_RDLVL_PAT_2__REG DENALI_PI_37
-#define LPDDR4__PI_RDLVL_PAT_2__FLD LPDDR4__DENALI_PI_37__PI_RDLVL_PAT_2
-
-#define LPDDR4__DENALI_PI_38_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_38_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3_WIDTH 32U
-#define LPDDR4__PI_RDLVL_PAT_3__REG DENALI_PI_38
-#define LPDDR4__PI_RDLVL_PAT_3__FLD LPDDR4__DENALI_PI_38__PI_RDLVL_PAT_3
-
-#define LPDDR4__DENALI_PI_39_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_39_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_SHIFT 0U
-#define LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4_WIDTH 32U
-#define LPDDR4__PI_RDLVL_PAT_4__REG DENALI_PI_39
-#define LPDDR4__PI_RDLVL_PAT_4__FLD LPDDR4__DENALI_PI_39__PI_RDLVL_PAT_4
-
-#define LPDDR4__DENALI_PI_40_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_40_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_SHIFT 0U
-#define LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5_WIDTH 32U
-#define LPDDR4__PI_RDLVL_PAT_5__REG DENALI_PI_40
-#define LPDDR4__PI_RDLVL_PAT_5__FLD LPDDR4__DENALI_PI_40__PI_RDLVL_PAT_5
-
-#define LPDDR4__DENALI_PI_41_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_41_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_SHIFT 0U
-#define LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6_WIDTH 32U
-#define LPDDR4__PI_RDLVL_PAT_6__REG DENALI_PI_41
-#define LPDDR4__PI_RDLVL_PAT_6__FLD LPDDR4__DENALI_PI_41__PI_RDLVL_PAT_6
-
-#define LPDDR4__DENALI_PI_42_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_42_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_SHIFT 0U
-#define LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7_WIDTH 32U
-#define LPDDR4__PI_RDLVL_PAT_7__REG DENALI_PI_42
-#define LPDDR4__PI_RDLVL_PAT_7__FLD LPDDR4__DENALI_PI_42__PI_RDLVL_PAT_7
-
-#define LPDDR4__DENALI_PI_43_READ_MASK 0x0101010FU
-#define LPDDR4__DENALI_PI_43_WRITE_MASK 0x0101010FU
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_SHIFT 0U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN_WIDTH 4U
-#define LPDDR4__PI_RDLVL_SEQ_EN__REG DENALI_PI_43
-#define LPDDR4__PI_RDLVL_SEQ_EN__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_SEQ_EN
-
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_SHIFT 8U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WIDTH 1U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOCLR 0U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC_WOSET 0U
-#define LPDDR4__PI_RDLVL_PERIODIC__REG DENALI_PI_43
-#define LPDDR4__PI_RDLVL_PERIODIC__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_PERIODIC
-
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_SHIFT 16U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT_WOSET 0U
-#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__REG DENALI_PI_43
-#define LPDDR4__PI_RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_SHIFT 24U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WIDTH 1U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOCLR 0U
-#define LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS_WOSET 0U
-#define LPDDR4__PI_RDLVL_DISABLE_DFS__REG DENALI_PI_43
-#define LPDDR4__PI_RDLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_43__PI_RDLVL_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_44_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_44_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_SHIFT 0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WIDTH 1U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOCLR 0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC_WOSET 0U
-#define LPDDR4__PI_RDLVL_GATE_PERIODIC__REG DENALI_PI_44
-#define LPDDR4__PI_RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_PERIODIC
-
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_SHIFT 8U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT_WOSET 0U
-#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__REG DENALI_PI_44
-#define LPDDR4__PI_RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_SHIFT 16U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WIDTH 1U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOCLR 0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS_WOSET 0U
-#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__REG DENALI_PI_44
-#define LPDDR4__PI_RDLVL_GATE_DISABLE_DFS__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_GATE_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_SHIFT 24U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE_WOSET 0U
-#define LPDDR4__PI_RDLVL_ROTATE__REG DENALI_PI_44
-#define LPDDR4__PI_RDLVL_ROTATE__FLD LPDDR4__DENALI_PI_44__PI_RDLVL_ROTATE
-
-#define LPDDR4__DENALI_PI_45_READ_MASK 0x000F0F01U
-#define LPDDR4__DENALI_PI_45_WRITE_MASK 0x000F0F01U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_SHIFT 0U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE_WOSET 0U
-#define LPDDR4__PI_RDLVL_GATE_ROTATE__REG DENALI_PI_45
-#define LPDDR4__PI_RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_ROTATE
-
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_SHIFT 8U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP_WIDTH 4U
-#define LPDDR4__PI_RDLVL_CS_MAP__REG DENALI_PI_45
-#define LPDDR4__PI_RDLVL_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_CS_MAP
-
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_SHIFT 16U
-#define LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP_WIDTH 4U
-#define LPDDR4__PI_RDLVL_GATE_CS_MAP__REG DENALI_PI_45
-#define LPDDR4__PI_RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_PI_45__PI_RDLVL_GATE_CS_MAP
-
-#define LPDDR4__DENALI_PI_46_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_46_WRITE_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_SHIFT 0U
-#define LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR_WIDTH 10U
-#define LPDDR4__PI_TDFI_RDLVL_RR__REG DENALI_PI_46
-#define LPDDR4__PI_TDFI_RDLVL_RR__FLD LPDDR4__DENALI_PI_46__PI_TDFI_RDLVL_RR
-
-#define LPDDR4__DENALI_PI_47_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_47_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_SHIFT 0U
-#define LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP_WIDTH 32U
-#define LPDDR4__PI_TDFI_RDLVL_RESP__REG DENALI_PI_47
-#define LPDDR4__PI_TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_PI_47__PI_TDFI_RDLVL_RESP
-
-#define LPDDR4__DENALI_PI_48_READ_MASK 0x0000FF0FU
-#define LPDDR4__DENALI_PI_48_WRITE_MASK 0x0000FF0FU
-#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_SHIFT 0U
-#define LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK_WIDTH 4U
-#define LPDDR4__PI_RDLVL_RESP_MASK__REG DENALI_PI_48
-#define LPDDR4__PI_RDLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_48__PI_RDLVL_RESP_MASK
-
-#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_SHIFT 8U
-#define LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN_WIDTH 8U
-#define LPDDR4__PI_TDFI_RDLVL_EN__REG DENALI_PI_48
-#define LPDDR4__PI_TDFI_RDLVL_EN__FLD LPDDR4__DENALI_PI_48__PI_TDFI_RDLVL_EN
-
-#define LPDDR4__DENALI_PI_49_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_49_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_SHIFT 0U
-#define LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX_WIDTH 32U
-#define LPDDR4__PI_TDFI_RDLVL_MAX__REG DENALI_PI_49
-#define LPDDR4__PI_TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_PI_49__PI_TDFI_RDLVL_MAX
-
-#define LPDDR4__DENALI_PI_50_READ_MASK 0x00FFFF01U
-#define LPDDR4__DENALI_PI_50_WRITE_MASK 0x00FFFF01U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WIDTH 1U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOCLR 0U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS_WOSET 0U
-#define LPDDR4__PI_RDLVL_ERROR_STATUS__REG DENALI_PI_50
-#define LPDDR4__PI_RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_SHIFT 8U
-#define LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL_WIDTH 16U
-#define LPDDR4__PI_RDLVL_INTERVAL__REG DENALI_PI_50
-#define LPDDR4__PI_RDLVL_INTERVAL__FLD LPDDR4__DENALI_PI_50__PI_RDLVL_INTERVAL
-
-#define LPDDR4__DENALI_PI_51_READ_MASK 0x0F0FFFFFU
-#define LPDDR4__DENALI_PI_51_WRITE_MASK 0x0F0FFFFFU
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_SHIFT 0U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL_WIDTH 16U
-#define LPDDR4__PI_RDLVL_GATE_INTERVAL__REG DENALI_PI_51
-#define LPDDR4__PI_RDLVL_GATE_INTERVAL__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_GATE_INTERVAL
-
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_SHIFT 16U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START_WIDTH 4U
-#define LPDDR4__PI_RDLVL_PATTERN_START__REG DENALI_PI_51
-#define LPDDR4__PI_RDLVL_PATTERN_START__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_START
-
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_SHIFT 24U
-#define LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM_WIDTH 4U
-#define LPDDR4__PI_RDLVL_PATTERN_NUM__REG DENALI_PI_51
-#define LPDDR4__PI_RDLVL_PATTERN_NUM__FLD LPDDR4__DENALI_PI_51__PI_RDLVL_PATTERN_NUM
-
-#define LPDDR4__DENALI_PI_52_READ_MASK 0x01011F1FU
-#define LPDDR4__DENALI_PI_52_WRITE_MASK 0x01011F1FU
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_SHIFT 0U
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM_WIDTH 5U
-#define LPDDR4__PI_RDLVL_STROBE_NUM__REG DENALI_PI_52
-#define LPDDR4__PI_RDLVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_STROBE_NUM
-
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_MASK 0x00001F00U
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_SHIFT 8U
-#define LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM_WIDTH 5U
-#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__REG DENALI_PI_52
-#define LPDDR4__PI_RDLVL_GATE_STROBE_NUM__FLD LPDDR4__DENALI_PI_52__PI_RDLVL_GATE_STROBE_NUM
-
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_SHIFT 16U
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN_WOSET 0U
-#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__REG DENALI_PI_52
-#define LPDDR4__PI_RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_PI_52__PI_RD_PREAMBLE_TRAINING_EN
-
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_SHIFT 24U
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE_WOSET 0U
-#define LPDDR4__PI_REG_DIMM_ENABLE__REG DENALI_PI_52
-#define LPDDR4__PI_REG_DIMM_ENABLE__FLD LPDDR4__DENALI_PI_52__PI_REG_DIMM_ENABLE
-
-#define LPDDR4__DENALI_PI_53_READ_MASK 0x03007F7FU
-#define LPDDR4__DENALI_PI_53_WRITE_MASK 0x03007F7FU
-#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_SHIFT 0U
-#define LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN_WIDTH 7U
-#define LPDDR4__PI_TDFI_RDDATA_EN__REG DENALI_PI_53
-#define LPDDR4__PI_TDFI_RDDATA_EN__FLD LPDDR4__DENALI_PI_53__PI_TDFI_RDDATA_EN
-
-#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_SHIFT 8U
-#define LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT_WIDTH 7U
-#define LPDDR4__PI_TDFI_PHY_WRLAT__REG DENALI_PI_53
-#define LPDDR4__PI_TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_PI_53__PI_TDFI_PHY_WRLAT
-
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_SHIFT 16U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WIDTH 1U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOCLR 0U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_REQ_WOSET 0U
-#define LPDDR4__PI_CALVL_REQ__REG DENALI_PI_53
-#define LPDDR4__PI_CALVL_REQ__FLD LPDDR4__DENALI_PI_53__PI_CALVL_REQ
-
-#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_SHIFT 24U
-#define LPDDR4__DENALI_PI_53__PI_CALVL_CS_WIDTH 2U
-#define LPDDR4__PI_CALVL_CS__REG DENALI_PI_53
-#define LPDDR4__PI_CALVL_CS__FLD LPDDR4__DENALI_PI_53__PI_CALVL_CS
-
-#define LPDDR4__DENALI_PI_54_READ_MASK 0x01030F01U
-#define LPDDR4__DENALI_PI_54_WRITE_MASK 0x01030F01U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_SHIFT 0U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WIDTH 1U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOCLR 0U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED3_WOSET 0U
-#define LPDDR4__PI_RESERVED3__REG DENALI_PI_54
-#define LPDDR4__PI_RESERVED3__FLD LPDDR4__DENALI_PI_54__PI_RESERVED3
-
-#define LPDDR4__DENALI_PI_54__PI_RESERVED4_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED4_SHIFT 8U
-#define LPDDR4__DENALI_PI_54__PI_RESERVED4_WIDTH 4U
-#define LPDDR4__PI_RESERVED4__REG DENALI_PI_54
-#define LPDDR4__PI_RESERVED4__FLD LPDDR4__DENALI_PI_54__PI_RESERVED4
-
-#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_SHIFT 16U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN_WIDTH 2U
-#define LPDDR4__PI_CALVL_SEQ_EN__REG DENALI_PI_54
-#define LPDDR4__PI_CALVL_SEQ_EN__FLD LPDDR4__DENALI_PI_54__PI_CALVL_SEQ_EN
-
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_SHIFT 24U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WIDTH 1U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOCLR 0U
-#define LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC_WOSET 0U
-#define LPDDR4__PI_CALVL_PERIODIC__REG DENALI_PI_54
-#define LPDDR4__PI_CALVL_PERIODIC__FLD LPDDR4__DENALI_PI_54__PI_CALVL_PERIODIC
-
-#define LPDDR4__DENALI_PI_55_READ_MASK 0x0F010101U
-#define LPDDR4__DENALI_PI_55_WRITE_MASK 0x0F010101U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_SHIFT 0U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT_WOSET 0U
-#define LPDDR4__PI_CALVL_ON_SREF_EXIT__REG DENALI_PI_55
-#define LPDDR4__PI_CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_SHIFT 8U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WIDTH 1U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOCLR 0U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS_WOSET 0U
-#define LPDDR4__PI_CALVL_DISABLE_DFS__REG DENALI_PI_55
-#define LPDDR4__PI_CALVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_55__PI_CALVL_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_SHIFT 16U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE_WOSET 0U
-#define LPDDR4__PI_CALVL_ROTATE__REG DENALI_PI_55
-#define LPDDR4__PI_CALVL_ROTATE__FLD LPDDR4__DENALI_PI_55__PI_CALVL_ROTATE
-
-#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_SHIFT 24U
-#define LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP_WIDTH 4U
-#define LPDDR4__PI_CALVL_CS_MAP__REG DENALI_PI_55
-#define LPDDR4__PI_CALVL_CS_MAP__FLD LPDDR4__DENALI_PI_55__PI_CALVL_CS_MAP
-
-#define LPDDR4__DENALI_PI_56_READ_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_56_WRITE_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_SHIFT 0U
-#define LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN_WIDTH 8U
-#define LPDDR4__PI_TDFI_CALVL_EN__REG DENALI_PI_56
-#define LPDDR4__PI_TDFI_CALVL_EN__FLD LPDDR4__DENALI_PI_56__PI_TDFI_CALVL_EN
-
-#define LPDDR4__DENALI_PI_57_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_57_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_SHIFT 0U
-#define LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP_WIDTH 32U
-#define LPDDR4__PI_TDFI_CALVL_RESP__REG DENALI_PI_57
-#define LPDDR4__PI_TDFI_CALVL_RESP__FLD LPDDR4__DENALI_PI_57__PI_TDFI_CALVL_RESP
-
-#define LPDDR4__DENALI_PI_58_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_58_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_SHIFT 0U
-#define LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX_WIDTH 32U
-#define LPDDR4__PI_TDFI_CALVL_MAX__REG DENALI_PI_58
-#define LPDDR4__PI_TDFI_CALVL_MAX__FLD LPDDR4__DENALI_PI_58__PI_TDFI_CALVL_MAX
-
-#define LPDDR4__DENALI_PI_59_READ_MASK 0xFFFF0301U
-#define LPDDR4__DENALI_PI_59_WRITE_MASK 0xFFFF0301U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_SHIFT 0U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WIDTH 1U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOCLR 0U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK_WOSET 0U
-#define LPDDR4__PI_CALVL_RESP_MASK__REG DENALI_PI_59
-#define LPDDR4__PI_CALVL_RESP_MASK__FLD LPDDR4__DENALI_PI_59__PI_CALVL_RESP_MASK
-
-#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_SHIFT 8U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS_WIDTH 2U
-#define LPDDR4__PI_CALVL_ERROR_STATUS__REG DENALI_PI_59
-#define LPDDR4__PI_CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_59__PI_CALVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_SHIFT 16U
-#define LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL_WIDTH 16U
-#define LPDDR4__PI_CALVL_INTERVAL__REG DENALI_PI_59
-#define LPDDR4__PI_CALVL_INTERVAL__FLD LPDDR4__DENALI_PI_59__PI_CALVL_INTERVAL
-
-#define LPDDR4__DENALI_PI_60_READ_MASK 0x1F1F3F1FU
-#define LPDDR4__DENALI_PI_60_WRITE_MASK 0x1F1F3F1FU
-#define LPDDR4__DENALI_PI_60__PI_TCACKEL_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_60__PI_TCACKEL_SHIFT 0U
-#define LPDDR4__DENALI_PI_60__PI_TCACKEL_WIDTH 5U
-#define LPDDR4__PI_TCACKEL__REG DENALI_PI_60
-#define LPDDR4__PI_TCACKEL__FLD LPDDR4__DENALI_PI_60__PI_TCACKEL
-
-#define LPDDR4__DENALI_PI_60__PI_TCAMRD_MASK 0x00003F00U
-#define LPDDR4__DENALI_PI_60__PI_TCAMRD_SHIFT 8U
-#define LPDDR4__DENALI_PI_60__PI_TCAMRD_WIDTH 6U
-#define LPDDR4__PI_TCAMRD__REG DENALI_PI_60
-#define LPDDR4__PI_TCAMRD__FLD LPDDR4__DENALI_PI_60__PI_TCAMRD
-
-#define LPDDR4__DENALI_PI_60__PI_TCACKEH_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_60__PI_TCACKEH_SHIFT 16U
-#define LPDDR4__DENALI_PI_60__PI_TCACKEH_WIDTH 5U
-#define LPDDR4__PI_TCACKEH__REG DENALI_PI_60
-#define LPDDR4__PI_TCACKEH__FLD LPDDR4__DENALI_PI_60__PI_TCACKEH
-
-#define LPDDR4__DENALI_PI_60__PI_TCAEXT_MASK 0x1F000000U
-#define LPDDR4__DENALI_PI_60__PI_TCAEXT_SHIFT 24U
-#define LPDDR4__DENALI_PI_60__PI_TCAEXT_WIDTH 5U
-#define LPDDR4__PI_TCAEXT__REG DENALI_PI_60
-#define LPDDR4__PI_TCAEXT__FLD LPDDR4__DENALI_PI_60__PI_TCAEXT
-
-#define LPDDR4__DENALI_PI_61_READ_MASK 0xFF0F0F01U
-#define LPDDR4__DENALI_PI_61_WRITE_MASK 0xFF0F0F01U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_SHIFT 0U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN_WOSET 0U
-#define LPDDR4__PI_CA_TRAIN_VREF_EN__REG DENALI_PI_61
-#define LPDDR4__PI_CA_TRAIN_VREF_EN__FLD LPDDR4__DENALI_PI_61__PI_CA_TRAIN_VREF_EN
-
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_SHIFT 8U
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE_WIDTH 4U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_61
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_INITIAL_STEPSIZE
-
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_SHIFT 16U
-#define LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE_WIDTH 4U
-#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_61
-#define LPDDR4__PI_CALVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_61__PI_CALVL_VREF_NORMAL_STEPSIZE
-
-#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_SHIFT 24U
-#define LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN_WIDTH 8U
-#define LPDDR4__PI_TDFI_INIT_START_MIN__REG DENALI_PI_61
-#define LPDDR4__PI_TDFI_INIT_START_MIN__FLD LPDDR4__DENALI_PI_61__PI_TDFI_INIT_START_MIN
-
-#define LPDDR4__DENALI_PI_62_READ_MASK 0x7F1F0FFFU
-#define LPDDR4__DENALI_PI_62_WRITE_MASK 0x7F1F0FFFU
-#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_SHIFT 0U
-#define LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN_WIDTH 8U
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__REG DENALI_PI_62
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_MIN__FLD LPDDR4__DENALI_PI_62__PI_TDFI_INIT_COMPLETE_MIN
-
-#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_SHIFT 8U
-#define LPDDR4__DENALI_PI_62__PI_TCKCKEH_WIDTH 4U
-#define LPDDR4__PI_TCKCKEH__REG DENALI_PI_62
-#define LPDDR4__PI_TCKCKEH__FLD LPDDR4__DENALI_PI_62__PI_TCKCKEH
-
-#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_SHIFT 16U
-#define LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM_WIDTH 5U
-#define LPDDR4__PI_CALVL_STROBE_NUM__REG DENALI_PI_62
-#define LPDDR4__PI_CALVL_STROBE_NUM__FLD LPDDR4__DENALI_PI_62__PI_CALVL_STROBE_NUM
-
-#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_SHIFT 24U
-#define LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF_WIDTH 7U
-#define LPDDR4__PI_SW_CA_TRAIN_VREF__REG DENALI_PI_62
-#define LPDDR4__PI_SW_CA_TRAIN_VREF__FLD LPDDR4__DENALI_PI_62__PI_SW_CA_TRAIN_VREF
-
-#define LPDDR4__DENALI_PI_63_READ_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_PI_63_WRITE_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_SHIFT 0U
-#define LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START_WIDTH 8U
-#define LPDDR4__PI_CLKDISABLE_2_INIT_START__REG DENALI_PI_63
-#define LPDDR4__PI_CLKDISABLE_2_INIT_START__FLD LPDDR4__DENALI_PI_63__PI_CLKDISABLE_2_INIT_START
-
-#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_SHIFT 8U
-#define LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE_WIDTH 8U
-#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__REG DENALI_PI_63
-#define LPDDR4__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE__FLD LPDDR4__DENALI_PI_63__PI_INIT_STARTORCOMPLETE_2_CLKDISABLE
-
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_SHIFT 16U
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WIDTH 1U
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOCLR 0U
-#define LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL_WOSET 0U
-#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__REG DENALI_PI_63
-#define LPDDR4__PI_DRAM_CLK_DISABLE_DEASSERT_SEL__FLD LPDDR4__DENALI_PI_63__PI_DRAM_CLK_DISABLE_DEASSERT_SEL
-
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_SHIFT 24U
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WIDTH 1U
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOCLR 0U
-#define LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE_WOSET 0U
-#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__REG DENALI_PI_63
-#define LPDDR4__PI_REFRESH_BETWEEN_SEGMENT_DISABLE__FLD LPDDR4__DENALI_PI_63__PI_REFRESH_BETWEEN_SEGMENT_DISABLE
-
-#define LPDDR4__DENALI_PI_64_READ_MASK 0x00FFFF01U
-#define LPDDR4__DENALI_PI_64_WRITE_MASK 0x00FFFF01U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_SHIFT 0U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WIDTH 1U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOCLR 0U
-#define LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE_WOSET 0U
-#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__REG DENALI_PI_64
-#define LPDDR4__PI_MC_DFS_PI_SET_VREF_ENABLE__FLD LPDDR4__DENALI_PI_64__PI_MC_DFS_PI_SET_VREF_ENABLE
-
-#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_MASK 0x00FFFF00U
-#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_SHIFT 8U
-#define LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK_WIDTH 16U
-#define LPDDR4__PI_FSM_ERROR_INFO_MASK__REG DENALI_PI_64
-#define LPDDR4__PI_FSM_ERROR_INFO_MASK__FLD LPDDR4__DENALI_PI_64__PI_FSM_ERROR_INFO_MASK
-
-#define LPDDR4__DENALI_PI_65_READ_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_PI_65_WRITE_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_SHIFT 0U
-#define LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR_WIDTH 16U
-#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__REG DENALI_PI_65
-#define LPDDR4__PI_SC_FSM_ERROR_INFO_WOCLR__FLD LPDDR4__DENALI_PI_65__PI_SC_FSM_ERROR_INFO_WOCLR
-
-#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_SHIFT 16U
-#define LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO_WIDTH 16U
-#define LPDDR4__PI_FSM_ERROR_INFO__REG DENALI_PI_65
-#define LPDDR4__PI_FSM_ERROR_INFO__FLD LPDDR4__DENALI_PI_65__PI_FSM_ERROR_INFO
-
-#define LPDDR4__DENALI_PI_66_READ_MASK 0x010F0701U
-#define LPDDR4__DENALI_PI_66_WRITE_MASK 0x010F0701U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_SHIFT 0U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN_WOSET 0U
-#define LPDDR4__PI_WDQLVL_VREF_EN__REG DENALI_PI_66
-#define LPDDR4__PI_WDQLVL_VREF_EN__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_VREF_EN
-
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_MASK 0x00000700U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_SHIFT 8U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM_WIDTH 3U
-#define LPDDR4__PI_WDQLVL_BST_NUM__REG DENALI_PI_66
-#define LPDDR4__PI_WDQLVL_BST_NUM__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_BST_NUM
-
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_SHIFT 16U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK_WIDTH 4U
-#define LPDDR4__PI_WDQLVL_RESP_MASK__REG DENALI_PI_66
-#define LPDDR4__PI_WDQLVL_RESP_MASK__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_RESP_MASK
-
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_SHIFT 24U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WIDTH 1U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOCLR 0U
-#define LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE_WOSET 0U
-#define LPDDR4__PI_WDQLVL_ROTATE__REG DENALI_PI_66
-#define LPDDR4__PI_WDQLVL_ROTATE__FLD LPDDR4__DENALI_PI_66__PI_WDQLVL_ROTATE
-
-#define LPDDR4__DENALI_PI_67_READ_MASK 0x011F1F0FU
-#define LPDDR4__DENALI_PI_67_WRITE_MASK 0x011F1F0FU
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_SHIFT 0U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP_WIDTH 4U
-#define LPDDR4__PI_WDQLVL_CS_MAP__REG DENALI_PI_67
-#define LPDDR4__PI_WDQLVL_CS_MAP__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_CS_MAP
-
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_MASK 0x00001F00U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_SHIFT 8U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE_WIDTH 5U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__REG DENALI_PI_67
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_INITIAL_STEPSIZE
-
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_SHIFT 16U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE_WIDTH 5U
-#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__REG DENALI_PI_67
-#define LPDDR4__PI_WDQLVL_VREF_NORMAL_STEPSIZE__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_VREF_NORMAL_STEPSIZE
-
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_SHIFT 24U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WIDTH 1U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOCLR 0U
-#define LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC_WOSET 0U
-#define LPDDR4__PI_WDQLVL_PERIODIC__REG DENALI_PI_67
-#define LPDDR4__PI_WDQLVL_PERIODIC__FLD LPDDR4__DENALI_PI_67__PI_WDQLVL_PERIODIC
-
-#define LPDDR4__DENALI_PI_68_READ_MASK 0x00FF0300U
-#define LPDDR4__DENALI_PI_68_WRITE_MASK 0x00FF0300U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_SHIFT 0U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WIDTH 1U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOCLR 0U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ_WOSET 0U
-#define LPDDR4__PI_WDQLVL_REQ__REG DENALI_PI_68
-#define LPDDR4__PI_WDQLVL_REQ__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_REQ
-
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_SHIFT 8U
-#define LPDDR4__DENALI_PI_68__PI_WDQLVL_CS_WIDTH 2U
-#define LPDDR4__PI_WDQLVL_CS__REG DENALI_PI_68
-#define LPDDR4__PI_WDQLVL_CS__FLD LPDDR4__DENALI_PI_68__PI_WDQLVL_CS
-
-#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_SHIFT 16U
-#define LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN_WIDTH 8U
-#define LPDDR4__PI_TDFI_WDQLVL_EN__REG DENALI_PI_68
-#define LPDDR4__PI_TDFI_WDQLVL_EN__FLD LPDDR4__DENALI_PI_68__PI_TDFI_WDQLVL_EN
-
-#define LPDDR4__DENALI_PI_69_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_69_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_SHIFT 0U
-#define LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP_WIDTH 32U
-#define LPDDR4__PI_TDFI_WDQLVL_RESP__REG DENALI_PI_69
-#define LPDDR4__PI_TDFI_WDQLVL_RESP__FLD LPDDR4__DENALI_PI_69__PI_TDFI_WDQLVL_RESP
-
-#define LPDDR4__DENALI_PI_70_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_70_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_SHIFT 0U
-#define LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX_WIDTH 32U
-#define LPDDR4__PI_TDFI_WDQLVL_MAX__REG DENALI_PI_70
-#define LPDDR4__PI_TDFI_WDQLVL_MAX__FLD LPDDR4__DENALI_PI_70__PI_TDFI_WDQLVL_MAX
-
-#define LPDDR4__DENALI_PI_71_READ_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_PI_71_WRITE_MASK 0x0101FFFFU
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_SHIFT 0U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL_WIDTH 16U
-#define LPDDR4__PI_WDQLVL_INTERVAL__REG DENALI_PI_71
-#define LPDDR4__PI_WDQLVL_INTERVAL__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_INTERVAL
-
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_SHIFT 16U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT_WOSET 0U
-#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__REG DENALI_PI_71
-#define LPDDR4__PI_WDQLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_ON_SREF_EXIT
-
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_SHIFT 24U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WIDTH 1U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOCLR 0U
-#define LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS_WOSET 0U
-#define LPDDR4__PI_WDQLVL_DISABLE_DFS__REG DENALI_PI_71
-#define LPDDR4__PI_WDQLVL_DISABLE_DFS__FLD LPDDR4__DENALI_PI_71__PI_WDQLVL_DISABLE_DFS
-
-#define LPDDR4__DENALI_PI_72_READ_MASK 0x01010103U
-#define LPDDR4__DENALI_PI_72_WRITE_MASK 0x01010103U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS_WIDTH 2U
-#define LPDDR4__PI_WDQLVL_ERROR_STATUS__REG DENALI_PI_72
-#define LPDDR4__PI_WDQLVL_ERROR_STATUS__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_SHIFT 8U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN_WOSET 0U
-#define LPDDR4__PI_WDQLVL_OSC_EN__REG DENALI_PI_72
-#define LPDDR4__PI_WDQLVL_OSC_EN__FLD LPDDR4__DENALI_PI_72__PI_WDQLVL_OSC_EN
-
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_SHIFT 16U
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN_WOSET 0U
-#define LPDDR4__PI_DQS_OSC_PERIOD_EN__REG DENALI_PI_72
-#define LPDDR4__PI_DQS_OSC_PERIOD_EN__FLD LPDDR4__DENALI_PI_72__PI_DQS_OSC_PERIOD_EN
-
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_SHIFT 24U
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN_WOSET 0U
-#define LPDDR4__PI_PARALLEL_WDQLVL_EN__REG DENALI_PI_72
-#define LPDDR4__PI_PARALLEL_WDQLVL_EN__FLD LPDDR4__DENALI_PI_72__PI_PARALLEL_WDQLVL_EN
-
-#define LPDDR4__DENALI_PI_73_READ_MASK 0x0F1F0703U
-#define LPDDR4__DENALI_PI_73_WRITE_MASK 0x0F1F0703U
-#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_SHIFT 0U
-#define LPDDR4__DENALI_PI_73__PI_BANK_DIFF_WIDTH 2U
-#define LPDDR4__PI_BANK_DIFF__REG DENALI_PI_73
-#define LPDDR4__PI_BANK_DIFF__FLD LPDDR4__DENALI_PI_73__PI_BANK_DIFF
-
-#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_MASK 0x00000700U
-#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_SHIFT 8U
-#define LPDDR4__DENALI_PI_73__PI_ROW_DIFF_WIDTH 3U
-#define LPDDR4__PI_ROW_DIFF__REG DENALI_PI_73
-#define LPDDR4__PI_ROW_DIFF__FLD LPDDR4__DENALI_PI_73__PI_ROW_DIFF
-
-#define LPDDR4__DENALI_PI_73__PI_TCCD_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_73__PI_TCCD_SHIFT 16U
-#define LPDDR4__DENALI_PI_73__PI_TCCD_WIDTH 5U
-#define LPDDR4__PI_TCCD__REG DENALI_PI_73
-#define LPDDR4__PI_TCCD__FLD LPDDR4__DENALI_PI_73__PI_TCCD
-
-#define LPDDR4__DENALI_PI_73__PI_RESERVED5_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_73__PI_RESERVED5_SHIFT 24U
-#define LPDDR4__DENALI_PI_73__PI_RESERVED5_WIDTH 4U
-#define LPDDR4__PI_RESERVED5__REG DENALI_PI_73
-#define LPDDR4__PI_RESERVED5__FLD LPDDR4__DENALI_PI_73__PI_RESERVED5
-
-#define LPDDR4__DENALI_PI_74_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_74_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_74__PI_RESERVED6_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_74__PI_RESERVED6_SHIFT 0U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED6_WIDTH 4U
-#define LPDDR4__PI_RESERVED6__REG DENALI_PI_74
-#define LPDDR4__PI_RESERVED6__FLD LPDDR4__DENALI_PI_74__PI_RESERVED6
-
-#define LPDDR4__DENALI_PI_74__PI_RESERVED7_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED7_SHIFT 8U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED7_WIDTH 4U
-#define LPDDR4__PI_RESERVED7__REG DENALI_PI_74
-#define LPDDR4__PI_RESERVED7__FLD LPDDR4__DENALI_PI_74__PI_RESERVED7
-
-#define LPDDR4__DENALI_PI_74__PI_RESERVED8_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED8_SHIFT 16U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED8_WIDTH 4U
-#define LPDDR4__PI_RESERVED8__REG DENALI_PI_74
-#define LPDDR4__PI_RESERVED8__FLD LPDDR4__DENALI_PI_74__PI_RESERVED8
-
-#define LPDDR4__DENALI_PI_74__PI_RESERVED9_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED9_SHIFT 24U
-#define LPDDR4__DENALI_PI_74__PI_RESERVED9_WIDTH 4U
-#define LPDDR4__PI_RESERVED9__REG DENALI_PI_74
-#define LPDDR4__PI_RESERVED9__FLD LPDDR4__DENALI_PI_74__PI_RESERVED9
-
-#define LPDDR4__DENALI_PI_75_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_75_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_75__PI_RESERVED10_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_75__PI_RESERVED10_SHIFT 0U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED10_WIDTH 4U
-#define LPDDR4__PI_RESERVED10__REG DENALI_PI_75
-#define LPDDR4__PI_RESERVED10__FLD LPDDR4__DENALI_PI_75__PI_RESERVED10
-
-#define LPDDR4__DENALI_PI_75__PI_RESERVED11_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED11_SHIFT 8U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED11_WIDTH 4U
-#define LPDDR4__PI_RESERVED11__REG DENALI_PI_75
-#define LPDDR4__PI_RESERVED11__FLD LPDDR4__DENALI_PI_75__PI_RESERVED11
-
-#define LPDDR4__DENALI_PI_75__PI_RESERVED12_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED12_SHIFT 16U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED12_WIDTH 4U
-#define LPDDR4__PI_RESERVED12__REG DENALI_PI_75
-#define LPDDR4__PI_RESERVED12__FLD LPDDR4__DENALI_PI_75__PI_RESERVED12
-
-#define LPDDR4__DENALI_PI_75__PI_RESERVED13_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED13_SHIFT 24U
-#define LPDDR4__DENALI_PI_75__PI_RESERVED13_WIDTH 4U
-#define LPDDR4__PI_RESERVED13__REG DENALI_PI_75
-#define LPDDR4__PI_RESERVED13__FLD LPDDR4__DENALI_PI_75__PI_RESERVED13
-
-#define LPDDR4__DENALI_PI_76_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_76_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_76__PI_RESERVED14_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_76__PI_RESERVED14_SHIFT 0U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED14_WIDTH 4U
-#define LPDDR4__PI_RESERVED14__REG DENALI_PI_76
-#define LPDDR4__PI_RESERVED14__FLD LPDDR4__DENALI_PI_76__PI_RESERVED14
-
-#define LPDDR4__DENALI_PI_76__PI_RESERVED15_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED15_SHIFT 8U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED15_WIDTH 4U
-#define LPDDR4__PI_RESERVED15__REG DENALI_PI_76
-#define LPDDR4__PI_RESERVED15__FLD LPDDR4__DENALI_PI_76__PI_RESERVED15
-
-#define LPDDR4__DENALI_PI_76__PI_RESERVED16_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED16_SHIFT 16U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED16_WIDTH 4U
-#define LPDDR4__PI_RESERVED16__REG DENALI_PI_76
-#define LPDDR4__PI_RESERVED16__FLD LPDDR4__DENALI_PI_76__PI_RESERVED16
-
-#define LPDDR4__DENALI_PI_76__PI_RESERVED17_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED17_SHIFT 24U
-#define LPDDR4__DENALI_PI_76__PI_RESERVED17_WIDTH 4U
-#define LPDDR4__PI_RESERVED17__REG DENALI_PI_76
-#define LPDDR4__PI_RESERVED17__FLD LPDDR4__DENALI_PI_76__PI_RESERVED17
-
-#define LPDDR4__DENALI_PI_77_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_77_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_77__PI_RESERVED18_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_77__PI_RESERVED18_SHIFT 0U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED18_WIDTH 4U
-#define LPDDR4__PI_RESERVED18__REG DENALI_PI_77
-#define LPDDR4__PI_RESERVED18__FLD LPDDR4__DENALI_PI_77__PI_RESERVED18
-
-#define LPDDR4__DENALI_PI_77__PI_RESERVED19_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED19_SHIFT 8U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED19_WIDTH 4U
-#define LPDDR4__PI_RESERVED19__REG DENALI_PI_77
-#define LPDDR4__PI_RESERVED19__FLD LPDDR4__DENALI_PI_77__PI_RESERVED19
-
-#define LPDDR4__DENALI_PI_77__PI_RESERVED20_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED20_SHIFT 16U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED20_WIDTH 4U
-#define LPDDR4__PI_RESERVED20__REG DENALI_PI_77
-#define LPDDR4__PI_RESERVED20__FLD LPDDR4__DENALI_PI_77__PI_RESERVED20
-
-#define LPDDR4__DENALI_PI_77__PI_RESERVED21_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED21_SHIFT 24U
-#define LPDDR4__DENALI_PI_77__PI_RESERVED21_WIDTH 4U
-#define LPDDR4__PI_RESERVED21__REG DENALI_PI_77
-#define LPDDR4__PI_RESERVED21__FLD LPDDR4__DENALI_PI_77__PI_RESERVED21
-
-#define LPDDR4__DENALI_PI_78_READ_MASK 0x000F0F0FU
-#define LPDDR4__DENALI_PI_78_WRITE_MASK 0x000F0F0FU
-#define LPDDR4__DENALI_PI_78__PI_RESERVED22_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_78__PI_RESERVED22_SHIFT 0U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED22_WIDTH 4U
-#define LPDDR4__PI_RESERVED22__REG DENALI_PI_78
-#define LPDDR4__PI_RESERVED22__FLD LPDDR4__DENALI_PI_78__PI_RESERVED22
-
-#define LPDDR4__DENALI_PI_78__PI_RESERVED23_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED23_SHIFT 8U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED23_WIDTH 4U
-#define LPDDR4__PI_RESERVED23__REG DENALI_PI_78
-#define LPDDR4__PI_RESERVED23__FLD LPDDR4__DENALI_PI_78__PI_RESERVED23
-
-#define LPDDR4__DENALI_PI_78__PI_RESERVED24_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED24_SHIFT 16U
-#define LPDDR4__DENALI_PI_78__PI_RESERVED24_WIDTH 4U
-#define LPDDR4__PI_RESERVED24__REG DENALI_PI_78
-#define LPDDR4__PI_RESERVED24__FLD LPDDR4__DENALI_PI_78__PI_RESERVED24
-
-#define LPDDR4__DENALI_PI_79_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_79_WRITE_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_PI_79__PI_INT_STATUS_WIDTH 28U
-#define LPDDR4__PI_INT_STATUS__REG DENALI_PI_79
-#define LPDDR4__PI_INT_STATUS__FLD LPDDR4__DENALI_PI_79__PI_INT_STATUS
-
-#define LPDDR4__DENALI_PI_80__PI_INT_ACK_MASK 0x07FFFFFFU
-#define LPDDR4__DENALI_PI_80__PI_INT_ACK_SHIFT 0U
-#define LPDDR4__DENALI_PI_80__PI_INT_ACK_WIDTH 27U
-#define LPDDR4__PI_INT_ACK__REG DENALI_PI_80
-#define LPDDR4__PI_INT_ACK__FLD LPDDR4__DENALI_PI_80__PI_INT_ACK
-
-#define LPDDR4__DENALI_PI_81_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_81_WRITE_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_81__PI_INT_MASK_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_81__PI_INT_MASK_SHIFT 0U
-#define LPDDR4__DENALI_PI_81__PI_INT_MASK_WIDTH 28U
-#define LPDDR4__PI_INT_MASK__REG DENALI_PI_81
-#define LPDDR4__PI_INT_MASK__FLD LPDDR4__DENALI_PI_81__PI_INT_MASK
-
-#define LPDDR4__DENALI_PI_82_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_82_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0_WIDTH 32U
-#define LPDDR4__PI_BIST_EXP_DATA_0__REG DENALI_PI_82
-#define LPDDR4__PI_BIST_EXP_DATA_0__FLD LPDDR4__DENALI_PI_82__PI_BIST_EXP_DATA_0
-
-#define LPDDR4__DENALI_PI_83_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_83_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1_WIDTH 32U
-#define LPDDR4__PI_BIST_EXP_DATA_1__REG DENALI_PI_83
-#define LPDDR4__PI_BIST_EXP_DATA_1__FLD LPDDR4__DENALI_PI_83__PI_BIST_EXP_DATA_1
-
-#define LPDDR4__DENALI_PI_84_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_84_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2_WIDTH 32U
-#define LPDDR4__PI_BIST_EXP_DATA_2__REG DENALI_PI_84
-#define LPDDR4__PI_BIST_EXP_DATA_2__FLD LPDDR4__DENALI_PI_84__PI_BIST_EXP_DATA_2
-
-#define LPDDR4__DENALI_PI_85_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_85_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3_WIDTH 32U
-#define LPDDR4__PI_BIST_EXP_DATA_3__REG DENALI_PI_85
-#define LPDDR4__PI_BIST_EXP_DATA_3__FLD LPDDR4__DENALI_PI_85__PI_BIST_EXP_DATA_3
-
-#define LPDDR4__DENALI_PI_86_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_86_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0_WIDTH 32U
-#define LPDDR4__PI_BIST_FAIL_DATA_0__REG DENALI_PI_86
-#define LPDDR4__PI_BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_PI_86__PI_BIST_FAIL_DATA_0
-
-#define LPDDR4__DENALI_PI_87_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_87_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1_WIDTH 32U
-#define LPDDR4__PI_BIST_FAIL_DATA_1__REG DENALI_PI_87
-#define LPDDR4__PI_BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_PI_87__PI_BIST_FAIL_DATA_1
-
-#define LPDDR4__DENALI_PI_88_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_88_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2_WIDTH 32U
-#define LPDDR4__PI_BIST_FAIL_DATA_2__REG DENALI_PI_88
-#define LPDDR4__PI_BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_PI_88__PI_BIST_FAIL_DATA_2
-
-#define LPDDR4__DENALI_PI_89_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_89_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3_WIDTH 32U
-#define LPDDR4__PI_BIST_FAIL_DATA_3__REG DENALI_PI_89
-#define LPDDR4__PI_BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_PI_89__PI_BIST_FAIL_DATA_3
-
-#define LPDDR4__DENALI_PI_90_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_90_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0_WIDTH 32U
-#define LPDDR4__PI_BIST_FAIL_ADDR_0__REG DENALI_PI_90
-#define LPDDR4__PI_BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_PI_90__PI_BIST_FAIL_ADDR_0
-
-#define LPDDR4__DENALI_PI_91_READ_MASK 0x011F1F07U
-#define LPDDR4__DENALI_PI_91_WRITE_MASK 0x011F1F07U
-#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_MASK 0x00000007U
-#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1_WIDTH 3U
-#define LPDDR4__PI_BIST_FAIL_ADDR_1__REG DENALI_PI_91
-#define LPDDR4__PI_BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_PI_91__PI_BIST_FAIL_ADDR_1
-
-#define LPDDR4__DENALI_PI_91__PI_BSTLEN_MASK 0x00001F00U
-#define LPDDR4__DENALI_PI_91__PI_BSTLEN_SHIFT 8U
-#define LPDDR4__DENALI_PI_91__PI_BSTLEN_WIDTH 5U
-#define LPDDR4__PI_BSTLEN__REG DENALI_PI_91
-#define LPDDR4__PI_BSTLEN__FLD LPDDR4__DENALI_PI_91__PI_BSTLEN
-
-#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_SHIFT 16U
-#define LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK_WIDTH 5U
-#define LPDDR4__PI_LONG_COUNT_MASK__REG DENALI_PI_91
-#define LPDDR4__PI_LONG_COUNT_MASK__FLD LPDDR4__DENALI_PI_91__PI_LONG_COUNT_MASK
-
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_SHIFT 24U
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN_WOSET 0U
-#define LPDDR4__PI_CMD_SWAP_EN__REG DENALI_PI_91
-#define LPDDR4__PI_CMD_SWAP_EN__FLD LPDDR4__DENALI_PI_91__PI_CMD_SWAP_EN
-
-#define LPDDR4__DENALI_PI_92_READ_MASK 0x03030301U
-#define LPDDR4__DENALI_PI_92_WRITE_MASK 0x03030301U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_SHIFT 0U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN_WOSET 0U
-#define LPDDR4__PI_DATA_BYTE_SWAP_EN__REG DENALI_PI_92
-#define LPDDR4__PI_DATA_BYTE_SWAP_EN__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_EN
-
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_SHIFT 8U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0_WIDTH 2U
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__REG DENALI_PI_92
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE0__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE0
-
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_SHIFT 16U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1_WIDTH 2U
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__REG DENALI_PI_92
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE1__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE1
-
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_SHIFT 24U
-#define LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2_WIDTH 2U
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__REG DENALI_PI_92
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE2__FLD LPDDR4__DENALI_PI_92__PI_DATA_BYTE_SWAP_SLICE2
-
-#define LPDDR4__DENALI_PI_93_READ_MASK 0x03FF0103U
-#define LPDDR4__DENALI_PI_93_WRITE_MASK 0x03FF0103U
-#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_SHIFT 0U
-#define LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3_WIDTH 2U
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__REG DENALI_PI_93
-#define LPDDR4__PI_DATA_BYTE_SWAP_SLICE3__FLD LPDDR4__DENALI_PI_93__PI_DATA_BYTE_SWAP_SLICE3
-
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_SHIFT 8U
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN_WOSET 0U
-#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__REG DENALI_PI_93
-#define LPDDR4__PI_CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_PI_93__PI_CTRLUPD_REQ_PER_AREF_EN
-
-#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_SHIFT 16U
-#define LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN_WIDTH 8U
-#define LPDDR4__PI_TDFI_CTRLUPD_MIN__REG DENALI_PI_93
-#define LPDDR4__PI_TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_PI_93__PI_TDFI_CTRLUPD_MIN
-
-#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_SHIFT 24U
-#define LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS_WIDTH 2U
-#define LPDDR4__PI_UPDATE_ERROR_STATUS__REG DENALI_PI_93
-#define LPDDR4__PI_UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_PI_93__PI_UPDATE_ERROR_STATUS
-
-#define LPDDR4__DENALI_PI_94_READ_MASK 0x013F0301U
-#define LPDDR4__DENALI_PI_94_WRITE_MASK 0x013F0301U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_SHIFT 0U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WIDTH 1U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOCLR 0U
-#define LPDDR4__DENALI_PI_94__PI_BIST_GO_WOSET 0U
-#define LPDDR4__PI_BIST_GO__REG DENALI_PI_94
-#define LPDDR4__PI_BIST_GO__FLD LPDDR4__DENALI_PI_94__PI_BIST_GO
-
-#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_SHIFT 8U
-#define LPDDR4__DENALI_PI_94__PI_BIST_RESULT_WIDTH 2U
-#define LPDDR4__PI_BIST_RESULT__REG DENALI_PI_94
-#define LPDDR4__PI_BIST_RESULT__FLD LPDDR4__DENALI_PI_94__PI_BIST_RESULT
-
-#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_MASK 0x003F0000U
-#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_SHIFT 16U
-#define LPDDR4__DENALI_PI_94__PI_ADDR_SPACE_WIDTH 6U
-#define LPDDR4__PI_ADDR_SPACE__REG DENALI_PI_94
-#define LPDDR4__PI_ADDR_SPACE__FLD LPDDR4__DENALI_PI_94__PI_ADDR_SPACE
-
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_SHIFT 24U
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WIDTH 1U
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOCLR 0U
-#define LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK_WOSET 0U
-#define LPDDR4__PI_BIST_DATA_CHECK__REG DENALI_PI_94
-#define LPDDR4__PI_BIST_DATA_CHECK__FLD LPDDR4__DENALI_PI_94__PI_BIST_DATA_CHECK
-
-#define LPDDR4__DENALI_PI_95_READ_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_95_WRITE_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_SHIFT 0U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WIDTH 1U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOCLR 0U
-#define LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK_WOSET 0U
-#define LPDDR4__PI_BIST_ADDR_CHECK__REG DENALI_PI_95
-#define LPDDR4__PI_BIST_ADDR_CHECK__FLD LPDDR4__DENALI_PI_95__PI_BIST_ADDR_CHECK
-
-#define LPDDR4__DENALI_PI_96_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_96_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0_WIDTH 32U
-#define LPDDR4__PI_BIST_START_ADDRESS_0__REG DENALI_PI_96
-#define LPDDR4__PI_BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_PI_96__PI_BIST_START_ADDRESS_0
-
-#define LPDDR4__DENALI_PI_97_READ_MASK 0x0000FF07U
-#define LPDDR4__DENALI_PI_97_WRITE_MASK 0x0000FF07U
-#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_MASK 0x00000007U
-#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1_WIDTH 3U
-#define LPDDR4__PI_BIST_START_ADDRESS_1__REG DENALI_PI_97
-#define LPDDR4__PI_BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_PI_97__PI_BIST_START_ADDRESS_1
-
-#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_SHIFT 8U
-#define LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN_WIDTH 8U
-#define LPDDR4__PI_MBIST_INIT_PATTERN__REG DENALI_PI_97
-#define LPDDR4__PI_MBIST_INIT_PATTERN__FLD LPDDR4__DENALI_PI_97__PI_MBIST_INIT_PATTERN
-
-#define LPDDR4__DENALI_PI_98_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_98_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0_WIDTH 32U
-#define LPDDR4__PI_BIST_DATA_MASK_0__REG DENALI_PI_98
-#define LPDDR4__PI_BIST_DATA_MASK_0__FLD LPDDR4__DENALI_PI_98__PI_BIST_DATA_MASK_0
-
-#define LPDDR4__DENALI_PI_99_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_99_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1_WIDTH 32U
-#define LPDDR4__PI_BIST_DATA_MASK_1__REG DENALI_PI_99
-#define LPDDR4__PI_BIST_DATA_MASK_1__FLD LPDDR4__DENALI_PI_99__PI_BIST_DATA_MASK_1
-
-#define LPDDR4__DENALI_PI_100_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_100_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_SHIFT 0U
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT_WIDTH 12U
-#define LPDDR4__PI_BIST_ERR_COUNT__REG DENALI_PI_100
-#define LPDDR4__PI_BIST_ERR_COUNT__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_COUNT
-
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_SHIFT 16U
-#define LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP_WIDTH 12U
-#define LPDDR4__PI_BIST_ERR_STOP__REG DENALI_PI_100
-#define LPDDR4__PI_BIST_ERR_STOP__FLD LPDDR4__DENALI_PI_100__PI_BIST_ERR_STOP
-
-#define LPDDR4__DENALI_PI_101_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_101_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_0_0__REG DENALI_PI_101
-#define LPDDR4__PI_BIST_ADDR_MASK_0_0__FLD LPDDR4__DENALI_PI_101__PI_BIST_ADDR_MASK_0_0
-
-#define LPDDR4__DENALI_PI_102_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_102_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_0_1__REG DENALI_PI_102
-#define LPDDR4__PI_BIST_ADDR_MASK_0_1__FLD LPDDR4__DENALI_PI_102__PI_BIST_ADDR_MASK_0_1
-
-#define LPDDR4__DENALI_PI_103_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_103_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_1_0__REG DENALI_PI_103
-#define LPDDR4__PI_BIST_ADDR_MASK_1_0__FLD LPDDR4__DENALI_PI_103__PI_BIST_ADDR_MASK_1_0
-
-#define LPDDR4__DENALI_PI_104_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_104_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_1_1__REG DENALI_PI_104
-#define LPDDR4__PI_BIST_ADDR_MASK_1_1__FLD LPDDR4__DENALI_PI_104__PI_BIST_ADDR_MASK_1_1
-
-#define LPDDR4__DENALI_PI_105_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_105_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_2_0__REG DENALI_PI_105
-#define LPDDR4__PI_BIST_ADDR_MASK_2_0__FLD LPDDR4__DENALI_PI_105__PI_BIST_ADDR_MASK_2_0
-
-#define LPDDR4__DENALI_PI_106_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_106_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_2_1__REG DENALI_PI_106
-#define LPDDR4__PI_BIST_ADDR_MASK_2_1__FLD LPDDR4__DENALI_PI_106__PI_BIST_ADDR_MASK_2_1
-
-#define LPDDR4__DENALI_PI_107_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_107_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_3_0__REG DENALI_PI_107
-#define LPDDR4__PI_BIST_ADDR_MASK_3_0__FLD LPDDR4__DENALI_PI_107__PI_BIST_ADDR_MASK_3_0
-
-#define LPDDR4__DENALI_PI_108_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_108_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_3_1__REG DENALI_PI_108
-#define LPDDR4__PI_BIST_ADDR_MASK_3_1__FLD LPDDR4__DENALI_PI_108__PI_BIST_ADDR_MASK_3_1
-
-#define LPDDR4__DENALI_PI_109_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_109_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_4_0__REG DENALI_PI_109
-#define LPDDR4__PI_BIST_ADDR_MASK_4_0__FLD LPDDR4__DENALI_PI_109__PI_BIST_ADDR_MASK_4_0
-
-#define LPDDR4__DENALI_PI_110_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_110_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_4_1__REG DENALI_PI_110
-#define LPDDR4__PI_BIST_ADDR_MASK_4_1__FLD LPDDR4__DENALI_PI_110__PI_BIST_ADDR_MASK_4_1
-
-#define LPDDR4__DENALI_PI_111_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_111_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_5_0__REG DENALI_PI_111
-#define LPDDR4__PI_BIST_ADDR_MASK_5_0__FLD LPDDR4__DENALI_PI_111__PI_BIST_ADDR_MASK_5_0
-
-#define LPDDR4__DENALI_PI_112_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_112_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_5_1__REG DENALI_PI_112
-#define LPDDR4__PI_BIST_ADDR_MASK_5_1__FLD LPDDR4__DENALI_PI_112__PI_BIST_ADDR_MASK_5_1
-
-#define LPDDR4__DENALI_PI_113_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_113_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_6_0__REG DENALI_PI_113
-#define LPDDR4__PI_BIST_ADDR_MASK_6_0__FLD LPDDR4__DENALI_PI_113__PI_BIST_ADDR_MASK_6_0
-
-#define LPDDR4__DENALI_PI_114_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_114_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_6_1__REG DENALI_PI_114
-#define LPDDR4__PI_BIST_ADDR_MASK_6_1__FLD LPDDR4__DENALI_PI_114__PI_BIST_ADDR_MASK_6_1
-
-#define LPDDR4__DENALI_PI_115_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_115_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_7_0__REG DENALI_PI_115
-#define LPDDR4__PI_BIST_ADDR_MASK_7_0__FLD LPDDR4__DENALI_PI_115__PI_BIST_ADDR_MASK_7_0
-
-#define LPDDR4__DENALI_PI_116_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_116_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_7_1__REG DENALI_PI_116
-#define LPDDR4__PI_BIST_ADDR_MASK_7_1__FLD LPDDR4__DENALI_PI_116__PI_BIST_ADDR_MASK_7_1
-
-#define LPDDR4__DENALI_PI_117_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_117_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_8_0__REG DENALI_PI_117
-#define LPDDR4__PI_BIST_ADDR_MASK_8_0__FLD LPDDR4__DENALI_PI_117__PI_BIST_ADDR_MASK_8_0
-
-#define LPDDR4__DENALI_PI_118_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_118_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_8_1__REG DENALI_PI_118
-#define LPDDR4__PI_BIST_ADDR_MASK_8_1__FLD LPDDR4__DENALI_PI_118__PI_BIST_ADDR_MASK_8_1
-
-#define LPDDR4__DENALI_PI_119_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_119_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0_WIDTH 32U
-#define LPDDR4__PI_BIST_ADDR_MASK_9_0__REG DENALI_PI_119
-#define LPDDR4__PI_BIST_ADDR_MASK_9_0__FLD LPDDR4__DENALI_PI_119__PI_BIST_ADDR_MASK_9_0
-
-#define LPDDR4__DENALI_PI_120_READ_MASK 0x0303070FU
-#define LPDDR4__DENALI_PI_120_WRITE_MASK 0x0303070FU
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1_WIDTH 4U
-#define LPDDR4__PI_BIST_ADDR_MASK_9_1__REG DENALI_PI_120
-#define LPDDR4__PI_BIST_ADDR_MASK_9_1__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MASK_9_1
-
-#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_MASK 0x00000700U
-#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_SHIFT 8U
-#define LPDDR4__DENALI_PI_120__PI_BIST_MODE_WIDTH 3U
-#define LPDDR4__PI_BIST_MODE__REG DENALI_PI_120
-#define LPDDR4__PI_BIST_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_MODE
-
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_SHIFT 16U
-#define LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE_WIDTH 2U
-#define LPDDR4__PI_BIST_ADDR_MODE__REG DENALI_PI_120
-#define LPDDR4__PI_BIST_ADDR_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_ADDR_MODE
-
-#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_SHIFT 24U
-#define LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE_WIDTH 2U
-#define LPDDR4__PI_BIST_PAT_MODE__REG DENALI_PI_120
-#define LPDDR4__PI_BIST_PAT_MODE__FLD LPDDR4__DENALI_PI_120__PI_BIST_PAT_MODE
-
-#define LPDDR4__DENALI_PI_121_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_121_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0_WIDTH 32U
-#define LPDDR4__PI_BIST_USER_PAT_0__REG DENALI_PI_121
-#define LPDDR4__PI_BIST_USER_PAT_0__FLD LPDDR4__DENALI_PI_121__PI_BIST_USER_PAT_0
-
-#define LPDDR4__DENALI_PI_122_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_122_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1_WIDTH 32U
-#define LPDDR4__PI_BIST_USER_PAT_1__REG DENALI_PI_122
-#define LPDDR4__PI_BIST_USER_PAT_1__FLD LPDDR4__DENALI_PI_122__PI_BIST_USER_PAT_1
-
-#define LPDDR4__DENALI_PI_123_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_123_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2_WIDTH 32U
-#define LPDDR4__PI_BIST_USER_PAT_2__REG DENALI_PI_123
-#define LPDDR4__PI_BIST_USER_PAT_2__FLD LPDDR4__DENALI_PI_123__PI_BIST_USER_PAT_2
-
-#define LPDDR4__DENALI_PI_124_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_124_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3_WIDTH 32U
-#define LPDDR4__PI_BIST_USER_PAT_3__REG DENALI_PI_124
-#define LPDDR4__PI_BIST_USER_PAT_3__FLD LPDDR4__DENALI_PI_124__PI_BIST_USER_PAT_3
-
-#define LPDDR4__DENALI_PI_125_READ_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_125_WRITE_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_SHIFT 0U
-#define LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM_WIDTH 4U
-#define LPDDR4__PI_BIST_PAT_NUM__REG DENALI_PI_125
-#define LPDDR4__PI_BIST_PAT_NUM__FLD LPDDR4__DENALI_PI_125__PI_BIST_PAT_NUM
-
-#define LPDDR4__DENALI_PI_126_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_126_WRITE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0_WIDTH 30U
-#define LPDDR4__PI_BIST_STAGE_0__REG DENALI_PI_126
-#define LPDDR4__PI_BIST_STAGE_0__FLD LPDDR4__DENALI_PI_126__PI_BIST_STAGE_0
-
-#define LPDDR4__DENALI_PI_127_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_127_WRITE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1_WIDTH 30U
-#define LPDDR4__PI_BIST_STAGE_1__REG DENALI_PI_127
-#define LPDDR4__PI_BIST_STAGE_1__FLD LPDDR4__DENALI_PI_127__PI_BIST_STAGE_1
-
-#define LPDDR4__DENALI_PI_128_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_128_WRITE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2_WIDTH 30U
-#define LPDDR4__PI_BIST_STAGE_2__REG DENALI_PI_128
-#define LPDDR4__PI_BIST_STAGE_2__FLD LPDDR4__DENALI_PI_128__PI_BIST_STAGE_2
-
-#define LPDDR4__DENALI_PI_129_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_129_WRITE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3_WIDTH 30U
-#define LPDDR4__PI_BIST_STAGE_3__REG DENALI_PI_129
-#define LPDDR4__PI_BIST_STAGE_3__FLD LPDDR4__DENALI_PI_129__PI_BIST_STAGE_3
-
-#define LPDDR4__DENALI_PI_130_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_130_WRITE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_SHIFT 0U
-#define LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4_WIDTH 30U
-#define LPDDR4__PI_BIST_STAGE_4__REG DENALI_PI_130
-#define LPDDR4__PI_BIST_STAGE_4__FLD LPDDR4__DENALI_PI_130__PI_BIST_STAGE_4
-
-#define LPDDR4__DENALI_PI_131_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_131_WRITE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_SHIFT 0U
-#define LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5_WIDTH 30U
-#define LPDDR4__PI_BIST_STAGE_5__REG DENALI_PI_131
-#define LPDDR4__PI_BIST_STAGE_5__FLD LPDDR4__DENALI_PI_131__PI_BIST_STAGE_5
-
-#define LPDDR4__DENALI_PI_132_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_132_WRITE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_SHIFT 0U
-#define LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6_WIDTH 30U
-#define LPDDR4__PI_BIST_STAGE_6__REG DENALI_PI_132
-#define LPDDR4__PI_BIST_STAGE_6__FLD LPDDR4__DENALI_PI_132__PI_BIST_STAGE_6
-
-#define LPDDR4__DENALI_PI_133_READ_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_133_WRITE_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_MASK 0x3FFFFFFFU
-#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_SHIFT 0U
-#define LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7_WIDTH 30U
-#define LPDDR4__PI_BIST_STAGE_7__REG DENALI_PI_133
-#define LPDDR4__PI_BIST_STAGE_7__FLD LPDDR4__DENALI_PI_133__PI_BIST_STAGE_7
-
-#define LPDDR4__DENALI_PI_134_READ_MASK 0x0101010FU
-#define LPDDR4__DENALI_PI_134_WRITE_MASK 0x0101010FU
-#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_SHIFT 0U
-#define LPDDR4__DENALI_PI_134__PI_COL_DIFF_WIDTH 4U
-#define LPDDR4__PI_COL_DIFF__REG DENALI_PI_134
-#define LPDDR4__PI_COL_DIFF__FLD LPDDR4__DENALI_PI_134__PI_COL_DIFF
-
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_SHIFT 8U
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN_WOSET 0U
-#define LPDDR4__PI_SELF_REFRESH_EN__REG DENALI_PI_134
-#define LPDDR4__PI_SELF_REFRESH_EN__FLD LPDDR4__DENALI_PI_134__PI_SELF_REFRESH_EN
-
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_SHIFT 16U
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT_WOSET 0U
-#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__REG DENALI_PI_134
-#define LPDDR4__PI_PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_PI_134__PI_PWRUP_SREFRESH_EXIT
-
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_SHIFT 24U
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WIDTH 1U
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOCLR 0U
-#define LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH_WOSET 0U
-#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__REG DENALI_PI_134
-#define LPDDR4__PI_SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_PI_134__PI_SREFRESH_EXIT_NO_REFRESH
-
-#define LPDDR4__DENALI_PI_135_READ_MASK 0x01010100U
-#define LPDDR4__DENALI_PI_135_WRITE_MASK 0x01010100U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_SHIFT 0U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WIDTH 1U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOCLR 0U
-#define LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ_WOSET 0U
-#define LPDDR4__PI_SREF_ENTRY_REQ__REG DENALI_PI_135
-#define LPDDR4__PI_SREF_ENTRY_REQ__FLD LPDDR4__DENALI_PI_135__PI_SREF_ENTRY_REQ
-
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_SHIFT 8U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT_WOSET 0U
-#define LPDDR4__PI_NO_MRW_BT_INIT__REG DENALI_PI_135
-#define LPDDR4__PI_NO_MRW_BT_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_BT_INIT
-
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_SHIFT 16U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT_WOSET 0U
-#define LPDDR4__PI_NO_MRW_INIT__REG DENALI_PI_135
-#define LPDDR4__PI_NO_MRW_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_MRW_INIT
-
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_SHIFT 24U
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT_WOSET 0U
-#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__REG DENALI_PI_135
-#define LPDDR4__PI_NO_PHY_IND_TRAIN_INIT__FLD LPDDR4__DENALI_PI_135__PI_NO_PHY_IND_TRAIN_INIT
-
-#define LPDDR4__DENALI_PI_136_READ_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_136_WRITE_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_SHIFT 0U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT_WOSET 0U
-#define LPDDR4__PI_NO_AUTO_MRR_INIT__REG DENALI_PI_136
-#define LPDDR4__PI_NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_PI_136__PI_NO_AUTO_MRR_INIT
-
-#define LPDDR4__DENALI_PI_137_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_137_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_SHIFT 0U
-#define LPDDR4__DENALI_PI_137__PI_TRST_PWRON_WIDTH 32U
-#define LPDDR4__PI_TRST_PWRON__REG DENALI_PI_137
-#define LPDDR4__PI_TRST_PWRON__FLD LPDDR4__DENALI_PI_137__PI_TRST_PWRON
-
-#define LPDDR4__DENALI_PI_138_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_138_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_SHIFT 0U
-#define LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE_WIDTH 32U
-#define LPDDR4__PI_CKE_INACTIVE__REG DENALI_PI_138
-#define LPDDR4__PI_CKE_INACTIVE__FLD LPDDR4__DENALI_PI_138__PI_CKE_INACTIVE
-
-#define LPDDR4__DENALI_PI_139_READ_MASK 0xFFFF0101U
-#define LPDDR4__DENALI_PI_139_WRITE_MASK 0xFFFF0101U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_SHIFT 0U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WIDTH 1U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOCLR 0U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_WOSET 0U
-#define LPDDR4__PI_DLL_RST__REG DENALI_PI_139
-#define LPDDR4__PI_DLL_RST__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST
-
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_SHIFT 8U
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN_WOSET 0U
-#define LPDDR4__PI_DRAM_INIT_EN__REG DENALI_PI_139
-#define LPDDR4__PI_DRAM_INIT_EN__FLD LPDDR4__DENALI_PI_139__PI_DRAM_INIT_EN
-
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_SHIFT 16U
-#define LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY_WIDTH 16U
-#define LPDDR4__PI_DLL_RST_DELAY__REG DENALI_PI_139
-#define LPDDR4__PI_DLL_RST_DELAY__FLD LPDDR4__DENALI_PI_139__PI_DLL_RST_DELAY
-
-#define LPDDR4__DENALI_PI_140_READ_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_140_WRITE_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_SHIFT 0U
-#define LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY_WIDTH 8U
-#define LPDDR4__PI_DLL_RST_ADJ_DLY__REG DENALI_PI_140
-#define LPDDR4__PI_DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_PI_140__PI_DLL_RST_ADJ_DLY
-
-#define LPDDR4__DENALI_PI_141_READ_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PI_141_WRITE_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_SHIFT 0U
-#define LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG_WIDTH 26U
-#define LPDDR4__PI_WRITE_MODEREG__REG DENALI_PI_141
-#define LPDDR4__PI_WRITE_MODEREG__FLD LPDDR4__DENALI_PI_141__PI_WRITE_MODEREG
-
-#define LPDDR4__DENALI_PI_142_READ_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_PI_142_WRITE_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_SHIFT 0U
-#define LPDDR4__DENALI_PI_142__PI_MRW_STATUS_WIDTH 8U
-#define LPDDR4__PI_MRW_STATUS__REG DENALI_PI_142
-#define LPDDR4__PI_MRW_STATUS__FLD LPDDR4__DENALI_PI_142__PI_MRW_STATUS
-
-#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_MASK 0x01FFFF00U
-#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_SHIFT 8U
-#define LPDDR4__DENALI_PI_142__PI_READ_MODEREG_WIDTH 17U
-#define LPDDR4__PI_READ_MODEREG__REG DENALI_PI_142
-#define LPDDR4__PI_READ_MODEREG__FLD LPDDR4__DENALI_PI_142__PI_READ_MODEREG
-
-#define LPDDR4__DENALI_PI_143_READ_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_PI_143_WRITE_MASK 0x01FFFFFFU
-#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0_WIDTH 24U
-#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__REG DENALI_PI_143
-#define LPDDR4__PI_PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_PI_143__PI_PERIPHERAL_MRR_DATA_0
-
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_SHIFT 24U
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WIDTH 1U
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOCLR 0U
-#define LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT_WOSET 0U
-#define LPDDR4__PI_NO_ZQ_INIT__REG DENALI_PI_143
-#define LPDDR4__PI_NO_ZQ_INIT__FLD LPDDR4__DENALI_PI_143__PI_NO_ZQ_INIT
-
-#define LPDDR4__DENALI_PI_144_READ_MASK 0x0101000FU
-#define LPDDR4__DENALI_PI_144_WRITE_MASK 0x0101000FU
-#define LPDDR4__DENALI_PI_144__PI_RESERVED25_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_144__PI_RESERVED25_SHIFT 0U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED25_WIDTH 4U
-#define LPDDR4__PI_RESERVED25__REG DENALI_PI_144
-#define LPDDR4__PI_RESERVED25__FLD LPDDR4__DENALI_PI_144__PI_RESERVED25
-
-#define LPDDR4__DENALI_PI_144__PI_RESERVED26_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED26_SHIFT 8U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED26_WIDTH 4U
-#define LPDDR4__PI_RESERVED26__REG DENALI_PI_144
-#define LPDDR4__PI_RESERVED26__FLD LPDDR4__DENALI_PI_144__PI_RESERVED26
-
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_SHIFT 16U
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WIDTH 1U
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOCLR 0U
-#define LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING_WOSET 0U
-#define LPDDR4__PI_ZQ_REQ_PENDING__REG DENALI_PI_144
-#define LPDDR4__PI_ZQ_REQ_PENDING__FLD LPDDR4__DENALI_PI_144__PI_ZQ_REQ_PENDING
-
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_SHIFT 24U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WIDTH 1U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOCLR 0U
-#define LPDDR4__DENALI_PI_144__PI_RESERVED27_WOSET 0U
-#define LPDDR4__PI_RESERVED27__REG DENALI_PI_144
-#define LPDDR4__PI_RESERVED27__FLD LPDDR4__DENALI_PI_144__PI_RESERVED27
-
-#define LPDDR4__DENALI_PI_145_READ_MASK 0xFF010F07U
-#define LPDDR4__DENALI_PI_145_WRITE_MASK 0xFF010F07U
-#define LPDDR4__DENALI_PI_145__PI_RESERVED28_MASK 0x00000007U
-#define LPDDR4__DENALI_PI_145__PI_RESERVED28_SHIFT 0U
-#define LPDDR4__DENALI_PI_145__PI_RESERVED28_WIDTH 3U
-#define LPDDR4__PI_RESERVED28__REG DENALI_PI_145
-#define LPDDR4__PI_RESERVED28__FLD LPDDR4__DENALI_PI_145__PI_RESERVED28
-
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0_WIDTH 4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_0__REG DENALI_PI_145
-#define LPDDR4__PI_MONITOR_SRC_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_SRC_SEL_0
-
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WIDTH 1U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOCLR 0U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0_WOSET 0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_0__REG DENALI_PI_145
-#define LPDDR4__PI_MONITOR_CAP_SEL_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_CAP_SEL_0
-
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_145__PI_MONITOR_0_WIDTH 8U
-#define LPDDR4__PI_MONITOR_0__REG DENALI_PI_145
-#define LPDDR4__PI_MONITOR_0__FLD LPDDR4__DENALI_PI_145__PI_MONITOR_0
-
-#define LPDDR4__DENALI_PI_146_READ_MASK 0x0FFF010FU
-#define LPDDR4__DENALI_PI_146_WRITE_MASK 0x0FFF010FU
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1_WIDTH 4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_1__REG DENALI_PI_146
-#define LPDDR4__PI_MONITOR_SRC_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_1
-
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WIDTH 1U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOCLR 0U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1_WOSET 0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_1__REG DENALI_PI_146
-#define LPDDR4__PI_MONITOR_CAP_SEL_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_CAP_SEL_1
-
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_1_WIDTH 8U
-#define LPDDR4__PI_MONITOR_1__REG DENALI_PI_146
-#define LPDDR4__PI_MONITOR_1__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_1
-
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2_WIDTH 4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_2__REG DENALI_PI_146
-#define LPDDR4__PI_MONITOR_SRC_SEL_2__FLD LPDDR4__DENALI_PI_146__PI_MONITOR_SRC_SEL_2
-
-#define LPDDR4__DENALI_PI_147_READ_MASK 0x010FFF01U
-#define LPDDR4__DENALI_PI_147_WRITE_MASK 0x010FFF01U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WIDTH 1U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOCLR 0U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2_WOSET 0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_2__REG DENALI_PI_147
-#define LPDDR4__PI_MONITOR_CAP_SEL_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_2
-
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_2_WIDTH 8U
-#define LPDDR4__PI_MONITOR_2__REG DENALI_PI_147
-#define LPDDR4__PI_MONITOR_2__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_2
-
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3_WIDTH 4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_3__REG DENALI_PI_147
-#define LPDDR4__PI_MONITOR_SRC_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_SRC_SEL_3
-
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_SHIFT 24U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WIDTH 1U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOCLR 0U
-#define LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3_WOSET 0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_3__REG DENALI_PI_147
-#define LPDDR4__PI_MONITOR_CAP_SEL_3__FLD LPDDR4__DENALI_PI_147__PI_MONITOR_CAP_SEL_3
-
-#define LPDDR4__DENALI_PI_148_READ_MASK 0xFF010FFFU
-#define LPDDR4__DENALI_PI_148_WRITE_MASK 0xFF010FFFU
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_3_WIDTH 8U
-#define LPDDR4__PI_MONITOR_3__REG DENALI_PI_148
-#define LPDDR4__PI_MONITOR_3__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_3
-
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_SHIFT 8U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4_WIDTH 4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_4__REG DENALI_PI_148
-#define LPDDR4__PI_MONITOR_SRC_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_SRC_SEL_4
-
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_SHIFT 16U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WIDTH 1U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOCLR 0U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4_WOSET 0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_4__REG DENALI_PI_148
-#define LPDDR4__PI_MONITOR_CAP_SEL_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_CAP_SEL_4
-
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_SHIFT 24U
-#define LPDDR4__DENALI_PI_148__PI_MONITOR_4_WIDTH 8U
-#define LPDDR4__PI_MONITOR_4__REG DENALI_PI_148
-#define LPDDR4__PI_MONITOR_4__FLD LPDDR4__DENALI_PI_148__PI_MONITOR_4
-
-#define LPDDR4__DENALI_PI_149_READ_MASK 0x0FFF010FU
-#define LPDDR4__DENALI_PI_149_WRITE_MASK 0x0FFF010FU
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_SHIFT 0U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5_WIDTH 4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_5__REG DENALI_PI_149
-#define LPDDR4__PI_MONITOR_SRC_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_5
-
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_SHIFT 8U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WIDTH 1U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOCLR 0U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5_WOSET 0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_5__REG DENALI_PI_149
-#define LPDDR4__PI_MONITOR_CAP_SEL_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_CAP_SEL_5
-
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_SHIFT 16U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_5_WIDTH 8U
-#define LPDDR4__PI_MONITOR_5__REG DENALI_PI_149
-#define LPDDR4__PI_MONITOR_5__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_5
-
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_SHIFT 24U
-#define LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6_WIDTH 4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_6__REG DENALI_PI_149
-#define LPDDR4__PI_MONITOR_SRC_SEL_6__FLD LPDDR4__DENALI_PI_149__PI_MONITOR_SRC_SEL_6
-
-#define LPDDR4__DENALI_PI_150_READ_MASK 0x010FFF01U
-#define LPDDR4__DENALI_PI_150_WRITE_MASK 0x010FFF01U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_SHIFT 0U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WIDTH 1U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOCLR 0U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6_WOSET 0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_6__REG DENALI_PI_150
-#define LPDDR4__PI_MONITOR_CAP_SEL_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_6
-
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_SHIFT 8U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_6_WIDTH 8U
-#define LPDDR4__PI_MONITOR_6__REG DENALI_PI_150
-#define LPDDR4__PI_MONITOR_6__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_6
-
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_SHIFT 16U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7_WIDTH 4U
-#define LPDDR4__PI_MONITOR_SRC_SEL_7__REG DENALI_PI_150
-#define LPDDR4__PI_MONITOR_SRC_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_SRC_SEL_7
-
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_SHIFT 24U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WIDTH 1U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOCLR 0U
-#define LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7_WOSET 0U
-#define LPDDR4__PI_MONITOR_CAP_SEL_7__REG DENALI_PI_150
-#define LPDDR4__PI_MONITOR_CAP_SEL_7__FLD LPDDR4__DENALI_PI_150__PI_MONITOR_CAP_SEL_7
-
-#define LPDDR4__DENALI_PI_151_READ_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_151_WRITE_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_SHIFT 0U
-#define LPDDR4__DENALI_PI_151__PI_MONITOR_7_WIDTH 8U
-#define LPDDR4__PI_MONITOR_7__REG DENALI_PI_151
-#define LPDDR4__PI_MONITOR_7__FLD LPDDR4__DENALI_PI_151__PI_MONITOR_7
-
-#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_SHIFT 0U
-#define LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE_WIDTH 8U
-#define LPDDR4__PI_MONITOR_STROBE__REG DENALI_PI_152
-#define LPDDR4__PI_MONITOR_STROBE__FLD LPDDR4__DENALI_PI_152__PI_MONITOR_STROBE
-
-#define LPDDR4__DENALI_PI_153_READ_MASK 0x011F1F01U
-#define LPDDR4__DENALI_PI_153_WRITE_MASK 0x011F1F01U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_SHIFT 0U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WIDTH 1U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOCLR 0U
-#define LPDDR4__DENALI_PI_153__PI_DLL_LOCK_WOSET 0U
-#define LPDDR4__PI_DLL_LOCK__REG DENALI_PI_153
-#define LPDDR4__PI_DLL_LOCK__FLD LPDDR4__DENALI_PI_153__PI_DLL_LOCK
-
-#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_MASK 0x00001F00U
-#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_SHIFT 8U
-#define LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS_WIDTH 5U
-#define LPDDR4__PI_FREQ_NUMBER_STATUS__REG DENALI_PI_153
-#define LPDDR4__PI_FREQ_NUMBER_STATUS__FLD LPDDR4__DENALI_PI_153__PI_FREQ_NUMBER_STATUS
-
-#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_SHIFT 16U
-#define LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM_WIDTH 5U
-#define LPDDR4__PI_FREQ_RETENTION_NUM__REG DENALI_PI_153
-#define LPDDR4__PI_FREQ_RETENTION_NUM__FLD LPDDR4__DENALI_PI_153__PI_FREQ_RETENTION_NUM
-
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_SHIFT 24U
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WIDTH 1U
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOCLR 0U
-#define LPDDR4__DENALI_PI_153__PI_RESERVED29_WOSET 0U
-#define LPDDR4__PI_RESERVED29__REG DENALI_PI_153
-#define LPDDR4__PI_RESERVED29__FLD LPDDR4__DENALI_PI_153__PI_RESERVED29
-
-#define LPDDR4__DENALI_PI_154_READ_MASK 0x01010103U
-#define LPDDR4__DENALI_PI_154_WRITE_MASK 0x01010103U
-#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_SHIFT 0U
-#define LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE_WIDTH 2U
-#define LPDDR4__PI_PHYMSTR_TYPE__REG DENALI_PI_154
-#define LPDDR4__PI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_154__PI_PHYMSTR_TYPE
-
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_SHIFT 8U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WIDTH 1U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOCLR 0U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED30_WOSET 0U
-#define LPDDR4__PI_RESERVED30__REG DENALI_PI_154
-#define LPDDR4__PI_RESERVED30__FLD LPDDR4__DENALI_PI_154__PI_RESERVED30
-
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_SHIFT 16U
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN_WOSET 0U
-#define LPDDR4__PI_POWER_REDUC_EN__REG DENALI_PI_154
-#define LPDDR4__PI_POWER_REDUC_EN__FLD LPDDR4__DENALI_PI_154__PI_POWER_REDUC_EN
-
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_SHIFT 24U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WIDTH 1U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOCLR 0U
-#define LPDDR4__DENALI_PI_154__PI_RESERVED31_WOSET 0U
-#define LPDDR4__PI_RESERVED31__REG DENALI_PI_154
-#define LPDDR4__PI_RESERVED31__FLD LPDDR4__DENALI_PI_154__PI_RESERVED31
-
-#define LPDDR4__DENALI_PI_155_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_155_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_SHIFT 0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WIDTH 1U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOCLR 0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED32_WOSET 0U
-#define LPDDR4__PI_RESERVED32__REG DENALI_PI_155
-#define LPDDR4__PI_RESERVED32__FLD LPDDR4__DENALI_PI_155__PI_RESERVED32
-
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_SHIFT 8U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WIDTH 1U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOCLR 0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED33_WOSET 0U
-#define LPDDR4__PI_RESERVED33__REG DENALI_PI_155
-#define LPDDR4__PI_RESERVED33__FLD LPDDR4__DENALI_PI_155__PI_RESERVED33
-
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_SHIFT 16U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WIDTH 1U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOCLR 0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED34_WOSET 0U
-#define LPDDR4__PI_RESERVED34__REG DENALI_PI_155
-#define LPDDR4__PI_RESERVED34__FLD LPDDR4__DENALI_PI_155__PI_RESERVED34
-
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_SHIFT 24U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WIDTH 1U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOCLR 0U
-#define LPDDR4__DENALI_PI_155__PI_RESERVED35_WOSET 0U
-#define LPDDR4__PI_RESERVED35__REG DENALI_PI_155
-#define LPDDR4__PI_RESERVED35__FLD LPDDR4__DENALI_PI_155__PI_RESERVED35
-
-#define LPDDR4__DENALI_PI_156_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_156_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_SHIFT 0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WIDTH 1U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOCLR 0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED36_WOSET 0U
-#define LPDDR4__PI_RESERVED36__REG DENALI_PI_156
-#define LPDDR4__PI_RESERVED36__FLD LPDDR4__DENALI_PI_156__PI_RESERVED36
-
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_SHIFT 8U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WIDTH 1U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOCLR 0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED37_WOSET 0U
-#define LPDDR4__PI_RESERVED37__REG DENALI_PI_156
-#define LPDDR4__PI_RESERVED37__FLD LPDDR4__DENALI_PI_156__PI_RESERVED37
-
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_SHIFT 16U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WIDTH 1U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOCLR 0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED38_WOSET 0U
-#define LPDDR4__PI_RESERVED38__REG DENALI_PI_156
-#define LPDDR4__PI_RESERVED38__FLD LPDDR4__DENALI_PI_156__PI_RESERVED38
-
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_SHIFT 24U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WIDTH 1U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOCLR 0U
-#define LPDDR4__DENALI_PI_156__PI_RESERVED39_WOSET 0U
-#define LPDDR4__PI_RESERVED39__REG DENALI_PI_156
-#define LPDDR4__PI_RESERVED39__FLD LPDDR4__DENALI_PI_156__PI_RESERVED39
-
-#define LPDDR4__DENALI_PI_157_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_157_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_SHIFT 0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WIDTH 1U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOCLR 0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED40_WOSET 0U
-#define LPDDR4__PI_RESERVED40__REG DENALI_PI_157
-#define LPDDR4__PI_RESERVED40__FLD LPDDR4__DENALI_PI_157__PI_RESERVED40
-
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_SHIFT 8U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WIDTH 1U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOCLR 0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED41_WOSET 0U
-#define LPDDR4__PI_RESERVED41__REG DENALI_PI_157
-#define LPDDR4__PI_RESERVED41__FLD LPDDR4__DENALI_PI_157__PI_RESERVED41
-
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_SHIFT 16U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WIDTH 1U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOCLR 0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED42_WOSET 0U
-#define LPDDR4__PI_RESERVED42__REG DENALI_PI_157
-#define LPDDR4__PI_RESERVED42__FLD LPDDR4__DENALI_PI_157__PI_RESERVED42
-
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_SHIFT 24U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WIDTH 1U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOCLR 0U
-#define LPDDR4__DENALI_PI_157__PI_RESERVED43_WOSET 0U
-#define LPDDR4__PI_RESERVED43__REG DENALI_PI_157
-#define LPDDR4__PI_RESERVED43__FLD LPDDR4__DENALI_PI_157__PI_RESERVED43
-
-#define LPDDR4__DENALI_PI_158_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_158_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_SHIFT 0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WIDTH 1U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOCLR 0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED44_WOSET 0U
-#define LPDDR4__PI_RESERVED44__REG DENALI_PI_158
-#define LPDDR4__PI_RESERVED44__FLD LPDDR4__DENALI_PI_158__PI_RESERVED44
-
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_SHIFT 8U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WIDTH 1U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOCLR 0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED45_WOSET 0U
-#define LPDDR4__PI_RESERVED45__REG DENALI_PI_158
-#define LPDDR4__PI_RESERVED45__FLD LPDDR4__DENALI_PI_158__PI_RESERVED45
-
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_SHIFT 16U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WIDTH 1U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOCLR 0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED46_WOSET 0U
-#define LPDDR4__PI_RESERVED46__REG DENALI_PI_158
-#define LPDDR4__PI_RESERVED46__FLD LPDDR4__DENALI_PI_158__PI_RESERVED46
-
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_SHIFT 24U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WIDTH 1U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOCLR 0U
-#define LPDDR4__DENALI_PI_158__PI_RESERVED47_WOSET 0U
-#define LPDDR4__PI_RESERVED47__REG DENALI_PI_158
-#define LPDDR4__PI_RESERVED47__FLD LPDDR4__DENALI_PI_158__PI_RESERVED47
-
-#define LPDDR4__DENALI_PI_159_READ_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PI_159_WRITE_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_SHIFT 0U
-#define LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND_WIDTH 8U
-#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__REG DENALI_PI_159
-#define LPDDR4__PI_WRLVL_MAX_STROBE_PEND__FLD LPDDR4__DENALI_PI_159__PI_WRLVL_MAX_STROBE_PEND
-
-#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_MASK 0x0001FF00U
-#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_SHIFT 8U
-#define LPDDR4__DENALI_PI_159__PI_TREFBW_THR_WIDTH 9U
-#define LPDDR4__PI_TREFBW_THR__REG DENALI_PI_159
-#define LPDDR4__PI_TREFBW_THR__FLD LPDDR4__DENALI_PI_159__PI_TREFBW_THR
-
-#define LPDDR4__DENALI_PI_160_READ_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_160_WRITE_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_SHIFT 0U
-#define LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY_WIDTH 5U
-#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__REG DENALI_PI_160
-#define LPDDR4__PI_FREQ_CHANGE_REG_COPY__FLD LPDDR4__DENALI_PI_160__PI_FREQ_CHANGE_REG_COPY
-
-#define LPDDR4__DENALI_PI_161_READ_MASK 0x0F011F01U
-#define LPDDR4__DENALI_PI_161_WRITE_MASK 0x0F011F01U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_SHIFT 0U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WIDTH 1U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOCLR 0U
-#define LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF_WOSET 0U
-#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__REG DENALI_PI_161
-#define LPDDR4__PI_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PI_161__PI_FREQ_SEL_FROM_REGIF
-
-#define LPDDR4__DENALI_PI_161__PI_RESERVED48_MASK 0x00001F00U
-#define LPDDR4__DENALI_PI_161__PI_RESERVED48_SHIFT 8U
-#define LPDDR4__DENALI_PI_161__PI_RESERVED48_WIDTH 5U
-#define LPDDR4__PI_RESERVED48__REG DENALI_PI_161
-#define LPDDR4__PI_RESERVED48__FLD LPDDR4__DENALI_PI_161__PI_RESERVED48
-
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_SHIFT 16U
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WIDTH 1U
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOCLR 0U
-#define LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN_WOSET 0U
-#define LPDDR4__PI_PARALLEL_CALVL_EN__REG DENALI_PI_161
-#define LPDDR4__PI_PARALLEL_CALVL_EN__FLD LPDDR4__DENALI_PI_161__PI_PARALLEL_CALVL_EN
-
-#define LPDDR4__DENALI_PI_161__PI_CATR_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_161__PI_CATR_SHIFT 24U
-#define LPDDR4__DENALI_PI_161__PI_CATR_WIDTH 4U
-#define LPDDR4__PI_CATR__REG DENALI_PI_161
-#define LPDDR4__PI_CATR__FLD LPDDR4__DENALI_PI_161__PI_CATR
-
-#define LPDDR4__DENALI_PI_162_READ_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_162_WRITE_MASK 0x01010101U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_SHIFT 0U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WIDTH 1U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOCLR 0U
-#define LPDDR4__DENALI_PI_162__PI_NO_CATR_READ_WOSET 0U
-#define LPDDR4__PI_NO_CATR_READ__REG DENALI_PI_162
-#define LPDDR4__PI_NO_CATR_READ__FLD LPDDR4__DENALI_PI_162__PI_NO_CATR_READ
-
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_SHIFT 8U
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WIDTH 1U
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOCLR 0U
-#define LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE_WOSET 0U
-#define LPDDR4__PI_MASK_INIT_COMPLETE__REG DENALI_PI_162
-#define LPDDR4__PI_MASK_INIT_COMPLETE__FLD LPDDR4__DENALI_PI_162__PI_MASK_INIT_COMPLETE
-
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_MASK 0x00010000U
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_SHIFT 16U
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WIDTH 1U
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOCLR 0U
-#define LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC_WOSET 0U
-#define LPDDR4__PI_DISCONNECT_MC__REG DENALI_PI_162
-#define LPDDR4__PI_DISCONNECT_MC__FLD LPDDR4__DENALI_PI_162__PI_DISCONNECT_MC
-
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_SHIFT 24U
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WIDTH 1U
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOCLR 0U
-#define LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START_WOSET 0U
-#define LPDDR4__PI_NOTCARE_MC_INIT_START__REG DENALI_PI_162
-#define LPDDR4__PI_NOTCARE_MC_INIT_START__FLD LPDDR4__DENALI_PI_162__PI_NOTCARE_MC_INIT_START
-
-#define LPDDR4__DENALI_PI_163_READ_MASK 0xFFFFFF01U
-#define LPDDR4__DENALI_PI_163_WRITE_MASK 0xFFFFFF01U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_MASK 0x00000001U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_SHIFT 0U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WIDTH 1U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOCLR 0U
-#define LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13_WOSET 0U
-#define LPDDR4__PI_TRACE_MC_MR13__REG DENALI_PI_163
-#define LPDDR4__PI_TRACE_MC_MR13__FLD LPDDR4__DENALI_PI_163__PI_TRACE_MC_MR13
-
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F0_WIDTH 8U
-#define LPDDR4__PI_TSDO_F0__REG DENALI_PI_163
-#define LPDDR4__PI_TSDO_F0__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F0
-
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F1_WIDTH 8U
-#define LPDDR4__PI_TSDO_F1__REG DENALI_PI_163
-#define LPDDR4__PI_TSDO_F1__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F1
-
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_163__PI_TSDO_F2_WIDTH 8U
-#define LPDDR4__PI_TSDO_F2__REG DENALI_PI_163
-#define LPDDR4__PI_TSDO_F2__FLD LPDDR4__DENALI_PI_163__PI_TSDO_F2
-
-#define LPDDR4__DENALI_PI_164_READ_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_164_WRITE_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0_WIDTH 8U
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__REG DENALI_PI_164
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F0__FLD LPDDR4__DENALI_PI_164__PI_TDELAY_RDWR_2_BUS_IDLE_F0
-
-#define LPDDR4__DENALI_PI_165_READ_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_165_WRITE_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1_WIDTH 8U
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__REG DENALI_PI_165
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F1__FLD LPDDR4__DENALI_PI_165__PI_TDELAY_RDWR_2_BUS_IDLE_F1
-
-#define LPDDR4__DENALI_PI_166_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_166_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2_WIDTH 8U
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__REG DENALI_PI_166
-#define LPDDR4__PI_TDELAY_RDWR_2_BUS_IDLE_F2__FLD LPDDR4__DENALI_PI_166__PI_TDELAY_RDWR_2_BUS_IDLE_F2
-
-#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_MASK 0x000FFF00U
-#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_166__PI_ZQINIT_F0_WIDTH 12U
-#define LPDDR4__PI_ZQINIT_F0__REG DENALI_PI_166
-#define LPDDR4__PI_ZQINIT_F0__FLD LPDDR4__DENALI_PI_166__PI_ZQINIT_F0
-
-#define LPDDR4__DENALI_PI_167_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_167_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F1_WIDTH 12U
-#define LPDDR4__PI_ZQINIT_F1__REG DENALI_PI_167
-#define LPDDR4__PI_ZQINIT_F1__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F1
-
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_167__PI_ZQINIT_F2_WIDTH 12U
-#define LPDDR4__PI_ZQINIT_F2__REG DENALI_PI_167
-#define LPDDR4__PI_ZQINIT_F2__FLD LPDDR4__DENALI_PI_167__PI_ZQINIT_F2
-
-#define LPDDR4__DENALI_PI_168_READ_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_168_WRITE_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F0_WIDTH 7U
-#define LPDDR4__PI_WRLAT_F0__REG DENALI_PI_168
-#define LPDDR4__PI_WRLAT_F0__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F0
-
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0_WIDTH 7U
-#define LPDDR4__PI_CASLAT_LIN_F0__REG DENALI_PI_168
-#define LPDDR4__PI_CASLAT_LIN_F0__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F0
-
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_MASK 0x007F0000U
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_168__PI_WRLAT_F1_WIDTH 7U
-#define LPDDR4__PI_WRLAT_F1__REG DENALI_PI_168
-#define LPDDR4__PI_WRLAT_F1__FLD LPDDR4__DENALI_PI_168__PI_WRLAT_F1
-
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1_WIDTH 7U
-#define LPDDR4__PI_CASLAT_LIN_F1__REG DENALI_PI_168
-#define LPDDR4__PI_CASLAT_LIN_F1__FLD LPDDR4__DENALI_PI_168__PI_CASLAT_LIN_F1
-
-#define LPDDR4__DENALI_PI_169_READ_MASK 0x03FF7F7FU
-#define LPDDR4__DENALI_PI_169_WRITE_MASK 0x03FF7F7FU
-#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_169__PI_WRLAT_F2_WIDTH 7U
-#define LPDDR4__PI_WRLAT_F2__REG DENALI_PI_169
-#define LPDDR4__PI_WRLAT_F2__FLD LPDDR4__DENALI_PI_169__PI_WRLAT_F2
-
-#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2_WIDTH 7U
-#define LPDDR4__PI_CASLAT_LIN_F2__REG DENALI_PI_169
-#define LPDDR4__PI_CASLAT_LIN_F2__FLD LPDDR4__DENALI_PI_169__PI_CASLAT_LIN_F2
-
-#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_169__PI_TRFC_F0_WIDTH 10U
-#define LPDDR4__PI_TRFC_F0__REG DENALI_PI_169
-#define LPDDR4__PI_TRFC_F0__FLD LPDDR4__DENALI_PI_169__PI_TRFC_F0
-
-#define LPDDR4__DENALI_PI_170_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_170_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_170__PI_TREF_F0_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_170__PI_TREF_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_170__PI_TREF_F0_WIDTH 20U
-#define LPDDR4__PI_TREF_F0__REG DENALI_PI_170
-#define LPDDR4__PI_TREF_F0__FLD LPDDR4__DENALI_PI_170__PI_TREF_F0
-
-#define LPDDR4__DENALI_PI_171_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_171_WRITE_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_171__PI_TRFC_F1_WIDTH 10U
-#define LPDDR4__PI_TRFC_F1__REG DENALI_PI_171
-#define LPDDR4__PI_TRFC_F1__FLD LPDDR4__DENALI_PI_171__PI_TRFC_F1
-
-#define LPDDR4__DENALI_PI_172_READ_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_172_WRITE_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_172__PI_TREF_F1_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_172__PI_TREF_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_172__PI_TREF_F1_WIDTH 20U
-#define LPDDR4__PI_TREF_F1__REG DENALI_PI_172
-#define LPDDR4__PI_TREF_F1__FLD LPDDR4__DENALI_PI_172__PI_TREF_F1
-
-#define LPDDR4__DENALI_PI_173_READ_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_173_WRITE_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_173__PI_TRFC_F2_WIDTH 10U
-#define LPDDR4__PI_TRFC_F2__REG DENALI_PI_173
-#define LPDDR4__PI_TRFC_F2__FLD LPDDR4__DENALI_PI_173__PI_TRFC_F2
-
-#define LPDDR4__DENALI_PI_174_READ_MASK 0x0F0FFFFFU
-#define LPDDR4__DENALI_PI_174_WRITE_MASK 0x0F0FFFFFU
-#define LPDDR4__DENALI_PI_174__PI_TREF_F2_MASK 0x000FFFFFU
-#define LPDDR4__DENALI_PI_174__PI_TREF_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_174__PI_TREF_F2_WIDTH 20U
-#define LPDDR4__PI_TREF_F2__REG DENALI_PI_174
-#define LPDDR4__PI_TREF_F2__FLD LPDDR4__DENALI_PI_174__PI_TREF_F2
-
-#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0_WIDTH 4U
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__REG DENALI_PI_174
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_PI_174__PI_TDFI_CTRL_DELAY_F0
-
-#define LPDDR4__DENALI_PI_175_READ_MASK 0x03030F0FU
-#define LPDDR4__DENALI_PI_175_WRITE_MASK 0x03030F0FU
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1_WIDTH 4U
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__REG DENALI_PI_175
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F1
-
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2_WIDTH 4U
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__REG DENALI_PI_175
-#define LPDDR4__PI_TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_PI_175__PI_TDFI_CTRL_DELAY_F2
-
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0_WIDTH 2U
-#define LPDDR4__PI_WRLVL_EN_F0__REG DENALI_PI_175
-#define LPDDR4__PI_WRLVL_EN_F0__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F0
-
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1_WIDTH 2U
-#define LPDDR4__PI_WRLVL_EN_F1__REG DENALI_PI_175
-#define LPDDR4__PI_WRLVL_EN_F1__FLD LPDDR4__DENALI_PI_175__PI_WRLVL_EN_F1
-
-#define LPDDR4__DENALI_PI_176_READ_MASK 0x0003FF03U
-#define LPDDR4__DENALI_PI_176_WRITE_MASK 0x0003FF03U
-#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2_WIDTH 2U
-#define LPDDR4__PI_WRLVL_EN_F2__REG DENALI_PI_176
-#define LPDDR4__PI_WRLVL_EN_F2__FLD LPDDR4__DENALI_PI_176__PI_WRLVL_EN_F2
-
-#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_MASK 0x0003FF00U
-#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0_WIDTH 10U
-#define LPDDR4__PI_TDFI_WRLVL_WW_F0__REG DENALI_PI_176
-#define LPDDR4__PI_TDFI_WRLVL_WW_F0__FLD LPDDR4__DENALI_PI_176__PI_TDFI_WRLVL_WW_F0
-
-#define LPDDR4__DENALI_PI_177_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_177_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1_WIDTH 10U
-#define LPDDR4__PI_TDFI_WRLVL_WW_F1__REG DENALI_PI_177
-#define LPDDR4__PI_TDFI_WRLVL_WW_F1__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F1
-
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2_WIDTH 10U
-#define LPDDR4__PI_TDFI_WRLVL_WW_F2__REG DENALI_PI_177
-#define LPDDR4__PI_TDFI_WRLVL_WW_F2__FLD LPDDR4__DENALI_PI_177__PI_TDFI_WRLVL_WW_F2
-
-#define LPDDR4__DENALI_PI_178_READ_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PI_178_WRITE_MASK 0x01FF01FFU
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0_WIDTH 8U
-#define LPDDR4__PI_TODTL_2CMD_F0__REG DENALI_PI_178
-#define LPDDR4__PI_TODTL_2CMD_F0__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F0
-
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WIDTH 1U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOCLR 0U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F0_WOSET 0U
-#define LPDDR4__PI_ODT_EN_F0__REG DENALI_PI_178
-#define LPDDR4__PI_ODT_EN_F0__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F0
-
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1_WIDTH 8U
-#define LPDDR4__PI_TODTL_2CMD_F1__REG DENALI_PI_178
-#define LPDDR4__PI_TODTL_2CMD_F1__FLD LPDDR4__DENALI_PI_178__PI_TODTL_2CMD_F1
-
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_MASK 0x01000000U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WIDTH 1U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOCLR 0U
-#define LPDDR4__DENALI_PI_178__PI_ODT_EN_F1_WOSET 0U
-#define LPDDR4__PI_ODT_EN_F1__REG DENALI_PI_178
-#define LPDDR4__PI_ODT_EN_F1__FLD LPDDR4__DENALI_PI_178__PI_ODT_EN_F1
-
-#define LPDDR4__DENALI_PI_179_READ_MASK 0x0F0F01FFU
-#define LPDDR4__DENALI_PI_179_WRITE_MASK 0x0F0F01FFU
-#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2_WIDTH 8U
-#define LPDDR4__PI_TODTL_2CMD_F2__REG DENALI_PI_179
-#define LPDDR4__PI_TODTL_2CMD_F2__FLD LPDDR4__DENALI_PI_179__PI_TODTL_2CMD_F2
-
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_MASK 0x00000100U
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WIDTH 1U
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOCLR 0U
-#define LPDDR4__DENALI_PI_179__PI_ODT_EN_F2_WOSET 0U
-#define LPDDR4__PI_ODT_EN_F2__REG DENALI_PI_179
-#define LPDDR4__PI_ODT_EN_F2__FLD LPDDR4__DENALI_PI_179__PI_ODT_EN_F2
-
-#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_179__PI_ODTLON_F0_WIDTH 4U
-#define LPDDR4__PI_ODTLON_F0__REG DENALI_PI_179
-#define LPDDR4__PI_ODTLON_F0__FLD LPDDR4__DENALI_PI_179__PI_ODTLON_F0
-
-#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0_WIDTH 4U
-#define LPDDR4__PI_TODTON_MIN_F0__REG DENALI_PI_179
-#define LPDDR4__PI_TODTON_MIN_F0__FLD LPDDR4__DENALI_PI_179__PI_TODTON_MIN_F0
-
-#define LPDDR4__DENALI_PI_180_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_180_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F1_WIDTH 4U
-#define LPDDR4__PI_ODTLON_F1__REG DENALI_PI_180
-#define LPDDR4__PI_ODTLON_F1__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F1
-
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1_WIDTH 4U
-#define LPDDR4__PI_TODTON_MIN_F1__REG DENALI_PI_180
-#define LPDDR4__PI_TODTON_MIN_F1__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F1
-
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_180__PI_ODTLON_F2_WIDTH 4U
-#define LPDDR4__PI_ODTLON_F2__REG DENALI_PI_180
-#define LPDDR4__PI_ODTLON_F2__FLD LPDDR4__DENALI_PI_180__PI_ODTLON_F2
-
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2_WIDTH 4U
-#define LPDDR4__PI_TODTON_MIN_F2__REG DENALI_PI_180
-#define LPDDR4__PI_TODTON_MIN_F2__FLD LPDDR4__DENALI_PI_180__PI_TODTON_MIN_F2
-
-#define LPDDR4__DENALI_PI_181_READ_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_181_WRITE_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0_WIDTH 2U
-#define LPDDR4__PI_RDLVL_EN_F0__REG DENALI_PI_181
-#define LPDDR4__PI_RDLVL_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F0
-
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0_WIDTH 2U
-#define LPDDR4__PI_RDLVL_GATE_EN_F0__REG DENALI_PI_181
-#define LPDDR4__PI_RDLVL_GATE_EN_F0__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F0
-
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1_WIDTH 2U
-#define LPDDR4__PI_RDLVL_EN_F1__REG DENALI_PI_181
-#define LPDDR4__PI_RDLVL_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_EN_F1
-
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1_WIDTH 2U
-#define LPDDR4__PI_RDLVL_GATE_EN_F1__REG DENALI_PI_181
-#define LPDDR4__PI_RDLVL_GATE_EN_F1__FLD LPDDR4__DENALI_PI_181__PI_RDLVL_GATE_EN_F1
-
-#define LPDDR4__DENALI_PI_182_READ_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_182_WRITE_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2_WIDTH 2U
-#define LPDDR4__PI_RDLVL_EN_F2__REG DENALI_PI_182
-#define LPDDR4__PI_RDLVL_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_EN_F2
-
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2_WIDTH 2U
-#define LPDDR4__PI_RDLVL_GATE_EN_F2__REG DENALI_PI_182
-#define LPDDR4__PI_RDLVL_GATE_EN_F2__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_GATE_EN_F2
-
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0_WIDTH 2U
-#define LPDDR4__PI_RDLVL_PAT0_EN_F0__REG DENALI_PI_182
-#define LPDDR4__PI_RDLVL_PAT0_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_PAT0_EN_F0
-
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0_WIDTH 2U
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__REG DENALI_PI_182
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F0__FLD LPDDR4__DENALI_PI_182__PI_RDLVL_RXCAL_EN_F0
-
-#define LPDDR4__DENALI_PI_183_READ_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_183_WRITE_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0_WIDTH 2U
-#define LPDDR4__PI_RDLVL_DFE_EN_F0__REG DENALI_PI_183
-#define LPDDR4__PI_RDLVL_DFE_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_DFE_EN_F0
-
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0_WIDTH 2U
-#define LPDDR4__PI_RDLVL_MULTI_EN_F0__REG DENALI_PI_183
-#define LPDDR4__PI_RDLVL_MULTI_EN_F0__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_MULTI_EN_F0
-
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1_WIDTH 2U
-#define LPDDR4__PI_RDLVL_PAT0_EN_F1__REG DENALI_PI_183
-#define LPDDR4__PI_RDLVL_PAT0_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_PAT0_EN_F1
-
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1_WIDTH 2U
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__REG DENALI_PI_183
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F1__FLD LPDDR4__DENALI_PI_183__PI_RDLVL_RXCAL_EN_F1
-
-#define LPDDR4__DENALI_PI_184_READ_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_184_WRITE_MASK 0x03030303U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1_WIDTH 2U
-#define LPDDR4__PI_RDLVL_DFE_EN_F1__REG DENALI_PI_184
-#define LPDDR4__PI_RDLVL_DFE_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_DFE_EN_F1
-
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1_WIDTH 2U
-#define LPDDR4__PI_RDLVL_MULTI_EN_F1__REG DENALI_PI_184
-#define LPDDR4__PI_RDLVL_MULTI_EN_F1__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_MULTI_EN_F1
-
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2_WIDTH 2U
-#define LPDDR4__PI_RDLVL_PAT0_EN_F2__REG DENALI_PI_184
-#define LPDDR4__PI_RDLVL_PAT0_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_PAT0_EN_F2
-
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2_WIDTH 2U
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__REG DENALI_PI_184
-#define LPDDR4__PI_RDLVL_RXCAL_EN_F2__FLD LPDDR4__DENALI_PI_184__PI_RDLVL_RXCAL_EN_F2
-
-#define LPDDR4__DENALI_PI_185_READ_MASK 0x7F7F0303U
-#define LPDDR4__DENALI_PI_185_WRITE_MASK 0x7F7F0303U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2_WIDTH 2U
-#define LPDDR4__PI_RDLVL_DFE_EN_F2__REG DENALI_PI_185
-#define LPDDR4__PI_RDLVL_DFE_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_DFE_EN_F2
-
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2_WIDTH 2U
-#define LPDDR4__PI_RDLVL_MULTI_EN_F2__REG DENALI_PI_185
-#define LPDDR4__PI_RDLVL_MULTI_EN_F2__FLD LPDDR4__DENALI_PI_185__PI_RDLVL_MULTI_EN_F2
-
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_MASK 0x007F0000U
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0_WIDTH 7U
-#define LPDDR4__PI_RDLAT_ADJ_F0__REG DENALI_PI_185
-#define LPDDR4__PI_RDLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F0
-
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1_WIDTH 7U
-#define LPDDR4__PI_RDLAT_ADJ_F1__REG DENALI_PI_185
-#define LPDDR4__PI_RDLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_185__PI_RDLAT_ADJ_F1
-
-#define LPDDR4__DENALI_PI_186_READ_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_186_WRITE_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2_WIDTH 7U
-#define LPDDR4__PI_RDLAT_ADJ_F2__REG DENALI_PI_186
-#define LPDDR4__PI_RDLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_RDLAT_ADJ_F2
-
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0_WIDTH 7U
-#define LPDDR4__PI_WRLAT_ADJ_F0__REG DENALI_PI_186
-#define LPDDR4__PI_WRLAT_ADJ_F0__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F0
-
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_MASK 0x007F0000U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1_WIDTH 7U
-#define LPDDR4__PI_WRLAT_ADJ_F1__REG DENALI_PI_186
-#define LPDDR4__PI_WRLAT_ADJ_F1__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F1
-
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2_WIDTH 7U
-#define LPDDR4__PI_WRLAT_ADJ_F2__REG DENALI_PI_186
-#define LPDDR4__PI_WRLAT_ADJ_F2__FLD LPDDR4__DENALI_PI_186__PI_WRLAT_ADJ_F2
-
-#define LPDDR4__DENALI_PI_187_READ_MASK 0x00070707U
-#define LPDDR4__DENALI_PI_187_WRITE_MASK 0x00070707U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_MASK 0x00000007U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0_WIDTH 3U
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__REG DENALI_PI_187
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F0
-
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_MASK 0x00000700U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1_WIDTH 3U
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__REG DENALI_PI_187
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F1
-
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_MASK 0x00070000U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2_WIDTH 3U
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__REG DENALI_PI_187
-#define LPDDR4__PI_TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_PI_187__PI_TDFI_PHY_WRDATA_F2
-
-#define LPDDR4__DENALI_PI_188_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_188_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0_WIDTH 10U
-#define LPDDR4__PI_TDFI_CALVL_CC_F0__REG DENALI_PI_188
-#define LPDDR4__PI_TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CC_F0
-
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0_WIDTH 10U
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__REG DENALI_PI_188
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_PI_188__PI_TDFI_CALVL_CAPTURE_F0
-
-#define LPDDR4__DENALI_PI_189_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_189_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1_WIDTH 10U
-#define LPDDR4__PI_TDFI_CALVL_CC_F1__REG DENALI_PI_189
-#define LPDDR4__PI_TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CC_F1
-
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1_WIDTH 10U
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__REG DENALI_PI_189
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_PI_189__PI_TDFI_CALVL_CAPTURE_F1
-
-#define LPDDR4__DENALI_PI_190_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_190_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2_WIDTH 10U
-#define LPDDR4__PI_TDFI_CALVL_CC_F2__REG DENALI_PI_190
-#define LPDDR4__PI_TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CC_F2
-
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2_WIDTH 10U
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__REG DENALI_PI_190
-#define LPDDR4__PI_TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_PI_190__PI_TDFI_CALVL_CAPTURE_F2
-
-#define LPDDR4__DENALI_PI_191_READ_MASK 0x1F030303U
-#define LPDDR4__DENALI_PI_191_WRITE_MASK 0x1F030303U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0_WIDTH 2U
-#define LPDDR4__PI_CALVL_EN_F0__REG DENALI_PI_191
-#define LPDDR4__PI_CALVL_EN_F0__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F0
-
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1_WIDTH 2U
-#define LPDDR4__PI_CALVL_EN_F1__REG DENALI_PI_191
-#define LPDDR4__PI_CALVL_EN_F1__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F1
-
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2_WIDTH 2U
-#define LPDDR4__PI_CALVL_EN_F2__REG DENALI_PI_191
-#define LPDDR4__PI_CALVL_EN_F2__FLD LPDDR4__DENALI_PI_191__PI_CALVL_EN_F2
-
-#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_MASK 0x1F000000U
-#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_191__PI_TMRZ_F0_WIDTH 5U
-#define LPDDR4__PI_TMRZ_F0__REG DENALI_PI_191
-#define LPDDR4__PI_TMRZ_F0__FLD LPDDR4__DENALI_PI_191__PI_TMRZ_F0
-
-#define LPDDR4__DENALI_PI_192_READ_MASK 0x001F3FFFU
-#define LPDDR4__DENALI_PI_192_WRITE_MASK 0x001F3FFFU
-#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_192__PI_TCAENT_F0_WIDTH 14U
-#define LPDDR4__PI_TCAENT_F0__REG DENALI_PI_192
-#define LPDDR4__PI_TCAENT_F0__FLD LPDDR4__DENALI_PI_192__PI_TCAENT_F0
-
-#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_192__PI_TMRZ_F1_WIDTH 5U
-#define LPDDR4__PI_TMRZ_F1__REG DENALI_PI_192
-#define LPDDR4__PI_TMRZ_F1__FLD LPDDR4__DENALI_PI_192__PI_TMRZ_F1
-
-#define LPDDR4__DENALI_PI_193_READ_MASK 0x001F3FFFU
-#define LPDDR4__DENALI_PI_193_WRITE_MASK 0x001F3FFFU
-#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_193__PI_TCAENT_F1_WIDTH 14U
-#define LPDDR4__PI_TCAENT_F1__REG DENALI_PI_193
-#define LPDDR4__PI_TCAENT_F1__FLD LPDDR4__DENALI_PI_193__PI_TCAENT_F1
-
-#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_193__PI_TMRZ_F2_WIDTH 5U
-#define LPDDR4__PI_TMRZ_F2__REG DENALI_PI_193
-#define LPDDR4__PI_TMRZ_F2__FLD LPDDR4__DENALI_PI_193__PI_TMRZ_F2
-
-#define LPDDR4__DENALI_PI_194_READ_MASK 0x1F1F3FFFU
-#define LPDDR4__DENALI_PI_194_WRITE_MASK 0x1F1F3FFFU
-#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_MASK 0x00003FFFU
-#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_194__PI_TCAENT_F2_WIDTH 14U
-#define LPDDR4__PI_TCAENT_F2__REG DENALI_PI_194
-#define LPDDR4__PI_TCAENT_F2__FLD LPDDR4__DENALI_PI_194__PI_TCAENT_F2
-
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0_WIDTH 5U
-#define LPDDR4__PI_TDFI_CACSCA_F0__REG DENALI_PI_194
-#define LPDDR4__PI_TDFI_CACSCA_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CACSCA_F0
-
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_MASK 0x1F000000U
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0_WIDTH 5U
-#define LPDDR4__PI_TDFI_CASEL_F0__REG DENALI_PI_194
-#define LPDDR4__PI_TDFI_CASEL_F0__FLD LPDDR4__DENALI_PI_194__PI_TDFI_CASEL_F0
-
-#define LPDDR4__DENALI_PI_195_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_195_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0_WIDTH 10U
-#define LPDDR4__PI_TVREF_SHORT_F0__REG DENALI_PI_195
-#define LPDDR4__PI_TVREF_SHORT_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_SHORT_F0
-
-#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0_WIDTH 10U
-#define LPDDR4__PI_TVREF_LONG_F0__REG DENALI_PI_195
-#define LPDDR4__PI_TVREF_LONG_F0__FLD LPDDR4__DENALI_PI_195__PI_TVREF_LONG_F0
-
-#define LPDDR4__DENALI_PI_196_READ_MASK 0x03FF1F1FU
-#define LPDDR4__DENALI_PI_196_WRITE_MASK 0x03FF1F1FU
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1_WIDTH 5U
-#define LPDDR4__PI_TDFI_CACSCA_F1__REG DENALI_PI_196
-#define LPDDR4__PI_TDFI_CACSCA_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CACSCA_F1
-
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_MASK 0x00001F00U
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1_WIDTH 5U
-#define LPDDR4__PI_TDFI_CASEL_F1__REG DENALI_PI_196
-#define LPDDR4__PI_TDFI_CASEL_F1__FLD LPDDR4__DENALI_PI_196__PI_TDFI_CASEL_F1
-
-#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1_WIDTH 10U
-#define LPDDR4__PI_TVREF_SHORT_F1__REG DENALI_PI_196
-#define LPDDR4__PI_TVREF_SHORT_F1__FLD LPDDR4__DENALI_PI_196__PI_TVREF_SHORT_F1
-
-#define LPDDR4__DENALI_PI_197_READ_MASK 0x1F1F03FFU
-#define LPDDR4__DENALI_PI_197_WRITE_MASK 0x1F1F03FFU
-#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1_WIDTH 10U
-#define LPDDR4__PI_TVREF_LONG_F1__REG DENALI_PI_197
-#define LPDDR4__PI_TVREF_LONG_F1__FLD LPDDR4__DENALI_PI_197__PI_TVREF_LONG_F1
-
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2_WIDTH 5U
-#define LPDDR4__PI_TDFI_CACSCA_F2__REG DENALI_PI_197
-#define LPDDR4__PI_TDFI_CACSCA_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CACSCA_F2
-
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_MASK 0x1F000000U
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2_WIDTH 5U
-#define LPDDR4__PI_TDFI_CASEL_F2__REG DENALI_PI_197
-#define LPDDR4__PI_TDFI_CASEL_F2__FLD LPDDR4__DENALI_PI_197__PI_TDFI_CASEL_F2
-
-#define LPDDR4__DENALI_PI_198_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_198_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2_WIDTH 10U
-#define LPDDR4__PI_TVREF_SHORT_F2__REG DENALI_PI_198
-#define LPDDR4__PI_TVREF_SHORT_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_SHORT_F2
-
-#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2_WIDTH 10U
-#define LPDDR4__PI_TVREF_LONG_F2__REG DENALI_PI_198
-#define LPDDR4__PI_TVREF_LONG_F2__FLD LPDDR4__DENALI_PI_198__PI_TVREF_LONG_F2
-
-#define LPDDR4__DENALI_PI_199_READ_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_199_WRITE_MASK 0x7F7F7F7FU
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_199
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F0
-
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_199
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F0
-
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_MASK 0x007F0000U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_199
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_START_POINT_F1
-
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_199
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_199__PI_CALVL_VREF_INITIAL_STOP_POINT_F1
-
-#define LPDDR4__DENALI_PI_200_READ_MASK 0x0F0F7F7FU
-#define LPDDR4__DENALI_PI_200_WRITE_MASK 0x0F0F7F7FU
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_200
-#define LPDDR4__PI_CALVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_START_POINT_F2
-
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_200
-#define LPDDR4__PI_CALVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_INITIAL_STOP_POINT_F2
-
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0_WIDTH 4U
-#define LPDDR4__PI_CALVL_VREF_DELTA_F0__REG DENALI_PI_200
-#define LPDDR4__PI_CALVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F0
-
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1_WIDTH 4U
-#define LPDDR4__PI_CALVL_VREF_DELTA_F1__REG DENALI_PI_200
-#define LPDDR4__PI_CALVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_200__PI_CALVL_VREF_DELTA_F1
-
-#define LPDDR4__DENALI_PI_201_READ_MASK 0xFF1F0F0FU
-#define LPDDR4__DENALI_PI_201_WRITE_MASK 0xFF1F0F0FU
-#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2_WIDTH 4U
-#define LPDDR4__PI_CALVL_VREF_DELTA_F2__REG DENALI_PI_201
-#define LPDDR4__PI_CALVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_201__PI_CALVL_VREF_DELTA_F2
-
-#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0_WIDTH 4U
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__REG DENALI_PI_201
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F0__FLD LPDDR4__DENALI_PI_201__PI_TDFI_CALVL_STROBE_F0
-
-#define LPDDR4__DENALI_PI_201__PI_TXP_F0_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_201__PI_TXP_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_201__PI_TXP_F0_WIDTH 5U
-#define LPDDR4__PI_TXP_F0__REG DENALI_PI_201
-#define LPDDR4__PI_TXP_F0__FLD LPDDR4__DENALI_PI_201__PI_TXP_F0
-
-#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0_WIDTH 8U
-#define LPDDR4__PI_TMRWCKEL_F0__REG DENALI_PI_201
-#define LPDDR4__PI_TMRWCKEL_F0__FLD LPDDR4__DENALI_PI_201__PI_TMRWCKEL_F0
-
-#define LPDDR4__DENALI_PI_202_READ_MASK 0xFF1F0F1FU
-#define LPDDR4__DENALI_PI_202_WRITE_MASK 0xFF1F0F1FU
-#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_202__PI_TCKELCK_F0_WIDTH 5U
-#define LPDDR4__PI_TCKELCK_F0__REG DENALI_PI_202
-#define LPDDR4__PI_TCKELCK_F0__FLD LPDDR4__DENALI_PI_202__PI_TCKELCK_F0
-
-#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1_WIDTH 4U
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__REG DENALI_PI_202
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F1__FLD LPDDR4__DENALI_PI_202__PI_TDFI_CALVL_STROBE_F1
-
-#define LPDDR4__DENALI_PI_202__PI_TXP_F1_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_202__PI_TXP_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_202__PI_TXP_F1_WIDTH 5U
-#define LPDDR4__PI_TXP_F1__REG DENALI_PI_202
-#define LPDDR4__PI_TXP_F1__FLD LPDDR4__DENALI_PI_202__PI_TXP_F1
-
-#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1_WIDTH 8U
-#define LPDDR4__PI_TMRWCKEL_F1__REG DENALI_PI_202
-#define LPDDR4__PI_TMRWCKEL_F1__FLD LPDDR4__DENALI_PI_202__PI_TMRWCKEL_F1
-
-#define LPDDR4__DENALI_PI_203_READ_MASK 0xFF1F0F1FU
-#define LPDDR4__DENALI_PI_203_WRITE_MASK 0xFF1F0F1FU
-#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_203__PI_TCKELCK_F1_WIDTH 5U
-#define LPDDR4__PI_TCKELCK_F1__REG DENALI_PI_203
-#define LPDDR4__PI_TCKELCK_F1__FLD LPDDR4__DENALI_PI_203__PI_TCKELCK_F1
-
-#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2_WIDTH 4U
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__REG DENALI_PI_203
-#define LPDDR4__PI_TDFI_CALVL_STROBE_F2__FLD LPDDR4__DENALI_PI_203__PI_TDFI_CALVL_STROBE_F2
-
-#define LPDDR4__DENALI_PI_203__PI_TXP_F2_MASK 0x001F0000U
-#define LPDDR4__DENALI_PI_203__PI_TXP_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_203__PI_TXP_F2_WIDTH 5U
-#define LPDDR4__PI_TXP_F2__REG DENALI_PI_203
-#define LPDDR4__PI_TXP_F2__FLD LPDDR4__DENALI_PI_203__PI_TXP_F2
-
-#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2_WIDTH 8U
-#define LPDDR4__PI_TMRWCKEL_F2__REG DENALI_PI_203
-#define LPDDR4__PI_TMRWCKEL_F2__FLD LPDDR4__DENALI_PI_203__PI_TMRWCKEL_F2
-
-#define LPDDR4__DENALI_PI_204_READ_MASK 0x0003FF1FU
-#define LPDDR4__DENALI_PI_204_WRITE_MASK 0x0003FF1FU
-#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_MASK 0x0000001FU
-#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_204__PI_TCKELCK_F2_WIDTH 5U
-#define LPDDR4__PI_TCKELCK_F2__REG DENALI_PI_204
-#define LPDDR4__PI_TCKELCK_F2__FLD LPDDR4__DENALI_PI_204__PI_TCKELCK_F2
-
-#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_MASK 0x0003FF00U
-#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0_WIDTH 10U
-#define LPDDR4__PI_TDFI_INIT_START_F0__REG DENALI_PI_204
-#define LPDDR4__PI_TDFI_INIT_START_F0__FLD LPDDR4__DENALI_PI_204__PI_TDFI_INIT_START_F0
-
-#define LPDDR4__DENALI_PI_205_READ_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PI_205_WRITE_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0_WIDTH 16U
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__REG DENALI_PI_205
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_COMPLETE_F0
-
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1_WIDTH 10U
-#define LPDDR4__PI_TDFI_INIT_START_F1__REG DENALI_PI_205
-#define LPDDR4__PI_TDFI_INIT_START_F1__FLD LPDDR4__DENALI_PI_205__PI_TDFI_INIT_START_F1
-
-#define LPDDR4__DENALI_PI_206_READ_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PI_206_WRITE_MASK 0x03FFFFFFU
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1_WIDTH 16U
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__REG DENALI_PI_206
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_COMPLETE_F1
-
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2_WIDTH 10U
-#define LPDDR4__PI_TDFI_INIT_START_F2__REG DENALI_PI_206
-#define LPDDR4__PI_TDFI_INIT_START_F2__FLD LPDDR4__DENALI_PI_206__PI_TDFI_INIT_START_F2
-
-#define LPDDR4__DENALI_PI_207_READ_MASK 0x003FFFFFU
-#define LPDDR4__DENALI_PI_207_WRITE_MASK 0x003FFFFFU
-#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2_WIDTH 16U
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__REG DENALI_PI_207
-#define LPDDR4__PI_TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_PI_207__PI_TDFI_INIT_COMPLETE_F2
-
-#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_MASK 0x003F0000U
-#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0_WIDTH 6U
-#define LPDDR4__PI_TCKEHDQS_F0__REG DENALI_PI_207
-#define LPDDR4__PI_TCKEHDQS_F0__FLD LPDDR4__DENALI_PI_207__PI_TCKEHDQS_F0
-
-#define LPDDR4__DENALI_PI_208_READ_MASK 0x003F03FFU
-#define LPDDR4__DENALI_PI_208_WRITE_MASK 0x003F03FFU
-#define LPDDR4__DENALI_PI_208__PI_TFC_F0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_208__PI_TFC_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_208__PI_TFC_F0_WIDTH 10U
-#define LPDDR4__PI_TFC_F0__REG DENALI_PI_208
-#define LPDDR4__PI_TFC_F0__FLD LPDDR4__DENALI_PI_208__PI_TFC_F0
-
-#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_MASK 0x003F0000U
-#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1_WIDTH 6U
-#define LPDDR4__PI_TCKEHDQS_F1__REG DENALI_PI_208
-#define LPDDR4__PI_TCKEHDQS_F1__FLD LPDDR4__DENALI_PI_208__PI_TCKEHDQS_F1
-
-#define LPDDR4__DENALI_PI_209_READ_MASK 0x003F03FFU
-#define LPDDR4__DENALI_PI_209_WRITE_MASK 0x003F03FFU
-#define LPDDR4__DENALI_PI_209__PI_TFC_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_209__PI_TFC_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_209__PI_TFC_F1_WIDTH 10U
-#define LPDDR4__PI_TFC_F1__REG DENALI_PI_209
-#define LPDDR4__PI_TFC_F1__FLD LPDDR4__DENALI_PI_209__PI_TFC_F1
-
-#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_MASK 0x003F0000U
-#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2_WIDTH 6U
-#define LPDDR4__PI_TCKEHDQS_F2__REG DENALI_PI_209
-#define LPDDR4__PI_TCKEHDQS_F2__FLD LPDDR4__DENALI_PI_209__PI_TCKEHDQS_F2
-
-#define LPDDR4__DENALI_PI_210_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_210_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_210__PI_TFC_F2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_210__PI_TFC_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_210__PI_TFC_F2_WIDTH 10U
-#define LPDDR4__PI_TFC_F2__REG DENALI_PI_210
-#define LPDDR4__PI_TFC_F2__FLD LPDDR4__DENALI_PI_210__PI_TFC_F2
-
-#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0_WIDTH 10U
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__REG DENALI_PI_210
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F0__FLD LPDDR4__DENALI_PI_210__PI_TDFI_WDQLVL_WR_F0
-
-#define LPDDR4__DENALI_PI_211_READ_MASK 0x7F7F03FFU
-#define LPDDR4__DENALI_PI_211_WRITE_MASK 0x7F7F03FFU
-#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0_WIDTH 10U
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__REG DENALI_PI_211
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F0__FLD LPDDR4__DENALI_PI_211__PI_TDFI_WDQLVL_RW_F0
-
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_MASK 0x007F0000U
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0_WIDTH 7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__REG DENALI_PI_211
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_START_POINT_F0
-
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0_WIDTH 7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__REG DENALI_PI_211
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0__FLD LPDDR4__DENALI_PI_211__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0
-
-#define LPDDR4__DENALI_PI_212_READ_MASK 0x0003030FU
-#define LPDDR4__DENALI_PI_212_WRITE_MASK 0x0003030FU
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0_WIDTH 4U
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__REG DENALI_PI_212
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_VREF_DELTA_F0
-
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0_WIDTH 2U
-#define LPDDR4__PI_WDQLVL_EN_F0__REG DENALI_PI_212
-#define LPDDR4__PI_WDQLVL_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_WDQLVL_EN_F0
-
-#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0_WIDTH 2U
-#define LPDDR4__PI_NTP_TRAIN_EN_F0__REG DENALI_PI_212
-#define LPDDR4__PI_NTP_TRAIN_EN_F0__FLD LPDDR4__DENALI_PI_212__PI_NTP_TRAIN_EN_F0
-
-#define LPDDR4__DENALI_PI_213_READ_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_213_WRITE_MASK 0x03FF03FFU
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1_WIDTH 10U
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__REG DENALI_PI_213
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_WR_F1
-
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_MASK 0x03FF0000U
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1_WIDTH 10U
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__REG DENALI_PI_213
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F1__FLD LPDDR4__DENALI_PI_213__PI_TDFI_WDQLVL_RW_F1
-
-#define LPDDR4__DENALI_PI_214_READ_MASK 0x030F7F7FU
-#define LPDDR4__DENALI_PI_214_WRITE_MASK 0x030F7F7FU
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1_WIDTH 7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__REG DENALI_PI_214
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_START_POINT_F1
-
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_MASK 0x00007F00U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1_WIDTH 7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__REG DENALI_PI_214
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1
-
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1_WIDTH 4U
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__REG DENALI_PI_214
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_VREF_DELTA_F1
-
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_MASK 0x03000000U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1_WIDTH 2U
-#define LPDDR4__PI_WDQLVL_EN_F1__REG DENALI_PI_214
-#define LPDDR4__PI_WDQLVL_EN_F1__FLD LPDDR4__DENALI_PI_214__PI_WDQLVL_EN_F1
-
-#define LPDDR4__DENALI_PI_215_READ_MASK 0x0003FF03U
-#define LPDDR4__DENALI_PI_215_WRITE_MASK 0x0003FF03U
-#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_MASK 0x00000003U
-#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1_WIDTH 2U
-#define LPDDR4__PI_NTP_TRAIN_EN_F1__REG DENALI_PI_215
-#define LPDDR4__PI_NTP_TRAIN_EN_F1__FLD LPDDR4__DENALI_PI_215__PI_NTP_TRAIN_EN_F1
-
-#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_MASK 0x0003FF00U
-#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2_WIDTH 10U
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__REG DENALI_PI_215
-#define LPDDR4__PI_TDFI_WDQLVL_WR_F2__FLD LPDDR4__DENALI_PI_215__PI_TDFI_WDQLVL_WR_F2
-
-#define LPDDR4__DENALI_PI_216_READ_MASK 0x7F7F03FFU
-#define LPDDR4__DENALI_PI_216_WRITE_MASK 0x7F7F03FFU
-#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_MASK 0x000003FFU
-#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2_WIDTH 10U
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__REG DENALI_PI_216
-#define LPDDR4__PI_TDFI_WDQLVL_RW_F2__FLD LPDDR4__DENALI_PI_216__PI_TDFI_WDQLVL_RW_F2
-
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_MASK 0x007F0000U
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2_WIDTH 7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__REG DENALI_PI_216
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_START_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_START_POINT_F2
-
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_MASK 0x7F000000U
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2_WIDTH 7U
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__REG DENALI_PI_216
-#define LPDDR4__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2__FLD LPDDR4__DENALI_PI_216__PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2
-
-#define LPDDR4__DENALI_PI_217_READ_MASK 0xFF03030FU
-#define LPDDR4__DENALI_PI_217_WRITE_MASK 0xFF03030FU
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2_WIDTH 4U
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__REG DENALI_PI_217
-#define LPDDR4__PI_WDQLVL_VREF_DELTA_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_VREF_DELTA_F2
-
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_MASK 0x00000300U
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2_WIDTH 2U
-#define LPDDR4__PI_WDQLVL_EN_F2__REG DENALI_PI_217
-#define LPDDR4__PI_WDQLVL_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_WDQLVL_EN_F2
-
-#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_MASK 0x00030000U
-#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2_WIDTH 2U
-#define LPDDR4__PI_NTP_TRAIN_EN_F2__REG DENALI_PI_217
-#define LPDDR4__PI_NTP_TRAIN_EN_F2__FLD LPDDR4__DENALI_PI_217__PI_NTP_TRAIN_EN_F2
-
-#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_217__PI_TRTP_F0_WIDTH 8U
-#define LPDDR4__PI_TRTP_F0__REG DENALI_PI_217
-#define LPDDR4__PI_TRTP_F0__FLD LPDDR4__DENALI_PI_217__PI_TRTP_F0
-
-#define LPDDR4__DENALI_PI_218_READ_MASK 0xFF3FFFFFU
-#define LPDDR4__DENALI_PI_218_WRITE_MASK 0xFF3FFFFFU
-#define LPDDR4__DENALI_PI_218__PI_TRP_F0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_218__PI_TRP_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_218__PI_TRP_F0_WIDTH 8U
-#define LPDDR4__PI_TRP_F0__REG DENALI_PI_218
-#define LPDDR4__PI_TRP_F0__FLD LPDDR4__DENALI_PI_218__PI_TRP_F0
-
-#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_218__PI_TRCD_F0_WIDTH 8U
-#define LPDDR4__PI_TRCD_F0__REG DENALI_PI_218
-#define LPDDR4__PI_TRCD_F0__FLD LPDDR4__DENALI_PI_218__PI_TRCD_F0
-
-#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_MASK 0x003F0000U
-#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_218__PI_TWTR_F0_WIDTH 6U
-#define LPDDR4__PI_TWTR_F0__REG DENALI_PI_218
-#define LPDDR4__PI_TWTR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWTR_F0
-
-#define LPDDR4__DENALI_PI_218__PI_TWR_F0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_218__PI_TWR_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_218__PI_TWR_F0_WIDTH 8U
-#define LPDDR4__PI_TWR_F0__REG DENALI_PI_218
-#define LPDDR4__PI_TWR_F0__FLD LPDDR4__DENALI_PI_218__PI_TWR_F0
-
-#define LPDDR4__DENALI_PI_219_READ_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_PI_219_WRITE_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0_WIDTH 17U
-#define LPDDR4__PI_TRAS_MAX_F0__REG DENALI_PI_219
-#define LPDDR4__PI_TRAS_MAX_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MAX_F0
-
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0_WIDTH 8U
-#define LPDDR4__PI_TRAS_MIN_F0__REG DENALI_PI_219
-#define LPDDR4__PI_TRAS_MIN_F0__FLD LPDDR4__DENALI_PI_219__PI_TRAS_MIN_F0
-
-#define LPDDR4__DENALI_PI_220_READ_MASK 0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_220_WRITE_MASK 0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0_WIDTH 4U
-#define LPDDR4__PI_TDQSCK_MAX_F0__REG DENALI_PI_220
-#define LPDDR4__PI_TDQSCK_MAX_F0__FLD LPDDR4__DENALI_PI_220__PI_TDQSCK_MAX_F0
-
-#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_MASK 0x00003F00U
-#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_220__PI_TCCDMW_F0_WIDTH 6U
-#define LPDDR4__PI_TCCDMW_F0__REG DENALI_PI_220
-#define LPDDR4__PI_TCCDMW_F0__FLD LPDDR4__DENALI_PI_220__PI_TCCDMW_F0
-
-#define LPDDR4__DENALI_PI_220__PI_TSR_F0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_220__PI_TSR_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_220__PI_TSR_F0_WIDTH 8U
-#define LPDDR4__PI_TSR_F0__REG DENALI_PI_220
-#define LPDDR4__PI_TSR_F0__FLD LPDDR4__DENALI_PI_220__PI_TSR_F0
-
-#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_SHIFT 24U
-#define LPDDR4__DENALI_PI_220__PI_TMRD_F0_WIDTH 8U
-#define LPDDR4__PI_TMRD_F0__REG DENALI_PI_220
-#define LPDDR4__PI_TMRD_F0__FLD LPDDR4__DENALI_PI_220__PI_TMRD_F0
-
-#define LPDDR4__DENALI_PI_221_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_221_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_221__PI_TMRW_F0_WIDTH 8U
-#define LPDDR4__PI_TMRW_F0__REG DENALI_PI_221
-#define LPDDR4__PI_TMRW_F0__FLD LPDDR4__DENALI_PI_221__PI_TMRW_F0
-
-#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_221__PI_TRTP_F1_WIDTH 8U
-#define LPDDR4__PI_TRTP_F1__REG DENALI_PI_221
-#define LPDDR4__PI_TRTP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRTP_F1
-
-#define LPDDR4__DENALI_PI_221__PI_TRP_F1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_221__PI_TRP_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_221__PI_TRP_F1_WIDTH 8U
-#define LPDDR4__PI_TRP_F1__REG DENALI_PI_221
-#define LPDDR4__PI_TRP_F1__FLD LPDDR4__DENALI_PI_221__PI_TRP_F1
-
-#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_221__PI_TRCD_F1_WIDTH 8U
-#define LPDDR4__PI_TRCD_F1__REG DENALI_PI_221
-#define LPDDR4__PI_TRCD_F1__FLD LPDDR4__DENALI_PI_221__PI_TRCD_F1
-
-#define LPDDR4__DENALI_PI_222_READ_MASK 0x0000FF3FU
-#define LPDDR4__DENALI_PI_222_WRITE_MASK 0x0000FF3FU
-#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_MASK 0x0000003FU
-#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_222__PI_TWTR_F1_WIDTH 6U
-#define LPDDR4__PI_TWTR_F1__REG DENALI_PI_222
-#define LPDDR4__PI_TWTR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWTR_F1
-
-#define LPDDR4__DENALI_PI_222__PI_TWR_F1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_222__PI_TWR_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_222__PI_TWR_F1_WIDTH 8U
-#define LPDDR4__PI_TWR_F1__REG DENALI_PI_222
-#define LPDDR4__PI_TWR_F1__FLD LPDDR4__DENALI_PI_222__PI_TWR_F1
-
-#define LPDDR4__DENALI_PI_223_READ_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_PI_223_WRITE_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1_WIDTH 17U
-#define LPDDR4__PI_TRAS_MAX_F1__REG DENALI_PI_223
-#define LPDDR4__PI_TRAS_MAX_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MAX_F1
-
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1_WIDTH 8U
-#define LPDDR4__PI_TRAS_MIN_F1__REG DENALI_PI_223
-#define LPDDR4__PI_TRAS_MIN_F1__FLD LPDDR4__DENALI_PI_223__PI_TRAS_MIN_F1
-
-#define LPDDR4__DENALI_PI_224_READ_MASK 0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_224_WRITE_MASK 0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1_WIDTH 4U
-#define LPDDR4__PI_TDQSCK_MAX_F1__REG DENALI_PI_224
-#define LPDDR4__PI_TDQSCK_MAX_F1__FLD LPDDR4__DENALI_PI_224__PI_TDQSCK_MAX_F1
-
-#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_MASK 0x00003F00U
-#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_224__PI_TCCDMW_F1_WIDTH 6U
-#define LPDDR4__PI_TCCDMW_F1__REG DENALI_PI_224
-#define LPDDR4__PI_TCCDMW_F1__FLD LPDDR4__DENALI_PI_224__PI_TCCDMW_F1
-
-#define LPDDR4__DENALI_PI_224__PI_TSR_F1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_224__PI_TSR_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_224__PI_TSR_F1_WIDTH 8U
-#define LPDDR4__PI_TSR_F1__REG DENALI_PI_224
-#define LPDDR4__PI_TSR_F1__FLD LPDDR4__DENALI_PI_224__PI_TSR_F1
-
-#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_224__PI_TMRD_F1_WIDTH 8U
-#define LPDDR4__PI_TMRD_F1__REG DENALI_PI_224
-#define LPDDR4__PI_TMRD_F1__FLD LPDDR4__DENALI_PI_224__PI_TMRD_F1
-
-#define LPDDR4__DENALI_PI_225_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_225_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_225__PI_TMRW_F1_WIDTH 8U
-#define LPDDR4__PI_TMRW_F1__REG DENALI_PI_225
-#define LPDDR4__PI_TMRW_F1__FLD LPDDR4__DENALI_PI_225__PI_TMRW_F1
-
-#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_225__PI_TRTP_F2_WIDTH 8U
-#define LPDDR4__PI_TRTP_F2__REG DENALI_PI_225
-#define LPDDR4__PI_TRTP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRTP_F2
-
-#define LPDDR4__DENALI_PI_225__PI_TRP_F2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_225__PI_TRP_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_225__PI_TRP_F2_WIDTH 8U
-#define LPDDR4__PI_TRP_F2__REG DENALI_PI_225
-#define LPDDR4__PI_TRP_F2__FLD LPDDR4__DENALI_PI_225__PI_TRP_F2
-
-#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_225__PI_TRCD_F2_WIDTH 8U
-#define LPDDR4__PI_TRCD_F2__REG DENALI_PI_225
-#define LPDDR4__PI_TRCD_F2__FLD LPDDR4__DENALI_PI_225__PI_TRCD_F2
-
-#define LPDDR4__DENALI_PI_226_READ_MASK 0x0000FF3FU
-#define LPDDR4__DENALI_PI_226_WRITE_MASK 0x0000FF3FU
-#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_MASK 0x0000003FU
-#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_226__PI_TWTR_F2_WIDTH 6U
-#define LPDDR4__PI_TWTR_F2__REG DENALI_PI_226
-#define LPDDR4__PI_TWTR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWTR_F2
-
-#define LPDDR4__DENALI_PI_226__PI_TWR_F2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_226__PI_TWR_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_226__PI_TWR_F2_WIDTH 8U
-#define LPDDR4__PI_TWR_F2__REG DENALI_PI_226
-#define LPDDR4__PI_TWR_F2__FLD LPDDR4__DENALI_PI_226__PI_TWR_F2
-
-#define LPDDR4__DENALI_PI_227_READ_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_PI_227_WRITE_MASK 0xFF01FFFFU
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_MASK 0x0001FFFFU
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2_WIDTH 17U
-#define LPDDR4__PI_TRAS_MAX_F2__REG DENALI_PI_227
-#define LPDDR4__PI_TRAS_MAX_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MAX_F2
-
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2_WIDTH 8U
-#define LPDDR4__PI_TRAS_MIN_F2__REG DENALI_PI_227
-#define LPDDR4__PI_TRAS_MIN_F2__FLD LPDDR4__DENALI_PI_227__PI_TRAS_MIN_F2
-
-#define LPDDR4__DENALI_PI_228_READ_MASK 0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_228_WRITE_MASK 0xFFFF3F0FU
-#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2_WIDTH 4U
-#define LPDDR4__PI_TDQSCK_MAX_F2__REG DENALI_PI_228
-#define LPDDR4__PI_TDQSCK_MAX_F2__FLD LPDDR4__DENALI_PI_228__PI_TDQSCK_MAX_F2
-
-#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_MASK 0x00003F00U
-#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_SHIFT 8U
-#define LPDDR4__DENALI_PI_228__PI_TCCDMW_F2_WIDTH 6U
-#define LPDDR4__PI_TCCDMW_F2__REG DENALI_PI_228
-#define LPDDR4__PI_TCCDMW_F2__FLD LPDDR4__DENALI_PI_228__PI_TCCDMW_F2
-
-#define LPDDR4__DENALI_PI_228__PI_TSR_F2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_228__PI_TSR_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_228__PI_TSR_F2_WIDTH 8U
-#define LPDDR4__PI_TSR_F2__REG DENALI_PI_228
-#define LPDDR4__PI_TSR_F2__FLD LPDDR4__DENALI_PI_228__PI_TSR_F2
-
-#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_SHIFT 24U
-#define LPDDR4__DENALI_PI_228__PI_TMRD_F2_WIDTH 8U
-#define LPDDR4__PI_TMRD_F2__REG DENALI_PI_228
-#define LPDDR4__PI_TMRD_F2__FLD LPDDR4__DENALI_PI_228__PI_TMRD_F2
-
-#define LPDDR4__DENALI_PI_229_READ_MASK 0x1FFFFFFFU
-#define LPDDR4__DENALI_PI_229_WRITE_MASK 0x1FFFFFFFU
-#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_229__PI_TMRW_F2_WIDTH 8U
-#define LPDDR4__PI_TMRW_F2__REG DENALI_PI_229
-#define LPDDR4__PI_TMRW_F2__FLD LPDDR4__DENALI_PI_229__PI_TMRW_F2
-
-#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_MASK 0x1FFFFF00U
-#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0_WIDTH 21U
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__REG DENALI_PI_229
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_PI_229__PI_TDFI_CTRLUPD_MAX_F0
-
-#define LPDDR4__DENALI_PI_230_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_230_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0_WIDTH 32U
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_PI_230
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_PI_230__PI_TDFI_CTRLUPD_INTERVAL_F0
-
-#define LPDDR4__DENALI_PI_231_READ_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_PI_231_WRITE_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1_WIDTH 21U
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__REG DENALI_PI_231
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_PI_231__PI_TDFI_CTRLUPD_MAX_F1
-
-#define LPDDR4__DENALI_PI_232_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_232_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1_WIDTH 32U
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_PI_232
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_PI_232__PI_TDFI_CTRLUPD_INTERVAL_F1
-
-#define LPDDR4__DENALI_PI_233_READ_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_PI_233_WRITE_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_MASK 0x001FFFFFU
-#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2_WIDTH 21U
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__REG DENALI_PI_233
-#define LPDDR4__PI_TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_PI_233__PI_TDFI_CTRLUPD_MAX_F2
-
-#define LPDDR4__DENALI_PI_234_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_234_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2_WIDTH 32U
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_PI_234
-#define LPDDR4__PI_TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_PI_234__PI_TDFI_CTRLUPD_INTERVAL_F2
-
-#define LPDDR4__DENALI_PI_235_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_235_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F0_WIDTH 16U
-#define LPDDR4__PI_TXSR_F0__REG DENALI_PI_235
-#define LPDDR4__PI_TXSR_F0__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F0
-
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_235__PI_TXSR_F1_WIDTH 16U
-#define LPDDR4__PI_TXSR_F1__REG DENALI_PI_235
-#define LPDDR4__PI_TXSR_F1__FLD LPDDR4__DENALI_PI_235__PI_TXSR_F1
-
-#define LPDDR4__DENALI_PI_236_READ_MASK 0x3F3FFFFFU
-#define LPDDR4__DENALI_PI_236_WRITE_MASK 0x3F3FFFFFU
-#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_236__PI_TXSR_F2_WIDTH 16U
-#define LPDDR4__PI_TXSR_F2__REG DENALI_PI_236
-#define LPDDR4__PI_TXSR_F2__FLD LPDDR4__DENALI_PI_236__PI_TXSR_F2
-
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_MASK 0x003F0000U
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F0_WIDTH 6U
-#define LPDDR4__PI_TEXCKE_F0__REG DENALI_PI_236
-#define LPDDR4__PI_TEXCKE_F0__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F0
-
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_MASK 0x3F000000U
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_SHIFT 24U
-#define LPDDR4__DENALI_PI_236__PI_TEXCKE_F1_WIDTH 6U
-#define LPDDR4__PI_TEXCKE_F1__REG DENALI_PI_236
-#define LPDDR4__PI_TEXCKE_F1__FLD LPDDR4__DENALI_PI_236__PI_TEXCKE_F1
-
-#define LPDDR4__DENALI_PI_237_READ_MASK 0xFFFFFF3FU
-#define LPDDR4__DENALI_PI_237_WRITE_MASK 0xFFFFFF3FU
-#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_MASK 0x0000003FU
-#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_237__PI_TEXCKE_F2_WIDTH 6U
-#define LPDDR4__PI_TEXCKE_F2__REG DENALI_PI_237
-#define LPDDR4__PI_TEXCKE_F2__FLD LPDDR4__DENALI_PI_237__PI_TEXCKE_F2
-
-#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_MASK 0xFFFFFF00U
-#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_SHIFT 8U
-#define LPDDR4__DENALI_PI_237__PI_TINIT_F0_WIDTH 24U
-#define LPDDR4__PI_TINIT_F0__REG DENALI_PI_237
-#define LPDDR4__PI_TINIT_F0__FLD LPDDR4__DENALI_PI_237__PI_TINIT_F0
-
-#define LPDDR4__DENALI_PI_238_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_238_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_238__PI_TINIT3_F0_WIDTH 24U
-#define LPDDR4__PI_TINIT3_F0__REG DENALI_PI_238
-#define LPDDR4__PI_TINIT3_F0__FLD LPDDR4__DENALI_PI_238__PI_TINIT3_F0
-
-#define LPDDR4__DENALI_PI_239_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_239_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_239__PI_TINIT4_F0_WIDTH 24U
-#define LPDDR4__PI_TINIT4_F0__REG DENALI_PI_239
-#define LPDDR4__PI_TINIT4_F0__FLD LPDDR4__DENALI_PI_239__PI_TINIT4_F0
-
-#define LPDDR4__DENALI_PI_240_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_240_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_240__PI_TINIT5_F0_WIDTH 24U
-#define LPDDR4__PI_TINIT5_F0__REG DENALI_PI_240
-#define LPDDR4__PI_TINIT5_F0__FLD LPDDR4__DENALI_PI_240__PI_TINIT5_F0
-
-#define LPDDR4__DENALI_PI_241_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_241_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_241__PI_TXSNR_F0_WIDTH 16U
-#define LPDDR4__PI_TXSNR_F0__REG DENALI_PI_241
-#define LPDDR4__PI_TXSNR_F0__FLD LPDDR4__DENALI_PI_241__PI_TXSNR_F0
-
-#define LPDDR4__DENALI_PI_242_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_242_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_242__PI_TINIT_F1_WIDTH 24U
-#define LPDDR4__PI_TINIT_F1__REG DENALI_PI_242
-#define LPDDR4__PI_TINIT_F1__FLD LPDDR4__DENALI_PI_242__PI_TINIT_F1
-
-#define LPDDR4__DENALI_PI_243_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_243_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_243__PI_TINIT3_F1_WIDTH 24U
-#define LPDDR4__PI_TINIT3_F1__REG DENALI_PI_243
-#define LPDDR4__PI_TINIT3_F1__FLD LPDDR4__DENALI_PI_243__PI_TINIT3_F1
-
-#define LPDDR4__DENALI_PI_244_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_244_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_244__PI_TINIT4_F1_WIDTH 24U
-#define LPDDR4__PI_TINIT4_F1__REG DENALI_PI_244
-#define LPDDR4__PI_TINIT4_F1__FLD LPDDR4__DENALI_PI_244__PI_TINIT4_F1
-
-#define LPDDR4__DENALI_PI_245_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_245_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_245__PI_TINIT5_F1_WIDTH 24U
-#define LPDDR4__PI_TINIT5_F1__REG DENALI_PI_245
-#define LPDDR4__PI_TINIT5_F1__FLD LPDDR4__DENALI_PI_245__PI_TINIT5_F1
-
-#define LPDDR4__DENALI_PI_246_READ_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_246_WRITE_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_246__PI_TXSNR_F1_WIDTH 16U
-#define LPDDR4__PI_TXSNR_F1__REG DENALI_PI_246
-#define LPDDR4__PI_TXSNR_F1__FLD LPDDR4__DENALI_PI_246__PI_TXSNR_F1
-
-#define LPDDR4__DENALI_PI_247_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_247_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_247__PI_TINIT_F2_WIDTH 24U
-#define LPDDR4__PI_TINIT_F2__REG DENALI_PI_247
-#define LPDDR4__PI_TINIT_F2__FLD LPDDR4__DENALI_PI_247__PI_TINIT_F2
-
-#define LPDDR4__DENALI_PI_248_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_248_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_248__PI_TINIT3_F2_WIDTH 24U
-#define LPDDR4__PI_TINIT3_F2__REG DENALI_PI_248
-#define LPDDR4__PI_TINIT3_F2__FLD LPDDR4__DENALI_PI_248__PI_TINIT3_F2
-
-#define LPDDR4__DENALI_PI_249_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_249_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_249__PI_TINIT4_F2_WIDTH 24U
-#define LPDDR4__PI_TINIT4_F2__REG DENALI_PI_249
-#define LPDDR4__PI_TINIT4_F2__FLD LPDDR4__DENALI_PI_249__PI_TINIT4_F2
-
-#define LPDDR4__DENALI_PI_250_READ_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_250_WRITE_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_MASK 0x00FFFFFFU
-#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_250__PI_TINIT5_F2_WIDTH 24U
-#define LPDDR4__PI_TINIT5_F2__REG DENALI_PI_250
-#define LPDDR4__PI_TINIT5_F2__FLD LPDDR4__DENALI_PI_250__PI_TINIT5_F2
-
-#define LPDDR4__DENALI_PI_251_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_251_WRITE_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_251__PI_TXSNR_F2_WIDTH 16U
-#define LPDDR4__PI_TXSNR_F2__REG DENALI_PI_251
-#define LPDDR4__PI_TXSNR_F2__FLD LPDDR4__DENALI_PI_251__PI_TXSNR_F2
-
-#define LPDDR4__DENALI_PI_251__PI_RESERVED49_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PI_251__PI_RESERVED49_SHIFT 16U
-#define LPDDR4__DENALI_PI_251__PI_RESERVED49_WIDTH 12U
-#define LPDDR4__PI_RESERVED49__REG DENALI_PI_251
-#define LPDDR4__PI_RESERVED49__FLD LPDDR4__DENALI_PI_251__PI_RESERVED49
-
-#define LPDDR4__DENALI_PI_252_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_252_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_252__PI_RESERVED50_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PI_252__PI_RESERVED50_SHIFT 0U
-#define LPDDR4__DENALI_PI_252__PI_RESERVED50_WIDTH 12U
-#define LPDDR4__PI_RESERVED50__REG DENALI_PI_252
-#define LPDDR4__PI_RESERVED50__FLD LPDDR4__DENALI_PI_252__PI_RESERVED50
-
-#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_SHIFT 16U
-#define LPDDR4__DENALI_PI_252__PI_TZQCAL_F0_WIDTH 12U
-#define LPDDR4__PI_TZQCAL_F0__REG DENALI_PI_252
-#define LPDDR4__PI_TZQCAL_F0__FLD LPDDR4__DENALI_PI_252__PI_TZQCAL_F0
-
-#define LPDDR4__DENALI_PI_253_READ_MASK 0x000FFF7FU
-#define LPDDR4__DENALI_PI_253_WRITE_MASK 0x000FFF7FU
-#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_253__PI_TZQLAT_F0_WIDTH 7U
-#define LPDDR4__PI_TZQLAT_F0__REG DENALI_PI_253
-#define LPDDR4__PI_TZQLAT_F0__FLD LPDDR4__DENALI_PI_253__PI_TZQLAT_F0
-
-#define LPDDR4__DENALI_PI_253__PI_RESERVED51_MASK 0x000FFF00U
-#define LPDDR4__DENALI_PI_253__PI_RESERVED51_SHIFT 8U
-#define LPDDR4__DENALI_PI_253__PI_RESERVED51_WIDTH 12U
-#define LPDDR4__PI_RESERVED51__REG DENALI_PI_253
-#define LPDDR4__PI_RESERVED51__FLD LPDDR4__DENALI_PI_253__PI_RESERVED51
-
-#define LPDDR4__DENALI_PI_254_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_254_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_254__PI_RESERVED52_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PI_254__PI_RESERVED52_SHIFT 0U
-#define LPDDR4__DENALI_PI_254__PI_RESERVED52_WIDTH 12U
-#define LPDDR4__PI_RESERVED52__REG DENALI_PI_254
-#define LPDDR4__PI_RESERVED52__FLD LPDDR4__DENALI_PI_254__PI_RESERVED52
-
-#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_SHIFT 16U
-#define LPDDR4__DENALI_PI_254__PI_TZQCAL_F1_WIDTH 12U
-#define LPDDR4__PI_TZQCAL_F1__REG DENALI_PI_254
-#define LPDDR4__PI_TZQCAL_F1__FLD LPDDR4__DENALI_PI_254__PI_TZQCAL_F1
-
-#define LPDDR4__DENALI_PI_255_READ_MASK 0x000FFF7FU
-#define LPDDR4__DENALI_PI_255_WRITE_MASK 0x000FFF7FU
-#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_SHIFT 0U
-#define LPDDR4__DENALI_PI_255__PI_TZQLAT_F1_WIDTH 7U
-#define LPDDR4__PI_TZQLAT_F1__REG DENALI_PI_255
-#define LPDDR4__PI_TZQLAT_F1__FLD LPDDR4__DENALI_PI_255__PI_TZQLAT_F1
-
-#define LPDDR4__DENALI_PI_255__PI_RESERVED53_MASK 0x000FFF00U
-#define LPDDR4__DENALI_PI_255__PI_RESERVED53_SHIFT 8U
-#define LPDDR4__DENALI_PI_255__PI_RESERVED53_WIDTH 12U
-#define LPDDR4__PI_RESERVED53__REG DENALI_PI_255
-#define LPDDR4__PI_RESERVED53__FLD LPDDR4__DENALI_PI_255__PI_RESERVED53
-
-#define LPDDR4__DENALI_PI_256_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_256_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_256__PI_RESERVED54_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PI_256__PI_RESERVED54_SHIFT 0U
-#define LPDDR4__DENALI_PI_256__PI_RESERVED54_WIDTH 12U
-#define LPDDR4__PI_RESERVED54__REG DENALI_PI_256
-#define LPDDR4__PI_RESERVED54__FLD LPDDR4__DENALI_PI_256__PI_RESERVED54
-
-#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_256__PI_TZQCAL_F2_WIDTH 12U
-#define LPDDR4__PI_TZQCAL_F2__REG DENALI_PI_256
-#define LPDDR4__PI_TZQCAL_F2__FLD LPDDR4__DENALI_PI_256__PI_TZQCAL_F2
-
-#define LPDDR4__DENALI_PI_257_READ_MASK 0x000FFF7FU
-#define LPDDR4__DENALI_PI_257_WRITE_MASK 0x000FFF7FU
-#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_MASK 0x0000007FU
-#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_SHIFT 0U
-#define LPDDR4__DENALI_PI_257__PI_TZQLAT_F2_WIDTH 7U
-#define LPDDR4__PI_TZQLAT_F2__REG DENALI_PI_257
-#define LPDDR4__PI_TZQLAT_F2__FLD LPDDR4__DENALI_PI_257__PI_TZQLAT_F2
-
-#define LPDDR4__DENALI_PI_257__PI_RESERVED55_MASK 0x000FFF00U
-#define LPDDR4__DENALI_PI_257__PI_RESERVED55_SHIFT 8U
-#define LPDDR4__DENALI_PI_257__PI_RESERVED55_WIDTH 12U
-#define LPDDR4__PI_RESERVED55__REG DENALI_PI_257
-#define LPDDR4__PI_RESERVED55__FLD LPDDR4__DENALI_PI_257__PI_RESERVED55
-
-#define LPDDR4__DENALI_PI_258_READ_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_258_WRITE_MASK 0x0FFF0FFFU
-#define LPDDR4__DENALI_PI_258__PI_RESERVED56_MASK 0x00000FFFU
-#define LPDDR4__DENALI_PI_258__PI_RESERVED56_SHIFT 0U
-#define LPDDR4__DENALI_PI_258__PI_RESERVED56_WIDTH 12U
-#define LPDDR4__PI_RESERVED56__REG DENALI_PI_258
-#define LPDDR4__PI_RESERVED56__FLD LPDDR4__DENALI_PI_258__PI_RESERVED56
-
-#define LPDDR4__DENALI_PI_258__PI_RESERVED57_MASK 0x0FFF0000U
-#define LPDDR4__DENALI_PI_258__PI_RESERVED57_SHIFT 16U
-#define LPDDR4__DENALI_PI_258__PI_RESERVED57_WIDTH 12U
-#define LPDDR4__PI_RESERVED57__REG DENALI_PI_258
-#define LPDDR4__PI_RESERVED57__FLD LPDDR4__DENALI_PI_258__PI_RESERVED57
-
-#define LPDDR4__DENALI_PI_259_READ_MASK 0xFF0F0F0FU
-#define LPDDR4__DENALI_PI_259_WRITE_MASK 0xFF0F0F0FU
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_SHIFT 0U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0_WIDTH 4U
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__REG DENALI_PI_259
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F0__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F0
-
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_SHIFT 8U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1_WIDTH 4U
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__REG DENALI_PI_259
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F1__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F1
-
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_SHIFT 16U
-#define LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2_WIDTH 4U
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__REG DENALI_PI_259
-#define LPDDR4__PI_WDQ_OSC_DELTA_INDEX_F2__FLD LPDDR4__DENALI_PI_259__PI_WDQ_OSC_DELTA_INDEX_F2
-
-#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_259__PI_MR13_DATA_0_WIDTH 8U
-#define LPDDR4__PI_MR13_DATA_0__REG DENALI_PI_259
-#define LPDDR4__PI_MR13_DATA_0__FLD LPDDR4__DENALI_PI_259__PI_MR13_DATA_0
-
-#define LPDDR4__DENALI_PI_260_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_260_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_260__PI_MR15_DATA_0_WIDTH 8U
-#define LPDDR4__PI_MR15_DATA_0__REG DENALI_PI_260
-#define LPDDR4__PI_MR15_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR15_DATA_0
-
-#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_260__PI_MR16_DATA_0_WIDTH 8U
-#define LPDDR4__PI_MR16_DATA_0__REG DENALI_PI_260
-#define LPDDR4__PI_MR16_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR16_DATA_0
-
-#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_260__PI_MR17_DATA_0_WIDTH 8U
-#define LPDDR4__PI_MR17_DATA_0__REG DENALI_PI_260
-#define LPDDR4__PI_MR17_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR17_DATA_0
-
-#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_260__PI_MR20_DATA_0_WIDTH 8U
-#define LPDDR4__PI_MR20_DATA_0__REG DENALI_PI_260
-#define LPDDR4__PI_MR20_DATA_0__FLD LPDDR4__DENALI_PI_260__PI_MR20_DATA_0
-
-#define LPDDR4__DENALI_PI_261_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_261_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_261__PI_MR32_DATA_0_WIDTH 8U
-#define LPDDR4__PI_MR32_DATA_0__REG DENALI_PI_261
-#define LPDDR4__PI_MR32_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR32_DATA_0
-
-#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_261__PI_MR40_DATA_0_WIDTH 8U
-#define LPDDR4__PI_MR40_DATA_0__REG DENALI_PI_261
-#define LPDDR4__PI_MR40_DATA_0__FLD LPDDR4__DENALI_PI_261__PI_MR40_DATA_0
-
-#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_261__PI_MR13_DATA_1_WIDTH 8U
-#define LPDDR4__PI_MR13_DATA_1__REG DENALI_PI_261
-#define LPDDR4__PI_MR13_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR13_DATA_1
-
-#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_SHIFT 24U
-#define LPDDR4__DENALI_PI_261__PI_MR15_DATA_1_WIDTH 8U
-#define LPDDR4__PI_MR15_DATA_1__REG DENALI_PI_261
-#define LPDDR4__PI_MR15_DATA_1__FLD LPDDR4__DENALI_PI_261__PI_MR15_DATA_1
-
-#define LPDDR4__DENALI_PI_262_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_262_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_262__PI_MR16_DATA_1_WIDTH 8U
-#define LPDDR4__PI_MR16_DATA_1__REG DENALI_PI_262
-#define LPDDR4__PI_MR16_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR16_DATA_1
-
-#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_262__PI_MR17_DATA_1_WIDTH 8U
-#define LPDDR4__PI_MR17_DATA_1__REG DENALI_PI_262
-#define LPDDR4__PI_MR17_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR17_DATA_1
-
-#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_262__PI_MR20_DATA_1_WIDTH 8U
-#define LPDDR4__PI_MR20_DATA_1__REG DENALI_PI_262
-#define LPDDR4__PI_MR20_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR20_DATA_1
-
-#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_SHIFT 24U
-#define LPDDR4__DENALI_PI_262__PI_MR32_DATA_1_WIDTH 8U
-#define LPDDR4__PI_MR32_DATA_1__REG DENALI_PI_262
-#define LPDDR4__PI_MR32_DATA_1__FLD LPDDR4__DENALI_PI_262__PI_MR32_DATA_1
-
-#define LPDDR4__DENALI_PI_263_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_263_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_263__PI_MR40_DATA_1_WIDTH 8U
-#define LPDDR4__PI_MR40_DATA_1__REG DENALI_PI_263
-#define LPDDR4__PI_MR40_DATA_1__FLD LPDDR4__DENALI_PI_263__PI_MR40_DATA_1
-
-#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_263__PI_MR13_DATA_2_WIDTH 8U
-#define LPDDR4__PI_MR13_DATA_2__REG DENALI_PI_263
-#define LPDDR4__PI_MR13_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR13_DATA_2
-
-#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_SHIFT 16U
-#define LPDDR4__DENALI_PI_263__PI_MR15_DATA_2_WIDTH 8U
-#define LPDDR4__PI_MR15_DATA_2__REG DENALI_PI_263
-#define LPDDR4__PI_MR15_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR15_DATA_2
-
-#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_263__PI_MR16_DATA_2_WIDTH 8U
-#define LPDDR4__PI_MR16_DATA_2__REG DENALI_PI_263
-#define LPDDR4__PI_MR16_DATA_2__FLD LPDDR4__DENALI_PI_263__PI_MR16_DATA_2
-
-#define LPDDR4__DENALI_PI_264_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_264_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_264__PI_MR17_DATA_2_WIDTH 8U
-#define LPDDR4__PI_MR17_DATA_2__REG DENALI_PI_264
-#define LPDDR4__PI_MR17_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR17_DATA_2
-
-#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_264__PI_MR20_DATA_2_WIDTH 8U
-#define LPDDR4__PI_MR20_DATA_2__REG DENALI_PI_264
-#define LPDDR4__PI_MR20_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR20_DATA_2
-
-#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_SHIFT 16U
-#define LPDDR4__DENALI_PI_264__PI_MR32_DATA_2_WIDTH 8U
-#define LPDDR4__PI_MR32_DATA_2__REG DENALI_PI_264
-#define LPDDR4__PI_MR32_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR32_DATA_2
-
-#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_264__PI_MR40_DATA_2_WIDTH 8U
-#define LPDDR4__PI_MR40_DATA_2__REG DENALI_PI_264
-#define LPDDR4__PI_MR40_DATA_2__FLD LPDDR4__DENALI_PI_264__PI_MR40_DATA_2
-
-#define LPDDR4__DENALI_PI_265_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_265_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_265__PI_MR13_DATA_3_WIDTH 8U
-#define LPDDR4__PI_MR13_DATA_3__REG DENALI_PI_265
-#define LPDDR4__PI_MR13_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR13_DATA_3
-
-#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_265__PI_MR15_DATA_3_WIDTH 8U
-#define LPDDR4__PI_MR15_DATA_3__REG DENALI_PI_265
-#define LPDDR4__PI_MR15_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR15_DATA_3
-
-#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_265__PI_MR16_DATA_3_WIDTH 8U
-#define LPDDR4__PI_MR16_DATA_3__REG DENALI_PI_265
-#define LPDDR4__PI_MR16_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR16_DATA_3
-
-#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_SHIFT 24U
-#define LPDDR4__DENALI_PI_265__PI_MR17_DATA_3_WIDTH 8U
-#define LPDDR4__PI_MR17_DATA_3__REG DENALI_PI_265
-#define LPDDR4__PI_MR17_DATA_3__FLD LPDDR4__DENALI_PI_265__PI_MR17_DATA_3
-
-#define LPDDR4__DENALI_PI_266_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_266_WRITE_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_266__PI_MR20_DATA_3_WIDTH 8U
-#define LPDDR4__PI_MR20_DATA_3__REG DENALI_PI_266
-#define LPDDR4__PI_MR20_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR20_DATA_3
-
-#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_266__PI_MR32_DATA_3_WIDTH 8U
-#define LPDDR4__PI_MR32_DATA_3__REG DENALI_PI_266
-#define LPDDR4__PI_MR32_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR32_DATA_3
-
-#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_266__PI_MR40_DATA_3_WIDTH 8U
-#define LPDDR4__PI_MR40_DATA_3__REG DENALI_PI_266
-#define LPDDR4__PI_MR40_DATA_3__FLD LPDDR4__DENALI_PI_266__PI_MR40_DATA_3
-
-#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_266__PI_CKE_MUX_0_WIDTH 4U
-#define LPDDR4__PI_CKE_MUX_0__REG DENALI_PI_266
-#define LPDDR4__PI_CKE_MUX_0__FLD LPDDR4__DENALI_PI_266__PI_CKE_MUX_0
-
-#define LPDDR4__DENALI_PI_267_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_267_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_1_WIDTH 4U
-#define LPDDR4__PI_CKE_MUX_1__REG DENALI_PI_267
-#define LPDDR4__PI_CKE_MUX_1__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_1
-
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_2_WIDTH 4U
-#define LPDDR4__PI_CKE_MUX_2__REG DENALI_PI_267
-#define LPDDR4__PI_CKE_MUX_2__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_2
-
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_267__PI_CKE_MUX_3_WIDTH 4U
-#define LPDDR4__PI_CKE_MUX_3__REG DENALI_PI_267
-#define LPDDR4__PI_CKE_MUX_3__FLD LPDDR4__DENALI_PI_267__PI_CKE_MUX_3
-
-#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_267__PI_CS_MUX_0_WIDTH 4U
-#define LPDDR4__PI_CS_MUX_0__REG DENALI_PI_267
-#define LPDDR4__PI_CS_MUX_0__FLD LPDDR4__DENALI_PI_267__PI_CS_MUX_0
-
-#define LPDDR4__DENALI_PI_268_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_268_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_1_WIDTH 4U
-#define LPDDR4__PI_CS_MUX_1__REG DENALI_PI_268
-#define LPDDR4__PI_CS_MUX_1__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_1
-
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_2_WIDTH 4U
-#define LPDDR4__PI_CS_MUX_2__REG DENALI_PI_268
-#define LPDDR4__PI_CS_MUX_2__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_2
-
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_268__PI_CS_MUX_3_WIDTH 4U
-#define LPDDR4__PI_CS_MUX_3__REG DENALI_PI_268
-#define LPDDR4__PI_CS_MUX_3__FLD LPDDR4__DENALI_PI_268__PI_CS_MUX_3
-
-#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0_WIDTH 4U
-#define LPDDR4__PI_RESET_N_MUX_0__REG DENALI_PI_268
-#define LPDDR4__PI_RESET_N_MUX_0__FLD LPDDR4__DENALI_PI_268__PI_RESET_N_MUX_0
-
-#define LPDDR4__DENALI_PI_269_READ_MASK 0xFF0F0F0FU
-#define LPDDR4__DENALI_PI_269_WRITE_MASK 0xFF0F0F0FU
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1_WIDTH 4U
-#define LPDDR4__PI_RESET_N_MUX_1__REG DENALI_PI_269
-#define LPDDR4__PI_RESET_N_MUX_1__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_1
-
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2_WIDTH 4U
-#define LPDDR4__PI_RESET_N_MUX_2__REG DENALI_PI_269
-#define LPDDR4__PI_RESET_N_MUX_2__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_2
-
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3_WIDTH 4U
-#define LPDDR4__PI_RESET_N_MUX_3__REG DENALI_PI_269
-#define LPDDR4__PI_RESET_N_MUX_3__FLD LPDDR4__DENALI_PI_269__PI_RESET_N_MUX_3
-
-#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0_WIDTH 8U
-#define LPDDR4__PI_MRSINGLE_DATA_0__REG DENALI_PI_269
-#define LPDDR4__PI_MRSINGLE_DATA_0__FLD LPDDR4__DENALI_PI_269__PI_MRSINGLE_DATA_0
-
-#define LPDDR4__DENALI_PI_270_READ_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_270_WRITE_MASK 0x0FFFFFFFU
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1_WIDTH 8U
-#define LPDDR4__PI_MRSINGLE_DATA_1__REG DENALI_PI_270
-#define LPDDR4__PI_MRSINGLE_DATA_1__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_1
-
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2_WIDTH 8U
-#define LPDDR4__PI_MRSINGLE_DATA_2__REG DENALI_PI_270
-#define LPDDR4__PI_MRSINGLE_DATA_2__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_2
-
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3_WIDTH 8U
-#define LPDDR4__PI_MRSINGLE_DATA_3__REG DENALI_PI_270
-#define LPDDR4__PI_MRSINGLE_DATA_3__FLD LPDDR4__DENALI_PI_270__PI_MRSINGLE_DATA_3
-
-#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0_WIDTH 4U
-#define LPDDR4__PI_ZQ_CAL_START_MAP_0__REG DENALI_PI_270
-#define LPDDR4__PI_ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_PI_270__PI_ZQ_CAL_START_MAP_0
-
-#define LPDDR4__DENALI_PI_271_READ_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_271_WRITE_MASK 0x0F0F0F0FU
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0_WIDTH 4U
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__REG DENALI_PI_271
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_0
-
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1_WIDTH 4U
-#define LPDDR4__PI_ZQ_CAL_START_MAP_1__REG DENALI_PI_271
-#define LPDDR4__PI_ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_1
-
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1_WIDTH 4U
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__REG DENALI_PI_271
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_LATCH_MAP_1
-
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_MASK 0x0F000000U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2_WIDTH 4U
-#define LPDDR4__PI_ZQ_CAL_START_MAP_2__REG DENALI_PI_271
-#define LPDDR4__PI_ZQ_CAL_START_MAP_2__FLD LPDDR4__DENALI_PI_271__PI_ZQ_CAL_START_MAP_2
-
-#define LPDDR4__DENALI_PI_272_READ_MASK 0x000F0F0FU
-#define LPDDR4__DENALI_PI_272_WRITE_MASK 0x000F0F0FU
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_MASK 0x0000000FU
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2_WIDTH 4U
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__REG DENALI_PI_272
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_2__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_2
-
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_MASK 0x00000F00U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3_WIDTH 4U
-#define LPDDR4__PI_ZQ_CAL_START_MAP_3__REG DENALI_PI_272
-#define LPDDR4__PI_ZQ_CAL_START_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_START_MAP_3
-
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_MASK 0x000F0000U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3_WIDTH 4U
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__REG DENALI_PI_272
-#define LPDDR4__PI_ZQ_CAL_LATCH_MAP_3__FLD LPDDR4__DENALI_PI_272__PI_ZQ_CAL_LATCH_MAP_3
-
-#define LPDDR4__DENALI_PI_273_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_273_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0_WIDTH 16U
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__REG DENALI_PI_273
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_0_0
-
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0_WIDTH 16U
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__REG DENALI_PI_273
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_0__FLD LPDDR4__DENALI_PI_273__PI_DQS_OSC_BASE_VALUE_1_0
-
-#define LPDDR4__DENALI_PI_274_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_274_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_MASK 0x0000FFFFU
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1_WIDTH 16U
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__REG DENALI_PI_274
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_0_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_0_1
-
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_MASK 0xFFFF0000U
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1_WIDTH 16U
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__REG DENALI_PI_274
-#define LPDDR4__PI_DQS_OSC_BASE_VALUE_1_1__FLD LPDDR4__DENALI_PI_274__PI_DQS_OSC_BASE_VALUE_1_1
-
-#define LPDDR4__DENALI_PI_275_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_275_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F0_0__REG DENALI_PI_275
-#define LPDDR4__PI_MR1_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR1_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F0_0__REG DENALI_PI_275
-#define LPDDR4__PI_MR2_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR2_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F0_0__REG DENALI_PI_275
-#define LPDDR4__PI_MR3_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR3_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F0_0__REG DENALI_PI_275
-#define LPDDR4__PI_MR11_DATA_F0_0__FLD LPDDR4__DENALI_PI_275__PI_MR11_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_276_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_276_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F0_0__REG DENALI_PI_276
-#define LPDDR4__PI_MR12_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR12_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F0_0__REG DENALI_PI_276
-#define LPDDR4__PI_MR14_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR14_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F0_0__REG DENALI_PI_276
-#define LPDDR4__PI_MR22_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR22_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F0_0__REG DENALI_PI_276
-#define LPDDR4__PI_MR23_DATA_F0_0__FLD LPDDR4__DENALI_PI_276__PI_MR23_DATA_F0_0
-
-#define LPDDR4__DENALI_PI_277_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_277_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F1_0__REG DENALI_PI_277
-#define LPDDR4__PI_MR1_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR1_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F1_0__REG DENALI_PI_277
-#define LPDDR4__PI_MR2_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR2_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F1_0__REG DENALI_PI_277
-#define LPDDR4__PI_MR3_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR3_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F1_0__REG DENALI_PI_277
-#define LPDDR4__PI_MR11_DATA_F1_0__FLD LPDDR4__DENALI_PI_277__PI_MR11_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_278_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_278_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F1_0__REG DENALI_PI_278
-#define LPDDR4__PI_MR12_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR12_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F1_0__REG DENALI_PI_278
-#define LPDDR4__PI_MR14_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR14_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F1_0__REG DENALI_PI_278
-#define LPDDR4__PI_MR22_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR22_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F1_0__REG DENALI_PI_278
-#define LPDDR4__PI_MR23_DATA_F1_0__FLD LPDDR4__DENALI_PI_278__PI_MR23_DATA_F1_0
-
-#define LPDDR4__DENALI_PI_279_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_279_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F2_0__REG DENALI_PI_279
-#define LPDDR4__PI_MR1_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR1_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F2_0__REG DENALI_PI_279
-#define LPDDR4__PI_MR2_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR2_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F2_0__REG DENALI_PI_279
-#define LPDDR4__PI_MR3_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR3_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F2_0__REG DENALI_PI_279
-#define LPDDR4__PI_MR11_DATA_F2_0__FLD LPDDR4__DENALI_PI_279__PI_MR11_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_280_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_280_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_SHIFT 0U
-#define LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F2_0__REG DENALI_PI_280
-#define LPDDR4__PI_MR12_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR12_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_SHIFT 8U
-#define LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F2_0__REG DENALI_PI_280
-#define LPDDR4__PI_MR14_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR14_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_SHIFT 16U
-#define LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F2_0__REG DENALI_PI_280
-#define LPDDR4__PI_MR22_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR22_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_SHIFT 24U
-#define LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F2_0__REG DENALI_PI_280
-#define LPDDR4__PI_MR23_DATA_F2_0__FLD LPDDR4__DENALI_PI_280__PI_MR23_DATA_F2_0
-
-#define LPDDR4__DENALI_PI_281_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_281_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F0_1__REG DENALI_PI_281
-#define LPDDR4__PI_MR1_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR1_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F0_1__REG DENALI_PI_281
-#define LPDDR4__PI_MR2_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR2_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F0_1__REG DENALI_PI_281
-#define LPDDR4__PI_MR3_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR3_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_SHIFT 24U
-#define LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F0_1__REG DENALI_PI_281
-#define LPDDR4__PI_MR11_DATA_F0_1__FLD LPDDR4__DENALI_PI_281__PI_MR11_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_282_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_282_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F0_1__REG DENALI_PI_282
-#define LPDDR4__PI_MR12_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR12_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F0_1__REG DENALI_PI_282
-#define LPDDR4__PI_MR14_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR14_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F0_1__REG DENALI_PI_282
-#define LPDDR4__PI_MR22_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR22_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_SHIFT 24U
-#define LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F0_1__REG DENALI_PI_282
-#define LPDDR4__PI_MR23_DATA_F0_1__FLD LPDDR4__DENALI_PI_282__PI_MR23_DATA_F0_1
-
-#define LPDDR4__DENALI_PI_283_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_283_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F1_1__REG DENALI_PI_283
-#define LPDDR4__PI_MR1_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR1_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F1_1__REG DENALI_PI_283
-#define LPDDR4__PI_MR2_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR2_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F1_1__REG DENALI_PI_283
-#define LPDDR4__PI_MR3_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR3_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_SHIFT 24U
-#define LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F1_1__REG DENALI_PI_283
-#define LPDDR4__PI_MR11_DATA_F1_1__FLD LPDDR4__DENALI_PI_283__PI_MR11_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_284_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_284_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F1_1__REG DENALI_PI_284
-#define LPDDR4__PI_MR12_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR12_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F1_1__REG DENALI_PI_284
-#define LPDDR4__PI_MR14_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR14_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F1_1__REG DENALI_PI_284
-#define LPDDR4__PI_MR22_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR22_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_SHIFT 24U
-#define LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F1_1__REG DENALI_PI_284
-#define LPDDR4__PI_MR23_DATA_F1_1__FLD LPDDR4__DENALI_PI_284__PI_MR23_DATA_F1_1
-
-#define LPDDR4__DENALI_PI_285_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_285_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F2_1__REG DENALI_PI_285
-#define LPDDR4__PI_MR1_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR1_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F2_1__REG DENALI_PI_285
-#define LPDDR4__PI_MR2_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR2_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F2_1__REG DENALI_PI_285
-#define LPDDR4__PI_MR3_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR3_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_SHIFT 24U
-#define LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F2_1__REG DENALI_PI_285
-#define LPDDR4__PI_MR11_DATA_F2_1__FLD LPDDR4__DENALI_PI_285__PI_MR11_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_286_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_286_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_SHIFT 0U
-#define LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F2_1__REG DENALI_PI_286
-#define LPDDR4__PI_MR12_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR12_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_SHIFT 8U
-#define LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F2_1__REG DENALI_PI_286
-#define LPDDR4__PI_MR14_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR14_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_SHIFT 16U
-#define LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F2_1__REG DENALI_PI_286
-#define LPDDR4__PI_MR22_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR22_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_SHIFT 24U
-#define LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F2_1__REG DENALI_PI_286
-#define LPDDR4__PI_MR23_DATA_F2_1__FLD LPDDR4__DENALI_PI_286__PI_MR23_DATA_F2_1
-
-#define LPDDR4__DENALI_PI_287_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_287_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F0_2__REG DENALI_PI_287
-#define LPDDR4__PI_MR1_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR1_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F0_2__REG DENALI_PI_287
-#define LPDDR4__PI_MR2_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR2_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_SHIFT 16U
-#define LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F0_2__REG DENALI_PI_287
-#define LPDDR4__PI_MR3_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR3_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F0_2__REG DENALI_PI_287
-#define LPDDR4__PI_MR11_DATA_F0_2__FLD LPDDR4__DENALI_PI_287__PI_MR11_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_288_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_288_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F0_2__REG DENALI_PI_288
-#define LPDDR4__PI_MR12_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR12_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F0_2__REG DENALI_PI_288
-#define LPDDR4__PI_MR14_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR14_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_SHIFT 16U
-#define LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F0_2__REG DENALI_PI_288
-#define LPDDR4__PI_MR22_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR22_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F0_2__REG DENALI_PI_288
-#define LPDDR4__PI_MR23_DATA_F0_2__FLD LPDDR4__DENALI_PI_288__PI_MR23_DATA_F0_2
-
-#define LPDDR4__DENALI_PI_289_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_289_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F1_2__REG DENALI_PI_289
-#define LPDDR4__PI_MR1_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR1_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F1_2__REG DENALI_PI_289
-#define LPDDR4__PI_MR2_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR2_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_SHIFT 16U
-#define LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F1_2__REG DENALI_PI_289
-#define LPDDR4__PI_MR3_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR3_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F1_2__REG DENALI_PI_289
-#define LPDDR4__PI_MR11_DATA_F1_2__FLD LPDDR4__DENALI_PI_289__PI_MR11_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_290_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_290_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F1_2__REG DENALI_PI_290
-#define LPDDR4__PI_MR12_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR12_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F1_2__REG DENALI_PI_290
-#define LPDDR4__PI_MR14_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR14_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_SHIFT 16U
-#define LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F1_2__REG DENALI_PI_290
-#define LPDDR4__PI_MR22_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR22_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F1_2__REG DENALI_PI_290
-#define LPDDR4__PI_MR23_DATA_F1_2__FLD LPDDR4__DENALI_PI_290__PI_MR23_DATA_F1_2
-
-#define LPDDR4__DENALI_PI_291_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_291_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F2_2__REG DENALI_PI_291
-#define LPDDR4__PI_MR1_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR1_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F2_2__REG DENALI_PI_291
-#define LPDDR4__PI_MR2_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR2_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_SHIFT 16U
-#define LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F2_2__REG DENALI_PI_291
-#define LPDDR4__PI_MR3_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR3_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F2_2__REG DENALI_PI_291
-#define LPDDR4__PI_MR11_DATA_F2_2__FLD LPDDR4__DENALI_PI_291__PI_MR11_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_292_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_292_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_SHIFT 0U
-#define LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F2_2__REG DENALI_PI_292
-#define LPDDR4__PI_MR12_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR12_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_SHIFT 8U
-#define LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F2_2__REG DENALI_PI_292
-#define LPDDR4__PI_MR14_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR14_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_SHIFT 16U
-#define LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F2_2__REG DENALI_PI_292
-#define LPDDR4__PI_MR22_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR22_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_SHIFT 24U
-#define LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F2_2__REG DENALI_PI_292
-#define LPDDR4__PI_MR23_DATA_F2_2__FLD LPDDR4__DENALI_PI_292__PI_MR23_DATA_F2_2
-
-#define LPDDR4__DENALI_PI_293_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_293_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F0_3__REG DENALI_PI_293
-#define LPDDR4__PI_MR1_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR1_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F0_3__REG DENALI_PI_293
-#define LPDDR4__PI_MR2_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR2_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F0_3__REG DENALI_PI_293
-#define LPDDR4__PI_MR3_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR3_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_SHIFT 24U
-#define LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F0_3__REG DENALI_PI_293
-#define LPDDR4__PI_MR11_DATA_F0_3__FLD LPDDR4__DENALI_PI_293__PI_MR11_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_294_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_294_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F0_3__REG DENALI_PI_294
-#define LPDDR4__PI_MR12_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR12_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F0_3__REG DENALI_PI_294
-#define LPDDR4__PI_MR14_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR14_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F0_3__REG DENALI_PI_294
-#define LPDDR4__PI_MR22_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR22_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_SHIFT 24U
-#define LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F0_3__REG DENALI_PI_294
-#define LPDDR4__PI_MR23_DATA_F0_3__FLD LPDDR4__DENALI_PI_294__PI_MR23_DATA_F0_3
-
-#define LPDDR4__DENALI_PI_295_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_295_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F1_3__REG DENALI_PI_295
-#define LPDDR4__PI_MR1_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR1_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F1_3__REG DENALI_PI_295
-#define LPDDR4__PI_MR2_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR2_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F1_3__REG DENALI_PI_295
-#define LPDDR4__PI_MR3_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR3_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_SHIFT 24U
-#define LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F1_3__REG DENALI_PI_295
-#define LPDDR4__PI_MR11_DATA_F1_3__FLD LPDDR4__DENALI_PI_295__PI_MR11_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_296_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_296_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F1_3__REG DENALI_PI_296
-#define LPDDR4__PI_MR12_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR12_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F1_3__REG DENALI_PI_296
-#define LPDDR4__PI_MR14_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR14_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F1_3__REG DENALI_PI_296
-#define LPDDR4__PI_MR22_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR22_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_SHIFT 24U
-#define LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F1_3__REG DENALI_PI_296
-#define LPDDR4__PI_MR23_DATA_F1_3__FLD LPDDR4__DENALI_PI_296__PI_MR23_DATA_F1_3
-
-#define LPDDR4__DENALI_PI_297_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_297_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3_WIDTH 8U
-#define LPDDR4__PI_MR1_DATA_F2_3__REG DENALI_PI_297
-#define LPDDR4__PI_MR1_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR1_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3_WIDTH 8U
-#define LPDDR4__PI_MR2_DATA_F2_3__REG DENALI_PI_297
-#define LPDDR4__PI_MR2_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR2_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3_WIDTH 8U
-#define LPDDR4__PI_MR3_DATA_F2_3__REG DENALI_PI_297
-#define LPDDR4__PI_MR3_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR3_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_SHIFT 24U
-#define LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3_WIDTH 8U
-#define LPDDR4__PI_MR11_DATA_F2_3__REG DENALI_PI_297
-#define LPDDR4__PI_MR11_DATA_F2_3__FLD LPDDR4__DENALI_PI_297__PI_MR11_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_298_READ_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_298_WRITE_MASK 0xFFFFFFFFU
-#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_MASK 0x000000FFU
-#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_SHIFT 0U
-#define LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3_WIDTH 8U
-#define LPDDR4__PI_MR12_DATA_F2_3__REG DENALI_PI_298
-#define LPDDR4__PI_MR12_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR12_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_MASK 0x0000FF00U
-#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_SHIFT 8U
-#define LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3_WIDTH 8U
-#define LPDDR4__PI_MR14_DATA_F2_3__REG DENALI_PI_298
-#define LPDDR4__PI_MR14_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR14_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_MASK 0x00FF0000U
-#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_SHIFT 16U
-#define LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3_WIDTH 8U
-#define LPDDR4__PI_MR22_DATA_F2_3__REG DENALI_PI_298
-#define LPDDR4__PI_MR22_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR22_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_MASK 0xFF000000U
-#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_SHIFT 24U
-#define LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3_WIDTH 8U
-#define LPDDR4__PI_MR23_DATA_F2_3__REG DENALI_PI_298
-#define LPDDR4__PI_MR23_DATA_F2_3__FLD LPDDR4__DENALI_PI_298__PI_MR23_DATA_F2_3
-
-#define LPDDR4__DENALI_PI_299_READ_MASK 0x000007FFU
-#define LPDDR4__DENALI_PI_299_WRITE_MASK 0x000007FFU
-#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_MASK 0x000007FFU
-#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_SHIFT 0U
-#define LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF_WIDTH 11U
-#define LPDDR4__PI_PARITY_ERROR_REGIF__REG DENALI_PI_299
-#define LPDDR4__PI_PARITY_ERROR_REGIF__FLD LPDDR4__DENALI_PI_299__PI_PARITY_ERROR_REGIF
-
-#endif /* REG_LPDDR4_PI_MACROS_H_ */
diff --git a/drivers/ram/k3-j721e/lpddr4_sanity.h b/drivers/ram/k3-j721e/lpddr4_sanity.h
deleted file mode 100644
index 0f0fc27..0000000
--- a/drivers/ram/k3-j721e/lpddr4_sanity.h
+++ /dev/null
@@ -1,1165 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- * api-generator: 12.02.13bb8d5
- * Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-
-/**
- * This file contains sanity API functions. The purpose of sanity functions
- * is to check input parameters validity. They take the same parameters as
- * original API functions and return 0 on success or EINVAL on wrong parameter
- * value(s).
- */
-
-#ifndef LPDDR4_SANITY_H
-#define LPDDR4_SANITY_H
-
-#include <errno.h>
-#include <linux/types.h>
-#include "lpddr4_if.h"
-
-#define CDN_EOK 0U /* no error */
-
-static inline uint32_t lpddr4_configsf(const lpddr4_config *obj);
-static inline uint32_t lpddr4_privatedatasf(const lpddr4_privatedata *obj);
-static inline uint32_t lpddr4_reginitdatasf(const lpddr4_reginitdata *obj);
-
-static inline uint32_t lpddr4_sanityfunction1(const lpddr4_config* config, const uint16_t* configsize);
-static inline uint32_t lpddr4_sanityfunction2(const lpddr4_privatedata* pd, const lpddr4_config* cfg);
-static inline uint32_t lpddr4_sanityfunction3(const lpddr4_privatedata* pd);
-static inline uint32_t lpddr4_sanityfunction4(const lpddr4_privatedata* pd, const lpddr4_regblock cpp, const uint32_t* regvalue);
-static inline uint32_t lpddr4_sanityfunction5(const lpddr4_privatedata* pd, const lpddr4_regblock cpp);
-static inline uint32_t lpddr4_sanityfunction6(const lpddr4_privatedata* pd, const uint64_t* mmrvalue, const uint8_t* mmrstatus);
-static inline uint32_t lpddr4_sanityfunction7(const lpddr4_privatedata* pd, const uint8_t* mrwstatus);
-static inline uint32_t lpddr4_sanityfunction8(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-static inline uint32_t lpddr4_sanityfunction11(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
-static inline uint32_t lpddr4_sanityfunction14(const lpddr4_privatedata* pd, const uint64_t* mask);
-static inline uint32_t lpddr4_sanityfunction15(const lpddr4_privatedata* pd, const uint64_t* mask);
-static inline uint32_t lpddr4_sanityfunction16(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr, const bool* irqstatus);
-static inline uint32_t lpddr4_sanityfunction17(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr);
-static inline uint32_t lpddr4_sanityfunction18(const lpddr4_privatedata* pd, const uint32_t* mask);
-static inline uint32_t lpddr4_sanityfunction20(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr, const bool* irqstatus);
-static inline uint32_t lpddr4_sanityfunction21(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr);
-static inline uint32_t lpddr4_sanityfunction22(const lpddr4_privatedata* pd, const lpddr4_debuginfo* debuginfo);
-static inline uint32_t lpddr4_sanityfunction23(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-static inline uint32_t lpddr4_sanityfunction25(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
-static inline uint32_t lpddr4_sanityfunction26(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
-static inline uint32_t lpddr4_sanityfunction27(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
-static inline uint32_t lpddr4_sanityfunction28(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
-static inline uint32_t lpddr4_sanityfunction29(const lpddr4_privatedata* pd, const bool* on_off);
-static inline uint32_t lpddr4_sanityfunction31(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
-static inline uint32_t lpddr4_sanityfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
-
-#define lpddr4_probesf lpddr4_sanityfunction1
-#define lpddr4_initsf lpddr4_sanityfunction2
-#define lpddr4_startsf lpddr4_sanityfunction3
-#define lpddr4_readregsf lpddr4_sanityfunction4
-#define lpddr4_writeregsf lpddr4_sanityfunction5
-#define lpddr4_getmmrregistersf lpddr4_sanityfunction6
-#define lpddr4_setmmrregistersf lpddr4_sanityfunction7
-#define lpddr4_writectlconfigsf lpddr4_sanityfunction8
-#define lpddr4_writephyconfigsf lpddr4_sanityfunction8
-#define lpddr4_writephyindepconfigsf lpddr4_sanityfunction8
-#define lpddr4_readctlconfigsf lpddr4_sanityfunction11
-#define lpddr4_readphyconfigsf lpddr4_sanityfunction11
-#define lpddr4_readphyindepconfigsf lpddr4_sanityfunction11
-#define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14
-#define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15
-#define lpddr4_checkctlinterruptsf lpddr4_sanityfunction16
-#define lpddr4_ackctlinterruptsf lpddr4_sanityfunction17
-#define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction18
-#define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction18
-#define lpddr4_checkphyindepinterrupsf lpddr4_sanityfunction20
-#define lpddr4_ackphyindepinterruptsf lpddr4_sanityfunction21
-#define lpddr4_getdebuginitinfosf lpddr4_sanityfunction22
-#define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction23
-#define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction23
-#define lpddr4_geteccenablesf lpddr4_sanityfunction25
-#define lpddr4_seteccenablesf lpddr4_sanityfunction26
-#define lpddr4_getreducmodesf lpddr4_sanityfunction27
-#define lpddr4_setreducmodesf lpddr4_sanityfunction28
-#define lpddr4_getdbireadmodesf lpddr4_sanityfunction29
-#define lpddr4_getdbiwritemodesf lpddr4_sanityfunction29
-#define lpddr4_setdbimodesf lpddr4_sanityfunction31
-#define lpddr4_getrefreshratesf lpddr4_sanityfunction32
-#define lpddr4_setrefreshratesf lpddr4_sanityfunction32
-#define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
-
-/**
- * Function to validate struct Config
- *
- * @param[in] obj pointer to struct to be verified
- * @returns 0 for valid
- * @returns EINVAL for invalid
- */
-static inline uint32_t lpddr4_configsf(const lpddr4_config *obj)
-{
- uint32_t ret = 0;
-
- if (obj == NULL)
- {
- ret = EINVAL;
- }
-
- return ret;
-}
-
-/**
- * Function to validate struct PrivateData
- *
- * @param[in] obj pointer to struct to be verified
- * @returns 0 for valid
- * @returns EINVAL for invalid
- */
-static inline uint32_t lpddr4_privatedatasf(const lpddr4_privatedata *obj)
-{
- uint32_t ret = 0;
-
- if (obj == NULL)
- {
- ret = EINVAL;
- }
-
- return ret;
-}
-
-/**
- * Function to validate struct RegInitData
- *
- * @param[in] obj pointer to struct to be verified
- * @returns 0 for valid
- * @returns EINVAL for invalid
- */
-static inline uint32_t lpddr4_reginitdatasf(const lpddr4_reginitdata *obj)
-{
- uint32_t ret = 0;
-
- if (obj == NULL)
- {
- ret = EINVAL;
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] config Driver/hardware configuration required.
- * @param[out] configSize Size of memory allocations required.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction1(const lpddr4_config* config, const uint16_t* configsize)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (configsize == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_configsf(config) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cfg Specifies driver/hardware configuration.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction2(const lpddr4_privatedata* pd, const lpddr4_config* cfg)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_configsf(cfg) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction3(const lpddr4_privatedata* pd)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @param[out] regValue Register value read
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction4(const lpddr4_privatedata* pd, const lpddr4_regblock cpp, const uint32_t* regvalue)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (regvalue == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (cpp != LPDDR4_CTL_REGS) &&
- (cpp != LPDDR4_PHY_REGS) &&
- (cpp != LPDDR4_PHY_INDEP_REGS)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction5(const lpddr4_privatedata* pd, const lpddr4_regblock cpp)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (cpp != LPDDR4_CTL_REGS) &&
- (cpp != LPDDR4_PHY_REGS) &&
- (cpp != LPDDR4_PHY_INDEP_REGS)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
- * @param[out] mmrStatus Status of mode register read(mrr) instruction.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction6(const lpddr4_privatedata* pd, const uint64_t* mmrvalue, const uint8_t* mmrstatus)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (mmrvalue == NULL)
- {
- ret = EINVAL;
- }
- else if (mmrstatus == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mrwStatus Status of mode register write(mrw) instruction.
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction7(const lpddr4_privatedata* pd, const uint8_t* mrwstatus)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (mrwstatus == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] regValues Register values to be written
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction8(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_reginitdatasf(regvalues) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] regValues Register values which are read
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction11(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (regvalues == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction14(const lpddr4_privatedata* pd, const uint64_t* mask)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (mask == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mask Value of interrupt mask to be written
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction15(const lpddr4_privatedata* pd, const uint64_t* mask)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (mask == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction16(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr, const bool* irqstatus)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (irqstatus == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (intr != LPDDR4_RESET_DONE) &&
- (intr != LPDDR4_BUS_ACCESS_ERROR) &&
- (intr != LPDDR4_MULTIPLE_BUS_ACCESS_ERROR) &&
- (intr != LPDDR4_ECC_MULTIPLE_CORR_ERROR) &&
- (intr != LPDDR4_ECC_MULTIPLE_UNCORR_ERROR) &&
- (intr != LPDDR4_ECC_WRITEBACK_EXEC_ERROR) &&
- (intr != LPDDR4_ECC_SCRUB_DONE) &&
- (intr != LPDDR4_ECC_SCRUB_ERROR) &&
- (intr != LPDDR4_PORT_COMMAND_ERROR) &&
- (intr != LPDDR4_MC_INIT_DONE) &&
- (intr != LPDDR4_LP_DONE) &&
- (intr != LPDDR4_BIST_DONE) &&
- (intr != LPDDR4_WRAP_ERROR) &&
- (intr != LPDDR4_INVALID_BURST_ERROR) &&
- (intr != LPDDR4_RDLVL_ERROR) &&
- (intr != LPDDR4_RDLVL_GATE_ERROR) &&
- (intr != LPDDR4_WRLVL_ERROR) &&
- (intr != LPDDR4_CA_TRAINING_ERROR) &&
- (intr != LPDDR4_DFI_UPDATE_ERROR) &&
- (intr != LPDDR4_MRR_ERROR) &&
- (intr != LPDDR4_PHY_MASTER_ERROR) &&
- (intr != LPDDR4_WRLVL_REQ) &&
- (intr != LPDDR4_RDLVL_REQ) &&
- (intr != LPDDR4_RDLVL_GATE_REQ) &&
- (intr != LPDDR4_CA_TRAINING_REQ) &&
- (intr != LPDDR4_LEVELING_DONE) &&
- (intr != LPDDR4_PHY_ERROR) &&
- (intr != LPDDR4_MR_READ_DONE) &&
- (intr != LPDDR4_TEMP_CHANGE) &&
- (intr != LPDDR4_TEMP_ALERT) &&
- (intr != LPDDR4_SW_DQS_COMPLETE) &&
- (intr != LPDDR4_DQS_OSC_BV_UPDATED) &&
- (intr != LPDDR4_DQS_OSC_OVERFLOW) &&
- (intr != LPDDR4_DQS_OSC_VAR_OUT) &&
- (intr != LPDDR4_MR_WRITE_DONE) &&
- (intr != LPDDR4_INHIBIT_DRAM_DONE) &&
- (intr != LPDDR4_DFI_INIT_STATE) &&
- (intr != LPDDR4_DLL_RESYNC_DONE) &&
- (intr != LPDDR4_TDFI_TO) &&
- (intr != LPDDR4_DFS_DONE) &&
- (intr != LPDDR4_DFS_STATUS) &&
- (intr != LPDDR4_REFRESH_STATUS) &&
- (intr != LPDDR4_ZQ_STATUS) &&
- (intr != LPDDR4_SW_REQ_MODE) &&
- (intr != LPDDR4_LOR_BITS)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction17(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (intr != LPDDR4_RESET_DONE) &&
- (intr != LPDDR4_BUS_ACCESS_ERROR) &&
- (intr != LPDDR4_MULTIPLE_BUS_ACCESS_ERROR) &&
- (intr != LPDDR4_ECC_MULTIPLE_CORR_ERROR) &&
- (intr != LPDDR4_ECC_MULTIPLE_UNCORR_ERROR) &&
- (intr != LPDDR4_ECC_WRITEBACK_EXEC_ERROR) &&
- (intr != LPDDR4_ECC_SCRUB_DONE) &&
- (intr != LPDDR4_ECC_SCRUB_ERROR) &&
- (intr != LPDDR4_PORT_COMMAND_ERROR) &&
- (intr != LPDDR4_MC_INIT_DONE) &&
- (intr != LPDDR4_LP_DONE) &&
- (intr != LPDDR4_BIST_DONE) &&
- (intr != LPDDR4_WRAP_ERROR) &&
- (intr != LPDDR4_INVALID_BURST_ERROR) &&
- (intr != LPDDR4_RDLVL_ERROR) &&
- (intr != LPDDR4_RDLVL_GATE_ERROR) &&
- (intr != LPDDR4_WRLVL_ERROR) &&
- (intr != LPDDR4_CA_TRAINING_ERROR) &&
- (intr != LPDDR4_DFI_UPDATE_ERROR) &&
- (intr != LPDDR4_MRR_ERROR) &&
- (intr != LPDDR4_PHY_MASTER_ERROR) &&
- (intr != LPDDR4_WRLVL_REQ) &&
- (intr != LPDDR4_RDLVL_REQ) &&
- (intr != LPDDR4_RDLVL_GATE_REQ) &&
- (intr != LPDDR4_CA_TRAINING_REQ) &&
- (intr != LPDDR4_LEVELING_DONE) &&
- (intr != LPDDR4_PHY_ERROR) &&
- (intr != LPDDR4_MR_READ_DONE) &&
- (intr != LPDDR4_TEMP_CHANGE) &&
- (intr != LPDDR4_TEMP_ALERT) &&
- (intr != LPDDR4_SW_DQS_COMPLETE) &&
- (intr != LPDDR4_DQS_OSC_BV_UPDATED) &&
- (intr != LPDDR4_DQS_OSC_OVERFLOW) &&
- (intr != LPDDR4_DQS_OSC_VAR_OUT) &&
- (intr != LPDDR4_MR_WRITE_DONE) &&
- (intr != LPDDR4_INHIBIT_DRAM_DONE) &&
- (intr != LPDDR4_DFI_INIT_STATE) &&
- (intr != LPDDR4_DLL_RESYNC_DONE) &&
- (intr != LPDDR4_TDFI_TO) &&
- (intr != LPDDR4_DFS_DONE) &&
- (intr != LPDDR4_DFS_STATUS) &&
- (intr != LPDDR4_REFRESH_STATUS) &&
- (intr != LPDDR4_ZQ_STATUS) &&
- (intr != LPDDR4_SW_REQ_MODE) &&
- (intr != LPDDR4_LOR_BITS)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mask Value of interrupt mask
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction18(const lpddr4_privatedata* pd, const uint32_t* mask)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (mask == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be checked
- * @param[out] irqStatus Status of the interrupt, TRUE if active
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction20(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr, const bool* irqstatus)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (irqstatus == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (intr != LPDDR4_PHY_INDEP_INIT_DONE_BIT) &&
- (intr != LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_CALVL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_RDLVL_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_WRLVL_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_CALVL_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_LVL_DONE_BIT) &&
- (intr != LPDDR4_PHY_INDEP_BIST_DONE_BIT) &&
- (intr != LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
- (intr != LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] intr Interrupt to be acknowledged
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction21(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (intr != LPDDR4_PHY_INDEP_INIT_DONE_BIT) &&
- (intr != LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_CALVL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT) &&
- (intr != LPDDR4_PHY_INDEP_RDLVL_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_WRLVL_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_CALVL_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT) &&
- (intr != LPDDR4_PHY_INDEP_LVL_DONE_BIT) &&
- (intr != LPDDR4_PHY_INDEP_BIST_DONE_BIT) &&
- (intr != LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
- (intr != LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] debugInfo status
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction22(const lpddr4_privatedata* pd, const lpddr4_debuginfo* debuginfo)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (debuginfo == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] lpiWakeUpParam LPI timing parameter
- * @param[in] fspNum Frequency copy
- * @param[out] cycles Timing value(in cycles)
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction23(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (lpiwakeupparam == NULL)
- {
- ret = EINVAL;
- }
- else if (fspnum == NULL)
- {
- ret = EINVAL;
- }
- else if (cycles == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) &&
- (*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) &&
- (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) &&
- (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) &&
- (*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) &&
- (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) &&
- (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN)
- )
- {
- ret = EINVAL;
- }
- else if (
- (*fspnum != LPDDR4_FSP_0) &&
- (*fspnum != LPDDR4_FSP_1) &&
- (*fspnum != LPDDR4_FSP_2)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] eccParam ECC parameter setting
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction25(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (eccparam == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] eccParam ECC control parameter setting
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction26(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (eccparam == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (*eccparam != LPDDR4_ECC_DISABLED) &&
- (*eccparam != LPDDR4_ECC_ENABLED) &&
- (*eccparam != LPDDR4_ECC_ERR_DETECT) &&
- (*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] mode Half Datapath setting
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction27(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (mode == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode Half Datapath setting
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction28(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (mode == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (*mode != LPDDR4_REDUC_ON) &&
- (*mode != LPDDR4_REDUC_OFF)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[out] on_off DBI read value
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction29(const lpddr4_privatedata* pd, const bool* on_off)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (on_off == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] mode status
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction31(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (mode == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (*mode != LPDDR4_DBI_RD_ON) &&
- (*mode != LPDDR4_DBI_RD_OFF) &&
- (*mode != LPDDR4_DBI_WR_ON) &&
- (*mode != LPDDR4_DBI_WR_OFF)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-/**
- * A common function to check the validity of API functions with
- * following parameter types
- * @param[in] pD Driver state info specific to this instance.
- * @param[in] fspNum Frequency set number
- * @param[out] cycles Refresh rate (in cycles)
- * @return 0 success
- * @return EINVAL invalid parameters
- */
-static inline uint32_t lpddr4_sanityfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles)
-{
- /* Declaring return variable */
- uint32_t ret = 0;
-
- if (fspnum == NULL)
- {
- ret = EINVAL;
- }
- else if (cycles == NULL)
- {
- ret = EINVAL;
- }
- else if (lpddr4_privatedatasf(pd) == EINVAL)
- {
- ret = EINVAL;
- }
- else if (
- (*fspnum != LPDDR4_FSP_0) &&
- (*fspnum != LPDDR4_FSP_1) &&
- (*fspnum != LPDDR4_FSP_2)
- )
- {
- ret = EINVAL;
- }
- else
- {
- /*
- * All 'if ... else if' constructs shall be terminated with an 'else' statement
- * (MISRA2012-RULE-15_7-3)
- */
- }
-
- return ret;
-}
-
-#endif /* LPDDR4_SANITY_H */
diff --git a/drivers/ram/k3-j721e/lpddr4_structs_if.h b/drivers/ram/k3-j721e/lpddr4_structs_if.h
deleted file mode 100644
index dc6dd35..0000000
--- a/drivers/ram/k3-j721e/lpddr4_structs_if.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause */
-/**********************************************************************
- * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
- **********************************************************************
- * WARNING: This file is auto-generated using api-generator utility.
- * api-generator: 12.02.13bb8d5
- * Do not edit it manually.
- **********************************************************************
- * Cadence Core Driver for LPDDR4.
- **********************************************************************
- */
-#ifndef LPDDR4_STRUCTS_IF_H
-#define LPDDR4_STRUCTS_IF_H
-
-#include <linux/types.h>
-#include "lpddr4_if.h"
-
-/** @defgroup DataStructure Dynamic Data Structures
- * This section defines the data structures used by the driver to provide
- * hardware information, modification and dynamic operation of the driver.
- * These data structures are defined in the header file of the core driver
- * and utilized by the API.
- * @{
- */
-
-/**********************************************************************
-* Structures and unions
-**********************************************************************/
-/**
- * Configuration of device.
- * Object of this type is used for probe and init functions.
- */
-struct lpddr4_config_s
-{
- /** Base address of controller registers */
- struct lpddr4_ctlregs_s* ctlbase;
- /** Information/warning handler */
- lpddr4_infocallback infohandler;
- /** Controller interrupt handler */
- lpddr4_ctlcallback ctlinterrupthandler;
- /** PHY Independent Module interrupt handler */
- lpddr4_phyindepcallback phyindepinterrupthandler;
-};
-
-/**
- * Structure contains private data for Core Driver that should not be used by
- * upper layers. This is not a part of API and manipulating of those data may cause
- * unpredictable behavior of Core Driver.
- */
-struct lpddr4_privatedata_s
-{
- /** Base address of controller registers */
- struct lpddr4_ctlregs_s* ctlbase;
- /** Information/warning handler */
- lpddr4_infocallback infohandler;
- /** Controller interrupt handler */
- lpddr4_ctlcallback ctlinterrupthandler;
- /** PHY Independent Module interrupt handler */
- lpddr4_phyindepcallback phyindepinterrupthandler;
-};
-
-/** Structure to contain debug information reported by the driver. */
-struct lpddr4_debuginfo_s
-{
- /** PLL Lock error. */
- bool pllerror;
- /** I/O calibration error. */
- bool iocaliberror;
- /** RX offset error. */
- bool rxoffseterror;
- /** CA training error. */
- bool catraingerror;
- /** Write levelling error. */
- bool wrlvlerror;
- /** Gate Level error. */
- bool gatelvlerror;
- /** Read Level error. */
- bool readlvlerror;
- /** Write DQ training error. */
- bool dqtrainingerror;
-};
-
-/** Frequency Set Point mode register values */
-struct lpddr4_fspmoderegs_s
-{
- /** MR1 register data for the FSP. */
- uint8_t mr1data_fn[LPDDR4_MAX_CS];
- /** MR2 register data for the FSP. */
- uint8_t mr2data_fn[LPDDR4_MAX_CS];
- /** MR3 register data for the FSP. */
- uint8_t mr3data_fn[LPDDR4_MAX_CS];
- /** MR11 register data for the FSP. */
- uint8_t mr11data_fn[LPDDR4_MAX_CS];
- /** MR12 register data for the FSP. */
- uint8_t mr12data_fn[LPDDR4_MAX_CS];
- /** MR13 register data for the FSP. */
- uint8_t mr13data_fn[LPDDR4_MAX_CS];
- /** MR14 register data for the FSP. */
- uint8_t mr14data_fn[LPDDR4_MAX_CS];
- /** MR22 register data for the selected frequency. */
- uint8_t mr22data_fn[LPDDR4_MAX_CS];
-};
-
-/** Structure to hold data set to initalise registers. */
-struct lpddr4_reginitdata_s
-{
- /** Register initialisation data for the Controller. */
- uint32_t denalictlreg[LPDDR4_CTL_REG_COUNT];
- /** Should be set to true, if the corresponding denaliCtlReg element has been updated. */
- bool updatectlreg[LPDDR4_CTL_REG_COUNT];
- /** Register initialisation data for PHY independent module. */
- uint32_t denaliphyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
- /** Should be set to true, if the corresponding denaliPhyIndepReg element has been updated. */
- bool updatephyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
- /** Register initialisation data for the PHY. */
- uint32_t denaliphyreg[LPDDR4_PHY_REG_COUNT];
- /** Should be set to true, if the corresponding denaliPhyReg element has been updated. */
- bool updatephyreg[LPDDR4_PHY_REG_COUNT];
-};
-
-#endif /* LPDDR4_STRUCTS_IF_H */
diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
index 08de692..0aaac02 100644
--- a/drivers/ram/sifive/Kconfig
+++ b/drivers/ram/sifive/Kconfig
@@ -5,9 +5,9 @@
help
This enables support for ram drivers of SiFive SoCs.
-config SIFIVE_FU540_DDR
- bool "SiFive FU540 DDR driver"
+config SIFIVE_DDR
+ bool "SiFive DDR driver"
depends on RAM_SIFIVE
- default y if TARGET_SIFIVE_UNLEASHED
+ default y if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
help
- This enables DDR support for the platforms based on SiFive FU540 SoC.
+ This enables DDR support for the platforms based on SiFive SoC.
diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile
index d66efec..4ef89f8 100644
--- a/drivers/ram/sifive/Makefile
+++ b/drivers/ram/sifive/Makefile
@@ -3,4 +3,4 @@
# Copyright (c) 2020 SiFive, Inc
#
-obj-$(CONFIG_SIFIVE_FU540_DDR) += fu540_ddr.o
+obj-$(CONFIG_SIFIVE_DDR) += sifive_ddr.o
diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/sifive_ddr.c
similarity index 81%
rename from drivers/ram/sifive/fu540_ddr.c
rename to drivers/ram/sifive/sifive_ddr.c
index c0653bb..ba18466 100644
--- a/drivers/ram/sifive/fu540_ddr.c
+++ b/drivers/ram/sifive/sifive_ddr.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
- * (C) Copyright 2020 SiFive, Inc.
+ * (C) Copyright 2020-2021 SiFive, Inc.
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
@@ -65,16 +65,16 @@
DECLARE_GLOBAL_DATA_PTR;
-struct fu540_ddrctl {
+struct sifive_ddrctl {
volatile u32 denali_ctl[265];
};
-struct fu540_ddrphy {
+struct sifive_ddrphy {
volatile u32 denali_phy[1215];
};
/**
- * struct fu540_ddr_info
+ * struct sifive_ddr_info
*
* @dev : pointer for the device
* @info : UCLASS RAM information
@@ -83,23 +83,23 @@
* @ctrl : DDR control base address
* @physical_filter_ctrl : DDR physical filter control base address
*/
-struct fu540_ddr_info {
+struct sifive_ddr_info {
struct udevice *dev;
struct ram_info info;
- struct fu540_ddrctl *ctl;
- struct fu540_ddrphy *phy;
+ struct sifive_ddrctl *ctl;
+ struct sifive_ddrphy *phy;
struct clk ddr_clk;
u32 *physical_filter_ctrl;
};
#if defined(CONFIG_SPL_BUILD)
-struct fu540_ddr_params {
- struct fu540_ddrctl pctl_regs;
- struct fu540_ddrphy phy_regs;
+struct sifive_ddr_params {
+ struct sifive_ddrctl pctl_regs;
+ struct sifive_ddrphy phy_regs;
};
struct sifive_dmc_plat {
- struct fu540_ddr_params ddr_params;
+ struct sifive_ddr_params ddr_params;
};
/*
@@ -118,7 +118,7 @@
}
}
-static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
+static void sifive_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
{
u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
@@ -135,8 +135,8 @@
0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
}
-static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
- u64 ddr_end)
+static void sifive_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
+ u64 ddr_end)
{
volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
@@ -149,7 +149,7 @@
filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);
}
-static void fu540_ddr_check_errata(u32 regbase, u32 updownreg)
+static void sifive_ddr_check_errata(u32 regbase, u32 updownreg)
{
u64 fails = 0;
u32 dq = 0;
@@ -202,7 +202,7 @@
}
}
-static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
+static u64 sifive_ddr_phy_fixup(volatile u32 *ddrphyreg)
{
u32 slicebase = 0;
@@ -213,7 +213,7 @@
for (u32 reg = 0; reg < 4; reg++) {
u32 updownreg = readl(regbase + reg + ddrphyreg);
- fu540_ddr_check_errata(regbase, updownreg);
+ sifive_ddr_check_errata(regbase, updownreg);
}
slicebase += 128;
}
@@ -221,18 +221,18 @@
return(0);
}
-static u32 fu540_ddr_get_dram_class(volatile u32 *ctl)
+static u32 sifive_ddr_get_dram_class(volatile u32 *ctl)
{
u32 reg = readl(DENALI_CTL_0 + ctl);
return ((reg >> DRAM_CLASS_OFFSET) & 0xF);
}
-static int fu540_ddr_setup(struct udevice *dev)
+static int sifive_ddr_setup(struct udevice *dev)
{
- struct fu540_ddr_info *priv = dev_get_priv(dev);
+ struct sifive_ddr_info *priv = dev_get_priv(dev);
struct sifive_dmc_plat *plat = dev_get_plat(dev);
- struct fu540_ddr_params *params = &plat->ddr_params;
+ struct sifive_ddr_params *params = &plat->ddr_params;
volatile u32 *denali_ctl = priv->ctl->denali_ctl;
volatile u32 *denali_phy = priv->phy->denali_phy;
const u64 ddr_size = priv->info.size;
@@ -251,7 +251,7 @@
sdram_copy_to_reg(priv->ctl->denali_ctl,
params->pctl_regs.denali_ctl,
- sizeof(struct fu540_ddrctl));
+ sizeof(struct sifive_ddrctl));
/* phy reset */
for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
@@ -285,7 +285,7 @@
setbits_le32(DENALI_CTL_182 + denali_ctl,
1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
- if (fu540_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) {
+ if (sifive_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) {
/* Enable vref training DENALI_CTL_184 */
setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
}
@@ -302,15 +302,15 @@
| (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
/* set up range protection */
- fu540_ddr_setup_range_protection(denali_ctl, priv->info.size);
+ sifive_ddr_setup_range_protection(denali_ctl, priv->info.size);
/* Mask off port command error interrupt DENALI_CTL_136 */
setbits_le32(DENALI_CTL_136 + denali_ctl,
1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
- fu540_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
+ sifive_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
- fu540_ddr_phy_fixup(denali_phy);
+ sifive_ddr_phy_fixup(denali_phy);
/* check size */
priv->info.size = get_ram_size((long *)priv->info.base,
@@ -329,9 +329,9 @@
}
#endif
-static int fu540_ddr_probe(struct udevice *dev)
+static int sifive_ddr_probe(struct udevice *dev)
{
- struct fu540_ddr_info *priv = dev_get_priv(dev);
+ struct sifive_ddr_info *priv = dev_get_priv(dev);
/* Read memory base and size from DT */
fdtdec_setup_mem_size_base();
@@ -342,7 +342,7 @@
int ret;
u32 clock = 0;
- debug("FU540 DDR probe\n");
+ debug("sifive DDR probe\n");
priv->dev = dev;
ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
@@ -369,42 +369,43 @@
return ret;
}
- priv->ctl = (struct fu540_ddrctl *)dev_read_addr_index(dev, 0);
- priv->phy = (struct fu540_ddrphy *)dev_read_addr_index(dev, 1);
+ priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index(dev, 0);
+ priv->phy = (struct sifive_ddrphy *)dev_read_addr_index(dev, 1);
priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2);
- return fu540_ddr_setup(dev);
+ return sifive_ddr_setup(dev);
#endif
return 0;
}
-static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info)
+static int sifive_ddr_get_info(struct udevice *dev, struct ram_info *info)
{
- struct fu540_ddr_info *priv = dev_get_priv(dev);
+ struct sifive_ddr_info *priv = dev_get_priv(dev);
*info = priv->info;
return 0;
}
-static struct ram_ops fu540_ddr_ops = {
- .get_info = fu540_ddr_get_info,
+static struct ram_ops sifive_ddr_ops = {
+ .get_info = sifive_ddr_get_info,
};
-static const struct udevice_id fu540_ddr_ids[] = {
+static const struct udevice_id sifive_ddr_ids[] = {
{ .compatible = "sifive,fu540-c000-ddr" },
+ { .compatible = "sifive,fu740-c000-ddr" },
{ }
};
-U_BOOT_DRIVER(fu540_ddr) = {
- .name = "fu540_ddr",
+U_BOOT_DRIVER(sifive_ddr) = {
+ .name = "sifive_ddr",
.id = UCLASS_RAM,
- .of_match = fu540_ddr_ids,
- .ops = &fu540_ddr_ops,
- .probe = fu540_ddr_probe,
- .priv_auto = sizeof(struct fu540_ddr_info),
+ .of_match = sifive_ddr_ids,
+ .ops = &sifive_ddr_ops,
+ .probe = sifive_ddr_probe,
+ .priv_auto = sizeof(struct sifive_ddr_info),
#if defined(CONFIG_SPL_BUILD)
- .plat_auto = sizeof(struct sifive_dmc_plat),
+ .plat_auto = sizeof(struct sifive_dmc_plat),
#endif
};
diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c
index 3c569a3..6f3e12d 100644
--- a/drivers/remoteproc/ti_k3_r5f_rproc.c
+++ b/drivers/remoteproc/ti_k3_r5f_rproc.c
@@ -804,19 +804,27 @@
return ret;
}
- ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci, core->tsp.dev_id,
- &r_state, &core->in_use);
- if (ret)
- return ret;
+ /*
+ * The PM functionality is not supported by the firmware during
+ * SPL execution with the separated DM firmware image. The following
+ * piece of code is not compiled in that case.
+ */
+ if (!IS_ENABLED(CONFIG_K3_DM_FW)) {
+ ret = core->tsp.sci->ops.dev_ops.is_on(core->tsp.sci,
+ core->tsp.dev_id,
+ &r_state, &core->in_use);
+ if (ret)
+ return ret;
- if (core->in_use) {
- dev_info(dev, "Core %d is already in use. No rproc commands work\n",
- core->tsp.proc_id);
- return 0;
- }
+ if (core->in_use) {
+ dev_info(dev, "Core %d is already in use. No rproc commands work\n",
+ core->tsp.proc_id);
+ return 0;
+ }
- /* Make sure Local reset is asserted. Redundant? */
- reset_assert(&core->reset);
+ /* Make sure Local reset is asserted. Redundant? */
+ reset_assert(&core->reset);
+ }
ret = k3_r5f_rproc_configure(core);
if (ret) {
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 019565f..a42b3f0 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -166,7 +166,7 @@
config RESET_SIFIVE
bool "Reset Driver for SiFive SoC's"
- depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_UNLEASHED
+ depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED)
default y
help
PRCI module within SiFive SoC's provides mechanism to reset
diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index 071c389..ac89eaf 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -95,7 +95,7 @@
int ret;
ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0,
- index > 0, &args);
+ index, &args);
return reset_get_by_index_tail(ret, node, &args, "resets",
index > 0, reset_ctl);
diff --git a/drivers/reset/stm32-reset.c b/drivers/reset/stm32-reset.c
index daa2e47..bbc6b13 100644
--- a/drivers/reset/stm32-reset.c
+++ b/drivers/reset/stm32-reset.c
@@ -40,8 +40,8 @@
static int stm32_reset_assert(struct reset_ctl *reset_ctl)
{
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
- int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
- int offset = reset_ctl->id % BITS_PER_LONG;
+ int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
+ int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
reset_ctl->id, bank, offset);
@@ -61,8 +61,8 @@
static int stm32_reset_deassert(struct reset_ctl *reset_ctl)
{
struct stm32_reset_priv *priv = dev_get_priv(reset_ctl->dev);
- int bank = (reset_ctl->id / BITS_PER_LONG) * 4;
- int offset = reset_ctl->id % BITS_PER_LONG;
+ int bank = (reset_ctl->id / (sizeof(u32) * BITS_PER_BYTE)) * 4;
+ int offset = reset_ctl->id % (sizeof(u32) * BITS_PER_BYTE);
dev_dbg(reset_ctl->dev, "reset id = %ld bank = %d offset = %d)\n",
reset_ctl->id, bank, offset);
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index c84a9d2..cbdfddb 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -188,4 +188,11 @@
families of ultra-low-power battery- and capacitor-backed real-time
clock chips.
+config RTC_DAVINCI
+ bool "Enable TI OMAP RTC driver"
+ depends on ARCH_DAVINCI || ARCH_OMAP2PLUS
+ help
+ Say "yes" here to support the on chip real time clock
+ present on TI OMAP1, AM33xx, DA8xx/OMAP-L13x, AM43xx and DRA7xx.
+
endmenu
diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c
index c446e7a..c7ce41b 100644
--- a/drivers/rtc/davinci.c
+++ b/drivers/rtc/davinci.c
@@ -2,81 +2,443 @@
/*
* (C) Copyright 2011 DENX Software Engineering GmbH
* Heiko Schocher <hs@denx.de>
+ * Copyright (C) 2021 Dario Binacchi <dariobin@libero.it>
*/
#include <common.h>
#include <command.h>
+#include <dm.h>
+#include <clk.h>
#include <log.h>
#include <rtc.h>
#include <asm/io.h>
-#include <asm/davinci_rtc.h>
+#include <dm/device_compat.h>
#include <linux/delay.h>
-int rtc_get(struct rtc_time *tmp)
+/* RTC registers */
+#define OMAP_RTC_SECONDS_REG 0x00
+#define OMAP_RTC_MINUTES_REG 0x04
+#define OMAP_RTC_HOURS_REG 0x08
+#define OMAP_RTC_DAYS_REG 0x0C
+#define OMAP_RTC_MONTHS_REG 0x10
+#define OMAP_RTC_YEARS_REG 0x14
+#define OMAP_RTC_WEEKS_REG 0x18
+
+#define OMAP_RTC_CTRL_REG 0x40
+#define OMAP_RTC_STATUS_REG 0x44
+#define OMAP_RTC_INTERRUPTS_REG 0x48
+
+#define OMAP_RTC_OSC_REG 0x54
+
+#define OMAP_RTC_SCRATCH0_REG 0x60
+#define OMAP_RTC_SCRATCH1_REG 0x64
+#define OMAP_RTC_SCRATCH2_REG 0x68
+
+#define OMAP_RTC_KICK0_REG 0x6c
+#define OMAP_RTC_KICK1_REG 0x70
+
+#define OMAP_RTC_PMIC_REG 0x98
+
+/* OMAP_RTC_CTRL_REG bit fields: */
+#define OMAP_RTC_CTRL_SPLIT BIT(7)
+#define OMAP_RTC_CTRL_DISABLE BIT(6)
+#define OMAP_RTC_CTRL_SET_32_COUNTER BIT(5)
+#define OMAP_RTC_CTRL_TEST BIT(4)
+#define OMAP_RTC_CTRL_MODE_12_24 BIT(3)
+#define OMAP_RTC_CTRL_AUTO_COMP BIT(2)
+#define OMAP_RTC_CTRL_ROUND_30S BIT(1)
+#define OMAP_RTC_CTRL_STOP BIT(0)
+
+/* OMAP_RTC_STATUS_REG bit fields */
+#define OMAP_RTC_STATUS_POWER_UP BIT(7)
+#define OMAP_RTC_STATUS_ALARM2 BIT(7)
+#define OMAP_RTC_STATUS_ALARM BIT(6)
+#define OMAP_RTC_STATUS_1D_EVENT BIT(5)
+#define OMAP_RTC_STATUS_1H_EVENT BIT(4)
+#define OMAP_RTC_STATUS_1M_EVENT BIT(3)
+#define OMAP_RTC_STATUS_1S_EVENT BIT(2)
+#define OMAP_RTC_STATUS_RUN BIT(1)
+#define OMAP_RTC_STATUS_BUSY BIT(0)
+
+/* OMAP_RTC_OSC_REG bit fields */
+#define OMAP_RTC_OSC_32KCLK_EN BIT(6)
+#define OMAP_RTC_OSC_SEL_32KCLK_SRC BIT(3)
+#define OMAP_RTC_OSC_OSC32K_GZ_DISABLE BIT(4)
+
+/* OMAP_RTC_KICKER values */
+#define OMAP_RTC_KICK0_VALUE 0x83e70b13
+#define OMAP_RTC_KICK1_VALUE 0x95a4f1e0
+
+struct omap_rtc_device_type {
+ bool has_32kclk_en;
+ bool has_irqwakeen;
+ bool has_pmic_mode;
+ bool has_power_up_reset;
+};
+
+struct omap_rtc_priv {
+ fdt_addr_t base;
+ u8 max_reg;
+ struct udevice *dev;
+ struct clk clk;
+ bool has_ext_clk;
+ const struct omap_rtc_device_type *type;
+};
+
+static inline u8 omap_rtc_readb(struct omap_rtc_priv *priv, unsigned int reg)
{
- struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
- unsigned long sec, min, hour, mday, wday, mon_cent, year;
- unsigned long status;
+ return readb(priv->base + reg);
+}
+
+static inline u32 omap_rtc_readl(struct omap_rtc_priv *priv, unsigned int reg)
+{
+ return readl(priv->base + reg);
+}
+
+static inline void omap_rtc_writeb(struct omap_rtc_priv *priv, unsigned int reg,
+ u8 val)
+{
+ writeb(val, priv->base + reg);
+}
+
+static inline void omap_rtc_writel(struct omap_rtc_priv *priv, unsigned int reg,
+ u32 val)
+{
+ writel(val, priv->base + reg);
+}
+
+static inline void omap_rtc_unlock(struct omap_rtc_priv *priv)
+{
+ omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, OMAP_RTC_KICK0_VALUE);
+ omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, OMAP_RTC_KICK1_VALUE);
+}
+
+static inline void omap_rtc_lock(struct omap_rtc_priv *priv)
+{
+ omap_rtc_writel(priv, OMAP_RTC_KICK0_REG, 0);
+ omap_rtc_writel(priv, OMAP_RTC_KICK1_REG, 0);
+}
- status = readl(&rtc->status);
- if ((status & RTC_STATE_RUN) != RTC_STATE_RUN) {
+static int omap_rtc_wait_not_busy(struct omap_rtc_priv *priv)
+{
+ int count;
+ u8 status;
+
+ status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
+ if ((status & OMAP_RTC_STATUS_RUN) != OMAP_RTC_STATUS_RUN) {
printf("RTC doesn't run\n");
return -1;
}
- if ((status & RTC_STATE_BUSY) == RTC_STATE_BUSY)
- udelay(20);
+
+ /* BUSY may stay active for 1/32768 second (~30 usec) */
+ for (count = 0; count < 50; count++) {
+ if (!(status & OMAP_RTC_STATUS_BUSY))
+ break;
+
+ udelay(1);
+ status = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
+ }
+
+ /* now we have ~15 usec to read/write various registers */
+ return 0;
+}
+
+static int omap_rtc_reset(struct udevice *dev)
+{
+ struct omap_rtc_priv *priv = dev_get_priv(dev);
+
+ /* run RTC counter */
+ omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, 0x01);
+ return 0;
+}
- sec = readl(&rtc->second);
- min = readl(&rtc->minutes);
- hour = readl(&rtc->hours);
- mday = readl(&rtc->day);
- wday = readl(&rtc->dotw);
- mon_cent = readl(&rtc->month);
- year = readl(&rtc->year);
+static int omap_rtc_set(struct udevice *dev, const struct rtc_time *tm)
+{
+ struct omap_rtc_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = omap_rtc_wait_not_busy(priv);
+ if (ret)
+ return ret;
+
+ omap_rtc_unlock(priv);
+ omap_rtc_writeb(priv, OMAP_RTC_YEARS_REG, bin2bcd(tm->tm_year % 100));
+ omap_rtc_writeb(priv, OMAP_RTC_MONTHS_REG, bin2bcd(tm->tm_mon));
+ omap_rtc_writeb(priv, OMAP_RTC_WEEKS_REG, bin2bcd(tm->tm_wday));
+ omap_rtc_writeb(priv, OMAP_RTC_DAYS_REG, bin2bcd(tm->tm_mday));
+ omap_rtc_writeb(priv, OMAP_RTC_HOURS_REG, bin2bcd(tm->tm_hour));
+ omap_rtc_writeb(priv, OMAP_RTC_MINUTES_REG, bin2bcd(tm->tm_min));
+ omap_rtc_writeb(priv, OMAP_RTC_SECONDS_REG, bin2bcd(tm->tm_sec));
+ omap_rtc_lock(priv);
+
+ dev_dbg(dev, "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
+ tm->tm_min, tm->tm_sec);
+
+ return 0;
+}
- debug("Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
+static int omap_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+ struct omap_rtc_priv *priv = dev_get_priv(dev);
+ unsigned long sec, min, hour, mday, wday, mon_cent, year;
+ int ret;
+
+ ret = omap_rtc_wait_not_busy(priv);
+ if (ret)
+ return ret;
+
+ sec = omap_rtc_readb(priv, OMAP_RTC_SECONDS_REG);
+ min = omap_rtc_readb(priv, OMAP_RTC_MINUTES_REG);
+ hour = omap_rtc_readb(priv, OMAP_RTC_HOURS_REG);
+ mday = omap_rtc_readb(priv, OMAP_RTC_DAYS_REG);
+ wday = omap_rtc_readb(priv, OMAP_RTC_WEEKS_REG);
+ mon_cent = omap_rtc_readb(priv, OMAP_RTC_MONTHS_REG);
+ year = omap_rtc_readb(priv, OMAP_RTC_YEARS_REG);
+
+ dev_dbg(dev,
+ "Get RTC year: %02lx mon/cent: %02lx mday: %02lx wday: %02lx "
"hr: %02lx min: %02lx sec: %02lx\n",
year, mon_cent, mday, wday,
hour, min, sec);
+ tm->tm_sec = bcd2bin(sec & 0x7F);
+ tm->tm_min = bcd2bin(min & 0x7F);
+ tm->tm_hour = bcd2bin(hour & 0x3F);
+ tm->tm_mday = bcd2bin(mday & 0x3F);
+ tm->tm_mon = bcd2bin(mon_cent & 0x1F);
+ tm->tm_year = bcd2bin(year) + 2000;
+ tm->tm_wday = bcd2bin(wday & 0x07);
+ tm->tm_yday = 0;
+ tm->tm_isdst = 0;
+
+ dev_dbg(dev, "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday, tm->tm_hour,
+ tm->tm_min, tm->tm_sec);
+
- tmp->tm_sec = bcd2bin(sec & 0x7F);
- tmp->tm_min = bcd2bin(min & 0x7F);
- tmp->tm_hour = bcd2bin(hour & 0x3F);
- tmp->tm_mday = bcd2bin(mday & 0x3F);
- tmp->tm_mon = bcd2bin(mon_cent & 0x1F);
- tmp->tm_year = bcd2bin(year) + 2000;
- tmp->tm_wday = bcd2bin(wday & 0x07);
- tmp->tm_yday = 0;
- tmp->tm_isdst = 0;
+ return 0;
+}
+
+static int omap_rtc_scratch_read(struct udevice *dev, uint offset,
+ u8 *buffer, uint len)
+{
+ struct omap_rtc_priv *priv = dev_get_priv(dev);
+ u32 *val = (u32 *)buffer;
+ unsigned int reg;
+ int i;
- debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ if (len & 3)
+ return -EFAULT;
+
+ for (i = 0; i < len / 4; i++) {
+ reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
+ if (reg >= OMAP_RTC_KICK0_REG)
+ return -EFAULT;
+
+ val[i] = omap_rtc_readl(priv, reg);
+ }
return 0;
}
-int rtc_set(struct rtc_time *tmp)
+static int omap_rtc_scratch_write(struct udevice *dev, uint offset,
+ const u8 *buffer, uint len)
{
- struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
+ struct omap_rtc_priv *priv = dev_get_priv(dev);
+ u32 *val = (u32 *)buffer;
+ unsigned int reg;
+ int i;
- debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
- writel(bin2bcd(tmp->tm_year % 100), &rtc->year);
- writel(bin2bcd(tmp->tm_mon), &rtc->month);
+ if (len & 3)
+ return -EFAULT;
- writel(bin2bcd(tmp->tm_wday), &rtc->dotw);
- writel(bin2bcd(tmp->tm_mday), &rtc->day);
- writel(bin2bcd(tmp->tm_hour), &rtc->hours);
- writel(bin2bcd(tmp->tm_min), &rtc->minutes);
- writel(bin2bcd(tmp->tm_sec), &rtc->second);
+ omap_rtc_unlock(priv);
+ for (i = 0; i < len / 4; i++) {
+ reg = OMAP_RTC_SCRATCH0_REG + offset + (i * 4);
+ if (reg >= OMAP_RTC_KICK0_REG)
+ return -EFAULT;
+
+ omap_rtc_writel(priv, reg, val[i]);
+ }
+ omap_rtc_lock(priv);
+
return 0;
}
-void rtc_reset(void)
+static int omap_rtc_remove(struct udevice *dev)
{
- struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE;
+ struct omap_rtc_priv *priv = dev_get_priv(dev);
+ u8 reg;
- /* run RTC counter */
- writel(0x01, &rtc->ctrl);
+ if (priv->clk.dev)
+ clk_disable(&priv->clk);
+
+ omap_rtc_unlock(priv);
+
+ /* leave rtc running, but disable irqs */
+ omap_rtc_writeb(priv, OMAP_RTC_INTERRUPTS_REG, 0);
+
+ if (priv->has_ext_clk) {
+ reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
+ reg &= ~OMAP_RTC_OSC_SEL_32KCLK_SRC;
+ omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
+ }
+
+ omap_rtc_lock(priv);
+ return 0;
}
+
+static int omap_rtc_probe(struct udevice *dev)
+{
+ struct omap_rtc_priv *priv = dev_get_priv(dev);
+ struct rtc_time tm;
+ u8 reg, mask, new_ctrl;
+
+ priv->dev = dev;
+ priv->type = (struct omap_rtc_device_type *)dev_get_driver_data(dev);
+ priv->max_reg = OMAP_RTC_PMIC_REG;
+
+ if (!clk_get_by_name(dev, "ext-clk", &priv->clk))
+ priv->has_ext_clk = true;
+ else
+ clk_get_by_name(dev, "int-clk", &priv->clk);
+
+ if (priv->clk.dev)
+ clk_enable(&priv->clk);
+ else
+ dev_warn(dev, "missing clock\n");
+
+ omap_rtc_unlock(priv);
+
+ /*
+ * disable interrupts
+ *
+ * NOTE: ALARM2 is not cleared on AM3352 if rtc_write (writeb) is used
+ */
+ omap_rtc_writel(priv, OMAP_RTC_INTERRUPTS_REG, 0);
+
+ if (priv->type->has_32kclk_en) {
+ reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
+ omap_rtc_writeb(priv, OMAP_RTC_OSC_REG,
+ reg | OMAP_RTC_OSC_32KCLK_EN);
+ }
+
+ /* clear old status */
+ reg = omap_rtc_readb(priv, OMAP_RTC_STATUS_REG);
+
+ mask = OMAP_RTC_STATUS_ALARM;
+
+ if (priv->type->has_pmic_mode)
+ mask |= OMAP_RTC_STATUS_ALARM2;
+
+ if (priv->type->has_power_up_reset) {
+ mask |= OMAP_RTC_STATUS_POWER_UP;
+ if (reg & OMAP_RTC_STATUS_POWER_UP)
+ dev_info(dev, "RTC power up reset detected\n");
+ }
+
+ if (reg & mask)
+ omap_rtc_writeb(priv, OMAP_RTC_STATUS_REG, reg & mask);
+
+ /* On boards with split power, RTC_ON_NOFF won't reset the RTC */
+ reg = omap_rtc_readb(priv, OMAP_RTC_CTRL_REG);
+ if (reg & OMAP_RTC_CTRL_STOP)
+ dev_info(dev, "already running\n");
+
+ /* force to 24 hour mode */
+ new_ctrl = reg & (OMAP_RTC_CTRL_SPLIT | OMAP_RTC_CTRL_AUTO_COMP);
+ new_ctrl |= OMAP_RTC_CTRL_STOP;
+
+ /*
+ * BOARD-SPECIFIC CUSTOMIZATION CAN GO HERE:
+ *
+ * - Device wake-up capability setting should come through chip
+ * init logic. OMAP1 boards should initialize the "wakeup capable"
+ * flag in the platform device if the board is wired right for
+ * being woken up by RTC alarm. For OMAP-L138, this capability
+ * is built into the SoC by the "Deep Sleep" capability.
+ *
+ * - Boards wired so RTC_ON_nOFF is used as the reset signal,
+ * rather than nPWRON_RESET, should forcibly enable split
+ * power mode. (Some chip errata report that RTC_CTRL_SPLIT
+ * is write-only, and always reads as zero...)
+ */
+
+ if (new_ctrl & OMAP_RTC_CTRL_SPLIT)
+ dev_info(dev, "split power mode\n");
+
+ if (reg != new_ctrl)
+ omap_rtc_writeb(priv, OMAP_RTC_CTRL_REG, new_ctrl);
+
+ /*
+ * If we have the external clock then switch to it so we can keep
+ * ticking across suspend.
+ */
+ if (priv->has_ext_clk) {
+ reg = omap_rtc_readb(priv, OMAP_RTC_OSC_REG);
+ reg &= ~OMAP_RTC_OSC_OSC32K_GZ_DISABLE;
+ reg |= OMAP_RTC_OSC_32KCLK_EN | OMAP_RTC_OSC_SEL_32KCLK_SRC;
+ omap_rtc_writeb(priv, OMAP_RTC_OSC_REG, reg);
+ }
+
+ omap_rtc_lock(priv);
+
+ if (omap_rtc_get(dev, &tm)) {
+ dev_err(dev, "failed to get datetime\n");
+ } else if (tm.tm_year == 2000 && tm.tm_mon == 1 && tm.tm_mday == 1 &&
+ tm.tm_wday == 0) {
+ tm.tm_wday = 6;
+ omap_rtc_set(dev, &tm);
+ }
+
+ return 0;
+}
+
+static int omap_rtc_of_to_plat(struct udevice *dev)
+{
+ struct omap_rtc_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE) {
+ dev_err(dev, "invalid address\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dev, "base=%pa\n", &priv->base);
+ return 0;
+}
+
+static const struct rtc_ops omap_rtc_ops = {
+ .get = omap_rtc_get,
+ .set = omap_rtc_set,
+ .reset = omap_rtc_reset,
+ .read = omap_rtc_scratch_read,
+ .write = omap_rtc_scratch_write,
+};
+
+static const struct omap_rtc_device_type omap_rtc_am3352_type = {
+ .has_32kclk_en = true,
+ .has_irqwakeen = true,
+ .has_pmic_mode = true,
+};
+
+static const struct omap_rtc_device_type omap_rtc_da830_type = {
+ .has_32kclk_en = false,
+ .has_irqwakeen = false,
+ .has_pmic_mode = false,
+};
+
+static const struct udevice_id omap_rtc_ids[] = {
+ {.compatible = "ti,am3352-rtc", .data = (ulong)&omap_rtc_am3352_type},
+ {.compatible = "ti,da830-rtc", .data = (ulong)&omap_rtc_da830_type }
+};
+
+U_BOOT_DRIVER(omap_rtc) = {
+ .name = "omap_rtc",
+ .id = UCLASS_RTC,
+ .of_match = omap_rtc_ids,
+ .ops = &omap_rtc_ops,
+ .of_to_plat = omap_rtc_of_to_plat,
+ .probe = omap_rtc_probe,
+ .remove = omap_rtc_remove,
+ .priv_auto = sizeof(struct omap_rtc_priv),
+};
diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c
index 4f9de0d..5283d5e 100644
--- a/drivers/serial/serial_pl01x.c
+++ b/drivers/serial/serial_pl01x.c
@@ -30,8 +30,8 @@
#ifndef CONFIG_DM_SERIAL
static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
-static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
-static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
+static enum pl01x_type pl01x_type __section(".data");
+static struct pl01x_regs *base_regs __section(".data");
#define NUM_PORTS (sizeof(port)/sizeof(port[0]))
#endif
diff --git a/drivers/soc/soc_ti_k3.c b/drivers/soc/soc_ti_k3.c
index ecc3278..9abed7d 100644
--- a/drivers/soc/soc_ti_k3.c
+++ b/drivers/soc/soc_ti_k3.c
@@ -13,6 +13,7 @@
#define AM65X 0xbb5a
#define J721E 0xbb64
#define J7200 0xbb6d
+#define AM64X 0xbb38
#define REV_SR1_0 0
#define REV_SR2_0 1
@@ -44,6 +45,9 @@
case J7200:
family = "J7200";
break;
+ case AM64X:
+ family = "AM64X";
+ break;
default:
family = "Unknown Silicon";
};
diff --git a/drivers/soc/ti/k3-navss-ringacc-u-boot.c b/drivers/soc/ti/k3-navss-ringacc-u-boot.c
new file mode 100644
index 0000000..f958239
--- /dev/null
+++ b/drivers/soc/ti/k3-navss-ringacc-u-boot.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot specific helpers for TI K3 AM65x NAVSS Ring accelerator
+ * Manager (RA) subsystem driver
+ *
+ * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com
+ */
+
+struct k3_nav_ring_cfg_regs {
+ u32 resv_64[16];
+ u32 ba_lo; /* Ring Base Address Lo Register */
+ u32 ba_hi; /* Ring Base Address Hi Register */
+ u32 size; /* Ring Size Register */
+ u32 event; /* Ring Event Register */
+ u32 orderid; /* Ring OrderID Register */
+};
+
+#define KNAV_RINGACC_CFG_REGS_STEP 0x100
+
+#define KNAV_RINGACC_CFG_RING_BA_HI_ADDR_HI_MASK GENMASK(15, 0)
+
+#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK GENMASK(31, 30)
+#define KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT (30)
+
+#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_MASK GENMASK(26, 24)
+#define KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT (24)
+
+static void k3_ringacc_ring_reset_raw(struct k3_nav_ring *ring)
+{
+ writel(0, &ring->cfg->size);
+}
+
+static void k3_ringacc_ring_reconfig_qmode_raw(struct k3_nav_ring *ring, enum k3_nav_ring_mode mode)
+{
+ u32 val;
+
+ val = readl(&ring->cfg->size);
+ val &= KNAV_RINGACC_CFG_RING_SIZE_QMODE_MASK;
+ val |= mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT;
+ writel(val, &ring->cfg->size);
+}
+
+static void k3_ringacc_ring_free_raw(struct k3_nav_ring *ring)
+{
+ writel(0, &ring->cfg->ba_hi);
+ writel(0, &ring->cfg->ba_lo);
+ writel(0, &ring->cfg->size);
+}
+
+static void k3_nav_ringacc_ring_cfg_raw(struct k3_nav_ring *ring)
+{
+ u32 val;
+
+ writel(lower_32_bits(ring->ring_mem_dma), &ring->cfg->ba_lo);
+ writel(upper_32_bits(ring->ring_mem_dma), &ring->cfg->ba_hi);
+
+ val = ring->mode << KNAV_RINGACC_CFG_RING_SIZE_QMODE_SHIFT |
+ ring->elm_size << KNAV_RINGACC_CFG_RING_SIZE_ELSIZE_SHIFT |
+ ring->size;
+ writel(val, &ring->cfg->size);
+}
diff --git a/drivers/soc/ti/k3-navss-ringacc.c b/drivers/soc/ti/k3-navss-ringacc.c
index c5099ad..f110d78 100644
--- a/drivers/soc/ti/k3-navss-ringacc.c
+++ b/drivers/soc/ti/k3-navss-ringacc.c
@@ -23,6 +23,7 @@
#include <linux/err.h>
#include <linux/soc/ti/k3-navss-ringacc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
+#include <linux/soc/ti/cppi5.h>
#define set_bit(bit, bitmap) __set_bit(bit, bitmap)
#define clear_bit(bit, bitmap) __clear_bit(bit, bitmap)
@@ -56,6 +57,7 @@
}
#define KNAV_RINGACC_CFG_RING_SIZE_ELCNT_MASK GENMASK(19, 0)
+#define K3_DMARING_RING_CFG_RING_SIZE_ELCNT_MASK GENMASK(15, 0)
/**
* struct k3_nav_ring_rt_regs - The RA Control/Status Registers region
@@ -71,6 +73,13 @@
};
#define KNAV_RINGACC_RT_REGS_STEP 0x1000
+#define K3_DMARING_RING_RT_REGS_STEP 0x2000
+#define K3_DMARING_RING_RT_REGS_REVERSE_OFS 0x1000
+#define KNAV_RINGACC_RT_OCC_MASK GENMASK(20, 0)
+#define K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE BIT(31)
+#define K3_DMARING_RING_RT_DB_ENTRY_MASK GENMASK(7, 0)
+#define K3_DMARING_RING_RT_DB_TDOWN_ACK BIT(31)
+
/**
* struct k3_nav_ring_fifo_regs - The Ring Accelerator Queues Registers region
@@ -82,36 +91,6 @@
u32 peek_tail_data[128]; /* Ring Peek Tail Entry Data Regs */
};
-/**
- * struct k3_ringacc_proxy_gcfg_regs - RA Proxy Global Config MMIO Region
- */
-struct k3_ringacc_proxy_gcfg_regs {
- u32 revision; /* Revision Register */
- u32 config; /* Config Register */
-};
-
-#define K3_RINGACC_PROXY_CFG_THREADS_MASK GENMASK(15, 0)
-
-/**
- * struct k3_ringacc_proxy_target_regs - RA Proxy Datapath MMIO Region
- */
-struct k3_ringacc_proxy_target_regs {
- u32 control; /* Proxy Control Register */
- u32 status; /* Proxy Status Register */
- u8 resv_512[504];
- u32 data[128]; /* Proxy Data Register */
-};
-
-#define K3_RINGACC_PROXY_TARGET_STEP 0x1000
-#define K3_RINGACC_PROXY_NOT_USED (-1)
-
-enum k3_ringacc_proxy_access_mode {
- PROXY_ACCESS_MODE_HEAD = 0,
- PROXY_ACCESS_MODE_TAIL = 1,
- PROXY_ACCESS_MODE_PEEK_HEAD = 2,
- PROXY_ACCESS_MODE_PEEK_TAIL = 3,
-};
-
#define KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES (512U)
#define KNAV_RINGACC_FIFO_REGS_STEP 0x1000
#define KNAV_RINGACC_MAX_DB_RING_CNT (127U)
@@ -145,9 +124,9 @@
/**
* struct k3_nav_ring - RA Ring descriptor
*
+ * @cfg - Ring configuration registers
* @rt - Ring control/status registers
* @fifos - Ring queues registers
- * @proxy - Ring Proxy Datapath registers
* @ring_mem_dma - Ring buffer dma address
* @ring_mem_virt - Ring buffer virt address
* @ops - Ring operations
@@ -158,12 +137,11 @@
* @ring_id - Ring Id
* @parent - Pointer on struct @k3_nav_ringacc
* @use_count - Use count for shared rings
- * @proxy_id - RA Ring Proxy Id (only if @K3_NAV_RINGACC_RING_USE_PROXY)
*/
struct k3_nav_ring {
+ struct k3_nav_ring_cfg_regs __iomem *cfg;
struct k3_nav_ring_rt_regs __iomem *rt;
struct k3_nav_ring_fifo_regs __iomem *fifos;
- struct k3_ringacc_proxy_target_regs __iomem *proxy;
dma_addr_t ring_mem_dma;
void *ring_mem_virt;
struct k3_nav_ring_ops *ops;
@@ -173,11 +151,11 @@
u32 flags;
#define KNAV_RING_FLAG_BUSY BIT(1)
#define K3_NAV_RING_FLAG_SHARED BIT(2)
+#define K3_NAV_RING_FLAG_REVERSE BIT(3)
struct k3_nav_ring_state state;
u32 ring_id;
struct k3_nav_ringacc *parent;
u32 use_count;
- int proxy_id;
};
struct k3_nav_ringacc_ops {
@@ -188,8 +166,6 @@
* struct k3_nav_ringacc - Rings accelerator descriptor
*
* @dev - pointer on RA device
- * @proxy_gcfg - RA proxy global config registers
- * @proxy_target_base - RA proxy datapath region
* @num_rings - number of ring in RA
* @rm_gp_range - general purpose rings range from tisci
* @dma_ring_reset_quirk - DMA reset w/a enable
@@ -200,17 +176,15 @@
* @tisci_ring_ops - ti-sci rings ops
* @tisci_dev_id - ti-sci device id
* @ops: SoC specific ringacc operation
+ * @dual_ring: indicate k3_dmaring dual ring support
*/
struct k3_nav_ringacc {
struct udevice *dev;
- struct k3_ringacc_proxy_gcfg_regs __iomem *proxy_gcfg;
- void __iomem *proxy_target_base;
u32 num_rings; /* number of rings in Ringacc module */
unsigned long *rings_inuse;
struct ti_sci_resource *rm_gp_range;
bool dma_ring_reset_quirk;
u32 num_proxies;
- unsigned long *proxy_inuse;
struct k3_nav_ring *rings;
struct list_head list;
@@ -220,12 +194,24 @@
u32 tisci_dev_id;
const struct k3_nav_ringacc_ops *ops;
+ bool dual_ring;
};
-static long k3_nav_ringacc_ring_get_fifo_pos(struct k3_nav_ring *ring)
+#include "k3-navss-ringacc-u-boot.c"
+
+static int k3_nav_ringacc_ring_read_occ(struct k3_nav_ring *ring)
+{
+ return readl(&ring->rt->occ) & KNAV_RINGACC_RT_OCC_MASK;
+}
+
+static void k3_nav_ringacc_ring_update_occ(struct k3_nav_ring *ring)
{
- return KNAV_RINGACC_FIFO_WINDOW_SIZE_BYTES -
- (4 << ring->elm_size);
+ u32 val;
+
+ val = readl(&ring->rt->occ);
+
+ ring->state.occ = val & KNAV_RINGACC_RT_OCC_MASK;
+ ring->state.tdown_complete = !!(val & K3_DMARING_RING_RT_OCC_TDOWN_COMPLETE);
}
static void *k3_nav_ringacc_get_elm_addr(struct k3_nav_ring *ring, u32 idx)
@@ -235,38 +221,21 @@
static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem);
static int k3_nav_ringacc_ring_pop_mem(struct k3_nav_ring *ring, void *elem);
+static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem);
+static int k3_dmaring_ring_reverse_pop_mem(struct k3_nav_ring *ring, void *elem);
static struct k3_nav_ring_ops k3_nav_mode_ring_ops = {
.push_tail = k3_nav_ringacc_ring_push_mem,
.pop_head = k3_nav_ringacc_ring_pop_mem,
};
-static int k3_nav_ringacc_ring_push_io(struct k3_nav_ring *ring, void *elem);
-static int k3_nav_ringacc_ring_pop_io(struct k3_nav_ring *ring, void *elem);
-static int k3_nav_ringacc_ring_push_head_io(struct k3_nav_ring *ring,
- void *elem);
-static int k3_nav_ringacc_ring_pop_tail_io(struct k3_nav_ring *ring,
- void *elem);
-
-static struct k3_nav_ring_ops k3_nav_mode_msg_ops = {
- .push_tail = k3_nav_ringacc_ring_push_io,
- .push_head = k3_nav_ringacc_ring_push_head_io,
- .pop_tail = k3_nav_ringacc_ring_pop_tail_io,
- .pop_head = k3_nav_ringacc_ring_pop_io,
+static struct k3_nav_ring_ops k3_dmaring_fwd_ring_ops = {
+ .push_tail = k3_nav_ringacc_ring_push_mem,
+ .pop_head = k3_dmaring_ring_fwd_pop_mem,
};
-static int k3_ringacc_ring_push_head_proxy(struct k3_nav_ring *ring,
- void *elem);
-static int k3_ringacc_ring_push_tail_proxy(struct k3_nav_ring *ring,
- void *elem);
-static int k3_ringacc_ring_pop_head_proxy(struct k3_nav_ring *ring, void *elem);
-static int k3_ringacc_ring_pop_tail_proxy(struct k3_nav_ring *ring, void *elem);
-
-static struct k3_nav_ring_ops k3_nav_mode_proxy_ops = {
- .push_tail = k3_ringacc_ring_push_tail_proxy,
- .push_head = k3_ringacc_ring_push_head_proxy,
- .pop_tail = k3_ringacc_ring_pop_tail_proxy,
- .pop_head = k3_ringacc_ring_pop_head_proxy,
+static struct k3_nav_ring_ops k3_dmaring_reverse_ring_ops = {
+ .pop_head = k3_dmaring_ring_reverse_pop_mem,
};
struct udevice *k3_nav_ringacc_get_dev(struct k3_nav_ringacc *ringacc)
@@ -275,10 +244,8 @@
}
struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
- int id, u32 flags)
+ int id)
{
- int proxy_id = K3_RINGACC_PROXY_NOT_USED;
-
if (id == K3_NAV_RINGACC_RING_ID_ANY) {
/* Request for any general purpose ring */
struct ti_sci_resource_desc *gp_rings =
@@ -300,24 +267,10 @@
else if (ringacc->rings[id].flags & K3_NAV_RING_FLAG_SHARED)
goto out;
- if (flags & K3_NAV_RINGACC_RING_USE_PROXY) {
- proxy_id = find_next_zero_bit(ringacc->proxy_inuse,
- ringacc->num_proxies, 0);
- if (proxy_id == ringacc->num_proxies)
- goto error;
- }
-
if (!try_module_get(ringacc->dev->driver->owner))
goto error;
- if (proxy_id != K3_RINGACC_PROXY_NOT_USED) {
- set_bit(proxy_id, ringacc->proxy_inuse);
- ringacc->rings[id].proxy_id = proxy_id;
- pr_debug("Giving ring#%d proxy#%d\n",
- id, proxy_id);
- } else {
- pr_debug("Giving ring#%d\n", id);
- }
+ pr_debug("Giving ring#%d\n", id);
set_bit(id, ringacc->rings_inuse);
out:
@@ -328,6 +281,27 @@
return NULL;
}
+static int k3_dmaring_ring_request_rings_pair(struct k3_nav_ringacc *ringacc,
+ int fwd_id, int compl_id,
+ struct k3_nav_ring **fwd_ring,
+ struct k3_nav_ring **compl_ring)
+{
+ /* k3_dmaring: fwd_id == compl_id, so we ignore compl_id */
+ if (fwd_id < 0)
+ return -EINVAL;
+
+ if (test_bit(fwd_id, ringacc->rings_inuse))
+ return -EBUSY;
+
+ *fwd_ring = &ringacc->rings[fwd_id];
+ *compl_ring = &ringacc->rings[fwd_id + ringacc->num_rings];
+ set_bit(fwd_id, ringacc->rings_inuse);
+ ringacc->rings[fwd_id].use_count++;
+ dev_dbg(ringacc->dev, "Giving ring#%d\n", fwd_id);
+
+ return 0;
+}
+
int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
int fwd_id, int compl_id,
struct k3_nav_ring **fwd_ring,
@@ -338,11 +312,15 @@
if (!fwd_ring || !compl_ring)
return -EINVAL;
+ if (ringacc->dual_ring)
+ return k3_dmaring_ring_request_rings_pair(ringacc, fwd_id, compl_id,
+ fwd_ring, compl_ring);
+
- *fwd_ring = k3_nav_ringacc_request_ring(ringacc, fwd_id, 0);
+ *fwd_ring = k3_nav_ringacc_request_ring(ringacc, fwd_id);
if (!(*fwd_ring))
return -ENODEV;
- *compl_ring = k3_nav_ringacc_request_ring(ringacc, compl_id, 0);
+ *compl_ring = k3_nav_ringacc_request_ring(ringacc, compl_id);
if (!(*compl_ring)) {
k3_nav_ringacc_ring_free(*fwd_ring);
ret = -ENODEV;
@@ -356,6 +334,9 @@
struct k3_nav_ringacc *ringacc = ring->parent;
int ret;
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ return k3_ringacc_ring_reset_raw(ring);
+
ret = ringacc->tisci_ring_ops->config(
ringacc->tisci,
TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID,
@@ -388,6 +369,9 @@
struct k3_nav_ringacc *ringacc = ring->parent;
int ret;
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ return k3_ringacc_ring_reconfig_qmode_raw(ring, mode);
+
ret = ringacc->tisci_ring_ops->config(
ringacc->tisci,
TI_SCI_MSG_VALUE_RM_RING_MODE_VALID,
@@ -468,6 +452,9 @@
struct k3_nav_ringacc *ringacc = ring->parent;
int ret;
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ return k3_ringacc_ring_free_raw(ring);
+
ret = ringacc->tisci_ring_ops->config(
ringacc->tisci,
TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER,
@@ -493,6 +480,13 @@
ringacc = ring->parent;
+ /*
+ * k3_dmaring: rings shared memory and configuration, only forward ring is
+ * configured and reverse ring considered as slave.
+ */
+ if (ringacc->dual_ring && (ring->flags & K3_NAV_RING_FLAG_REVERSE))
+ return 0;
+
pr_debug("%s flags: 0x%08x\n", __func__, ring->flags);
if (!test_bit(ring->ring_id, ringacc->rings_inuse))
@@ -511,11 +505,6 @@
ring->ring_mem_virt, ring->ring_mem_dma);
ring->flags &= ~KNAV_RING_FLAG_BUSY;
ring->ops = NULL;
- if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED) {
- clear_bit(ring->proxy_id, ringacc->proxy_inuse);
- ring->proxy = NULL;
- ring->proxy_id = K3_RINGACC_PROXY_NOT_USED;
- }
no_init:
clear_bit(ring->ring_id, ringacc->rings_inuse);
@@ -555,10 +544,89 @@
ring->mode,
ring->elm_size,
0);
- if (ret)
+ if (ret) {
dev_err(ringacc->dev, "TISCI config ring fail (%d) ring_idx %d\n",
ret, ring_idx);
+ return ret;
+ }
+
+ /*
+ * Above TI SCI call handles firewall configuration, cfg
+ * register configuration still has to be done locally in
+ * absence of RM services.
+ */
+ if (IS_ENABLED(CONFIG_K3_DM_FW))
+ k3_nav_ringacc_ring_cfg_raw(ring);
+
+ return 0;
+}
+static int k3_dmaring_ring_cfg(struct k3_nav_ring *ring, struct k3_nav_ring_cfg *cfg)
+{
+ struct k3_nav_ringacc *ringacc;
+ struct k3_nav_ring *reverse_ring;
+ int ret = 0;
+
+ if (cfg->elm_size != K3_NAV_RINGACC_RING_ELSIZE_8 ||
+ cfg->mode != K3_NAV_RINGACC_RING_MODE_RING ||
+ cfg->size & ~K3_DMARING_RING_CFG_RING_SIZE_ELCNT_MASK)
+ return -EINVAL;
+
+ ringacc = ring->parent;
+
+ /*
+ * k3_dmaring: rings shared memory and configuration, only forward ring is
+ * configured and reverse ring considered as slave.
+ */
+ if (ringacc->dual_ring && (ring->flags & K3_NAV_RING_FLAG_REVERSE))
+ return 0;
+
+ if (!test_bit(ring->ring_id, ringacc->rings_inuse))
+ return -EINVAL;
+
+ ring->size = cfg->size;
+ ring->elm_size = cfg->elm_size;
+ ring->mode = cfg->mode;
+ memset(&ring->state, 0, sizeof(ring->state));
+
+ ring->ops = &k3_dmaring_fwd_ring_ops;
+
+ ring->ring_mem_virt =
+ dma_alloc_coherent(ring->size * (4 << ring->elm_size),
+ (unsigned long *)&ring->ring_mem_dma);
+ if (!ring->ring_mem_virt) {
+ dev_err(ringacc->dev, "Failed to alloc ring mem\n");
+ ret = -ENOMEM;
+ goto err_free_ops;
+ }
+
+ ret = k3_nav_ringacc_ring_cfg_sci(ring);
+ if (ret)
+ goto err_free_mem;
+
+ ring->flags |= KNAV_RING_FLAG_BUSY;
+
+ /* k3_dmaring: configure reverse ring */
+ reverse_ring = &ringacc->rings[ring->ring_id + ringacc->num_rings];
+ reverse_ring->size = cfg->size;
+ reverse_ring->elm_size = cfg->elm_size;
+ reverse_ring->mode = cfg->mode;
+ memset(&reverse_ring->state, 0, sizeof(reverse_ring->state));
+ reverse_ring->ops = &k3_dmaring_reverse_ring_ops;
+
+ reverse_ring->ring_mem_virt = ring->ring_mem_virt;
+ reverse_ring->ring_mem_dma = ring->ring_mem_dma;
+ reverse_ring->flags |= KNAV_RING_FLAG_BUSY;
+
+ return 0;
+
+err_free_mem:
+ dma_free_coherent(ringacc->dev,
+ ring->size * (4 << ring->elm_size),
+ ring->ring_mem_virt,
+ ring->ring_mem_dma);
+err_free_ops:
+ ring->ops = NULL;
return ret;
}
@@ -570,6 +638,10 @@
if (!ring || !cfg)
return -EINVAL;
+
+ if (ringacc->dual_ring)
+ return k3_dmaring_ring_cfg(ring, cfg);
+
if (cfg->elm_size > K3_NAV_RINGACC_RING_ELSIZE_256 ||
cfg->mode > K3_NAV_RINGACC_RING_MODE_QM ||
cfg->size & ~KNAV_RINGACC_CFG_RING_SIZE_ELCNT_MASK ||
@@ -584,32 +656,14 @@
ring->mode = cfg->mode;
memset(&ring->state, 0, sizeof(ring->state));
- if (ring->proxy_id != K3_RINGACC_PROXY_NOT_USED)
- ring->proxy = ringacc->proxy_target_base +
- ring->proxy_id * K3_RINGACC_PROXY_TARGET_STEP;
-
switch (ring->mode) {
case K3_NAV_RINGACC_RING_MODE_RING:
ring->ops = &k3_nav_mode_ring_ops;
break;
- case K3_NAV_RINGACC_RING_MODE_QM:
- /*
- * In Queue mode elm_size can be 8 only and each operation
- * uses 2 element slots
- */
- if (cfg->elm_size != K3_NAV_RINGACC_RING_ELSIZE_8 ||
- cfg->size % 2)
- goto err_free_proxy;
- case K3_NAV_RINGACC_RING_MODE_MESSAGE:
- if (ring->proxy)
- ring->ops = &k3_nav_mode_proxy_ops;
- else
- ring->ops = &k3_nav_mode_msg_ops;
- break;
default:
ring->ops = NULL;
ret = -EINVAL;
- goto err_free_proxy;
+ goto err_free_ops;
};
ring->ring_mem_virt =
@@ -640,8 +694,6 @@
ring->ring_mem_dma);
err_free_ops:
ring->ops = NULL;
-err_free_proxy:
- ring->proxy = NULL;
return ret;
}
@@ -686,159 +738,63 @@
K3_RINGACC_ACCESS_MODE_PEEK_TAIL,
};
-static int k3_ringacc_ring_cfg_proxy(struct k3_nav_ring *ring,
- enum k3_ringacc_proxy_access_mode mode)
+static int k3_dmaring_ring_fwd_pop_mem(struct k3_nav_ring *ring, void *elem)
{
- u32 val;
-
- val = ring->ring_id;
- val |= mode << 16;
- val |= ring->elm_size << 24;
- ringacc_writel(val, &ring->proxy->control);
- return 0;
-}
-
-static int k3_nav_ringacc_ring_access_proxy(
- struct k3_nav_ring *ring, void *elem,
- enum k3_ringacc_access_mode access_mode)
-{
- void __iomem *ptr;
+ void *elem_ptr;
+ u32 elem_idx;
- ptr = (void __iomem *)&ring->proxy->data;
+ /*
+ * k3_dmaring: forward ring is always tied DMA channel and HW does not
+ * maintain any state data required for POP operation and its unknown
+ * how much elements were consumed by HW. So, to actually
+ * do POP, the read pointer has to be recalculated every time.
+ */
+ ring->state.occ = k3_nav_ringacc_ring_read_occ(ring);
+ if (ring->state.windex >= ring->state.occ)
+ elem_idx = ring->state.windex - ring->state.occ;
+ else
+ elem_idx = ring->size - (ring->state.occ - ring->state.windex);
- switch (access_mode) {
- case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
- case K3_RINGACC_ACCESS_MODE_POP_HEAD:
- k3_ringacc_ring_cfg_proxy(ring, PROXY_ACCESS_MODE_HEAD);
- break;
- case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
- case K3_RINGACC_ACCESS_MODE_POP_TAIL:
- k3_ringacc_ring_cfg_proxy(ring, PROXY_ACCESS_MODE_TAIL);
- break;
- default:
- return -EINVAL;
- }
+ elem_ptr = k3_nav_ringacc_get_elm_addr(ring, elem_idx);
+ invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
+ ALIGN((unsigned long)ring->ring_mem_virt +
+ ring->size * (4 << ring->elm_size),
+ ARCH_DMA_MINALIGN));
- ptr += k3_nav_ringacc_ring_get_fifo_pos(ring);
+ memcpy(elem, elem_ptr, (4 << ring->elm_size));
- switch (access_mode) {
- case K3_RINGACC_ACCESS_MODE_POP_HEAD:
- case K3_RINGACC_ACCESS_MODE_POP_TAIL:
- pr_debug("proxy:memcpy_fromio(x): --> ptr(%p), mode:%d\n",
- ptr, access_mode);
- memcpy_fromio(elem, ptr, (4 << ring->elm_size));
- ring->state.occ--;
- break;
- case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
- case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
- pr_debug("proxy:memcpy_toio(x): --> ptr(%p), mode:%d\n",
- ptr, access_mode);
- memcpy_toio(ptr, elem, (4 << ring->elm_size));
- ring->state.free--;
- break;
- default:
- return -EINVAL;
- }
+ ring->state.occ--;
+ writel(-1, &ring->rt->db);
- pr_debug("proxy: free%d occ%d\n",
- ring->state.free, ring->state.occ);
+ dev_dbg(ring->parent->dev, "%s: occ%d Windex%d Rindex%d pos_ptr%px\n",
+ __func__, ring->state.occ, ring->state.windex, elem_idx,
+ elem_ptr);
return 0;
}
-static int k3_ringacc_ring_push_head_proxy(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_proxy(
- ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_HEAD);
-}
-
-static int k3_ringacc_ring_push_tail_proxy(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_proxy(
- ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_TAIL);
-}
-
-static int k3_ringacc_ring_pop_head_proxy(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_proxy(
- ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
-static int k3_ringacc_ring_pop_tail_proxy(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_proxy(
- ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
-static int k3_nav_ringacc_ring_access_io(
- struct k3_nav_ring *ring, void *elem,
- enum k3_ringacc_access_mode access_mode)
+static int k3_dmaring_ring_reverse_pop_mem(struct k3_nav_ring *ring, void *elem)
{
- void __iomem *ptr;
+ void *elem_ptr;
- switch (access_mode) {
- case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
- case K3_RINGACC_ACCESS_MODE_POP_HEAD:
- ptr = (void __iomem *)&ring->fifos->head_data;
- break;
- case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
- case K3_RINGACC_ACCESS_MODE_POP_TAIL:
- ptr = (void __iomem *)&ring->fifos->tail_data;
- break;
- default:
- return -EINVAL;
- }
+ elem_ptr = k3_nav_ringacc_get_elm_addr(ring, ring->state.rindex);
- ptr += k3_nav_ringacc_ring_get_fifo_pos(ring);
+ if (ring->state.occ) {
+ invalidate_dcache_range((unsigned long)ring->ring_mem_virt,
+ ALIGN((unsigned long)ring->ring_mem_virt +
+ ring->size * (4 << ring->elm_size),
+ ARCH_DMA_MINALIGN));
- switch (access_mode) {
- case K3_RINGACC_ACCESS_MODE_POP_HEAD:
- case K3_RINGACC_ACCESS_MODE_POP_TAIL:
- pr_debug("memcpy_fromio(x): --> ptr(%p), mode:%d\n",
- ptr, access_mode);
- memcpy_fromio(elem, ptr, (4 << ring->elm_size));
+ memcpy(elem, elem_ptr, (4 << ring->elm_size));
+ ring->state.rindex = (ring->state.rindex + 1) % ring->size;
ring->state.occ--;
- break;
- case K3_RINGACC_ACCESS_MODE_PUSH_TAIL:
- case K3_RINGACC_ACCESS_MODE_PUSH_HEAD:
- pr_debug("memcpy_toio(x): --> ptr(%p), mode:%d\n",
- ptr, access_mode);
- memcpy_toio(ptr, elem, (4 << ring->elm_size));
- ring->state.free--;
- break;
- default:
- return -EINVAL;
+ writel(-1 & K3_DMARING_RING_RT_DB_ENTRY_MASK, &ring->rt->db);
}
- pr_debug("free%d index%d occ%d index%d\n",
- ring->state.free, ring->state.windex, ring->state.occ, ring->state.rindex);
+ dev_dbg(ring->parent->dev, "%s: occ%d index%d pos_ptr%px\n",
+ __func__, ring->state.occ, ring->state.rindex, elem_ptr);
return 0;
}
-static int k3_nav_ringacc_ring_push_head_io(struct k3_nav_ring *ring,
- void *elem)
-{
- return k3_nav_ringacc_ring_access_io(
- ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_HEAD);
-}
-
-static int k3_nav_ringacc_ring_push_io(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_io(
- ring, elem, K3_RINGACC_ACCESS_MODE_PUSH_TAIL);
-}
-
-static int k3_nav_ringacc_ring_pop_io(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_io(
- ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
-static int k3_nav_ringacc_ring_pop_tail_io(struct k3_nav_ring *ring, void *elem)
-{
- return k3_nav_ringacc_ring_access_io(
- ring, elem, K3_RINGACC_ACCESS_MODE_POP_HEAD);
-}
-
static int k3_nav_ringacc_ring_push_mem(struct k3_nav_ring *ring, void *elem)
{
void *elem_ptr;
@@ -930,7 +886,7 @@
return -EINVAL;
if (!ring->state.occ)
- ring->state.occ = k3_nav_ringacc_ring_get_occ(ring);
+ k3_nav_ringacc_ring_update_occ(ring);
pr_debug("ring_pop%d: occ%d index%d\n",
ring->ring_id, ring->state.occ, ring->state.rindex);
@@ -952,7 +908,7 @@
return -EINVAL;
if (!ring->state.occ)
- ring->state.occ = k3_nav_ringacc_ring_get_occ(ring);
+ k3_nav_ringacc_ring_update_occ(ring);
pr_debug("ring_pop_tail: occ%d index%d\n",
ring->state.occ, ring->state.rindex);
@@ -969,6 +925,7 @@
static int k3_nav_ringacc_probe_dt(struct k3_nav_ringacc *ringacc)
{
struct udevice *dev = ringacc->dev;
+ struct udevice *devp = dev;
struct udevice *tisci_dev = NULL;
int ret;
@@ -981,7 +938,7 @@
ringacc->dma_ring_reset_quirk =
dev_read_bool(dev, "ti,dma-ring-reset-quirk");
- ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, dev,
+ ret = uclass_get_device_by_phandle(UCLASS_FIRMWARE, devp,
"ti,sci", &tisci_dev);
if (ret) {
pr_debug("TISCI RA RM get failed (%d)\n", ret);
@@ -991,14 +948,14 @@
ringacc->tisci = (struct ti_sci_handle *)
(ti_sci_get_handle_from_sysfw(tisci_dev));
- ret = dev_read_u32_default(dev, "ti,sci", 0);
+ ret = dev_read_u32_default(devp, "ti,sci", 0);
if (!ret) {
dev_err(dev, "TISCI RA RM disabled\n");
ringacc->tisci = NULL;
return ret;
}
- ret = dev_read_u32(dev, "ti,sci-dev-id", &ringacc->tisci_dev_id);
+ ret = dev_read_u32(devp, "ti,sci-dev-id", &ringacc->tisci_dev_id);
if (ret) {
dev_err(dev, "ti,sci-dev-id read failure %d\n", ret);
ringacc->tisci = NULL;
@@ -1017,36 +974,23 @@
static int k3_nav_ringacc_init(struct udevice *dev, struct k3_nav_ringacc *ringacc)
{
- void __iomem *base_fifo, *base_rt;
+ void __iomem *base_cfg, *base_rt;
int ret, i;
ret = k3_nav_ringacc_probe_dt(ringacc);
if (ret)
return ret;
+ base_cfg = dev_remap_addr_name(dev, "cfg");
+ pr_debug("cfg %p\n", base_cfg);
+ if (!base_cfg)
+ return -EINVAL;
+
base_rt = (uint32_t *)devfdt_get_addr_name(dev, "rt");
pr_debug("rt %p\n", base_rt);
if (IS_ERR(base_rt))
return PTR_ERR(base_rt);
- base_fifo = (uint32_t *)devfdt_get_addr_name(dev, "fifos");
- pr_debug("fifos %p\n", base_fifo);
- if (IS_ERR(base_fifo))
- return PTR_ERR(base_fifo);
-
- ringacc->proxy_gcfg = (struct k3_ringacc_proxy_gcfg_regs __iomem *)
- devfdt_get_addr_name(dev, "proxy_gcfg");
- if (IS_ERR(ringacc->proxy_gcfg))
- return PTR_ERR(ringacc->proxy_gcfg);
- ringacc->proxy_target_base =
- (struct k3_ringacc_proxy_gcfg_regs __iomem *)
- devfdt_get_addr_name(dev, "proxy_target");
- if (IS_ERR(ringacc->proxy_target_base))
- return PTR_ERR(ringacc->proxy_target_base);
-
- ringacc->num_proxies = ringacc_readl(&ringacc->proxy_gcfg->config) &
- K3_RINGACC_PROXY_CFG_THREADS_MASK;
-
ringacc->rings = devm_kzalloc(dev,
sizeof(*ringacc->rings) *
ringacc->num_rings,
@@ -1054,21 +998,17 @@
ringacc->rings_inuse = devm_kcalloc(dev,
BITS_TO_LONGS(ringacc->num_rings),
sizeof(unsigned long), GFP_KERNEL);
- ringacc->proxy_inuse = devm_kcalloc(dev,
- BITS_TO_LONGS(ringacc->num_proxies),
- sizeof(unsigned long), GFP_KERNEL);
- if (!ringacc->rings || !ringacc->rings_inuse || !ringacc->proxy_inuse)
+ if (!ringacc->rings || !ringacc->rings_inuse)
return -ENOMEM;
for (i = 0; i < ringacc->num_rings; i++) {
+ ringacc->rings[i].cfg = base_cfg +
+ KNAV_RINGACC_CFG_REGS_STEP * i;
ringacc->rings[i].rt = base_rt +
KNAV_RINGACC_RT_REGS_STEP * i;
- ringacc->rings[i].fifos = base_fifo +
- KNAV_RINGACC_FIFO_REGS_STEP * i;
ringacc->rings[i].parent = ringacc;
ringacc->rings[i].ring_id = i;
- ringacc->rings[i].proxy_id = K3_RINGACC_PROXY_NOT_USED;
}
dev_set_drvdata(dev, ringacc);
@@ -1083,12 +1023,68 @@
ringacc->tisci_dev_id);
dev_info(dev, "dma-ring-reset-quirk: %s\n",
ringacc->dma_ring_reset_quirk ? "enabled" : "disabled");
- dev_info(dev, "RA Proxy rev. %08x, num_proxies:%u\n",
- ringacc_readl(&ringacc->proxy_gcfg->revision),
- ringacc->num_proxies);
return 0;
}
+struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
+ struct k3_ringacc_init_data *data)
+{
+ struct k3_nav_ringacc *ringacc;
+ void __iomem *base_rt;
+ int i;
+
+ ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL);
+ if (!ringacc)
+ return ERR_PTR(-ENOMEM);
+
+ ringacc->dual_ring = true;
+
+ ringacc->dev = dev;
+ ringacc->num_rings = data->num_rings;
+ ringacc->tisci = data->tisci;
+ ringacc->tisci_dev_id = data->tisci_dev_id;
+
+ base_rt = (uint32_t *)devfdt_get_addr_name(dev, "ringrt");
+ if (IS_ERR(base_rt))
+ return base_rt;
+
+ ringacc->rings = devm_kzalloc(dev,
+ sizeof(*ringacc->rings) *
+ ringacc->num_rings * 2,
+ GFP_KERNEL);
+ ringacc->rings_inuse = devm_kcalloc(dev,
+ BITS_TO_LONGS(ringacc->num_rings),
+ sizeof(unsigned long), GFP_KERNEL);
+
+ if (!ringacc->rings || !ringacc->rings_inuse)
+ return ERR_PTR(-ENOMEM);
+
+ for (i = 0; i < ringacc->num_rings; i++) {
+ struct k3_nav_ring *ring = &ringacc->rings[i];
+
+ ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i;
+ ring->parent = ringacc;
+ ring->ring_id = i;
+
+ ring = &ringacc->rings[ringacc->num_rings + i];
+ ring->rt = base_rt + K3_DMARING_RING_RT_REGS_STEP * i +
+ K3_DMARING_RING_RT_REGS_REVERSE_OFS;
+ ring->parent = ringacc;
+ ring->ring_id = i;
+ ring->flags = K3_NAV_RING_FLAG_REVERSE;
+ }
+
+ ringacc->tisci_ring_ops = &ringacc->tisci->ops.rm_ring_ops;
+
+ dev_info(dev, "k3_dmaring Ring probed rings:%u, sci-dev-id:%u\n",
+ ringacc->num_rings,
+ ringacc->tisci_dev_id);
+ dev_info(dev, "dma-ring-reset-quirk: %s\n",
+ ringacc->dma_ring_reset_quirk ? "enabled" : "disabled");
+
+ return ringacc;
+}
+
struct ringacc_match_data {
struct k3_nav_ringacc_ops ops;
};
diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c
index 634cd56..775b9ff 100644
--- a/drivers/spi/atcspi200_spi.c
+++ b/drivers/spi/atcspi200_spi.c
@@ -201,7 +201,7 @@
size_t cmd_len = ns->cmd_len;
unsigned long data_len = bitlen / 8;
int rf_cnt;
- int ret = 0;
+ int ret = 0, timeout = 0;
max_tran_len = ns->max_transfer_length;
switch (flags) {
@@ -243,11 +243,12 @@
ns->tran_len = tran_len;
num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
num_bytes = (tran_len) % CHUNK_SIZE;
+ timeout = SPI_TIMEOUT;
if(num_bytes == 0)
num_bytes = CHUNK_SIZE;
__atcspi200_spi_start(ns);
- while (num_blks) {
+ while (num_blks && (timeout--)) {
event = in_le32(&ns->regs->status);
if ((event & TXEPTY) && (data_out)) {
__nspi_espi_tx(ns, dout);
@@ -269,6 +270,11 @@
din = (unsigned char *)din + rx_bytes;
}
}
+
+ if (!timeout) {
+ debug("spi_xfer: %s() timeout\n", __func__);
+ break;
+ }
}
data_len -= tran_len;
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index 43812da..bc5da0a 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -110,13 +110,70 @@
static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
struct mvebu_spi_plat *plat = dev_get_plat(bus);
+ struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
struct kwspi_registers *reg = plat->spireg;
- u32 data;
+ u32 data, divider;
+ unsigned int spr, sppr;
+
+ if (spi->max_hz && (hz > spi->max_hz)) {
+ debug("%s: limit speed to the max_hz of the bus %d\n",
+ __func__, spi->max_hz);
+ hz = spi->max_hz;
+ }
+
+ /*
+ * Calculate spi clock prescaller using max_hz.
+ * SPPR is SPI Baud Rate Pre-selection, it holds bits 5 and 7:6 in
+ * SPI Interface Configuration Register;
+ * SPR is SPI Baud Rate Selection, it holds bits 3:0 in SPI Interface
+ * Configuration Register.
+ * The SPR together with the SPPR define the SPI CLK frequency as
+ * follows:
+ * SPI actual frequency = core_clk / (SPR * (2 ^ SPPR))
+ */
+ divider = DIV_ROUND_UP(CONFIG_SYS_TCLK, hz);
+ if (divider < 16) {
+ /* This is the easy case, divider is less than 16 */
+ spr = divider;
+ sppr = 0;
+
+ } else {
+ unsigned int two_pow_sppr;
+ /*
+ * Find the highest bit set in divider. This and the
+ * three next bits define SPR (apart from rounding).
+ * SPPR is then the number of zero bits that must be
+ * appended:
+ */
+ sppr = fls(divider) - 4;
+
+ /*
+ * As SPR only has 4 bits, we have to round divider up
+ * to the next multiple of 2 ** sppr.
+ */
+ two_pow_sppr = 1 << sppr;
+ divider = (divider + two_pow_sppr - 1) & -two_pow_sppr;
+
+ /*
+ * recalculate sppr as rounding up divider might have
+ * increased it enough to change the position of the
+ * highest set bit. In this case the bit that now
+ * doesn't make it into SPR is 0, so there is no need to
+ * round again.
+ */
+ sppr = fls(divider) - 4;
+ spr = divider >> sppr;
+
+ /*
+ * Now do range checking. SPR is constructed to have a
+ * width of 4 bits, so this is fine for sure. So we
+ * still need to check for sppr to fit into 3 bits:
+ */
+ if (sppr > 7)
+ return -EINVAL;
+ }
- /* calculate spi clock prescaller using max_hz */
- data = ((CONFIG_SYS_TCLK / 2) / hz) + 0x10;
- data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
- data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
+ data = ((sppr & 0x6) << 5) | ((sppr & 0x1) << 4) | spr;
/* program spi clock prescaler using max_hz */
writel(KWSPI_ADRLEN_3BYTE | data, ®->cfg);
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index f8d13d1..1778006 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -10,7 +10,6 @@
#include <log.h>
#include <asm/arch/sys_proto.h>
#include <asm/cache.h>
-#include <asm/global_data.h>
#include <asm/io.h>
#include <clk.h>
#include <dm.h>
@@ -156,8 +155,6 @@
u32 dmadstmsb; /* 0x28 */
};
-DECLARE_GLOBAL_DATA_PTR;
-
struct zynqmp_qspi_plat {
struct zynqmp_qspi_regs *regs;
struct zynqmp_qspi_dma_regs *dma_regs;
diff --git a/drivers/sysinfo/Kconfig b/drivers/sysinfo/Kconfig
index 85c1e81..381dcd8 100644
--- a/drivers/sysinfo/Kconfig
+++ b/drivers/sysinfo/Kconfig
@@ -30,4 +30,12 @@
one which provides a way to specify this SMBIOS information in the
devicetree, without needing any board-specific functionality.
+config SYSINFO_GPIO
+ bool "Enable gpio sysinfo driver"
+ help
+ Support querying gpios to determine board revision. This uses gpios to
+ form a ternary number (when they are pulled-up, -down, or floating).
+ This ternary number is then mapped to a board revision name using
+ device tree properties.
+
endif
diff --git a/drivers/sysinfo/Makefile b/drivers/sysinfo/Makefile
index 6d04fcb..d9f708b 100644
--- a/drivers/sysinfo/Makefile
+++ b/drivers/sysinfo/Makefile
@@ -4,5 +4,6 @@
# Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
obj-y += sysinfo-uclass.o
obj-$(CONFIG_SYSINFO_GAZERBEAM) += gazerbeam.o
+obj-$(CONFIG_SYSINFO_GPIO) += gpio.o
obj-$(CONFIG_SYSINFO_SANDBOX) += sandbox.o
obj-$(CONFIG_SYSINFO_SMBIOS) += smbios.o
diff --git a/drivers/sysinfo/gazerbeam.h b/drivers/sysinfo/gazerbeam.h
index 171729d..6bf3c00 100644
--- a/drivers/sysinfo/gazerbeam.h
+++ b/drivers/sysinfo/gazerbeam.h
@@ -5,10 +5,12 @@
*
*/
+#include <sysinfo.h>
+
enum {
- BOARD_MULTICHANNEL,
- BOARD_VARIANT,
- BOARD_HWVERSION,
+ BOARD_HWVERSION = SYSINFO_ID_BOARD_MODEL,
+ BOARD_MULTICHANNEL = SYSINFO_ID_USER,
+ BOARD_VARIANT
};
enum {
diff --git a/drivers/sysinfo/gpio.c b/drivers/sysinfo/gpio.c
new file mode 100644
index 0000000..1d7f050
--- /dev/null
+++ b/drivers/sysinfo/gpio.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Sean Anderson <sean.anderson@seco.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <sysinfo.h>
+#include <asm/gpio.h>
+#include <dm/device_compat.h>
+
+/**
+ * struct sysinfo_gpio_priv - GPIO sysinfo private data
+ * @gpios: List of GPIOs used to detect the revision
+ * @gpio_num: The number of GPIOs in @gpios
+ * @revision: The revision as detected from the GPIOs.
+ */
+struct sysinfo_gpio_priv {
+ struct gpio_desc *gpios;
+ int gpio_num, revision;
+};
+
+static int sysinfo_gpio_detect(struct udevice *dev)
+{
+ int ret;
+ struct sysinfo_gpio_priv *priv = dev_get_priv(dev);
+
+ ret = dm_gpio_get_values_as_int_base3(priv->gpios, priv->gpio_num);
+ if (ret < 0)
+ return ret;
+
+ priv->revision = ret;
+ return 0;
+}
+
+static int sysinfo_gpio_get_int(struct udevice *dev, int id, int *val)
+{
+ struct sysinfo_gpio_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case SYSINFO_ID_BOARD_MODEL:
+ *val = priv->revision;
+ return 0;
+ default:
+ return -EINVAL;
+ };
+}
+
+static int sysinfo_gpio_get_str(struct udevice *dev, int id, size_t size, char *val)
+{
+ struct sysinfo_gpio_priv *priv = dev_get_priv(dev);
+
+ switch (id) {
+ case SYSINFO_ID_BOARD_MODEL: {
+ const char *name = NULL;
+ int i, ret;
+ u32 revision;
+
+ for (i = 0; i < priv->gpio_num; i++) {
+ ret = dev_read_u32_index(dev, "revisions", i,
+ &revision);
+ if (ret) {
+ if (ret != -EOVERFLOW)
+ return ret;
+ break;
+ }
+
+ if (revision == priv->revision) {
+ ret = dev_read_string_index(dev, "names", i,
+ &name);
+ if (ret < 0)
+ return ret;
+ break;
+ }
+ }
+ if (!name)
+ name = "unknown";
+
+ strncpy(val, name, size);
+ val[size - 1] = '\0';
+ return 0;
+ } default:
+ return -EINVAL;
+ };
+}
+
+static const struct sysinfo_ops sysinfo_gpio_ops = {
+ .detect = sysinfo_gpio_detect,
+ .get_int = sysinfo_gpio_get_int,
+ .get_str = sysinfo_gpio_get_str,
+};
+
+static int sysinfo_gpio_probe(struct udevice *dev)
+{
+ int ret;
+ struct sysinfo_gpio_priv *priv = dev_get_priv(dev);
+
+ priv->gpio_num = gpio_get_list_count(dev, "gpios");
+ if (priv->gpio_num < 0) {
+ dev_err(dev, "could not get gpios length (err = %d)\n",
+ priv->gpio_num);
+ return priv->gpio_num;
+ }
+
+ priv->gpios = calloc(priv->gpio_num, sizeof(*priv->gpios));
+ if (!priv->gpios) {
+ dev_err(dev, "could not allocate memory for %d gpios\n",
+ priv->gpio_num);
+ return -ENOMEM;
+ }
+
+ ret = gpio_request_list_by_name(dev, "gpios", priv->gpios,
+ priv->gpio_num, GPIOD_IS_IN);
+ if (ret != priv->gpio_num) {
+ dev_err(dev, "could not get gpios (err = %d)\n",
+ priv->gpio_num);
+ return ret;
+ }
+
+ if (!dev_read_bool(dev, "revisions") || !dev_read_bool(dev, "names")) {
+ dev_err(dev, "revisions or names properties missing\n");
+ return -ENOENT;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id sysinfo_gpio_ids[] = {
+ { .compatible = "gpio-sysinfo" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(sysinfo_gpio) = {
+ .name = "sysinfo_gpio",
+ .id = UCLASS_SYSINFO,
+ .of_match = sysinfo_gpio_ids,
+ .ops = &sysinfo_gpio_ops,
+ .priv_auto = sizeof(struct sysinfo_gpio_priv),
+ .probe = sysinfo_gpio_probe,
+};
diff --git a/drivers/sysinfo/sandbox.h b/drivers/sysinfo/sandbox.h
index 2cff494..d9c5804 100644
--- a/drivers/sysinfo/sandbox.h
+++ b/drivers/sysinfo/sandbox.h
@@ -5,7 +5,7 @@
*/
enum {
- BOOL_CALLED_DETECT,
+ BOOL_CALLED_DETECT = SYSINFO_ID_USER,
INT_TEST1,
INT_TEST2,
STR_VACATIONSPOT,
diff --git a/drivers/sysinfo/sysinfo-uclass.c b/drivers/sysinfo/sysinfo-uclass.c
index 6df58fe..4a660df 100644
--- a/drivers/sysinfo/sysinfo-uclass.c
+++ b/drivers/sysinfo/sysinfo-uclass.c
@@ -8,6 +8,10 @@
#include <dm.h>
#include <sysinfo.h>
+struct sysinfo_priv {
+ bool detected;
+};
+
int sysinfo_get(struct udevice **devp)
{
return uclass_first_device_err(UCLASS_SYSINFO, devp);
@@ -15,19 +19,29 @@
int sysinfo_detect(struct udevice *dev)
{
+ int ret;
+ struct sysinfo_priv *priv = dev_get_uclass_priv(dev);
struct sysinfo_ops *ops = sysinfo_get_ops(dev);
if (!ops->detect)
return -ENOSYS;
- return ops->detect(dev);
+ ret = ops->detect(dev);
+ if (!ret)
+ priv->detected = true;
+
+ return ret;
}
int sysinfo_get_fit_loadable(struct udevice *dev, int index, const char *type,
const char **strp)
{
+ struct sysinfo_priv *priv = dev_get_uclass_priv(dev);
struct sysinfo_ops *ops = sysinfo_get_ops(dev);
+ if (!priv->detected)
+ return -EPERM;
+
if (!ops->get_fit_loadable)
return -ENOSYS;
@@ -36,8 +50,12 @@
int sysinfo_get_bool(struct udevice *dev, int id, bool *val)
{
+ struct sysinfo_priv *priv = dev_get_uclass_priv(dev);
struct sysinfo_ops *ops = sysinfo_get_ops(dev);
+ if (!priv->detected)
+ return -EPERM;
+
if (!ops->get_bool)
return -ENOSYS;
@@ -46,8 +64,12 @@
int sysinfo_get_int(struct udevice *dev, int id, int *val)
{
+ struct sysinfo_priv *priv = dev_get_uclass_priv(dev);
struct sysinfo_ops *ops = sysinfo_get_ops(dev);
+ if (!priv->detected)
+ return -EPERM;
+
if (!ops->get_int)
return -ENOSYS;
@@ -56,8 +78,12 @@
int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val)
{
+ struct sysinfo_priv *priv = dev_get_uclass_priv(dev);
struct sysinfo_ops *ops = sysinfo_get_ops(dev);
+ if (!priv->detected)
+ return -EPERM;
+
if (!ops->get_str)
return -ENOSYS;
@@ -68,4 +94,5 @@
.id = UCLASS_SYSINFO,
.name = "sysinfo",
.post_bind = dm_scan_fdt_dev,
+ .per_device_auto = sizeof(bool),
};
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index eb5c48c..2ebdeab 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -19,7 +19,7 @@
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
-obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o
+obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
obj-$(CONFIG_STI_TIMER) += sti-timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
diff --git a/drivers/timer/mpc83xx_timer.c b/drivers/timer/mpc83xx_timer.c
index f4f6e90..9522931 100644
--- a/drivers/timer/mpc83xx_timer.c
+++ b/drivers/timer/mpc83xx_timer.c
@@ -20,6 +20,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_WATCHDOG_FREQ
+#define CONFIG_SYS_WATCHDOG_FREQ (CONFIG_SYS_HZ / 2)
+#endif
+
/**
* struct mpc83xx_timer_priv - Private data structure for MPC83xx timer driver
* @decrementer_count: Value to which the decrementer register should be re-set
@@ -171,7 +175,7 @@
priv->timestamp++;
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
- if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
+ if (CONFIG_SYS_WATCHDOG_FREQ && (priv->timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
WATCHDOG_RESET();
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c
index 30f835e..c8bf4ae 100644
--- a/drivers/usb/dwc3/dwc3-generic.c
+++ b/drivers/usb/dwc3/dwc3-generic.c
@@ -163,7 +163,8 @@
};
#endif
-#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || \
+ !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_HOST)
static int dwc3_generic_host_probe(struct udevice *dev)
{
struct xhci_hcor *hcor;
diff --git a/drivers/usb/dwc3/dwc3-meson-g12a.c b/drivers/usb/dwc3/dwc3-meson-g12a.c
index bd8bf22..90418dd 100644
--- a/drivers/usb/dwc3/dwc3-meson-g12a.c
+++ b/drivers/usb/dwc3/dwc3-meson-g12a.c
@@ -298,7 +298,7 @@
for (i = 0 ; i < PHY_COUNT ; ++i) {
ret = generic_phy_get_by_name(priv->dev, phy_names[i],
&priv->phys[i]);
- if (ret == -ENOENT)
+ if (ret == -ENOENT || ret == -ENODATA)
continue;
if (ret)
diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c
index 7642a31..06be9de 100644
--- a/drivers/usb/host/ehci-mx6.c
+++ b/drivers/usb/host/ehci-mx6.c
@@ -265,6 +265,8 @@
}
#endif
+#if !defined(CONFIG_PHY)
+/* Should be done in the MXS PHY driver */
static void usb_oc_config(struct usbnc_regs *usbnc, int index)
{
void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
@@ -285,6 +287,7 @@
clrbits_le32(ctrl, UCTRL_PWR_POL);
#endif
}
+#endif
#if !CONFIG_IS_ENABLED(DM_USB)
/**
@@ -432,10 +435,12 @@
struct clk clk;
struct phy phy;
enum usb_init_type init_type;
+#if !defined(CONFIG_PHY)
int portnr;
void __iomem *phy_addr;
void __iomem *misc_addr;
void __iomem *anatop_addr;
+#endif
};
static int mx6_init_after_reset(struct ehci_ctrl *dev)
@@ -448,14 +453,14 @@
usb_power_config_mx6(priv->anatop_addr, priv->portnr);
usb_power_config_mx7(priv->misc_addr);
usb_power_config_mx7ulp(priv->phy_addr);
-#endif
usb_oc_config(priv->misc_addr, priv->portnr);
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
@@ -558,6 +563,7 @@
static int mx6_parse_dt_addrs(struct udevice *dev)
{
+#if !defined(CONFIG_PHY)
struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
int phy_off, misc_off;
const void *blob = gd->fdt_blob;
@@ -594,7 +600,7 @@
priv->misc_addr = addr;
-#if !defined(CONFIG_PHY) && defined(CONFIG_MX6)
+#if defined(CONFIG_MX6)
int anatop_off;
/* Resolve ANATOP offset through USB PHY node */
@@ -608,6 +614,7 @@
priv->anatop_addr = addr;
#endif
+#endif
return 0;
}
@@ -661,14 +668,14 @@
usb_power_config_mx6(priv->anatop_addr, priv->portnr);
usb_power_config_mx7(priv->misc_addr);
usb_power_config_mx7ulp(priv->phy_addr);
-#endif
usb_oc_config(priv->misc_addr, priv->portnr);
-#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
+#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
usb_internal_phy_clock_gate(priv->phy_addr, 1);
usb_phy_enable(ehci, priv->phy_addr);
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_REGULATOR)
if (priv->vbus_supply) {
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 6cf8a2b..fd6f410 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -89,3 +89,13 @@
help
All data is copied between memory and FIFO by the CPU.
DMA controllers are ignored.
+
+config USB_MUSB_FIXED_CONFIGDATA
+ bool "Hardcode MUSB CONFIGDATA register"
+ depends on USB_MUSB_SUNXI
+ default n if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I_A23
+ default y
+ help
+ Newer Allwinner SoCs do not implement the MUSB_CONFIGDATA register,
+ so it always reads 0. Select this option to override this and
+ return a hardcoded value instead.
diff --git a/drivers/usb/musb-new/musb_regs.h b/drivers/usb/musb-new/musb_regs.h
index c4d7203..e9362f6 100644
--- a/drivers/usb/musb-new/musb_regs.h
+++ b/drivers/usb/musb-new/musb_regs.h
@@ -431,8 +431,7 @@
static inline u8 musb_read_configdata(void __iomem *mbase)
{
-#if defined CONFIG_MACH_SUN8I_A33 || defined CONFIG_MACH_SUN8I_A83T || \
- defined CONFIG_MACH_SUNXI_H3_H5 || defined CONFIG_MACH_SUN50I
+#ifdef CONFIG_USB_MUSB_FIXED_CONFIGDATA
/* <Sigh> allwinner saves a reg, and we need to hardcode this */
return 0xde;
#else
diff --git a/drivers/w1-eeprom/ds24xxx.c b/drivers/w1-eeprom/ds24xxx.c
index d12fd57..4be378b 100644
--- a/drivers/w1-eeprom/ds24xxx.c
+++ b/drivers/w1-eeprom/ds24xxx.c
@@ -53,3 +53,10 @@
.ops = &ds24xxx_ops,
.probe = ds24xxx_probe,
};
+
+u8 family_supported[] = {
+ W1_FAMILY_DS24B33,
+ W1_FAMILY_DS2431,
+};
+
+U_BOOT_W1_DEVICE(ds24xxx, family_supported);
diff --git a/drivers/w1-eeprom/ds2502.c b/drivers/w1-eeprom/ds2502.c
index b3d68d7..a67f5ed 100644
--- a/drivers/w1-eeprom/ds2502.c
+++ b/drivers/w1-eeprom/ds2502.c
@@ -243,3 +243,9 @@
.ops = &ds2502_ops,
.probe = ds2502_probe,
};
+
+u8 family_supported[] = {
+ W1_FAMILY_DS2502,
+};
+
+U_BOOT_W1_DEVICE(ds2502, family_supported);
diff --git a/drivers/w1-eeprom/w1-eeprom-uclass.c b/drivers/w1-eeprom/w1-eeprom-uclass.c
index 97a9d43..7a02af3 100644
--- a/drivers/w1-eeprom/w1-eeprom-uclass.c
+++ b/drivers/w1-eeprom/w1-eeprom-uclass.c
@@ -37,37 +37,6 @@
return ops->read_buf(dev, offset, buf, count);
}
-int w1_eeprom_register_new_device(u64 id)
-{
- u8 family = id & 0xff;
- int ret;
- struct udevice *dev;
-
- for (ret = uclass_first_device(UCLASS_W1_EEPROM, &dev);
- !ret && dev;
- uclass_next_device(&dev)) {
- if (ret || !dev) {
- debug("cannot find w1 eeprom dev\n");
- return ret;
- }
- if (dev_get_driver_data(dev) == family) {
- struct w1_device *w1;
-
- w1 = dev_get_parent_plat(dev);
- if (w1->id) /* device already in use */
- continue;
- w1->id = id;
- debug("%s: Match found: %s:%s %llx\n", __func__,
- dev->name, dev->driver->name, id);
- return 0;
- }
- }
-
- debug("%s: No matches found: error %d\n", __func__, ret);
-
- return ret;
-}
-
int w1_eeprom_get_id(struct udevice *dev, u64 *id)
{
struct w1_device *w1 = dev_get_parent_plat(dev);
diff --git a/drivers/w1/w1-uclass.c b/drivers/w1/w1-uclass.c
index 8bc6cb1..b989273 100644
--- a/drivers/w1/w1-uclass.c
+++ b/drivers/w1/w1-uclass.c
@@ -4,9 +4,11 @@
* Copyright (c) 2015 Free Electrons
* Copyright (c) 2015 NextThing Co.
* Copyright (c) 2018 Microchip Technology, Inc.
+ * Copyright (c) 2021 Bootlin
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
* Eugen Hristev <eugen.hristev@microchip.com>
+ * Kory Maincent <kory.maincent@bootlin.com>
*
*/
@@ -26,6 +28,76 @@
u64 search_id;
};
+int w1_bus_find_dev(const struct udevice *bus, u64 id, struct udevice
+**devp)
+{
+ struct udevice *dev;
+ u8 family = id & 0xff;
+ int ret;
+
+ for (ret = uclass_first_device(UCLASS_W1_EEPROM, &dev);
+ !ret && dev;
+ uclass_next_device(&dev)) {
+ if (ret || !dev) {
+ debug("cannot find w1 eeprom dev\n");
+ return -ENODEV;
+ }
+
+ if (dev_get_driver_data(dev) == family) {
+ *devp = dev;
+ return 0;
+ }
+ }
+
+ return -ENODEV;
+}
+
+int w1_register_new_device(u64 id, struct udevice *bus)
+{
+ u8 family = id & 0xff;
+ int n_ents, ret = 0;
+ struct udevice *dev;
+
+ struct w1_driver_entry *start, *entry;
+
+ start = ll_entry_start(struct w1_driver_entry, w1_driver_entry);
+ n_ents = ll_entry_count(struct w1_driver_entry, w1_driver_entry);
+
+ for (entry = start; entry != start + n_ents; entry++) {
+ const u8 *match_family;
+ const struct driver *drv;
+ struct w1_device *w1;
+
+ for (match_family = entry->family; match_family;
+ match_family++) {
+ if (*match_family != family)
+ continue;
+
+ ret = w1_bus_find_dev(bus, id, &dev);
+
+ /* If nothing in the device tree, bind a device */
+ if (ret == -ENODEV) {
+ drv = entry->driver;
+ ret = device_bind(bus, drv, drv->name,
+ NULL, ofnode_null(), &dev);
+ if (ret)
+ return ret;
+ }
+
+ device_probe(dev);
+
+ w1 = dev_get_parent_plat(dev);
+ w1->id = id;
+
+ return 0;
+ }
+ }
+
+ debug("%s: No matches found: error %d\n", __func__, ret);
+
+ return ret;
+}
+
static int w1_enumerate(struct udevice *bus)
{
const struct w1_ops *ops = device_get_ops(bus);
@@ -97,8 +169,8 @@
debug("%s: Detected new device 0x%llx (family 0x%x)\n",
bus->name, rn, (u8)(rn & 0xff));
- /* attempt to register as w1-eeprom device */
- w1_eeprom_register_new_device(rn);
+ /* attempt to register as w1 device */
+ w1_register_new_device(rn, bus);
}
}
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index 0603ffb..2687135 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -148,7 +148,7 @@
/* Do not reset the watchdog too often */
now = get_timer(0);
- if (time_after(now, next_reset)) {
+ if (time_after_eq(now, next_reset)) {
next_reset = now + reset_period;
wdt_reset(gd->watchdog_dev);
}
diff --git a/dts/Kconfig b/dts/Kconfig
index 99ce75e..dabe008 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -19,6 +19,24 @@
bool
select DTOC
+config BINMAN_STANDALONE_FDT
+ bool
+ depends on BINMAN
+ default y if OF_BOARD || OF_PRIOR_STAGE
+ help
+ This option tells U-Boot build system that a standalone device tree
+ source is explicitly required when using binman to package U-Boot.
+
+ This is not necessary in a common scenario where a device tree source
+ that contains the binman node is provided in the arch/<arch>/dts
+ directory for a specific board. Such device tree sources are built for
+ OF_SEPARATE or OF_EMBED. However for a scenario like the board device
+ tree blob is not provided in the U-Boot build tree, but fed to U-Boot
+ in the runtime, e.g.: in the OF_PRIOR_STAGE case that it is passed by
+ a prior stage bootloader. For such scenario, a standalone device tree
+ blob containing binman node to describe how to package U-Boot should
+ be provided explicitly.
+
menu "Device Tree Control"
depends on SUPPORT_OF_CONTROL
diff --git a/env/Kconfig b/env/Kconfig
index 08e49c2..1411f9e 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -445,7 +445,7 @@
string "Device and partition for where to store the environemt in FAT"
depends on ENV_IS_IN_FAT
default "0:1" if TI_COMMON_CMD_OPTIONS
- default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP
+ default "0:auto" if ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_VERSAL
default "0:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA = -1
default "1:auto" if ARCH_SUNXI && MMC_SUNXI_SLOT_EXTRA != -1
default "0" if ARCH_AT91
@@ -556,6 +556,7 @@
hex "Redundant environment offset"
depends on (ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \
ENV_IS_IN_SPI_FLASH) && SYS_REDUNDAND_ENVIRONMENT
+ default 0
help
Offset from the start of the device (or partition) of the redundant
environment location.
@@ -669,6 +670,24 @@
later by U-Boot code. With CONFIG_OF_CONTROL this is instead
controlled by the value of /config/load-environment.
+config ENV_IMPORT_FDT
+ bool "Amend environment by FDT properties"
+ depends on OF_CONTROL
+ help
+ If selected, after the environment has been loaded from its
+ persistent location, the "env_fdt_path" variable is looked
+ up and used as a path to a node in the control DTB. The
+ property/value pairs in that node is then used to update the
+ run-time environment. This can be useful to use the same
+ U-Boot binary with different board variants.
+
+config ENV_FDT_PATH
+ string "Default value for env_fdt_path variable"
+ depends on ENV_IMPORT_FDT
+ default "/config/environment"
+ help
+ The initial value of the env_fdt_path variable.
+
config ENV_APPEND
bool "Always append the environment with new data"
default n
diff --git a/env/common.c b/env/common.c
index 49bbb05..81e9e0b 100644
--- a/env/common.c
+++ b/env/common.c
@@ -20,6 +20,7 @@
#include <errno.h>
#include <malloc.h>
#include <u-boot/crc.h>
+#include <dm/ofnode.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -334,3 +335,32 @@
return found;
}
#endif
+
+#ifdef CONFIG_ENV_IMPORT_FDT
+void env_import_fdt(void)
+{
+ const char *path;
+ struct ofprop prop;
+ ofnode node;
+ int res;
+
+ path = env_get("env_fdt_path");
+ if (!path || !path[0])
+ return;
+
+ node = ofnode_path(path);
+ if (!ofnode_valid(node)) {
+ printf("Warning: device tree node '%s' not found\n", path);
+ return;
+ }
+
+ for (res = ofnode_get_first_property(node, &prop);
+ !res;
+ res = ofnode_get_next_property(&prop)) {
+ const char *name, *val;
+
+ val = ofnode_get_property_by_prop(&prop, &name, NULL);
+ env_set(name, val);
+ }
+}
+#endif
diff --git a/fs/btrfs/disk-io.c b/fs/btrfs/disk-io.c
index c6fdec9..349411c 100644
--- a/fs/btrfs/disk-io.c
+++ b/fs/btrfs/disk-io.c
@@ -291,7 +291,7 @@
int btrfs_read_dev_super(struct blk_desc *desc, struct disk_partition *part,
struct btrfs_super_block *sb)
{
- char tmp[BTRFS_SUPER_INFO_SIZE];
+ ALLOC_CACHE_ALIGN_BUFFER(char, tmp, BTRFS_SUPER_INFO_SIZE);
struct btrfs_super_block *buf = (struct btrfs_super_block *)tmp;
int ret;
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 019d532..2c23793 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -390,10 +390,16 @@
csize);
ret = btrfs_decompress(btrfs_file_extent_compression(leaf, fi),
cbuf, csize, dbuf, dsize);
- if (ret < 0 || ret != dsize) {
+ if (ret == (u32)-1) {
ret = -EIO;
goto out;
}
+ /*
+ * The compressed part ends before sector boundary, the remaining needs
+ * to be zeroed out.
+ */
+ if (ret < dsize)
+ memset(dbuf + ret, 0, dsize - ret);
memcpy(dest, dbuf, dsize);
ret = dsize;
out:
@@ -494,10 +500,16 @@
ret = btrfs_decompress(btrfs_file_extent_compression(leaf, fi), cbuf,
csize, dbuf, dsize);
- if (ret != dsize) {
+ if (ret == (u32)-1) {
ret = -EIO;
goto out;
}
+ /*
+ * The compressed part ends before sector boundary, the remaining needs
+ * to be zeroed out.
+ */
+ if (ret < dsize)
+ memset(dbuf + ret, 0, dsize - ret);
/* Then copy the needed part */
memcpy(dest, dbuf + btrfs_file_extent_offset(leaf, fi), len);
ret = len;
diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c
index 29805c3..997be2d 100644
--- a/fs/squashfs/sqfs.c
+++ b/fs/squashfs/sqfs.c
@@ -876,7 +876,7 @@
char **token_list = NULL, *path = NULL;
u32 *pos_list = NULL;
- dirs = malloc(sizeof(*dirs));
+ dirs = calloc(1, sizeof(*dirs));
if (!dirs)
return -EINVAL;
diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h
index e1a5f4b..e278d4c 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -184,12 +184,6 @@
#ifdef CONFIG_DM
/**
- * @dm_flags: additional flags for Driver Model
- *
- * See &enum gd_dm_flags
- */
- unsigned long dm_flags;
- /**
* @dm_root: root instance for Driver Model
*/
struct udevice *dm_root;
@@ -519,12 +513,6 @@
#define gd_acpi_ctx() NULL
#endif
-#if CONFIG_IS_ENABLED(DM)
-#define gd_size_cells_0() (gd->dm_flags & GD_DM_FLG_SIZE_CELLS_0)
-#else
-#define gd_size_cells_0() (0)
-#endif
-
/**
* enum gd_flags - global data flags
*
@@ -584,41 +572,33 @@
*/
GD_FLG_RECORD = 0x01000,
/**
+ * @GD_FLG_RECORD_OVF: record console overflow
+ */
+ GD_FLG_RECORD_OVF = 0x02000,
+ /**
* @GD_FLG_ENV_DEFAULT: default variable flag
*/
- GD_FLG_ENV_DEFAULT = 0x02000,
+ GD_FLG_ENV_DEFAULT = 0x04000,
/**
* @GD_FLG_SPL_EARLY_INIT: early SPL initialization is done
*/
- GD_FLG_SPL_EARLY_INIT = 0x04000,
+ GD_FLG_SPL_EARLY_INIT = 0x08000,
/**
* @GD_FLG_LOG_READY: log system is ready for use
*/
- GD_FLG_LOG_READY = 0x08000,
+ GD_FLG_LOG_READY = 0x10000,
/**
* @GD_FLG_WDT_READY: watchdog is ready for use
*/
- GD_FLG_WDT_READY = 0x10000,
+ GD_FLG_WDT_READY = 0x20000,
/**
* @GD_FLG_SKIP_LL_INIT: don't perform low-level initialization
*/
- GD_FLG_SKIP_LL_INIT = 0x20000,
+ GD_FLG_SKIP_LL_INIT = 0x40000,
/**
* @GD_FLG_SMP_READY: SMP initialization is complete
*/
- GD_FLG_SMP_READY = 0x40000,
-};
-
-/**
- * enum gd_dm_flags - global data flags for Driver Model
- *
- * See field dm_flags of &struct global_data.
- */
-enum gd_dm_flags {
- /**
- * @GD_DM_FLG_SIZE_CELLS_0: Enable #size-cells=<0> translation
- */
- GD_DM_FLG_SIZE_CELLS_0 = 0x00001,
+ GD_FLG_SMP_READY = 0x80000,
};
#endif /* __ASSEMBLY__ */
diff --git a/include/clk.h b/include/clk.h
index ca6b85f..f3c88fe 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -277,19 +277,41 @@
}
#endif
+/**
+ * enum clk_defaults_stage - What stage clk_set_defaults() is called at
+ * @CLK_DEFAULTS_PRE: Called before probe. Setting of defaults for clocks owned
+ * by this clock driver will be defered until after probing.
+ * @CLK_DEFAULTS_POST: Called after probe. Only defaults for clocks owned by
+ * this clock driver will be set.
+ * @CLK_DEFAULTS_POST_FORCE: Called after probe, and always set defaults, even
+ * before relocation. Usually, defaults are not set
+ * pre-relocation to avoid setting them twice (when
+ * the device is probed again post-relocation). This
+ * may incur a performance cost as device tree
+ * properties must be parsed for a second time.
+ * However, when not using SPL, pre-relocation may be
+ * the only time we can set defaults for some clocks
+ * (such as those used for the RAM we will relocate
+ * into).
+ */
+enum clk_defaults_stage {
+ CLK_DEFAULTS_PRE = 0,
+ CLK_DEFAULTS_POST = 1,
+ CLK_DEFAULTS_POST_FORCE,
+};
+
#if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) && \
CONFIG_IS_ENABLED(CLK)
+
/**
* clk_set_defaults - Process 'assigned-{clocks/clock-parents/clock-rates}'
* properties to configure clocks
*
* @dev: A device to process (the ofnode associated with this device
* will be processed).
- * @stage: A integer. 0 indicates that this is called before the device
- * is probed. 1 indicates that this is called just after the
- * device has been probed
+ * @stage: The stage of the probing process this function is called during.
*/
-int clk_set_defaults(struct udevice *dev, int stage);
+int clk_set_defaults(struct udevice *dev, enum clk_defaults_stage stage);
#else
static inline int clk_set_defaults(struct udevice *dev, int stage)
{
diff --git a/include/configs/am64x_evm.h b/include/configs/am64x_evm.h
new file mode 100644
index 0000000..c2c2bf0
--- /dev/null
+++ b/include/configs/am64x_evm.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration header file for K3 AM642 SoC family
+ *
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ */
+
+#ifndef __CONFIG_AM642_EVM_H
+#define __CONFIG_AM642_EVM_H
+
+#include <linux/sizes.h>
+#include <config_distro_bootcmd.h>
+#include <environment/ti/mmc.h>
+#include <asm/arch/am64_hardware.h>
+#include <environment/ti/k3_dfu.h>
+
+/* DDR Configuration */
+#define CONFIG_SYS_SDRAM_BASE1 0x880000000
+
+#ifdef CONFIG_SYS_K3_SPL_ATF
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin"
+#endif
+
+#ifndef CONFIG_CPU_V7R
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
+#if defined(CONFIG_TARGET_AM642_A53_EVM)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
+ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE - 4)
+#else
+/*
+ * Maximum size in memory allocated to the SPL BSS. Keep it as tight as
+ * possible (to allow the build to go through), as this directly affects
+ * our memory footprint. The less we use for BSS the more we have available
+ * for everything else.
+ */
+#define CONFIG_SPL_BSS_MAX_SIZE 0x1000
+/*
+ * Link BSS to be within SPL in a dedicated region located near the top of
+ * the MCU SRAM, this way making it available also before relocation. Note
+ * that we are not using the actual top of the MCU SRAM as there is a memory
+ * location filled in by the boot ROM that we want to read out without any
+ * interference from the C context.
+ */
+#define CONFIG_SPL_BSS_START_ADDR (TI_SRAM_SCRATCH_BOARD_EEPROM_START -\
+ CONFIG_SPL_BSS_MAX_SIZE)
+/* Set the stack right below the SPL BSS section */
+#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR
+/* Configure R5 SPL post-relocation malloc pool in DDR */
+#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
+#endif
+
+#define PARTS_DEFAULT \
+ /* Linux partitions */ \
+ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0"
+
+/* U-Boot general configuration */
+#define EXTRA_ENV_AM642_BOARD_SETTINGS \
+ "findfdt=" \
+ "if test $board_name = am64x_gpevm; then " \
+ "setenv fdtfile k3-am642-evm.dtb; fi; " \
+ "if test $board_name = am64x_skevm; then " \
+ "setenv fdtfile k3-am642-sk.dtb; fi;" \
+ "if test $fdtfile = undefined; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0" \
+ "name_kern=Image\0" \
+ "console=ttyS2,115200n8\0" \
+ "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000 " \
+ "${mtdparts}\0" \
+ "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0"
+
+/* U-Boot MMC-specific configuration */
+#define EXTRA_ENV_AM642_BOARD_SETTINGS_MMC \
+ "boot=mmc\0" \
+ "mmcdev=1\0" \
+ "bootpart=1:2\0" \
+ "bootdir=/boot\0" \
+ "rd_spec=-\0" \
+ "init_mmc=run args_all args_mmc\0" \
+ "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
+ "get_overlay_mmc=" \
+ "fdt address ${fdtaddr};" \
+ "fdt resize 0x100000;" \
+ "for overlay in $name_overlays;" \
+ "do;" \
+ "load mmc ${bootpart} ${dtboaddr} ${bootdir}/${overlay} && " \
+ "fdt apply ${dtboaddr};" \
+ "done;\0" \
+ "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \
+ "${bootdir}/${name_kern}\0" \
+ "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \
+ "${bootdir}/${name_fit}\0" \
+ "partitions=" PARTS_DEFAULT
+
+#define EXTRA_ENV_DFUARGS \
+ DFU_ALT_INFO_MMC \
+ DFU_ALT_INFO_EMMC \
+ DFU_ALT_INFO_RAM \
+ DFU_ALT_INFO_OSPI
+
+/* Incorporate settings into the U-Boot environment */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ DEFAULT_LINUX_BOOT_ENV \
+ DEFAULT_MMC_TI_ARGS \
+ EXTRA_ENV_AM642_BOARD_SETTINGS \
+ EXTRA_ENV_AM642_BOARD_SETTINGS_MMC \
+ EXTRA_ENV_DFUARGS
+
+/* Now for the remaining common defines */
+#include <configs/ti_armv7_common.h>
+
+#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1
+
+/* MMC ENV related defines */
+#ifdef CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_SYS_MMC_ENV_PART 1
+#endif
+
+#endif /* __CONFIG_AM642_EVM_H */
diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h
index 76d7308..8c50fe9 100644
--- a/include/configs/am65x_evm.h
+++ b/include/configs/am65x_evm.h
@@ -22,7 +22,6 @@
#ifdef CONFIG_TARGET_AM654_A53_EVM
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \
CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE)
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x20000
#else
/*
* Maximum size in memory allocated to the SPL BSS. Keep it as tight as
@@ -45,7 +44,6 @@
/* Configure R5 SPL post-relocation malloc pool in DDR */
#define CONFIG_SYS_SPL_MALLOC_START 0x84000000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x5000
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF
@@ -56,12 +54,6 @@
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
-/*
- * If the maximum size is not declared then it is defined as
- * CONFIG_SYS_DFU_DATA_BUF_SIZE.
- */
-#define CONFIG_SYS_DFU_MAX_FILE_SIZE (1024 * 1024 * 8) /* 8 MiB */
-
#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
#define CONFIG_SYS_BOOTM_LEN SZ_64M
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h
index 8fe3226..b04a03f 100644
--- a/include/configs/apalis-imx8.h
+++ b/include/configs/apalis-imx8.h
@@ -21,8 +21,6 @@
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Networking */
-#define CONFIG_TFTP_TSIZE
-
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
diff --git a/include/configs/apalis-imx8x.h b/include/configs/apalis-imx8x.h
index fdb0da3..2ad4ca3 100644
--- a/include/configs/apalis-imx8x.h
+++ b/include/configs/apalis-imx8x.h
@@ -19,8 +19,6 @@
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-#define CONFIG_TFTP_TSIZE
-
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h
index 981f856..5719264 100644
--- a/include/configs/apalis-tk1.h
+++ b/include/configs/apalis-tk1.h
@@ -25,9 +25,6 @@
/* PCI networking support */
#define CONFIG_E1000_NO_NVM
-/* General networking support */
-#define CONFIG_TFTP_TSIZE
-
/*
* Custom Distro Boot configuration:
* 1. 8bit SD port (MMC1)
diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h
index f0c003d..9e5f523 100644
--- a/include/configs/apalis_t30.h
+++ b/include/configs/apalis_t30.h
@@ -28,9 +28,6 @@
/* PCI networking support */
#define CONFIG_E1000_NO_NVM
-/* General networking support */
-#define CONFIG_TFTP_TSIZE
-
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h
index 22ee2ba..2fa3485 100644
--- a/include/configs/colibri-imx6ull.h
+++ b/include/configs/colibri-imx6ull.h
@@ -18,9 +18,6 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
-/* Network */
-#define CONFIG_TFTP_TSIZE
-
/* ENET1 */
#define IMX_FEC_BASE ENET2_BASE_ADDR
@@ -143,7 +140,6 @@
#define CONFIG_USBD_HS
/* USB Device Firmware Update support */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h
index 59593f6..cb22b3c 100644
--- a/include/configs/colibri-imx8x.h
+++ b/include/configs/colibri-imx8x.h
@@ -21,9 +21,6 @@
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
-/* Networking */
-#define CONFIG_TFTP_TSIZE
-
#define CONFIG_IPADDR 192.168.10.2
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_SERVERIP 192.168.10.1
diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h
index 94e17bb..158bb09 100644
--- a/include/configs/colibri_t20.h
+++ b/include/configs/colibri_t20.h
@@ -17,9 +17,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2
-/* General networking support */
-#define CONFIG_TFTP_TSIZE
-
/* LCD support */
#define CONFIG_LCD_LOGO
diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h
index 94802a6..30b48c5 100644
--- a/include/configs/colibri_t30.h
+++ b/include/configs/colibri_t30.h
@@ -26,9 +26,6 @@
#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30
-/* General networking support */
-#define CONFIG_TFTP_TSIZE
-
/* Increase console I/O buffer size */
#undef CONFIG_SYS_CBSIZE
#define CONFIG_SYS_CBSIZE 1024
diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h
index cae7c14..5bd440f 100644
--- a/include/configs/colibri_vf.h
+++ b/include/configs/colibri_vf.h
@@ -143,6 +143,5 @@
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
/* USB DFU */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#endif /* __CONFIG_H */
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 55f77e4..bd4d6e8 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -81,7 +81,6 @@
#define CONFIG_AT91_WANTS_COMMON_PHY
/* DFU class support */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index 4a469af..d9be1c3 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -66,7 +66,6 @@
/* USB Gadget (DFU, UMS) */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB IDs */
diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h
index 005f65d..5e2aca3 100644
--- a/include/configs/exynos4-common.h
+++ b/include/configs/exynos4-common.h
@@ -19,7 +19,6 @@
/* SD/MMC configuration */
#define CONFIG_MMC_DEFAULT_DEV 0
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB Samsung's IDs */
diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h
index 2d854af..c8e9d3b 100644
--- a/include/configs/ge_bx50v3.h
+++ b/include/configs/ge_bx50v3.h
@@ -92,12 +92,12 @@
"swappartitions=" \
"setexpr partnum 3 - ${partnum}\0" \
"failbootcmd=" \
- "echo reached failbootcmd; " \
"cls; " \
"setcurs 5 4; " \
"lcdputs \"Monitor failed to start. " \
"Try again, or contact GE Service for support.\"; " \
- "bootcount reset; \0" \
+ "bootcount reset; " \
+ "while true; do sleep 1; done; \0" \
"altbootcmd=" \
"run doquiet; " \
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
@@ -115,23 +115,16 @@
"tryboot=" \
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
"run loadimage || run swappartitions && run loadimage || " \
- "setenv partnum 0 && echo MISSING IMAGE;" \
+ "setenv partnum 0 && echo MISSING IMAGE;" \
"run doboot; " \
"run failbootcmd\0" \
#define CONFIG_MMCBOOTCOMMAND \
- "if mmc dev ${devnum}; then " \
- "run doquiet; " \
- "run tryboot; " \
- "fi; " \
-
-#define CONFIG_USBBOOTCOMMAND \
- "echo Unsupported; " \
+ "run doquiet; " \
+ "run tryboot; " \
#ifdef CONFIG_CMD_NFS
#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND
-#elif CONFIG_CMD_USB
-#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND
#else
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
#endif
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h
new file mode 100644
index 0000000..4a3706d
--- /dev/null
+++ b/include/configs/imx7-cm.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2021 Ronetix GmbH
+ *
+ * Configuration settings for the Ronetix's iMX7-CM System-on-Module.
+ */
+
+#ifndef __IMX7_CM_CONFIG_H
+#define __IMX7_CM_CONFIG_H
+
+#include "mx7_common.h"
+
+#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
+
+#define CONFIG_ETHPRIME "FEC"
+
+#undef CONFIG_SYS_AUTOLOAD
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#undef CONFIG_BOOTCOMMAND
+
+/*
+ * Use:
+ * boot-mode=mix
+ * boot-mode=sd
+ * boot-mode=net
+ */
+#define MY_CONFIG_BOOT_MODE "boot-mode=sd\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ MY_CONFIG_BOOT_MODE \
+ "image=zImage\0" \
+ "console=ttymxc0\0" \
+ "fdt_file=imx7-cm.dtb\0" \
+ "fdt_addr=0x83000000\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ \
+ "bootsd=" \
+ "echo Booting from SD card ...; " \
+ "run mmcargs; " \
+ "mmc dev ${mmcdev};" \
+ "run loadimage; " \
+ "run loadfdt; " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "\0" \
+ \
+ "bootmix=" \
+ "echo Boot Kernel and FDT from TFTP, RootFs from SD card ...; " \
+ "run mmcargs; " \
+ "mmc dev ${mmcdev};" \
+ "tftp ${fdt_addr} ${fdt_file}; " \
+ "tftp ${image}; " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "\0" \
+ \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \
+ "\0" \
+ "bootnet=" \
+ "echo Booting from net ...; " \
+ "run netargs; " \
+ "tftp ${image}; " \
+ "tftp ${fdt_addr} ${fdt_file}; " \
+ "bootz ${loadaddr} - ${fdt_addr}; " \
+ "\0"
+
+#define CONFIG_BOOTCOMMAND "run boot${boot-mode}"
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+/* Physical Memory Map */
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* MMC Config*/
+#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
+
+/* USB Configs */
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+
+#define CONFIG_USBD_HS
+
+/* SPL */
+#include "imx7_spl.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h
new file mode 100644
index 0000000..faeee21
--- /dev/null
+++ b/include/configs/imx8mm-cl-iot-gate.h
@@ -0,0 +1,196 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019 NXP
+ */
+
+#ifndef __IMX8MM_CL_IOT_GATE_H
+#define __IMX8MM_CL_IOT_GATE_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x920000
+#define CONFIG_SPL_BSS_START_ADDR 0x910000
+#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x912000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_MMC)
+# define BOOT_TARGET_MMC(func) \
+ func(MMC, mmc, 2) \
+ func(MMC, mmc, 0)
+#else
+# define BOOT_TARGET_MMC(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_USB)
+# define BOOT_TARGET_USB(func) func(USB, usb, 0)
+#else
+# define BOOT_TARGET_USB(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_PXE)
+# define BOOT_TARGET_PXE(func) func(PXE, pxe, na)
+#else
+# define BOOT_TARGET_PXE(func)
+#endif
+
+#if CONFIG_IS_ENABLED(CMD_DHCP)
+# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na)
+#else
+# define BOOT_TARGET_DHCP(func)
+#endif
+
+#define BOOT_TARGET_DEVICES(func) \
+ BOOT_TARGET_USB(func) \
+ BOOT_TARGET_MMC(func) \
+ BOOT_TARGET_PXE(func) \
+ BOOT_TARGET_DHCP(func)
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "console=ttymxc2,115200 earlycon=ec_imx6q,0x30880000,115200\0" \
+ "fdt_addr=0x43000000\0" \
+ "fdt_addr_r=0x43000000\0" \
+ "boot_fit=no\0" \
+ "dfu_alt_info=mmc 2=flash-bin raw 0x42 0x250 mmcpart 1;" \
+ "u-boot-itb raw 0x300 0x1B00 mmcpart 1\0" \
+ "fdt_file=sb-iotgimx8.dtb\0" \
+ "fdtfile=sb-iotgimx8.dtb\0" \
+ "initrd_addr=0x43800000\0" \
+ "bootm_size=0x10000000\0" \
+ "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "kernel_addr_r=0x40480000\0" \
+ "pxefile_addr_r=0x40480000\0" \
+ "ramdisk_addr_r=0x43800000\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+ "bootm ${loadaddr}; " \
+ "else " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \
+ "bootm ${loadaddr}; " \
+ "else " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "fi;\0"
+
+#ifndef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "fi;"
+#endif
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
+
+#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* USDHC */
+#define CONFIG_FSL_USDHC
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#define CONFIG_ETHPRIME "FEC"
+
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_FEC_MXC_PHYADDR 0
+#define FEC_QUIRK_ENET_MAC
+
+#define IMX_FEC_BASE 0x30BE0000
+
+/* USB Configs */
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
+
+#endif /*__IMX8MM_CL_IOT_GATE_H*/
diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h
new file mode 100644
index 0000000..af5be68
--- /dev/null
+++ b/include/configs/imx8mm_icore_mx8mm.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#ifndef __IMX8MM_ICORE_MX8MM_H
+#define __IMX8MM_ICORE_MX8MM_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SPL_MAX_SIZE (148 * 1024)
+#define CONFIG_SYS_MONITOR_LEN SZ_512K
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+#define CONFIG_SYS_UBOOT_BASE \
+ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
+
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_SPL_STACK 0x920000
+# define CONFIG_SPL_BSS_START_ADDR 0x910000
+# define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
+# define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+# define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+# define CONFIG_MALLOC_F_ADDR 0x930000
+/* For RAW image gives a error info not panic */
+# define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 2) \
+ func(MMC, mmc, 0)
+#include <config_distro_bootcmd.h>
+#undef CONFIG_ISO_PARTITION
+#else
+#define BOOTENV
+#endif
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "fdt_addr_r=0x44000000\0" \
+ "kernel_addr_r=0x42000000\0" \
+ "ramdisk_addr_r=0x46400000\0" \
+ "scriptaddr=0x46000000\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "console=ttymxc1,115200\0" \
+ BOOTENV
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE SZ_2M
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_32M
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+
+/* SDRAM configuration */
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
+#define CONFIG_SYS_BOOTM_LEN SZ_256M
+
+#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END \
+ (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1))
+
+/* UART */
+#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* USDHC */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+/* I2C */
+#define CONFIG_SYS_I2C_SPEED 100000
+
+#endif /* __IMX8MM_ICORE_MX8MM_H */
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h
new file mode 100644
index 0000000..9db3bd5
--- /dev/null
+++ b/include/configs/imx8mq_cm.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8M_CM_H
+#define __IMX8M_CM_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
+
+#define CONFIG_SPL_MAX_SIZE (124 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SPL_STACK 0x187FF0
+#define CONFIG_SPL_BSS_START_ADDR 0x00180000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
+#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
+
+/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
+#define CONFIG_MALLOC_F_ADDR 0x182000
+/* For RAW image gives a error info not panic */
+#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
+
+#endif
+
+#define CONFIG_REMAKE_ELF
+
+/* ENET Config */
+/* ENET1 */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_ETHPRIME "FEC"
+#endif
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0) \
+ func(MMC, mmc, 1) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+#endif
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ BOOTENV \
+ "scriptaddr=0x43500000\0" \
+ "kernel_addr_r=0x40880000\0" \
+ "image=Image\0" \
+ "console=ttymxc0,115200\0" \
+ "fdt_addr=0x43000000\0" \
+ "boot_fdt=try\0" \
+ "fdt_file=imx8mq-cm.dtb\0" \
+ "initrd_addr=0x43800000\0" \
+ "bootm_size=0x10000000\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x40480000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
+#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+#define PHYS_SDRAM 0x40000000
+#define PHYS_SDRAM_SIZE 0x40000000 /* 1 GB DDR */
+
+#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_IMX_BOOTAUX
+
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+#endif
diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h
index d313329..b1e6a56 100644
--- a/include/configs/mx53ppd.h
+++ b/include/configs/mx53ppd.h
@@ -64,23 +64,25 @@
"vt.global_cursor_default=0 bootcause=${bootcause} ${quiet}\0" \
"bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \
"rootwait ${bootargs}\0" \
- "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
- "then setenv quiet; fi\0" \
+ "doquiet=" \
+ "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \
+ "then setenv quiet; fi\0" \
"hasfirstboot=" \
"test -e ${dev} ${devnum}:${partnum} /boot/bootcause/firstboot\0" \
- "swappartitions=setexpr partnum 3 - ${partnum}\0" \
+ "swappartitions=" \
+ "setexpr partnum 3 - ${partnum}\0" \
"failbootcmd=" \
"cls; " \
"setcurs 5 4; " \
"lcdputs \"Monitor failed to start. " \
"Try again, or contact GE Service for support.\"; " \
- "bootcount reset; \0" \
+ "bootcount reset; " \
+ "while true; do sleep 1; done; \0" \
"altbootcmd=" \
"run doquiet; " \
"setenv partnum 1; run hasfirstboot || setenv partnum 2; " \
"run hasfirstboot || setenv partnum 0; " \
"if test ${partnum} != 0; then " \
- "setenv bootcause REVERT; " \
"run swappartitions loadimage doboot; " \
"fi; " \
"run failbootcmd\0" \
@@ -101,10 +103,8 @@
"lcd:800x480-24@60,monitor=lcd\0" \
#define CONFIG_MMCBOOTCOMMAND \
- "if mmc dev ${devnum}; then " \
- "run doquiet; " \
- "run tryboot; " \
- "fi; " \
+ "run doquiet; " \
+ "run tryboot; " \
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h
index 23368de..fe991ea 100644
--- a/include/configs/nokia_rx51.h
+++ b/include/configs/nokia_rx51.h
@@ -85,9 +85,6 @@
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
-/* Watchdog support */
-#define CONFIG_HW_WATCHDOG
-
/*
* Framebuffer
*/
diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h
index 7c585ad..2800896 100644
--- a/include/configs/octeontx2_common.h
+++ b/include/configs/octeontx2_common.h
@@ -28,9 +28,6 @@
/* Allow environment variable to be overwritten */
#define CONFIG_ENV_OVERWRITE
-/** Reduce hashes printed out */
-#define CONFIG_TFTP_TSIZE
-
/* Autoboot options */
#define CONFIG_RESET_TO_RETRY
#define CONFIG_BOOT_RETRY_TIME -1
diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h
index 434e544..0e4a176 100644
--- a/include/configs/octeontx_common.h
+++ b/include/configs/octeontx_common.h
@@ -51,9 +51,6 @@
/* Allow environment variable to be overwritten */
#define CONFIG_ENV_OVERWRITE
-/** Reduce hashes printed out */
-#define CONFIG_TFTP_TSIZE
-
/* Autoboot options */
#define CONFIG_RESET_TO_RETRY
#define CONFIG_BOOT_RETRY_TIME -1
diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h
index 0c86196..fc70dc6 100644
--- a/include/configs/odroid_xu3.h
+++ b/include/configs/odroid_xu3.h
@@ -27,7 +27,6 @@
#define CONFIG_USB_EHCI_EXYNOS
/* DFU */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define DFU_MANIFEST_POLL_TIMEOUT 25000
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h
index 19c8aeb..6199f0d 100644
--- a/include/configs/pico-imx6.h
+++ b/include/configs/pico-imx6.h
@@ -38,7 +38,6 @@
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_DFU_ENV_SETTINGS \
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
index 747ef09..04a2531 100644
--- a/include/configs/pico-imx6ul.h
+++ b/include/configs/pico-imx6ul.h
@@ -49,7 +49,6 @@
#define CONFIG_USBD_HS
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_DFU_ENV_SETTINGS \
diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
deleted file mode 100644
index 5e787d7..0000000
--- a/include/configs/qemu-mips.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-/*
- * This file contains the configuration parameters for qemu-mips target.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_QEMU_MIPS
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addmisc=setenv bootargs ${bootargs} " \
- "console=ttyS0,${baudrate} " \
- "panic=1\0" \
- "bootfile=/tftpboot/vmlinux\0" \
- "load=tftp 80500000 ${u-boot}\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "bootp;bootelf"
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_DRIVER_NE2000
-#define CONFIG_DRIVER_NE2000_BASE 0xb4000300
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 115200
-#define CONFIG_SYS_NS16550_COM1 0xb40003f8
-
-#ifdef CONFIG_SYS_BIG_ENDIAN
-#define CONFIG_IDE_SWAP_IO
-#endif
-
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
-
-#define CONFIG_SYS_IDE_MAXDEVICE 4
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
-
-#define CONFIG_SYS_MHZ 132
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-
-/* Cached addr */
-#define CONFIG_SYS_SDRAM_BASE 0x80000000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0x81000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-
-/* We boot from this flash, selected with dip switch */
-#define CONFIG_SYS_FLASH_BASE 0xbfc00000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-/* Address and size of Primary Environment Sector */
-
-#define MEM_SIZE 128
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
deleted file mode 100644
index 0ed00bc..0000000
--- a/include/configs/qemu-mips64.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- */
-
-/*
- * This file contains the configuration parameters for qemu-mips64 target.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_QEMU_MIPS
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addmisc=setenv bootargs ${bootargs} " \
- "console=ttyS0,${baudrate} " \
- "panic=1\0" \
- "bootfile=/tftpboot/vmlinux\0" \
- "load=tftp ffffffff80500000 ${u-boot}\0" \
- ""
-
-#define CONFIG_BOOTCOMMAND "bootp;bootelf"
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-#define CONFIG_DRIVER_NE2000
-#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 115200
-#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8
-
-#ifdef CONFIG_SYS_BIG_ENDIAN
-#define CONFIG_IDE_SWAP_IO
-#endif
-
-#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
-#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-#define CONFIG_SYS_ATA_BASE_ADDR 0xffffffffb4000000
-
-#define CONFIG_SYS_IDE_MAXDEVICE 4
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
-
-#define CONFIG_SYS_MHZ 132
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-
-/* Cached addr */
-#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-
-/* We boot from this flash, selected with dip switch */
-#define CONFIG_SYS_FLASH_BASE 0xffffffffbfc00000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 128
-
-/* Address and size of Primary Environment Sector */
-
-#define MEM_SIZE 128
-
-#endif /* __CONFIG_H */
diff --git a/include/configs/rpi.h b/include/configs/rpi.h
index 834f1cd..522b41c 100644
--- a/include/configs/rpi.h
+++ b/include/configs/rpi.h
@@ -68,15 +68,8 @@
#define CONFIG_LCD_DT_SIMPLEFB
#define CONFIG_VIDEO_BCM2835
-#ifdef CONFIG_CMD_USB
-#define CONFIG_TFTP_TSIZE
-#endif
-
/* DFU over USB/UDC */
#ifdef CONFIG_CMD_DFU
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
-#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_2M
-
#ifdef CONFIG_ARM64
#define KERNEL_FILENAME "Image"
#else
diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h
index 9688bdc..6af6009 100644
--- a/include/configs/s5p_goni.h
+++ b/include/configs/s5p_goni.h
@@ -41,7 +41,6 @@
#define CONFIG_PWM 1
/* USB Composite download gadget - g_dnl */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB Samsung's IDs */
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index e18af74..f96dd77 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -143,7 +143,6 @@
#define CONFIG_USBD_HS
/* USB Device Firmware Update support */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#endif /* CONFIG_SPL_BUILD */
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
new file mode 100644
index 0000000..4fad69b
--- /dev/null
+++ b/include/configs/sifive-unmatched.h
@@ -0,0 +1,83 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020-2021 SiFive, Inc
+ *
+ * Authors:
+ * Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __SIFIVE_UNMATCHED_H
+#define __SIFIVE_UNMATCHED_H
+
+#include <linux/sizes.h>
+
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE 0x00100000
+#define CONFIG_SPL_BSS_START_ADDR 0x85000000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+ CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
+
+#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \
+ GENERATED_GBL_DATA_SIZE)
+
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_MALLOC_LEN SZ_8M
+
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+
+#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
+
+#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */
+
+#define CONFIG_SYS_CACHELINE_SIZE 64
+
+/* Environment options */
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+ func(NVME, nvme, 0) \
+ func(USB, usb, 0) \
+ func(MMC, mmc, 0) \
+ func(PXE, pxe, na) \
+ func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47"
+#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985"
+#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4"
+
+#define PARTS_DEFAULT \
+ "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
+ "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
+ "name=system,size=-,bootable,type=${type_guid_gpt_system};"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "kernel_addr_r=0x84000000\0" \
+ "fdt_addr_r=0x88000000\0" \
+ "scriptaddr=0x88100000\0" \
+ "pxefile_addr_r=0x88200000\0" \
+ "ramdisk_addr_r=0x88300000\0" \
+ "kernel_comp_addr_r=0x90000000\0" \
+ "kernel_comp_size=0x4000000\0" \
+ "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
+ "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
+ "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
+ "partitions=" PARTS_DEFAULT "\0" \
+ BOOTENV
+
+#define CONFIG_PREBOOT \
+ "setenv fdt_addr ${fdtcontroladdr};" \
+ "fdt addr ${fdtcontroladdr};"
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* __SIFIVE_UNMATCHED_H */
diff --git a/include/configs/sipeed-maix.h b/include/configs/sipeed-maix.h
index 4c1ff98..0fbe8a5 100644
--- a/include/configs/sipeed-maix.h
+++ b/include/configs/sipeed-maix.h
@@ -15,8 +15,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_SDRAM_BASE 0x80000000
-/* Don't relocate into AI ram since it isn't set up yet */
-#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M)
+#define CONFIG_SYS_SDRAM_SIZE SZ_8M
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h
index 6e715dc..5e8637e 100644
--- a/include/configs/smartweb.h
+++ b/include/configs/smartweb.h
@@ -122,7 +122,6 @@
#define CONFIG_USB_GADGET_AT91
/* DFU class support */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#endif
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index f5f99ee..34a0041 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -49,7 +49,6 @@
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_TFTP_PORT
-#define CONFIG_TFTP_TSIZE
/* USB */
#define CONFIG_USB_ATMEL
diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h
index bbd3b11..077e9d6 100644
--- a/include/configs/snapper9g45.h
+++ b/include/configs/snapper9g45.h
@@ -49,7 +49,6 @@
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_TFTP_PORT
-#define CONFIG_TFTP_TSIZE
/* MMC */
#define CONFIG_GENERIC_ATMEL_MCI
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 62b327c..c5e4292 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -148,7 +148,6 @@
* USB Gadget (DFU, UMS)
*/
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* USB IDs */
diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h
index e31b77c..7af7b08 100644
--- a/include/configs/syzygy_hub.h
+++ b/include/configs/syzygy_hub.h
@@ -58,7 +58,6 @@
"jtagboot=echo TFTPing FIT to RAM... && " \
"tftpboot ${load_addr} ${fit_image} && " \
"bootm ${load_addr}\0" \
- DFU_ALT_INFO \
BOOTENV
#include <configs/zynq-common.h>
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index 39eae8e..6e86946 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -92,7 +92,6 @@
#define CONFIG_USB_GADGET_AT91
/* DFU class support */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
#define DFU_MANIFEST_POLL_TIMEOUT 25000
#endif
diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h
index e6b61c4..201f4bc 100644
--- a/include/configs/tegra-common-usb-gadget.h
+++ b/include/configs/tegra-common-usb-gadget.h
@@ -13,8 +13,6 @@
#define CONFIG_CI_UDC_HAS_HOSTPC
#endif
/* DFU protocol */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M
-#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M
#endif
#endif /* _TEGRA_COMMON_USB_GADGET_H_ */
diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h
index 010d28a..c12cd7c 100644
--- a/include/configs/topic_miami.h
+++ b/include/configs/topic_miami.h
@@ -49,7 +49,6 @@
"${devicetree_addr}; " \
"fi\0"
/* Note that addresses here should match the addresses in the env */
-# undef DFU_ALT_INFO
# define DFU_ALT_INFO \
"dfu_alt_info=" \
"uImage ram 0x2080000 0x500000;" \
diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h
index 0b55c14..7da18f9 100644
--- a/include/configs/turris_omnia.h
+++ b/include/configs/turris_omnia.h
@@ -108,12 +108,35 @@
#include <config_distro_bootcmd.h>
+/*
+ * The factory reset bootcommand on Omnia first sets all the front LEDs to green
+ * and then tries to load the rescue image from SPI flash memory and boot it
+ */
+#define TURRIS_OMNIA_BOOTCMD_RESCUE \
+ "i2c dev 2; " \
+ "i2c mw 0x2a.1 0x3 0x1c 1; " \
+ "i2c mw 0x2a.1 0x4 0x1c 1; " \
+ "mw.l 0x01000000 0x00ff000c; " \
+ "i2c write 0x01000000 0x2a.1 0x5 4 -s; " \
+ "setenv bootargs \"earlyprintk console=ttyS0,115200" \
+ " omniarescue=$omnia_reset rescue_mode=$omnia_reset\"; " \
+ "sf probe; " \
+ "sf read 0x1000000 0x100000 0x700000; " \
+ "lzmadec 0x1000000 0x1700000; " \
+ "if gpio input gpio@71_4; then " \
+ "bootm 0x1700000#sfp; " \
+ "else " \
+ "bootm 0x1700000; " \
+ "fi; " \
+ "bootz 0x1000000"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
RELOCATION_LIMITS_ENV_SETTINGS \
LOAD_ADDRESS_ENV_SETTINGS \
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
"console=ttyS0,115200\0" \
"ethact=ethernet@34000\0" \
+ "bootcmd_rescue=" TURRIS_OMNIA_BOOTCMD_RESCUE "\0" \
BOOTENV
#endif /* CONFIG_SPL_BUILD */
diff --git a/include/configs/warp.h b/include/configs/warp.h
index 0f97804..bda8ff9 100644
--- a/include/configs/warp.h
+++ b/include/configs/warp.h
@@ -50,7 +50,6 @@
#define CONFIG_USBD_HS
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* I2C Configs */
diff --git a/include/configs/warp7.h b/include/configs/warp7.h
index 8eb1060..a5d52e3 100644
--- a/include/configs/warp7.h
+++ b/include/configs/warp7.h
@@ -149,7 +149,6 @@
#define CONFIG_USBD_HS
/* USB Device Firmware Update support */
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01"
diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h
index f186dd6..ab39b0b 100644
--- a/include/configs/x86-common.h
+++ b/include/configs/x86-common.h
@@ -76,7 +76,6 @@
* USB configuration
*/
-#define CONFIG_TFTP_TSIZE
#define CONFIG_BOOTP_BOOTFILESIZE
/* Default environment */
diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h
index f1d2594..ebe8196 100644
--- a/include/configs/xilinx_versal.h
+++ b/include/configs/xilinx_versal.h
@@ -47,23 +47,8 @@
#define CONFIG_SYS_MAXARGS 64
#if defined(CONFIG_CMD_DFU)
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_THOR_RESET_OFF
-#define DFU_ALT_INFO_RAM \
- "dfu_ram_info=" \
- "setenv dfu_alt_info " \
- "Image ram 80000 $kernel_size_r\\\\;" \
- "system.dtb ram $fdt_addr_r $fdt_size_r\0" \
- "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
- "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
-
-#define DFU_ALT_INFO \
- DFU_ALT_INFO_RAM
-#endif
-
-#if !defined(DFU_ALT_INFO)
-# define DFU_ALT_INFO
#endif
/* Ethernet driver */
@@ -129,23 +114,40 @@
#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
"jtag "
+#define BOOT_TARGET_DEVICES_USB_DFU(func) \
+ func(USB_DFU, usb_dfu, 0) func(USB_DFU, usb_dfu, 1)
+
-#define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0)
+#define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \
+ "$scriptaddr $script_size_f && " \
+ "dfu " #instance " ram " #instance " 60 && " \
+ "echo DFU" #instance ": Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; " \
+ "echo DFU" #instance ": SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) \
+ ""
+
+#define BOOT_TARGET_DEVICES_USB_THOR(func) \
+ func(USB_THOR, usb_thor, 0) func(USB_THOR, usb_thor, 1)
-#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \
- "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \
- "$script_size_f; dfu 0 ram 0 && " \
- "echo DFU: Trying to boot script at ${scriptaddr} && " \
+#define BOOTENV_DEV_USB_THOR(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \
+ "$scriptaddr $script_size_f && " \
+ "thordown " #instance " ram " #instance " && " \
+ "echo THOR" #instance ": Trying to boot script at ${scriptaddr} && " \
"source ${scriptaddr}; " \
- "echo DFU: SCRIPT FAILED: continuing...;\0"
+ "echo THOR" #instance ": SCRIPT FAILED: continuing...;\0"
-#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \
- "dfu_usb "
+#define BOOTENV_DEV_NAME_USB_THOR(devtypeu, devtypel, instance) \
+ ""
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_JTAG(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_XSPI(func) \
- BOOT_TARGET_DEVICES_DFU_USB(func) \
+ BOOT_TARGET_DEVICES_USB_DFU(func) \
+ BOOT_TARGET_DEVICES_USB_THOR(func) \
BOOT_TARGET_DEVICES_PXE(func) \
BOOT_TARGET_DEVICES_DHCP(func)
@@ -155,8 +157,7 @@
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
- BOOTENV \
- DFU_ALT_INFO
+ BOOTENV
#endif
#endif /* __XILINX_VERSAL_H */
diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h
index 15ad419..cadaf1a 100644
--- a/include/configs/xilinx_zynqmp.h
+++ b/include/configs/xilinx_zynqmp.h
@@ -27,7 +27,7 @@
#endif
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000)
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x4000000)
/* Serial setup */
#define CONFIG_CPU_ARMV8
@@ -52,21 +52,8 @@
#define CONFIG_SYS_LOAD_ADDR 0x8000000
#if defined(CONFIG_ZYNQMP_USB)
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000
#define DFU_DEFAULT_POLL_TIMEOUT 300
#define CONFIG_THOR_RESET_OFF
-#define DFU_ALT_INFO_RAM \
- "dfu_ram_info=" \
- "setenv dfu_alt_info " \
- "Image ram 80000 $kernel_size_r\\\\;" \
- "system.dtb ram $fdt_addr_r $fdt_size_r\0" \
- "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
- "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" \
- "dfu_ram_tftp=run dfu_ram_info && setenv updatefile boot && " \
- "setenv loadaddr 10000000 && dfu tftp ram 0\0"
-
-#define DFU_ALT_INFO \
- DFU_ALT_INFO_RAM
#ifndef CONFIG_SPL_BUILD
# define PARTS_DEFAULT \
@@ -76,10 +63,6 @@
#endif
#endif
-#if !defined(DFU_ALT_INFO)
-# define DFU_ALT_INFO
-#endif
-
#if !defined(PARTS_DEFAULT)
# define PARTS_DEFAULT
#endif
@@ -179,11 +162,41 @@
#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
"jtag "
+#define BOOT_TARGET_DEVICES_USB_DFU(func) \
+ func(USB_DFU, usb_dfu, 0) func(USB_DFU, usb_dfu, 1)
+
+#define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \
+ "$scriptaddr $script_size_f && " \
+ "dfu " #instance " ram " #instance " 60 && " \
+ "echo DFU" #instance ": Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; " \
+ "echo DFU" #instance ": SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) \
+ ""
+
+#define BOOT_TARGET_DEVICES_USB_THOR(func) \
+ func(USB_THOR, usb_thor, 0) func(USB_THOR, usb_thor, 1)
+
+#define BOOTENV_DEV_USB_THOR(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \
+ "$scriptaddr $script_size_f && " \
+ "thordown " #instance " ram " #instance " && " \
+ "echo THOR" #instance ": Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; " \
+ "echo THOR" #instance ": SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_USB_THOR(devtypeu, devtypel, instance) \
+ ""
+
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_JTAG(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_QSPI(func) \
BOOT_TARGET_DEVICES_NAND(func) \
+ BOOT_TARGET_DEVICES_USB_DFU(func) \
+ BOOT_TARGET_DEVICES_USB_THOR(func) \
BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_SCSI(func) \
BOOT_TARGET_DEVICES_PXE(func) \
@@ -195,8 +208,7 @@
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
ENV_MEM_LAYOUT_SETTINGS \
- BOOTENV \
- DFU_ALT_INFO
+ BOOTENV
#endif
/* SPL can't handle all huge variables - define just DFU */
diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h
index 1607a8d..7859b77 100644
--- a/include/configs/zynq-common.h
+++ b/include/configs/zynq-common.h
@@ -58,41 +58,10 @@
#ifdef CONFIG_USB_EHCI_ZYNQ
# define CONFIG_EHCI_IS_TDI
-# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define DFU_DEFAULT_POLL_TIMEOUT 300
# define CONFIG_THOR_RESET_OFF
-# define DFU_ALT_INFO_RAM \
- "dfu_ram_info=" \
- "setenv dfu_alt_info " \
- "${kernel_image} ram 0x3000000 0x500000\\\\;" \
- "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \
- "${ramdisk_image} ram 0x2000000 0x600000\0" \
- "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
- "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
-
-# if defined(CONFIG_MMC_SDHCI_ZYNQ)
-# define DFU_ALT_INFO_MMC \
- "dfu_mmc_info=" \
- "setenv dfu_alt_info " \
- "${kernel_image} fat 0 1\\\\;" \
- "${devicetree_image} fat 0 1\\\\;" \
- "${ramdisk_image} fat 0 1\0" \
- "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
- "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
-
-# define DFU_ALT_INFO \
- DFU_ALT_INFO_RAM \
- DFU_ALT_INFO_MMC
-# else
-# define DFU_ALT_INFO \
- DFU_ALT_INFO_RAM
-# endif
#endif
-#if !defined(DFU_ALT_INFO)
-# define DFU_ALT_INFO
-#endif
-
/* enable preboot to be loaded before CONFIG_BOOTDELAY */
/* Boot configuration */
@@ -180,12 +149,42 @@
#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \
"jtag "
+#define BOOT_TARGET_DEVICES_USB_DFU(func) \
+ func(USB_DFU, usb_dfu, 0) func(USB_DFU, usb_dfu, 1)
+
+#define BOOTENV_DEV_USB_DFU(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \
+ "$scriptaddr $script_size_f && " \
+ "dfu " #instance " ram " #instance " 60 && " \
+ "echo DFU" #instance ": Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; " \
+ "echo DFU" #instance ": SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_USB_DFU(devtypeu, devtypel, instance) \
+ ""
+
+#define BOOT_TARGET_DEVICES_USB_THOR(func) \
+ func(USB_THOR, usb_thor, 0) func(USB_THOR, usb_thor, 1)
+
+#define BOOTENV_DEV_USB_THOR(devtypeu, devtypel, instance) \
+ "bootcmd_" #devtypel #instance "=setenv dfu_alt_info boot.scr ram " \
+ "$scriptaddr $script_size_f && " \
+ "thordown " #instance " ram " #instance " && " \
+ "echo THOR" #instance ": Trying to boot script at ${scriptaddr} && " \
+ "source ${scriptaddr}; " \
+ "echo THOR" #instance ": SCRIPT FAILED: continuing...;\0"
+
+#define BOOTENV_DEV_NAME_USB_THOR(devtypeu, devtypel, instance) \
+ ""
+
#define BOOT_TARGET_DEVICES(func) \
BOOT_TARGET_DEVICES_JTAG(func) \
BOOT_TARGET_DEVICES_MMC(func) \
BOOT_TARGET_DEVICES_QSPI(func) \
BOOT_TARGET_DEVICES_NAND(func) \
BOOT_TARGET_DEVICES_NOR(func) \
+ BOOT_TARGET_DEVICES_USB_DFU(func) \
+ BOOT_TARGET_DEVICES_USB_THOR(func) \
BOOT_TARGET_DEVICES_USB(func) \
BOOT_TARGET_DEVICES_PXE(func) \
BOOT_TARGET_DEVICES_DHCP(func)
@@ -203,7 +202,6 @@
"kernel_addr_r=0x2000000\0" \
"scriptaddr=0x3000000\0" \
"ramdisk_addr_r=0x3100000\0" \
- DFU_ALT_INFO \
BOOTENV
#endif
diff --git a/include/console.h b/include/console.h
index 7e628c0..f848bcb 100644
--- a/include/console.h
+++ b/include/console.h
@@ -72,7 +72,8 @@
*
* @str: Place to put string
* @maxlen: Maximum length of @str including nul terminator
- * @return length of string returned
+ * @return length of string returned, or -ENOSPC if the console buffer was
+ * overflowed by the output
*/
int console_record_readline(char *str, int maxlen);
diff --git a/include/dfu.h b/include/dfu.h
index d18b701..afada39 100644
--- a/include/dfu.h
+++ b/include/dfu.h
@@ -100,12 +100,6 @@
};
#define DFU_NAME_SIZE 32
-#ifndef CONFIG_SYS_DFU_DATA_BUF_SIZE
-#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024*1024*8) /* 8 MiB */
-#endif
-#ifndef CONFIG_SYS_DFU_MAX_FILE_SIZE
-#define CONFIG_SYS_DFU_MAX_FILE_SIZE CONFIG_SYS_DFU_DATA_BUF_SIZE
-#endif
#ifndef DFU_DEFAULT_POLL_TIMEOUT
#define DFU_DEFAULT_POLL_TIMEOUT 0
#endif
diff --git a/include/display_options.h b/include/display_options.h
index 049688e..43810cb 100644
--- a/include/display_options.h
+++ b/include/display_options.h
@@ -47,6 +47,31 @@
int print_buffer(ulong addr, const void *data, uint width, uint count,
uint linelen);
+/*
+ * Maximum length of an output line is when width == 1
+ * 9 for address,
+ * a space, two hex digits and an ASCII character for each byte
+ * 2 spaces between the hex and ASCII
+ * \0 terminator
+ */
+#define HEXDUMP_MAX_BUF_LENGTH(bytes) (9 + (bytes) * 4 + 3)
+
+/**
+ * hexdump_line() - Print out a single line of a hex dump
+ *
+ * @addr: Starting address to display at start of line
+ * @data: pointer to data buffer
+ * @width: data value width. May be 1, 2, or 4.
+ * @count: number of values to display
+ * @linelen: Number of values to print per line; specify 0 for default length
+ * @out: Output buffer to hold the dump
+ * @size: Size of output buffer in bytes
+ * @return number of bytes processed, if OK, -ENOSPC if buffer too small
+ *
+ */
+int hexdump_line(ulong addr, const void *data, uint width, uint count,
+ uint linelen, char *out, int size);
+
/**
* display_options() - display the version string / build tag
*
diff --git a/include/dm/ofnode.h b/include/dm/ofnode.h
index 2c0597c..8a69fd8 100644
--- a/include/dm/ofnode.h
+++ b/include/dm/ofnode.h
@@ -511,6 +511,16 @@
phys_addr_t ofnode_get_addr(ofnode node);
/**
+ * ofnode_get_size() - get size from a node
+ *
+ * This reads the register size from a node
+ *
+ * @node: node to read from
+ * @return size of the address, or FDT_SIZE_T_NONE if not present or invalid
+ */
+fdt_size_t ofnode_get_size(ofnode node);
+
+/**
* ofnode_stringlist_search() - find a string in a string list and return index
*
* Note that it is possible for this function to succeed on property values
diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h
index fe852bb..6b0d5b4 100644
--- a/include/dt-bindings/clock/k210-sysctl.h
+++ b/include/dt-bindings/clock/k210-sysctl.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
+ * Copyright (C) 2019-21 Sean Anderson <seanga2@gmail.com>
*/
#ifndef CLOCK_K210_SYSCTL_H
@@ -9,52 +9,50 @@
/*
* Arbitrary identifiers for clocks.
*/
-#define K210_CLK_NONE 0
-#define K210_CLK_IN0_H 1
-#define K210_CLK_PLL0_H 2
-#define K210_CLK_PLL0 3
-#define K210_CLK_PLL1 4
-#define K210_CLK_PLL2 5
-#define K210_CLK_PLL2_H 6
-#define K210_CLK_CPU 7
-#define K210_CLK_SRAM0 8
-#define K210_CLK_SRAM1 9
-#define K210_CLK_APB0 10
-#define K210_CLK_APB1 11
-#define K210_CLK_APB2 12
-#define K210_CLK_ROM 13
-#define K210_CLK_DMA 14
-#define K210_CLK_AI 15
-#define K210_CLK_DVP 16
-#define K210_CLK_FFT 17
-#define K210_CLK_GPIO 18
-#define K210_CLK_SPI0 19
-#define K210_CLK_SPI1 20
-#define K210_CLK_SPI2 21
-#define K210_CLK_SPI3 22
-#define K210_CLK_I2S0 23
-#define K210_CLK_I2S1 24
-#define K210_CLK_I2S2 25
-#define K210_CLK_I2S0_M 26
-#define K210_CLK_I2S1_M 27
-#define K210_CLK_I2S2_M 28
-#define K210_CLK_I2C0 29
-#define K210_CLK_I2C1 30
-#define K210_CLK_I2C2 31
-#define K210_CLK_UART1 32
-#define K210_CLK_UART2 33
-#define K210_CLK_UART3 34
-#define K210_CLK_AES 35
-#define K210_CLK_FPIOA 36
-#define K210_CLK_TIMER0 37
-#define K210_CLK_TIMER1 38
-#define K210_CLK_TIMER2 39
-#define K210_CLK_WDT0 40
-#define K210_CLK_WDT1 41
-#define K210_CLK_SHA 42
-#define K210_CLK_OTP 43
-#define K210_CLK_RTC 44
-#define K210_CLK_ACLK 45
-#define K210_CLK_CLINT 46
+
+#define K210_CLK_PLL0 0
+#define K210_CLK_PLL1 1
+#define K210_CLK_PLL2 2
+#define K210_CLK_CPU 3
+#define K210_CLK_SRAM0 4
+#define K210_CLK_SRAM1 5
+#define K210_CLK_ACLK 6
+#define K210_CLK_CLINT 7
+#define K210_CLK_APB0 8
+#define K210_CLK_APB1 9
+#define K210_CLK_APB2 10
+#define K210_CLK_ROM 11
+#define K210_CLK_DMA 12
+#define K210_CLK_AI 13
+#define K210_CLK_DVP 14
+#define K210_CLK_FFT 15
+#define K210_CLK_GPIO 16
+#define K210_CLK_SPI0 17
+#define K210_CLK_SPI1 18
+#define K210_CLK_SPI2 19
+#define K210_CLK_SPI3 20
+#define K210_CLK_I2S0 21
+#define K210_CLK_I2S1 22
+#define K210_CLK_I2S2 23
+#define K210_CLK_I2S0_M 24
+#define K210_CLK_I2S1_M 25
+#define K210_CLK_I2S2_M 26
+#define K210_CLK_I2C0 27
+#define K210_CLK_I2C1 28
+#define K210_CLK_I2C2 29
+#define K210_CLK_UART1 30
+#define K210_CLK_UART2 31
+#define K210_CLK_UART3 32
+#define K210_CLK_AES 33
+#define K210_CLK_FPIOA 34
+#define K210_CLK_TIMER0 35
+#define K210_CLK_TIMER1 36
+#define K210_CLK_TIMER2 37
+#define K210_CLK_WDT0 38
+#define K210_CLK_WDT1 39
+#define K210_CLK_SHA 40
+#define K210_CLK_OTP 41
+#define K210_CLK_RTC 42
+#define K210_CLK_IN0 43
#endif /* CLOCK_K210_SYSCTL_H */
diff --git a/include/dt-bindings/clock/sifive-fu740-prci.h b/include/dt-bindings/clock/sifive-fu740-prci.h
new file mode 100644
index 0000000..c122478
--- /dev/null
+++ b/include/dt-bindings/clock/sifive-fu740-prci.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ * Zong Li
+ * Pragnesh Patel
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
+#define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H
+
+/* Clock indexes for use by Device Tree data and the PRCI driver */
+
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_DVFSCOREPLL 3
+#define PRCI_CLK_HFPCLKPLL 4
+#define PRCI_CLK_CLTXPLL 5
+#define PRCI_CLK_TLCLK 6
+#define PRCI_CLK_PCLK 7
+#define PRCI_CLK_PCIEAUX 8
+
+#endif
diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h
index 4f7e282..8353a78 100644
--- a/include/dt-bindings/comphy/comphy_data.h
+++ b/include/dt-bindings/comphy/comphy_data.h
@@ -6,52 +6,44 @@
#ifndef _COMPHY_DATA_H_
#define _COMPHY_DATA_H_
-#define PHY_SPEED_1_25G 0
-#define PHY_SPEED_1_5G 1
-#define PHY_SPEED_2_5G 2
-#define PHY_SPEED_3G 3
-#define PHY_SPEED_3_125G 4
-#define PHY_SPEED_5G 5
-#define PHY_SPEED_5_15625G 6
-#define PHY_SPEED_6G 7
-#define PHY_SPEED_6_25G 8
-#define PHY_SPEED_10_3125G 9
-#define PHY_SPEED_MAX 10
-#define PHY_SPEED_INVALID 0xff
+#define COMPHY_SPEED_1_25G 0
+#define COMPHY_SPEED_2_5G 1
+#define COMPHY_SPEED_3_125G 2
+#define COMPHY_SPEED_5G 3
+#define COMPHY_SPEED_5_15625G 4
+#define COMPHY_SPEED_6G 5
+#define COMPHY_SPEED_10_3125G 6
+#define COMPHY_SPEED_MAX 7
+#define COMPHY_SPEED_INVALID 0xff
-#define PHY_TYPE_UNCONNECTED 0
-#define PHY_TYPE_PEX0 1
-#define PHY_TYPE_PEX1 2
-#define PHY_TYPE_PEX2 3
-#define PHY_TYPE_PEX3 4
-#define PHY_TYPE_SATA0 5
-#define PHY_TYPE_SATA1 6
-#define PHY_TYPE_SATA2 7
-#define PHY_TYPE_SATA3 8
-#define PHY_TYPE_SGMII0 9
-#define PHY_TYPE_SGMII1 10
-#define PHY_TYPE_SGMII2 11
-#define PHY_TYPE_SGMII3 12
-#define PHY_TYPE_QSGMII 13
-#define PHY_TYPE_USB3_HOST0 14
-#define PHY_TYPE_USB3_HOST1 15
-#define PHY_TYPE_USB3_DEVICE 16
-#define PHY_TYPE_XAUI0 17
-#define PHY_TYPE_XAUI1 18
-#define PHY_TYPE_XAUI2 19
-#define PHY_TYPE_XAUI3 20
-#define PHY_TYPE_RXAUI0 21
-#define PHY_TYPE_RXAUI1 22
-#define PHY_TYPE_SFI 23
-#define PHY_TYPE_IGNORE 24
-#define PHY_TYPE_MAX 25
-#define PHY_TYPE_INVALID 0xff
+#define COMPHY_TYPE_UNCONNECTED 0
+#define COMPHY_TYPE_PEX0 1
+#define COMPHY_TYPE_PEX1 2
+#define COMPHY_TYPE_PEX2 3
+#define COMPHY_TYPE_PEX3 4
+#define COMPHY_TYPE_SATA0 5
+#define COMPHY_TYPE_SATA1 6
+#define COMPHY_TYPE_SGMII0 7
+#define COMPHY_TYPE_SGMII1 8
+#define COMPHY_TYPE_SGMII2 9
+#define COMPHY_TYPE_USB3 10
+#define COMPHY_TYPE_USB3_HOST0 11
+#define COMPHY_TYPE_USB3_HOST1 12
+#define COMPHY_TYPE_USB3_DEVICE 13
+#define COMPHY_TYPE_RXAUI0 14
+#define COMPHY_TYPE_RXAUI1 15
+#define COMPHY_TYPE_SFI0 16
+#define COMPHY_TYPE_SFI1 17
+#define COMPHY_TYPE_AP 18
+#define COMPHY_TYPE_IGNORE 19
+#define COMPHY_TYPE_MAX 20
+#define COMPHY_TYPE_INVALID 0xff
-#define PHY_POLARITY_NO_INVERT 0
-#define PHY_POLARITY_TXD_INVERT 1
-#define PHY_POLARITY_RXD_INVERT 2
-#define PHY_POLARITY_ALL_INVERT \
- (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
+#define COMPHY_POLARITY_NO_INVERT 0
+#define COMPHY_POLARITY_TXD_INVERT 1
+#define COMPHY_POLARITY_RXD_INVERT 2
+#define COMPHY_POLARITY_ALL_INVERT \
+ (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT)
#define UTMI_PHY_TO_USB3_HOST0 0
#define UTMI_PHY_TO_USB3_HOST1 1
diff --git a/include/dt-bindings/pinctrl/k3.h b/include/dt-bindings/pinctrl/k3.h
index ce0cd38..e6cb1d0 100644
--- a/include/dt-bindings/pinctrl/k3.h
+++ b/include/dt-bindings/pinctrl/k3.h
@@ -2,7 +2,7 @@
/*
* This header provides constants for TI K3-AM65 pinctrl bindings.
*
- * Copyright (C) 2018 Texas Instruments
+ * Copyright (C) 2018-2021 Texas Instruments
*/
#ifndef _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
#define _DT_BINDINGS_PINCTRL_TI_K3_AM65_H
@@ -38,4 +38,7 @@
#define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
#define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+#define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
+
#endif
diff --git a/include/dt-bindings/pinctrl/pinctrl-zynqmp.h b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
new file mode 100644
index 0000000..cdb2157
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-zynqmp.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * MIO pin configuration defines for Xilinx ZynqMP
+ *
+ * Copyright (C) 2020 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_ZYNQMP_H
+#define _DT_BINDINGS_PINCTRL_ZYNQMP_H
+
+/* Bit value for different voltage levels */
+#define IO_STANDARD_LVCMOS33 0
+#define IO_STANDARD_LVCMOS18 1
+
+/* Bit values for Slew Rates */
+#define SLEW_RATE_FAST 0
+#define SLEW_RATE_SLOW 1
+
+#endif /* _DT_BINDINGS_PINCTRL_ZYNQMP_H */
diff --git a/include/dt-bindings/reset/sifive-fu740-prci.h b/include/dt-bindings/reset/sifive-fu740-prci.h
new file mode 100644
index 0000000..02210f4
--- /dev/null
+++ b/include/dt-bindings/reset/sifive-fu740-prci.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2020-2021 Sifive, Inc.
+ * Author: Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H
+#define __DT_BINDINGS_RESET_SIFIVE_FU740_PRCI_H
+
+/* Reset indexes for use by device tree data and the PRCI driver */
+#define PRCI_RST_DDR_CTRL_N 0
+#define PRCI_RST_DDR_AXI_N 1
+#define PRCI_RST_DDR_AHB_N 2
+#define PRCI_RST_DDR_PHY_N 3
+#define PRCI_RST_PCIE_POWER_UP_N 4
+#define PRCI_RST_GEMGXL_N 5
+#define PRCI_RST_CLTX_N 6
+
+#endif
diff --git a/include/efi_loader.h b/include/efi_loader.h
index de1a496..0a9c82a 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -217,8 +217,8 @@
/* GUID for the ESRT */
extern const efi_guid_t efi_esrt_guid;
-extern unsigned int __efi_runtime_start, __efi_runtime_stop;
-extern unsigned int __efi_runtime_rel_start, __efi_runtime_rel_stop;
+extern char __efi_runtime_start[], __efi_runtime_stop[];
+extern char __efi_runtime_rel_start[], __efi_runtime_rel_stop[];
/**
* struct efi_open_protocol_info_item - open protocol info item
@@ -426,6 +426,10 @@
efi_status_t efi_rng_register(void);
/* Called by efi_init_obj_list() to install EFI_TCG2_PROTOCOL */
efi_status_t efi_tcg2_register(void);
+/* measure the pe-coff image, extend PCR and add Event Log */
+efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size,
+ struct efi_loaded_image_obj *handle,
+ struct efi_loaded_image *loaded_image_info);
/* Create handles and protocols for the partitions of a block device */
int efi_disk_create_partitions(efi_handle_t parent, struct blk_desc *desc,
const char *if_typename, int diskid,
@@ -678,12 +682,51 @@
(((_dp)->type == DEVICE_PATH_TYPE_##_type) && \
((_dp)->sub_type == DEVICE_PATH_SUB_TYPE_##_subtype))
-/*
- * Use these to indicate that your code / data should go into the EFI runtime
- * section and thus still be available when the OS is running
+/**
+ * __efi_runtime_data - declares a non-const variable for EFI runtime section
+ *
+ * This macro indicates that a variable is non-const and should go into the
+ * EFI runtime section, and thus still be available when the OS is running.
+ *
+ * Only use on variables not declared const.
+ *
+ * Example:
+ *
+ * ::
+ *
+ * static __efi_runtime_data my_computed_table[256];
*/
-#define __efi_runtime_data __attribute__ ((section (".data.efi_runtime")))
-#define __efi_runtime __attribute__ ((section (".text.efi_runtime")))
+#define __efi_runtime_data __section(".data.efi_runtime")
+
+/**
+ * __efi_runtime_rodata - declares a read-only variable for EFI runtime section
+ *
+ * This macro indicates that a variable is read-only (const) and should go into
+ * the EFI runtime section, and thus still be available when the OS is running.
+ *
+ * Only use on variables also declared const.
+ *
+ * Example:
+ *
+ * ::
+ *
+ * static const __efi_runtime_rodata my_const_table[] = { 1, 2, 3 };
+ */
+#define __efi_runtime_rodata __section(".rodata.efi_runtime")
+
+/**
+ * __efi_runtime - declares a function for EFI runtime section
+ *
+ * This macro indicates that a function should go into the EFI runtime section,
+ * and thus still be available when the OS is running.
+ *
+ * Example:
+ *
+ * ::
+ *
+ * static __efi_runtime compute_my_table(void);
+ */
+#define __efi_runtime __section(".text.efi_runtime")
/* Indicate supported runtime services */
efi_status_t efi_init_runtime_supported(void);
@@ -847,6 +890,8 @@
bool efi_capsule_auth_enabled(void);
+void *efi_prepare_aligned_image(void *efi, u64 *efi_size);
+
bool efi_image_parse(void *efi, size_t len, struct efi_image_regions **regp,
WIN_CERTIFICATE **auth, size_t *auth_len);
@@ -888,6 +933,7 @@
/* Without CONFIG_EFI_LOADER we don't have a runtime section, stub it out */
#define __efi_runtime_data
+#define __efi_runtime_rodata
#define __efi_runtime
static inline efi_status_t efi_add_runtime_mmio(void *mmio_ptr, u64 len)
{
diff --git a/include/efi_tcg2.h b/include/efi_tcg2.h
index 40e241c..bcfb981 100644
--- a/include/efi_tcg2.h
+++ b/include/efi_tcg2.h
@@ -9,6 +9,7 @@
#if !defined _EFI_TCG2_PROTOCOL_H_
#define _EFI_TCG2_PROTOCOL_H_
+#include <efi_api.h>
#include <tpm-v2.h>
#define EFI_TCG2_PROTOCOL_GUID \
@@ -53,6 +54,14 @@
u8 event[];
} __packed;
+struct uefi_image_load_event {
+ efi_physical_addr_t image_location_in_memory;
+ u64 image_length_in_memory;
+ u64 image_link_time_address;
+ u64 length_of_device_path;
+ struct efi_device_path device_path[];
+};
+
struct efi_tcg2_boot_service_capability {
u8 size;
struct efi_tcg2_version structure_version;
diff --git a/include/env.h b/include/env.h
index b5731e4..d5e2bcb 100644
--- a/include/env.h
+++ b/include/env.h
@@ -375,4 +375,19 @@
* This is used for those unfortunate archs with crappy toolchains
*/
void env_reloc(void);
+
+
+/**
+ * env_import_fdt() - Import environment values from device tree blob
+ *
+ * This uses the value of the environment variable "env_fdt_path" as a
+ * path to an fdt node, whose property/value pairs are added to the
+ * environment.
+ */
+#ifdef CONFIG_ENV_IMPORT_FDT
+void env_import_fdt(void);
+#else
+static inline void env_import_fdt(void) {}
+#endif
+
#endif
diff --git a/include/env_default.h b/include/env_default.h
index ea31a8e..1ddd64b 100644
--- a/include/env_default.h
+++ b/include/env_default.h
@@ -103,6 +103,9 @@
#ifdef CONFIG_SYS_SOC
"soc=" CONFIG_SYS_SOC "\0"
#endif
+#ifdef CONFIG_ENV_IMPORT_FDT
+ "env_fdt_path=" CONFIG_ENV_FDT_PATH "\0"
+#endif
#endif
#if defined(CONFIG_BOOTCOUNT_BOOTLIMIT) && (CONFIG_BOOTCOUNT_BOOTLIMIT > 0)
"bootlimit=" __stringify(CONFIG_BOOTCOUNT_BOOTLIMIT)"\0"
diff --git a/include/environment/ti/dfu.h b/include/environment/ti/dfu.h
index 720c345..3c90570 100644
--- a/include/environment/ti/dfu.h
+++ b/include/environment/ti/dfu.h
@@ -13,7 +13,7 @@
"boot part 0 1;" \
"rootfs part 0 2;" \
"MLO fat 0 1;" \
- "MLO.raw raw 0x100 0x100;" \
+ "MLO.raw raw 0x100 0x200;" \
"u-boot.img.raw raw 0x300 0x1000;" \
"u-env.raw raw 0x1300 0x200;" \
"spl-os-args.raw raw 0x1500 0x200;" \
@@ -29,7 +29,7 @@
"boot part 1 1;" \
"rootfs part 1 2;" \
"MLO fat 1 1;" \
- "MLO.raw raw 0x100 0x100;" \
+ "MLO.raw raw 0x100 0x200;" \
"u-boot.img.raw raw 0x300 0x1000;" \
"u-env.raw raw 0x1300 0x200;" \
"spl-os-args.raw raw 0x1500 0x200;" \
diff --git a/include/errno.h b/include/errno.h
index 3af539b..652ad67 100644
--- a/include/errno.h
+++ b/include/errno.h
@@ -8,7 +8,13 @@
#include <linux/errno.h>
-extern int errno;
+#ifdef __SANDBOX__
+#define __errno_asm_label asm("__u_boot_errno")
+#else
+#define __errno_asm_label
+#endif
+
+extern int errno __errno_asm_label;
#define __set_errno(val) do { errno = val; } while (0)
diff --git a/include/extension_board.h b/include/extension_board.h
new file mode 100644
index 0000000..c530a0a
--- /dev/null
+++ b/include/extension_board.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021
+ * Köry Maincent, Bootlin, <kory.maincent@bootlin.com>
+ */
+
+#ifndef __EXTENSION_SUPPORT_H
+#define __EXTENSION_SUPPORT_H
+
+struct extension {
+ struct list_head list;
+ char name[32];
+ char owner[32];
+ char version[32];
+ char overlay[32];
+ char other[32];
+};
+
+/**
+ * extension_board_scan - Add system-specific function to scan extension board.
+ * @param extension_list List of extension board information to update.
+ * @return the number of extension.
+ *
+ * This function is called if CONFIG_CMD_EXTENSION is defined.
+ * Needs to fill the list extension_list with elements.
+ * Each element need to be allocated to an extension structure.
+ *
+ */
+int extension_board_scan(struct list_head *extension_list);
+
+#endif /* __EXTENSION_SUPPORT_H */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 46eb1db..1e4dbc0 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -185,6 +185,16 @@
*/
int ft_board_setup(void *blob, struct bd_info *bd);
+/**
+ * board_fdt_chosen_bootargs() - Arbitrarily amend fdt kernel command line
+ *
+ * This is used for late modification of kernel command line arguments just
+ * before they are added into the /chosen node in flat device tree.
+ *
+ * @return: pointer to kernel command line arguments in memory
+ */
+char *board_fdt_chosen_bootargs(void);
+
/*
* The keystone2 SOC requires all 32 bit aliased addresses to be converted
* to their 36 physical format. This has to happen after all fdt nodes
@@ -342,6 +352,8 @@
int fdt_overlay_apply_verbose(void *fdt, void *fdto);
+int fdt_valid(struct fdt_header **blobp);
+
/**
* fdt_get_cells_len() - Get the length of a type of cell in top-level nodes
*
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 62d1660..e0a49b1 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -24,15 +24,16 @@
typedef phys_addr_t fdt_addr_t;
typedef phys_size_t fdt_size_t;
-#ifdef CONFIG_PHYS_64BIT
#define FDT_ADDR_T_NONE (-1U)
+#define FDT_SIZE_T_NONE (-1U)
+
+#ifdef CONFIG_PHYS_64BIT
#define fdt_addr_to_cpu(reg) be64_to_cpu(reg)
#define fdt_size_to_cpu(reg) be64_to_cpu(reg)
#define cpu_to_fdt_addr(reg) cpu_to_be64(reg)
#define cpu_to_fdt_size(reg) cpu_to_be64(reg)
typedef fdt64_t fdt_val_t;
#else
-#define FDT_ADDR_T_NONE (-1U)
#define fdt_addr_to_cpu(reg) be32_to_cpu(reg)
#define fdt_size_to_cpu(reg) be32_to_cpu(reg)
#define cpu_to_fdt_addr(reg) cpu_to_be32(reg)
diff --git a/include/hexdump.h b/include/hexdump.h
index f7b76ff..f2ca479 100644
--- a/include/hexdump.h
+++ b/include/hexdump.h
@@ -10,7 +10,7 @@
#include <linux/ctype.h>
#include <linux/types.h>
-enum {
+enum dump_prefix_t {
DUMP_PREFIX_NONE,
DUMP_PREFIX_ADDRESS,
DUMP_PREFIX_OFFSET
@@ -81,10 +81,85 @@
return dst;
}
+/**
+ * hex_dump_to_buffer - convert a blob of data to "hex ASCII" in memory
+ * @buf: data blob to dump
+ * @len: number of bytes in the @buf
+ * @rowsize: number of bytes to print per line; max 64
+ * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1)
+ * @linebuf: where to put the converted data
+ * @linebuflen: total size of @linebuf, including space for terminating NUL
+ * @ascii: include ASCII after the hex output
+ *
+ * hex_dump_to_buffer() works on one "line" of output at a time, i.e.,
+ * 16 or 32 bytes of input data converted to hex + ASCII output.
+ *
+ * Given a buffer of u8 data, hex_dump_to_buffer() converts the input data
+ * to a hex + ASCII dump at the supplied memory location.
+ * The converted output is always NUL-terminated.
+ *
+ * E.g.:
+ * hex_dump_to_buffer(frame->data, frame->len, 16, 1,
+ * linebuf, sizeof(linebuf), true);
+ *
+ * example output buffer:
+ * 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO
+ *
+ * Return:
+ * The amount of bytes placed in the buffer without terminating NUL. If the
+ * output was truncated, then the return value is the number of bytes
+ * (excluding the terminating NUL) which would have been written to the final
+ * string if enough space had been available.
+ */
int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize,
char *linebuf, size_t linebuflen, bool ascii);
-void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize,
- int groupsize, const void *buf, size_t len, bool ascii);
+
+/**
+ * print_hex_dump - print a text hex dump to syslog for a binary blob of data
+ * @prefix_str: string to prefix each line with;
+ * caller supplies trailing spaces for alignment if desired
+ * @prefix_type: controls whether prefix of an offset, address, or none
+ * is printed (see enum dump_prefix_t)
+ * @rowsize: number of bytes to print per line; max 64
+ * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1)
+ * @buf: data blob to dump
+ * @len: number of bytes in the @buf
+ * @ascii: include ASCII after the hex output
+ * Returns: 0 if finished normally, -EINTR if Ctrl-C was pressed, -ENOSYS if not
+ * supported
+ *
+ * Given a buffer of u8 data, print_hex_dump() prints a hex + ASCII dump
+ * to the stdio, with an optional leading prefix.
+ *
+ * print_hex_dump() works on one "line" of output at a time, i.e.,
+ * 16 or 32 bytes of input data converted to hex + ASCII output.
+ * print_hex_dump() iterates over the entire input @buf, breaking it into
+ * "line size" chunks to format and print.
+ *
+ * E.g.:
+ * print_hex_dump("raw data: ", DUMP_PREFIX_ADDRESS, 16, 1, frame->data,
+ * frame->len, true);
+ *
+ * Example output using %DUMP_PREFIX_OFFSET and 1-byte mode:
+ * 0009ab42: 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO
+ * Example output using %DUMP_PREFIX_ADDRESS and 4-byte mode:
+ * ffffffff88089af0: 73727170 77767574 7b7a7978 7f7e7d7c pqrstuvwxyz{|}~.
+ */
+int print_hex_dump(const char *prefix_str, int prefix_type, int rowsize,
+ int groupsize, const void *buf, size_t len, bool ascii);
+
+/**
+ * print_hex_dump_bytes - shorthand form of print_hex_dump() with default params
+ * @prefix_str: string to prefix each line with;
+ * caller supplies trailing spaces for alignment if desired
+ * @prefix_type: controls whether prefix of an offset, address, or none
+ * is printed (see enum dump_prefix_t)
+ * @buf: data blob to dump
+ * @len: number of bytes in the @buf
+ *
+ * Calls print_hex_dump(), rowsize of 16, groupsize of 1,
+ * and ASCII output included.
+ */
void print_hex_dump_bytes(const char *prefix_str, int prefix_type,
const void *buf, size_t len);
diff --git a/include/image.h b/include/image.h
index 459685d..0c24bf6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -1581,11 +1581,14 @@
* into the FIT creation (i.e. the binary blobs would have been pre-processed
* before being added to the FIT image).
*
+ * @fit: pointer to fit image
+ * @node: offset of image node
* @image: pointer to the image start pointer
* @size: pointer to the image size
* @return no return value (failure should be handled internally)
*/
-void board_fit_image_post_process(void **p_image, size_t *p_size);
+void board_fit_image_post_process(const void *fit, int node, void **p_image,
+ size_t *p_size);
#define FDT_ERROR ((ulong)(-1))
diff --git a/include/k3-clk.h b/include/k3-clk.h
new file mode 100644
index 0000000..0735228
--- /dev/null
+++ b/include/k3-clk.h
@@ -0,0 +1,176 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2020 - Texas Instruments Incorporated - http://www.ti.com
+ * Tero Kristo <t-kristo@ti.com>
+ */
+
+#ifndef __K3_CLK_H__
+#define __K3_CLK_H__
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/clk-provider.h>
+#include <linux/types.h>
+#include <stdint.h>
+
+struct dev_clk {
+ int dev_id;
+ int clk_id;
+ const char *clk_name;
+};
+
+#define DEV_CLK(_dev_id, _clk_id, _clk_name) { .dev_id = _dev_id, \
+ .clk_id = _clk_id, .clk_name = _clk_name, }
+
+#define CLK_TYPE_MUX 0x01
+#define CLK_TYPE_DIV 0x02
+#define CLK_TYPE_PLL 0x03
+#define CLK_TYPE_HFOSC 0x04
+#define CLK_TYPE_POSTDIV 0x05
+#define CLK_TYPE_MUX_PLLCTRL 0x06
+#define CLK_TYPE_FIXED_RATE 0x07
+
+struct pll_data {
+ u32 reg;
+ const char *name;
+ const char *parent;
+ u32 flags;
+};
+
+struct mux_data {
+ u32 reg;
+ const char *name;
+ const char * const *parents;
+ int num_parents;
+ u32 flags;
+ int shift;
+ int width;
+};
+
+struct div_data {
+ u32 reg;
+ const char *name;
+ const char *parent;
+ u32 flags;
+ int shift;
+ int width;
+};
+
+struct hfosc_data {
+ const char *name;
+ u32 flags;
+};
+
+struct fixed_rate_data {
+ const char *name;
+ u64 rate;
+ u32 flags;
+};
+
+struct postdiv_data {
+ const char *name;
+ const char *parent;
+ int width;
+ u32 flags;
+};
+
+struct mux_pllctrl_data {
+ u32 reg;
+ const char *name;
+ const char * const *parents;
+ int num_parents;
+ u32 flags;
+};
+
+struct clk_data {
+ int type;
+ u32 default_freq;
+ union {
+ struct pll_data pll;
+ struct mux_data mux;
+ struct div_data div;
+ struct hfosc_data hfosc;
+ struct postdiv_data postdiv;
+ struct mux_pllctrl_data mux_pllctrl;
+ struct fixed_rate_data fixed_rate;
+ } clk;
+};
+
+#define CLK_MUX(_name, _parents, _num_parents, _reg, _shift, _width, _flags) \
+ { \
+ .type = CLK_TYPE_MUX, \
+ .clk.mux = { .name = _name, .parents = _parents, \
+ .reg = _reg, \
+ .num_parents = _num_parents, .shift = _shift, \
+ .width = _width, .flags = _flags } \
+ }
+
+#define CLK_DIV(_name, _parent, _reg, _shift, _width, _flags) \
+ { \
+ .type = CLK_TYPE_DIV, \
+ .clk.div = {.name = _name, .parent = _parent, .reg = _reg, .shift = _shift, .width = _width, .flags = _flags } \
+ }
+
+#define CLK_DIV_DEFFREQ(_name, _parent, _reg, _shift, _width, _flags, _freq) \
+ { \
+ .type = CLK_TYPE_DIV, \
+ .default_freq = _freq, \
+ .clk.div = { \
+ .name = _name, .parent = _parent, \
+ .reg = _reg, .shift = _shift, \
+ .width = _width, .flags = _flags } \
+ }
+
+#define CLK_PLL(_name, _parent, _reg, _flags) \
+ { \
+ .type = CLK_TYPE_PLL, \
+ .clk.pll = {.name = _name, .parent = _parent, .reg = _reg, .flags = _flags } \
+ }
+
+#define CLK_PLL_DEFFREQ(_name, _parent, _reg, _flags, _freq) \
+ { \
+ .type = CLK_TYPE_PLL, \
+ .default_freq = _freq, \
+ .clk.pll = { .name = _name, .parent = _parent, \
+ .reg = _reg, .flags = _flags } \
+ }
+
+#define CLK_HFOSC(_name, _flags) \
+ { \
+ .type = CLK_TYPE_HFOSC, \
+ .clk.hfosc = { .name = _name, .flags = _flags } \
+ }
+
+#define CLK_FIXED_RATE(_name, _rate, _flags) \
+ { \
+ .type = CLK_TYPE_FIXED_RATE, \
+ .clk.fixed_rate = { .name = _name, .rate = _rate, .flags = _flags } \
+ }
+
+#define CLK_POSTDIV(_name, _parent, _width, _flags) \
+ { \
+ .type = CLK_TYPE_POSTDIV, \
+ .clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \
+ }
+
+#define CLK_MUX_PLLCTRL(_name, _parents, _num_parents, _reg, _flags) \
+ { \
+ .type = CLK_TYPE_MUX, \
+ .clk.mux_pllctrl = { .name = _name, .parents = _parents,\
+ .num_parents = _num_parents, .flags = _flags } \
+ }
+
+struct ti_k3_clk_platdata {
+ const struct clk_data *clk_list;
+ int clk_list_cnt;
+ const struct dev_clk *soc_dev_clk_data;
+ int soc_dev_clk_data_cnt;
+};
+
+extern const struct ti_k3_clk_platdata j721e_clk_platdata;
+extern const struct ti_k3_clk_platdata j7200_clk_platdata;
+
+struct clk *clk_register_ti_pll(const char *name, const char *parent_name,
+ void __iomem *reg);
+
+#endif /* __K3_CLK_H__ */
diff --git a/include/k3-dev.h b/include/k3-dev.h
new file mode 100644
index 0000000..55c5057
--- /dev/null
+++ b/include/k3-dev.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments K3 Device Platform Data
+ *
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ */
+#ifndef __K3_DEV_H__
+#define __K3_DEV_H__
+
+#include <asm/io.h>
+#include <linux/types.h>
+#include <stdint.h>
+
+#define LPSC_MODULE_EXISTS BIT(0)
+#define LPSC_NO_CLOCK_GATING BIT(1)
+#define LPSC_DEPENDS BIT(2)
+#define LPSC_HAS_RESET_ISO BIT(3)
+#define LPSC_HAS_LOCAL_RESET BIT(4)
+#define LPSC_NO_MODULE_RESET BIT(5)
+
+#define PSC_PD_EXISTS BIT(0)
+#define PSC_PD_ALWAYSON BIT(1)
+#define PSC_PD_DEPENDS BIT(2)
+
+#define MDSTAT_STATE_MASK 0x3f
+#define MDSTAT_BUSY_MASK 0x30
+#define MDSTAT_STATE_SWRSTDISABLE 0x0
+#define MDSTAT_STATE_ENABLE 0x3
+
+struct ti_psc {
+ int id;
+ void __iomem *base;
+};
+
+struct ti_pd;
+
+struct ti_pd {
+ int id;
+ int usecount;
+ struct ti_psc *psc;
+ struct ti_pd *depend;
+};
+
+struct ti_lpsc;
+
+struct ti_lpsc {
+ int id;
+ int usecount;
+ struct ti_psc *psc;
+ struct ti_pd *pd;
+ struct ti_lpsc *depend;
+};
+
+struct ti_dev {
+ struct ti_lpsc *lpsc;
+ int id;
+};
+
+/**
+ * struct ti_k3_pd_platdata - pm domain controller information structure
+ */
+struct ti_k3_pd_platdata {
+ struct ti_psc *psc;
+ struct ti_pd *pd;
+ struct ti_lpsc *lpsc;
+ struct ti_dev *devs;
+ int num_psc;
+ int num_pd;
+ int num_lpsc;
+ int num_devs;
+};
+
+#define PSC(_id, _base) { .id = _id, .base = (void *)_base, }
+#define PSC_PD(_id, _psc, _depend) { .id = _id, .psc = _psc, .depend = _depend }
+#define PSC_LPSC(_id, _psc, _pd, _depend) { .id = _id, .psc = _psc, .pd = _pd, .depend = _depend }
+#define PSC_DEV(_id, _lpsc) { .id = _id, .lpsc = _lpsc }
+
+extern const struct ti_k3_pd_platdata j721e_pd_platdata;
+extern const struct ti_k3_pd_platdata j7200_pd_platdata;
+
+u8 ti_pd_state(struct ti_pd *pd);
+u8 lpsc_get_state(struct ti_lpsc *lpsc);
+int ti_lpsc_transition(struct ti_lpsc *lpsc, u8 state);
+
+#endif
diff --git a/include/kendryte/bypass.h b/include/kendryte/bypass.h
deleted file mode 100644
index ab85bbc..0000000
--- a/include/kendryte/bypass.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
- */
-#ifndef K210_BYPASS_H
-#define K210_BYPASS_H
-
-struct clk;
-
-struct k210_bypass {
- struct clk clk;
- struct clk **children; /* Clocks to reparent */
- struct clk **saved_parents; /* Parents saved over en-/dis-able */
- struct clk *bypassee; /* Clock to bypass */
- const struct clk_ops *bypassee_ops; /* Ops of the bypass clock */
- struct clk *alt; /* Clock to set children to when bypassing */
- size_t child_count;
-};
-
-#define to_k210_bypass(_clk) container_of(_clk, struct k210_bypass, clk)
-
-int k210_bypass_set_children(struct clk *clk, struct clk **children,
- size_t child_count);
-struct clk *k210_register_bypass_struct(const char *name,
- const char *parent_name,
- struct k210_bypass *bypass);
-struct clk *k210_register_bypass(const char *name, const char *parent_name,
- struct clk *bypassee,
- const struct clk_ops *bypassee_ops,
- struct clk *alt);
-#endif /* K210_BYPASS_H */
diff --git a/include/kendryte/clk.h b/include/kendryte/clk.h
deleted file mode 100644
index 9c6245d..0000000
--- a/include/kendryte/clk.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
- */
-
-#ifndef K210_CLK_H
-#define K210_CLK_H
-
-#define LOG_CATEGORY UCLASS_CLK
-#include <linux/types.h>
-#include <linux/clk-provider.h>
-
-static inline struct clk *k210_clk_gate(const char *name,
- const char *parent_name,
- void __iomem *reg, u8 bit_idx)
-{
- return clk_register_gate(NULL, name, parent_name, 0, reg, bit_idx, 0,
- NULL);
-}
-
-static inline struct clk *k210_clk_half(const char *name,
- const char *parent_name)
-{
- return clk_register_fixed_factor(NULL, name, parent_name, 0, 1, 2);
-}
-
-static inline struct clk *k210_clk_div(const char *name,
- const char *parent_name,
- void __iomem *reg, u8 shift, u8 width)
-{
- return clk_register_divider(NULL, name, parent_name, 0, reg, shift,
- width, 0);
-}
-
-#endif /* K210_CLK_H */
diff --git a/include/kendryte/pll.h b/include/kendryte/pll.h
index 55a40b9..fd16a89 100644
--- a/include/kendryte/pll.h
+++ b/include/kendryte/pll.h
@@ -5,35 +5,7 @@
#ifndef K210_PLL_H
#define K210_PLL_H
-#include <clk.h>
#include <test/export.h>
-#include <asm/io.h>
-
-#define K210_PLL_CLKR GENMASK(3, 0)
-#define K210_PLL_CLKF GENMASK(9, 4)
-#define K210_PLL_CLKOD GENMASK(13, 10) /* Output Divider */
-#define K210_PLL_BWADJ GENMASK(19, 14) /* BandWidth Adjust */
-#define K210_PLL_RESET BIT(20)
-#define K210_PLL_PWRD BIT(21) /* PoWeReD */
-#define K210_PLL_INTFB BIT(22) /* Internal FeedBack */
-#define K210_PLL_BYPASS BIT(23)
-#define K210_PLL_TEST BIT(24)
-#define K210_PLL_EN BIT(25)
-#define K210_PLL_TEST_EN BIT(26)
-
-#define K210_PLL_LOCK 0
-#define K210_PLL_CLEAR_SLIP 2
-#define K210_PLL_TEST_OUT 3
-
-struct k210_pll {
- struct clk clk;
- void __iomem *reg; /* Base PLL register */
- void __iomem *lock; /* Common PLL lock register */
- u8 shift; /* Offset of bits in lock register */
- u8 width; /* Width of lock bits to test against */
-};
-
-#define to_k210_pll(_clk) container_of(_clk, struct k210_pll, clk)
struct k210_pll_config {
u8 r;
@@ -44,19 +16,9 @@
#ifdef CONFIG_UNIT_TEST
TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in,
struct k210_pll_config *best);
-
#ifndef nop
#define nop()
#endif
#endif
-
-extern const struct clk_ops k210_pll_ops;
-
-struct clk *k210_register_pll_struct(const char *name, const char *parent_name,
- struct k210_pll *pll);
-struct clk *k210_register_pll(const char *name, const char *parent_name,
- void __iomem *reg, void __iomem *lock, u8 shift,
- u8 width);
-
#endif /* K210_PLL_H */
diff --git a/include/linker_lists.h b/include/linker_lists.h
index 2fea54c..0575164 100644
--- a/include/linker_lists.h
+++ b/include/linker_lists.h
@@ -69,8 +69,8 @@
*/
#define ll_entry_declare(_type, _name, _list) \
_type _u_boot_list_2_##_list##_2_##_name __aligned(4) \
- __attribute__((unused, \
- section(".u_boot_list_2_"#_list"_2_"#_name)))
+ __attribute__((unused)) \
+ __section(".u_boot_list_2_"#_list"_2_"#_name)
/**
* ll_entry_declare_list() - Declare a list of link-generated array entries
@@ -92,8 +92,8 @@
*/
#define ll_entry_declare_list(_type, _name, _list) \
_type _u_boot_list_2_##_list##_2_##_name[] __aligned(4) \
- __attribute__((unused, \
- section(".u_boot_list_2_"#_list"_2_"#_name)))
+ __attribute__((unused)) \
+ __section(".u_boot_list_2_"#_list"_2_"#_name)
/*
* We need a 0-byte-size type for iterator symbols, and the compiler
@@ -125,8 +125,8 @@
#define ll_entry_start(_type, _list) \
({ \
static char start[0] __aligned(CONFIG_LINKER_LIST_ALIGN) \
- __attribute__((unused, \
- section(".u_boot_list_2_"#_list"_1"))); \
+ __attribute__((unused)) \
+ __section(".u_boot_list_2_"#_list"_1"); \
(_type *)&start; \
})
@@ -151,8 +151,8 @@
*/
#define ll_entry_end(_type, _list) \
({ \
- static char end[0] __aligned(4) __attribute__((unused, \
- section(".u_boot_list_2_"#_list"_3"))); \
+ static char end[0] __aligned(4) __attribute__((unused)) \
+ __section(".u_boot_list_2_"#_list"_3"); \
(_type *)&end; \
})
/**
@@ -245,8 +245,8 @@
*/
#define ll_start(_type) \
({ \
- static char start[0] __aligned(4) __attribute__((unused, \
- section(".u_boot_list_1"))); \
+ static char start[0] __aligned(4) __attribute__((unused)) \
+ __section(".u_boot_list_1"); \
(_type *)&start; \
})
@@ -268,8 +268,8 @@
*/
#define ll_end(_type) \
({ \
- static char end[0] __aligned(4) __attribute__((unused, \
- section(".u_boot_list_3"))); \
+ static char end[0] __aligned(4) __attribute__((unused)) \
+ __section(".u_boot_list_3"); \
(_type *)&end; \
})
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 6fda14f..9d296f2 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -247,6 +247,9 @@
void __iomem *reg, u8 shift, u8 width,
u8 clk_mux_flags);
+struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
+ ulong rate);
+
const char *clk_hw_get_name(const struct clk *hw);
ulong clk_generic_get_rate(struct clk *clk);
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 5e3b3c0..98dd3fc 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -24,7 +24,7 @@
long ______r; \
static struct ftrace_likely_data \
__aligned(4) \
- __section(_ftrace_annotated_branch) \
+ __section("_ftrace_annotated_branch") \
______f = { \
.data.func = __func__, \
.data.file = __FILE__, \
@@ -60,7 +60,7 @@
#define __trace_if_value(cond) ({ \
static struct ftrace_branch_data \
__aligned(4) \
- __section(_ftrace_branch) \
+ __section("_ftrace_branch") \
__if_trace = { \
.func = __func__, \
.file = __FILE__, \
@@ -118,7 +118,7 @@
".popsection\n\t"
/* Annotate a C jump table to allow objtool to follow the code flow */
-#define __annotate_jump_table __section(.rodata..c_jump_table)
+#define __annotate_jump_table __section(".rodata..c_jump_table")
#else
#define annotate_reachable()
@@ -294,8 +294,8 @@
* visible to the compiler.
*/
#define __ADDRESSABLE(sym) \
- static void * __section(.discard.addressable) __used \
- __PASTE(__addressable_##sym, __LINE__) = (void *)&sym;
+ static void * __section(".discard.addressable") __used \
+ __UNIQUE_ID(__PASTE(__addressable_,sym)) = (void *)&sym;
/**
* offset_to_ptr - convert a relative memory offset to an absolute pointer
diff --git a/include/linux/compiler_attributes.h b/include/linux/compiler_attributes.h
index cdf0165..44c9a08 100644
--- a/include/linux/compiler_attributes.h
+++ b/include/linux/compiler_attributes.h
@@ -246,7 +246,7 @@
* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#index-section-variable-attribute
* clang: https://clang.llvm.org/docs/AttributeReference.html#section-declspec-allocate
*/
-#define __section(S) __attribute__((__section__(#S)))
+#define __section(S) __attribute__((__section__(S)))
/*
* gcc: https://gcc.gnu.org/onlinedocs/gcc/Common-Function-Attributes.html#index-unused-function-attribute
diff --git a/include/linux/rational.h b/include/linux/rational.h
new file mode 100644
index 0000000..33f5f5f
--- /dev/null
+++ b/include/linux/rational.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer <oskar@scara.com>
+ *
+ * helper functions when coping with rational numbers,
+ * e.g. when calculating optimum numerator/denominator pairs for
+ * pll configuration taking into account restricted register size
+ */
+
+#ifndef _LINUX_RATIONAL_H
+#define _LINUX_RATIONAL_H
+
+void rational_best_approximation(
+ unsigned long given_numerator, unsigned long given_denominator,
+ unsigned long max_numerator, unsigned long max_denominator,
+ unsigned long *best_numerator, unsigned long *best_denominator);
+
+#endif /* _LINUX_RATIONAL_H */
diff --git a/include/linux/soc/ti/k3-navss-ringacc.h b/include/linux/soc/ti/k3-navss-ringacc.h
index 9176277..0ad8f20 100644
--- a/include/linux/soc/ti/k3-navss-ringacc.h
+++ b/include/linux/soc/ti/k3-navss-ringacc.h
@@ -83,22 +83,17 @@
};
#define K3_NAV_RINGACC_RING_ID_ANY (-1)
-#define K3_NAV_RINGACC_RING_USE_PROXY BIT(1)
/**
* k3_nav_ringacc_request_ring - request ring from ringacc
* @ringacc: pointer on ringacc
* @id: ring id or K3_NAV_RINGACC_RING_ID_ANY for any general purpose ring
- * @flags:
- * @K3_NAV_RINGACC_RING_USE_PROXY: if set - proxy will be allocated and
- * used to access ring memory. Sopported only for rings in
- * Message/Credentials/Queue mode.
*
* Returns pointer on the Ring - struct k3_nav_ring
* or NULL in case of failure.
*/
struct k3_nav_ring *k3_nav_ringacc_request_ring(struct k3_nav_ringacc *ringacc,
- int id, u32 flags);
+ int id);
int k3_nav_ringacc_request_rings_pair(struct k3_nav_ringacc *ringacc,
int fwd_id, int compl_id,
@@ -238,4 +233,19 @@
*/
int k3_nav_ringacc_ring_pop_tail(struct k3_nav_ring *ring, void *elem);
+/* DMA ring support */
+struct ti_sci_handle;
+
+/**
+ * struct struct k3_ringacc_init_data - Initialization data for DMA rings
+ */
+struct k3_ringacc_init_data {
+ const struct ti_sci_handle *tisci;
+ u32 tisci_dev_id;
+ u32 num_rings;
+};
+
+struct k3_nav_ringacc *k3_ringacc_dmarings_init(struct udevice *dev,
+ struct k3_ringacc_init_data *data);
+
#endif /* __SOC_TI_K3_NAVSS_RINGACC_API_H_ */
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index eb916ba..7947379 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -379,6 +379,13 @@
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
#define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
+#define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
+
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_TCHAN 0
+#define TI_SCI_RM_BCDMA_EXTENDED_CH_TYPE_BCHAN 1
+
/* UDMAP TX/RX channel valid_params common declarations */
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
@@ -389,6 +396,7 @@
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
/**
* Configures a Navigator Subsystem UDMAP transmit channel
@@ -403,6 +411,8 @@
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_TDTYPE_VALID BIT(15)
+#define TI_SCI_MSG_VALUE_RM_UDMAP_CH_EXTENDED_CH_TYPE_VALID BIT(16)
u16 nav_id;
u16 index;
u8 tx_pause_on_err;
@@ -419,6 +429,9 @@
u8 tx_orderid;
u16 fdepth;
u8 tx_sched_priority;
+ u8 tx_burst_size;
+ u8 tx_tdtype;
+ u8 extended_ch_type;
};
/**
@@ -448,6 +461,7 @@
u8 rx_chan_type;
u8 rx_ignore_short;
u8 rx_ignore_long;
+ u8 rx_burst_size;
};
/**
diff --git a/include/lmb.h b/include/lmb.h
index 541e170..3c4afdf 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -13,6 +13,16 @@
*/
/**
+ * enum lmb_flags - definition of memory region attributes
+ * @LMB_NONE: no special request
+ * @LMB_NOMAP: don't add to mmu configuration
+ */
+enum lmb_flags {
+ LMB_NONE = 0x0,
+ LMB_NOMAP = 0x4,
+};
+
+/**
* struct lmb_property - Description of one region.
*
* @base: Base address of the region.
@@ -21,6 +31,7 @@
struct lmb_property {
phys_addr_t base;
phys_size_t size;
+ enum lmb_flags flags;
};
/**
@@ -69,6 +80,17 @@
phys_size_t size, void *fdt_blob);
extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
+/**
+ * lmb_reserve_flags - Reserve one region with a specific flags bitfield.
+ *
+ * @lmb the logical memory block struct
+ * @base base address of the memory region
+ * @size size of the memory region
+ * @flags flags for the memory region
+ * @return 0 if OK, > 0 for coalesced region or a negative error code.
+ */
+long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base,
+ phys_size_t size, enum lmb_flags flags);
extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
extern phys_addr_t lmb_alloc_base(struct lmb *lmb, phys_size_t size, ulong align,
phys_addr_t max_addr);
@@ -78,6 +100,15 @@
phys_size_t size);
extern phys_size_t lmb_get_free_size(struct lmb *lmb, phys_addr_t addr);
extern int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr);
+/**
+ * lmb_is_reserved_flags - test if tha address is in reserved region with a bitfield flag
+ *
+ * @lmb the logical memory block struct
+ * @addr address to be tested
+ * @flags flags bitfied to be tested
+ * @return 0 if not reserved or reserved without the requested flag else 1
+ */
+int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags);
extern long lmb_free(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern void lmb_dump_all(struct lmb *lmb);
@@ -92,6 +123,13 @@
void board_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve(struct lmb *lmb);
+/* Low level functions */
+
+static inline bool lmb_is_nomap(struct lmb_property *m)
+{
+ return m->flags & LMB_NOMAP;
+}
+
#endif /* __KERNEL__ */
#endif /* _LINUX_LMB_H */
diff --git a/include/log.h b/include/log.h
index add3a1e..e0e12ce 100644
--- a/include/log.h
+++ b/include/log.h
@@ -140,6 +140,24 @@
return 0;
}
+/**
+ * _log_buffer - Internal function to print data buffer in hex and ascii form
+ *
+ * @cat: Category of log record (indicating which subsystem generated it)
+ * @level: Level of log record (indicating its severity)
+ * @file: File name of file where log record was generated
+ * @line: Line number in file where log record was generated
+ * @func: Function where log record was generated
+ * @addr: Starting address to display at start of line
+ * @data: pointer to data buffer
+ * @width: data value width. May be 1, 2, or 4.
+ * @count: number of values to display
+ * @linelen: Number of values to print per line; specify 0 for default length
+ */
+int _log_buffer(enum log_category_t cat, enum log_level_t level,
+ const char *file, int line, const char *func, ulong addr,
+ const void *data, uint width, uint count, uint linelen);
+
/* Define this at the top of a file to add a prefix to debug messages */
#ifndef pr_fmt
#define pr_fmt(fmt) fmt
@@ -156,6 +174,10 @@
*/
#if CONFIG_IS_ENABLED(LOG)
#define _LOG_MAX_LEVEL CONFIG_VAL(LOG_MAX_LEVEL)
+#else
+#define _LOG_MAX_LEVEL LOGL_INFO
+#endif
+
#define log_emer(_fmt...) log(LOG_CATEGORY, LOGL_EMERG, ##_fmt)
#define log_alert(_fmt...) log(LOG_CATEGORY, LOGL_ALERT, ##_fmt)
#define log_crit(_fmt...) log(LOG_CATEGORY, LOGL_CRIT, ##_fmt)
@@ -167,41 +189,50 @@
#define log_content(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG_CONTENT, ##_fmt)
#define log_io(_fmt...) log(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt)
#define log_cont(_fmt...) log(LOGC_CONT, LOGL_CONT, ##_fmt)
-#else
-#define _LOG_MAX_LEVEL LOGL_INFO
-#define log_emerg(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
-#define log_alert(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
-#define log_crit(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
-#define log_err(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
-#define log_warning(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
-#define log_notice(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
-#define log_info(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
-#define log_cont(_fmt, ...) printf(_fmt, ##__VA_ARGS__)
-#define log_debug(_fmt, ...) debug(_fmt, ##__VA_ARGS__)
-#define log_content(_fmt...) log_nop(LOG_CATEGORY, \
- LOGL_DEBUG_CONTENT, ##_fmt)
-#define log_io(_fmt...) log_nop(LOG_CATEGORY, LOGL_DEBUG_IO, ##_fmt)
-#endif
-#if CONFIG_IS_ENABLED(LOG)
#ifdef LOG_DEBUG
#define _LOG_DEBUG LOGL_FORCE_DEBUG
#else
#define _LOG_DEBUG 0
#endif
+#if CONFIG_IS_ENABLED(LOG)
+
/* Emit a log record if the level is less that the maximum */
#define log(_cat, _level, _fmt, _args...) ({ \
int _l = _level; \
- if (CONFIG_IS_ENABLED(LOG) && \
- (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL)) \
+ if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \
_log((enum log_category_t)(_cat), \
(enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \
__LINE__, __func__, \
pr_fmt(_fmt), ##_args); \
})
+
+/* Emit a dump if the level is less that the maximum */
+#define log_buffer(_cat, _level, _addr, _data, _width, _count, _linelen) ({ \
+ int _l = _level; \
+ if (_LOG_DEBUG != 0 || _l <= _LOG_MAX_LEVEL) \
+ _log_buffer((enum log_category_t)(_cat), \
+ (enum log_level_t)(_l | _LOG_DEBUG), __FILE__, \
+ __LINE__, __func__, _addr, _data, \
+ _width, _count, _linelen); \
+ })
#else
-#define log(_cat, _level, _fmt, _args...)
+
+/* Note: _LOG_DEBUG != 0 avoids a warning with clang */
+#define log(_cat, _level, _fmt, _args...) ({ \
+ int _l = _level; \
+ if (_LOG_DEBUG != 0 || _l <= LOGL_INFO || \
+ (_DEBUG && _l == LOGL_DEBUG)) \
+ printf(_fmt, ##_args); \
+ })
+
+#define log_buffer(_cat, _level, _addr, _data, _width, _count, _linelen) ({ \
+ int _l = _level; \
+ if (_LOG_DEBUG != 0 || _l <= LOGL_INFO || \
+ (_DEBUG && _l == LOGL_DEBUG)) \
+ print_buffer(_addr, _data, _width, _count, _linelen); \
+ })
#endif
#define log_nop(_cat, _level, _fmt, _args...) ({ \
diff --git a/include/mvebu/comphy.h b/include/mvebu/comphy.h
index cde7a02..4d1b703 100644
--- a/include/mvebu/comphy.h
+++ b/include/mvebu/comphy.h
@@ -16,7 +16,7 @@
bool end_point;
};
+int comphy_rx_training(struct udevice *dev, u32 lane);
int comphy_update_map(struct comphy_map *serdes_map, int count);
#endif /* _MVEBU_COMPHY_H_ */
-
diff --git a/include/pci.h b/include/pci.h
index 5f36537..2353ceb 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -1690,6 +1690,14 @@
*/
int sandbox_pci_get_client(struct udevice *emul, struct udevice **devp);
+/**
+ * board_pci_fixup_dev() - Board callback for PCI device fixups
+ *
+ * @bus: PCI bus
+ * @dev: PCI device
+ */
+extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev);
+
#endif /* CONFIG_DM_PCI */
/**
diff --git a/include/phy_interface.h b/include/phy_interface.h
index 841ade3..ebb18ec 100644
--- a/include/phy_interface.h
+++ b/include/phy_interface.h
@@ -25,6 +25,8 @@
PHY_INTERFACE_MODE_RGMII_RXID,
PHY_INTERFACE_MODE_RGMII_TXID,
PHY_INTERFACE_MODE_RTBI,
+ PHY_INTERFACE_MODE_1000BASEX,
+ PHY_INTERFACE_MODE_2500BASEX,
PHY_INTERFACE_MODE_XGMII,
PHY_INTERFACE_MODE_XAUI,
PHY_INTERFACE_MODE_RXAUI,
@@ -55,6 +57,8 @@
[PHY_INTERFACE_MODE_RGMII_RXID] = "rgmii-rxid",
[PHY_INTERFACE_MODE_RGMII_TXID] = "rgmii-txid",
[PHY_INTERFACE_MODE_RTBI] = "rtbi",
+ [PHY_INTERFACE_MODE_1000BASEX] = "1000base-x",
+ [PHY_INTERFACE_MODE_2500BASEX] = "2500base-x",
[PHY_INTERFACE_MODE_XGMII] = "xgmii",
[PHY_INTERFACE_MODE_XAUI] = "xaui",
[PHY_INTERFACE_MODE_RXAUI] = "rxaui",
diff --git a/include/power/regulator.h b/include/power/regulator.h
index da9a065..fad87c9 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -151,6 +151,7 @@
* @max_uA* - maximum amperage (micro Amps)
* @always_on* - bool type, true or false
* @boot_on* - bool type, true or false
+ * @force_off* - bool type, true or false
* TODO(sjg@chromium.org): Consider putting the above two into @flags
* @ramp_delay - Time to settle down after voltage change (unit: uV/us)
* @flags: - flags value (see REGULATOR_FLAG_...)
@@ -176,6 +177,7 @@
unsigned int ramp_delay;
bool always_on;
bool boot_on;
+ bool force_off;
const char *name;
int flags;
u8 ctrl_reg;
@@ -421,6 +423,15 @@
int regulators_enable_boot_on(bool verbose);
/**
+ * regulators_enable_boot_off() - disable regulators needed for boot
+ *
+ * This disables all regulators which are marked to be off at boot time.
+ *
+ * This effectively calls regulator_unset() for every regulator.
+ */
+int regulators_enable_boot_off(bool verbose);
+
+/**
* regulator_autoset: setup the voltage/current on a regulator
*
* The setup depends on constraints found in device's uclass's platform data
@@ -440,6 +451,18 @@
int regulator_autoset(struct udevice *dev);
/**
+ * regulator_unset: turn off a regulator
+ *
+ * The setup depends on constraints found in device's uclass's platform data
+ * (struct dm_regulator_uclass_platdata):
+ *
+ * - Disable - will set - if 'force_off' is set to true,
+ *
+ * The function returns on the first-encountered error.
+ */
+int regulator_unset(struct udevice *dev);
+
+/**
* regulator_autoset_by_name: setup the regulator given by its uclass's
* platform data name field. The setup depends on constraints found in device's
* uclass's platform data (struct dm_regulator_uclass_plat):
diff --git a/include/sysinfo.h b/include/sysinfo.h
index 8054d4d..b140d74 100644
--- a/include/sysinfo.h
+++ b/include/sysinfo.h
@@ -60,7 +60,8 @@
* This operation might take a long time (e.g. read from EEPROM,
* check the presence of a device on a bus etc.), hence this is not
* done in the probe() method, but later during operation in this
- * dedicated method.
+ * dedicated method. This method will be called before any other
+ * methods.
*
* Return: 0 if OK, -ve on error.
*/
@@ -104,7 +105,7 @@
* get_fit_loadable - Get the name of an image to load from FIT
* This function can be used to provide the image names based on runtime
* detection. A classic use-case would when DTBOs are used to describe
- * additionnal daughter cards.
+ * additional daughter cards.
*
* @dev: The sysinfo instance to gather the data.
* @index: Index of the image. Starts at 0 and gets incremented
@@ -127,6 +128,9 @@
*
* @dev: The device containing the information
*
+ * This function must be called before any other accessor function for this
+ * device.
+ *
* Return: 0 if OK, -ve on error.
*/
int sysinfo_detect(struct udevice *dev);
@@ -138,7 +142,8 @@
* @id: A unique identifier for the bool value to be read.
* @val: Pointer to a buffer that receives the value read.
*
- * Return: 0 if OK, -ve on error.
+ * Return: 0 if OK, -EPERM if called before sysinfo_detect(), else -ve on
+ * error.
*/
int sysinfo_get_bool(struct udevice *dev, int id, bool *val);
@@ -149,7 +154,8 @@
* @id: A unique identifier for the int value to be read.
* @val: Pointer to a buffer that receives the value read.
*
- * Return: 0 if OK, -ve on error.
+ * Return: 0 if OK, -EPERM if called before sysinfo_detect(), else -ve on
+ * error.
*/
int sysinfo_get_int(struct udevice *dev, int id, int *val);
@@ -161,7 +167,8 @@
* @size: The size of the buffer to receive the string data.
* @val: Pointer to a buffer that receives the value read.
*
- * Return: 0 if OK, -ve on error.
+ * Return: 0 if OK, -EPERM if called before sysinfo_detect(), else -ve on
+ * error.
*/
int sysinfo_get_str(struct udevice *dev, int id, size_t size, char *val);
@@ -173,7 +180,8 @@
* function that returns the unique device. This is especially useful for use
* in sysinfo files.
*
- * Return: 0 if OK, -ve on error.
+ * Return: 0 if OK, -EPERM if called before sysinfo_detect(), else -ve on
+ * error.
*/
int sysinfo_get(struct udevice **devp);
@@ -181,7 +189,7 @@
* sysinfo_get_fit_loadable - Get the name of an image to load from FIT
* This function can be used to provide the image names based on runtime
* detection. A classic use-case would when DTBOs are used to describe
- * additionnal daughter cards.
+ * additional daughter cards.
*
* @dev: The sysinfo instance to gather the data.
* @index: Index of the image. Starts at 0 and gets incremented
@@ -190,8 +198,8 @@
* @strp: A pointer to string. Untouched if the function fails
*
*
- * Return: 0 if OK, -ENOENT if no loadable is available else -ve on
- * error.
+ * Return: 0 if OK, -EPERM if called before sysinfo_detect(), -ENOENT if no
+ * loadable is available else -ve on error.
*/
int sysinfo_get_fit_loadable(struct udevice *dev, int index, const char *type,
const char **strp);
diff --git a/include/test/suites.h b/include/test/suites.h
index f5d8e13..80b41f1 100644
--- a/include/test/suites.h
+++ b/include/test/suites.h
@@ -41,6 +41,7 @@
int do_ut_optee(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_overlay(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
+int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
int do_ut_setexpr(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[]);
int do_ut_str(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]);
diff --git a/include/test/test.h b/include/test/test.h
index bf7d785..0104e18 100644
--- a/include/test/test.h
+++ b/include/test/test.h
@@ -32,8 +32,8 @@
struct udevice *testdev;
int force_fail_alloc;
int skip_post_probe;
- char expect_str[256];
- char actual_str[256];
+ char expect_str[512];
+ char actual_str[512];
};
/* Test flags for each test */
diff --git a/include/test/ut.h b/include/test/ut.h
index fbbba28..656e25f 100644
--- a/include/test/ut.h
+++ b/include/test/ut.h
@@ -177,23 +177,6 @@
} \
}
-/*
- * Assert that two string expressions are equal, up to length of the
- * first
- */
-#define ut_asserteq_strn(expr1, expr2) { \
- const char *_val1 = (expr1), *_val2 = (expr2); \
- int _len = strlen(_val1); \
- \
- if (memcmp(_val1, _val2, _len)) { \
- ut_failf(uts, __FILE__, __LINE__, __func__, \
- #expr1 " = " #expr2, \
- "Expected \"%.*s\", got \"%.*s\"", \
- _len, _val1, _len, _val2); \
- return CMD_RET_FAILURE; \
- } \
-}
-
/* Assert that two memory areas are equal */
#define ut_asserteq_mem(expr1, expr2, len) { \
const u8 *_val1 = (u8 *)(expr1), *_val2 = (u8 *)(expr2); \
diff --git a/include/tpm-v2.h b/include/tpm-v2.h
index df67a19..247b386 100644
--- a/include/tpm-v2.h
+++ b/include/tpm-v2.h
@@ -53,14 +53,40 @@
#define TPM2_PT_MAX_COMMAND_SIZE (u32)(TPM2_PT_FIXED + 30)
#define TPM2_PT_MAX_RESPONSE_SIZE (u32)(TPM2_PT_FIXED + 31)
-/* event types */
-#define EV_POST_CODE ((u32)0x00000001)
-#define EV_NO_ACTION ((u32)0x00000003)
-#define EV_SEPARATOR ((u32)0x00000004)
-#define EV_S_CRTM_CONTENTS ((u32)0x00000007)
-#define EV_S_CRTM_VERSION ((u32)0x00000008)
-#define EV_CPU_MICROCODE ((u32)0x00000009)
-#define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
+/*
+ * event types, cf.
+ * "TCG Server Management Domain Firmware Profile Specification",
+ * rev 1.00, 2020-05-01
+ */
+#define EV_POST_CODE ((u32)0x00000001)
+#define EV_NO_ACTION ((u32)0x00000003)
+#define EV_SEPARATOR ((u32)0x00000004)
+#define EV_ACTION ((u32)0x00000005)
+#define EV_TAG ((u32)0x00000006)
+#define EV_S_CRTM_CONTENTS ((u32)0x00000007)
+#define EV_S_CRTM_VERSION ((u32)0x00000008)
+#define EV_CPU_MICROCODE ((u32)0x00000009)
+#define EV_PLATFORM_CONFIG_FLAGS ((u32)0x0000000A)
+#define EV_TABLE_OF_DEVICES ((u32)0x0000000B)
+#define EV_COMPACT_HASH ((u32)0x0000000C)
+
+/*
+ * event types, cf.
+ * "TCG PC Client Platform Firmware Profile Specification", Family "2.0"
+ * rev 1.04, June 3, 2019
+ */
+#define EV_EFI_EVENT_BASE ((u32)0x80000000)
+#define EV_EFI_VARIABLE_DRIVER_CONFIG ((u32)0x80000001)
+#define EV_EFI_VARIABLE_BOOT ((u32)0x80000002)
+#define EV_EFI_BOOT_SERVICES_APPLICATION ((u32)0x80000003)
+#define EV_EFI_BOOT_SERVICES_DRIVER ((u32)0x80000004)
+#define EV_EFI_RUNTIME_SERVICES_DRIVER ((u32)0x80000005)
+#define EV_EFI_GPT_EVENT ((u32)0x80000006)
+#define EV_EFI_ACTION ((u32)0x80000007)
+#define EV_EFI_PLATFORM_FIRMWARE_BLOB ((u32)0x80000008)
+#define EV_EFI_HANDOFF_TABLES ((u32)0x80000009)
+#define EV_EFI_HCRTM_EVENT ((u32)0x80000010)
+#define EV_EFI_VARIABLE_AUTHORITY ((u32)0x800000E0)
/* TPMS_TAGGED_PROPERTY Structure */
struct tpms_tagged_property {
diff --git a/include/w1-eeprom.h b/include/w1-eeprom.h
index 2233736..b3cf77a 100644
--- a/include/w1-eeprom.h
+++ b/include/w1-eeprom.h
@@ -27,7 +27,5 @@
int w1_eeprom_dm_init(void);
-int w1_eeprom_register_new_device(u64 id);
-
int w1_eeprom_get_id(struct udevice *dev, u64 *id);
#endif
diff --git a/include/w1.h b/include/w1.h
index 77f439e..b18078b 100644
--- a/include/w1.h
+++ b/include/w1.h
@@ -15,6 +15,23 @@
#define W1_FAMILY_DS2502 0x09
#define W1_FAMILY_EEP_SANDBOX 0xfe
+struct w1_driver_entry {
+ struct driver *driver;
+ u8 *family;
+};
+
+/* U_BOOT_W1_DEVICE() tells U-Boot to create a one-wire device.
+ *
+ * @__name: Device name (C identifier, not a string. E.g. gpio7_at_ff7e0000)
+ * @__driver: Driver name (C identifier, not a string. E.g. gpio7_at_ff7e0000)
+ * @__family: Family code number of the one-wire
+ */
+#define U_BOOT_W1_DEVICE(__name, __family) \
+ ll_entry_declare(struct w1_driver_entry, __name, w1_driver_entry) = { \
+ .driver = llsym(struct driver, __name, driver), \
+ .family = __family, \
+ }
+
struct w1_device {
u64 id;
};
diff --git a/lib/Kconfig b/lib/Kconfig
index 6d2d41d..ad0cd52 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -25,7 +25,7 @@
config BINMAN_FDT
bool "Allow access to binman information in the device tree"
depends on BINMAN && DM && OF_CONTROL
- default y
+ default y if OF_SEPARATE || OF_EMBED
help
This enables U-Boot to access information about binman entries,
stored in the device tree in a binman node. Typical uses are to
@@ -389,21 +389,32 @@
(digest).
config SHA_HW_ACCEL
- bool "Enable hashing using hardware"
+ bool "Enable hardware acceleration for SHA hash functions"
+ help
+ This option enables hardware acceleration for the SHA1 and SHA256
+ hashing algorithms. This affects the 'hash' command and also the
+ hash_lookup_algo() function.
+
+if SHA_HW_ACCEL
+
+config SHA512_HW_ACCEL
+ bool "Enable hardware acceleration for SHA512"
+ depends on SHA512_ALGO
help
- This option enables hardware acceleration for SHA hashing.
- This affects the 'hash' command and also the hash_lookup_algo()
- function.
+ This option enables hardware acceleration for the SHA384 and SHA512
+ hashing algorithms. This affects the 'hash' command and also the
+ hash_lookup_algo() function.
config SHA_PROG_HW_ACCEL
bool "Enable Progressive hashing support using hardware"
- depends on SHA_HW_ACCEL
help
This option enables hardware-acceleration for SHA progressive
hashing.
Data can be streamed in a block at a time and the hashing is
performed in hardware.
+endif
+
config MD5
bool "Support MD5 algorithm"
help
@@ -663,6 +674,13 @@
See also SMBIOS_SYSINFO which allows SMBIOS values to be provided in
the devicetree.
+config LIB_RATIONAL
+ bool "enable continued fraction calculation routines"
+
+config SPL_LIB_RATIONAL
+ bool "enable continued fraction calculation routines for SPL"
+ depends on SPL
+
endmenu
config ASN1_COMPILER
diff --git a/lib/Makefile b/lib/Makefile
index 6825671..881034f 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -61,7 +61,7 @@
obj-$(CONFIG_$(SPL_)ACPIGEN) += acpi/
obj-$(CONFIG_$(SPL_)MD5) += md5.o
obj-$(CONFIG_$(SPL_)RSA) += rsa/
-obj-$(CONFIG_FIT_SIGNATURE) += hash-checksum.o
+obj-$(CONFIG_HASH) += hash-checksum.o
obj-$(CONFIG_SHA1) += sha1.o
obj-$(CONFIG_SHA256) += sha256.o
obj-$(CONFIG_SHA512_ALGO) += sha512.o
@@ -73,6 +73,8 @@
obj-$(CONFIG_$(SPL_)LZMA) += lzma/
obj-$(CONFIG_$(SPL_)LZ4) += lz4_wrapper.o
+obj-$(CONFIG_$(SPL_)LIB_RATIONAL) += rational.o
+
obj-$(CONFIG_LIBAVB) += libavb/
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += libfdt/
diff --git a/lib/crc32.c b/lib/crc32.c
index e9be3bf..f2acc10 100644
--- a/lib/crc32.c
+++ b/lib/crc32.c
@@ -26,6 +26,7 @@
#ifdef USE_HOSTCC
#define __efi_runtime
#define __efi_runtime_data
+#define __efi_runtime_rodata
#endif
#define tole(x) cpu_to_le32(x)
@@ -88,7 +89,7 @@
* Table of CRC-32's of all single-byte values (made by make_crc_table)
*/
-static const uint32_t __efi_runtime_data crc_table[256] = {
+static const uint32_t __efi_runtime_rodata crc_table[256] = {
tole(0x00000000L), tole(0x77073096L), tole(0xee0e612cL), tole(0x990951baL),
tole(0x076dc419L), tole(0x706af48fL), tole(0xe963a535L), tole(0x9e6495a3L),
tole(0x0edb8832L), tole(0x79dcb8a4L), tole(0xe0d5e91eL), tole(0x97d2d988L),
diff --git a/lib/display_options.c b/lib/display_options.c
index cd48998..c08a87e 100644
--- a/lib/display_options.c
+++ b/lib/display_options.c
@@ -131,10 +131,11 @@
printf (" %ciB%s", c, s);
}
-#define MAX_LINE_LENGTH_BYTES (64)
-#define DEFAULT_LINE_LENGTH_BYTES (16)
-int print_buffer(ulong addr, const void *data, uint width, uint count,
- uint linelen)
+#define MAX_LINE_LENGTH_BYTES 64
+#define DEFAULT_LINE_LENGTH_BYTES 16
+
+int hexdump_line(ulong addr, const void *data, uint width, uint count,
+ uint linelen, char *out, int size)
{
/* linebuf as a union causes proper alignment */
union linebuf {
@@ -143,62 +144,86 @@
uint16_t us[MAX_LINE_LENGTH_BYTES/sizeof(uint16_t) + 1];
uint8_t uc[MAX_LINE_LENGTH_BYTES/sizeof(uint8_t) + 1];
} lb;
+ uint thislinelen;
int i;
ulong x;
- if (linelen*width > MAX_LINE_LENGTH_BYTES)
+ if (linelen * width > MAX_LINE_LENGTH_BYTES)
linelen = MAX_LINE_LENGTH_BYTES / width;
if (linelen < 1)
linelen = DEFAULT_LINE_LENGTH_BYTES / width;
- while (count) {
- uint thislinelen = linelen;
- printf("%08lx:", addr);
+ /*
+ * Check the size here so that we don't need to use snprintf(). This
+ * helps to reduce code size
+ */
+ if (size < HEXDUMP_MAX_BUF_LENGTH(linelen * width))
+ return -ENOSPC;
+
+ thislinelen = linelen;
+ out += sprintf(out, "%08lx:", addr);
+
+ /* check for overflow condition */
+ if (count < thislinelen)
+ thislinelen = count;
+
+ /* Copy from memory into linebuf and print hex values */
+ for (i = 0; i < thislinelen; i++) {
+ if (width == 4)
+ x = lb.ui[i] = *(volatile uint32_t *)data;
+ else if (MEM_SUPPORT_64BIT_DATA && width == 8)
+ x = lb.uq[i] = *(volatile ulong *)data;
+ else if (width == 2)
+ x = lb.us[i] = *(volatile uint16_t *)data;
+ else
+ x = lb.uc[i] = *(volatile uint8_t *)data;
+ if (CONFIG_IS_ENABLED(USE_TINY_PRINTF))
+ out += sprintf(out, " %x", (uint)x);
+ else
+ out += sprintf(out, " %0*lx", width * 2, x);
+ data += width;
+ }
+
+ /* fill line with whitespace for nice ASCII print */
+ for (i = 0; i < (linelen - thislinelen) * (width * 2 + 1); i++)
+ *out++ = ' ';
- /* check for overflow condition */
- if (count < thislinelen)
- thislinelen = count;
+ /* Print data in ASCII characters */
+ for (i = 0; i < thislinelen * width; i++) {
+ if (!isprint(lb.uc[i]) || lb.uc[i] >= 0x80)
+ lb.uc[i] = '.';
+ }
+ lb.uc[i] = '\0';
+ out += sprintf(out, " %s", lb.uc);
- /* Copy from memory into linebuf and print hex values */
- for (i = 0; i < thislinelen; i++) {
- if (width == 4)
- x = lb.ui[i] = *(volatile uint32_t *)data;
- else if (MEM_SUPPORT_64BIT_DATA && width == 8)
- x = lb.uq[i] = *(volatile ulong *)data;
- else if (width == 2)
- x = lb.us[i] = *(volatile uint16_t *)data;
- else
- x = lb.uc[i] = *(volatile uint8_t *)data;
- if (CONFIG_IS_ENABLED(USE_TINY_PRINTF))
- printf(" %x", (uint)x);
- else
- printf(" %0*lx", width * 2, x);
- data += width;
- }
+ return thislinelen;
+}
- while (thislinelen < linelen) {
- /* fill line with whitespace for nice ASCII print */
- for (i=0; i<width*2+1; i++)
- puts(" ");
- linelen--;
- }
+int print_buffer(ulong addr, const void *data, uint width, uint count,
+ uint linelen)
+{
+ if (linelen*width > MAX_LINE_LENGTH_BYTES)
+ linelen = MAX_LINE_LENGTH_BYTES / width;
+ if (linelen < 1)
+ linelen = DEFAULT_LINE_LENGTH_BYTES / width;
+
+ while (count) {
+ uint thislinelen;
+ char buf[HEXDUMP_MAX_BUF_LENGTH(width * linelen)];
- /* Print data in ASCII characters */
- for (i = 0; i < thislinelen * width; i++) {
- if (!isprint(lb.uc[i]) || lb.uc[i] >= 0x80)
- lb.uc[i] = '.';
- }
- lb.uc[i] = '\0';
- printf(" %s\n", lb.uc);
+ thislinelen = hexdump_line(addr, data, width, count, linelen,
+ buf, sizeof(buf));
+ assert(thislinelen >= 0);
+ puts(buf);
+ putc('\n');
/* update references */
+ data += thislinelen * width;
addr += thislinelen * width;
count -= thislinelen;
-#ifndef CONFIG_SPL_BUILD
- if (ctrlc())
- return -1;
-#endif
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc())
+ return -EINTR;
}
return 0;
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 0b99d7c..6242cac 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -166,6 +166,7 @@
depends on EFI_CAPSULE_FIRMWARE
depends on EFI_CAPSULE_ON_DISK
depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
+ select HASH
select SHA256
select RSA
select RSA_VERIFY
@@ -174,6 +175,7 @@
select PKCS7_MESSAGE_PARSER
select PKCS7_VERIFY
select IMAGE_SIGN_INFO
+ select EFI_SIGNATURE_SUPPORT
default n
help
Select this option if you want to enable capsule
@@ -300,7 +302,14 @@
config EFI_TCG2_PROTOCOL
bool "EFI_TCG2_PROTOCOL support"
+ default y
depends on TPM_V2
+ select SHA1
+ select SHA256
+ select SHA512_ALGO
+ select SHA384
+ select SHA512
+ select HASH
help
Provide a EFI_TCG2_PROTOCOL implementation using the TPM hardware
of the platform.
@@ -327,6 +336,7 @@
config EFI_SECURE_BOOT
bool "Enable EFI secure boot support"
depends on EFI_LOADER
+ select HASH
select SHA256
select RSA
select RSA_VERIFY_WITH_PKEY
@@ -336,6 +346,7 @@
select X509_CERTIFICATE_PARSER
select PKCS7_MESSAGE_PARSER
select PKCS7_VERIFY
+ select EFI_SIGNATURE_SUPPORT
default n
help
Select this option to enable EFI secure boot support.
@@ -343,6 +354,9 @@
it is signed with a trusted key. To do that, you need to install,
at least, PK, KEK and db.
+config EFI_SIGNATURE_SUPPORT
+ bool
+
config EFI_ESRT
bool "Enable the UEFI ESRT generation"
depends on EFI_CAPSULE_FIRMWARE_MANAGEMENT
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index 8bd343e..fd344ce 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -63,7 +63,7 @@
obj-$(CONFIG_EFI_RNG_PROTOCOL) += efi_rng.o
obj-$(CONFIG_EFI_TCG2_PROTOCOL) += efi_tcg2.o
obj-$(CONFIG_EFI_LOAD_FILE2_INITRD) += efi_load_initrd.o
-obj-y += efi_signature.o
+obj-$(CONFIG_EFI_SIGNATURE_SUPPORT) += efi_signature.o
EFI_VAR_SEED_FILE := $(subst $\",,$(CONFIG_EFI_VAR_SEED_FILE))
$(obj)/efi_var_seed.o: $(srctree)/$(EFI_VAR_SEED_FILE)
diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index 6ee883d..9ead0d2 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -208,16 +208,6 @@
const efi_guid_t efi_guid_capsule_root_cert_guid =
EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
-__weak int efi_get_public_key_data(void **pkey, efi_uintn_t *pkey_len)
-{
- /* The platform is supposed to provide
- * a method for getting the public key
- * stored in the form of efi signature
- * list
- */
- return 0;
-}
-
efi_status_t efi_capsule_authenticate(const void *capsule, efi_uintn_t capsule_size,
void **image, efi_uintn_t *image_size)
{
diff --git a/lib/efi_loader/efi_device_path.c b/lib/efi_loader/efi_device_path.c
index 4b20859..76c2f82 100644
--- a/lib/efi_loader/efi_device_path.c
+++ b/lib/efi_loader/efi_device_path.c
@@ -1171,7 +1171,7 @@
struct blk_desc *desc = NULL;
struct disk_partition fs_partition;
int part = 0;
- char filename[32] = { 0 }; /* dp->str is u16[32] long */
+ char *filename;
char *s;
if (path && !file)
@@ -1198,12 +1198,17 @@
if (!path)
return EFI_SUCCESS;
- snprintf(filename, sizeof(filename), "%s", path);
+ filename = calloc(1, strlen(path) + 1);
+ if (!filename)
+ return EFI_OUT_OF_RESOURCES;
+
+ sprintf(filename, "%s", path);
/* DOS style file path: */
s = filename;
while ((s = strchr(s, '/')))
*s++ = '\\';
*file = efi_dp_from_file(desc, part, filename);
+ free(filename);
if (!*file)
return EFI_INVALID_PARAMETER;
diff --git a/lib/efi_loader/efi_file.c b/lib/efi_loader/efi_file.c
index 204105e..6b3f596 100644
--- a/lib/efi_loader/efi_file.c
+++ b/lib/efi_loader/efi_file.c
@@ -554,7 +554,7 @@
efi_status_t ret = EFI_SUCCESS;
u64 bs;
- if (!this || !buffer_size || !buffer)
+ if (!this || !buffer_size)
return EFI_INVALID_PARAMETER;
bs = *buffer_size;
diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c
index 7a3cca2..a1b88db 100644
--- a/lib/efi_loader/efi_firmware.c
+++ b/lib/efi_loader/efi_firmware.c
@@ -190,7 +190,7 @@
IMAGE_ATTRIBUTE_IMAGE_UPDATABLE;
/* Check if the capsule authentication is enabled */
- if (env_get("capsule_authentication_enabled"))
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE))
image_info[0].attributes_setting |=
IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED;
@@ -421,8 +421,7 @@
return EFI_EXIT(EFI_INVALID_PARAMETER);
/* Authenticate the capsule if authentication enabled */
- if (IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE) &&
- env_get("capsule_authentication_enabled")) {
+ if (IS_ENABLED(CONFIG_EFI_CAPSULE_AUTHENTICATE)) {
capsule_payload = NULL;
capsule_payload_size = 0;
status = efi_capsule_authenticate(image, image_size,
diff --git a/lib/efi_loader/efi_image_loader.c b/lib/efi_loader/efi_image_loader.c
index f53ef36..bcd57f7 100644
--- a/lib/efi_loader/efi_image_loader.c
+++ b/lib/efi_loader/efi_image_loader.c
@@ -213,7 +213,68 @@
}
}
-#ifdef CONFIG_EFI_SECURE_BOOT
+/**
+ * efi_image_region_add() - add an entry of region
+ * @regs: Pointer to array of regions
+ * @start: Start address of region (included)
+ * @end: End address of region (excluded)
+ * @nocheck: flag against overlapped regions
+ *
+ * Take one entry of region [@start, @end[ and insert it into the list.
+ *
+ * * If @nocheck is false, the list will be sorted ascending by address.
+ * Overlapping entries will not be allowed.
+ *
+ * * If @nocheck is true, the list will be sorted ascending by sequence
+ * of adding the entries. Overlapping is allowed.
+ *
+ * Return: status code
+ */
+efi_status_t efi_image_region_add(struct efi_image_regions *regs,
+ const void *start, const void *end,
+ int nocheck)
+{
+ struct image_region *reg;
+ int i, j;
+
+ if (regs->num >= regs->max) {
+ EFI_PRINT("%s: no more room for regions\n", __func__);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ if (end < start)
+ return EFI_INVALID_PARAMETER;
+
+ for (i = 0; i < regs->num; i++) {
+ reg = ®s->reg[i];
+ if (nocheck)
+ continue;
+
+ /* new data after registered region */
+ if (start >= reg->data + reg->size)
+ continue;
+
+ /* new data preceding registered region */
+ if (end <= reg->data) {
+ for (j = regs->num - 1; j >= i; j--)
+ memcpy(®s->reg[j + 1], ®s->reg[j],
+ sizeof(*reg));
+ break;
+ }
+
+ /* new data overlapping registered region */
+ EFI_PRINT("%s: new region already part of another\n", __func__);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ reg = ®s->reg[i];
+ reg->data = start;
+ reg->size = end - start;
+ regs->num++;
+
+ return EFI_SUCCESS;
+}
+
/**
* cmp_pe_section() - compare virtual addresses of two PE image sections
* @arg1: pointer to pointer to first section header
@@ -242,6 +303,38 @@
}
/**
+ * efi_prepare_aligned_image() - prepare 8-byte aligned image
+ * @efi: pointer to the EFI binary
+ * @efi_size: size of @efi binary
+ *
+ * If @efi is not 8-byte aligned, this function newly allocates
+ * the image buffer.
+ *
+ * Return: valid pointer to a image, return NULL if allocation fails.
+ */
+void *efi_prepare_aligned_image(void *efi, u64 *efi_size)
+{
+ size_t new_efi_size;
+ void *new_efi;
+
+ /*
+ * Size must be 8-byte aligned and the trailing bytes must be
+ * zero'ed. Otherwise hash value may be incorrect.
+ */
+ if (!IS_ALIGNED(*efi_size, 8)) {
+ new_efi_size = ALIGN(*efi_size, 8);
+ new_efi = calloc(new_efi_size, 1);
+ if (!new_efi)
+ return NULL;
+ memcpy(new_efi, efi, *efi_size);
+ *efi_size = new_efi_size;
+ return new_efi;
+ } else {
+ return efi;
+ }
+}
+
+/**
* efi_image_parse() - parse a PE image
* @efi: Pointer to image
* @len: Size of @efi
@@ -422,6 +515,7 @@
return false;
}
+#ifdef CONFIG_EFI_SECURE_BOOT
/**
* efi_image_unsigned_authenticate() - authenticate unsigned image with
* SHA256 hash
@@ -499,7 +593,7 @@
struct efi_signature_store *db = NULL, *dbx = NULL;
void *new_efi = NULL;
u8 *auth, *wincerts_end;
- size_t new_efi_size, auth_size;
+ size_t auth_size;
bool ret = false;
EFI_PRINT("%s: Enter, %d\n", __func__, ret);
@@ -507,21 +601,11 @@
if (!efi_secure_boot_enabled())
return true;
- /*
- * Size must be 8-byte aligned and the trailing bytes must be
- * zero'ed. Otherwise hash value may be incorrect.
- */
- if (efi_size & 0x7) {
- new_efi_size = (efi_size + 0x7) & ~0x7ULL;
- new_efi = calloc(new_efi_size, 1);
- if (!new_efi)
- return false;
- memcpy(new_efi, efi, efi_size);
- efi = new_efi;
- efi_size = new_efi_size;
- }
+ new_efi = efi_prepare_aligned_image(efi, (u64 *)&efi_size);
+ if (!new_efi)
+ return false;
- if (!efi_image_parse(efi, efi_size, ®s, &wincerts,
+ if (!efi_image_parse(new_efi, efi_size, ®s, &wincerts,
&wincerts_len)) {
EFI_PRINT("Parsing PE executable image failed\n");
goto err;
@@ -663,7 +747,8 @@
efi_sigstore_free(dbx);
pkcs7_free_message(msg);
free(regs);
- free(new_efi);
+ if (new_efi != efi)
+ free(new_efi);
EFI_PRINT("%s: Exit, %d\n", __func__, ret);
return ret;
@@ -829,6 +914,13 @@
goto err;
}
+#if CONFIG_IS_ENABLED(EFI_TCG2_PROTOCOL)
+ /* Measure an PE/COFF image */
+ if (tcg2_measure_pe_image(efi, efi_size, handle,
+ loaded_image_info))
+ log_err("PE image measurement failed\n");
+#endif
+
/* Copy PE headers */
memcpy(efi_reloc, efi,
sizeof(*dos)
diff --git a/lib/efi_loader/efi_signature.c b/lib/efi_loader/efi_signature.c
index c7ec275..bdd0988 100644
--- a/lib/efi_loader/efi_signature.c
+++ b/lib/efi_loader/efi_signature.c
@@ -15,18 +15,16 @@
#include <crypto/public_key.h>
#include <linux/compat.h>
#include <linux/oid_registry.h>
+#include <u-boot/hash-checksum.h>
#include <u-boot/rsa.h>
#include <u-boot/sha256.h>
-const efi_guid_t efi_guid_image_security_database =
- EFI_IMAGE_SECURITY_DATABASE_GUID;
const efi_guid_t efi_guid_sha256 = EFI_CERT_SHA256_GUID;
const efi_guid_t efi_guid_cert_rsa2048 = EFI_CERT_RSA2048_GUID;
const efi_guid_t efi_guid_cert_x509 = EFI_CERT_X509_GUID;
const efi_guid_t efi_guid_cert_x509_sha256 = EFI_CERT_X509_SHA256_GUID;
const efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
-#if defined(CONFIG_EFI_SECURE_BOOT) || defined(CONFIG_EFI_CAPSULE_AUTHENTICATE)
static u8 pkcs7_hdr[] = {
/* SEQUENCE */
0x30, 0x82, 0x05, 0xc7,
@@ -540,68 +538,6 @@
}
/**
- * efi_image_region_add() - add an entry of region
- * @regs: Pointer to array of regions
- * @start: Start address of region (included)
- * @end: End address of region (excluded)
- * @nocheck: flag against overlapped regions
- *
- * Take one entry of region [@start, @end[ and insert it into the list.
- *
- * * If @nocheck is false, the list will be sorted ascending by address.
- * Overlapping entries will not be allowed.
- *
- * * If @nocheck is true, the list will be sorted ascending by sequence
- * of adding the entries. Overlapping is allowed.
- *
- * Return: status code
- */
-efi_status_t efi_image_region_add(struct efi_image_regions *regs,
- const void *start, const void *end,
- int nocheck)
-{
- struct image_region *reg;
- int i, j;
-
- if (regs->num >= regs->max) {
- EFI_PRINT("%s: no more room for regions\n", __func__);
- return EFI_OUT_OF_RESOURCES;
- }
-
- if (end < start)
- return EFI_INVALID_PARAMETER;
-
- for (i = 0; i < regs->num; i++) {
- reg = ®s->reg[i];
- if (nocheck)
- continue;
-
- /* new data after registered region */
- if (start >= reg->data + reg->size)
- continue;
-
- /* new data preceding registered region */
- if (end <= reg->data) {
- for (j = regs->num - 1; j >= i; j--)
- memcpy(®s->reg[j + 1], ®s->reg[j],
- sizeof(*reg));
- break;
- }
-
- /* new data overlapping registered region */
- EFI_PRINT("%s: new region already part of another\n", __func__);
- return EFI_INVALID_PARAMETER;
- }
-
- reg = ®s->reg[i];
- reg->data = start;
- reg->size = end - start;
- regs->num++;
-
- return EFI_SUCCESS;
-}
-
-/**
* efi_sigstore_free - free signature store
* @sigstore: Pointer to signature store structure
*
@@ -846,4 +782,3 @@
return efi_build_signature_store(db, db_size);
}
-#endif /* CONFIG_EFI_SECURE_BOOT || CONFIG_EFI_CAPSULE_AUTHENTICATE */
diff --git a/lib/efi_loader/efi_tcg2.c b/lib/efi_loader/efi_tcg2.c
index 94e8f22..1319a8b 100644
--- a/lib/efi_loader/efi_tcg2.c
+++ b/lib/efi_loader/efi_tcg2.c
@@ -13,8 +13,10 @@
#include <efi_loader.h>
#include <efi_tcg2.h>
#include <log.h>
+#include <malloc.h>
#include <version.h>
#include <tpm-v2.h>
+#include <u-boot/hash-checksum.h>
#include <u-boot/sha1.h>
#include <u-boot/sha256.h>
#include <u-boot/sha512.h>
@@ -53,7 +55,7 @@
u16 hash_len;
};
-const static struct digest_info hash_algo_list[] = {
+static const struct digest_info hash_algo_list[] = {
{
TPM2_ALG_SHA1,
EFI_TCG2_BOOT_HASH_ALG_SHA1,
@@ -87,7 +89,7 @@
*/
static u32 alg_to_mask(u16 hash_alg)
{
- int i;
+ size_t i;
for (i = 0; i < MAX_HASH_COUNT; i++) {
if (hash_algo_list[i].hash_alg == hash_alg)
@@ -106,7 +108,7 @@
*/
static u16 alg_to_len(u16 hash_alg)
{
- int i;
+ size_t i;
for (i = 0; i < MAX_HASH_COUNT; i++) {
if (hash_algo_list[i].hash_alg == hash_alg)
@@ -119,7 +121,7 @@
static u32 tcg_event_final_size(struct tpml_digest_values *digest_list)
{
u32 len;
- int i;
+ size_t i;
len = offsetof(struct tcg_pcr_event2, digests);
len += offsetof(struct tpml_digest_values, digests);
@@ -145,7 +147,7 @@
struct tpml_digest_values *digest_list)
{
u32 rc;
- int i;
+ size_t i;
for (i = 0; i < digest_list->count; i++) {
u32 alg = digest_list->digests[i].hash_alg;
@@ -178,7 +180,7 @@
{
void *log = (void *)((uintptr_t)event_log.buffer + event_log.pos);
size_t pos;
- int i;
+ size_t i;
u32 event_size;
if (event_log.get_event_called)
@@ -400,8 +402,12 @@
u8 response[TPM2_RESPONSE_BUFFER_SIZE];
struct tpml_pcr_selection pcrs;
u32 ret, num_pcr;
- int i, tpm_ret;
+ size_t i;
+ int tpm_ret;
+ *supported_pcr = 0;
+ *active_pcr = 0;
+ *pcr_banks = 0;
memset(response, 0, sizeof(response));
ret = tpm2_get_capability(dev, TPM2_CAP_PCRS, 0, response, 1);
if (ret)
@@ -480,7 +486,7 @@
static efi_status_t __get_active_pcr_banks(u32 *active_pcr_banks)
{
struct udevice *dev;
- u32 active, supported, pcr_banks;
+ u32 active = 0, supported = 0, pcr_banks = 0;
efi_status_t ret;
int err;
@@ -518,7 +524,7 @@
u8 final[TPM2_SHA512_DIGEST_SIZE];
efi_status_t ret;
u32 active;
- int i;
+ size_t i;
ret = __get_active_pcr_banks(&active);
if (ret != EFI_SUCCESS)
@@ -707,6 +713,183 @@
}
/**
+ * tcg2_hash_pe_image() - calculate PE/COFF image hash
+ *
+ * @efi: pointer to the EFI binary
+ * @efi_size: size of @efi binary
+ * @digest_list: list of digest algorithms to extend
+ *
+ * Return: status code
+ */
+static efi_status_t tcg2_hash_pe_image(void *efi, u64 efi_size,
+ struct tpml_digest_values *digest_list)
+{
+ WIN_CERTIFICATE *wincerts = NULL;
+ size_t wincerts_len;
+ struct efi_image_regions *regs = NULL;
+ void *new_efi = NULL;
+ u8 hash[TPM2_SHA512_DIGEST_SIZE];
+ efi_status_t ret;
+ u32 active;
+ int i;
+
+ new_efi = efi_prepare_aligned_image(efi, &efi_size);
+ if (!new_efi)
+ return EFI_OUT_OF_RESOURCES;
+
+ if (!efi_image_parse(new_efi, efi_size, ®s, &wincerts,
+ &wincerts_len)) {
+ log_err("Parsing PE executable image failed\n");
+ ret = EFI_UNSUPPORTED;
+ goto out;
+ }
+
+ ret = __get_active_pcr_banks(&active);
+ if (ret != EFI_SUCCESS) {
+ goto out;
+ }
+
+ digest_list->count = 0;
+ for (i = 0; i < MAX_HASH_COUNT; i++) {
+ u16 hash_alg = hash_algo_list[i].hash_alg;
+
+ if (!(active & alg_to_mask(hash_alg)))
+ continue;
+ switch (hash_alg) {
+ case TPM2_ALG_SHA1:
+ hash_calculate("sha1", regs->reg, regs->num, hash);
+ break;
+ case TPM2_ALG_SHA256:
+ hash_calculate("sha256", regs->reg, regs->num, hash);
+ break;
+ case TPM2_ALG_SHA384:
+ hash_calculate("sha384", regs->reg, regs->num, hash);
+ break;
+ case TPM2_ALG_SHA512:
+ hash_calculate("sha512", regs->reg, regs->num, hash);
+ break;
+ default:
+ EFI_PRINT("Unsupported algorithm %x\n", hash_alg);
+ return EFI_INVALID_PARAMETER;
+ }
+ digest_list->digests[i].hash_alg = hash_alg;
+ memcpy(&digest_list->digests[i].digest, hash, (u32)alg_to_len(hash_alg));
+ digest_list->count++;
+ }
+
+out:
+ if (new_efi != efi)
+ free(new_efi);
+ free(regs);
+
+ return ret;
+}
+
+/**
+ * tcg2_measure_pe_image() - measure PE/COFF image
+ *
+ * @efi: pointer to the EFI binary
+ * @efi_size: size of @efi binary
+ * @handle: loaded image handle
+ * @loaded_image: loaded image protocol
+ *
+ * Return: status code
+ */
+efi_status_t tcg2_measure_pe_image(void *efi, u64 efi_size,
+ struct efi_loaded_image_obj *handle,
+ struct efi_loaded_image *loaded_image)
+{
+ struct tpml_digest_values digest_list;
+ efi_status_t ret;
+ struct udevice *dev;
+ u32 pcr_index, event_type, event_size;
+ struct uefi_image_load_event *image_load_event;
+ struct efi_device_path *device_path;
+ u32 device_path_length;
+ IMAGE_DOS_HEADER *dos;
+ IMAGE_NT_HEADERS32 *nt;
+ struct efi_handler *handler;
+
+ ret = platform_get_tpm2_device(&dev);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ switch (handle->image_type) {
+ case IMAGE_SUBSYSTEM_EFI_APPLICATION:
+ pcr_index = 4;
+ event_type = EV_EFI_BOOT_SERVICES_APPLICATION;
+ break;
+ case IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER:
+ pcr_index = 2;
+ event_type = EV_EFI_BOOT_SERVICES_DRIVER;
+ break;
+ case IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER:
+ pcr_index = 2;
+ event_type = EV_EFI_RUNTIME_SERVICES_DRIVER;
+ break;
+ default:
+ return EFI_UNSUPPORTED;
+ }
+
+ ret = tcg2_hash_pe_image(efi, efi_size, &digest_list);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = tcg2_pcr_extend(dev, pcr_index, &digest_list);
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ ret = EFI_CALL(efi_search_protocol(&handle->header,
+ &efi_guid_loaded_image_device_path,
+ &handler));
+ if (ret != EFI_SUCCESS)
+ return ret;
+
+ device_path = EFI_CALL(handler->protocol_interface);
+ device_path_length = efi_dp_size(device_path);
+ if (device_path_length > 0) {
+ /* add end node size */
+ device_path_length += sizeof(struct efi_device_path);
+ }
+ event_size = sizeof(struct uefi_image_load_event) + device_path_length;
+ image_load_event = (struct uefi_image_load_event *)malloc(event_size);
+ if (!image_load_event)
+ return EFI_OUT_OF_RESOURCES;
+
+ image_load_event->image_location_in_memory = (uintptr_t)efi;
+ image_load_event->image_length_in_memory = efi_size;
+ image_load_event->length_of_device_path = device_path_length;
+
+ dos = (IMAGE_DOS_HEADER *)efi;
+ nt = (IMAGE_NT_HEADERS32 *)(efi + dos->e_lfanew);
+ if (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC) {
+ IMAGE_NT_HEADERS64 *nt64 = (IMAGE_NT_HEADERS64 *)nt;
+
+ image_load_event->image_link_time_address =
+ nt64->OptionalHeader.ImageBase;
+ } else if (nt->OptionalHeader.Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC) {
+ image_load_event->image_link_time_address =
+ nt->OptionalHeader.ImageBase;
+ } else {
+ ret = EFI_INVALID_PARAMETER;
+ goto out;
+ }
+
+ if (device_path_length > 0) {
+ memcpy(image_load_event->device_path, device_path,
+ device_path_length);
+ }
+
+ ret = tcg2_agile_log_append(pcr_index, event_type, &digest_list,
+ event_size, (u8 *)image_load_event);
+
+out:
+ free(image_load_event);
+
+ return ret;
+}
+
+/**
* efi_tcg2_hash_log_extend_event() - extend and optionally log events
*
* @this: TCG2 protocol instance
@@ -749,8 +932,7 @@
goto out;
}
- if (efi_tcg_event->header.pcr_index < 0 ||
- efi_tcg_event->header.pcr_index > TPM2_MAX_PCRS) {
+ if (efi_tcg_event->header.pcr_index > TPM2_MAX_PCRS) {
ret = EFI_INVALID_PARAMETER;
goto out;
}
@@ -758,24 +940,32 @@
/*
* if PE_COFF_IMAGE is set we need to make sure the image is not
* corrupted, verify it and hash the PE/COFF image in accordance with
- * the procedure specified in "Calculating the PE Image Hash"
- * section of the "Windows Authenticode Portable Executable Signature
+ * the procedure specified in "Calculating the PE Image Hash"
+ * section of the "Windows Authenticode Portable Executable Signature
* Format"
- * Not supported for now
*/
if (flags & PE_COFF_IMAGE) {
- ret = EFI_UNSUPPORTED;
- goto out;
- }
+ IMAGE_NT_HEADERS32 *nt;
- pcr_index = efi_tcg_event->header.pcr_index;
- event_type = efi_tcg_event->header.event_type;
+ ret = efi_check_pe((void *)(uintptr_t)data_to_hash,
+ data_to_hash_len, (void **)&nt);
+ if (ret != EFI_SUCCESS) {
+ log_err("Not a valid PE-COFF file\n");
+ goto out;
+ }
+ ret = tcg2_hash_pe_image((void *)(uintptr_t)data_to_hash,
+ data_to_hash_len, &digest_list);
+ } else {
+ ret = tcg2_create_digest((u8 *)(uintptr_t)data_to_hash,
+ data_to_hash_len, &digest_list);
+ }
- ret = tcg2_create_digest((u8 *)data_to_hash, data_to_hash_len,
- &digest_list);
if (ret != EFI_SUCCESS)
goto out;
+ pcr_index = efi_tcg_event->header.pcr_index;
+ event_type = efi_tcg_event->header.event_type;
+
ret = tcg2_pcr_extend(dev, pcr_index, &digest_list);
if (ret != EFI_SUCCESS)
goto out;
@@ -810,9 +1000,11 @@
* Return: status code
*/
static efi_status_t EFIAPI
-efi_tcg2_submit_command(struct efi_tcg2_protocol *this,
- u32 input_param_block_size, u8 *input_param_block,
- u32 output_param_block_size, u8 *output_param_block)
+efi_tcg2_submit_command(__maybe_unused struct efi_tcg2_protocol *this,
+ u32 __maybe_unused input_param_block_size,
+ u8 __maybe_unused *input_param_block,
+ u32 __maybe_unused output_param_block_size,
+ u8 __maybe_unused *output_param_block)
{
return EFI_UNSUPPORTED;
}
@@ -847,8 +1039,8 @@
* Return: status code
*/
static efi_status_t EFIAPI
-efi_tcg2_set_active_pcr_banks(struct efi_tcg2_protocol *this,
- u32 active_pcr_banks)
+efi_tcg2_set_active_pcr_banks(__maybe_unused struct efi_tcg2_protocol *this,
+ u32 __maybe_unused active_pcr_banks)
{
return EFI_UNSUPPORTED;
}
@@ -866,8 +1058,9 @@
* Return: status code
*/
static efi_status_t EFIAPI
-efi_tcg2_get_result_of_set_active_pcr_banks(struct efi_tcg2_protocol *this,
- u32 *operation_present, u32 *response)
+efi_tcg2_get_result_of_set_active_pcr_banks(__maybe_unused struct efi_tcg2_protocol *this,
+ u32 __maybe_unused *operation_present,
+ u32 __maybe_unused *response)
{
return EFI_UNSUPPORTED;
}
@@ -897,8 +1090,9 @@
struct tcg_efi_spec_id_event *spec_event;
size_t spec_event_size;
efi_status_t ret = EFI_DEVICE_ERROR;
- u32 active, supported;
- int err, i;
+ u32 active = 0, supported = 0;
+ int err;
+ size_t i;
/*
* Create Spec event. This needs to be the first event in the log
@@ -999,6 +1193,11 @@
event_log.final_pos = sizeof(*final_event);
ret = efi_install_configuration_table(&efi_guid_final_events,
final_event);
+ if (ret != EFI_SUCCESS) {
+ efi_free_pool(event_log.final_buffer);
+ event_log.final_buffer = NULL;
+ }
+
out:
return ret;
}
@@ -1047,18 +1246,21 @@
ret = create_specid_event(dev, (void *)((uintptr_t)event_log.buffer + sizeof(*event_header)),
&spec_event_size);
if (ret != EFI_SUCCESS)
- goto out;
+ goto free_pool;
put_unaligned_le32(spec_event_size, &event_header->event_size);
event_log.pos = spec_event_size + sizeof(*event_header);
event_log.last_event_size = event_log.pos;
ret = create_final_event();
if (ret != EFI_SUCCESS)
- goto out;
+ goto free_pool;
- return EFI_SUCCESS;
out:
- tcg2_uninit();
+ return ret;
+
+free_pool:
+ efi_free_pool(event_log.buffer);
+ event_log.buffer = NULL;
return ret;
}
@@ -1107,8 +1309,7 @@
ret = platform_get_tpm2_device(&dev);
if (ret != EFI_SUCCESS) {
log_warning("Unable to find TPMv2 device\n");
- ret = EFI_SUCCESS;
- goto out;
+ return EFI_SUCCESS;
}
ret = efi_init_event_log();
@@ -1116,19 +1317,29 @@
goto fail;
ret = efi_append_scrtm_version(dev);
- if (ret != EFI_SUCCESS)
- goto out;
+ if (ret != EFI_SUCCESS) {
+ tcg2_uninit();
+ goto fail;
+ }
ret = efi_add_protocol(efi_root, &efi_guid_tcg2_protocol,
(void *)&efi_tcg2_protocol);
if (ret != EFI_SUCCESS) {
- log_err("Cannot install EFI_TCG2_PROTOCOL\n");
+ tcg2_uninit();
goto fail;
}
-
-out:
return ret;
+
fail:
- tcg2_uninit();
- return ret;
+ log_err("Cannot install EFI_TCG2_PROTOCOL\n");
+ /*
+ * Return EFI_SUCCESS and don't stop the EFI subsystem.
+ * That's done for 2 reasons
+ * - If the protocol is not installed the PCRs won't be extended. So
+ * someone later in the boot flow will notice that and take the
+ * necessary actions.
+ * - The TPM sandbox is limited and we won't be able to run any efi
+ * related tests with TCG2 enabled
+ */
+ return EFI_SUCCESS;
}
diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c
index b11ed91..83479dd 100644
--- a/lib/efi_loader/efi_var_common.c
+++ b/lib/efi_loader/efi_var_common.c
@@ -24,6 +24,9 @@
const enum efi_auth_var_type type;
};
+const efi_guid_t efi_guid_image_security_database =
+ EFI_IMAGE_SECURITY_DATABASE_GUID;
+
static const struct efi_auth_var_name_type name_type[] = {
{u"PK", &efi_global_variable_guid, EFI_AUTH_VAR_PK},
{u"KEK", &efi_global_variable_guid, EFI_AUTH_VAR_KEK},
diff --git a/lib/efi_selftest/Makefile b/lib/efi_selftest/Makefile
index aa71d09..9ff6e17 100644
--- a/lib/efi_selftest/Makefile
+++ b/lib/efi_selftest/Makefile
@@ -10,6 +10,8 @@
CFLAGS_dtbdump.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_dtbdump.o := $(CFLAGS_NON_EFI)
+CFLAGS_efi_selftest_miniapp_exception.o := $(CFLAGS_EFI) -Os -ffreestanding
+CFLAGS_REMOVE_efi_selftest_miniapp_exception.o := $(CFLAGS_NON_EFI)
CFLAGS_efi_selftest_miniapp_exit.o := $(CFLAGS_EFI) -Os -ffreestanding
CFLAGS_REMOVE_efi_selftest_miniapp_exit.o := $(CFLAGS_NON_EFI)
CFLAGS_efi_selftest_miniapp_return.o := $(CFLAGS_EFI) -Os -ffreestanding
diff --git a/lib/errno.c b/lib/errno.c
index 8330a8f..ca0c756 100644
--- a/lib/errno.c
+++ b/lib/errno.c
@@ -1 +1,3 @@
-int errno = 0;
+#include <errno.h>
+
+int errno __errno_asm_label = 0;
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 8645891..4b097fb 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -942,7 +942,11 @@
while (ptr + na + ns <= end) {
if (i == index) {
- res->start = fdtdec_get_number(ptr, na);
+ if (CONFIG_IS_ENABLED(OF_TRANSLATE))
+ res->start = fdt_translate_address(fdt, node, ptr);
+ else
+ res->start = fdtdec_get_number(ptr, na);
+
res->end = res->start;
res->end += fdtdec_get_number(&ptr[na], ns) - 1;
return 0;
diff --git a/lib/hexdump.c b/lib/hexdump.c
index a3f219a..149c93e 100644
--- a/lib/hexdump.c
+++ b/lib/hexdump.c
@@ -10,45 +10,18 @@
#include <common.h>
#include <hexdump.h>
+#include <mapmem.h>
#include <linux/ctype.h>
#include <linux/compat.h>
#include <linux/log2.h>
#include <asm/unaligned.h>
+#define MAX_LINE_LENGTH_BYTES 64
+
const char hex_asc[] = "0123456789abcdef";
const char hex_asc_upper[] = "0123456789ABCDEF";
#if CONFIG_IS_ENABLED(HEXDUMP)
-/**
- * hex_dump_to_buffer - convert a blob of data to "hex ASCII" in memory
- * @buf: data blob to dump
- * @len: number of bytes in the @buf
- * @rowsize: number of bytes to print per line; must be 16 or 32
- * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1)
- * @linebuf: where to put the converted data
- * @linebuflen: total size of @linebuf, including space for terminating NUL
- * @ascii: include ASCII after the hex output
- *
- * hex_dump_to_buffer() works on one "line" of output at a time, i.e.,
- * 16 or 32 bytes of input data converted to hex + ASCII output.
- *
- * Given a buffer of u8 data, hex_dump_to_buffer() converts the input data
- * to a hex + ASCII dump at the supplied memory location.
- * The converted output is always NUL-terminated.
- *
- * E.g.:
- * hex_dump_to_buffer(frame->data, frame->len, 16, 1,
- * linebuf, sizeof(linebuf), true);
- *
- * example output buffer:
- * 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO
- *
- * Return:
- * The amount of bytes placed in the buffer without terminating NUL. If the
- * output was truncated, then the return value is the number of bytes
- * (excluding the terminating NUL) which would have been written to the final
- * string if enough space had been available.
- */
int hex_dump_to_buffer(const void *buf, size_t len, int rowsize, int groupsize,
char *linebuf, size_t linebuflen, bool ascii)
{
@@ -59,8 +32,10 @@
int ascii_column;
int ret;
- if (rowsize != 16 && rowsize != 32)
+ if (!rowsize)
rowsize = 16;
+ else
+ rowsize = min(rowsize, MAX_LINE_LENGTH_BYTES);
if (len > rowsize) /* limit to one line at a time */
len = rowsize;
@@ -150,44 +125,17 @@
return ascii ? ascii_column + len : (groupsize * 2 + 1) * ngroups - 1;
}
-/**
- * print_hex_dump - print a text hex dump to syslog for a binary blob of data
- * @prefix_str: string to prefix each line with;
- * caller supplies trailing spaces for alignment if desired
- * @prefix_type: controls whether prefix of an offset, address, or none
- * is printed (%DUMP_PREFIX_OFFSET, %DUMP_PREFIX_ADDRESS, %DUMP_PREFIX_NONE)
- * @rowsize: number of bytes to print per line; must be 16 or 32
- * @groupsize: number of bytes to print at a time (1, 2, 4, 8; default = 1)
- * @buf: data blob to dump
- * @len: number of bytes in the @buf
- * @ascii: include ASCII after the hex output
- *
- * Given a buffer of u8 data, print_hex_dump() prints a hex + ASCII dump
- * to the stdio, with an optional leading prefix.
- *
- * print_hex_dump() works on one "line" of output at a time, i.e.,
- * 16 or 32 bytes of input data converted to hex + ASCII output.
- * print_hex_dump() iterates over the entire input @buf, breaking it into
- * "line size" chunks to format and print.
- *
- * E.g.:
- * print_hex_dump("raw data: ", DUMP_PREFIX_ADDRESS, 16, 1, frame->data,
- * frame->len, true);
- *
- * Example output using %DUMP_PREFIX_OFFSET and 1-byte mode:
- * 0009ab42: 40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f @ABCDEFGHIJKLMNO
- * Example output using %DUMP_PREFIX_ADDRESS and 4-byte mode:
- * ffffffff88089af0: 73727170 77767574 7b7a7978 7f7e7d7c pqrstuvwxyz{|}~.
- */
-void print_hex_dump(const char *prefix_str, int prefix_type, int rowsize,
- int groupsize, const void *buf, size_t len, bool ascii)
+int print_hex_dump(const char *prefix_str, int prefix_type, int rowsize,
+ int groupsize, const void *buf, size_t len, bool ascii)
{
const u8 *ptr = buf;
int i, linelen, remaining = len;
- char linebuf[32 * 3 + 2 + 32 + 1];
+ char linebuf[MAX_LINE_LENGTH_BYTES * 3 + 2 + MAX_LINE_LENGTH_BYTES + 1];
- if (rowsize != 16 && rowsize != 32)
+ if (!rowsize)
rowsize = 16;
+ else
+ rowsize = min(rowsize, MAX_LINE_LENGTH_BYTES);
for (i = 0; i < len; i += rowsize) {
linelen = min(remaining, rowsize);
@@ -198,7 +146,9 @@
switch (prefix_type) {
case DUMP_PREFIX_ADDRESS:
- printf("%s%p: %s\n", prefix_str, ptr + i, linebuf);
+ printf("%s%0*lx: %s\n", prefix_str,
+ IS_ENABLED(CONFIG_PHYS_64BIT) ? 16 : 8,
+ (ulong)map_to_sysmem(ptr) + i, linebuf);
break;
case DUMP_PREFIX_OFFSET:
printf("%s%.8x: %s\n", prefix_str, i, linebuf);
@@ -207,21 +157,13 @@
printf("%s%s\n", prefix_str, linebuf);
break;
}
+ if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc())
+ return -EINTR;
}
+
+ return 0;
}
-/**
- * print_hex_dump_bytes - shorthand form of print_hex_dump() with default params
- * @prefix_str: string to prefix each line with;
- * caller supplies trailing spaces for alignment if desired
- * @prefix_type: controls whether prefix of an offset, address, or none
- * is printed (%DUMP_PREFIX_OFFSET, %DUMP_PREFIX_ADDRESS, %DUMP_PREFIX_NONE)
- * @buf: data blob to dump
- * @len: number of bytes in the @buf
- *
- * Calls print_hex_dump(), rowsize of 16, groupsize of 1,
- * and ASCII output included.
- */
void print_hex_dump_bytes(const char *prefix_str, int prefix_type,
const void *buf, size_t len)
{
@@ -232,14 +174,14 @@
* Some code in U-Boot copy-pasted from Linux kernel uses both
* functions below so to keep stuff compilable we keep these stubs here.
*/
-void print_hex_dump(const char *prefix_str, int prefix_type,
- int rowsize, int groupsize, const void *buf,
- size_t len, bool ascii)
+int print_hex_dump(const char *prefix_str, int prefix_type, int rowsize,
+ int groupsize, const void *buf, size_t len, bool ascii)
{
+ return -ENOSYS;
}
void print_hex_dump_bytes(const char *prefix_str, int prefix_type,
- const void *buf, size_t len)
+ const void *buf, size_t len)
{
}
#endif /* CONFIG_HEXDUMP */
diff --git a/lib/image-sparse.c b/lib/image-sparse.c
index 187ac28..d80fdbb 100644
--- a/lib/image-sparse.c
+++ b/lib/image-sparse.c
@@ -55,10 +55,10 @@
lbaint_t blk;
lbaint_t blkcnt;
lbaint_t blks;
- uint32_t bytes_written = 0;
+ uint64_t bytes_written = 0;
unsigned int chunk;
unsigned int offset;
- unsigned int chunk_data_sz;
+ uint64_t chunk_data_sz;
uint32_t *fill_buf = NULL;
uint32_t fill_val;
sparse_header_t *sparse_header;
@@ -132,8 +132,8 @@
sizeof(chunk_header_t));
}
- chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
- blkcnt = chunk_data_sz / info->blksz;
+ chunk_data_sz = ((u64)sparse_header->blk_sz) * chunk_header->chunk_sz;
+ blkcnt = DIV_ROUND_UP_ULL(chunk_data_sz, info->blksz);
switch (chunk_header->chunk_type) {
case CHUNK_TYPE_RAW:
if (chunk_header->total_sz !=
@@ -162,7 +162,7 @@
return -1;
}
blk += blks;
- bytes_written += blkcnt * info->blksz;
+ bytes_written += ((u64)blkcnt) * info->blksz;
total_blocks += chunk_header->chunk_sz;
data += chunk_data_sz;
break;
@@ -222,8 +222,9 @@
blk += blks;
i += j;
}
- bytes_written += blkcnt * info->blksz;
- total_blocks += chunk_data_sz / sparse_header->blk_sz;
+ bytes_written += ((u64)blkcnt) * info->blksz;
+ total_blocks += DIV_ROUND_UP_ULL(chunk_data_sz,
+ sparse_header->blk_sz);
free(fill_buf);
break;
@@ -253,7 +254,7 @@
debug("Wrote %d blocks, expected to write %d blocks\n",
total_blocks, sparse_header->total_blks);
- printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name);
+ printf("........ wrote %llu bytes to '%s'\n", bytes_written, part_name);
if (total_blocks != sparse_header->total_blks) {
info->mssg("sparse image write failure", response);
diff --git a/lib/lmb.c b/lib/lmb.c
index c08c4d9..7bd1255 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -14,28 +14,32 @@
#define LMB_ALLOC_ANYWHERE 0
-void lmb_dump_all_force(struct lmb *lmb)
+static void lmb_dump_region(struct lmb_region *rgn, char *name)
{
- unsigned long i;
+ unsigned long long base, size, end;
+ enum lmb_flags flags;
+ int i;
- printf("lmb_dump_all:\n");
- printf(" memory.cnt = 0x%lx\n", lmb->memory.cnt);
- for (i = 0; i < lmb->memory.cnt; i++) {
- printf(" memory.reg[0x%lx].base = 0x%llx\n", i,
- (unsigned long long)lmb->memory.region[i].base);
- printf(" .size = 0x%llx\n",
- (unsigned long long)lmb->memory.region[i].size);
- }
+ printf(" %s.cnt = 0x%lx\n", name, rgn->cnt);
- printf("\n reserved.cnt = 0x%lx\n", lmb->reserved.cnt);
- for (i = 0; i < lmb->reserved.cnt; i++) {
- printf(" reserved.reg[0x%lx].base = 0x%llx\n", i,
- (unsigned long long)lmb->reserved.region[i].base);
- printf(" .size = 0x%llx\n",
- (unsigned long long)lmb->reserved.region[i].size);
+ for (i = 0; i < rgn->cnt; i++) {
+ base = rgn->region[i].base;
+ size = rgn->region[i].size;
+ end = base + size - 1;
+ flags = rgn->region[i].flags;
+
+ printf(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x\n",
+ name, i, base, end, size, flags);
}
}
+void lmb_dump_all_force(struct lmb *lmb)
+{
+ printf("lmb_dump_all:\n");
+ lmb_dump_region(&lmb->memory, "memory");
+ lmb_dump_region(&lmb->reserved, "reserved");
+}
+
void lmb_dump_all(struct lmb *lmb)
{
#ifdef DEBUG
@@ -81,6 +85,7 @@
for (i = r; i < rgn->cnt - 1; i++) {
rgn->region[i].base = rgn->region[i + 1].base;
rgn->region[i].size = rgn->region[i + 1].size;
+ rgn->region[i].flags = rgn->region[i + 1].flags;
}
rgn->cnt--;
}
@@ -144,7 +149,8 @@
}
/* This routine called with relocation disabled. */
-static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size)
+static long lmb_add_region_flags(struct lmb_region *rgn, phys_addr_t base,
+ phys_size_t size, enum lmb_flags flags)
{
unsigned long coalesced = 0;
long adjacent, i;
@@ -152,6 +158,7 @@
if (rgn->cnt == 0) {
rgn->region[0].base = base;
rgn->region[0].size = size;
+ rgn->region[0].flags = flags;
rgn->cnt = 1;
return 0;
}
@@ -160,18 +167,27 @@
for (i = 0; i < rgn->cnt; i++) {
phys_addr_t rgnbase = rgn->region[i].base;
phys_size_t rgnsize = rgn->region[i].size;
+ phys_size_t rgnflags = rgn->region[i].flags;
- if ((rgnbase == base) && (rgnsize == size))
- /* Already have this region, so we're done */
- return 0;
+ if (rgnbase == base && rgnsize == size) {
+ if (flags == rgnflags)
+ /* Already have this region, so we're done */
+ return 0;
+ else
+ return -1; /* regions with new flags */
+ }
adjacent = lmb_addrs_adjacent(base, size, rgnbase, rgnsize);
if (adjacent > 0) {
+ if (flags != rgnflags)
+ break;
rgn->region[i].base -= size;
rgn->region[i].size += size;
coalesced++;
break;
} else if (adjacent < 0) {
+ if (flags != rgnflags)
+ break;
rgn->region[i].size += size;
coalesced++;
break;
@@ -182,8 +198,10 @@
}
if ((i < rgn->cnt - 1) && lmb_regions_adjacent(rgn, i, i + 1)) {
- lmb_coalesce_regions(rgn, i, i + 1);
- coalesced++;
+ if (rgn->region[i].flags == rgn->region[i + 1].flags) {
+ lmb_coalesce_regions(rgn, i, i + 1);
+ coalesced++;
+ }
}
if (coalesced)
@@ -196,9 +214,11 @@
if (base < rgn->region[i].base) {
rgn->region[i + 1].base = rgn->region[i].base;
rgn->region[i + 1].size = rgn->region[i].size;
+ rgn->region[i + 1].flags = rgn->region[i].flags;
} else {
rgn->region[i + 1].base = base;
rgn->region[i + 1].size = size;
+ rgn->region[i + 1].flags = flags;
break;
}
}
@@ -206,6 +226,7 @@
if (base < rgn->region[0].base) {
rgn->region[0].base = base;
rgn->region[0].size = size;
+ rgn->region[0].flags = flags;
}
rgn->cnt++;
@@ -213,6 +234,12 @@
return 0;
}
+static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base,
+ phys_size_t size)
+{
+ return lmb_add_region_flags(rgn, base, size, LMB_NONE);
+}
+
/* This routine may be called with relocation disabled. */
long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size)
{
@@ -267,14 +294,21 @@
* beginging of the hole and add the region after hole.
*/
rgn->region[i].size = base - rgn->region[i].base;
- return lmb_add_region(rgn, end + 1, rgnend - end);
+ return lmb_add_region_flags(rgn, end + 1, rgnend - end,
+ rgn->region[i].flags);
}
-long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size)
+long lmb_reserve_flags(struct lmb *lmb, phys_addr_t base, phys_size_t size,
+ enum lmb_flags flags)
{
struct lmb_region *_rgn = &(lmb->reserved);
- return lmb_add_region(_rgn, base, size);
+ return lmb_add_region_flags(_rgn, base, size, flags);
+}
+
+long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size)
+{
+ return lmb_reserve_flags(lmb, base, size, LMB_NONE);
}
static long lmb_overlaps_region(struct lmb_region *rgn, phys_addr_t base,
@@ -409,7 +443,7 @@
return 0;
}
-int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
+int lmb_is_reserved_flags(struct lmb *lmb, phys_addr_t addr, int flags)
{
int i;
@@ -417,11 +451,16 @@
phys_addr_t upper = lmb->reserved.region[i].base +
lmb->reserved.region[i].size - 1;
if ((addr >= lmb->reserved.region[i].base) && (addr <= upper))
- return 1;
+ return (lmb->reserved.region[i].flags & flags) == flags;
}
return 0;
}
+int lmb_is_reserved(struct lmb *lmb, phys_addr_t addr)
+{
+ return lmb_is_reserved_flags(lmb, addr, LMB_NONE);
+}
+
__weak void board_lmb_reserve(struct lmb *lmb)
{
/* please define platform specific board_lmb_reserve() */
diff --git a/lib/rational.c b/lib/rational.c
new file mode 100644
index 0000000..316db3b
--- /dev/null
+++ b/lib/rational.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * rational fractions
+ *
+ * Copyright (C) 2009 emlix GmbH, Oskar Schirmer <oskar@scara.com>
+ * Copyright (C) 2019 Trent Piepho <tpiepho@gmail.com>
+ *
+ * helper functions when coping with rational numbers
+ */
+
+#include <linux/rational.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+
+/*
+ * calculate best rational approximation for a given fraction
+ * taking into account restricted register size, e.g. to find
+ * appropriate values for a pll with 5 bit denominator and
+ * 8 bit numerator register fields, trying to set up with a
+ * frequency ratio of 3.1415, one would say:
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+
+void rational_best_approximation(
+ unsigned long given_numerator, unsigned long given_denominator,
+ unsigned long max_numerator, unsigned long max_denominator,
+ unsigned long *best_numerator, unsigned long *best_denominator)
+{
+ /* n/d is the starting rational, which is continually
+ * decreased each iteration using the Euclidean algorithm.
+ *
+ * dp is the value of d from the prior iteration.
+ *
+ * n2/d2, n1/d1, and n0/d0 are our successively more accurate
+ * approximations of the rational. They are, respectively,
+ * the current, previous, and two prior iterations of it.
+ *
+ * a is current term of the continued fraction.
+ */
+ unsigned long n, d, n0, d0, n1, d1, n2, d2;
+ n = given_numerator;
+ d = given_denominator;
+ n0 = d1 = 0;
+ n1 = d0 = 1;
+
+ for (;;) {
+ unsigned long dp, a;
+
+ if (d == 0)
+ break;
+ /* Find next term in continued fraction, 'a', via
+ * Euclidean algorithm.
+ */
+ dp = d;
+ a = n / d;
+ d = n % d;
+ n = dp;
+
+ /* Calculate the current rational approximation (aka
+ * convergent), n2/d2, using the term just found and
+ * the two prior approximations.
+ */
+ n2 = n0 + a * n1;
+ d2 = d0 + a * d1;
+
+ /* If the current convergent exceeds the maxes, then
+ * return either the previous convergent or the
+ * largest semi-convergent, the final term of which is
+ * found below as 't'.
+ */
+ if ((n2 > max_numerator) || (d2 > max_denominator)) {
+ unsigned long t = min((max_numerator - n0) / n1,
+ (max_denominator - d0) / d1);
+
+ /* This tests if the semi-convergent is closer
+ * than the previous convergent.
+ */
+ if (2u * t > a || (2u * t == a && d0 * dp > d1 * d)) {
+ n1 = n0 + t * n1;
+ d1 = d0 + t * d1;
+ }
+ break;
+ }
+ n0 = n1;
+ n1 = n2;
+ d0 = d1;
+ d1 = d2;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
diff --git a/lib/string.c b/lib/string.c
index a0cff8f..ba176fb 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -16,6 +16,7 @@
*/
#include <config.h>
+#include <linux/compiler.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/ctype.h>
@@ -513,7 +514,7 @@
*
* Do not use memset() to access IO space, use memset_io() instead.
*/
-void * memset(void * s,int c,size_t count)
+__used void * memset(void * s,int c,size_t count)
{
unsigned long *sl = (unsigned long *) s;
char *s8;
@@ -552,7 +553,7 @@
* You should not use this function to access IO space, use memcpy_toio()
* or memcpy_fromio() instead.
*/
-void * memcpy(void *dest, const void *src, size_t count)
+__used void * memcpy(void *dest, const void *src, size_t count)
{
unsigned long *dl = (unsigned long *)dest, *sl = (unsigned long *)src;
char *d8, *s8;
@@ -586,7 +587,7 @@
*
* Unlike memcpy(), memmove() copes with overlapping areas.
*/
-void * memmove(void * dest,const void *src,size_t count)
+__used void * memmove(void * dest,const void *src,size_t count)
{
char *tmp, *s;
@@ -622,7 +623,7 @@
* @ct: Another area of memory
* @count: The size of the area.
*/
-int memcmp(const void * cs,const void * ct,size_t count)
+__used int memcmp(const void * cs,const void * ct,size_t count)
{
const unsigned char *su1, *su2;
int res = 0;
diff --git a/lib/trace.c b/lib/trace.c
index 9e34b19..505a318 100644
--- a/lib/trace.c
+++ b/lib/trace.c
@@ -13,8 +13,8 @@
DECLARE_GLOBAL_DATA_PTR;
-static char trace_enabled __attribute__((section(".data")));
-static char trace_inited __attribute__((section(".data")));
+static char trace_enabled __section(".data");
+static char trace_inited __section(".data");
/* The header block at the start of the trace memory area */
struct trace_hdr {
diff --git a/net/Kconfig b/net/Kconfig
index c4b4dae..ba0ca81 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -74,6 +74,17 @@
before an ack response is required.
The default TFTP implementation implies a window size of 1.
+config TFTP_TSIZE
+ bool "Track TFTP transfers based on file size option"
+ depends on CMD_TFTPBOOT
+ default y if (ARCH_OMAP2PLUS || ARCH_K3)
+ help
+ By default, TFTP progress bar is increased for each received UDP
+ frame, which can lead into long time being spent for sending
+ data over the UART. Enabling this option, TFTP queries the file
+ size from server, and if supported, limits the progress bar to
+ 50 characters total which fits on single line.
+
config SERVERIP_FROM_PROXYDHCP
bool "Get serverip value from Proxy DHCP response"
help
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index 705a886..7e59ca5 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -331,12 +331,11 @@
# Rule to compile a set of .o files into one .o file
#
ifdef builtin-target
-quiet_cmd_link_o_target = LD $@
+quiet_cmd_link_o_target = AR $@
# If the list of objects to link is empty, just create an empty built-in.o
cmd_link_o_target = $(if $(strip $(obj-y)),\
- $(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \
- $(cmd_secanalysis),\
- rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@)
+ rm -f $@; $(AR) cDPrsT $@ $(filter $(obj-y), $^), \
+ rm -f $@; $(AR) cDPrsT$(KBUILD_ARFLAGS) $@)
$(builtin-target): $(obj-y) FORCE
$(call if_changed,link_o_target)
@@ -362,7 +361,7 @@
#
ifdef lib-target
quiet_cmd_link_l_target = AR $@
-cmd_link_l_target = rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@ $(lib-y)
+cmd_link_l_target = rm -f $@; $(AR) cDPrsT$(KBUILD_ARFLAGS) $@ $(lib-y)
$(lib-target): $(lib-y) FORCE
$(call if_changed,link_l_target)
@@ -382,10 +381,11 @@
$($(subst $(obj)/,,$(@:.o=-objs))) \
$($(subst $(obj)/,,$(@:.o=-y)))), $^)
-quiet_cmd_link_multi-y = LD $@
-cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) $(cmd_secanalysis)
+
+quiet_cmd_link_multi-y = AR $@
+cmd_link_multi-y = rm -f $@; $(AR) cDPrsT$(KBUILD_ARFLAGS) $@ $(link_multi_deps)
-quiet_cmd_link_multi-m = LD [M] $@
+quiet_cmd_link_multi-m = AR [M] $@
cmd_link_multi-m = $(cmd_link_multi-y)
$(multi-used-y): FORCE
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 78543c6..78bbebe 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -419,6 +419,9 @@
targets += $(obj)/efi_crt0.o $(obj)/efi_reloc.o $(obj)/efi_freestanding.o
+CFLAGS_REMOVE_efi_reloc.o := $(LTO_CFLAGS)
+CFLAGS_REMOVE_efi_freestanding.o := $(LTO_CFLAGS)
+
# ACPI
# ---------------------------------------------------------------------------
#
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index c69525f..5be1a9b 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -399,6 +399,8 @@
# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
LDFLAGS_$(SPL_BIN) += $(call ld-option, --no-dynamic-linker)
+LDFLAGS_$(SPL_BIN) += --build-id=none
+
# Pick the best-match (i.e. SPL_TEXT_BASE for SPL, TPL_TEXT_BASE for TPL)
ifneq ($(CONFIG_$(SPL_TPL_)TEXT_BASE),)
LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(SPL_TPL_)TEXT_BASE)
@@ -448,18 +450,65 @@
$(obj)/$(SPL_BIN).sym: $(obj)/$(SPL_BIN) FORCE
$(call if_changed,sym)
+# Generate linker list symbols references to force compiler to not optimize
+# them away when compiling with LTO
+ifdef CONFIG_LTO
+u-boot-spl-keep-syms-lto := $(obj)/keep-syms-lto.o
+u-boot-spl-keep-syms-lto_c := \
+ $(patsubst $(obj)/%.o,$(obj)/%.c,$(u-boot-spl-keep-syms-lto))
+
+quiet_cmd_keep_syms_lto = KSL $@
+ cmd_keep_syms_lto = \
+ NM=$(NM) $(srctree)/scripts/gen_ll_addressable_symbols.sh $^ >$@
+
+quiet_cmd_keep_syms_lto_cc = KSLCC $@
+ cmd_keep_syms_lto_cc = \
+ $(CC) $(filter-out $(LTO_CFLAGS),$(c_flags)) -c -o $@ $<
+
+$(u-boot-spl-keep-syms-lto_c): $(u-boot-spl-main) $(u-boot-spl-platdata)
+ $(call if_changed,keep_syms_lto)
+$(u-boot-spl-keep-syms-lto): $(u-boot-spl-keep-syms-lto_c)
+ $(call if_changed,keep_syms_lto_cc)
+else
+u-boot-spl-keep-syms-lto :=
+endif
+
# Rule to link u-boot-spl
# May be overridden by arch/$(ARCH)/config.mk
+ifdef CONFIG_LTO
+quiet_cmd_u-boot-spl ?= LTO $@
+ cmd_u-boot-spl ?= \
+ ( \
+ cd $(obj) && \
+ $(CC) -nostdlib -nostartfiles $(LTO_FINAL_LDFLAGS) $(c_flags) \
+ $(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_$(@F):%=-Wl,%) \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-init)) \
+ -Wl,--whole-archive \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-keep-syms-lto)) \
+ $(PLATFORM_LIBS) \
+ -Wl,--no-whole-archive \
+ -Wl,-Map,$(SPL_BIN).map -o $(SPL_BIN) \
+ )
+else
quiet_cmd_u-boot-spl ?= LD $@
- cmd_u-boot-spl ?= (cd $(obj) && $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_$(@F)) \
- $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \
- $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \
- $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) \
- --end-group \
- $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN))
+ cmd_u-boot-spl ?= \
+ ( \
+ cd $(obj) && \
+ $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_$(@F)) \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-init)) \
+ --whole-archive \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \
+ $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) \
+ --no-whole-archive \
+ $(PLATFORM_LIBS) -Map $(SPL_BIN).map -o $(SPL_BIN) \
+ )
+endif
$(obj)/$(SPL_BIN): $(u-boot-spl-platdata) $(u-boot-spl-init) \
- $(u-boot-spl-main) $(obj)/u-boot-spl.lds FORCE
+ $(u-boot-spl-main) $(u-boot-spl-keep-syms-lto) \
+ $(obj)/u-boot-spl.lds FORCE
$(call if_changed,u-boot-spl)
$(sort $(u-boot-spl-init) $(u-boot-spl-main)): $(u-boot-spl-dirs) ;
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 4e04758..08a8275 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -2326,13 +2326,15 @@
# suffix: Suffix to expect on member, e.g. "_priv"
# warning: Warning name, e.g. "PRIV_AUTO"
sub u_boot_struct_name {
- my ($line, $auto, $suffix, $warning) = @_;
+ my ($line, $auto, $suffix, $warning, $herecurr) = @_;
# Use _priv as a suffix for the device-private data struct
if ($line =~ /^\+\s*\.${auto}\s*=\s*sizeof\(struct\((\w+)\).*/) {
my $struct_name = $1;
if ($struct_name !~ /^\w+${suffix}/) {
- WARN($warning, "struct \'$struct_name\' should have a ${suffix} suffix");
+ WARN($warning,
+ "struct \'$struct_name\' should have a ${suffix} suffix\n"
+ . $herecurr);
}
}
}
@@ -2410,17 +2412,17 @@
}
# Check struct names for the 'auto' members of struct driver
- u_boot_struct_name($line, "priv_auto", "_priv", "PRIV_AUTO");
- u_boot_struct_name($line, "plat_auto", "_plat", "PLAT_AUTO");
- u_boot_struct_name($line, "per_child_auto", "_priv", "CHILD_PRIV_AUTO");
+ u_boot_struct_name($line, "priv_auto", "_priv", "PRIV_AUTO", $herecurr);
+ u_boot_struct_name($line, "plat_auto", "_plat", "PLAT_AUTO", $herecurr);
+ u_boot_struct_name($line, "per_child_auto", "_priv", "CHILD_PRIV_AUTO", $herecurr);
u_boot_struct_name($line, "per_child_plat_auto", "_plat",
- "CHILD_PLAT_AUTO");
+ "CHILD_PLAT_AUTO", $herecurr);
# Now the ones for struct uclass, skipping those in common with above
u_boot_struct_name($line, "per_device_auto", "_priv",
- "DEVICE_PRIV_AUTO");
+ "DEVICE_PRIV_AUTO", $herecurr);
u_boot_struct_name($line, "per_device_plat_auto", "_plat",
- "DEVICE_PLAT_AUTO");
+ "DEVICE_PLAT_AUTO", $herecurr);
}
sub process {
@@ -6071,7 +6073,7 @@
my $old = substr($rawline, $-[1], $+[1] - $-[1]);
my $new = substr($old, 1, -1);
if (WARN("PREFER_SECTION",
- "__section($new) is preferred over __attribute__((section($old)))\n" . $herecurr) &&
+ "__section(\"$new\") is preferred over __attribute__((section($old)))\n" . $herecurr) &&
$fix) {
$fixed[$fixlinenr] =~ s/\b__attribute__\s*\(\s*\(\s*_*section_*\s*\(\s*\Q$old\E\s*\)\s*\)\s*\)/__section($new)/;
}
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 3eda10e..0f5ac8f 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -48,7 +48,6 @@
CONFIG_ARMV7_SECURE_RESERVE_SIZE
CONFIG_ARMV8_SWITCH_TO_EL1
CONFIG_ARM_ARCH_CP15_ERRATA
-CONFIG_ARM_FREQ
CONFIG_ARM_GIC_BASE_ADDRESS
CONFIG_ARM_PL180_MMCI_BASE
CONFIG_ARM_PL180_MMCI_CLOCK_FREQ
@@ -108,14 +107,12 @@
CONFIG_BOARD_IS_OPENRD_ULTIMATE
CONFIG_BOARD_NAME
CONFIG_BOARD_POSTCLK_INIT
-CONFIG_BOARD_REVISION_TAG
CONFIG_BOARD_SIZE_LIMIT
CONFIG_BOOGER
CONFIG_BOOTBLOCK
CONFIG_BOOTFILE
CONFIG_BOOTMODE
CONFIG_BOOTP_
-CONFIG_BOOTP_BOOTFILE
CONFIG_BOOTP_BOOTFILESIZE
CONFIG_BOOTP_DHCP_REQUEST_DELAY
CONFIG_BOOTP_ID_CACHE_SIZE
@@ -130,7 +127,6 @@
CONFIG_BOOTSCRIPT_COPY_RAM
CONFIG_BOOTSCRIPT_HDR_ADDR
CONFIG_BOOTSCRIPT_KEY_HASH
-CONFIG_BOOT_DIR
CONFIG_BOOT_MODE_BIT
CONFIG_BOOT_OS_NET
CONFIG_BOOT_PARAMS_ADDR
@@ -171,8 +167,6 @@
CONFIG_CHIP_SELECT_QUAD_CAPABLE
CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
CONFIG_CI_UDC_HAS_HOSTPC
-CONFIG_CLK0_DIV
-CONFIG_CLK0_EN
CONFIG_CLK_1000_200_200
CONFIG_CLK_1000_330_165
CONFIG_CLK_1000_400_200
@@ -195,10 +189,6 @@
CONFIG_COLDFIRE
CONFIG_COMMANDS
CONFIG_COMMON_BOOT
-CONFIG_COMMON_ENV_MISC
-CONFIG_COMMON_ENV_SETTINGS
-CONFIG_COMMON_ENV_UBI
-CONFIG_COMPACT_FLASH
CONFIG_COMPAT
CONFIG_CONS_EXTC_PINSEL
CONFIG_CONS_EXTC_RATE
@@ -208,7 +198,6 @@
CONFIG_CONS_SCIF1
CONFIG_CONS_SCIF2
CONFIG_CONS_SCIF4
-CONFIG_CONTROLCENTERD
CONFIG_CON_ROT
CONFIG_CORTINA_FW_ADDR
CONFIG_CORTINA_FW_LENGTH
@@ -279,7 +268,6 @@
CONFIG_DEFAULT
CONFIG_DEFAULT_IMMR
CONFIG_DESIGNWARE_ETH
-CONFIG_DEVELOP
CONFIG_DEVICE_TREE_LIST
CONFIG_DFU_ALT
CONFIG_DFU_ALT_BOOT_EMMC
@@ -312,8 +300,6 @@
CONFIG_DRIVER_AT91EMAC_QUIET
CONFIG_DRIVER_DM9000
CONFIG_DRIVER_EP93XX_MAC
-CONFIG_DRIVER_NE2000
-CONFIG_DRIVER_NE2000_BASE
CONFIG_DSP_CLUSTER_START
CONFIG_DWC2_DFLT_SPEED_FULL
CONFIG_DWC2_DMA_BURST_SIZE
@@ -346,7 +332,6 @@
CONFIG_DW_UDC
CONFIG_DW_WDT_BASE
CONFIG_DW_WDT_CLOCK_KHZ
-CONFIG_DYNAMIC_MMC_DEVNO
CONFIG_E1000_NO_NVM
CONFIG_E300
CONFIG_E5500
@@ -395,7 +380,6 @@
CONFIG_ENV_MIN_ENTRIES
CONFIG_ENV_OFFSET_OOB
CONFIG_ENV_RANGE
-CONFIG_ENV_RDADDR
CONFIG_ENV_REFLASH
CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS
CONFIG_ENV_SETTINGS_NAND_V1
@@ -436,7 +420,6 @@
CONFIG_ETHPRIME
CONFIG_ETH_BUFSIZE
CONFIG_ETH_RXSIZE
-CONFIG_EXTRA_BOOTARGS
CONFIG_EXTRA_CLOCK
CONFIG_EXTRA_ENV
CONFIG_EXTRA_ENV_BOARD_SETTINGS
@@ -491,13 +474,10 @@
CONFIG_FEROCEON
CONFIG_FEROCEON_88FR131
CONFIG_FILE
-CONFIG_FIRMWARE_OFFSET
-CONFIG_FIRMWARE_SIZE
CONFIG_FIXED_PHY
CONFIG_FIXED_PHY_ADDR
CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
CONFIG_FLASHBOOTCOMMAND
-CONFIG_FLASHCARD
CONFIG_FLASH_BR_PRELIM
CONFIG_FLASH_CFI_LEGACY
CONFIG_FLASH_OR_PRELIM
@@ -606,7 +586,6 @@
CONFIG_G_DNL_THOR_VENDOR_NUM
CONFIG_G_DNL_UMS_PRODUCT_NUM
CONFIG_G_DNL_UMS_VENDOR_NUM
-CONFIG_H264_FREQ
CONFIG_HAS_ETH0
CONFIG_HAS_ETH1
CONFIG_HAS_ETH2
@@ -614,7 +593,6 @@
CONFIG_HAS_FEC
CONFIG_HAS_FSL_DR_USB
CONFIG_HAS_FSL_MPH_USB
-CONFIG_HCLK_FREQ
CONFIG_HDBOOT
CONFIG_HDMI_ENCODER_I2C_ADDR
CONFIG_HETROGENOUS_CLUSTERS
@@ -766,8 +744,6 @@
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL
CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA
CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP
-CONFIG_HRCON_DH
-CONFIG_HRCON_FANS
CONFIG_HSMMC2_8BIT
CONFIG_HUSH_INIT_VAR
CONFIG_HVBOOT
@@ -804,7 +780,6 @@
CONFIG_IMX6_PWM_PER_CLK
CONFIG_IMX_HDMI
CONFIG_IMX_NAND
-CONFIG_IMX_OTP
CONFIG_IMX_VIDEO_SKIP
CONFIG_INETSPACE_V2
CONFIG_INITRD_TAG
@@ -842,7 +817,6 @@
CONFIG_JTAG_CONSOLE
CONFIG_KCLK_DIS
CONFIG_KEEP_SERVERADDR
-CONFIG_KERNEL_OFFSET
CONFIG_KEYBOARD
CONFIG_KEYSTONE_NAND_MAX_RBL_PAGE
CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE
@@ -886,9 +860,6 @@
CONFIG_KM_UBI_PART_BOOT_OPTS
CONFIG_KM_UIMAGE_NAME
CONFIG_KM_UPDATE_UBOOT
-CONFIG_KONA
-CONFIG_KONA_GPIO
-CONFIG_KONA_RESET_S
CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE
CONFIG_KSNAV_NETCP_PDMA_RX_BASE
CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM
@@ -950,7 +921,6 @@
CONFIG_LITTLETON_LCD
CONFIG_LMS283GF05
CONFIG_LOADADDR
-CONFIG_LOADCMD
CONFIG_LOADS_ECHO
CONFIG_LOWPOWER_ADDR
CONFIG_LOWPOWER_FLAG
@@ -1053,8 +1023,6 @@
CONFIG_MPC85XX_FEC_NAME
CONFIG_MPC85XX_PCI2
CONFIG_MPC8xxx_DISABLE_BPTR
-CONFIG_MPLL_FREQ
-CONFIG_MSHC_FREQ
CONFIG_MTD_CONCAT
CONFIG_MTD_ECC_SOFT
CONFIG_MTD_NAND_MUSEUM_IDS
@@ -1089,11 +1057,8 @@
CONFIG_MX35
CONFIG_MX35_CLK32
CONFIG_MX35_HCLK_FREQ
-CONFIG_MX6DL_LPDDR2
-CONFIG_MX6DQ_LPDDR2
CONFIG_MXC_EPDC
CONFIG_MXC_GPT_HCLK
-CONFIG_MXC_MCI_REGS_BASE
CONFIG_MXC_NAND_HWECC
CONFIG_MXC_NAND_IP_REGS_BASE
CONFIG_MXC_NAND_REGS_BASE
@@ -1143,7 +1108,6 @@
CONFIG_NET_MULTI
CONFIG_NET_RETRY_COUNT
CONFIG_NEVER_ASSERT_ODT_TO_CPU
-CONFIG_NFC_FREQ
CONFIG_NFSBOOTCOMMAND
CONFIG_NFS_TIMEOUT
CONFIG_NOBQFMAN
@@ -1153,7 +1117,6 @@
CONFIG_NO_ETH
CONFIG_NO_RELOCATION
CONFIG_NO_WAIT
-CONFIG_NR_DRAM_POPULATED
CONFIG_NS16550_MIN_FUNCTIONS
CONFIG_NS8382X
CONFIG_NUM_DSP_CPUS
@@ -1222,10 +1185,6 @@
CONFIG_PCI_SYS_PHYS
CONFIG_PCI_SYS_SIZE
CONFIG_PEN_ADDR_BIG_ENDIAN
-CONFIG_PERIF1_FREQ
-CONFIG_PERIF2_FREQ
-CONFIG_PERIF3_FREQ
-CONFIG_PERIF4_FREQ
CONFIG_PHYSMEM
CONFIG_PHY_BASE_ADR
CONFIG_PHY_BCM5421S
@@ -1241,9 +1200,6 @@
CONFIG_PL011_SERIAL_RLCR
CONFIG_PL01x_PORTS
CONFIG_PLATFORM_ENV_SETTINGS
-CONFIG_PLATINUM_BOARD
-CONFIG_PLATINUM_CPU
-CONFIG_PLATINUM_PROJECT
CONFIG_PM
CONFIG_PMC_BR_PRELIM
CONFIG_PMC_OR_PRELIM
@@ -1269,7 +1225,6 @@
CONFIG_POWER_I2C
CONFIG_POWER_LTC3676
CONFIG_POWER_LTC3676_I2C_ADDR
-CONFIG_POWER_MAX77696
CONFIG_POWER_MAX77696_I2C_ADDR
CONFIG_POWER_PFUZE100
CONFIG_POWER_PFUZE100_I2C_ADDR
@@ -1307,7 +1262,6 @@
CONFIG_PXA_VGA
CONFIG_PXA_VIDEO
CONFIG_QBMAN_CLK_DIV
-CONFIG_QEMU_MIPS
CONFIG_QIXIS_I2C_ACCESS
CONFIG_QSPI
CONFIG_QUOTA
@@ -1343,7 +1297,6 @@
CONFIG_RESTORE_FLASH
CONFIG_RES_BLOCK_SIZE
CONFIG_REVISION_TAG
-CONFIG_RFSPART
CONFIG_RIO
CONFIG_RMII
CONFIG_RMSTP0_ENA
@@ -1363,7 +1316,6 @@
CONFIG_ROCKCHIP_SDHCI_MAX_FREQ
CONFIG_ROCKCHIP_STIMER_BASE
CONFIG_ROM_STUBS
-CONFIG_ROOTFS_OFFSET
CONFIG_ROOTPATH
CONFIG_RTC_DS1337
CONFIG_RTC_DS1337_NOOSC
@@ -1380,11 +1332,7 @@
CONFIG_RTC_MCP79411
CONFIG_RTC_MXS
CONFIG_RTC_PT7C4338
-CONFIG_RUN_FROM_DDR0
-CONFIG_RUN_FROM_DDR1
-CONFIG_RUN_FROM_IRAM_ONLY
CONFIG_RX_DESCR_NUM
-CONFIG_S32V234
CONFIG_S5P
CONFIG_S5PC100
CONFIG_S5PC110
@@ -1417,7 +1365,6 @@
CONFIG_SECURE_BL1_ONLY
CONFIG_SECURE_RUNTIME_RESV_SRAM_SZ
CONFIG_SECURITY
-CONFIG_SEC_DEQ_TIMEOUT
CONFIG_SEC_FW_SIZE
CONFIG_SERIAL_BOOT
CONFIG_SERIAL_FLASH
@@ -1536,7 +1483,6 @@
CONFIG_SPI_HALF_DUPLEX
CONFIG_SPI_IDLE_VAL
CONFIG_SPI_N25Q256A_RESET
-CONFIG_SPLL_FREQ
CONFIG_SPL_
CONFIG_SPL_ATMEL_SIZE
CONFIG_SPL_BOARD_LOAD_IMAGE
@@ -1603,8 +1549,6 @@
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS
CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE
CONFIG_SSE2
-CONFIG_SSI1_FREQ
-CONFIG_SSI2_FREQ
CONFIG_SSP1_BASE
CONFIG_SSP2_BASE
CONFIG_SSP3_BASE
@@ -1613,28 +1557,20 @@
CONFIG_STATIC_BOARD_REV
CONFIG_STD_DEVICES_SETTINGS
CONFIG_STM32_FLASH
-CONFIG_STRIDER_CON
-CONFIG_STRIDER_CON_DP
-CONFIG_STRIDER_CPU
-CONFIG_STRIDER_CPU_DP
-CONFIG_STRIDER_FANS
CONFIG_STV0991
CONFIG_STV0991_HZ
CONFIG_STV0991_HZ_CLOCK
CONFIG_ST_SMI
CONFIG_SXNI855T
-CONFIG_SYSFLAGS_ADDR
CONFIG_SYSFS
CONFIG_SYSMGR_ISWGRP_HANDOFF
CONFIG_SYS_33MHZ
CONFIG_SYS_64BIT
CONFIG_SYS_64BIT_LBA
-CONFIG_SYS_64BIT_VSPRINTF
CONFIG_SYS_66MHZ
CONFIG_SYS_8313ERDB_BROKEN_PMC
CONFIG_SYS_83XX_DDR_USES_CS0
CONFIG_SYS_ADDRESS_MAP_A
-CONFIG_SYS_ADV7611_I2C
CONFIG_SYS_ALT_BOOT
CONFIG_SYS_ALT_FLASH
CONFIG_SYS_AMASK0
@@ -1687,7 +1623,6 @@
CONFIG_SYS_BFTIC3_SIZE
CONFIG_SYS_BITBANG_PHY_PORT
CONFIG_SYS_BITBANG_PHY_PORTS
-CONFIG_SYS_BLACK_IN_WRITE
CONFIG_SYS_BMAN_CENA_BASE
CONFIG_SYS_BMAN_CENA_SIZE
CONFIG_SYS_BMAN_CINH_BASE
@@ -1700,7 +1635,6 @@
CONFIG_SYS_BMAN_SP_CINH_SIZE
CONFIG_SYS_BMAN_SWP_ISDR_REG
CONFIG_SYS_BOARD_NAME
-CONFIG_SYS_BOARD_OMAP3_HA
CONFIG_SYS_BOOK3E_HV
CONFIG_SYS_BOOTCOUNT_BE
CONFIG_SYS_BOOTCOUNT_LE
@@ -1742,7 +1676,6 @@
CONFIG_SYS_CCSR_DO_NOT_RELOCATE
CONFIG_SYS_CFI_FLASH_CONFIG_REGS
CONFIG_SYS_CFI_FLASH_STATUS_POLL
-CONFIG_SYS_CF_BASE
CONFIG_SYS_CF_INTC_REG1
CONFIG_SYS_CH7301_I2C
CONFIG_SYS_CKEN
@@ -2055,8 +1988,6 @@
CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
CONFIG_SYS_DEFAULT_VIDEO_MODE
CONFIG_SYS_DEF_EEPROM_ADDR
-CONFIG_SYS_DFU_DATA_BUF_SIZE
-CONFIG_SYS_DFU_MAX_FILE_SIZE
CONFIG_SYS_DIAG_ADDR
CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
CONFIG_SYS_DIMM_SLOTS_PER_CTLR
@@ -2094,8 +2025,6 @@
CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
CONFIG_SYS_EEPROM_WREN
CONFIG_SYS_EHCI_USB1_ADDR
-CONFIG_SYS_ELBC_BASE
-CONFIG_SYS_ELBC_BASE_PHYS
CONFIG_SYS_ELO3_DMA3
CONFIG_SYS_EMAC_TI_CLKDIV
CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -2225,12 +2154,10 @@
CONFIG_SYS_FPGA_FTIM1
CONFIG_SYS_FPGA_FTIM2
CONFIG_SYS_FPGA_FTIM3
-CONFIG_SYS_FPGA_IS_PROTO
CONFIG_SYS_FPGA_NO_RFL_HI
CONFIG_SYS_FPGA_PROG
CONFIG_SYS_FPGA_PROG_FEEDBACK
CONFIG_SYS_FPGA_PROG_TIME
-CONFIG_SYS_FPGA_PTR
CONFIG_SYS_FPGA_SIZE
CONFIG_SYS_FPGA_WAIT
CONFIG_SYS_FPGA_WAIT_BUSY
@@ -2565,9 +2492,6 @@
CONFIG_SYS_I2C_0
CONFIG_SYS_I2C_2
CONFIG_SYS_I2C_5
-CONFIG_SYS_I2C_8574A_ADDR1
-CONFIG_SYS_I2C_8574A_ADDR2
-CONFIG_SYS_I2C_8574_ADDR1
CONFIG_SYS_I2C_8574_ADDR2
CONFIG_SYS_I2C_BASE
CONFIG_SYS_I2C_BASE0
@@ -2592,17 +2516,12 @@
CONFIG_SYS_I2C_FPGA_ADDR
CONFIG_SYS_I2C_FRAM
CONFIG_SYS_I2C_G762_ADDR
-CONFIG_SYS_I2C_GENERIC_MAC
CONFIG_SYS_I2C_IDT6V49205B
CONFIG_SYS_I2C_IFDR_DIV
CONFIG_SYS_I2C_IHS_CH0
-CONFIG_SYS_I2C_IHS_CH0_1
CONFIG_SYS_I2C_IHS_CH1
-CONFIG_SYS_I2C_IHS_CH1_1
CONFIG_SYS_I2C_IHS_CH2
-CONFIG_SYS_I2C_IHS_CH2_1
CONFIG_SYS_I2C_IHS_CH3
-CONFIG_SYS_I2C_IHS_CH3_1
CONFIG_SYS_I2C_IHS_DUAL
CONFIG_SYS_I2C_IHS_SLAVE_0
CONFIG_SYS_I2C_IHS_SLAVE_0_1
@@ -2621,7 +2540,6 @@
CONFIG_SYS_I2C_IHS_SPEED_3
CONFIG_SYS_I2C_IHS_SPEED_3_1
CONFIG_SYS_I2C_INIT_BOARD
-CONFIG_SYS_I2C_KONA
CONFIG_SYS_I2C_LDI_ADDR
CONFIG_SYS_I2C_LM75_ADDR
CONFIG_SYS_I2C_LM90_ADDR
@@ -2767,7 +2685,6 @@
CONFIG_SYS_ISA_MEM
CONFIG_SYS_JFFS2_FIRST_BANK
CONFIG_SYS_JFFS2_FIRST_SECTOR
-CONFIG_SYS_JFFS2_MEM_NAND
CONFIG_SYS_JFFS2_NUM_BANKS
CONFIG_SYS_JFFS2_SORT_FRAGMENTS
CONFIG_SYS_KMBEC_FPGA_BASE
@@ -2784,10 +2701,6 @@
CONFIG_SYS_LBAPP2_BASE_PHYS
CONFIG_SYS_LBAPP2_BR_PRELIM
CONFIG_SYS_LBAPP2_OR_PRELIM
-CONFIG_SYS_LBC0_BASE
-CONFIG_SYS_LBC0_BASE_PHYS
-CONFIG_SYS_LBC1_BASE
-CONFIG_SYS_LBC1_BASE_PHYS
CONFIG_SYS_LBC_ADDR
CONFIG_SYS_LBC_CACHE_BASE
CONFIG_SYS_LBC_FLASH_BASE
@@ -2811,7 +2724,6 @@
CONFIG_SYS_LB_SDRAM
CONFIG_SYS_LCD_BASE
CONFIG_SYS_LDB_CLOCK
-CONFIG_SYS_LED_BASE
CONFIG_SYS_LED_DISP_BASE
CONFIG_SYS_LIME_BASE
CONFIG_SYS_LIME_SIZE
@@ -2844,7 +2756,6 @@
CONFIG_SYS_MACB2_BASE
CONFIG_SYS_MACB3_BASE
CONFIG_SYS_MAIN_PWR_ON
-CONFIG_SYS_MALLOC_BASE
CONFIG_SYS_MALLOC_SIMPLE
CONFIG_SYS_MAMR
CONFIG_SYS_MAPLE
@@ -2859,7 +2770,6 @@
CONFIG_SYS_MAX_FLASH_BANKS_DETECT
CONFIG_SYS_MAX_FLASH_SECT
CONFIG_SYS_MAX_I2C_BUS
-CONFIG_SYS_MAX_MTD_BANKS
CONFIG_SYS_MAX_NAND_CHIPS
CONFIG_SYS_MAX_NAND_DEVICE
CONFIG_SYS_MAX_PCI_EPS
@@ -2877,7 +2787,6 @@
CONFIG_SYS_MCKR2_VAL
CONFIG_SYS_MCKR_CSS
CONFIG_SYS_MCKR_VAL
-CONFIG_SYS_MCLINK_MAX
CONFIG_SYS_MCMEM0_VAL
CONFIG_SYS_MCMEM1_VAL
CONFIG_SYS_MDCNFG_VAL
@@ -2937,7 +2846,6 @@
CONFIG_SYS_MPC85xx_ESDHC_OFFSET
CONFIG_SYS_MPC85xx_ESPI_ADDR
CONFIG_SYS_MPC85xx_ESPI_OFFSET
-CONFIG_SYS_MPC85xx_GPIO3_ADDR
CONFIG_SYS_MPC85xx_GPIO_ADDR
CONFIG_SYS_MPC85xx_GPIO_OFFSET
CONFIG_SYS_MPC85xx_GUTS_ADDR
@@ -3137,7 +3045,6 @@
CONFIG_SYS_OR_TIMING_MRAM
CONFIG_SYS_OSCIN_FREQ
CONFIG_SYS_OSD_DH
-CONFIG_SYS_OSD_SCREENS
CONFIG_SYS_OSPR_OFFSET
CONFIG_SYS_PACNT
CONFIG_SYS_PADAT
@@ -3695,7 +3602,6 @@
CONFIG_SYS_USB_EHCI_CPU_INIT
CONFIG_SYS_USB_EHCI_REGS_BASE
CONFIG_SYS_USB_FAT_BOOT_PARTITION
-CONFIG_SYS_USB_HOST
CONFIG_SYS_USB_OHCI_BOARD_INIT
CONFIG_SYS_USB_OHCI_CPU_INIT
CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
@@ -3788,7 +3694,6 @@
CONFIG_TPL_PAD_TO
CONFIG_TPM_TIS_BASE_ADDRESS
CONFIG_TPS6586X_POWER
-CONFIG_TRAILBLAZER
CONFIG_TRATS
CONFIG_TSEC
CONFIG_TSEC1
@@ -3803,12 +3708,9 @@
CONFIG_TSECV2_1
CONFIG_TSEC_TBI
CONFIG_TSEC_TBICR_SETTINGS
-CONFIG_TWL6030_INPUT
CONFIG_TWL6030_POWER
CONFIG_TX_DESCR_NUM
CONFIG_TZSW_RESERVED_DRAM_SIZE
-CONFIG_UART_BR_PRELIM
-CONFIG_UART_OR_PRELIM
CONFIG_UBIBLOCK
CONFIG_UBIFS_VOLUME
CONFIG_UBI_PART
@@ -3838,13 +3740,11 @@
CONFIG_USART1
CONFIG_USART_BASE
CONFIG_USART_ID
-CONFIG_USBBOOTCOMMAND
CONFIG_USBD_CONFIGURATION_STR
CONFIG_USBD_CTRL_INTERFACE_STR
CONFIG_USBD_DATA_INTERFACE_STR
CONFIG_USBD_HS
CONFIG_USBD_MANUFACTURER
-CONFIG_USBD_PRODUCTID
CONFIG_USBD_PRODUCTID_CDCACM
CONFIG_USBD_PRODUCTID_GSERIAL
CONFIG_USBD_PRODUCT_NAME
@@ -3857,7 +3757,6 @@
CONFIG_USBD_SERIAL_OUT_ENDPOINT
CONFIG_USBD_SERIAL_OUT_PKTSIZE
CONFIG_USBD_VENDORID
-CONFIG_USBID_ADDR
CONFIG_USBNET_DEV_ADDR
CONFIG_USBTTY
CONFIG_USB_ATMEL
@@ -3882,7 +3781,6 @@
CONFIG_USB_ETH_SUBSET
CONFIG_USB_EXT2_BOOT
CONFIG_USB_FAT_BOOT
-CONFIG_USB_FREQ
CONFIG_USB_GADGET_AMD5536UDC
CONFIG_USB_GADGET_AT91
CONFIG_USB_GADGET_DUMMY_HCD
@@ -3913,7 +3811,6 @@
CONFIG_USB_OTG_BLACKLIST_HUB
CONFIG_USB_PHY_TYPE
CONFIG_USB_PXA25X_SMALL
-CONFIG_USB_SERIALNO
CONFIG_USB_TI_CPPI_DMA
CONFIG_USB_TTY
CONFIG_USB_TUSB_OMAP_DMA
@@ -3923,14 +3820,12 @@
CONFIG_USER_LOWLEVEL_INIT
CONFIG_USE_INTERRUPT
CONFIG_USE_ONENAND_BOARD_INIT
-CONFIG_USE_SPIFLASH
CONFIG_UTBIPAR_INIT_TBIPA
CONFIG_U_BOOT_HDR_ADDR
CONFIG_U_BOOT_HDR_SIZE
CONFIG_VAL
CONFIG_VAR_SIZE_SPL
CONFIG_VERY_BIG_RAM
-CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP
CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
CONFIG_VIDEO_BCM2835
CONFIG_VIDEO_BMP_LOGO
diff --git a/scripts/dtc/pylibfdt/libfdt.i_shipped b/scripts/dtc/pylibfdt/libfdt.i_shipped
index 1d69ad3..27c29ea 100644
--- a/scripts/dtc/pylibfdt/libfdt.i_shipped
+++ b/scripts/dtc/pylibfdt/libfdt.i_shipped
@@ -1010,7 +1010,7 @@
}
$1 = (void *)PyByteArray_AsString($input);
fdt = $1;
- fdt = fdt; /* avoid unused variable warning */
+ (void)fdt; /* avoid unused variable warning */
}
/* Some functions do change the device tree, so use void * */
@@ -1021,7 +1021,7 @@
}
$1 = PyByteArray_AsString($input);
fdt = $1;
- fdt = fdt; /* avoid unused variable warning */
+ (void)fdt; /* avoid unused variable warning */
}
/* typemap used for fdt_get_property_by_offset() */
diff --git a/scripts/gen_ll_addressable_symbols.sh b/scripts/gen_ll_addressable_symbols.sh
new file mode 100755
index 0000000..3978a39
--- /dev/null
+++ b/scripts/gen_ll_addressable_symbols.sh
@@ -0,0 +1,12 @@
+#!/bin/bash
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (C) 2020 Marek Behún <marek.behun@nic.cz>
+
+# Generate __ADDRESSABLE(symbol) for every linker list entry symbol, so that LTO
+# does not optimize these symbols away
+
+set -e
+
+echo '#include <common.h>'
+$NM "$@" 2>/dev/null | grep -oe '_u_boot_list_2_[a-zA-Z0-9_]*_2_[a-zA-Z0-9_]*' | \
+ sort -u | sed -e 's/^\(.*\)/extern char \1[];\n__ADDRESSABLE(\1);/'
diff --git a/test/cmd/mem_search.c b/test/cmd/mem_search.c
index 9494279..f80c9c4 100644
--- a/test/cmd/mem_search.c
+++ b/test/cmd/mem_search.c
@@ -30,9 +30,9 @@
buf[0x100] = 0x12;
ut_assertok(console_record_reset_enable());
run_command("ms.b 1 ff 12", 0);
- ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
+ ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
ut_assert_nextline("--");
- ut_assert_nextline("000000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 ................");
+ ut_assert_nextline("000000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 12 ................");
ut_assert_nextline("2 matches");
ut_assert_console_end();
@@ -57,7 +57,7 @@
buf[BUF_SIZE / 2] = 0x1234;
ut_assertok(console_record_reset_enable());
run_command("ms.w 0 80 1234", 0);
- ut_assert_nextline("00000030: 0000 0000 1234 0000 0000 0000 0000 0000 ....4...........");
+ ut_assert_nextline("00000030: 0000 0000 1234 0000 0000 0000 0000 0000 ....4...........");
ut_assert_nextline("1 match");
ut_assert_console_end();
@@ -82,7 +82,7 @@
buf[BUF_SIZE / 4] = 0x12345678;
ut_assertok(console_record_reset_enable());
run_command("ms 0 40 12345678", 0);
- ut_assert_nextline("00000030: 00000000 00000000 12345678 00000000 ........xV4.....");
+ ut_assert_nextline("00000030: 00000000 00000000 12345678 00000000 ........xV4.....");
ut_assert_nextline("1 match");
ut_assert_console_end();
@@ -212,10 +212,10 @@
strcpy(buf + BUF_SIZE - strlen(str) + 1, str);
ut_assertok(console_record_reset_enable());
run_command("ms.b 0 100 68 65 6c 6c 6f", 0);
- ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he");
- ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo.............");
+ ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he");
+ ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo.............");
ut_assert_nextline("--");
- ut_assert_nextline("00000060: 00 00 00 68 65 6c 6c 6f 00 00 00 00 00 00 00 00 ...hello........");
+ ut_assert_nextline("00000060: 00 00 00 68 65 6c 6c 6f 00 00 00 00 00 00 00 00 ...hello........");
ut_assert_nextline("2 matches");
ut_assert_console_end();
unmap_sysmem(buf);
@@ -242,12 +242,12 @@
strcpy(buf + 0xa1, str2);
ut_assertok(console_record_reset_enable());
run_command("ms.s 0 100 hello", 0);
- ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he");
- ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo.............");
+ ut_assert_nextline("00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 68 65 ..............he");
+ ut_assert_nextline("00000020: 6c 6c 6f 00 00 00 00 00 00 00 00 00 00 00 00 00 llo.............");
ut_assert_nextline("--");
- ut_assert_nextline("00000060: 00 00 00 68 65 6c 6c 6f 00 00 00 00 00 00 00 00 ...hello........");
+ ut_assert_nextline("00000060: 00 00 00 68 65 6c 6c 6f 00 00 00 00 00 00 00 00 ...hello........");
ut_assert_nextline("--");
- ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere.....");
+ ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere.....");
ut_assert_nextline("3 matches");
ut_assert_console_end();
@@ -257,7 +257,7 @@
ut_assertok(console_record_reset_enable());
run_command("ms.s 0 100 hello there", 0);
- ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere.....");
+ ut_assert_nextline("000000a0: 00 68 65 6c 6c 6f 74 68 65 72 65 00 00 00 00 00 .hellothere.....");
ut_assert_nextline("1 match");
ut_assert_console_end();
@@ -284,7 +284,7 @@
buf[0x76] = 0x12;
ut_assertok(console_record_reset_enable());
run_command("ms.b -l2 1 ff 12", 0);
- ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
+ ut_assert_nextline("00000030: 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................");
ut_assert_nextline("--");
ut_assert_nextlinen("00000060: 00 00 12 00 00 00 00 00 00 00 00 00 00 00 00 00");
ut_assert_nextline("2 matches (repeat command to check for more)");
diff --git a/test/cmd_ut.c b/test/cmd_ut.c
index b9c1660..6f174c6 100644
--- a/test/cmd_ut.c
+++ b/test/cmd_ut.c
@@ -51,6 +51,7 @@
U_BOOT_CMD_MKENT(setexpr, CONFIG_SYS_MAXARGS, 1, do_ut_setexpr, "",
""),
#endif
+ U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_ut_print, "", ""),
#ifdef CONFIG_UT_TIME
U_BOOT_CMD_MKENT(time, CONFIG_SYS_MAXARGS, 1, do_ut_time, "", ""),
#endif
@@ -132,6 +133,7 @@
#ifdef CONFIG_UT_OVERLAY
"ut overlay [test-name]\n"
#endif
+ "ut print [test-name] - test printing\n"
"ut setexpr [test-name] - test setexpr command\n"
#ifdef CONFIG_SANDBOX
"ut str - Basic test of string functions\n"
diff --git a/test/dm/Makefile b/test/dm/Makefile
index e7cb1ee..c964461 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -96,6 +96,7 @@
obj-y += syscon.o
obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o
obj-$(CONFIG_SYSINFO) += sysinfo.o
+obj-$(CONFIG_SYSINFO_GPIO) += sysinfo-gpio.o
obj-$(CONFIG_TEE) += tee.o
obj-$(CONFIG_TIMER) += timer.o
obj-$(CONFIG_DM_USB) += usb.o
diff --git a/test/dm/ofnode.c b/test/dm/ofnode.c
index c539134..e0b525e 100644
--- a/test/dm/ofnode.c
+++ b/test/dm/ofnode.c
@@ -261,3 +261,34 @@
return 0;
}
DM_TEST(dm_test_ofnode_is_enabled, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int dm_test_ofnode_get_reg(struct unit_test_state *uts)
+{
+ ofnode node;
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ node = ofnode_path("/translation-test@8000");
+ ut_assert(ofnode_valid(node));
+ addr = ofnode_get_addr(node);
+ size = ofnode_get_size(node);
+ ut_asserteq(0x8000, addr);
+ ut_asserteq(0x4000, size);
+
+ node = ofnode_path("/translation-test@8000/dev@1,100");
+ ut_assert(ofnode_valid(node));
+ addr = ofnode_get_addr(node);
+ size = ofnode_get_size(node);
+ ut_asserteq(0x9000, addr);
+ ut_asserteq(0x1000, size);
+
+ node = ofnode_path("/emul-mux-controller");
+ ut_assert(ofnode_valid(node));
+ addr = ofnode_get_addr(node);
+ size = ofnode_get_size(node);
+ ut_asserteq(FDT_ADDR_T_NONE, addr);
+ ut_asserteq(FDT_SIZE_T_NONE, size);
+
+ return 0;
+}
+DM_TEST(dm_test_ofnode_get_reg, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/dm/part.c b/test/dm/part.c
index 051e901..78dd847 100644
--- a/test/dm/part.c
+++ b/test/dm/part.c
@@ -11,11 +11,25 @@
#include <dm/test.h>
#include <test/ut.h>
+static inline int do_test(struct unit_test_state *uts, int expected,
+ const char *part_str, bool whole)
+{
+ struct blk_desc *mmc_dev_desc;
+ struct disk_partition part_info;
+
+ ut_asserteq(expected,
+ part_get_info_by_dev_and_name_or_num("mmc", part_str,
+ &mmc_dev_desc,
+ &part_info, whole));
+ return 0;
+}
+
static int dm_test_part(struct unit_test_state *uts)
{
+ char *oldbootdevice;
char str_disk_guid[UUID_STR_LEN + 1];
+ int ret;
struct blk_desc *mmc_dev_desc;
- struct disk_partition part_info;
struct disk_partition parts[2] = {
{
.start = 48, /* GPT data takes up the first 34 blocks or so */
@@ -38,16 +52,22 @@
ut_assertok(gpt_restore(mmc_dev_desc, str_disk_guid, parts,
ARRAY_SIZE(parts)));
-#define test(expected, part_str, whole) \
- ut_asserteq(expected, \
- part_get_info_by_dev_and_name_or_num("mmc", part_str, \
- &mmc_dev_desc, \
- &part_info, whole))
+ oldbootdevice = env_get("bootdevice");
+#define test(expected, part_str, whole) do { \
+ ret = do_test(uts, expected, part_str, whole); \
+ if (ret) \
+ goto out; \
+} while (0)
+
+ env_set("bootdevice", NULL);
+ test(-ENODEV, NULL, true);
test(-ENODEV, "", true);
env_set("bootdevice", "0");
+ test(0, NULL, true);
test(0, "", true);
env_set("bootdevice", "1");
+ test(1, NULL, false);
test(1, "", false);
test(1, "-", false);
env_set("bootdevice", "");
@@ -70,7 +90,10 @@
test(-EINVAL, "1#bogus", false);
test(1, "1#test1", false);
test(2, "1#test2", false);
+ ret = 0;
- return 0;
+out:
+ env_set("bootdevice", oldbootdevice);
+ return ret;
}
DM_TEST(dm_test_part, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/dm/regmap.c b/test/dm/regmap.c
index 372a73c..04bb164 100644
--- a/test/dm/regmap.c
+++ b/test/dm/regmap.c
@@ -306,9 +306,8 @@
&dev));
priv = dev_get_priv(dev);
- srand(get_ticks() + rand());
for (i = 0; i < REGMAP_TEST_BUF_SZ; i++) {
- pattern[i] = rand();
+ pattern[i] = i * 0x87654321;
ut_assertok(regmap_write(priv->cfg_regmap, i, pattern[i]));
}
for (i = 0; i < REGMAP_TEST_BUF_SZ; i++) {
diff --git a/test/dm/reset.c b/test/dm/reset.c
index fc8e925..9c00452 100644
--- a/test/dm/reset.c
+++ b/test/dm/reset.c
@@ -24,18 +24,47 @@
static int dm_test_reset_base(struct unit_test_state *uts)
{
struct udevice *dev;
- struct reset_ctl reset_method1;
- struct reset_ctl reset_method2;
+ struct reset_ctl reset_method1, reset_method1_1;
+ struct reset_ctl reset_method2, reset_method2_1;
+ struct reset_ctl reset_method3, reset_method3_1;
+ struct reset_ctl reset_method4, reset_method4_1;
/* Get the device using the reset device */
ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
&dev));
/* Get the same reset port in 2 different ways and compare */
- ut_assertok(reset_get_by_index(dev, 1, &reset_method1));
+ ut_assertok(reset_get_by_index(dev, 0, &reset_method1));
+ ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 0,
+ &reset_method1_1));
+ ut_assertok(reset_get_by_index(dev, 1, &reset_method2));
ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 1,
- &reset_method2));
- ut_asserteq(reset_method1.id, reset_method2.id);
+ &reset_method2_1));
+ ut_assertok(reset_get_by_index(dev, 2, &reset_method3));
+ ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 2,
+ &reset_method3_1));
+ ut_assertok(reset_get_by_index(dev, 3, &reset_method4));
+ ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 3,
+ &reset_method4_1));
+
+ ut_asserteq(reset_method1.id, reset_method1_1.id);
+ ut_asserteq(reset_method2.id, reset_method2_1.id);
+ ut_asserteq(reset_method3.id, reset_method3_1.id);
+ ut_asserteq(reset_method4.id, reset_method4_1.id);
+
+ ut_asserteq(true, reset_method1.id != reset_method2.id);
+ ut_asserteq(true, reset_method1.id != reset_method3.id);
+ ut_asserteq(true, reset_method1.id != reset_method4.id);
+ ut_asserteq(true, reset_method2.id != reset_method3.id);
+ ut_asserteq(true, reset_method2.id != reset_method4.id);
+ ut_asserteq(true, reset_method3.id != reset_method4.id);
+
+ ut_asserteq(true, reset_method1_1.id != reset_method2_1.id);
+ ut_asserteq(true, reset_method1_1.id != reset_method3_1.id);
+ ut_asserteq(true, reset_method1_1.id != reset_method4_1.id);
+ ut_asserteq(true, reset_method2_1.id != reset_method3_1.id);
+ ut_asserteq(true, reset_method2_1.id != reset_method4_1.id);
+ ut_asserteq(true, reset_method3_1.id != reset_method4_1.id);
return 0;
}
diff --git a/test/dm/rtc.c b/test/dm/rtc.c
index 8ab997c..c7f9f8f 100644
--- a/test/dm/rtc.c
+++ b/test/dm/rtc.c
@@ -204,7 +204,7 @@
ut_assert_console_end();
run_command("rtc read 0x30 2", 0);
- ut_assert_nextline("00000030: aa bb ..");
+ ut_assert_nextline("00000030: aa bb ..");
ut_assert_console_end();
run_command("rtc dev 1", 0);
@@ -215,7 +215,7 @@
ut_assert_console_end();
run_command("rtc read 0x30 2", 0);
- ut_assert_nextline("00000030: cc dd ..");
+ ut_assert_nextline("00000030: cc dd ..");
ut_assert_console_end();
/*
@@ -227,7 +227,7 @@
ut_assert_console_end();
run_command("rtc read 0x30 2", 0);
- ut_assert_nextline("00000030: aa bb ..");
+ ut_assert_nextline("00000030: aa bb ..");
ut_assert_console_end();
return 0;
diff --git a/test/dm/sysinfo-gpio.c b/test/dm/sysinfo-gpio.c
new file mode 100644
index 0000000..2e494b3
--- /dev/null
+++ b/test/dm/sysinfo-gpio.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Sean Anderson <sean.anderson@seco.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <sysinfo.h>
+#include <asm/gpio.h>
+#include <dm/test.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static int dm_test_sysinfo_gpio(struct unit_test_state *uts)
+{
+ char buf[64];
+ int val;
+ struct udevice *sysinfo, *gpio;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_SYSINFO, "sysinfo-gpio",
+ &sysinfo));
+ ut_assertok(uclass_get_device_by_name(UCLASS_GPIO, "base-gpios", &gpio));
+
+ /*
+ * Set up pins: pull-up (1), pull-down (0) and floating (2). This should
+ * result in digits 2 0 1, i.e. 2 * 9 + 1 * 3 = 19
+ */
+ sandbox_gpio_set_flags(gpio, 15, GPIOD_EXT_PULL_UP);
+ sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_DOWN);
+ sandbox_gpio_set_flags(gpio, 17, 0);
+ ut_assertok(sysinfo_detect(sysinfo));
+ ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val));
+ ut_asserteq(19, val);
+ ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf),
+ buf));
+ ut_asserteq_str("rev_a", buf);
+
+ /*
+ * Set up pins: floating (2), pull-up (1) and pull-down (0). This should
+ * result in digits 0 1 2, i.e. 1 * 3 + 2 = 5
+ */
+ sandbox_gpio_set_flags(gpio, 15, 0);
+ sandbox_gpio_set_flags(gpio, 16, GPIOD_EXT_PULL_UP);
+ sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_DOWN);
+ ut_assertok(sysinfo_detect(sysinfo));
+ ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val));
+ ut_asserteq(5, val);
+ ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf),
+ buf));
+ ut_asserteq_str("foo", buf);
+
+ /*
+ * Set up pins: floating (2), pull-up (1) and pull-down (0). This should
+ * result in digits 1 2 0, i.e. 1 * 9 + 2 * 3 = 15
+ */
+ sandbox_gpio_set_flags(gpio, 15, GPIOD_EXT_PULL_DOWN);
+ sandbox_gpio_set_flags(gpio, 16, 0);
+ sandbox_gpio_set_flags(gpio, 17, GPIOD_EXT_PULL_UP);
+ ut_assertok(sysinfo_detect(sysinfo));
+ ut_assertok(sysinfo_get_int(sysinfo, SYSINFO_ID_BOARD_MODEL, &val));
+ ut_asserteq(15, val);
+ ut_assertok(sysinfo_get_str(sysinfo, SYSINFO_ID_BOARD_MODEL, sizeof(buf),
+ buf));
+ ut_asserteq_str("unknown", buf);
+
+ return 0;
+}
+DM_TEST(dm_test_sysinfo_gpio, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/dm/sysinfo.c b/test/dm/sysinfo.c
index 4aaa9e8..96b3a8e 100644
--- a/test/dm/sysinfo.c
+++ b/test/dm/sysinfo.c
@@ -17,40 +17,45 @@
static int dm_test_sysinfo(struct unit_test_state *uts)
{
struct udevice *sysinfo;
- bool called_detect;
+ bool called_detect = false;
char str[64];
int i;
ut_assertok(sysinfo_get(&sysinfo));
ut_assert(sysinfo);
- sysinfo_get_bool(sysinfo, BOOL_CALLED_DETECT, &called_detect);
+ ut_asserteq(-EPERM, sysinfo_get_bool(sysinfo, BOOL_CALLED_DETECT,
+ &called_detect));
ut_assert(!called_detect);
sysinfo_detect(sysinfo);
- sysinfo_get_bool(sysinfo, BOOL_CALLED_DETECT, &called_detect);
+ ut_assertok(sysinfo_get_bool(sysinfo, BOOL_CALLED_DETECT,
+ &called_detect));
ut_assert(called_detect);
- sysinfo_get_str(sysinfo, STR_VACATIONSPOT, sizeof(str), str);
+ ut_assertok(sysinfo_get_str(sysinfo, STR_VACATIONSPOT, sizeof(str),
+ str));
ut_assertok(strcmp(str, "R'lyeh"));
- sysinfo_get_int(sysinfo, INT_TEST1, &i);
+ ut_assertok(sysinfo_get_int(sysinfo, INT_TEST1, &i));
ut_asserteq(0, i);
- sysinfo_get_int(sysinfo, INT_TEST2, &i);
+ ut_assertok(sysinfo_get_int(sysinfo, INT_TEST2, &i));
ut_asserteq(100, i);
- sysinfo_get_str(sysinfo, STR_VACATIONSPOT, sizeof(str), str);
+ ut_assertok(sysinfo_get_str(sysinfo, STR_VACATIONSPOT, sizeof(str),
+ str));
ut_assertok(strcmp(str, "Carcosa"));
- sysinfo_get_int(sysinfo, INT_TEST1, &i);
+ ut_assertok(sysinfo_get_int(sysinfo, INT_TEST1, &i));
ut_asserteq(1, i);
- sysinfo_get_int(sysinfo, INT_TEST2, &i);
+ ut_assertok(sysinfo_get_int(sysinfo, INT_TEST2, &i));
ut_asserteq(99, i);
- sysinfo_get_str(sysinfo, STR_VACATIONSPOT, sizeof(str), str);
+ ut_assertok(sysinfo_get_str(sysinfo, STR_VACATIONSPOT, sizeof(str),
+ str));
ut_assertok(strcmp(str, "Yuggoth"));
return 0;
diff --git a/test/dm/test-fdt.c b/test/dm/test-fdt.c
index 6552d09..d273e21 100644
--- a/test/dm/test-fdt.c
+++ b/test/dm/test-fdt.c
@@ -5,7 +5,6 @@
#include <common.h>
#include <dm.h>
-#include <dm/device_compat.h>
#include <errno.h>
#include <fdtdec.h>
#include <log.h>
@@ -20,6 +19,7 @@
#include <dm/util.h>
#include <dm/lists.h>
#include <dm/of_access.h>
+#include <linux/ioport.h>
#include <test/test.h>
#include <test/ut.h>
@@ -551,64 +551,6 @@
.id = UCLASS_TEST_DUMMY,
};
-static int zero_size_cells_bus_bind(struct udevice *dev)
-{
- ofnode child;
- int err;
-
- ofnode_for_each_subnode(child, dev_ofnode(dev)) {
- if (ofnode_get_property(child, "compatible", NULL))
- continue;
-
- err = device_bind_driver_to_node(dev,
- "zero_size_cells_bus_child_drv",
- "zero_size_cells_bus_child",
- child, NULL);
- if (err) {
- dev_err(dev, "%s: failed to bind %s\n", __func__,
- ofnode_get_name(child));
- return err;
- }
- }
-
- return 0;
-}
-
-static const struct udevice_id zero_size_cells_bus_ids[] = {
- { .compatible = "sandbox,zero-size-cells-bus" },
- { }
-};
-
-U_BOOT_DRIVER(zero_size_cells_bus) = {
- .name = "zero_size_cells_bus_drv",
- .id = UCLASS_TEST_DUMMY,
- .of_match = zero_size_cells_bus_ids,
- .bind = zero_size_cells_bus_bind,
-};
-
-static int zero_size_cells_bus_child_bind(struct udevice *dev)
-{
- ofnode child;
- int err;
-
- ofnode_for_each_subnode(child, dev_ofnode(dev)) {
- err = lists_bind_fdt(dev, child, NULL, false);
- if (err) {
- dev_err(dev, "%s: lists_bind_fdt, err=%d\n",
- __func__, err);
- return err;
- }
- }
-
- return 0;
-}
-
-U_BOOT_DRIVER(zero_size_cells_bus_child_drv) = {
- .name = "zero_size_cells_bus_child_drv",
- .id = UCLASS_TEST_DUMMY,
- .bind = zero_size_cells_bus_child_bind,
-};
-
static int dm_test_fdt_translation(struct unit_test_state *uts)
{
struct udevice *dev;
@@ -630,17 +572,8 @@
/* No translation for busses with #size-cells == 0 */
ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 3, &dev));
ut_asserteq_str("dev@42", dev->name);
- /* No translation for busses with #size-cells == 0 */
ut_asserteq(0x42, dev_read_addr(dev));
- /* Translation for busses with #size-cells == 0 */
- gd->dm_flags |= GD_DM_FLG_SIZE_CELLS_0;
- ut_asserteq(0x8042, dev_read_addr(dev));
- ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 4, &dev));
- ut_asserteq_str("dev@19", dev->name);
- ut_asserteq(0xc019, dev_read_addr(dev));
- gd->dm_flags &= ~GD_DM_FLG_SIZE_CELLS_0;
-
/* dma address translation */
ut_assertok(uclass_find_device_by_seq(UCLASS_TEST_DUMMY, 0, &dev));
dma_addr[0] = cpu_to_be32(0);
@@ -1233,3 +1166,35 @@
return 0;
}
DM_TEST(dm_test_decode_display_timing, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+/* Test read_resourcee() */
+static int dm_test_read_resource(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct resource res;
+
+ /* test resource without translation */
+ ut_assertok(uclass_find_device_by_name(UCLASS_SIMPLE_BUS, "syscon@2", &dev));
+ ut_assertok(dev_read_resource(dev, 0, &res));
+ ut_asserteq(0x40, res.start);
+ ut_asserteq(0x44, res.end);
+ ut_assertok(dev_read_resource(dev, 1, &res));
+ ut_asserteq(0x48, res.start);
+ ut_asserteq(0x4d, res.end);
+
+ /* test resource with translation */
+ ut_assertok(uclass_find_device_by_name(UCLASS_TEST_DUMMY, "dev@1,100", &dev));
+ ut_assertok(dev_read_resource(dev, 0, &res));
+ ut_asserteq(0x9000, res.start);
+ ut_asserteq(0x9fff, res.end);
+
+ /* test named resource */
+ ut_assertok(uclass_find_device_by_name(UCLASS_TEST_DUMMY, "dev@0,0", &dev));
+ ut_assertok(dev_read_resource_byname(dev, "sandbox-dummy-0", &res));
+ ut_asserteq(0x8000, res.start);
+ ut_asserteq(0x8fff, res.end);
+
+ return 0;
+}
+
+DM_TEST(dm_test_read_resource, UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/env/Makefile b/test/env/Makefile
index 5c8eae3..9a98fd4 100644
--- a/test/env/Makefile
+++ b/test/env/Makefile
@@ -5,3 +5,4 @@
obj-y += cmd_ut_env.o
obj-y += attr.o
obj-y += hashtable.o
+obj-$(CONFIG_ENV_IMPORT_FDT) += fdt.o
diff --git a/test/env/fdt.c b/test/env/fdt.c
new file mode 100644
index 0000000..30bfa88
--- /dev/null
+++ b/test/env/fdt.c
@@ -0,0 +1,20 @@
+#include <common.h>
+#include <command.h>
+#include <env_attr.h>
+#include <test/env.h>
+#include <test/ut.h>
+
+static int env_test_fdt_import(struct unit_test_state *uts)
+{
+ const char *val;
+
+ val = env_get("from_fdt");
+ ut_assertnonnull(val);
+ ut_asserteq_str("yes", val);
+
+ val = env_get("fdt_env_path");
+ ut_assertnull(val);
+
+ return 0;
+}
+ENV_TEST(env_test_fdt_import, 0);
diff --git a/test/lib/lmb.c b/test/lib/lmb.c
index 0d8963f..b2c2b99 100644
--- a/test/lib/lmb.c
+++ b/test/lib/lmb.c
@@ -723,3 +723,92 @@
DM_TEST(lib_test_lmb_max_regions,
UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
+
+static int lib_test_lmb_flags(struct unit_test_state *uts)
+{
+ const phys_addr_t ram = 0x40000000;
+ const phys_size_t ram_size = 0x20000000;
+ struct lmb lmb;
+ long ret;
+
+ lmb_init(&lmb);
+
+ ret = lmb_add(&lmb, ram, ram_size);
+ ut_asserteq(ret, 0);
+
+ /* reserve, same flag */
+ ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000,
+ 0, 0, 0, 0);
+
+ /* reserve again, same flag */
+ ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NOMAP);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000,
+ 0, 0, 0, 0);
+
+ /* reserve again, new flag */
+ ret = lmb_reserve_flags(&lmb, 0x40010000, 0x10000, LMB_NONE);
+ ut_asserteq(ret, -1);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x10000,
+ 0, 0, 0, 0);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+
+ /* merge after */
+ ret = lmb_reserve_flags(&lmb, 0x40020000, 0x10000, LMB_NOMAP);
+ ut_asserteq(ret, 1);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40010000, 0x20000,
+ 0, 0, 0, 0);
+
+ /* merge before */
+ ret = lmb_reserve_flags(&lmb, 0x40000000, 0x10000, LMB_NOMAP);
+ ut_asserteq(ret, 1);
+ ASSERT_LMB(&lmb, ram, ram_size, 1, 0x40000000, 0x30000,
+ 0, 0, 0, 0);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+
+ ret = lmb_reserve_flags(&lmb, 0x40030000, 0x10000, LMB_NONE);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000,
+ 0x40030000, 0x10000, 0, 0);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0);
+
+ /* test that old API use LMB_NONE */
+ ret = lmb_reserve(&lmb, 0x40040000, 0x10000);
+ ut_asserteq(ret, 1);
+ ASSERT_LMB(&lmb, ram, ram_size, 2, 0x40000000, 0x30000,
+ 0x40030000, 0x20000, 0, 0);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0);
+
+ ret = lmb_reserve_flags(&lmb, 0x40070000, 0x10000, LMB_NOMAP);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000,
+ 0x40030000, 0x20000, 0x40070000, 0x10000);
+
+ ret = lmb_reserve_flags(&lmb, 0x40050000, 0x10000, LMB_NOMAP);
+ ut_asserteq(ret, 0);
+ ASSERT_LMB(&lmb, ram, ram_size, 4, 0x40000000, 0x30000,
+ 0x40030000, 0x20000, 0x40050000, 0x10000);
+
+ /* merge with 2 adjacent regions */
+ ret = lmb_reserve_flags(&lmb, 0x40060000, 0x10000, LMB_NOMAP);
+ ut_asserteq(ret, 2);
+ ASSERT_LMB(&lmb, ram, ram_size, 3, 0x40000000, 0x30000,
+ 0x40030000, 0x20000, 0x40050000, 0x30000);
+
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[0]), 1);
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[1]), 0);
+ ut_asserteq(lmb_is_nomap(&lmb.reserved.region[2]), 1);
+
+ return 0;
+}
+
+DM_TEST(lib_test_lmb_flags,
+ UT_TESTF_SCAN_PDATA | UT_TESTF_SCAN_FDT);
diff --git a/test/log/Makefile b/test/log/Makefile
index a3dedac..08eea70 100644
--- a/test/log/Makefile
+++ b/test/log/Makefile
@@ -17,8 +17,10 @@
ifdef CONFIG_LOG
obj-y += pr_cont_test.o
obj-$(CONFIG_CONSOLE_RECORD) += cont_test.o
+obj-y += pr_cont_test.o
else
obj-$(CONFIG_CONSOLE_RECORD) += nolog_test.o
+obj-$(CONFIG_CONSOLE_RECORD) += nolog_ndebug.o
endif
endif # CONFIG_UT_LOG
diff --git a/test/log/log_test.c b/test/log/log_test.c
index 4a814ff..f1e6750 100644
--- a/test/log/log_test.c
+++ b/test/log/log_test.c
@@ -429,3 +429,30 @@
return 0;
}
LOG_TEST_FLAGS(log_test_dropped, UT_TESTF_CONSOLE_REC);
+
+/* Check log_buffer() */
+int log_test_buffer(struct unit_test_state *uts)
+{
+ u8 *buf;
+ int i;
+
+ buf = malloc(0x20);
+ ut_assertnonnull(buf);
+ memset(buf, '\0', 0x20);
+ for (i = 0; i < 0x11; i++)
+ buf[i] = i * 0x11;
+
+ ut_assertok(console_record_reset_enable());
+ log_buffer(LOGC_BOOT, LOGL_INFO, 0, buf, 1, 0x12, 0);
+
+ /* This one should product no output due to the debug level */
+ log_buffer(LOGC_BOOT, LOGL_DEBUG, 0, buf, 1, 0x12, 0);
+
+ ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
+ ut_assert_nextline("00000010: 10 00 ..");
+ ut_assert_console_end();
+ free(buf);
+
+ return 0;
+}
+LOG_TEST_FLAGS(log_test_buffer, UT_TESTF_CONSOLE_REC);
diff --git a/test/log/nolog_ndebug.c b/test/log/nolog_ndebug.c
new file mode 100644
index 0000000..bd9a4f4
--- /dev/null
+++ b/test/log/nolog_ndebug.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ *
+ * Logging function tests for CONFIG_LOG=n without #define DEBUG
+ */
+
+#include <common.h>
+#include <console.h>
+#include <log.h>
+#include <asm/global_data.h>
+#include <test/log.h>
+#include <test/ut.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define BUFFSIZE 32
+
+static int log_test_log_disabled_ndebug(struct unit_test_state *uts)
+{
+ char buf[BUFFSIZE];
+ int i;
+
+ memset(buf, 0, BUFFSIZE);
+ console_record_reset_enable();
+
+ /* Output a log record at every level */
+ for (i = LOGL_EMERG; i < LOGL_COUNT; i++)
+ log(LOGC_NONE, i, "testing level %i\n", i);
+ gd->flags &= ~GD_FLG_RECORD;
+
+ /* Since DEBUG is not defined, we expect to not get debug output */
+ for (i = LOGL_EMERG; i < LOGL_DEBUG; i++)
+ ut_assertok(ut_check_console_line(uts, "testing level %d", i));
+ ut_assertok(ut_check_console_end(uts));
+
+ return 0;
+}
+LOG_TEST(log_test_log_disabled_ndebug);
diff --git a/test/log/nolog_test.c b/test/log/nolog_test.c
index cb4fb3d..4e52e5b 100644
--- a/test/log/nolog_test.c
+++ b/test/log/nolog_test.c
@@ -10,6 +10,7 @@
#include <common.h>
#include <console.h>
+#include <log.h>
#include <asm/global_data.h>
#include <test/log.h>
#include <test/test.h>
@@ -128,8 +129,10 @@
memset(buf, 0, BUFFSIZE);
console_record_reset_enable();
log_debug("testing %s\n", "log_debug");
+ log(LOGC_NONE, LOGL_DEBUG, "more %s\n", "log_debug");
gd->flags &= ~GD_FLG_RECORD;
ut_assertok(ut_check_console_line(uts, "testing log_debug"));
+ ut_assertok(ut_check_console_line(uts, "more log_debug"));
ut_assertok(ut_check_console_end(uts));
return 0;
}
diff --git a/test/print_ut.c b/test/print_ut.c
index 5b0a46d..e2bcfbe 100644
--- a/test/print_ut.c
+++ b/test/print_ut.c
@@ -3,42 +3,52 @@
* Copyright (c) 2012, The Chromium Authors
*/
-#define DEBUG
-
#include <common.h>
#include <command.h>
#include <efi_api.h>
#include <display_options.h>
#include <log.h>
+#include <mapmem.h>
#include <version.h>
+#include <test/suites.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+#define BUF_SIZE 0x100
#define FAKE_BUILD_TAG "jenkins-u-boot-denx_uboot_dm-master-build-aarch64" \
"and a lot more text to come"
+/* Declare a new print test */
+#define PRINT_TEST(_name, _flags) UNIT_TEST(_name, _flags, print_test)
+
+#if CONFIG_IS_ENABLED(LIB_UUID)
/* Test printing GUIDs */
-static void guid_ut_print(void)
+static int print_guid(struct unit_test_state *uts)
{
-#if CONFIG_IS_ENABLED(LIB_UUID)
unsigned char guid[16] = {
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16
};
char str[40];
sprintf(str, "%pUb", guid);
- assert(!strcmp("01020304-0506-0708-090a-0b0c0d0e0f10", str));
+ ut_assertok(strcmp("01020304-0506-0708-090a-0b0c0d0e0f10", str));
sprintf(str, "%pUB", guid);
- assert(!strcmp("01020304-0506-0708-090A-0B0C0D0E0F10", str));
+ ut_assertok(strcmp("01020304-0506-0708-090A-0B0C0D0E0F10", str));
sprintf(str, "%pUl", guid);
- assert(!strcmp("04030201-0605-0807-090a-0b0c0d0e0f10", str));
+ ut_assertok(strcmp("04030201-0605-0807-090a-0b0c0d0e0f10", str));
sprintf(str, "%pUL", guid);
- assert(!strcmp("04030201-0605-0807-090A-0B0C0D0E0F10", str));
-#endif
+ ut_assertok(strcmp("04030201-0605-0807-090A-0B0C0D0E0F10", str));
+
+ return 0;
}
+PRINT_TEST(print_guid, 0);
+#endif
+#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
/* Test efi_loader specific printing */
-static void efi_ut_print(void)
+static int print_efi_ut(struct unit_test_state *uts)
{
-#if CONFIG_IS_ENABLED(EFI_LOADER) && !defined(API_BUILD)
char str[10];
u8 buf[sizeof(struct efi_device_path_sd_mmc_path) +
sizeof(struct efi_device_path)];
@@ -60,92 +70,268 @@
dp_end->length = sizeof(struct efi_device_path);
snprintf(str, sizeof(str), "_%pD_", buf);
- assert(!strcmp("_/SD(3)_", str));
+ ut_assertok(strcmp("_/SD(3)_", str));
/* NULL device path */
snprintf(str, sizeof(str), "_%pD_", NULL);
- assert(!strcmp("_<NULL>_", str));
-#endif
+ ut_assertok(strcmp("_<NULL>_", str));
+
+ return 0;
}
+PRINT_TEST(print_efi_ut, 0);
+#endif
-static int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc,
- char *const argv[])
+static int print_printf(struct unit_test_state *uts)
{
char big_str[400];
int big_str_len;
char str[10], *s;
int len;
- printf("%s: Testing print\n", __func__);
-
snprintf(str, sizeof(str), "testing");
- assert(!strcmp("testing", str));
+ ut_assertok(strcmp("testing", str));
snprintf(str, sizeof(str), "testing but too long");
- assert(!strcmp("testing b", str));
+ ut_assertok(strcmp("testing b", str));
snprintf(str, 1, "testing none");
- assert(!strcmp("", str));
+ ut_assertok(strcmp("", str));
*str = 'x';
snprintf(str, 0, "testing none");
- assert(*str == 'x');
+ ut_asserteq('x', *str);
sprintf(big_str, "_%ls_", L"foo");
- assert(!strcmp("_foo_", big_str));
+ ut_assertok(strcmp("_foo_", big_str));
/* Test the banner function */
s = display_options_get_banner(true, str, sizeof(str));
- assert(s == str);
- assert(!strcmp("\n\nU-Boo\n\n", s));
+ ut_asserteq_ptr(str, s);
+ ut_assertok(strcmp("\n\nU-Boo\n\n", s));
/* Assert that we do not overwrite memory before the buffer */
str[0] = '`';
s = display_options_get_banner(true, str + 1, 1);
- assert(s == str + 1);
- assert(!strcmp("`", str));
+ ut_asserteq_ptr(str + 1, s);
+ ut_assertok(strcmp("`", str));
str[0] = '~';
s = display_options_get_banner(true, str + 1, 2);
- assert(s == str + 1);
- assert(!strcmp("~\n", str));
+ ut_asserteq_ptr(str + 1, s);
+ ut_assertok(strcmp("~\n", str));
/* The last two characters are set to \n\n for all buffer sizes > 2 */
s = display_options_get_banner(false, str, sizeof(str));
- assert(s == str);
- assert(!strcmp("U-Boot \n\n", s));
+ ut_asserteq_ptr(str, s);
+ ut_assertok(strcmp("U-Boot \n\n", s));
/* Give it enough space for some of the version */
big_str_len = strlen(version_string) - 5;
s = display_options_get_banner_priv(false, FAKE_BUILD_TAG, big_str,
big_str_len);
- assert(s == big_str);
- assert(!strncmp(version_string, s, big_str_len - 3));
- assert(!strcmp("\n\n", s + big_str_len - 3));
+ ut_asserteq_ptr(big_str, s);
+ ut_assertok(strncmp(version_string, s, big_str_len - 3));
+ ut_assertok(strcmp("\n\n", s + big_str_len - 3));
/* Give it enough space for the version and some of the build tag */
big_str_len = strlen(version_string) + 9 + 20;
s = display_options_get_banner_priv(false, FAKE_BUILD_TAG, big_str,
big_str_len);
- assert(s == big_str);
+ ut_asserteq_ptr(big_str, s);
len = strlen(version_string);
- assert(!strncmp(version_string, s, len));
- assert(!strncmp(", Build: ", s + len, 9));
- assert(!strncmp(FAKE_BUILD_TAG, s + 9 + len, 12));
- assert(!strcmp("\n\n", s + big_str_len - 3));
+ ut_assertok(strncmp(version_string, s, len));
+ ut_assertok(strncmp(", Build: ", s + len, 9));
+ ut_assertok(strncmp(FAKE_BUILD_TAG, s + 9 + len, 12));
+ ut_assertok(strcmp("\n\n", s + big_str_len - 3));
+
+ return 0;
+}
+PRINT_TEST(print_printf, 0);
+
+static int print_display_buffer(struct unit_test_state *uts)
+{
+ u8 *buf;
+ int i;
- /* Test efi_loader specific printing */
- efi_ut_print();
+ buf = map_sysmem(0, BUF_SIZE);
+ memset(buf, '\0', BUF_SIZE);
+ for (i = 0; i < 0x11; i++)
+ buf[i] = i * 0x11;
- /* Test printing GUIDs */
- guid_ut_print();
+ /* bytes */
+ console_record_reset();
+ print_buffer(0, buf, 1, 0x12, 0);
+ ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
+ ut_assert_nextline("00000010: 10 00 ..");
+ ut_assert_console_end();
- printf("%s: Everything went swimmingly\n", __func__);
+ /* line length */
+ console_record_reset();
+ print_buffer(0, buf, 1, 0x12, 8);
+ ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw");
+ ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........");
+ ut_assert_nextline("00000010: 10 00 ..");
+ ut_assert_console_end();
+
+ /* long line */
+ console_record_reset();
+ buf[0x41] = 0x41;
+ print_buffer(0, buf, 1, 0x42, 0x40);
+ ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................");
+ ut_assert_nextline("00000040: 00 41 .A");
+ ut_assert_console_end();
+
+ /* address */
+ console_record_reset();
+ print_buffer(0x12345678, buf, 1, 0x12, 0);
+ ut_assert_nextline("12345678: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
+ ut_assert_nextline("12345688: 10 00 ..");
+ ut_assert_console_end();
+
+ /* 16-bit */
+ console_record_reset();
+ print_buffer(0, buf, 2, 9, 0);
+ ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........");
+ ut_assert_nextline("00000010: 0010 ..");
+ ut_assert_console_end();
+
+ /* 32-bit */
+ console_record_reset();
+ print_buffer(0, buf, 4, 5, 0);
+ ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........");
+ ut_assert_nextline("00000010: 00000010 ....");
+ ut_assert_console_end();
+
+ /* 64-bit */
+ console_record_reset();
+ print_buffer(0, buf, 8, 3, 0);
+ ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........");
+ ut_assert_nextline("00000010: 0000000000000010 ........");
+ ut_assert_console_end();
+
+ /* ASCII */
+ console_record_reset();
+ buf[1] = 31;
+ buf[2] = 32;
+ buf[3] = 33;
+ for (i = 0; i < 4; i++)
+ buf[4 + i] = 126 + i;
+ buf[8] = 255;
+ print_buffer(0, buf, 1, 10, 0);
+ ut_assert_nextline("00000000: 00 1f 20 21 7e 7f 80 81 ff 99 .. !~.....");
+ ut_assert_console_end();
+
+ unmap_sysmem(buf);
+
+ return 0;
+}
+PRINT_TEST(print_display_buffer, UT_TESTF_CONSOLE_REC);
+
+static int print_hexdump_line(struct unit_test_state *uts)
+{
+ char *linebuf;
+ u8 *buf;
+ int i;
+
+ buf = map_sysmem(0, BUF_SIZE);
+ memset(buf, '\0', BUF_SIZE);
+ for (i = 0; i < 0x11; i++)
+ buf[i] = i * 0x11;
+
+ /* Check buffer size calculations */
+ linebuf = map_sysmem(0x400, BUF_SIZE);
+ memset(linebuf, '\xff', BUF_SIZE);
+ ut_asserteq(-ENOSPC, hexdump_line(0, buf, 1, 0x10, 0, linebuf, 75));
+ ut_asserteq(-1, linebuf[0]);
+ ut_asserteq(0x10, hexdump_line(0, buf, 1, 0x10, 0, linebuf, 76));
+ ut_asserteq(0, linebuf[75]);
+ ut_asserteq(-1, linebuf[76]);
+
+ unmap_sysmem(buf);
+
+ return 0;
+}
+PRINT_TEST(print_hexdump_line, UT_TESTF_CONSOLE_REC);
+
+static int print_do_hex_dump(struct unit_test_state *uts)
+{
+ u8 *buf;
+ int i;
+
+ buf = map_sysmem(0, BUF_SIZE);
+ memset(buf, '\0', BUF_SIZE);
+ for (i = 0; i < 0x11; i++)
+ buf[i] = i * 0x11;
+
+ /* bytes */
+ console_record_reset();
+ print_hex_dump_bytes("", DUMP_PREFIX_ADDRESS, buf, 0x12);
+ ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff ..\"3DUfw........");
+ ut_assert_nextline("00000010: 10 00 ..");
+ ut_assert_console_end();
+
+ /* line length */
+ console_record_reset();
+ print_hex_dump("", DUMP_PREFIX_ADDRESS, 8, 1, buf, 0x12, true);
+ ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 ..\"3DUfw");
+ ut_assert_nextline("00000008: 88 99 aa bb cc dd ee ff ........");
+ ut_assert_nextline("00000010: 10 00 ..");
+ ut_assert_console_end();
+ unmap_sysmem(buf);
+
+ /* long line */
+ console_record_reset();
+ buf[0x41] = 0x41;
+ print_hex_dump("", DUMP_PREFIX_ADDRESS, 0x40, 1, buf, 0x42, true);
+ ut_assert_nextline("00000000: 00 11 22 33 44 55 66 77 88 99 aa bb cc dd ee ff 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ..\"3DUfw........................................................");
+ ut_assert_nextline("00000040: 00 41 .A");
+ ut_assert_console_end();
+
+ /* 16-bit */
+ console_record_reset();
+ print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 2, buf, 0x12, true);
+ ut_assert_nextline("00000000: 1100 3322 5544 7766 9988 bbaa ddcc ffee ..\"3DUfw........");
+ ut_assert_nextline("00000010: 0010 ..");
+ ut_assert_console_end();
+ unmap_sysmem(buf);
+
+ /* 32-bit */
+ console_record_reset();
+ print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 4, buf, 0x14, true);
+ ut_assert_nextline("00000000: 33221100 77665544 bbaa9988 ffeeddcc ..\"3DUfw........");
+ ut_assert_nextline("00000010: 00000010 ....");
+ ut_assert_console_end();
+ unmap_sysmem(buf);
+
+ /* 64-bit */
+ console_record_reset();
+ print_hex_dump("", DUMP_PREFIX_ADDRESS, 16, 8, buf, 0x18, true);
+ ut_assert_nextline("00000000: 7766554433221100 ffeeddccbbaa9988 ..\"3DUfw........");
+ ut_assert_nextline("00000010: 0000000000000010 ........");
+ ut_assert_console_end();
+ unmap_sysmem(buf);
+
+ /* ASCII */
+ console_record_reset();
+ buf[1] = 31;
+ buf[2] = 32;
+ buf[3] = 33;
+ for (i = 0; i < 4; i++)
+ buf[4 + i] = 126 + i;
+ buf[8] = 255;
+ print_hex_dump("", DUMP_PREFIX_ADDRESS, 0, 1, buf, 10, true);
+ ut_assert_nextline("00000000: 00 1f 20 21 7e 7f 80 81 ff 99 .. !~.....");
+ ut_assert_console_end();
+ unmap_sysmem(buf);
+
return 0;
}
+PRINT_TEST(print_do_hex_dump, UT_TESTF_CONSOLE_REC);
-U_BOOT_CMD(
- ut_print, 1, 1, do_ut_print,
- "Very basic test of printf(), etc.",
- ""
-);
+int do_ut_print(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
+{
+ struct unit_test *tests = UNIT_TEST_SUITE_START(print_test);
+ const int n_ents = UNIT_TEST_SUITE_COUNT(print_test);
+
+ return cmd_ut_category("print", "print_", tests, n_ents, argc, argv);
+}
diff --git a/test/py/conftest.py b/test/py/conftest.py
index 1b909cd..11a3f30 100644
--- a/test/py/conftest.py
+++ b/test/py/conftest.py
@@ -226,7 +226,7 @@
import u_boot_console_exec_attach
console = u_boot_console_exec_attach.ConsoleExecAttach(log, ubconfig)
-re_ut_test_list = re.compile(r'_u_boot_list_2_ut_(.*)_test_2_\1_test_(.*)\s*$')
+re_ut_test_list = re.compile(r'[^a-zA-Z0-9_]_u_boot_list_2_ut_(.*)_test_2_\1_test_(.*)\s*$')
def generate_ut_subtest(metafunc, fixture_name, sym_path):
"""Provide parametrization for a ut_subtest fixture.
diff --git a/test/py/requirements.txt b/test/py/requirements.txt
index 5b48292..33c5c0b 100644
--- a/test/py/requirements.txt
+++ b/test/py/requirements.txt
@@ -17,6 +17,7 @@
pytest==5.2.1
python-mimeparse==1.6.0
python-subunit==1.3.0
+requests==2.25.1
six==1.12.0
testtools==2.3.0
traceback2==1.4.0
diff --git a/test/py/tests/test_extension.py b/test/py/tests/test_extension.py
new file mode 100644
index 0000000..267cf2f
--- /dev/null
+++ b/test/py/tests/test_extension.py
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0+
+# Copyright (c) 2020
+# Author: Kory Maincent <kory.maincent@bootlin.com>
+
+# Test U-Boot's "extension" commands.
+
+import os
+import pytest
+import u_boot_utils
+
+overlay_addr = 0x1000
+
+SANDBOX_DTB='arch/sandbox/dts/sandbox.dtb'
+OVERLAY_DIR='arch/sandbox/dts/'
+
+def load_dtb(u_boot_console):
+ u_boot_console.log.action('Loading devicetree to RAM...')
+ u_boot_console.run_command('host load hostfs - $fdt_addr_r %s' % (os.path.join(u_boot_console.config.build_dir, SANDBOX_DTB)))
+ u_boot_console.run_command('fdt addr $fdt_addr_r')
+
+@pytest.mark.buildconfigspec('cmd_fdt')
+@pytest.mark.boardspec('sandbox')
+def test_extension(u_boot_console):
+ """Test the 'extension' command."""
+
+ load_dtb(u_boot_console)
+
+ output = u_boot_console.run_command('extension list')
+ assert('No extension' in output)
+
+ output = u_boot_console.run_command('extension scan')
+ assert output == 'Found 2 extension board(s).'
+
+ output = u_boot_console.run_command('extension list')
+ assert('overlay0.dtbo' in output)
+ assert('overlay1.dtbo' in output)
+
+ u_boot_console.run_command_list([
+ 'setenv extension_overlay_addr %s' % (overlay_addr),
+ 'setenv extension_overlay_cmd \'host load hostfs - ${extension_overlay_addr} %s${extension_overlay_name}\'' % (os.path.join(u_boot_console.config.build_dir, OVERLAY_DIR))])
+
+ output = u_boot_console.run_command('extension apply 0')
+ assert('bytes read' in output)
+
+ output = u_boot_console.run_command('fdt print')
+ assert('button3' in output)
+
+ output = u_boot_console.run_command('extension apply all')
+ assert('bytes read' in output)
+
+ output = u_boot_console.run_command('fdt print')
+ assert('button4' in output)
+
diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py
index 50af9ef..410a675 100644
--- a/test/py/tests/test_fs/conftest.py
+++ b/test/py/tests/test_fs/conftest.py
@@ -278,14 +278,19 @@
check_call('mkdir -p %s' % mount_dir, shell=True)
except CalledProcessError as err:
pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err))
- return
- finally:
call('rm -f %s' % fs_img, shell=True)
+ return
try:
# Mount the image so we can populate it.
mount_fs(fs_type, fs_img, mount_dir)
+ except CalledProcessError as err:
+ pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err))
+ call('rmdir %s' % mount_dir, shell=True)
+ call('rm -f %s' % fs_img, shell=True)
+ return
+ try:
# Create a subdirectory.
check_call('mkdir %s/SUBDIR' % mount_dir, shell=True)
@@ -348,11 +353,12 @@
except CalledProcessError as err:
pytest.skip('Setup failed for filesystem: ' + fs_type + '. {}'.format(err))
+ umount_fs(mount_dir)
return
else:
+ umount_fs(mount_dir)
yield [fs_ubtype, fs_img, md5val]
finally:
- umount_fs(mount_dir)
call('rmdir %s' % mount_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
@@ -394,14 +400,19 @@
check_call('mkdir -p %s' % mount_dir, shell=True)
except CalledProcessError as err:
pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err))
- return
- finally:
call('rm -f %s' % fs_img, shell=True)
+ return
try:
# Mount the image so we can populate it.
mount_fs(fs_type, fs_img, mount_dir)
+ except CalledProcessError as err:
+ pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err))
+ call('rmdir %s' % mount_dir, shell=True)
+ call('rm -f %s' % fs_img, shell=True)
+ return
+ try:
# Create a test directory
check_call('mkdir %s/dir1' % mount_dir, shell=True)
@@ -443,11 +454,12 @@
check_call('rm %s' % tmp_file, shell=True)
except CalledProcessError:
pytest.skip('Setup failed for filesystem: ' + fs_type)
+ umount_fs(mount_dir)
return
else:
+ umount_fs(mount_dir)
yield [fs_ubtype, fs_img, md5val]
finally:
- umount_fs(mount_dir)
call('rmdir %s' % mount_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
@@ -517,14 +529,19 @@
check_call('mkdir -p %s' % mount_dir, shell=True)
except CalledProcessError as err:
pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err))
- return
- finally:
call('rm -f %s' % fs_img, shell=True)
+ return
try:
# Mount the image so we can populate it.
mount_fs(fs_type, fs_img, mount_dir)
+ except CalledProcessError as err:
+ pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err))
+ call('rmdir %s' % mount_dir, shell=True)
+ call('rm -f %s' % fs_img, shell=True)
+ return
+ try:
# Test Case 1 & 3
check_call('mkdir %s/dir1' % mount_dir, shell=True)
check_call('dd if=/dev/urandom of=%s/dir1/file1 bs=1K count=1'
@@ -548,11 +565,12 @@
except CalledProcessError:
pytest.skip('Setup failed for filesystem: ' + fs_type)
+ umount_fs(mount_dir)
return
else:
+ umount_fs(mount_dir)
yield [fs_ubtype, fs_img]
finally:
- umount_fs(mount_dir)
call('rmdir %s' % mount_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
@@ -594,14 +612,19 @@
check_call('mkdir -p %s' % mount_dir, shell=True)
except CalledProcessError as err:
pytest.skip('Preparing mount folder failed for filesystem: ' + fs_type + '. {}'.format(err))
- return
- finally:
call('rm -f %s' % fs_img, shell=True)
+ return
try:
# Mount the image so we can populate it.
mount_fs(fs_type, fs_img, mount_dir)
+ except CalledProcessError as err:
+ pytest.skip('Mounting to folder failed for filesystem: ' + fs_type + '. {}'.format(err))
+ call('rmdir %s' % mount_dir, shell=True)
+ call('rm -f %s' % fs_img, shell=True)
+ return
+ try:
# Create a subdirectory.
check_call('mkdir %s/SUBDIR' % mount_dir, shell=True)
@@ -625,10 +648,11 @@
except CalledProcessError:
pytest.skip('Setup failed for filesystem: ' + fs_type)
+ umount_fs(mount_dir)
return
else:
+ umount_fs(mount_dir)
yield [fs_ubtype, fs_img, md5val]
finally:
- umount_fs(mount_dir)
call('rmdir %s' % mount_dir, shell=True)
call('rm -f %s' % fs_img, shell=True)
diff --git a/test/test-main.c b/test/test-main.c
index 8c852d7..7afe874 100644
--- a/test/test-main.c
+++ b/test/test-main.c
@@ -135,25 +135,32 @@
static bool test_matches(const char *prefix, const char *test_name,
const char *select_name)
{
+ size_t len;
+
if (!select_name)
return true;
- if (!strcmp(test_name, select_name))
+ /* Allow glob expansion in the test name */
+ len = select_name[strlen(select_name) - 1] == '*' ? strlen(select_name) : 0;
+ if (len-- == 1)
return true;
- if (!prefix) {
- const char *p = strstr(test_name, "_test_");
+ if (!strncmp(test_name, select_name, len))
+ return true;
- /* convert xxx_test_yyy to yyy, i.e. remove the suite name */
- if (p)
- test_name = p + 6;
- } else {
+ if (prefix) {
/* All tests have this prefix */
if (!strncmp(test_name, prefix, strlen(prefix)))
test_name += strlen(prefix);
+ } else {
+ const char *p = strstr(test_name, "_test_");
+
+ /* convert xxx_test_yyy to yyy, i.e. remove the suite name */
+ if (p)
+ test_name = p + strlen("_test_");
}
- if (!strcmp(test_name, select_name))
+ if (!strncmp(test_name, select_name, len))
return true;
return false;
diff --git a/test/ut.c b/test/ut.c
index ea0af15..1eec2a5 100644
--- a/test/ut.c
+++ b/test/ut.c
@@ -51,14 +51,37 @@
return ut_check_free() - last;
}
+static int readline_check(struct unit_test_state *uts)
+{
+ int ret;
+
+ ret = console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+ if (ret == -ENOSPC) {
+ ut_fail(uts, __FILE__, __LINE__, __func__,
+ "Console record buffer too small - increase CONFIG_CONSOLE_RECORD_OUT_SIZE");
+ return ret;
+ }
+
+ return 0;
+}
+
int ut_check_console_line(struct unit_test_state *uts, const char *fmt, ...)
{
va_list args;
+ int len;
+ int ret;
va_start(args, fmt);
- vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args);
+ len = vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args);
va_end(args);
- console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+ if (len >= sizeof(uts->expect_str)) {
+ ut_fail(uts, __FILE__, __LINE__, __func__,
+ "unit_test_state->expect_str too small");
+ return -EOVERFLOW;
+ }
+ ret = readline_check(uts);
+ if (ret < 0)
+ return ret;
return strcmp(uts->expect_str, uts->actual_str);
}
@@ -66,11 +89,20 @@
int ut_check_console_linen(struct unit_test_state *uts, const char *fmt, ...)
{
va_list args;
+ int len;
+ int ret;
va_start(args, fmt);
- vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args);
+ len = vsnprintf(uts->expect_str, sizeof(uts->expect_str), fmt, args);
va_end(args);
- console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+ if (len >= sizeof(uts->expect_str)) {
+ ut_fail(uts, __FILE__, __LINE__, __func__,
+ "unit_test_state->expect_str too small");
+ return -EOVERFLOW;
+ }
+ ret = readline_check(uts);
+ if (ret < 0)
+ return ret;
return strncmp(uts->expect_str, uts->actual_str,
strlen(uts->expect_str));
@@ -78,19 +110,26 @@
int ut_check_skipline(struct unit_test_state *uts)
{
+ int ret;
+
if (!console_record_avail())
return -ENFILE;
- console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+ ret = readline_check(uts);
+ if (ret < 0)
+ return ret;
return 0;
}
int ut_check_console_end(struct unit_test_state *uts)
{
+ int ret;
+
if (!console_record_avail())
return 0;
-
- console_record_readline(uts->actual_str, sizeof(uts->actual_str));
+ ret = readline_check(uts);
+ if (ret < 0)
+ return ret;
return 1;
}
@@ -112,7 +151,7 @@
if (str[8] != ':' || str[9] != ' ')
return 1;
- bytes = len - 8 - 2 - 3 * 16 - 4;
+ bytes = len - 8 - 2 - 3 * 16 - 2;
upto += bytes;
}
diff --git a/tools/binman/binman.rst b/tools/binman/binman.rst
index 1aa2459..bc635aa 100644
--- a/tools/binman/binman.rst
+++ b/tools/binman/binman.rst
@@ -232,6 +232,30 @@
inclusion' below.
+Using binman with OF_BOARD or OF_PRIOR_STAGE
+--------------------------------------------
+
+Normally binman is used with a board configured with OF_SEPARATE or OF_EMBED.
+This is a typical scenario where a device tree source that contains the binman
+node is provided in the arch/<arch>/dts directory for a specific board.
+
+However for a board configured with OF_BOARD or OF_PRIOR_STAGE, no device tree
+blob is provided in the U-Boot build phase hence the binman node information
+is not available. In order to support such use case, a new Kconfig option
+BINMAN_STANDALONE_FDT is introduced, to tell the build system that a standalone
+device tree blob containing binman node is explicitly required.
+
+Note there is a Kconfig option BINMAN_FDT which enables U-Boot run time to
+access information about binman entries, stored in the device tree in a binman
+node. Generally speaking, this option makes sense for OF_SEPARATE or OF_EMBED.
+For the other OF_CONTROL methods, it's quite possible binman node is not
+available as binman is invoked during the build phase, thus this option is not
+turned on by default for these OF_CONTROL methods.
+
+See qemu-riscv64_spl_defconfig for an example of how binman is used with
+OF_PRIOR_STAGE to generate u-boot.itb image.
+
+
Access to binman entry offsets at run time (symbols)
----------------------------------------------------
@@ -322,9 +346,9 @@
command line. For example some entries need access to files and it is not
always convenient to put these filenames in the image definition (device tree).
-The-a option supports this::
+The -a option supports this::
- -a<prop>=<value>
+ -a <prop>=<value>
where::
diff --git a/tools/binman/entries.rst b/tools/binman/entries.rst
index a91211e..dcac700 100644
--- a/tools/binman/entries.rst
+++ b/tools/binman/entries.rst
@@ -461,11 +461,15 @@
When used, this entry will be populated with an FMAP which reflects the
entries in the current image. Note that any hierarchy is squashed, since
-FMAP does not support this. Also, CBFS entries appear as a single entry -
-the sub-entries are ignored.
+FMAP does not support this. Sections are represented as an area appearing
+before its contents, so that it is possible to reconstruct the hierarchy
+from the FMAP by using the offset information. This convention does not
+seem to be documented, but is used in Chromium OS.
+CBFS entries appear as a single entry, i.e. the sub-entries are ignored.
+
Entry: gbb: An entry which contains a Chromium OS Google Binary Block
---------------------------------------------------------------------
@@ -756,6 +760,19 @@
binman.
+
+Entry: opensbi: RISC-V OpenSBI fw_dynamic blob
+----------------------------------------------
+
+Properties / Entry arguments:
+ - opensbi-path: Filename of file to read into entry. This is typically
+ called fw_dynamic.bin
+
+This entry holds the run-time firmware, typically started by U-Boot SPL.
+See the U-Boot README for your architecture or board for how to use it. See
+https://github.com/riscv/opensbi for more information about OpenSBI.
+
+
Entry: powerpc-mpc85xx-bootpg-resetvec: PowerPC mpc85xx bootpg + resetvec code for U-Boot
-----------------------------------------------------------------------------------------
@@ -804,6 +821,11 @@
missing their contents. The second will produce an image but of
course it will not work.
+Properties:
+ _allow_missing: True if this section permits external blobs to be
+ missing their contents. The second will produce an image but of
+ course it will not work.
+
Since a section is also an entry, it inherits all the properies of entries
too.
diff --git a/tools/binman/etype/atf_bl31.py b/tools/binman/etype/atf_bl31.py
index 163d714..2041da4 100644
--- a/tools/binman/etype/atf_bl31.py
+++ b/tools/binman/etype/atf_bl31.py
@@ -2,7 +2,7 @@
# Copyright 2020 Google LLC
# Written by Simon Glass <sjg@chromium.org>
#
-# Entry-type module for Intel Management Engine binary blob
+# Entry-type module for ARM Trusted Firmware binary blob
#
from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
diff --git a/tools/binman/etype/fmap.py b/tools/binman/etype/fmap.py
index fe81c6f..cac99b6 100644
--- a/tools/binman/etype/fmap.py
+++ b/tools/binman/etype/fmap.py
@@ -28,8 +28,12 @@
When used, this entry will be populated with an FMAP which reflects the
entries in the current image. Note that any hierarchy is squashed, since
- FMAP does not support this. Also, CBFS entries appear as a single entry -
- the sub-entries are ignored.
+ FMAP does not support this. Sections are represented as an area appearing
+ before its contents, so that it is possible to reconstruct the hierarchy
+ from the FMAP by using the offset information. This convention does not
+ seem to be documented, but is used in Chromium OS.
+
+ CBFS entries appear as a single entry, i.e. the sub-entries are ignored.
"""
def __init__(self, section, etype, node):
super().__init__(section, etype, node)
@@ -45,6 +49,17 @@
tout.Debug("fmap: Add entry '%s' type '%s' (%s subentries)" %
(entry.GetPath(), entry.etype, ToHexSize(entries)))
if entries and entry.etype != 'cbfs':
+ # Create an area for the section, which encompasses all entries
+ # within it
+ if entry.image_pos is None:
+ pos = 0
+ else:
+ pos = entry.image_pos - entry.GetRootSkipAtStart()
+
+ # Drop @ symbols in name
+ name = entry.name.replace('@', '')
+ areas.append(
+ fmap_util.FmapArea(pos, entry.size or 0, name, 0))
for subentry in entries.values():
_AddEntries(areas, subentry)
else:
diff --git a/tools/binman/etype/opensbi.py b/tools/binman/etype/opensbi.py
new file mode 100644
index 0000000..74d473d
--- /dev/null
+++ b/tools/binman/etype/opensbi.py
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2021, Bin Meng <bmeng.cn@gmail.com>
+#
+# Entry-type module for RISC-V OpenSBI binary blob
+#
+
+from binman.etype.blob_named_by_arg import Entry_blob_named_by_arg
+
+class Entry_opensbi(Entry_blob_named_by_arg):
+ """RISC-V OpenSBI fw_dynamic blob
+
+ Properties / Entry arguments:
+ - opensbi-path: Filename of file to read into entry. This is typically
+ called fw_dynamic.bin
+
+ This entry holds the run-time firmware, typically started by U-Boot SPL.
+ See the U-Boot README for your architecture or board for how to use it. See
+ https://github.com/riscv/opensbi for more information about OpenSBI.
+ """
+ def __init__(self, section, etype, node):
+ super().__init__(section, etype, node, 'opensbi')
+ self.external = True
diff --git a/tools/binman/ftest.py b/tools/binman/ftest.py
index 89fe661..5383eec 100644
--- a/tools/binman/ftest.py
+++ b/tools/binman/ftest.py
@@ -76,6 +76,7 @@
FSP_S_DATA = b'fsp_s'
FSP_T_DATA = b'fsp_t'
ATF_BL31_DATA = b'bl31'
+OPENSBI_DATA = b'opensbi'
SCP_DATA = b'scp'
TEST_FDT1_DATA = b'fdt1'
TEST_FDT2_DATA = b'test-fdt2'
@@ -178,6 +179,7 @@
TestFunctional._MakeInputFile('compress', COMPRESS_DATA)
TestFunctional._MakeInputFile('compress_big', COMPRESS_DATA_BIG)
TestFunctional._MakeInputFile('bl31.bin', ATF_BL31_DATA)
+ TestFunctional._MakeInputFile('fw_dynamic.bin', OPENSBI_DATA)
TestFunctional._MakeInputFile('scp.bin', SCP_DATA)
# Add a few .dtb files for testing
@@ -1341,6 +1343,7 @@
def testSplNoDtb(self):
"""Test that an image with spl/u-boot-spl-nodtb.bin can be created"""
+ self._SetupSplElf()
data = self._DoReadFile('052_u_boot_spl_nodtb.dts')
self.assertEqual(U_BOOT_SPL_NODTB_DATA, data[:len(U_BOOT_SPL_NODTB_DATA)])
@@ -1594,26 +1597,41 @@
self.assertEqual(1, fhdr.ver_major)
self.assertEqual(0, fhdr.ver_minor)
self.assertEqual(0, fhdr.base)
- self.assertEqual(16 + 16 +
- fmap_util.FMAP_HEADER_LEN +
- fmap_util.FMAP_AREA_LEN * 3, fhdr.image_size)
+ expect_size = fmap_util.FMAP_HEADER_LEN + fmap_util.FMAP_AREA_LEN * 5
+ self.assertEqual(16 + 16 + expect_size, fhdr.image_size)
self.assertEqual(b'FMAP', fhdr.name)
- self.assertEqual(3, fhdr.nareas)
- for fentry in fentries:
- self.assertEqual(0, fentry.flags)
+ self.assertEqual(5, fhdr.nareas)
+ fiter = iter(fentries)
- self.assertEqual(0, fentries[0].offset)
- self.assertEqual(4, fentries[0].size)
- self.assertEqual(b'RO_U_BOOT', fentries[0].name)
+ fentry = next(fiter)
+ self.assertEqual(b'SECTION0', fentry.name)
+ self.assertEqual(0, fentry.offset)
+ self.assertEqual(16, fentry.size)
+ self.assertEqual(0, fentry.flags)
- self.assertEqual(16, fentries[1].offset)
- self.assertEqual(4, fentries[1].size)
- self.assertEqual(b'RW_U_BOOT', fentries[1].name)
+ fentry = next(fiter)
+ self.assertEqual(b'RO_U_BOOT', fentry.name)
+ self.assertEqual(0, fentry.offset)
+ self.assertEqual(4, fentry.size)
+ self.assertEqual(0, fentry.flags)
- self.assertEqual(32, fentries[2].offset)
- self.assertEqual(fmap_util.FMAP_HEADER_LEN +
- fmap_util.FMAP_AREA_LEN * 3, fentries[2].size)
- self.assertEqual(b'FMAP', fentries[2].name)
+ fentry = next(fiter)
+ self.assertEqual(b'SECTION1', fentry.name)
+ self.assertEqual(16, fentry.offset)
+ self.assertEqual(16, fentry.size)
+ self.assertEqual(0, fentry.flags)
+
+ fentry = next(fiter)
+ self.assertEqual(b'RW_U_BOOT', fentry.name)
+ self.assertEqual(16, fentry.offset)
+ self.assertEqual(4, fentry.size)
+ self.assertEqual(0, fentry.flags)
+
+ fentry = next(fiter)
+ self.assertEqual(b'FMAP', fentry.name)
+ self.assertEqual(32, fentry.offset)
+ self.assertEqual(expect_size, fentry.size)
+ self.assertEqual(0, fentry.flags)
def testBlobNamedByArg(self):
"""Test we can add a blob with the filename coming from an entry arg"""
@@ -2063,20 +2081,29 @@
self.assertEqual(expected, data[:32])
fhdr, fentries = fmap_util.DecodeFmap(data[36:])
- self.assertEqual(0x100, fhdr.image_size)
+ self.assertEqual(0x180, fhdr.image_size)
+ expect_size = fmap_util.FMAP_HEADER_LEN + fmap_util.FMAP_AREA_LEN * 4
+ fiter = iter(fentries)
- self.assertEqual(0, fentries[0].offset)
- self.assertEqual(4, fentries[0].size)
- self.assertEqual(b'U_BOOT', fentries[0].name)
+ fentry = next(fiter)
+ self.assertEqual(b'U_BOOT', fentry.name)
+ self.assertEqual(0, fentry.offset)
+ self.assertEqual(4, fentry.size)
- self.assertEqual(4, fentries[1].offset)
- self.assertEqual(3, fentries[1].size)
- self.assertEqual(b'INTEL_MRC', fentries[1].name)
+ fentry = next(fiter)
+ self.assertEqual(b'SECTION', fentry.name)
+ self.assertEqual(4, fentry.offset)
+ self.assertEqual(0x20 + expect_size, fentry.size)
- self.assertEqual(36, fentries[2].offset)
- self.assertEqual(fmap_util.FMAP_HEADER_LEN +
- fmap_util.FMAP_AREA_LEN * 3, fentries[2].size)
- self.assertEqual(b'FMAP', fentries[2].name)
+ fentry = next(fiter)
+ self.assertEqual(b'INTEL_MRC', fentry.name)
+ self.assertEqual(4, fentry.offset)
+ self.assertEqual(3, fentry.size)
+
+ fentry = next(fiter)
+ self.assertEqual(b'FMAP', fentry.name)
+ self.assertEqual(36, fentry.offset)
+ self.assertEqual(expect_size, fentry.size)
def testElf(self):
"""Basic test of ELF entries"""
@@ -3801,7 +3828,7 @@
'default-dt': 'test-fdt2',
}
data = self._DoReadFileDtb(
- '172_fit_fdt.dts',
+ '170_fit_fdt.dts',
entry_args=entry_args,
extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
self.assertEqual(U_BOOT_NODTB_DATA, data[-len(U_BOOT_NODTB_DATA):])
@@ -3823,7 +3850,7 @@
def testFitFdtMissingList(self):
"""Test handling of a missing 'of-list' entry arg"""
with self.assertRaises(ValueError) as e:
- self._DoReadFile('172_fit_fdt.dts')
+ self._DoReadFile('170_fit_fdt.dts')
self.assertIn("Generator node requires 'of-list' entry argument",
str(e.exception))
@@ -3846,7 +3873,7 @@
entry_args = {
'of-list': '',
}
- data = self._DoReadFileDtb('172_fit_fdt.dts', entry_args=entry_args)[0]
+ data = self._DoReadFileDtb('170_fit_fdt.dts', entry_args=entry_args)[0]
def testFitFdtMissing(self):
"""Test handling of a missing 'default-dt' entry arg"""
@@ -3855,7 +3882,7 @@
}
with self.assertRaises(ValueError) as e:
self._DoReadFileDtb(
- '172_fit_fdt.dts',
+ '170_fit_fdt.dts',
entry_args=entry_args,
extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
self.assertIn("Generated 'default' node requires default-dt entry argument",
@@ -3869,7 +3896,7 @@
}
with self.assertRaises(ValueError) as e:
self._DoReadFileDtb(
- '172_fit_fdt.dts',
+ '170_fit_fdt.dts',
entry_args=entry_args,
extra_indirs=[os.path.join(self._indir, TEST_FDT_SUBDIR)])[0]
self.assertIn("default-dt entry argument 'test-fdt3' not found in fdt list: test-fdt1, test-fdt2",
@@ -4272,6 +4299,7 @@
def testTplNoDtb(self):
"""Test that an image with tpl/u-boot-tpl-nodtb.bin can be created"""
+ self._SetupTplElf()
data = self._DoReadFile('192_u_boot_tpl_nodtb.dts')
self.assertEqual(U_BOOT_TPL_NODTB_DATA,
data[:len(U_BOOT_TPL_NODTB_DATA)])
@@ -4509,5 +4537,10 @@
expected += tools.GetBytes(0, 88 - len(expected)) + U_BOOT_NODTB_DATA
self.assertEqual(expected, data)
+ def testPackOpenSBI(self):
+ """Test that an image with an OpenSBI binary can be created"""
+ data = self._DoReadFile('201_opensbi.dts')
+ self.assertEqual(OPENSBI_DATA, data[:len(OPENSBI_DATA)])
+
if __name__ == "__main__":
unittest.main()
diff --git a/tools/binman/test/095_fmap_x86_section.dts b/tools/binman/test/095_fmap_x86_section.dts
index 4cfce45..fd5f018 100644
--- a/tools/binman/test/095_fmap_x86_section.dts
+++ b/tools/binman/test/095_fmap_x86_section.dts
@@ -7,7 +7,7 @@
binman {
end-at-4gb;
- size = <0x100>;
+ size = <0x180>;
u-boot {
};
section {
diff --git a/tools/binman/test/172_fit_fdt.dts b/tools/binman/test/170_fit_fdt.dts
similarity index 100%
rename from tools/binman/test/172_fit_fdt.dts
rename to tools/binman/test/170_fit_fdt.dts
diff --git a/tools/binman/test/201_opensbi.dts b/tools/binman/test/201_opensbi.dts
new file mode 100644
index 0000000..942183f
--- /dev/null
+++ b/tools/binman/test/201_opensbi.dts
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ binman {
+ opensbi {
+ filename = "fw_dynamic.bin";
+ };
+ };
+};
diff --git a/tools/buildman/builder.py b/tools/buildman/builder.py
index be8a8fa..ce852eb 100644
--- a/tools/buildman/builder.py
+++ b/tools/buildman/builder.py
@@ -182,6 +182,7 @@
only useful for testing in-tree builds.
work_in_output: Use the output directory as the work directory and
don't write to a separate output directory.
+ thread_exceptions: List of exceptions raised by thread jobs
Private members:
_base_board_dict: Last-summarised Dict of boards
@@ -235,7 +236,8 @@
no_subdirs=False, full_path=False, verbose_build=False,
mrproper=False, per_board_out_dir=False,
config_only=False, squash_config_y=False,
- warnings_as_errors=False, work_in_output=False):
+ warnings_as_errors=False, work_in_output=False,
+ test_thread_exceptions=False):
"""Create a new Builder object
Args:
@@ -262,6 +264,9 @@
warnings_as_errors: Treat all compiler warnings as errors
work_in_output: Use the output directory as the work directory and
don't write to a separate output directory.
+ test_thread_exceptions: Uses for tests only, True to make the
+ threads raise an exception instead of reporting their result.
+ This simulates a failure in the code somewhere
"""
self.toolchains = toolchains
self.base_dir = base_dir
@@ -311,13 +316,16 @@
self._re_migration_warning = re.compile(r'^={21} WARNING ={22}\n.*\n=+\n',
re.MULTILINE | re.DOTALL)
+ self.thread_exceptions = []
+ self.test_thread_exceptions = test_thread_exceptions
if self.num_threads:
self._single_builder = None
self.queue = queue.Queue()
self.out_queue = queue.Queue()
for i in range(self.num_threads):
- t = builderthread.BuilderThread(self, i, mrproper,
- per_board_out_dir)
+ t = builderthread.BuilderThread(
+ self, i, mrproper, per_board_out_dir,
+ test_exception=test_thread_exceptions)
t.setDaemon(True)
t.start()
self.threads.append(t)
@@ -1676,6 +1684,7 @@
Tuple containing:
- number of boards that failed to build
- number of boards that issued warnings
+ - list of thread exceptions raised
"""
self.commit_count = len(commits) if commits else 1
self.commits = commits
@@ -1689,7 +1698,7 @@
Print('\rStarting build...', newline=False)
self.SetupBuild(board_selected, commits)
self.ProcessResult(None)
-
+ self.thread_exceptions = []
# Create jobs to build all commits for each board
for brd in board_selected.values():
job = builderthread.BuilderJob()
@@ -1728,5 +1737,8 @@
rate = float(self.count) / duration.total_seconds()
msg += ', duration %s, rate %1.2f' % (duration, rate)
Print(msg)
+ if self.thread_exceptions:
+ Print('Failed: %d thread exceptions' % len(self.thread_exceptions),
+ colour=self.col.RED)
- return (self.fail, self.warned)
+ return (self.fail, self.warned, self.thread_exceptions)
diff --git a/tools/buildman/builderthread.py b/tools/buildman/builderthread.py
index 06ed272..48128cf 100644
--- a/tools/buildman/builderthread.py
+++ b/tools/buildman/builderthread.py
@@ -89,16 +89,23 @@
Members:
builder: The builder which contains information we might need
thread_num: Our thread number (0-n-1), used to decide on a
- temporary directory. If this is -1 then there are no threads
- and we are the (only) main process
+ temporary directory. If this is -1 then there are no threads
+ and we are the (only) main process
+ mrproper: Use 'make mrproper' before each reconfigure
+ per_board_out_dir: True to build in a separate persistent directory per
+ board rather than a thread-specific directory
+ test_exception: Used for testing; True to raise an exception instead of
+ reporting the build result
"""
- def __init__(self, builder, thread_num, mrproper, per_board_out_dir):
+ def __init__(self, builder, thread_num, mrproper, per_board_out_dir,
+ test_exception=False):
"""Set up a new builder thread"""
threading.Thread.__init__(self)
self.builder = builder
self.thread_num = thread_num
self.mrproper = mrproper
self.per_board_out_dir = per_board_out_dir
+ self.test_exception = test_exception
def Make(self, commit, brd, stage, cwd, *args, **kwargs):
"""Run 'make' on a particular commit and board.
@@ -344,10 +351,9 @@
# Write out the image and function size information and an objdump
env = result.toolchain.MakeEnvironment(self.builder.full_path)
- with open(os.path.join(build_dir, 'out-env'), 'w',
- encoding='utf-8') as fd:
+ with open(os.path.join(build_dir, 'out-env'), 'wb') as fd:
for var in sorted(env.keys()):
- print('%s="%s"' % (var, env[var]), file=fd)
+ fd.write(b'%s="%s"' % (var, env[var]))
lines = []
for fname in BASE_ELF_FILENAMES:
cmd = ['%snm' % self.toolchain.cross, '--size-sort', fname]
@@ -440,6 +446,22 @@
target = '%s-%s%s' % (base, dirname, ext)
shutil.copy(fname, os.path.join(build_dir, target))
+ def _SendResult(self, result):
+ """Send a result to the builder for processing
+
+ Args:
+ result: CommandResult object containing the results of the build
+
+ Raises:
+ ValueError if self.test_exception is true (for testing)
+ """
+ if self.test_exception:
+ raise ValueError('test exception')
+ if self.thread_num != -1:
+ self.builder.out_queue.put(result)
+ else:
+ self.builder.ProcessResult(result)
+
def RunJob(self, job):
"""Run a single job
@@ -513,10 +535,7 @@
# We have the build results, so output the result
self._WriteResult(result, job.keep_outputs, job.work_in_output)
- if self.thread_num != -1:
- self.builder.out_queue.put(result)
- else:
- self.builder.ProcessResult(result)
+ self._SendResult(result)
else:
# Just build the currently checked-out build
result, request_config = self.RunCommit(None, brd, work_dir, True,
@@ -525,10 +544,7 @@
work_in_output=job.work_in_output)
result.commit_upto = 0
self._WriteResult(result, job.keep_outputs, job.work_in_output)
- if self.thread_num != -1:
- self.builder.out_queue.put(result)
- else:
- self.builder.ProcessResult(result)
+ self._SendResult(result)
def run(self):
"""Our thread's run function
@@ -538,5 +554,9 @@
"""
while True:
job = self.builder.queue.get()
- self.RunJob(job)
+ try:
+ self.RunJob(job)
+ except Exception as e:
+ print('Thread exception:', e)
+ self.builder.thread_exceptions.append(e)
self.builder.queue.task_done()
diff --git a/tools/buildman/control.py b/tools/buildman/control.py
index a767570..a98d1b4 100644
--- a/tools/buildman/control.py
+++ b/tools/buildman/control.py
@@ -110,7 +110,7 @@
return None
def DoBuildman(options, args, toolchains=None, make_func=None, boards=None,
- clean_dir=False):
+ clean_dir=False, test_thread_exceptions=False):
"""The main control code for buildman
Args:
@@ -124,6 +124,11 @@
arguments. This setting is useful for tests.
board: Boards() object to use, containing a list of available
boards. If this is None it will be created and scanned.
+ clean_dir: Used for tests only, indicates that the existing output_dir
+ should be removed before starting the build
+ test_thread_exceptions: Uses for tests only, True to make the threads
+ raise an exception instead of reporting their result. This simulates
+ a failure in the code somewhere
"""
global builder
@@ -328,7 +333,8 @@
config_only=options.config_only,
squash_config_y=not options.preserve_config_y,
warnings_as_errors=options.warnings_as_errors,
- work_in_output=options.work_in_output)
+ work_in_output=options.work_in_output,
+ test_thread_exceptions=test_thread_exceptions)
builder.force_config_on_failure = not options.quick
if make_func:
builder.do_make = make_func
@@ -368,9 +374,11 @@
if options.summary:
builder.ShowSummary(commits, board_selected)
else:
- fail, warned = builder.BuildBoards(commits, board_selected,
- options.keep_outputs, options.verbose)
- if fail:
+ fail, warned, excs = builder.BuildBoards(
+ commits, board_selected, options.keep_outputs, options.verbose)
+ if excs:
+ return 102
+ elif fail:
return 100
elif warned and not options.ignore_warnings:
return 101
diff --git a/tools/buildman/func_test.py b/tools/buildman/func_test.py
index 3dd2e6e..7edbee0 100644
--- a/tools/buildman/func_test.py
+++ b/tools/buildman/func_test.py
@@ -16,6 +16,7 @@
from patman import command
from patman import gitutil
from patman import terminal
+from patman import test_util
from patman import tools
settings_data = '''
@@ -219,12 +220,28 @@
return command.RunPipe([[self._buildman_pathname] + list(args)],
capture=True, capture_stderr=True)
- def _RunControl(self, *args, clean_dir=False, boards=None):
+ def _RunControl(self, *args, boards=None, clean_dir=False,
+ test_thread_exceptions=False):
+ """Run buildman
+
+ Args:
+ args: List of arguments to pass
+ boards:
+ clean_dir: Used for tests only, indicates that the existing output_dir
+ should be removed before starting the build
+ test_thread_exceptions: Uses for tests only, True to make the threads
+ raise an exception instead of reporting their result. This simulates
+ a failure in the code somewhere
+
+ Returns:
+ result code from buildman
+ """
sys.argv = [sys.argv[0]] + list(args)
options, args = cmdline.ParseArgs()
result = control.DoBuildman(options, args, toolchains=self._toolchains,
make_func=self._HandleMake, boards=boards or self._boards,
- clean_dir=clean_dir)
+ clean_dir=clean_dir,
+ test_thread_exceptions=test_thread_exceptions)
self._builder = control.builder
return result
@@ -555,6 +572,18 @@
self.assertTrue(os.path.exists(os.path.join(board0_dir, 'done')))
self.assertTrue(os.path.exists(os.path.join(board0_dir, 'out-env')))
+ def testEnvironmentUnicode(self):
+ """Test there are no unicode errors when the env has non-ASCII chars"""
+ try:
+ varname = b'buildman_test_var'
+ os.environb[varname] = b'strange\x80chars'
+ self.assertEqual(0, self._RunControl('-o', self._output_dir))
+ board0_dir = os.path.join(self._output_dir, 'current', 'board0')
+ self.assertTrue(os.path.exists(os.path.join(board0_dir, 'done')))
+ self.assertTrue(os.path.exists(os.path.join(board0_dir, 'out-env')))
+ finally:
+ del os.environb[varname]
+
def testWorkInOutput(self):
"""Test the -w option which should write directly to the output dir"""
board_list = board.Boards()
@@ -588,3 +617,10 @@
with self.assertRaises(SystemExit) as e:
self._RunControl('-w', clean_dir=False)
self.assertIn("specify -o", str(e.exception))
+
+ def testThreadExceptions(self):
+ """Test that exceptions in threads are reported"""
+ with test_util.capture_sys_output() as (stdout, stderr):
+ self.assertEqual(102, self._RunControl('-o', self._output_dir,
+ test_thread_exceptions=True))
+ self.assertIn('Thread exception: test exception', stdout.getvalue())
diff --git a/tools/buildman/toolchain.py b/tools/buildman/toolchain.py
index acb5a29..fd137f7 100644
--- a/tools/buildman/toolchain.py
+++ b/tools/buildman/toolchain.py
@@ -179,27 +179,35 @@
output and possibly unicode encoded output of all build tools by
adding LC_ALL=C.
+ Note that os.environb is used to obtain the environment, since in some
+ cases the environment many contain non-ASCII characters and we see
+ errors like:
+
+ UnicodeEncodeError: 'utf-8' codec can't encode characters in position
+ 569-570: surrogates not allowed
+
Args:
full_path: Return the full path in CROSS_COMPILE and don't set
PATH
Returns:
- Dict containing the environemnt to use. This is based on the current
- environment, with changes as needed to CROSS_COMPILE, PATH and
- LC_ALL.
+ Dict containing the (bytes) environment to use. This is based on the
+ current environment, with changes as needed to CROSS_COMPILE, PATH
+ and LC_ALL.
"""
- env = dict(os.environ)
+ env = dict(os.environb)
wrapper = self.GetWrapper()
if self.override_toolchain:
# We'll use MakeArgs() to provide this
pass
elif full_path:
- env['CROSS_COMPILE'] = wrapper + os.path.join(self.path, self.cross)
+ env[b'CROSS_COMPILE'] = tools.ToBytes(
+ wrapper + os.path.join(self.path, self.cross))
else:
- env['CROSS_COMPILE'] = wrapper + self.cross
- env['PATH'] = self.path + ':' + env['PATH']
+ env[b'CROSS_COMPILE'] = tools.ToBytes(wrapper + self.cross)
+ env[b'PATH'] = tools.ToBytes(self.path) + b':' + env[b'PATH']
- env['LC_ALL'] = 'C'
+ env[b'LC_ALL'] = b'C'
return env
diff --git a/tools/dtoc/dtb_platdata.py b/tools/dtoc/dtb_platdata.py
index 1374f01..2d42480 100644
--- a/tools/dtoc/dtb_platdata.py
+++ b/tools/dtoc/dtb_platdata.py
@@ -824,8 +824,6 @@
self.buf('\t},\n')
def generate_uclasses(self):
- if not self.check_instantiate(True):
- return
self.out('\n')
self.out('#include <common.h>\n')
self.out('#include <dm.h>\n')
@@ -1038,22 +1036,6 @@
self.out(''.join(self.get_buf()))
- def check_instantiate(self, require):
- """Check if self._instantiate is set to the required value
-
- If not, this outputs a message into the current file
-
- Args:
- require: True to require --instantiate, False to require that it not
- be enabled
- """
- if require != self._instantiate:
- self.out(
- '/* This file is not used: --instantiate was %senabled */\n' %
- ('not ' if require else ''))
- return False
- return True
-
def generate_plat(self):
"""Generate device defintions for the platform data
@@ -1064,8 +1046,6 @@
See the documentation in doc/driver-model/of-plat.rst for more
information.
"""
- if not self.check_instantiate(False):
- return
self.out('/* Allow use of U_BOOT_DRVINFO() in this file */\n')
self.out('#define DT_PLAT_C\n')
self.out('\n')
@@ -1102,8 +1082,6 @@
See the documentation in doc/driver-model/of-plat.rst for more
information.
"""
- if not self.check_instantiate(True):
- return
self.out('#include <common.h>\n')
self.out('#include <dm.h>\n')
self.out('#include <dt-structs.h>\n')
@@ -1216,7 +1194,7 @@
plat.assign_seqs()
# Figure out what output files we plan to generate
- output_files = OUTPUT_FILES_COMMON
+ output_files = dict(OUTPUT_FILES_COMMON)
if instantiate:
output_files.update(OUTPUT_FILES_INST)
else:
diff --git a/tools/dtoc/test_dtoc.py b/tools/dtoc/test_dtoc.py
index a05e3d9..0b2805f 100755
--- a/tools/dtoc/test_dtoc.py
+++ b/tools/dtoc/test_dtoc.py
@@ -74,10 +74,6 @@
*/
'''
-UCLASS_HEADER = UCLASS_HEADER_COMMON + '''
-/* This file is not used: --instantiate was not enabled */
-'''
-
# Scanner saved from a previous run of the tests (to speed things up)
saved_scan = None
@@ -412,7 +408,6 @@
};
'''
- uclass_text = UCLASS_HEADER
uclass_text_inst = '''
#include <common.h>
@@ -511,15 +506,6 @@
},
};
-'''
- device_text = '''/*
- * DO NOT MODIFY
- *
- * Declares the DM_DEVICE_INST() records.
- * This was generated by dtoc from a .dtb (device tree binary) file.
- */
-
-/* This file is not used: --instantiate was not enabled */
'''
device_text_inst = '''/*
* DO NOT MODIFY
@@ -833,8 +819,7 @@
self.run_test(['all'], dtb_file, output)
data = tools.ReadFile(output, binary=False)
self._check_strings(
- self.decl_text + self.device_text + self.platdata_text +
- self.struct_text + self.uclass_text, data)
+ self.decl_text + self.platdata_text + self.struct_text, data)
def test_driver_alias(self):
"""Test output from a device tree file with a driver alias"""
@@ -1537,8 +1522,7 @@
self.run_test(['all'], dtb_file, output)
data = tools.ReadFile(output, binary=False)
self._check_strings(
- self.decl_text + self.device_text + self.platdata_text +
- self.struct_text + self.uclass_text, data)
+ self.decl_text + self.platdata_text + self.struct_text, data)
def test_no_command(self):
"""Test running dtoc without a command"""
@@ -1566,8 +1550,7 @@
self.assertIn("Must specify either output or output_dirs, not both",
str(exc.exception))
- def test_output_dirs(self):
- """Test outputting files to a directory"""
+ def check_output_dirs(self, instantiate):
# Remove the directory so that files from other tests are not there
tools._RemoveOutputDir()
tools.PrepareOutputDir(None)
@@ -1579,14 +1562,30 @@
self.assertEqual(2, len(fnames))
dtb_platdata.run_steps(
- ['all'], dtb_file, False, None, [outdir], None, False,
+ ['all'], dtb_file, False, None, [outdir], None, instantiate,
warning_disabled=True, scan=copy_scan())
fnames = glob.glob(outdir + '/*')
- self.assertEqual(7, len(fnames))
+ return fnames
+
+ def test_output_dirs(self):
+ """Test outputting files to a directory"""
+ fnames = self.check_output_dirs(False)
+ self.assertEqual(5, len(fnames))
leafs = set(os.path.basename(fname) for fname in fnames)
self.assertEqual(
{'dt-structs-gen.h', 'source.dts', 'dt-plat.c', 'source.dtb',
+ 'dt-decl.h'},
+ leafs)
+
+ def test_output_dirs_inst(self):
+ """Test outputting files to a directory with instantiation"""
+ fnames = self.check_output_dirs(True)
+ self.assertEqual(6, len(fnames))
+
+ leafs = set(os.path.basename(fname) for fname in fnames)
+ self.assertEqual(
+ {'dt-structs-gen.h', 'source.dts', 'source.dtb',
'dt-uclass.c', 'dt-decl.h', 'dt-device.c'},
leafs)
@@ -1785,14 +1784,6 @@
self._check_strings(self.decl_text_inst, data)
- self.run_test(['platdata'], dtb_file, output, True)
- with open(output) as infile:
- data = infile.read()
-
- self._check_strings(C_HEADER_PRE + '''
-/* This file is not used: --instantiate was enabled */
-''', data)
-
self.run_test(['uclass'], dtb_file, output, True)
with open(output) as infile:
data = infile.read()
diff --git a/tools/k3_fit_atf.sh b/tools/k3_fit_atf.sh
index 4e9f69c..3a476ce 100755
--- a/tools/k3_fit_atf.sh
+++ b/tools/k3_fit_atf.sh
@@ -5,7 +5,7 @@
# ATF, OPTEE, SPL and multiple device trees (given on the command line).
# Inspired from board/sunxi/mksunxi_fit_atf.sh
#
-# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
+# usage: $0 <atf_load_addr> <dt_name> [<dt_name> [<dt_name] ...]
[ -z "$ATF" ] && ATF="bl31.bin"
@@ -21,6 +21,13 @@
TEE=/dev/null
fi
+[ -z "$DM" ] && DM="dm.bin"
+
+if [ ! -e $DM ]; then
+ echo "WARNING DM file $DM NOT found, resulting might be non-functional" >&2
+ DM=/dev/null
+fi
+
if [ ! -z "$IS_HS" ]; then
HS_APPEND=_HS
fi
@@ -40,8 +47,8 @@
arch = "arm64";
compression = "none";
os = "arm-trusted-firmware";
- load = <0x70000000>;
- entry = <0x70000000>;
+ load = <$1>;
+ entry = <$1>;
};
tee {
description = "OPTEE";
@@ -53,6 +60,16 @@
load = <0x9e800000>;
entry = <0x9e800000>;
};
+ dm {
+ description = "DM binary";
+ data = /incbin/("$DM");
+ type = "firmware";
+ arch = "arm32";
+ compression = "none";
+ os = "DM";
+ load = <0xa0000000>;
+ entry = <0xa0000000>;
+ };
spl {
description = "SPL (64-bit)";
data = /incbin/("spl/u-boot-spl-nodtb.bin$HS_APPEND");
@@ -65,6 +82,9 @@
};
__HEADER_EOF
+# shift through ATF load address in the command line arguments
+shift
+
for dtname in $*
do
cat << __FDT_IMAGE_EOF
@@ -91,7 +111,7 @@
$(basename $dtname) {
description = "$(basename $dtname .dtb)";
firmware = "atf";
- loadables = "tee", "spl";
+ loadables = "tee", "dm", "spl";
fdt = "$(basename $dtname)";
};
__CONF_SECTION_EOF
diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py
index 63a8e37..8978df2 100644
--- a/tools/patman/checkpatch.py
+++ b/tools/patman/checkpatch.py
@@ -10,7 +10,15 @@
from patman import command
from patman import gitutil
from patman import terminal
-from patman import tools
+
+EMACS_PREFIX = r'(?:[0-9]{4}.*\.patch:[0-9]+: )?'
+TYPE_NAME = r'([A-Z_]+:)?'
+RE_ERROR = re.compile(r'ERROR:%s (.*)' % TYPE_NAME)
+RE_WARNING = re.compile(EMACS_PREFIX + r'WARNING:%s (.*)' % TYPE_NAME)
+RE_CHECK = re.compile(r'CHECK:%s (.*)' % TYPE_NAME)
+RE_FILE = re.compile(r'#(\d+): (FILE: ([^:]*):(\d+):)?')
+RE_NOTE = re.compile(r'NOTE: (.*)')
+
def FindCheckPatch():
top_level = gitutil.GetTopLevel()
@@ -38,14 +46,81 @@
sys.exit('Cannot find checkpatch.pl - please put it in your ' +
'~/bin directory or use --no-check')
-def CheckPatch(fname, verbose=False, show_types=False):
- """Run checkpatch.pl on a file.
+
+def CheckPatchParseOneMessage(message):
+ """Parse one checkpatch message
Args:
- fname: Filename to check
+ message: string to parse
+
+ Returns:
+ dict:
+ 'type'; error or warning
+ 'msg': text message
+ 'file' : filename
+ 'line': line number
+ """
+
+ if RE_NOTE.match(message):
+ return {}
+
+ item = {}
+
+ err_match = RE_ERROR.match(message)
+ warn_match = RE_WARNING.match(message)
+ check_match = RE_CHECK.match(message)
+ if err_match:
+ item['cptype'] = err_match.group(1)
+ item['msg'] = err_match.group(2)
+ item['type'] = 'error'
+ elif warn_match:
+ item['cptype'] = warn_match.group(1)
+ item['msg'] = warn_match.group(2)
+ item['type'] = 'warning'
+ elif check_match:
+ item['cptype'] = check_match.group(1)
+ item['msg'] = check_match.group(2)
+ item['type'] = 'check'
+ else:
+ message_indent = ' '
+ print('patman: failed to parse checkpatch message:\n%s' %
+ (message_indent + message.replace('\n', '\n' + message_indent)),
+ file=sys.stderr)
+ return {}
+
+ file_match = RE_FILE.search(message)
+ # some messages have no file, catch those here
+ no_file_match = any(s in message for s in [
+ '\nSubject:', 'Missing Signed-off-by: line(s)',
+ 'does MAINTAINERS need updating'
+ ])
+
+ if file_match:
+ err_fname = file_match.group(3)
+ if err_fname:
+ item['file'] = err_fname
+ item['line'] = int(file_match.group(4))
+ else:
+ item['file'] = '<patch>'
+ item['line'] = int(file_match.group(1))
+ elif no_file_match:
+ item['file'] = '<patch>'
+ else:
+ message_indent = ' '
+ print('patman: failed to find file / line information:\n%s' %
+ (message_indent + message.replace('\n', '\n' + message_indent)),
+ file=sys.stderr)
+
+ return item
+
+
+def CheckPatchParse(checkpatch_output, verbose=False):
+ """Parse checkpatch.pl output
+
+ Args:
+ checkpatch_output: string to parse
verbose: True to print out every line of the checkpatch output as it is
parsed
- show_types: Tell checkpatch to show the type (number) of each message
Returns:
namedtuple containing:
@@ -59,67 +134,38 @@
warnings: Number of warnings
checks: Number of checks
lines: Number of lines
- stdout: Full output of checkpatch
+ stdout: checkpatch_output
"""
fields = ['ok', 'problems', 'errors', 'warnings', 'checks', 'lines',
'stdout']
result = collections.namedtuple('CheckPatchResult', fields)
+ result.stdout = checkpatch_output
result.ok = False
result.errors, result.warnings, result.checks = 0, 0, 0
result.lines = 0
result.problems = []
- chk = FindCheckPatch()
- item = {}
- args = [chk, '--no-tree']
- if show_types:
- args.append('--show-types')
- result.stdout = command.Output(*args, fname, raise_on_error=False)
- #pipe = subprocess.Popen(cmd, stdout=subprocess.PIPE)
- #stdout, stderr = pipe.communicate()
# total: 0 errors, 0 warnings, 159 lines checked
# or:
# total: 0 errors, 2 warnings, 7 checks, 473 lines checked
- emacs_prefix = '(?:[0-9]{4}.*\.patch:[0-9]+: )?'
- emacs_stats = '(?:[0-9]{4}.*\.patch )?'
+ emacs_stats = r'(?:[0-9]{4}.*\.patch )?'
re_stats = re.compile(emacs_stats +
- 'total: (\\d+) errors, (\d+) warnings, (\d+)')
+ r'total: (\d+) errors, (\d+) warnings, (\d+)')
re_stats_full = re.compile(emacs_stats +
- 'total: (\\d+) errors, (\d+) warnings, (\d+)'
- ' checks, (\d+)')
- re_ok = re.compile('.*has no obvious style problems')
- re_bad = re.compile('.*has style problems, please review')
- type_name = '([A-Z_]+:)?'
- re_error = re.compile('ERROR:%s (.*)' % type_name)
- re_warning = re.compile(emacs_prefix + 'WARNING:%s (.*)' % type_name)
- re_check = re.compile('CHECK:%s (.*)' % type_name)
- re_file = re.compile('#(\d+): (FILE: ([^:]*):(\d+):)?')
- re_note = re.compile('NOTE: (.*)')
- re_new_file = re.compile('new file mode .*')
- indent = ' ' * 6
- for line in result.stdout.splitlines():
+ r'total: (\d+) errors, (\d+) warnings, (\d+)'
+ r' checks, (\d+)')
+ re_ok = re.compile(r'.*has no obvious style problems')
+ re_bad = re.compile(r'.*has style problems, please review')
+
+ # A blank line indicates the end of a message
+ for message in result.stdout.split('\n\n'):
if verbose:
- print(line)
+ print(message)
- # A blank line indicates the end of a message
- if not line:
- if item:
- result.problems.append(item)
- item = {}
- continue
- if re_note.match(line):
- continue
- # Skip lines which quote code
- if line.startswith(indent):
- continue
- # Skip code quotes
- if line.startswith('+'):
- continue
- if re_new_file.match(line):
- continue
- match = re_stats_full.match(line)
+ # either find stats, the verdict, or delegate
+ match = re_stats_full.match(message)
if not match:
- match = re_stats.match(line)
+ match = re_stats.match(message)
if match:
result.errors = int(match.group(1))
result.warnings = int(match.group(2))
@@ -128,46 +174,50 @@
result.lines = int(match.group(4))
else:
result.lines = int(match.group(3))
- continue
- elif re_ok.match(line):
+ elif re_ok.match(message):
result.ok = True
- continue
- elif re_bad.match(line):
+ elif re_bad.match(message):
result.ok = False
- continue
- err_match = re_error.match(line)
- warn_match = re_warning.match(line)
- file_match = re_file.match(line)
- check_match = re_check.match(line)
- subject_match = line.startswith('Subject:')
- if err_match:
- item['cptype'] = err_match.group(1)
- item['msg'] = err_match.group(2)
- item['type'] = 'error'
- elif warn_match:
- item['cptype'] = warn_match.group(1)
- item['msg'] = warn_match.group(2)
- item['type'] = 'warning'
- elif check_match:
- item['cptype'] = check_match.group(1)
- item['msg'] = check_match.group(2)
- item['type'] = 'check'
- elif file_match:
- err_fname = file_match.group(3)
- if err_fname:
- item['file'] = err_fname
- item['line'] = int(file_match.group(4))
- else:
- item['file'] = '<patch>'
- item['line'] = int(file_match.group(1))
- elif subject_match:
- item['file'] = '<patch subject>'
- item['line'] = None
else:
- print('bad line "%s", %d' % (line, len(line)))
+ problem = CheckPatchParseOneMessage(message)
+ if problem:
+ result.problems.append(problem)
return result
+
+def CheckPatch(fname, verbose=False, show_types=False):
+ """Run checkpatch.pl on a file and parse the results.
+
+ Args:
+ fname: Filename to check
+ verbose: True to print out every line of the checkpatch output as it is
+ parsed
+ show_types: Tell checkpatch to show the type (number) of each message
+
+ Returns:
+ namedtuple containing:
+ ok: False=failure, True=ok
+ problems: List of problems, each a dict:
+ 'type'; error or warning
+ 'msg': text message
+ 'file' : filename
+ 'line': line number
+ errors: Number of errors
+ warnings: Number of warnings
+ checks: Number of checks
+ lines: Number of lines
+ stdout: Full output of checkpatch
+ """
+ chk = FindCheckPatch()
+ args = [chk, '--no-tree']
+ if show_types:
+ args.append('--show-types')
+ output = command.Output(*args, fname, raise_on_error=False)
+
+ return CheckPatchParse(output, verbose)
+
+
def GetWarningMsg(col, msg_type, fname, line, msg):
'''Create a message for a given file/line
diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py
index 450fe66..1ce6448 100644
--- a/tools/patman/func_test.py
+++ b/tools/patman/func_test.py
@@ -25,13 +25,8 @@
from patman import tools
from patman.test_util import capture_sys_output
-try:
- import pygit2
- HAVE_PYGIT2 = True
- from patman import status
-except ModuleNotFoundError:
- HAVE_PYGIT2 = False
-
+import pygit2
+from patman import status
class TestFunctional(unittest.TestCase):
"""Functional tests for checking that patman behaves correctly"""
@@ -458,7 +453,6 @@
repo.branches.local.create('base', base_target)
return repo
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testBranch(self):
"""Test creating patches from a branch"""
repo = self.make_git_tree()
@@ -604,7 +598,6 @@
["Found possible blank line(s) at end of file 'lib/fdtdec.c'"],
pstrm.commit.warn)
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testNoUpstream(self):
"""Test CountCommitsToBranch when there is no upstream"""
repo = self.make_git_tree()
@@ -642,7 +635,6 @@
{'id': '1', 'name': 'Some patch'}]}
raise ValueError('Fake Patchwork does not understand: %s' % subpath)
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testStatusMismatch(self):
"""Test Patchwork patches not matching the series"""
series = Series()
@@ -652,7 +644,6 @@
self.assertIn('Warning: Patchwork reports 1 patches, series has 0',
err.getvalue())
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testStatusReadPatch(self):
"""Test handling a single patch in Patchwork"""
series = Series()
@@ -665,7 +656,6 @@
self.assertEqual('1', patch.id)
self.assertEqual('Some patch', patch.raw_subject)
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testParseSubject(self):
"""Test parsing of the patch subject"""
patch = status.Patch('1')
@@ -728,7 +718,6 @@
self.assertEqual('RESEND', patch.prefix)
self.assertEqual(None, patch.version)
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testCompareSeries(self):
"""Test operation of compare_with_series()"""
commit1 = Commit('abcd')
@@ -831,7 +820,6 @@
return patch.comments
raise ValueError('Fake Patchwork does not understand: %s' % subpath)
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testFindNewResponses(self):
"""Test operation of find_new_responses()"""
commit1 = Commit('abcd')
@@ -970,7 +958,6 @@
return patch.comments
raise ValueError('Fake Patchwork does not understand: %s' % subpath)
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testCreateBranch(self):
"""Test operation of create_branch()"""
repo = self.make_git_tree()
@@ -1058,7 +1045,6 @@
self.assertEqual('Reviewed-by: %s' % self.mary, next(lines))
self.assertEqual('Tested-by: %s' % self.leb, next(lines))
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testParseSnippets(self):
"""Test parsing of review snippets"""
text = '''Hi Fred,
@@ -1142,7 +1128,6 @@
'line2', 'line3', 'line4', 'line5', 'line6', 'line7', 'line8']],
pstrm.snippets)
- @unittest.skipIf(not HAVE_PYGIT2, 'Missing python3-pygit2')
def testReviewSnippets(self):
"""Test showing of review snippets"""
def _to_submitter(who):