| commit | 48ddbe8249277764231307c5e0aef15fde4c065d | [log] [tgz] |
|---|---|---|
| author | Mingkai Hu <mingkai.hu@nxp.com> | Wed Sep 07 17:56:08 2016 +0800 |
| committer | York Sun <york.sun@nxp.com> | Wed Sep 14 14:10:02 2016 -0700 |
| tree | a5bc36d5777e7938a0c7198fd9e94b3d9174f70e | |
| parent | fd4d7bb904ef640a6f2986c0c39fa313ea23e25f [diff] |
armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency According to design specification, the L2 cache operates at the same frequency as the A72 CPUs in the cluster with a 3-cycle latency, so increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else, will run into different call trace issues. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>