tree cae931b06803cf6ff873209a52e5e7dd706beb26
parent 2f4d36562e7055a82cf9de482ea73c2ec890ab6c
author Kumar Gala <galak@kernel.crashing.org> 1269634483 -0500
committer Kumar Gala <galak@kernel.crashing.org> 1269964110 -0500

85xx: Fix enabling of L1 cache parity on secondary cores

Use the same code between primary and secondary cores to init the
L1 cache.  We were not enabling cache parity on the secondary cores.

Also, reworked the L1 cache init code to match the e500mc L2 init code
that first invalidates the cache and locks.  Than enables the cache and
makes sure its enabled before continuing.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>