Merge tag 'u-boot-rockchip-20250110' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
CI: https://source.denx.de/u-boot/custodians/u-boot-rockchip/-/pipelines/24129
- Add boards:
rk3566: FriendlyARM NanoPi R3S
rk3588s: Radxa ROCK 5C,
rk3588: Khadas Edge2
- Migrate to OF_UPSTREAM:
rk3066a/rk3188;
rk3288: tinker, miqi, firefly;
- Migrate to TPL: rk3399 kevin and bob;
diff --git a/drivers/watchdog/rti_wdt.c b/drivers/watchdog/rti_wdt.c
index 99168d0..7b38726 100644
--- a/drivers/watchdog/rti_wdt.c
+++ b/drivers/watchdog/rti_wdt.c
@@ -131,18 +131,19 @@
u32 timer_margin;
int ret;
- if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY)
+ timer_margin = timeout_ms * priv->clk_hz / 1000;
+ timer_margin >>= WDT_PRELOAD_SHIFT;
+ if (timer_margin > WDT_PRELOAD_MAX)
+ timer_margin = WDT_PRELOAD_MAX;
+
+ if (readl(priv->regs + RTIDWDCTRL) == WDENABLE_KEY &&
+ readl(priv->regs + RTIDWDPRLD) != timer_margin)
return -EBUSY;
ret = rti_wdt_load_fw(dev);
if (ret < 0)
return ret;
- timer_margin = timeout_ms * priv->clk_hz / 1000;
- timer_margin >>= WDT_PRELOAD_SHIFT;
- if (timer_margin > WDT_PRELOAD_MAX)
- timer_margin = WDT_PRELOAD_MAX;
-
writel(timer_margin, priv->regs + RTIDWDPRLD);
writel(RTIWWDRX_NMI, priv->regs + RTIWWDRXCTRL);
writel(RTIWWDSIZE_50P, priv->regs + RTIWWDSIZECTRL);
@@ -186,14 +187,6 @@
priv->clk_hz = clk_get_rate(&clk);
- /*
- * If watchdog is running at 32k clock, it is not accurate.
- * Adjust frequency down in this case so that it does not expire
- * earlier than expected.
- */
- if (priv->clk_hz < 32768)
- priv->clk_hz = priv->clk_hz * 9 / 10;
-
return 0;
}