| /* |
| * Copyright 2009-2010 Freescale Semiconductor, Inc. |
| * |
| * SPDX-License-Identifier: GPL-2.0+ |
| */ |
| |
| #include <common.h> |
| #include <ns16550.h> |
| #include <asm/io.h> |
| #include <nand.h> |
| |
| u32 sysclk_tbl[] = { |
| 33333000, 39999600, 49999500, 66666000, |
| 83332500, 99999000, 133332000, 166665000 |
| }; |
| |
| void board_init_f(ulong bootflag) |
| { |
| int px_spd; |
| u32 plat_ratio, bus_clk, sys_clk; |
| ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; |
| |
| #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM) |
| /* for FPGA */ |
| set_lbc_br(3, CONFIG_SYS_BR3_PRELIM); |
| set_lbc_or(3, CONFIG_SYS_OR3_PRELIM); |
| #else |
| #error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined |
| #endif |
| |
| /* initialize selected port with appropriate baud rate */ |
| px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD)); |
| sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK]; |
| plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; |
| bus_clk = sys_clk * plat_ratio / 2; |
| |
| NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, |
| bus_clk / 16 / CONFIG_BAUDRATE); |
| |
| puts("\nNAND boot... "); |
| |
| /* copy code to RAM and jump to it - this should not return */ |
| /* NOTE - code has to be copied out of NAND buffer before |
| * other blocks can be read. |
| */ |
| relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0, |
| CONFIG_SYS_NAND_U_BOOT_RELOC); |
| } |
| |
| void board_init_r(gd_t *gd, ulong dest_addr) |
| { |
| nand_boot(); |
| } |
| |
| void putc(char c) |
| { |
| if (c == '\n') |
| NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); |
| |
| NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); |
| } |
| |
| void puts(const char *str) |
| { |
| while (*str) |
| putc(*str++); |
| } |