commit 4843ad3270a0cf406c6e338f8858345e86271625
author developer <developer@mediatek.com> Mon Jan 22 10:08:11 2024 +0800
committer Tom Rini <trini@konsulko.com> Fri Mar 01 16:35:52 2024 -0500
tree 5ab81952ed7259a3102d942b01ef32705a0fd7ea
parent 4c813af477f76dbec1c6f7ed625cba48d3a9e268

net: mediatek: add support for adjusting MDIO clock

User can assign a specific MDC speed to the eth node as follow:

&eth {
	...
	phy-mode = "usxgmii";
	phy-handle = <&phy8>;

	mdio {
		clock-frequency = <10500000>;
	};

	phy8: eth-phy@8 {
	      compatible = "ethernet-phy-id31c3.1c12";
	...
};

drivers/net/mtk_eth.h

diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h
index 491cac5..45229c0 100644
--- a/drivers/net/mtk_eth.h
+++ b/drivers/net/mtk_eth.h
@@ -180,6 +180,12 @@
 
 /* GMAC Registers */
 
+#define GMAC_PPSC_REG			0x0000
+#define PHY_MDC_CFG			GENMASK(29, 24)
+#define MDC_TURBO			BIT(20)
+#define MDC_MAX_FREQ			25000000
+#define MDC_MAX_DIVIDER			63
+
 #define GMAC_PIAC_REG			0x0004
 #define PHY_ACS_ST			BIT(31)
 #define MDIO_REG_ADDR_S			25
@@ -197,6 +203,7 @@
 #define P1_XGMAC_FORCE_LINK		BIT(15)
 
 #define GMAC_MAC_MISC_REG		0x0010
+#define MISC_MDC_TURBO			BIT(4)
 
 #define GMAC_GSW_CFG_REG		0x0080
 #define GSWTX_IPG_M			0xF0000