doc: replace @return by Return:
Sphinx expects Return: and not @return to indicate a return value.
find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;
find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 97f00f5..a1b4496 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -91,7 +91,7 @@
* @scu SCU registers
* @uart_index UART index, 1-5
*
- * @return current setting for uart clock rate
+ * Return: current setting for uart clock rate
*/
static ulong ast2500_get_uart_clk_rate(struct ast2500_scu *scu, int uart_index)
{
@@ -216,7 +216,7 @@
* The result (the best config we could find), would also be returned
* in this structure.
*
- * @return The clock rate, when the resulting div_config is used.
+ * Return: The clock rate, when the resulting div_config is used.
*/
static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate,
struct ast2500_div_config *cfg)
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index 3fb8d68..f191b0f 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -481,7 +481,7 @@
/**
* @brief lookup PLL divider config by input/output rate
* @param[in] *pll - PLL descriptor
- * @return true - if PLL divider config is found, false - else
+ * Return: true - if PLL divider config is found, false - else
* The function caller shall fill "pll->in" and "pll->out",
* then this function will search the lookup table
* to find a valid PLL divider configuration.
diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h
index 8e3fc55..442562a 100644
--- a/drivers/clk/microchip/mpfs_clk.h
+++ b/drivers/clk/microchip/mpfs_clk.h
@@ -13,7 +13,7 @@
* @base: base address of the mpfs system register.
* @clk_rate: the mpfs pll clock rate.
* @parent_name: a pointer to parent clock name.
- * @return zero on success, or a negative error code.
+ * Return: zero on success, or a negative error code.
*/
int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
const char *parent_name);
@@ -23,7 +23,7 @@
* @base: base address of the mpfs system register.
* @clk_rate: the mpfs pll clock rate.
* @parent_name: a pointer to parent clock name.
- * @return zero on success, or a negative error code.
+ * Return: zero on success, or a negative error code.
*/
int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
const char *parent_name);
@@ -35,7 +35,7 @@
* @table: a pointer to clock divider table.
* @width: width of the divider bit field.
* @flags: common clock framework flags.
- * @return divider value on success, or a negative error code.
+ * Return: divider value on success, or a negative error code.
*/
int divider_get_val(unsigned long rate, unsigned long parent_rate,
const struct clk_div_table *table,