Merge with /home/wd/git/u-boot/custodian/u-boot-mpc85xx
diff --git a/Makefile b/Makefile
index f516889..95e9e36 100644
--- a/Makefile
+++ b/Makefile
@@ -212,6 +212,9 @@
ifeq ($(CPU),mpc83xx)
LIBS += drivers/qe/qe.a
endif
+ifeq ($(CPU),mpc85xx)
+LIBS += drivers/qe/qe.a
+endif
LIBS += drivers/sk98lin/libsk98lin.a
LIBS += post/libpost.a post/drivers/libpostdrivers.a
LIBS += $(shell if [ -d post/lib_$(ARCH) ]; then echo \
@@ -1783,17 +1786,38 @@
MPC8560ADS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8560ads
+MPC8541CDS_legacy_config \
MPC8541CDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8541cds cds
+ @mkdir -p $(obj)include
+ @echo "" >$(obj)include/config.h ; \
+ if [ "$(findstring _legacy_,$@)" ] ; then \
+ echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
+ echo "... legacy" ; \
+ fi
+ @$(MKCONFIG) -a MPC8541CDS ppc mpc85xx mpc8541cds cds
MPC8544DS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8544ds freescale
+MPC8548CDS_legacy_config \
MPC8548CDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8548cds cds
+ @mkdir -p $(obj)include
+ @echo "" >$(obj)include/config.h ; \
+ if [ "$(findstring _legacy_,$@)" ] ; then \
+ echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
+ echo "... legacy" ; \
+ fi
+ @$(MKCONFIG) -a MPC8548CDS ppc mpc85xx mpc8548cds cds
+MPC8555CDS_legacy_config \
MPC8555CDS_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8555cds cds
+ @mkdir -p $(obj)include
+ @echo "" >$(obj)include/config.h ; \
+ if [ "$(findstring _legacy_,$@)" ] ; then \
+ echo "#define CONFIG_LEGACY" >>$(obj)include/config.h ; \
+ echo "... legacy" ; \
+ fi
+ @$(MKCONFIG) -a MPC8555CDS ppc mpc85xx mpc8555cds cds
MPC8568MDS_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc85xx mpc8568mds
diff --git a/board/cds/common/via.c b/board/cds/common/via.c
index e79bd02..4a63d77 100644
--- a/board/cds/common/via.c
+++ b/board/cds/common/via.c
@@ -28,11 +28,16 @@
pci_dev_t dev, struct pci_config_table *tab)
{
pci_dev_t bridge;
+ unsigned int cmdstat;
/* Enable USB and IDE functions */
pci_hose_write_config_byte(hose, dev, 0x48, 0x08);
- pciauto_config_device(hose, dev);
+ pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
+ cmdstat |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY| PCI_COMMAND_MASTER;
+ pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
+ pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
+ pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
/*
* Force the backplane P2P bridge to have a window
@@ -40,7 +45,7 @@
* This allows legacy I/O (i8259, etc) on the VIA
* southbridge to be accessed.
*/
- bridge = PCI_BDF(0,17,0);
+ bridge = PCI_BDF(0,BRIDGE_ID,0);
pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0);
pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0);
pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10);
diff --git a/board/cds/mpc8541cds/mpc8541cds.c b/board/cds/mpc8541cds/mpc8541cds.c
index 4192324..558ba99 100644
--- a/board/cds/mpc8541cds/mpc8541cds.c
+++ b/board/cds/mpc8541cds/mpc8541cds.c
@@ -476,14 +476,17 @@
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
{},
};
diff --git a/board/cds/mpc8548cds/config.mk b/board/cds/mpc8548cds/config.mk
index 242a676..b23bc87 100644
--- a/board/cds/mpc8548cds/config.mk
+++ b/board/cds/mpc8548cds/config.mk
@@ -1,5 +1,5 @@
#
-# Copyright 2004 Freescale Semiconductor.
+# Copyright 2004, 2007 Freescale Semiconductor.
#
# See file CREDITS for list of people who contributed to this
# project.
@@ -23,7 +23,9 @@
#
# mpc8548cds board
#
+ifndef TEXT_BASE
TEXT_BASE = 0xfff80000
+endif
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
diff --git a/board/cds/mpc8548cds/init.S b/board/cds/mpc8548cds/init.S
index d468f5b..72940b0 100644
--- a/board/cds/mpc8548cds/init.S
+++ b/board/cds/mpc8548cds/init.S
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* Copyright 2002,2003, Motorola Inc.
*
* See file CREDITS for list of people who contributed to this
@@ -28,6 +28,12 @@
#include <config.h>
#include <mpc85xx.h>
+#define LAWAR_TRGT_PCI1 0x00000000
+#define LAWAR_TRGT_PCI2 0x00100000
+#define LAWAR_TRGT_PCIE 0x00200000
+#define LAWAR_TRGT_RIO 0x00c00000
+#define LAWAR_TRGT_LBC 0x00400000
+#define LAWAR_TRGT_DDR 0x00f00000
/*
* TLB0 and TLB1 Entries
@@ -47,8 +53,8 @@
*/
#define entry_start \
- mflr r1 ; \
- bl 0f ;
+ mflr r1 ; \
+ bl 0f ;
#define entry_end \
0: mflr r0 ; \
@@ -84,8 +90,8 @@
#endif
/*
- * TLB0 16K Cacheable, non-guarded
- * 0xd001_0000 16K Temporary Global data for initialization
+ * TLB0 16K Cacheable, guarded
+ * Temporary Global data for initialization
*
* Use four 4K TLB0 entries. These entries must be cacheable
* as they provide the bootstrap memory before the memory
@@ -97,28 +103,28 @@
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
0,0,0,0,0,1,0,1,0,1)
.long TLB1_MAS0(0, 0, 0)
.long TLB1_MAS1(1, 0, 0, 0, 0)
.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
- 0,0,0,0,0,0,0,0)
+ 0,0,0,0,0,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
0,0,0,0,0,1,0,1,0,1)
@@ -130,51 +136,44 @@
*/
.long TLB1_MAS0(1, 0, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_BOOT_BLOCK), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_BOOT_BLOCK), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLB 1: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM
+ * TLB 1: 1G Non-cacheable, guarded
+ * 0x80000000 1G PCI1/PCIE 8,9,a,b
*/
.long TLB1_MAS0(1, 1, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI_PHYS), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI_PHYS), 0,0,0,0,0,1,0,1,0,1)
+#ifdef CFG_RIO_MEM_PHYS
/*
* TLB 2: 256M Non-cacheable, guarded
- * 0x90000000 256M PCI2 MEM
*/
.long TLB1_MAS0(1, 2, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI2_MEM_BASE),
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS),
0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI2_MEM_BASE),
- 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLB 3: 1GB Non-cacheable, guarded
- * 0xa0000000 256M PEX MEM First half
- * 0xb0000000 256M PEX MEM Second half
- * 0xc0000000 256M Rapid IO MEM First half
- * 0xd0000000 256M Rapid IO MEM Second half
+ * TLB 3: 256M Non-cacheable, guarded
*/
.long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLB 4: Reserved for future usage
- */
-
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_PHYS + 0x10000000),
+ 0,0,0,0,0,1,0,1,0,1)
+#endif
/*
* TLB 5: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 8M PCI1 IO
- * 0xe280_0000 8M PCI2 IO
- * 0xe300_0000 16M PEX IO
+ * 0xe200_0000 1M PCI1 IO
+ * 0xe210_0000 1M PCI2 IO
+ * 0xe300_0000 1M PCIe IO
*/
.long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
@@ -187,17 +186,18 @@
*/
.long TLB1_MAS0(1, 6, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,0,0,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_CACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLB 7: 1M Non-cacheable, guarded
- * 0xf8000000 1M CADMUS registers
+ * TLB 7: 64M Non-cacheable, guarded
+ * 0xf8000000 64M CADMUS registers, relocated L2SRAM
*/
.long TLB1_MAS0(1, 7, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1M)
- .long TLB1_MAS2(E500_TLB_EPN(CADMUS_BASE_ADDR), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CADMUS_BASE_ADDR), 0,0,0,0,0,1,0,1,0,1)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
+ .long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,1,0,1,0)
+ .long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_NONCACHE_BASE), 0,0,0,0,0,1,0,1,0,1)
+
2:
entry_end
@@ -205,14 +205,13 @@
* LAW(Local Access Window) configuration:
*
* 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x8fff_ffff PCI1 MEM 256M
- * 0x9000_0000 0x9fff_ffff PCI2 MEM 256M
- * 0xa000_0000 0xbfff_ffff PEX MEM 512M
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
* 0xc000_0000 0xdfff_ffff RapidIO 512M
* 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe27f_ffff PCI1 IO 8M
- * 0xe280_0000 0xe2ff_ffff PCI2 IO 8M
- * 0xe300_0000 0xe3ff_ffff PEX IO 16M
+ * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
+ * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M
* 0xf000_0000 0xf3ff_ffff SDRAM 64M
* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
@@ -222,47 +221,50 @@
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*
- * The defines below are 1-off of the actual LAWAR0 usage.
- * So LAWAR3 define uses the LAWAR4 register in the ECM.
+ * LAW 0 is reserved for boot mapping
*/
-#define LAWBAR0 0
-#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
-
-#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+ .section .bootpg, "ax"
+ .globl law_entry
+law_entry:
+ entry_start
-#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+ .long (4f-3f)/8
+3:
+ .long 0
+ .long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
-#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
-#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+#ifdef CFG_PCI1_MEM_PHYS
+ .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#define LAWBAR4 ((CFG_PCI2_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_8M))
+ .long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
-/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-#define LAWBAR5 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#ifdef CFG_PCI2_MEM_PHYS
+ .long (CFG_PCI2_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#define LAWBAR6 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
+ .long (CFG_PCI2_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
-#define LAWBAR7 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#ifdef CFG_PCIE1_MEM_PHYS
+ .long (CFG_PCIE1_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_512M)
-#define LAWBAR8 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
+ .long (CFG_PCIE1_IO_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_PCIE | (LAWAR_SIZE & LAWAR_SIZE_1M)
+#endif
- .section .bootpg, "ax"
- .globl law_entry
+ /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
+ .long (CFG_LBC_CACHE_BASE>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)
-law_entry:
- entry_start
- .long (4f-3f)/8
-3:
- .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
- .long LAWBAR4,LAWAR4,LAWBAR5,LAWAR5,LAWBAR6,LAWAR6,LAWBAR7,LAWAR7
- .long LAWBAR8,LAWAR8
+#ifdef CFG_RIO_MEM_PHYS
+ .long (CFG_RIO_MEM_PHYS>>12) & 0xfffff
+ .long LAWAR_EN | LAWAR_TRGT_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M)
+#endif
4:
entry_end
diff --git a/board/cds/mpc8548cds/mpc8548cds.c b/board/cds/mpc8548cds/mpc8548cds.c
index b7236417..48753d7 100644
--- a/board/cds/mpc8548cds/mpc8548cds.c
+++ b/board/cds/mpc8548cds/mpc8548cds.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
*
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
*
@@ -26,6 +26,7 @@
#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
#include <spd.h>
#include <miiphy.h>
@@ -33,10 +34,15 @@
#include "../common/eeprom.h"
#include "../common/via.h"
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#endif
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
#endif
+DECLARE_GLOBAL_DATA_PTR;
+
extern long int spd_sdram(void);
void local_bus_init(void);
@@ -56,13 +62,6 @@
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
- uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
- uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
- uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
- uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
-
- uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
-
uint cpu_board_rev = get_cpu_board_revision ();
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
@@ -71,20 +70,6 @@
printf ("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
-
- printf (" PCI1: %d bit, %s MHz, %s\n",
- (pci1_32) ? 32 : 64,
- (pci1_speed == 33000000) ? "33" :
- (pci1_speed == 66000000) ? "66" : "unknown",
- pci1_clk_sel ? "sync" : "async");
-
- if (pci_dual) {
- printf (" PCI2: 32 bit, 66 MHz, %s\n",
- pci2_clk_sel ? "sync" : "async");
- } else {
- printf (" PCI2: disabled\n");
- }
-
/*
* Initialize local bus.
*/
@@ -102,6 +87,8 @@
*/
gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
+ ecm->eedr = 0xffffffff; /* clear ecm errors */
+ ecm->eeer = 0xffffffff; /* enable ecm errors */
return 0;
}
@@ -176,6 +163,9 @@
lbc->lcrr |= 0x00030000;
asm("sync;isync;msync");
+
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
}
/*
@@ -301,7 +291,7 @@
}
#endif
-#if defined(CONFIG_PCI)
+#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
/* For some reason the Tundra PCI bridge shows up on itself as a
* different device. Work around that by refusing to configure it.
*/
@@ -309,32 +299,189 @@
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
{},
};
-static struct pci_controller hose[] = {
- { config_table: pci_mpc85xxcds_config_table,},
-#ifdef CONFIG_MPC85XX_PCI2
- {},
-#endif
-};
-
+static struct pci_controller pci1_hose = {
+ config_table: pci_mpc85xxcds_config_table};
#endif /* CONFIG_PCI */
+#ifdef CONFIG_PCI2
+static struct pci_controller pci2_hose;
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+int first_free_busno=0;
+
void
pci_init_board(void)
{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+ struct pci_config_table *table;
+
+ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+ uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
+
+ uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
+
+ if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter"
+ );
+
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count = 2;
+
+ /* relocate config table pointers */
+ hose->config_table = \
+ (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
+ for (table = hose->config_table; table && table->vendor; table++)
+ table->config_device += gd->reloc_off;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
+#ifdef CONFIG_PCIX_CHECK
+ if (!(gur->pordevsr & PORDEVSR_PCI)) {
+ /* PCI-X init */
+ if (CONFIG_SYS_CLK_FREQ < 66000000)
+ printf("PCI-X will only work at 66 MHz\n");
+
+ reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
+ | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
+ pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
+ }
+#endif
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
+#endif
+
+#ifdef CONFIG_PCI2
+{
+ uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
+ uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
+ if (pci_dual) {
+ printf (" PCI2: 32 bit, 66 MHz, %s\n",
+ pci2_clk_sel ? "sync" : "async");
+ } else {
+ printf (" PCI2: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
+#endif /* CONFIG_PCI2 */
+
+#ifdef CONFIG_PCIE1
+{
-#ifdef CONFIG_PCI
- pci_mpc85xx_init(&hose);
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
#endif
+
}
int last_stage_init(void)
@@ -367,3 +514,32 @@
return 0;
}
+
+
+#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+
+
+#ifdef CONFIG_PCI1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pci1_hose.last_busno - pci1_hose.first_busno;
+ debug("PCI@8000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+
+#ifdef CONFIG_PCIE1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+}
+#endif
diff --git a/board/cds/mpc8548cds/u-boot.lds b/board/cds/mpc8548cds/u-boot.lds
index c1f3495..530ba5a 100644
--- a/board/cds/mpc8548cds/u-boot.lds
+++ b/board/cds/mpc8548cds/u-boot.lds
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -71,7 +71,6 @@
cpu/mpc85xx/cpu.o (.text)
drivers/tsec.o (.text)
cpu/mpc85xx/speed.o (.text)
- cpu/mpc85xx/pci.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
diff --git a/board/cds/mpc8555cds/mpc8555cds.c b/board/cds/mpc8555cds/mpc8555cds.c
index 704bf03..8f16421 100644
--- a/board/cds/mpc8555cds/mpc8555cds.c
+++ b/board/cds/mpc8555cds/mpc8555cds.c
@@ -473,14 +473,17 @@
static struct pci_config_table pci_mpc85xxcds_config_table[] = {
{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
- {0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},
- {0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1,
+ {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
+ {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
mpc85xx_config_via_usbide, {0,0,0}},
- {0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},
- {0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},
- {0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5,
+ {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
+ mpc85xx_config_via_usb, {0,0,0}},
+ {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
+ mpc85xx_config_via_usb2, {0,0,0}},
+ {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
mpc85xx_config_via_power, {0,0,0}},
- {0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}},
+ {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
+ mpc85xx_config_via_ac97, {0,0,0}},
{},
};
diff --git a/board/freescale/mpc8544ds/init.S b/board/freescale/mpc8544ds/init.S
index 296fee5..ea7d54d 100644
--- a/board/freescale/mpc8544ds/init.S
+++ b/board/freescale/mpc8544ds/init.S
@@ -52,8 +52,8 @@
*/
#define entry_start \
- mflr r1 ; \
- bl 0f ;
+ mflr r1 ; \
+ bl 0f ;
#define entry_end \
0: mflr r0 ; \
@@ -214,7 +214,7 @@
.long 0
.long (LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN
- .long (CFG_PCI1_MEM_BASE>>12) & 0xfffff
+ .long (CFG_PCI1_MEM_PHYS>>12) & 0xfffff
.long LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M)
.long (CFG_PCI1_IO_PHYS>>12) & 0xfffff
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index 4ff1da9..8ddbb01 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -22,8 +22,10 @@
#include <common.h>
#include <command.h>
+#include <pci.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
#include <spd.h>
#include <miiphy.h>
@@ -51,12 +53,19 @@
{
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
+ volatile ccsr_lbc_t *lbc = &immap->im_lbc;
+ volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
if ((uint)&gur->porpllsr != 0xe00e0000) {
printf("immap size error %x\n",&gur->porpllsr);
}
printf ("Board: MPC8544DS\n");
+ lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
+ lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
+ ecm->eedr = 0xffffffff; /* Clear ecm errors */
+ ecm->eeer = 0xffffffff; /* Enable ecm errors */
+
return 0;
}
@@ -116,7 +125,317 @@
printf("DRAM test passed.\n");
return 0;
}
+#endif
+
+#ifdef CONFIG_PCI1
+static struct pci_controller pci1_hose;
+#endif
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+int first_free_busno=0;
+
+void
+pci_init_board(void)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_gur_t *gur = &immap->im_gur;
+ uint devdisr = gur->devdisr;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+ debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+ devdisr, io_sel, host_agent);
+
+ if (io_sel & 1) {
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
+ printf (" eTSEC1 is in sgmii mode.\n");
+ if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+ printf (" eTSEC3 is in sgmii mode.\n");
+ }
+
+#ifdef CONFIG_PCIE3
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie3_hose;
+ int pcie_ep = (host_agent == 3);
+ int pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE3 connected to ULI as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE3_MEM_BASE,
+ CFG_PCIE3_MEM_PHYS,
+ CFG_PCIE3_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE3_IO_BASE,
+ CFG_PCIE3_IO_PHYS,
+ CFG_PCIE3_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+#ifdef CFG_PCIE3_MEM_BASE2
+ /* outbound memory */
+ pci_set_region(hose->regions + 3,
+ CFG_PCIE3_MEM_BASE2,
+ CFG_PCIE3_MEM_PHYS2,
+ CFG_PCIE3_MEM_SIZE2,
+ PCI_REGION_MEM);
+ hose->region_count++;
+#endif
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf (" PCIE3 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ } else {
+ printf (" PCIE3: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie1_hose;
+ int pcie_ep = (host_agent == 5);
+ int pcie_configured = io_sel & 6;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE1_MEM_BASE,
+ CFG_PCIE1_MEM_PHYS,
+ CFG_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE1_IO_BASE,
+ CFG_PCIE1_IO_PHYS,
+ CFG_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+#ifdef CFG_PCIE1_MEM_BASE2
+ /* outbound memory */
+ pci_set_region(hose->regions + 3,
+ CFG_PCIE1_MEM_BASE2,
+ CFG_PCIE1_MEM_PHYS2,
+ CFG_PCIE1_MEM_SIZE2,
+ PCI_REGION_MEM);
+ hose->region_count++;
+#endif
+ hose->first_busno=first_free_busno;
+
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+
+ first_free_busno=hose->last_busno+1;
+ printf(" PCIE1 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ } else {
+ printf (" PCIE1: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE2
+ {
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pcie2_hose;
+ int pcie_ep = (host_agent == 3);
+ int pcie_configured = io_sel & 4;
+
+ if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCIE2_MEM_BASE,
+ CFG_PCIE2_MEM_PHYS,
+ CFG_PCIE2_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCIE2_IO_BASE,
+ CFG_PCIE2_IO_PHYS,
+ CFG_PCIE2_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = 3;
+#ifdef CFG_PCIE2_MEM_BASE2
+ /* outbound memory */
+ pci_set_region(hose->regions + 3,
+ CFG_PCIE2_MEM_BASE2,
+ CFG_PCIE2_MEM_PHYS2,
+ CFG_PCIE2_MEM_SIZE2,
+ PCI_REGION_MEM);
+ hose->region_count++;
+#endif
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf (" PCIE2 on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ } else {
+ printf (" PCIE2: disabled\n");
+ }
+
+ }
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+#endif
+
+
+#ifdef CONFIG_PCI1
+{
+ volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+ extern void fsl_pci_init(struct pci_controller *hose);
+ struct pci_controller *hose = &pci1_hose;
+
+ uint pci_agent = (host_agent == 6);
+ uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
+ uint pci_32 = 1;
+ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
+ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
+
+
+ if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
+ printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
+ (pci_32) ? 32 : 64,
+ (pci_speed == 33333000) ? "33" :
+ (pci_speed == 66666000) ? "66" : "unknown",
+ pci_clk_sel ? "sync" : "async",
+ pci_agent ? "agent" : "host",
+ pci_arb ? "arbiter" : "external-arbiter",
+ (uint)pci
+ );
+
+ /* inbound */
+ pci_set_region(hose->regions + 0,
+ CFG_PCI_MEMORY_BUS,
+ CFG_PCI_MEMORY_PHYS,
+ CFG_PCI_MEMORY_SIZE,
+ PCI_REGION_MEM | PCI_REGION_MEMORY);
+
+ /* outbound memory */
+ pci_set_region(hose->regions + 1,
+ CFG_PCI1_MEM_BASE,
+ CFG_PCI1_MEM_PHYS,
+ CFG_PCI1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(hose->regions + 2,
+ CFG_PCI1_IO_BASE,
+ CFG_PCI1_IO_PHYS,
+ CFG_PCI1_IO_SIZE,
+ PCI_REGION_IO);
+ hose->region_count = 3;
+#ifdef CFG_PCIE3_MEM_BASE2
+ /* outbound memory */
+ pci_set_region(hose->regions + 3,
+ CFG_PCIE3_MEM_BASE2,
+ CFG_PCIE3_MEM_PHYS2,
+ CFG_PCIE3_MEM_SIZE2,
+ PCI_REGION_MEM);
+ hose->region_count++;
+#endif
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ first_free_busno=hose->last_busno+1;
+ printf ("PCI on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+ } else {
+ printf (" PCI: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
#endif
+}
+
int last_stage_init(void)
{
@@ -197,5 +516,36 @@
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
}
+#ifdef CONFIG_PCIE1
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@a000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
+ debug("PCI@a000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+#ifdef CONFIG_PCIE2
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@9000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
+ debug("PCI@9000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+#ifdef CONFIG_PCIE3
+ p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@b000/bus-range", &len);
+ if (p != NULL) {
+ p[0] = 0;
+ p[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;;
+ debug("PCI@b000 first_busno=%d last_busno=%d\n",p[0],p[1]);
+ }
+#endif
+ ft_cpu_setup(blob, bd);
+
+ p = ft_get_prop(blob, "/memory/reg", &len);
+ if (p != NULL) {
+ *p++ = cpu_to_be32(bd->bi_memstart);
+ *p = cpu_to_be32(bd->bi_memsize);
+ }
}
#endif
diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c
index 41acb97..eef524b 100644
--- a/board/mpc8560ads/mpc8560ads.c
+++ b/board/mpc8560ads/mpc8560ads.c
@@ -554,7 +554,6 @@
{
u32 *p;
int len;
- ulong data;
p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
diff --git a/board/mpc8568mds/bcsr.c b/board/mpc8568mds/bcsr.c
index 2e2e8cd..aae0f98 100644
--- a/board/mpc8568mds/bcsr.c
+++ b/board/mpc8568mds/bcsr.c
@@ -47,3 +47,10 @@
bcsr[9] &= ~(0x01);
}
+
+void enable_8568mds_qe_mdio()
+{
+ u8 *bcsr = (u8 *)(CFG_BCSR);
+
+ bcsr[7] |= 0x01;
+}
diff --git a/board/mpc8568mds/bcsr.h b/board/mpc8568mds/bcsr.h
index 8d4cb2f..aefd9bf 100644
--- a/board/mpc8568mds/bcsr.h
+++ b/board/mpc8568mds/bcsr.h
@@ -95,5 +95,6 @@
void enable_8568mds_duart(void);
void enable_8568mds_flash_write(void);
void disable_8568mds_flash_write(void);
+void enable_8568mds_qe_mdio(void);
#endif /* __BCSR_H_ */
diff --git a/board/mpc8568mds/init.S b/board/mpc8568mds/init.S
index 0d87982..972a7d4 100644
--- a/board/mpc8568mds/init.S
+++ b/board/mpc8568mds/init.S
@@ -143,54 +143,42 @@
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLBe 2: 256M Non-cacheable, guarded
- * 0x80000000 256M PCI1 MEM
+ * TLBe 2: 1G Non-cacheable, guarded
+ * 0x80000000 512M PCI1 MEM
+ * 0xa0000000 512M PCIe MEM
*/
.long TLB1_MAS0(1, 2, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
+ .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_1G)
.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLBe 3: 256M Non-cacheable, guarded
- * 0xa0000000 256M PCIe Mem
- */
- .long TLB1_MAS0(1, 3, 0)
- .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
- .long TLB1_MAS2(E500_TLB_EPN(CFG_PEX_MEM_BASE), 0,0,0,0,1,0,1,0)
- .long TLB1_MAS3(E500_TLB_RPN(CFG_PEX_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
-
- /*
- * TLBe 4: Reserved for future usage
- */
-
- /*
- * TLBe 5: 64M Non-cacheable, guarded
+ * TLBe 3: 64M Non-cacheable, guarded
* 0xe000_0000 1M CCSRBAR
* 0xe200_0000 8M PCI1 IO
* 0xe280_0000 8M PCIe IO
*/
- .long TLB1_MAS0(1, 5, 0)
+ .long TLB1_MAS0(1, 3, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLBe 6: 64M Cacheable, non-guarded
+ * TLBe 4: 64M Cacheable, non-guarded
* 0xf000_0000 64M LBC SDRAM
*/
- .long TLB1_MAS0(1, 6, 0)
+ .long TLB1_MAS0(1, 4, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
.long TLB1_MAS2(E500_TLB_EPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,0,0,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_LBC_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
/*
- * TLBe 7: 256K Non-cacheable, guarded
+ * TLBe 5: 256K Non-cacheable, guarded
* 0xf8000000 32K BCSR
* 0xf8008000 32K PIB (CS4)
* 0xf8010000 32K PIB (CS5)
*/
- .long TLB1_MAS0(1, 7, 0)
+ .long TLB1_MAS0(1, 5, 0)
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256K)
.long TLB1_MAS2(E500_TLB_EPN(CFG_BCSR_BASE), 0,0,0,0,1,0,1,0)
.long TLB1_MAS3(E500_TLB_RPN(CFG_BCSR_BASE), 0,0,0,0,0,1,0,1,0,1)
@@ -202,12 +190,12 @@
* LAW(Local Access Window) configuration:
*
*0) 0x0000_0000 0x7fff_ffff DDR 2G
- *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 256MB
- *2) 0xa000_0000 0xbfff_ffff PCIe MEM 256MB
- *5) 0xc000_0000 0xdfff_ffff SRIO 256MB
+ *1) 0x8000_0000 0x9fff_ffff PCI1 MEM 512MB
+ *2) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
*-) 0xe000_0000 0xe00f_ffff CCSR 1M
*3) 0xe200_0000 0xe27f_ffff PCI1 I/O 8M
- *4) 0xe280_0000 0xe2ff_ffff PCIe I/0 8M
+ *4) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+ *5) 0xc000_0000 0xdfff_ffff SRIO 512MB
*6.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
*6.b) 0xf800_0000 0xf800_7fff BCSR 32KB
*6.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
@@ -226,20 +214,20 @@
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
-#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR2 ((CFG_PEX_MEM_BASE>>12) & 0xfffff)
-#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_512M))
#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff)
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_8M))
#define LAWBAR4 ((CFG_PEX_IO_PHYS>>12) & 0xfffff)
-#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_16M))
+#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_PEX | (LAWAR_SIZE & LAWAR_SIZE_8M))
#define LAWBAR5 ((CFG_SRIO_MEM_BASE>>12) & 0xfffff)
-#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_256M))
+#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
/* LBC window - maps 256M. That's SDRAM, BCSR, PIBs, and Flash */
#define LAWBAR6 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
diff --git a/board/mpc8568mds/mpc8568mds.c b/board/mpc8568mds/mpc8568mds.c
index 9c7960d..818ff13 100644
--- a/board/mpc8568mds/mpc8568mds.c
+++ b/board/mpc8568mds/mpc8568mds.c
@@ -27,9 +27,66 @@
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <spd.h>
+#include <i2c.h>
+#include <ioports.h>
#include "bcsr.h"
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* GETH1 */
+ {4, 10, 1, 0, 2}, /* TxD0 */
+ {4, 9, 1, 0, 2}, /* TxD1 */
+ {4, 8, 1, 0, 2}, /* TxD2 */
+ {4, 7, 1, 0, 2}, /* TxD3 */
+ {4, 23, 1, 0, 2}, /* TxD4 */
+ {4, 22, 1, 0, 2}, /* TxD5 */
+ {4, 21, 1, 0, 2}, /* TxD6 */
+ {4, 20, 1, 0, 2}, /* TxD7 */
+ {4, 15, 2, 0, 2}, /* RxD0 */
+ {4, 14, 2, 0, 2}, /* RxD1 */
+ {4, 13, 2, 0, 2}, /* RxD2 */
+ {4, 12, 2, 0, 2}, /* RxD3 */
+ {4, 29, 2, 0, 2}, /* RxD4 */
+ {4, 28, 2, 0, 2}, /* RxD5 */
+ {4, 27, 2, 0, 2}, /* RxD6 */
+ {4, 26, 2, 0, 2}, /* RxD7 */
+ {4, 11, 1, 0, 2}, /* TX_EN */
+ {4, 24, 1, 0, 2}, /* TX_ER */
+ {4, 16, 2, 0, 2}, /* RX_DV */
+ {4, 30, 2, 0, 2}, /* RX_ER */
+ {4, 17, 2, 0, 2}, /* RX_CLK */
+ {4, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+
+ /* GETH2 */
+ {5, 10, 1, 0, 2}, /* TxD0 */
+ {5, 9, 1, 0, 2}, /* TxD1 */
+ {5, 8, 1, 0, 2}, /* TxD2 */
+ {5, 7, 1, 0, 2}, /* TxD3 */
+ {5, 23, 1, 0, 2}, /* TxD4 */
+ {5, 22, 1, 0, 2}, /* TxD5 */
+ {5, 21, 1, 0, 2}, /* TxD6 */
+ {5, 20, 1, 0, 2}, /* TxD7 */
+ {5, 15, 2, 0, 2}, /* RxD0 */
+ {5, 14, 2, 0, 2}, /* RxD1 */
+ {5, 13, 2, 0, 2}, /* RxD2 */
+ {5, 12, 2, 0, 2}, /* RxD3 */
+ {5, 29, 2, 0, 2}, /* RxD4 */
+ {5, 28, 2, 0, 2}, /* RxD5 */
+ {5, 27, 2, 0, 3}, /* RxD6 */
+ {5, 26, 2, 0, 2}, /* RxD7 */
+ {5, 11, 1, 0, 2}, /* TX_EN */
+ {5, 24, 1, 0, 2}, /* TX_ER */
+ {5, 16, 2, 0, 2}, /* RX_DV */
+ {5, 30, 2, 0, 2}, /* RX_ER */
+ {5, 17, 2, 0, 2}, /* RX_CLK */
+ {5, 19, 1, 0, 2}, /* GTX_CLK */
+ {1, 31, 2, 0, 3}, /* GTX125 */
+ {4, 6, 3, 0, 2}, /* MDIO */
+ {4, 5, 1, 0, 2}, /* MDC */
+ {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
+};
+
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
@@ -49,6 +106,18 @@
enable_8568mds_duart();
enable_8568mds_flash_write();
+#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
+ enable_8568mds_qe_mdio();
+#endif
+
+#ifdef CFG_I2C2_OFFSET
+ /* Enable I2C2_SCL and I2C2_SDA */
+ volatile struct par_io *port_c;
+ port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
+ port_c->cpdir2 |= 0x0f000000;
+ port_c->cppar2 &= ~0x0f000000;
+ port_c->cppar2 |= 0x0a000000;
+#endif
return 0;
}
@@ -269,20 +338,62 @@
#endif
static struct pci_controller hose[] = {
+ {
#ifndef CONFIG_PCI_PNP
- { config_table: pci_mpc8568mds_config_table,},
+ config_table: pci_mpc8568mds_config_table,
#endif
-#ifdef CONFIG_MPC85XX_PCI2
- {},
-#endif
+ }
};
#endif /* CONFIG_PCI */
+/*
+ * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
+ */
+void
+pib_init(void)
+{
+ u8 val8, orig_i2c_bus;
+ /*
+ * Assign PIB PMC2/3 to PCI bus
+ */
+
+ /*switch temporarily to I2C bus #2 */
+ orig_i2c_bus = i2c_get_bus_num();
+ i2c_set_bus_num(1);
+
+ val8 = 0x00;
+ i2c_write(0x23, 0x6, 1, &val8, 1);
+ i2c_write(0x23, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x23, 0x2, 1, &val8, 1);
+ i2c_write(0x23, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x26, 0x6, 1, &val8, 1);
+ val8 = 0x34;
+ i2c_write(0x26, 0x7, 1, &val8, 1);
+ val8 = 0xf9;
+ i2c_write(0x26, 0x2, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x26, 0x3, 1, &val8, 1);
+
+ val8 = 0x00;
+ i2c_write(0x27, 0x6, 1, &val8, 1);
+ i2c_write(0x27, 0x7, 1, &val8, 1);
+ val8 = 0xff;
+ i2c_write(0x27, 0x2, 1, &val8, 1);
+ val8 = 0xef;
+ i2c_write(0x27, 0x3, 1, &val8, 1);
+
+ asm("eieio");
+}
+
void
pci_init_board(void)
{
#ifdef CONFIG_PCI
- pci_mpc85xx_init(&hose);
+ pib_init();
+ pci_mpc85xx_init(hose);
#endif
}
diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile
index ff67dcd..32091fa 100644
--- a/cpu/mpc85xx/Makefile
+++ b/cpu/mpc85xx/Makefile
@@ -30,7 +30,7 @@
START = start.o resetvec.o
COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \
- pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o
+ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 1d791c9..08e0468 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -280,7 +280,7 @@
if (p != NULL)
*p = cpu_to_be32(clock);
-#if defined(CONFIG_TSEC1)
+#if defined(CONFIG_HAS_ETH0)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p)
memcpy(p, bd->bi_enetaddr, 6);
@@ -308,6 +308,17 @@
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/local-mac-address", &len);
if (p)
memcpy(p, bd->bi_enet2addr, 6);
+
+#ifdef CONFIG_UEC_ETH
+ p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet2addr, 6);
+
+ p = ft_get_prop(blob, "/" OF_QE "/ucc@2000/local-mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet2addr, 6);
+
+#endif
#endif
#if defined(CONFIG_HAS_ETH3)
@@ -318,6 +329,17 @@
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/local-mac-address", &len);
if (p)
memcpy(p, bd->bi_enet3addr, 6);
+
+#ifdef CONFIG_UEC_ETH
+ p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet3addr, 6);
+
+ p = ft_get_prop(blob, "/" OF_QE "/ucc@3000/local-mac-address", &len);
+ if (p)
+ memcpy(p, bd->bi_enet3addr, 6);
+
+#endif
#endif
}
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c
index 9517146..7b99610 100644
--- a/cpu/mpc85xx/cpu_init.c
+++ b/cpu/mpc85xx/cpu_init.c
@@ -1,4 +1,6 @@
/*
+ * Copyright 2007 Freescale Semiconductor.
+ *
* (C) Copyright 2003 Motorola Inc.
* Modified by Xianghua Xiao, X.Xiao@motorola.com
*
@@ -32,6 +34,29 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_QE
+extern qe_iop_conf_t qe_iop_conf_tab[];
+extern void qe_config_iopin(u8 port, u8 pin, int dir,
+ int open_drain, int assign);
+extern void qe_init(uint qe_base);
+extern void qe_reset(void);
+
+static void config_qe_ioports(void)
+{
+ u8 port, pin;
+ int dir, open_drain, assign;
+ int i;
+
+ for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
+ port = qe_iop_conf_tab[i].port;
+ pin = qe_iop_conf_tab[i].pin;
+ dir = qe_iop_conf_tab[i].dir;
+ open_drain = qe_iop_conf_tab[i].open_drain;
+ assign = qe_iop_conf_tab[i].assign;
+ qe_config_iopin(port, pin, dir, open_drain, assign);
+ }
+}
+#endif
#ifdef CONFIG_CPM2
static void config_8560_ioports (volatile immap_t * immr)
@@ -133,15 +158,18 @@
#endif
/* now restrict to preliminary range */
+ /* if cs1 is already set via debugger, leave cs0/cs1 alone */
+ if (! memctl->br1 & 1) {
#if defined(CFG_BR0_PRELIM) && defined(CFG_OR0_PRELIM)
- memctl->br0 = CFG_BR0_PRELIM;
- memctl->or0 = CFG_OR0_PRELIM;
+ memctl->br0 = CFG_BR0_PRELIM;
+ memctl->or0 = CFG_OR0_PRELIM;
#endif
#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
- memctl->or1 = CFG_OR1_PRELIM;
- memctl->br1 = CFG_BR1_PRELIM;
+ memctl->or1 = CFG_OR1_PRELIM;
+ memctl->br1 = CFG_BR1_PRELIM;
#endif
+ }
#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
memctl->or2 = CFG_OR2_PRELIM;
@@ -176,6 +204,11 @@
#if defined(CONFIG_CPM2)
m8560_cpm_reset();
#endif
+#ifdef CONFIG_QE
+ /* Config QE ioports */
+ config_qe_ioports();
+#endif
+
}
@@ -185,16 +218,25 @@
* The newer 8548, etc, parts have twice as much cache, but
* use the same bit-encoding as the older 8555, etc, parts.
*
- * FIXME: Use PVR_VER(pvr) == 1 test here instead of SVR_VER()?
*/
int cpu_init_r(void)
{
+#if defined(CONFIG_CLEAR_LAW0) || defined(CONFIG_L2_CACHE)
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#endif
+#ifdef CONFIG_CLEAR_LAW0
+ volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
+
+ /* clear alternate boot location LAW (used for sdram, or ddr bank) */
+ ecm->lawar0 = 0;
+#endif
+
#if defined(CONFIG_L2_CACHE)
- volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_l2cache_t *l2cache = &immap->im_l2cache;
volatile uint cache_ctl;
uint svr, ver;
+ uint l2srbar;
svr = get_svr();
ver = SVR_VER(svr);
@@ -204,33 +246,55 @@
switch (cache_ctl & 0x30000000) {
case 0x20000000:
- if (ver == SVR_8548 || ver == SVR_8548_E) {
+ if (ver == SVR_8548 || ver == SVR_8548_E ||
+ ver == SVR_8544) {
printf ("L2 cache 512KB:");
+ /* set L2E=1, L2I=1, & L2SRAM=0 */
+ cache_ctl = 0xc0000000;
} else {
printf ("L2 cache 256KB:");
+ /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */
+ cache_ctl = 0xc8000000;
}
break;
- case 0x00000000:
case 0x10000000:
+ printf ("L2 cache 256KB:");
+ if (ver == SVR_8544 || ver == SVR_8544_E) {
+ cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
+ }
+ break;
case 0x30000000:
+ case 0x00000000:
default:
printf ("L2 cache unknown size (0x%08x)\n", cache_ctl);
return -1;
}
- asm("msync;isync");
- l2cache->l2ctl = 0x68000000; /* invalidate */
- cache_ctl = l2cache->l2ctl;
- asm("msync;isync");
-
- l2cache->l2ctl = 0xa8000000; /* enable 256KB L2 cache */
- cache_ctl = l2cache->l2ctl;
- asm("msync;isync");
-
- printf(" enabled\n");
+ if (l2cache->l2ctl & 0x80000000) {
+ printf(" already enabled.");
+ l2srbar = l2cache->l2srbar0;
+#ifdef CFG_INIT_L2_ADDR
+ if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) {
+ l2srbar = CFG_INIT_L2_ADDR;
+ l2cache->l2srbar0 = l2srbar;
+ printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR);
+ }
+#endif /* CFG_INIT_L2_ADDR */
+ puts("\n");
+ } else {
+ asm("msync;isync");
+ l2cache->l2ctl = cache_ctl; /* invalidate & enable */
+ asm("msync;isync");
+ printf(" enabled\n");
+ }
#else
printf("L2 cache: disabled\n");
#endif
+#ifdef CONFIG_QE
+ uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */
+ qe_init(qe_base);
+ qe_reset();
+#endif
return 0;
}
diff --git a/cpu/mpc85xx/interrupts.c b/cpu/mpc85xx/interrupts.c
index dc246dc..bf737d6 100644
--- a/cpu/mpc85xx/interrupts.c
+++ b/cpu/mpc85xx/interrupts.c
@@ -89,6 +89,39 @@
mtspr(SPRN_TCR, TCR_PIE);
set_dec (decrementer_count);
set_msr (get_msr () | MSR_EE);
+
+#ifdef CONFIG_INTERRUPTS
+ volatile ccsr_pic_t *pic = &immr->im_pic;
+
+ pic->iivpr1 = 0x810002; /* 50220 enable ecm interrupts */
+ debug("iivpr1@%x = %x\n",&pic->iivpr1, pic->iivpr1);
+
+ pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */
+ debug("iivpr2@%x = %x\n",&pic->iivpr2, pic->iivpr2);
+
+ pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */
+ debug("iivpr3@%x = %x\n",&pic->iivpr3, pic->iivpr3);
+
+#ifdef CONFIG_PCI1
+ pic->iivpr8 = 0x810008; /* enable pci1 interrupts */
+ debug("iivpr8@%x = %x\n",&pic->iivpr8, pic->iivpr8);
+#endif
+#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2)
+ pic->iivpr9 = 0x810009; /* enable pci1 interrupts */
+ debug("iivpr9@%x = %x\n",&pic->iivpr9, pic->iivpr9);
+#endif
+#ifdef CONFIG_PCIE1
+ pic->iivpr10 = 0x81000a; /* enable pcie1 interrupts */
+ debug("iivpr10@%x = %x\n",&pic->iivpr10, pic->iivpr10);
+#endif
+#ifdef CONFIG_PCIE3
+ pic->iivpr11 = 0x81000b; /* enable pcie3 interrupts */
+ debug("iivpr11@%x = %x\n",&pic->iivpr11, pic->iivpr11);
+#endif
+
+ pic->ctpr=0; /* 40080 clear current task priority register */
+#endif
+
return (0);
}
diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c
index 3c1a323..db09e45 100644
--- a/cpu/mpc85xx/pci.c
+++ b/cpu/mpc85xx/pci.c
@@ -142,7 +142,7 @@
u8 header_type;
pci_hose_read_config_byte(hose,
- PCI_BDF(0,17,0),
+ PCI_BDF(0,BRIDGE_ID,0),
PCI_HEADER_TYPE,
&header_type);
}
diff --git a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c
new file mode 100644
index 0000000..8878bc5
--- /dev/null
+++ b/cpu/mpc85xx/qe_io.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu@freescale.com>
+ * based on source code of Shlomi Gridish
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "common.h"
+#include "asm/errno.h"
+#include "asm/io.h"
+#include "asm/immap_85xx.h"
+
+#if defined(CONFIG_QE)
+#define NUM_OF_PINS 32
+void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
+{
+ u32 pin_2bit_mask;
+ u32 pin_2bit_dir;
+ u32 pin_2bit_assign;
+ u32 pin_1bit_mask;
+ u32 tmp_val;
+ volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+ volatile par_io_t *par_io = (volatile par_io_t *)
+ &(im->im_gur.qe_par_io);
+
+ /* Caculate pin location and 2bit mask and dir */
+ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+ pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2));
+
+ /* Setup the direction */
+ tmp_val = (pin > (NUM_OF_PINS/2) - 1) ? \
+ in_be32(&par_io[port].cpdir2) :
+ in_be32(&par_io[port].cpdir1);
+
+ if (pin > (NUM_OF_PINS/2) -1) {
+ out_be32(&par_io[port].cpdir2, ~pin_2bit_mask & tmp_val);
+ out_be32(&par_io[port].cpdir2, pin_2bit_dir | tmp_val);
+ } else {
+ out_be32(&par_io[port].cpdir1, ~pin_2bit_mask & tmp_val);
+ out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val);
+ }
+
+ /* Calculate pin location for 1bit mask */
+ pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1)));
+
+ /* Setup the open drain */
+ tmp_val = in_be32(&par_io[port].cpodr);
+ if (open_drain)
+ out_be32(&par_io[port].cpodr, pin_1bit_mask | tmp_val);
+ else
+ out_be32(&par_io[port].cpodr, ~pin_1bit_mask & tmp_val);
+
+ /* Setup the assignment */
+ tmp_val = (pin > (NUM_OF_PINS/2) - 1) ?
+ in_be32(&par_io[port].cppar2):
+ in_be32(&par_io[port].cppar1);
+ pin_2bit_assign = (u32)(assign
+ << (NUM_OF_PINS - (pin%(NUM_OF_PINS/2)+1)*2));
+
+ /* Clear and set 2 bits mask */
+ if (pin > (NUM_OF_PINS/2) - 1) {
+ out_be32(&par_io[port].cppar2, ~pin_2bit_mask & tmp_val);
+ out_be32(&par_io[port].cppar2, pin_2bit_assign | tmp_val);
+ } else {
+ out_be32(&par_io[port].cppar1, ~pin_2bit_mask & tmp_val);
+ out_be32(&par_io[port].cppar1, pin_2bit_assign | tmp_val);
+ }
+}
+
+#endif /* CONFIG_QE */
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 3777f49..5dc223a 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
@@ -173,11 +173,10 @@
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
- volatile ccsr_gur_t *gur = &immap->im_gur;
spd_eeprom_t spd;
unsigned int n_ranks;
unsigned int rank_density;
- unsigned int odt_rd_cfg, odt_wr_cfg;
+ unsigned int odt_rd_cfg, odt_wr_cfg, ba_bits;
unsigned int odt_cfg, mode_odt_enable;
unsigned int refresh_clk;
#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
@@ -189,7 +188,7 @@
unsigned int max_data_rate, effective_data_rate;
unsigned int busfreq;
unsigned sdram_cfg;
- unsigned int memsize;
+ unsigned int memsize = 0;
unsigned char caslat, caslat_ctrl;
unsigned int trfc, trfc_clk, trfc_low, trfc_high;
unsigned int trcd_clk;
@@ -204,8 +203,48 @@
unsigned int mode_caslat;
unsigned char sdram_type;
unsigned char d_init;
+ unsigned int bnds;
/*
+ * Skip configuration if already configured.
+ * memsize is determined from last configured chip select.
+ */
+ if (ddr->cs0_config & 0x80000000) {
+ debug(" cs0 already configured, bnds=%x\n",ddr->cs0_bnds);
+ bnds = 0xfff & ddr->cs0_bnds;
+ if (bnds < 0xff) { /* do not add if at top of 4G */
+ memsize = (bnds + 1) << 4;
+ }
+ }
+ if (ddr->cs1_config & 0x80000000) {
+ debug(" cs1 already configured, bnds=%x\n",ddr->cs1_bnds);
+ bnds = 0xfff & ddr->cs1_bnds;
+ if (bnds < 0xff) { /* do not add if at top of 4G */
+ memsize = (bnds + 1) << 4; /* assume ordered bnds */
+ }
+ }
+ if (ddr->cs2_config & 0x80000000) {
+ debug(" cs2 already configured, bnds=%x\n",ddr->cs2_bnds);
+ bnds = 0xfff & ddr->cs2_bnds;
+ if (bnds < 0xff) { /* do not add if at top of 4G */
+ memsize = (bnds + 1) << 4;
+ }
+ }
+ if (ddr->cs3_config & 0x80000000) {
+ debug(" cs3 already configured, bnds=%x\n",ddr->cs3_bnds);
+ bnds = 0xfff & ddr->cs3_bnds;
+ if (bnds < 0xff) { /* do not add if at top of 4G */
+ memsize = (bnds + 1) << 4;
+ }
+ }
+
+ if (memsize) {
+ printf(" Reusing current %dMB configuration\n",memsize);
+ memsize = setup_laws_and_tlbs(memsize);
+ return memsize << 20;
+ }
+
+ /*
* Read SPD information.
*/
CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) &spd, sizeof(spd));
@@ -262,6 +301,7 @@
return 0;
}
+#ifdef CONFIG_MPC8548
/*
* Adjust DDR II IO voltage biasing.
* Only 8548 rev 1 needs the fix
@@ -269,9 +309,11 @@
if ((SVR_VER(get_svr()) == SVR_8548_E) &&
(SVR_MJREV(get_svr()) == 1) &&
(spd.mem_type == SPD_MEMTYPE_DDR2)) {
+ volatile ccsr_gur_t *gur = &immap->im_gur;
gur->ddrioovcr = (0x80000000 /* Enable */
| 0x10000000);/* VSEL to 1.8V */
}
+#endif
/*
* Determine the size of each Rank in bytes.
@@ -299,9 +341,14 @@
#endif
}
+ ba_bits = 0;
+ if (spd.nbanks == 0x8)
+ ba_bits = 1;
+
ddr->cs0_config = ( 1 << 31
| (odt_rd_cfg << 20)
| (odt_wr_cfg << 16)
+ | (ba_bits << 14)
| (spd.nrow_addr - 12) << 8
| (spd.ncol_addr - 8) );
debug("\n");
@@ -645,13 +692,10 @@
*/
cpo = 0;
if (spd.mem_type == SPD_MEMTYPE_DDR2) {
- if (effective_data_rate == 266 || effective_data_rate == 333) {
+ if (effective_data_rate <= 333) {
cpo = 0x7; /* READ_LAT + 5/4 */
- } else if (effective_data_rate == 400) {
- cpo = 0x9; /* READ_LAT + 7/4 */
} else {
- /* Pure speculation */
- cpo = 0xb;
+ cpo = 0x9; /* READ_LAT + 7/4 */
}
}
@@ -858,7 +902,12 @@
if (spd.mem_type == SPD_MEMTYPE_DDR)
clk_adjust = 0x6;
else
+#ifdef CONFIG_MPC8568
+ /* Empirally setting clk_adjust */
+ clk_adjust = 0x6;
+#else
clk_adjust = 0x7;
+#endif
ddr->sdram_clk_cntl = (0
| 0x80000000
diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index 77c155c..2c98c2a 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -1,7 +1,6 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* Copyright (C) 2003 Motorola,Inc.
- * Xianghua Xiao<X.Xiao@motorola.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -46,7 +45,7 @@
#endif
#undef MSR_KERNEL
-#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
+#define MSR_KERNEL ( MSR_ME ) /* Machine Check */
/*
* Set up GOT: Global Offset Table
@@ -80,110 +79,37 @@
*
*/
- .section .bootpg,"ax"
- .globl _start_e500
+ .section .bootpg,"ax"
+ .globl _start_e500
_start_e500:
- mfspr r0, PVR
- lis r1, PVR_85xx_REV1@h
- ori r1, r1, PVR_85xx_REV1@l
- cmpw r0, r1
- bne 1f
- /* Semi-bogus errata fixup for Rev 1 */
- li r0,0x2000
- mtspr 977,r0
+/* clear registers/arrays not reset by hardware */
- /*
- * Before invalidating MMU L1/L2, read TLB1 Entry 0 and then
- * write it back immediately to fixup a Rev 1 bug (Errata CPU4)
- * for this initial TLB1 entry 0, otherwise the TLB1 entry 0
- * will be invalidated (incorrectly).
- */
- lis r2,0x1000
- mtspr MAS0,r2
- tlbre
- tlbwe
- isync
-
-1:
- /*
- * Clear and set up some registers.
- * Note: Some registers need strict synchronization by
- * sync/mbar/msync/isync when being "mtspr".
- * BookE: isync before PID,tlbivax,tlbwe
- * BookE: isync after MSR,PID; msync_isync after tlbivax & tlbwe
- * E500: msync,isync before L1CSR0
- * E500: isync after BBEAR,BBTAR,BUCSR,DBCR0,DBCR1,HID0,HID1,
- * L1CSR0, L1CSR1, MAS[0,1,2,3,4,6],MMUCSR0, PID[0,1,2],
- * SPEFCSR
- */
-
- /* invalidate d-cache */
- mfspr r0,L1CSR0
- ori r0,r0,0x0002
- msync
- isync
- mtspr L1CSR0,r0
- isync
-
- /* disable d-cache */
- li r0,0x0
- mtspr L1CSR0,r0
-
- /* invalidate i-cache */
- mfspr r0,L1CSR1
- ori r0,r0,0x0002
- mtspr L1CSR1,r0
- isync
-
- /* disable i-cache */
- li r0,0x0
- mtspr L1CSR1,r0
- isync
-
- /* clear registers */
- li r0,0
- mtspr SRR0,r0
- mtspr SRR1,r0
- mtspr CSRR0,r0
- mtspr CSRR1,r0
- mtspr MCSRR0,r0
- mtspr MCSRR1,r0
-
- mtspr ESR,r0
- mtspr MCSR,r0
- mtspr DEAR,r0
-
- /* not needed and conflicts with some debuggers */
- /* mtspr DBCR0,r0 */
- mtspr DBCR1,r0
- mtspr DBCR2,r0
- /* not needed and conflicts with some debuggers */
- /* mtspr IAC1,r0 */
- /* mtspr IAC2,r0 */
- mtspr DAC1,r0
- mtspr DAC2,r0
+ /* L1 */
+ li r0,2
+ mtspr L1CSR0,r0 /* invalidate d-cache */
+ mtspr L1CSR1,r0 /* invalidate i-cache */
mfspr r1,DBSR
mtspr DBSR,r1 /* Clear all valid bits */
- mtspr PID0,r0
- mtspr PID1,r0
- mtspr PID2,r0
- mtspr TCR,r0
+ /*
+ * Enable L1 Caches early
+ *
+ */
- mtspr BUCSR,r0 /* disable branch prediction */
- mtspr MAS4,r0
- mtspr MAS6,r0
-#if defined(CONFIG_ENABLE_36BIT_PHYS)
- mtspr MAS7,r0
-#endif
+ lis r2,L1CSR0_CPE@H /* enable parity */
+ ori r2,r2,L1CSR0_DCE
+ mtspr L1CSR0,r2 /* enable L1 Dcache */
isync
+ mtspr L1CSR1,r2 /* enable L1 Icache */
+ isync
+ msync
/* Setup interrupt vectors */
lis r1,TEXT_BASE@h
- mtspr IVPR, r1
+ mtspr IVPR,r1
li r1,0x0100
mtspr IVOR0,r1 /* 0: Critical input */
@@ -217,28 +143,8 @@
li r1,0x0f00
mtspr IVOR15,r1 /* 15: Debug */
- /*
- * Invalidate MMU L1/L2
- *
- * Note: There is a fixup earlier for Errata CPU4 on
- * Rev 1 parts that must precede this MMU invalidation.
- */
- li r2, 0x001e
- mtspr MMUCSR0, r2
- isync
/*
- * Invalidate all TLB0 entries.
- */
- li r3,4
- li r4,0
- tlbivax r4,r3
- /*
- * To avoid REV1 Errata CPU6 issues, make sure
- * the instruction following tlbivax is not a store.
- */
-
- /*
* After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
* 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
* region before we can access any CCSR registers such as L2
@@ -254,14 +160,14 @@
lwzu r4,0(r5) /* how many TLB1 entries we actually use */
mtctr r4
-0: lwzu r0,4(r5)
- lwzu r1,4(r5)
- lwzu r2,4(r5)
- lwzu r3,4(r5)
- mtspr MAS0,r0
- mtspr MAS1,r1
- mtspr MAS2,r2
- mtspr MAS3,r3
+0: lwzu r6,4(r5)
+ lwzu r7,4(r5)
+ lwzu r8,4(r5)
+ lwzu r9,4(r5)
+ mtspr MAS0,r6
+ mtspr MAS1,r7
+ mtspr MAS2,r8
+ mtspr MAS3,r9
isync
msync
tlbwe
@@ -271,22 +177,22 @@
1:
#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
/* Special sequence needed to update CCSRBAR itself */
- lis r4, CFG_CCSRBAR_DEFAULT@h
- ori r4, r4, CFG_CCSRBAR_DEFAULT@l
+ lis r4,CFG_CCSRBAR_DEFAULT@h
+ ori r4,r4,CFG_CCSRBAR_DEFAULT@l
- lis r5, CFG_CCSRBAR@h
- ori r5, r5, CFG_CCSRBAR@l
+ lis r5,CFG_CCSRBAR@h
+ ori r5,r5,CFG_CCSRBAR@l
srwi r6,r5,12
- stw r6, 0(r4)
+ stw r6,0(r4)
isync
- lis r5, 0xffff
+ lis r5,0xffff
ori r5,r5,0xf000
- lwz r5, 0(r5)
+ lwz r5,0(r5)
isync
- lis r3, CFG_CCSRBAR@h
- lwz r5, CFG_CCSRBAR@l(r3)
+ lis r3,CFG_CCSRBAR@h
+ lwz r5,CFG_CCSRBAR@l(r3)
isync
#endif
@@ -300,8 +206,8 @@
lwzu r5,0(r6) /* how many windows we actually use */
mtctr r5
- li r2,0x0c28 /* the first pair is reserved for boot-over-rio-or-pci */
- li r1,0x0c30
+ li r2,0x0c28 /* the first pair is reserved for */
+ li r1,0x0c30 /* boot-over-rio-or-pci */
0: lwzu r4,4(r6)
lwzu r3,4(r6)
@@ -311,31 +217,6 @@
addi r1,r1,0x0020
bdnz 0b
- /* Jump out the last 4K page and continue to 'normal' start */
-1: bl 3f
- b _start
-
-3: li r0,0
- mtspr SRR1,r0 /* Keep things disabled for now */
- mflr r1
- mtspr SRR0,r1
- rfi
-
-/*
- * r3 - 1st arg to board_init(): IMMP pointer
- * r4 - 2nd arg to board_init(): boot flag
- */
- .text
- .long 0x27051956 /* U-BOOT Magic Number */
- .globl version_string
-version_string:
- .ascii U_BOOT_VERSION
- .ascii " (", __DATE__, " - ", __TIME__, ")"
- .ascii CONFIG_IDENT_STRING, "\0"
-
- . = EXC_OFF_SYS_RESET
- .globl _start
-_start:
/* Clear and set up some registers. */
li r0,0x0000
lis r1,0xffff
@@ -354,17 +235,14 @@
/* Enable Time Base and Select Time Base Clock */
lis r0,HID0_EMCP@h /* Enable machine check */
- ori r0,r0,0x4000 /* time base is processor clock */
#if defined(CONFIG_ENABLE_36BIT_PHYS)
- ori r0,r0,0x0080 /* enable MAS7 updates */
+ ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */
+#else
+ ori r0,r0,HID0_TBEN@l /* enable Timebase */
#endif
mtspr HID0,r0
-#if defined(CONFIG_ADDR_STREAMING)
- li r0,0x3000
-#else
- li r0,0x1000
-#endif
+ li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mtspr HID1,r0
/* Enable Branch Prediction */
@@ -383,37 +261,53 @@
#endif
/* L1 DCache is used for initial RAM */
- mfspr r2, L1CSR0
- ori r2, r2, 0x0003
- oris r2, r2, 0x0001
- mtspr L1CSR0, r2 /* enable/invalidate L1 Dcache */
- isync
/* Allocate Initial RAM in data cache.
*/
- lis r3, CFG_INIT_RAM_ADDR@h
- ori r3, r3, CFG_INIT_RAM_ADDR@l
- li r2, 512 /* 512*32=16K */
+ lis r3,CFG_INIT_RAM_ADDR@h
+ ori r3,r3,CFG_INIT_RAM_ADDR@l
+ li r2,512 /* 512*32=16K */
mtctr r2
- li r0, 0
+ li r0,0
1:
- dcbz r0, r3
- dcbtls 0,r0, r3
- addi r3, r3, 32
+ dcbz r0,r3
+ dcbtls 0,r0,r3
+ addi r3,r3,32
bdnz 1b
-#ifndef CFG_RAMBOOT
+ /* Jump out the last 4K page and continue to 'normal' start */
+#ifdef CFG_RAMBOOT
+ bl 3f
+ b _start_cont
+#else
/* Calculate absolute address in FLASH and jump there */
/*--------------------------------------------------------------*/
- lis r3, CFG_MONITOR_BASE@h
- ori r3, r3, CFG_MONITOR_BASE@l
- addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
+ lis r3,CFG_MONITOR_BASE@h
+ ori r3,r3,CFG_MONITOR_BASE@l
+ addi r3,r3,_start_cont - _start + _START_OFFSET
mtlr r3
- blr
+#endif
-in_flash:
-#endif /* CFG_RAMBOOT */
+3: li r0,0
+ mtspr SRR1,r0 /* Keep things disabled for now */
+ mflr r1
+ mtspr SRR0,r1
+ rfi
+ isync
+
+ .text
+ .globl _start
+_start:
+ .long 0x27051956 /* U-BOOT Magic Number */
+ .globl version_string
+version_string:
+ .ascii U_BOOT_VERSION
+ .ascii " (", __DATE__, " - ", __TIME__, ")"
+ .ascii CONFIG_IDENT_STRING, "\0"
+ .align 4
+ .globl _start_cont
+_start_cont:
/* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
lis r1,CFG_INIT_RAM_ADDR@h
ori r1,r1,CFG_INIT_SP_OFFSET@l
@@ -424,26 +318,24 @@
stwu r1,-8(r1) /* Save back chain and move SP */
lis r0,RESET_VECTOR@h /* Address of reset vector */
- ori r0,r0, RESET_VECTOR@l
+ ori r0,r0,RESET_VECTOR@l
stwu r1,-8(r1) /* Save back chain and move SP */
stw r0,+12(r1) /* Save return addr (underflow vect) */
GET_GOT
bl cpu_init_f
- bl icache_enable
bl board_init_f
isync
-/* --FIXME-- machine check with MCSRRn and rfmci */
-
+ . = EXC_OFF_SYS_RESET
.globl _start_of_vectors
_start_of_vectors:
-#if 0
+
/* Critical input. */
- CRIT_EXCEPTION(0x0100, CritcalInput, CritcalInputException)
-#endif
-/* Machine check --FIXME-- Should be MACH_EXCEPTION */
- CRIT_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
+ CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
+
+/* Machine check */
+ MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
/* Data Storage exception. */
STD_EXCEPTION(0x0300, DataStorage, UnknownException)
@@ -452,7 +344,7 @@
STD_EXCEPTION(0x0400, InstStorage, UnknownException)
/* External Interrupt exception. */
- STD_EXCEPTION(0x0500, ExtInterrupt, UnknownException)
+ STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
/* Alignment exception. */
. = 0x0600
@@ -469,8 +361,8 @@
mtlr r6
blrl
.L_Alignment:
- .long AlignmentException - _start + EXC_OFF_SYS_RESET
- .long int_return - _start + EXC_OFF_SYS_RESET
+ .long AlignmentException - _start + _START_OFFSET
+ .long int_return - _start + _START_OFFSET
/* Program check exception */
. = 0x0700
@@ -483,8 +375,8 @@
mtlr r6
blrl
.L_ProgramCheck:
- .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
- .long int_return - _start + EXC_OFF_SYS_RESET
+ .long ProgramCheckException - _start + _START_OFFSET
+ .long int_return - _start + _START_OFFSET
/* No FPU on MPC85xx. This exception is not supposed to happen.
*/
@@ -496,23 +388,23 @@
* r3-... arguments
*/
SystemCall:
- addis r11,r0,0 /* get functions table addr */
- ori r11,r11,0 /* Note: this code is patched in trap_init */
- addis r12,r0,0 /* get number of functions */
+ addis r11,r0,0 /* get functions table addr */
+ ori r11,r11,0 /* Note: this code is patched in trap_init */
+ addis r12,r0,0 /* get number of functions */
ori r12,r12,0
- cmplw 0, r0, r12
+ cmplw 0,r0,r12
bge 1f
- rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
+ rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
add r11,r11,r0
lwz r11,0(r11)
- li r20,0xd00-4 /* Get stack pointer */
+ li r20,0xd00-4 /* Get stack pointer */
lwz r12,0(r20)
- subi r12,r12,12 /* Adjust stack pointer */
+ subi r12,r12,12 /* Adjust stack pointer */
li r0,0xc00+_end_back-SystemCall
- cmplw 0, r0, r12 /* Check stack overflow */
+ cmplw 0,r0,r12 /* Check stack overflow */
bgt 1f
stw r12,0(r20)
@@ -570,7 +462,7 @@
_end_of_vectors:
- . = 0x2100
+ . = . + (0x100 - ( . & 0xff )) /* align for debug */
/*
* This code finishes saving the registers to the exception frame
@@ -655,26 +547,58 @@
REST_GPR(31, r1)
lwz r2,_NIP(r1) /* Restore environment */
lwz r0,_MSR(r1)
- mtspr 990,r2 /* SRR2 */
- mtspr 991,r0 /* SRR3 */
+ mtspr SPRN_CSRR0,r2
+ mtspr SPRN_CSRR1,r0
lwz r0,GPR0(r1)
lwz r2,GPR2(r1)
lwz r1,GPR1(r1)
SYNC
rfci
+mck_return:
+ mfmsr r28 /* Disable interrupts */
+ li r4,0
+ ori r4,r4,MSR_EE
+ andc r28,r28,r4
+ SYNC /* Some chip revs need this... */
+ mtmsr r28
+ SYNC
+ lwz r2,_CTR(r1)
+ lwz r0,_LINK(r1)
+ mtctr r2
+ mtlr r0
+ lwz r2,_XER(r1)
+ lwz r0,_CCR(r1)
+ mtspr XER,r2
+ mtcrf 0xFF,r0
+ REST_10GPRS(3, r1)
+ REST_10GPRS(13, r1)
+ REST_8GPRS(23, r1)
+ REST_GPR(31, r1)
+ lwz r2,_NIP(r1) /* Restore environment */
+ lwz r0,_MSR(r1)
+ mtspr SPRN_MCSRR0,r2
+ mtspr SPRN_MCSRR1,r0
+ lwz r0,GPR0(r1)
+ lwz r2,GPR2(r1)
+ lwz r1,GPR1(r1)
+ SYNC
+ rfmci
+
/* Cache functions.
*/
invalidate_icache:
mfspr r0,L1CSR1
- ori r0,r0,0x0002
+ ori r0,r0,L1CSR1_ICFI
+ msync
+ isync
mtspr L1CSR1,r0
isync
- blr /* entire I cache */
+ blr /* entire I cache */
invalidate_dcache:
mfspr r0,L1CSR0
- ori r0,r0,0x0002
+ ori r0,r0,L1CSR0_DCFI
msync
isync
mtspr L1CSR0,r0
@@ -697,9 +621,9 @@
.globl icache_disable
icache_disable:
mfspr r0,L1CSR1
- lis r1,0xfffffffe@h
- ori r1,r1,0xfffffffe@l
- and r0,r0,r1
+ lis r3,0
+ ori r3,r3,L1CSR1_ICE
+ andc r0,r0,r3
mtspr L1CSR1,r0
isync
blr
@@ -707,7 +631,7 @@
.globl icache_status
icache_status:
mfspr r3,L1CSR1
- andi. r3,r3,1
+ andi. r3,r3,L1CSR1_ICE
blr
.globl dcache_enable
@@ -727,12 +651,10 @@
.globl dcache_disable
dcache_disable:
- mfspr r0,L1CSR0
- lis r1,0xfffffffe@h
- ori r1,r1,0xfffffffe@l
- and r0,r0,r1
- msync
- isync
+ mfspr r3,L1CSR0
+ lis r4,0
+ ori r4,r4,L1CSR0_DCE
+ andc r3,r3,r4
mtspr L1CSR0,r0
isync
blr
@@ -740,27 +662,27 @@
.globl dcache_status
dcache_status:
mfspr r3,L1CSR0
- andi. r3,r3,1
+ andi. r3,r3,L1CSR0_DCE
blr
.globl get_pir
get_pir:
- mfspr r3, PIR
+ mfspr r3,PIR
blr
.globl get_pvr
get_pvr:
- mfspr r3, PVR
+ mfspr r3,PVR
blr
.globl get_svr
get_svr:
- mfspr r3, SVR
+ mfspr r3,SVR
blr
.globl wr_tcr
wr_tcr:
- mtspr TCR, r3
+ mtspr TCR,r3
blr
/*------------------------------------------------------------------------------- */
@@ -913,16 +835,16 @@
*/
.globl relocate_code
relocate_code:
- mr r1, r3 /* Set new stack pointer */
- mr r9, r4 /* Save copy of Init Data pointer */
- mr r10, r5 /* Save copy of Destination Address */
+ mr r1,r3 /* Set new stack pointer */
+ mr r9,r4 /* Save copy of Init Data pointer */
+ mr r10,r5 /* Save copy of Destination Address */
- mr r3, r5 /* Destination Address */
- lis r4, CFG_MONITOR_BASE@h /* Source Address */
- ori r4, r4, CFG_MONITOR_BASE@l
+ mr r3,r5 /* Destination Address */
+ lis r4,CFG_MONITOR_BASE@h /* Source Address */
+ ori r4,r4,CFG_MONITOR_BASE@l
lwz r5,GOT(__init_end)
sub r5,r5,r4
- li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
+ li r6,CFG_CACHELINE_SIZE /* Cache Line Size */
/*
* Fix GOT pointer:
@@ -931,12 +853,12 @@
*
* Offset:
*/
- sub r15, r10, r4
+ sub r15,r10,r4
/* First our own GOT */
- add r14, r14, r15
+ add r14,r14,r15
/* the the one used by the C code */
- add r30, r30, r15
+ add r30,r30,r15
/*
* Now relocate code
@@ -997,10 +919,10 @@
* initialization, now running from RAM.
*/
- addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
+ addi r0,r10,in_ram - _start + _START_OFFSET
mtlr r0
blr /* NEVER RETURNS! */
-
+ .globl in_ram
in_ram:
/*
@@ -1044,19 +966,19 @@
lwz r3,GOT(__bss_start)
lwz r4,GOT(_end)
- cmplw 0, r3, r4
+ cmplw 0,r3,r4
beq 6f
- li r0, 0
+ li r0,0
5:
- stw r0, 0(r3)
- addi r3, r3, 4
- cmplw 0, r3, r4
+ stw r0,0(r3)
+ addi r3,r3,4
+ cmplw 0,r3,r4
bne 5b
6:
- mr r3, r9 /* Init Data pointer */
- mr r4, r10 /* Destination Address */
+ mr r3,r9 /* Init Data pointer */
+ mr r4,r10 /* Destination Address */
bl board_init_r
/*
@@ -1067,52 +989,54 @@
*/
.globl trap_init
trap_init:
- lwz r7, GOT(_start)
- lwz r8, GOT(_end_of_vectors)
+ lwz r7,GOT(_start_of_vectors)
+ lwz r8,GOT(_end_of_vectors)
- li r9, 0x100 /* reset vector always at 0x100 */
+ li r9,0x100 /* reset vector always at 0x100 */
- cmplw 0, r7, r8
+ cmplw 0,r7,r8
bgelr /* return if r7>=r8 - just in case */
mflr r4 /* save link register */
1:
- lwz r0, 0(r7)
- stw r0, 0(r9)
- addi r7, r7, 4
- addi r9, r9, 4
- cmplw 0, r7, r8
+ lwz r0,0(r7)
+ stw r0,0(r9)
+ addi r7,r7,4
+ addi r9,r9,4
+ cmplw 0,r7,r8
bne 1b
/*
* relocate `hdlr' and `int_return' entries
*/
- li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
+ li r7,.L_CriticalInput - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_DataStorage - _start + EXC_OFF_SYS_RESET
+ li r7,.L_MachineCheck - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_InstStorage - _start + EXC_OFF_SYS_RESET
+ li r7,.L_DataStorage - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_ExtInterrupt - _start + EXC_OFF_SYS_RESET
+ li r7,.L_InstStorage - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
+ li r7,.L_ExtInterrupt - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
+ li r7,.L_Alignment - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
+ li r7,.L_ProgramCheck - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_Decrementer - _start + EXC_OFF_SYS_RESET
+ li r7,.L_FPUnavailable - _start + _START_OFFSET
bl trap_reloc
- li r7, .L_IntervalTimer - _start + EXC_OFF_SYS_RESET
- li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
+ li r7,.L_Decrementer - _start + _START_OFFSET
+ bl trap_reloc
+ li r7,.L_IntervalTimer - _start + _START_OFFSET
+ li r8,_end_of_vectors - _start + _START_OFFSET
2:
bl trap_reloc
- addi r7, r7, 0x100 /* next exception vector */
- cmplw 0, r7, r8
+ addi r7,r7,0x100 /* next exception vector */
+ cmplw 0,r7,r8
blt 2b
lis r7,0x0
- mtspr IVPR, r7
+ mtspr IVPR,r7
mtlr r4 /* restore link register */
blr
@@ -1121,13 +1045,13 @@
* Function: relocate entries for one exception vector
*/
trap_reloc:
- lwz r0, 0(r7) /* hdlr ... */
- add r0, r0, r3 /* ... += dest_addr */
- stw r0, 0(r7)
+ lwz r0,0(r7) /* hdlr ... */
+ add r0,r0,r3 /* ... += dest_addr */
+ stw r0,0(r7)
- lwz r0, 4(r7) /* int_return ... */
- add r0, r0, r3 /* ... += dest_addr */
- stw r0, 4(r7)
+ lwz r0,4(r7) /* int_return ... */
+ add r0,r0,r3 /* ... += dest_addr */
+ stw r0,4(r7)
blr
@@ -1135,13 +1059,13 @@
.globl unlock_ram_in_cache
unlock_ram_in_cache:
/* invalidate the INIT_RAM section */
- lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
- ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
- li r2,512
- mtctr r2
-1: icbi r0, r3
- dcbi r0, r3
- addi r3, r3, 32
+ lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
+ ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
+ li r4,512
+ mtctr r4
+1: icbi r0,r3
+ dcbi r0,r3
+ addi r3,r3,32
bdnz 1b
sync /* Wait for all icbi to complete on bus */
isync
diff --git a/cpu/mpc85xx/traps.c b/cpu/mpc85xx/traps.c
index 9cd621c..efc80c7 100644
--- a/cpu/mpc85xx/traps.c
+++ b/cpu/mpc85xx/traps.c
@@ -1,6 +1,7 @@
/*
* linux/arch/ppc/kernel/traps.c
*
+ * Copyright 2007 Freescale Semiconductor.
* Copyright (C) 2003 Motorola
* Modified by Xianghua Xiao(x.xiao@motorola.com)
*
@@ -145,10 +146,13 @@
panic("Critical Input Exception");
}
+int machinecheck_count = 0;
+int machinecheck_error = 0;
void
MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup;
+ unsigned int mcsr, mcsrr0, mcsrr1, mcar;
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
@@ -159,34 +163,62 @@
return;
}
+ mcsrr0 = mfspr(SPRN_MCSRR0);
+ mcsrr1 = mfspr(SPRN_MCSRR1);
+ mcsr = mfspr(SPRN_MCSR);
+ mcar = mfspr(SPRN_MCAR);
+
+ machinecheck_count++;
+ machinecheck_error=1;
+
#if defined(CONFIG_CMD_KGDB)
if (debugger_exception_handler && (*debugger_exception_handler)(regs))
return;
#endif
printf("Machine check in kernel mode.\n");
- printf("Caused by (from msr): ");
- printf("regs %p ",regs);
- switch( regs->msr & 0x000F0000) {
- case (0x80000000>>12):
- printf("Machine check signal - probably due to mm fault\n"
- "with mmu off\n");
- break;
- case (0x80000000>>13):
- printf("Transfer error ack signal\n");
- break;
- case (0x80000000>>14):
- printf("Data parity signal\n");
- break;
- case (0x80000000>>15):
- printf("Address parity signal\n");
- break;
- default:
- printf("Unknown values in msr\n");
- }
+ printf("Caused by (from mcsr): ");
+ printf("mcsr = 0x%08x\n", mcsr);
+ if (mcsr & 0x80000000)
+ printf("Machine check input pin\n");
+ if (mcsr & 0x40000000)
+ printf("Instruction cache parity error\n");
+ if (mcsr & 0x20000000)
+ printf("Data cache push parity error\n");
+ if (mcsr & 0x10000000)
+ printf("Data cache parity error\n");
+ if (mcsr & 0x00000080)
+ printf("Bus instruction address error\n");
+ if (mcsr & 0x00000040)
+ printf("Bus Read address error\n");
+ if (mcsr & 0x00000020)
+ printf("Bus Write address error\n");
+ if (mcsr & 0x00000010)
+ printf("Bus Instruction data bus error\n");
+ if (mcsr & 0x00000008)
+ printf("Bus Read data bus error\n");
+ if (mcsr & 0x00000004)
+ printf("Bus Write bus error\n");
+ if (mcsr & 0x00000002)
+ printf("Bus Instruction parity error\n");
+ if (mcsr & 0x00000001)
+ printf("Bus Read parity error\n");
+
show_regs(regs);
+ printf("MCSR=0x%08x \tMCSRR0=0x%08x \nMCSRR1=0x%08x \tMCAR=0x%08x\n",
+ mcsr, mcsrr0, mcsrr1, mcar);
print_backtrace((unsigned long *)regs->gpr[1]);
- panic("machine check");
+ if (machinecheck_count > 10) {
+ panic("machine check count too high\n");
+ }
+
+ if (machinecheck_count > 1) {
+ regs->nip += 4; /* skip offending instruction */
+ printf("Skipping current instr, Returning to 0x%08x\n",
+ regs->nip);
+ } else {
+ printf("Returning back to 0x%08x\n",regs->nip);
+ }
}
void
@@ -253,6 +285,33 @@
regs->nip, regs->msr, regs->trap);
_exception(0, regs);
}
+void
+ExtIntException(struct pt_regs *regs)
+{
+ volatile immap_t *immap = (immap_t *)CFG_IMMR;
+ volatile ccsr_pic_t *pic = &immap->im_pic;
+ uint vect;
+
+#if defined(CONFIG_CMD_KGDB)
+ if (debugger_exception_handler && (*debugger_exception_handler)(regs))
+ return;
+#endif
+
+ printf("External Interrupt Exception at PC: %lx, SR: %lx, vector=%lx",
+ regs->nip, regs->msr, regs->trap);
+ vect = pic->iack0;
+ printf(" irq IACK0@%05x=%d\n",&pic->iack0,vect);
+ show_regs(regs);
+ print_backtrace((unsigned long *)regs->gpr[1]);
+ machinecheck_count++;
+#ifdef EXTINT_NOSKIP
+ printf("Returning back to 0x%08x\n",regs->nip);
+#else
+ regs->nip += 4; /* skip offending instruction */
+ printf("Skipping current instr, Returning to 0x%08x\n",regs->nip);
+#endif
+
+}
void
DebugException(struct pt_regs *regs)
diff --git a/doc/README.mpc8544ds b/doc/README.mpc8544ds
new file mode 100644
index 0000000..14c7f76
--- /dev/null
+++ b/doc/README.mpc8544ds
@@ -0,0 +1,122 @@
+Overview
+--------
+The MPC8544DS system is similar to the 85xx CDS systems such
+as the MPC8548CDS due to the similar E500 core. However, it
+is placed on the same board as the 8641 HPCN system.
+
+
+Flash Banks
+-----------
+Like the 85xx CDS systems, the 8544 DS board has two flash banks.
+They are both present on boot, but there locations can be swapped
+using the dip-switch SW10, bit 2.
+
+However, unlike the CDS systems, but similar to the 8641 HPCN
+board, a runtime reset through the FPGA can also affect a swap
+on the flash bank mappings for the next reset cycle.
+
+Irrespective of the switch SW10[2], booting is always from the
+boot bank at 0xfff8_0000.
+
+
+Memory Map
+----------
+
+0xff80_0000 - 0xffbf_ffff Alernate bank 4MB
+0xffc0_0000 - 0xffff_ffff Boot bank 4MB
+
+0xffb8_0000 Alternate image start 512KB
+0xfff8_0000 Boot image start 512KB
+
+
+Flashing Images
+---------------
+
+For example, to place a new image in the alternate flash bank
+and then reset with that new image temporarily, use this:
+
+ tftp 1000000 u-boot.bin.8544ds
+ erase ffb80000 ffbfffff
+ cp.b 1000000 ffb80000 80000
+ pixis_reset altbank
+
+
+To overwrite the image in the boot flash bank:
+
+ tftp 1000000 u-boot.bin.8544ds
+ protect off all
+ erase fff80000 ffffffff
+ cp.b 1000000 fff80000 80000
+
+Other example U-Boot image and flash manipulations examples
+can be found in the README.mpc85xxcds file as well.
+
+
+The pixis_reset command
+-----------------------
+A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
+using the FPGA sequencer. When the board restarts, it has the option
+of using either the current or alternate flash bank as the boot
+image, with or without the watchdog timer enabled, and finally with
+or without frequency changes.
+
+Usage is;
+
+ pixis_reset
+ pixis_reset altbank
+ pixis_reset altbank wd
+ pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+ pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
+
+Examples;
+
+ /* reset to current bank, like "reset" command */
+ pixis_reset
+
+ /* reset board but use the to alternate flash bank */
+ pixis_reset altbank
+
+ /* reset board, use alternate flash bank with watchdog timer enabled*/
+ pixis_reset altbank wd
+
+ /* reset board to alternate bank with frequency changed.
+ * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
+ */
+ pixis-reset altbank cf 40 2.5 10
+
+Valid clock choices are in the 8641 Reference Manuals.
+
+
+Using the Device Tree Source File
+---------------------------------
+To create the DTB (Device Tree Binary) image file,
+use a command similar to this:
+
+ dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb
+
+Likely, that .dts file will come from here;
+
+ linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
+
+After placing the DTB file in your TFTP disk area,
+you can download that dtb file using a command like:
+
+ tftp 900000 mpc8544ds.dtb
+
+Burn it to flash if you want.
+
+
+Booting Linux
+-------------
+
+Place a linux uImage in the TFTP disk area too.
+
+ tftp 1000000 uImage.8544
+ tftp 900000 mpc8544ds.dtb
+ bootm 1000000 - 900000
+
+Watch your ethact, netdev and bootargs U-Boot environment variables.
+You may want to do something like this too:
+
+ setenv ethact eTSEC3
+ setenv netdev eth1
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index c416a67..89a7279 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -391,17 +391,17 @@
return 0;
}
-static int init_mii_management_configuration(uec_t *uec_regs)
+static int init_mii_management_configuration(uec_mii_t *uec_mii_regs)
{
uint timeout = 0x1000;
u32 miimcfg = 0;
- miimcfg = in_be32(&uec_regs->miimcfg);
+ miimcfg = in_be32(&uec_mii_regs->miimcfg);
miimcfg |= MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE;
- out_be32(&uec_regs->miimcfg, miimcfg);
+ out_be32(&uec_mii_regs->miimcfg, miimcfg);
/* Wait until the bus is free */
- while ((in_be32(&uec_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
+ while ((in_be32(&uec_mii_regs->miimcfg) & MIIMIND_BUSY) && timeout--);
if (timeout <= 0) {
printf("%s: The MII Bus is stuck!", __FUNCTION__);
return -ETIMEDOUT;
@@ -413,13 +413,13 @@
static int init_phy(struct eth_device *dev)
{
uec_private_t *uec;
- uec_t *uec_regs;
+ uec_mii_t *umii_regs;
struct uec_mii_info *mii_info;
struct phy_info *curphy;
int err;
uec = (uec_private_t *)dev->priv;
- uec_regs = uec->uec_regs;
+ umii_regs = uec->uec_mii_regs;
uec->oldlink = 0;
uec->oldspeed = 0;
@@ -451,19 +451,19 @@
mii_info->mii_id = uec->uec_info->phy_address;
mii_info->dev = dev;
- mii_info->mdio_read = &read_phy_reg;
- mii_info->mdio_write = &write_phy_reg;
+ mii_info->mdio_read = &uec_read_phy_reg;
+ mii_info->mdio_write = &uec_write_phy_reg;
uec->mii_info = mii_info;
- if (init_mii_management_configuration(uec_regs)) {
+ if (init_mii_management_configuration(umii_regs)) {
printf("%s: The MII Bus is stuck!", dev->name);
err = -1;
goto bus_fail;
}
/* get info for this PHY */
- curphy = get_phy_info(uec->mii_info);
+ curphy = uec_get_phy_info(uec->mii_info);
if (!curphy) {
printf("%s: No PHY found", dev->name);
err = -1;
@@ -989,6 +989,13 @@
/* Setup MAC interface mode */
uec_set_mac_if_mode(uec, uec_info->enet_interface);
+ /* Setup MII management base */
+#ifndef CONFIG_eTSEC_MDIO_BUS
+ uec->uec_mii_regs = (uec_mii_t *)(&uec_regs->miimcfg);
+#else
+ uec->uec_mii_regs = (uec_mii_t *) CONFIG_MIIM_ADDRESS;
+#endif
+
/* Setup MII master clock source */
qe_set_mii_clk_src(uec_info->uf_info.ucc_num);
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 0495026..c384055 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -675,6 +675,7 @@
ucc_fast_private_t *uccf;
struct eth_device *dev;
uec_t *uec_regs;
+ uec_mii_t *uec_mii_regs;
/* enet init command parameter */
uec_init_cmd_pram_t *p_init_enet_param;
u32 init_enet_param_offset;
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index 76fd388..ca6faa6 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -60,14 +60,14 @@
/* Write value to the PHY for this device to the register at regnum, */
/* waiting until the write is done before it returns. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
-void write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
+void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int value)
{
uec_private_t *ugeth = (uec_private_t *) dev->priv;
- uec_t *ug_regs;
+ uec_mii_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
- ug_regs = ugeth->uec_regs;
+ ug_regs = ugeth->uec_mii_regs;
/* Stop the MII management read cycle */
out_be32 (&ug_regs->miimcom, 0);
@@ -87,15 +87,15 @@
/* Reads from register regnum in the PHY for device dev, */
/* returning the value. Clears miimcom first. All PHY */
/* configuration has to be done through the TSEC1 MIIM regs */
-int read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
+int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum)
{
uec_private_t *ugeth = (uec_private_t *) dev->priv;
- uec_t *ug_regs;
+ uec_mii_t *ug_regs;
enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum;
u32 tmp_reg;
u16 value;
- ug_regs = ugeth->uec_regs;
+ ug_regs = ugeth->uec_mii_regs;
/* Setting up the MII Mangement Address Register */
tmp_reg = ((u32) mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
@@ -521,7 +521,7 @@
/* Use the PHY ID registers to determine what type of PHY is attached
* to device dev. return a struct phy_info structure describing that PHY
*/
-struct phy_info *get_phy_info (struct uec_mii_info *mii_info)
+struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info)
{
u16 phy_reg;
u32 phy_ID;
diff --git a/drivers/qe/uec_phy.h b/drivers/qe/uec_phy.h
index 9bd926d..e59a940 100644
--- a/drivers/qe/uec_phy.h
+++ b/drivers/qe/uec_phy.h
@@ -249,10 +249,10 @@
void (*close) (struct uec_mii_info * mii_info);
};
-struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
-void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
+struct phy_info *uec_get_phy_info (struct uec_mii_info *mii_info);
+void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
int value);
-int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
+int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
u32 interrupts);
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index bbaeb3f..1f1583a 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -71,16 +71,16 @@
u32 lclk_clk;
u32 ddr_clk;
u32 pci_clk;
+#if defined(CONFIG_MPC8360)
+ u32 ddr_sec_clk;
+#endif /* CONFIG_MPC8360 */
+#endif
#if defined(CONFIG_QE)
u32 qe_clk;
u32 brg_clk;
uint mp_alloc_base;
uint mp_alloc_top;
#endif /* CONFIG_QE */
-#if defined (CONFIG_MPC8360)
- u32 ddr_sec_clk;
-#endif /* CONFIG_MPC8360 */
-#endif
#if defined(CONFIG_MPC5xxx)
unsigned long ipb_clk;
unsigned long pci_clk;
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e002d28..3d4816f 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1,6 +1,8 @@
/*
* MPC85xx Internal Memory Map
*
+ * Copyright 2007 Freescale Semiconductor.
+ *
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
*
@@ -1520,14 +1522,39 @@
char res58[60176];
} ccsr_rio_t;
+/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */
+typedef struct par_io {
+ uint cpodr; /* 0x100 */
+ uint cpdat; /* 0x104 */
+ uint cpdir1; /* 0x108 */
+ uint cpdir2; /* 0x10c */
+ uint cppar1; /* 0x110 */
+ uint cppar2; /* 0x114 */
+ char res[8];
+}par_io_t;
+
/*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */
+#define MPC85xx_PORBMSR_HA 0x00070000
uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */
uint pordevsr; /* 0xe000c - POR I/O device status regsiter */
+#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
+#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
+#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
+#define MPC85xx_PORDEVSR_IO_SEL 0x00380000
+#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
+#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
+#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
+#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000
+#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000
+#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060
+#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008
+#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007
uint pordbgmsr; /* 0xe0010 - POR debug mode status register */
char res1[12];
uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */
@@ -1541,6 +1568,25 @@
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
char res6[12];
uint devdisr; /* 0xe0070 - Device disable control */
+#define MPC85xx_DEVDISR_PCI1 0x80000000
+#define MPC85xx_DEVDISR_PCI2 0x40000000
+#define MPC85xx_DEVDISR_PCIE 0x20000000
+#define MPC85xx_DEVDISR_LBC 0x08000000
+#define MPC85xx_DEVDISR_PCIE2 0x04000000
+#define MPC85xx_DEVDISR_PCIE3 0x02000000
+#define MPC85xx_DEVDISR_SEC 0x01000000
+#define MPC85xx_DEVDISR_SRIO 0x00080000
+#define MPC85xx_DEVDISR_RMSG 0x00040000
+#define MPC85xx_DEVDISR_DDR 0x00010000
+#define MPC85xx_DEVDISR_CPU 0x00008000
+#define MPC85xx_DEVDISR_TB 0x00004000
+#define MPC85xx_DEVDISR_DMA 0x00000400
+#define MPC85xx_DEVDISR_TSEC1 0x00000080
+#define MPC85xx_DEVDISR_TSEC2 0x00000040
+#define MPC85xx_DEVDISR_TSEC3 0x00000020
+#define MPC85xx_DEVDISR_TSEC4 0x00000010
+#define MPC85xx_DEVDISR_I2C 0x00000004
+#define MPC85xx_DEVDISR_DUART 0x00000002
char res7[12];
uint powmgtcsr; /* 0xe0080 - Power management status and control register */
char res8[12];
@@ -1550,7 +1596,13 @@
uint svr; /* 0xe00a4 - System version register */
char res10a[8];
uint rstcr; /* 0xe00b0 - Reset control register */
+#ifdef MPC8568
+ char res10b[76];
+ par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
+ char res10c[3136];
+#else
char res10b[3404];
+#endif
uint clkocr; /* 0xe0e00 - Clock out select register */
char res11[12];
uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */
@@ -1562,7 +1614,7 @@
uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */
uint res14; /* 0xe0f28 */
uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */
- char res15[61651];
+ char res15[61648]; /* 0xe0f30 to 0xefffff */
} ccsr_gur_t;
#define PORDEVSR_PCI (0x00800000) /* PCI Mode */
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 950b949..a16a6d3 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -281,6 +281,17 @@
u8 res4[0x200 - 0x091];
} __attribute__ ((packed)) ucc_slow_t;
+typedef struct ucc_mii_mng {
+ u32 miimcfg; /* MII management configuration reg */
+ u32 miimcom; /* MII management command reg */
+ u32 miimadd; /* MII management address reg */
+ u32 miimcon; /* MII management control reg */
+ u32 miimstat; /* MII management status reg */
+ u32 miimind; /* MII management indication reg */
+ u32 ifctl; /* interface control reg */
+ u32 ifstat; /* interface statux reg */
+} __attribute__ ((packed))uec_mii_t;
+
typedef struct ucc_ethernet {
u32 maccfg1; /* mac configuration reg. 1 */
u32 maccfg2; /* mac configuration reg. 2 */
@@ -540,14 +551,21 @@
u8 res14[0x300];
u8 res15[0x3A00];
u8 res16[0x8000]; /* 0x108000 - 0x110000 */
+#if defined(CONFIG_MPC8568)
+ u8 muram[0x10000]; /* 0x1_0000 - 0x2_0000 Multi-user RAM */
+ u8 res17[0x20000]; /* 0x2_0000 - 0x4_0000 */
+#else
u8 muram[0xC000]; /* 0x110000 - 0x11C000 Multi-user RAM */
u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
u8 res18[0xC0000]; /* 0x140000 - 0x200000 */
+#endif
} __attribute__ ((packed)) qe_map_t;
extern qe_map_t *qe_immr;
-#if defined(CONFIG_MPC8360)
+#if defined(CONFIG_MPC8568)
+#define QE_MURAM_SIZE 0x10000UL
+#elif defined(CONFIG_MPC8360)
#define QE_MURAM_SIZE 0xc000UL
#elif defined(CONFIG_MPC832X)
#define QE_MURAM_SIZE 0x4000UL
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 9be5a27..0a160e2 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -217,12 +217,14 @@
#define HID0_DPM (1<<20)
#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */
#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */
+#define HID0_TBEN (1<<14) /* Time Base Enable */
#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */
#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */
#define HID0_DCI HID0_DCFI
#define HID0_SPD (1<<9) /* Speculative disable */
+#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */
#define HID0_SGE (1<<7) /* Store Gathering Enable */
#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */
#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */
@@ -450,6 +452,7 @@
#define SPRN_PID1 0x279 /* Process ID Register 1 */
#define SPRN_PID2 0x27a /* Process ID Register 2 */
#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */
+#define SPRN_MCAR 0x23d /* Machine Check Address register */
#ifdef CONFIG_440
#define MCSR_MCS 0x80000000 /* Machine Check Summary */
#define MCSR_IB 0x40000000 /* Instruction PLB Error */
diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h
index 50d3b6b..232f171 100644
--- a/include/configs/MPC8541CDS.h
+++ b/include/configs/MPC8541CDS.h
@@ -350,6 +350,13 @@
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x100000 /* 1M */
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
index d0f94a3..32934e1 100644
--- a/include/configs/MPC8544DS.h
+++ b/include/configs/MPC8544DS.h
@@ -34,14 +34,14 @@
#define CONFIG_MPC8544 1
#define CONFIG_MPC8544DS 1
-#undef CONFIG_PCI /* Enable PCI/PCIE */
-#undef CONFIG_PCI1 /* PCI controller 1 */
-#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
-#undef CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
-#undef CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
-#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI 1 /* Enable PCI/PCIE */
+#define CONFIG_PCI1 1 /* PCI controller 1 */
+#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#undef CONFIG_DDR_DLL
@@ -52,6 +52,7 @@
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_DDR_ECC_CMD
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
* When initializing flash, if we cannot find the manufacturer ID,
@@ -70,7 +71,7 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
@@ -86,13 +87,13 @@
#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
#define CFG_MEMTEST_END 0x00400000
#define CFG_ALT_MEMTEST
-#define CONFIG_PANIC_HANG /* do not reset board on panic */
+#define CONFIG_PANIC_HANG /* do not reset board on panic */
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
@@ -344,7 +345,7 @@
#define CONFIG_SATA_ULI5288
#define CFG_SCSI_MAX_SCSI_ID 4
#define CFG_SCSI_MAX_LUN 1
-#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
+#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
#endif /* SCSCI */
@@ -354,7 +355,7 @@
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
@@ -365,6 +366,10 @@
#define CONFIG_TSEC3_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
+#define CONFIG_TSEC_TBI 1 /* enable internal TBI phy */
+#define CONFIG_SGMII_RISER
+#define TSEC1_SGMII_PHY_ADDR_OFFSET 0x1c /* sgmii phy base */
+
#define TSEC1_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
@@ -374,7 +379,6 @@
#define CONFIG_ETHPRIME "eTSEC1"
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
-
#endif /* CONFIG_TSEC_ENET */
/*
@@ -392,7 +396,6 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
@@ -415,6 +418,8 @@
#define CONFIG_CMD_PCI
#define CONFIG_CMD_BEDBUG
#define CONFIG_CMD_NET
+ #define CONFIG_CMD_SCSI
+ #define CONFIG_CMD_EXT2
#endif
@@ -441,10 +446,10 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
+#define CFG_DCACHE_SIZE 32768
#define CFG_CACHELINE_SIZE 32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
@@ -482,7 +487,8 @@
#define CONFIG_HOSTNAME 8544ds_unknown
#define CONFIG_ROOTPATH /nfs/mpc85xx
-#define CONFIG_BOOTFILE 8544ds_tmt/uImage.uboot
+#define CONFIG_BOOTFILE 8544ds/uImage.uboot
+#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.0.1
#define CONFIG_GATEWAYIP 192.168.0.1
@@ -491,7 +497,7 @@
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
@@ -499,10 +505,7 @@
#define PCIE_ENV \
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
- "pcie1regs=setenv a e000a; run pciereg\0" \
- "pcie2regs=setenv a e0009; run pciereg\0" \
- "pcie3regs=setenv a e000b; run pciereg\0" \
- "pcieerr=md ${a}020 1; md ${a}e00;" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e;" \
"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1;" \
"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
@@ -511,12 +514,18 @@
"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
"pci w $b.0 130 ffffffff\0" \
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
- "pcie1err=setenv a e000a; run pcieerr\0" \
- "pcie2err=setenv a e0009; run pcieerr\0" \
- "pcie3err=setenv a e000b; run pcieerr\0" \
- "pcie1errc=setenv a e000a; run pcieerrc\0" \
- "pcie2errc=setenv a e0009; run pcieerrc\0" \
- "pcie3errc=setenv a e000b; run pcieerrc\0"
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie2regs=setenv a e0009; run pciereg\0" \
+ "pcie3regs=setenv a e000b; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie2cfg=setenv b 5; run pciecfg\0" \
+ "pcie3cfg=setenv b 0; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
+ "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
+ "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
+ "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
#else
#define PCIE_ENV ""
#endif
@@ -524,14 +533,14 @@
#if defined(CONFIG_PCI1)
#define PCI_ENV \
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
- "echo e;md ${a}e00 9\0" \
+ "echo e;md ${a}e00 9\0" \
"pci1regs=setenv a e0008; run pcireg\0" \
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
"pci d.w $b.0 56 1\0" \
- "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
- "pci w.w $b.0 56 ffff\0" \
- "pci1err=setenv a e0008; run pcierr\0" \
- "pci1errc=setenv a e0008; run pcierrc\0"
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
+ "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
#else
#define PCI_ENV ""
#endif
@@ -551,25 +560,39 @@
#define ENET_ENV ""
#endif
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
- "ramdiskfile=8544ds_tmt/ramdisk.uboot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=8544ds_tmt/mpc8544ds.dtb\0" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
+ "ramdiskfile=8544ds/ramdisk.uboot\0" \
+ "dtbaddr=c00000\0" \
+ "dtbfile=8544ds/mpc8544ds.dtb\0" \
+ "bdev=sda3\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
- "ddrregs=setenv a e0002; run ddrreg\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
- "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
- "guregs=setenv a e00e0; run gureg\0" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
- "ecmregs=setenv a e0001; run ecmreg\0" \
- PCIE_ENV \
- PCI_ENV \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
ENET_ENV
@@ -579,23 +602,23 @@
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
-#define CONFIG_RAMBOOTCOMMAND \
+#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
-#define CONFIG_BOOTCOMMAND \
- "setenv bootargs root=/dev/sda3 rw " \
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 2e84fc8..cda9fd5 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -11,7 +11,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -36,8 +36,14 @@
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
-#define CONFIG_PCI
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#define CONFIG_PCI /* enable any pci type devices */
+#define CONFIG_PCI1 /* PCI controller 1 */
+#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#undef CONFIG_RIO
+#undef CONFIG_PCI2
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
@@ -46,6 +52,7 @@
#define CONFIG_DDR_ECC /* only for ECC DDR module */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
/*
@@ -65,16 +72,16 @@
/*
* These can be toggled for performance analysis, otherwise use default.
*/
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_L2_CACHE /* toggle L2 cache */
+#define CONFIG_BTB /* toggle branch predition */
+#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
+#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#undef CFG_DRAM_TEST /* memory test, takes time */
@@ -85,10 +92,14 @@
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
-#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
+#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
+#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
+#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
+
/*
* DDR Setup
*/
@@ -106,7 +117,6 @@
#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Local Bus Definitions
*/
@@ -124,9 +134,9 @@
* Use GPCM = BRx[24:26] = 000
* Valid = BRx[31] = 1
*
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
- * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
+ * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
*
* OR0, OR1:
* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
@@ -137,11 +147,12 @@
* TRLX = use relaxed timing = ORx[29] = 1
* EAD = use external address latch delay = OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
- * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
+ * 0 4 8 12 16 20 24 28
+ * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 8M */
+#define CFG_BOOT_BLOCK 0xff000000 /* boot TLB block */
+#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 16M */
#define CFG_BR0_PRELIM 0xff801001
#define CFG_BR1_PRELIM 0xff001001
@@ -156,7 +167,7 @@
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
@@ -166,7 +177,12 @@
/*
* SDRAM on the Local Bus
*/
-#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
+#define CFG_LBC_CACHE_SIZE 64
+#define CFG_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
+#define CFG_LBC_NONCACHE_SIZE 64
+
+#define CFG_LBC_SDRAM_BASE CFG_LBC_CACHE_BASE /* Localbus SDRAM */
#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
@@ -180,14 +196,14 @@
* SDRAM for MSEL = BR2[24:26] = 011
* Valid = BR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
*
* FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
* FIXME: the top 17 bits of BR2.
*/
-#define CFG_BR2_PRELIM 0xf0001861
+#define CFG_BR2_PRELIM 0xf0001861
/*
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
@@ -196,19 +212,19 @@
* 64MB mask for AM, OR2[0:7] = 1111 1100
* XAM, OR2[17:18] = 11
* 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
+ * 13 rows OR2[23-25] = 100
* EAD set for extra time OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CFG_OR2_PRELIM 0xfc006901
-#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
-#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
-#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
-#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
+#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
+#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
+#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
+#define CFG_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
@@ -236,7 +252,7 @@
/*
* Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1)
- * or BSMA1617 (for CPU 1.0) (old)
+ * or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFCR16 \
@@ -256,61 +272,63 @@
* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
* port-size = 8-bits = BR[19:20] = 01
* no parity checking = BR[21:22] = 00
- * GPMC for MSEL = BR[24:26] = 000
- * Valid = BR[31] = 1
+ * GPMC for MSEL = BR[24:26] = 000
+ * Valid = BR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
*
* For OR3, need:
- * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
+ * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
* disable buffer ctrl OR[19] = 0
- * CSNT OR[20] = 1
- * ACS OR[21:22] = 11
- * XACS OR[23] = 1
+ * CSNT OR[20] = 1
+ * ACS OR[21:22] = 11
+ * XACS OR[23] = 1
* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
- * SETA OR[28] = 0
- * TRLX OR[29] = 1
- * EHTR OR[30] = 1
- * EAD extra time OR[31] = 1
+ * SETA OR[28] = 0
+ * TRLX OR[29] = 1
+ * EHTR OR[30] = 1
+ * EAD extra time OR[31] = 1
*
- * 0 4 8 12 16 20 24 28
+ * 0 4 8 12 16 20 24 28
* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
*/
#define CADMUS_BASE_ADDR 0xf8000000
-#define CFG_BR3_PRELIM 0xf8000801
-#define CFG_OR3_PRELIM 0xfff00ff7
+#define CFG_BR3_PRELIM 0xf8000801
+#define CFG_OR3_PRELIM 0xfff00ff7
#define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK 1
+#define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
+
+#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 2
+#define CONFIG_CONS_INDEX 2
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
-#define CFG_NS16550_REG_SIZE 1
+#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK get_bus_freq(0)
-#define CFG_BAUDRATE_TABLE \
+#define CFG_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
-#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
+#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
+#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
/* Use the HUSH parser */
#define CFG_HUSH_PARSER
-#ifdef CFG_HUSH_PARSER
+#ifdef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
@@ -331,55 +349,74 @@
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#undef CONFIG_SOFT_I2C /* I2C bit-banged */
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_EEPROM_ADDR 0x57
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
+#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
+
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
-#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
-#define CFG_PCI2_MEM_BASE 0x90000000
+#ifdef CONFIG_PCI2
+#define CFG_PCI2_MEM_BASE 0xa0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI2_IO_BASE 0x00000000
#define CFG_PCI2_IO_PHYS 0xe2800000
-#define CFG_PCI2_IO_SIZE 0x00800000 /* 8M */
+#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#endif
-#define CFG_PEX_MEM_BASE 0xa0000000
-#define CFG_PEX_MEM_PHYS CFG_PEX_MEM_BASE
-#define CFG_PEX_MEM_SIZE 0x20000000 /* 512M */
-#define CFG_PEX_IO_BASE 0x00000000
-#define CFG_PEX_IO_PHYS 0xe3000000
-#define CFG_PEX_IO_SIZE 0x01000000 /* 16M */
+#ifdef CONFIG_PCIE1
+#define CFG_PCIE1_MEM_BASE 0xa0000000
+#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_PCIE1_IO_BASE 0x00000000
+#define CFG_PCIE1_IO_PHYS 0xe3000000
+#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
+#ifdef CONFIG_RIO
/*
* RapidIO MMU
*/
#define CFG_RIO_MEM_BASE 0xC0000000
#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */
+#endif
+
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_85XX_PCI2
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
+
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS 0x00000000
+#define CFG_PCI_MEMORY_PHYS 0x00000000
+#define CFG_PCI_MEMORY_SIZE 0x80000000
#endif /* CONFIG_PCI */
@@ -387,7 +424,7 @@
#if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
+#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MII 1 /* MII PHY management */
@@ -397,7 +434,7 @@
#define CONFIG_TSEC2_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC2"
-#undef CONFIG_TSEC4
+#define CONFIG_TSEC4
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
@@ -413,7 +450,7 @@
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
-
+#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
@@ -473,7 +510,7 @@
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
/* Cache Configuration */
#define CFG_DCACHE_SIZE 32768
@@ -501,58 +538,156 @@
/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
+#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
+#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
-#define CONFIG_IPADDR 192.168.1.253
+#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH /nfsroot
-#define CONFIG_BOOTFILE your.uImage
+#define CONFIG_HOSTNAME unknown
+#define CONFIG_ROOTPATH /nfsroot
+#define CONFIG_BOOTFILE 8548cds/uImage.uboot
+#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
-#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/
+#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
+#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CONFIG_BAUDRATE 115200
+#if defined(CONFIG_PCIE1)
+#define PCIE_ENV \
+ "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
+ "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
+ "pcieerr=md ${a}020 1; md ${a}e00 e; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
+ "pci d $b.0 130 1\0" \
+ "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;"\
+ "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
+ "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
+ "pcie1regs=setenv a e000a; run pciereg\0" \
+ "pcie1cfg=setenv b 3; run pciecfg\0" \
+ "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
+ "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0"
+#else
+#define PCIE_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1) || defined(CONFIG_PCI2)
+#define PCI_ENV \
+ "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
+ "echo e;md ${a}e00 9\0" \
+ "pcierr=md ${a}e00 8; pci d.b $b.0 7 1;pci d.w $b.0 1e 1;" \
+ "pci d.w $b.0 56 1\0" \
+ "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
+ "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0"
+#else
+#define PCI_ENV ""
+#endif
+
+#if defined(CONFIG_PCI1)
+#define PCI_ENV1 \
+ "pci1regs=setenv a e0008; run pcireg\0" \
+ "pci1err=setenv a e0008; setenv b 0; run pcierr\0" \
+ "pci1errc=setenv a e0008; setenv b 0; run pcierrc\0"
+#else
+#define PCI_ENV1 ""
+#endif
+
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS1\0" \
- "ramdiskaddr=600000\0" \
- "ramdiskfile=your.ramdisk.u-boot\0" \
- "fdtaddr=400000\0" \
- "fdtfile=your.fdt.dtb\0"
+#if defined(CONFIG_PCI2)
+#define PCI_ENV2 \
+ "pci2regs=setenv a e0009; run pcireg\0" \
+ "pci2err=setenv a e0009; setenv b 123; run pcierr\0" \
+ "pci2errc=setenv a e0009; setenv b 123; run pcierrc\0"
+#else
+#define PCI_ENV2 ""
+#endif
+
+#if defined(CONFIG_TSEC_ENET)
+#define ENET_ENV \
+ "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
+ "md ${a}098 2\0" \
+ "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
+ "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
+ "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
+ "echo mib;md ${a}680 31\0" \
+ "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
+ "enet1regs=setenv a e0024; run enetreg\0" \
+ "enet2regs=setenv a e0025; run enetreg\0" \
+ "enet3regs=setenv a e0026; run enetreg\0" \
+ "enet4regs=setenv a e0027; run enetreg\0"
+#else
+#define ENET_ENV ""
+#endif
+
+#if 0
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
+ "consoledev=ttyS1\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=ramdisk.uboot\0" \
+ "dtbaddr=c00000\0" \
+ "dtbfile=mpc8548cds.dtb\0" \
+ "eoi=mw e00400b0 0\0" \
+ "iack=md e00400a0 1\0" \
+ "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
+ "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
+ "ddrregs=setenv a e0002; run ddrreg\0" \
+ "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
+ "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
+ "guregs=setenv a e00e0; run gureg\0" \
+ "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
+ "ecmregs=setenv a e0001; run ecmreg\0" \
+ "lawregs=md e0000c08 4b\0" \
+ "lbcregs=md e0005000 36\0" \
+ "dma0regs=md e0021100 12\0" \
+ "dma1regs=md e0021180 12\0" \
+ "dma2regs=md e0021200 12\0" \
+ "dma3regs=md e0021280 12\0" \
+ PCIE_ENV \
+ PCI_ENV \
+ PCI_ENV1 \
+ PCI_ENV2 \
+ ENET_ENV
+#endif
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
+#define CONFIG_NFSBOOTCOMMAND \
+ "setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr - $dtbaddr"
#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "bootm $loadaddr $ramdiskaddr"
+ "setenv bootargs root=/dev/ram rw " \
+ "console=$consoledev,$baudrate $othbootargs;" \
+ "tftp $ramdiskaddr $ramdiskfile;" \
+ "tftp $loadaddr $bootfile;" \
+ "tftp $dtbaddr $dtbfile;" \
+ "bootm $loadaddr $ramdiskaddr $dtbaddr"
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
+#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
#endif /* __CONFIG_H */
diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h
index a3025bd..e8fe99a 100644
--- a/include/configs/MPC8555CDS.h
+++ b/include/configs/MPC8555CDS.h
@@ -350,6 +350,13 @@
#define CFG_PCI2_IO_PHYS 0xe2100000
#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
+#ifdef CONFIG_LEGACY
+#define BRIDGE_ID 17
+#define VIA_ID 2
+#else
+#define BRIDGE_ID 28
+#define VIA_ID 4
+#endif
#if defined(CONFIG_PCI)
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index eef168c..dc9cb1f 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -28,20 +28,21 @@
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
+#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */
#define CONFIG_MPC8568 1 /* MPC8568 specific */
#define CONFIG_MPC8568MDS 1 /* MPC8568MDS board specific */
-#undef CONFIG_PCI
+#define CONFIG_PCI
#define CONFIG_TSEC_ENET /* tsec ethernet support */
+#undef CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_DLL /* possible DLL fix needed */
/*#define CONFIG_DDR_2T_TIMING Sets the 2T timing bit */
/*#define CONFIG_DDR_ECC*/ /* only for ECC DDR module */
-/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
+/*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/ /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
@@ -297,6 +298,7 @@
#define OF_CPU "PowerPC,8568@0"
#define OF_SOC "soc8568@e0000000"
+#define OF_QE "qe@e0080000"
#define OF_TBCLK (bd->bi_busfreq / 8)
#define OF_STDOUT_PATH "/soc8568@e0000000/serial@4600"
@@ -306,11 +308,14 @@
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support*/
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_ADDR 0x52
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
+#define CFG_I2C2_OFFSET 0x3100
/*
* General PCI
@@ -318,7 +323,7 @@
*/
#define CFG_PCI1_MEM_BASE 0x80000000
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
#define CFG_PCI1_IO_BASE 0x00000000
#define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x00800000 /* 8M */
@@ -337,6 +342,44 @@
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#ifdef CONFIG_QE
+/*
+ * QE UEC ethernet configuration
+ */
+#define CONFIG_UEC_ETH
+#ifndef CONFIG_TSEC_ENET
+#define CONFIG_ETHPRIME "Freescale GETH"
+#endif
+#define CONFIG_PHY_MODE_NEED_CHANGE
+#define CONFIG_eTSEC_MDIO_BUS
+
+#ifdef CONFIG_eTSEC_MDIO_BUS
+#define CONFIG_MIIM_ADDRESS 0xE0024520
+#endif
+
+#define CONFIG_UEC_ETH1 /* GETH1 */
+
+#ifdef CONFIG_UEC_ETH1
+#define CFG_UEC1_UCC_NUM 0 /* UCC1 */
+#define CFG_UEC1_RX_CLK QE_CLK_NONE
+#define CFG_UEC1_TX_CLK QE_CLK16
+#define CFG_UEC1_ETH_TYPE GIGA_ETH
+#define CFG_UEC1_PHY_ADDR 7
+#define CFG_UEC1_INTERFACE_MODE ENET_1000_GMII
+#endif
+
+#define CONFIG_UEC_ETH2 /* GETH2 */
+
+#ifdef CONFIG_UEC_ETH2
+#define CFG_UEC2_UCC_NUM 1 /* UCC2 */
+#define CFG_UEC2_RX_CLK QE_CLK_NONE
+#define CFG_UEC2_TX_CLK QE_CLK16
+#define CFG_UEC2_ETH_TYPE GIGA_ETH
+#define CFG_UEC2_PHY_ADDR 1
+#define CFG_UEC2_INTERFACE_MODE ENET_1000_GMII
+#endif
+#endif /* CONFIG_QE */
+
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
@@ -345,13 +388,12 @@
#endif /* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1
#endif
+#if defined(CONFIG_TSEC_ENET)
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
@@ -457,12 +499,15 @@
*/
/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
+#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH)
+#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
diff --git a/include/mpc85xx.h b/include/mpc85xx.h
index 6fbd504..321b24f 100644
--- a/include/mpc85xx.h
+++ b/include/mpc85xx.h
@@ -1,14 +1,14 @@
/*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007 Freescale Semiconductor.
* Copyright(c) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
*/
#ifndef __MPC85xx_H__
#define __MPC85xx_H__
-#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
-#define _START_OFFSET EXC_OFF_SYS_RESET
+/* define for common ppc_asm.tmpl */
+#define EXC_OFF_SYS_RESET 0x100 /* System reset */
+#define _START_OFFSET 0
#if defined(CONFIG_E500)
#include <e500.h>
diff --git a/include/ppc_asm.tmpl b/include/ppc_asm.tmpl
index ac8f317..0019d46 100644
--- a/include/ppc_asm.tmpl
+++ b/include/ppc_asm.tmpl
@@ -285,7 +285,6 @@
.long hdlr - _start + _START_OFFSET; \
.long crit_return - _start + _START_OFFSET
-#ifdef CONFIG_440
#define MCK_EXCEPTION(n, label, hdlr) \
. = n; \
label: \
@@ -299,6 +298,5 @@
.L_ ## label : \
.long hdlr - _start + _START_OFFSET; \
.long mck_return - _start + _START_OFFSET
-#endif /* CONFIG_440 */
#endif /* __PPC_ASM_TMPL__ */