diff --git a/Makefile b/Makefile
index e693f7f..7310c4e 100644
--- a/Makefile
+++ b/Makefile
@@ -372,7 +372,7 @@
 		$(OBJCOPY) ${OBJCFLAGS} -O ihex $< $@
 
 $(obj)u-boot.srec:	$(obj)u-boot
-		$(OBJCOPY) -O srec $< $@
+		$(OBJCOPY) ${OBJCFLAGS} -O srec $< $@
 
 $(obj)u-boot.bin:	$(obj)u-boot
 		$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
diff --git a/README b/README
index 3c233db..8f0b38c 100644
--- a/README
+++ b/README
@@ -818,6 +818,22 @@
 		as a convenience, when switching between booting from
 		RAM and NFS.
 
+- Bootcount:
+		CONFIG_BOOTCOUNT_LIMIT
+		Implements a mechanism for detecting a repeating reboot
+		cycle, see:
+		http://www.denx.de/wiki/view/DULG/UBootBootCountLimit
+
+		CONFIG_BOOTCOUNT_ENV
+		If no softreset save registers are found on the hardware
+		"bootcount" is stored in the environment. To prevent a
+		saveenv on all reboots, the environment variable
+		"upgrade_available" is used. If "upgrade_available" is
+		0, "bootcount" is always 0, if "upgrade_available" is
+		1 "bootcount" is incremented in the environment.
+		So the Userspace Applikation must set the "upgrade_available"
+		and "bootcount" variable to 0, if a boot was successfully.
+
 - Pre-Boot Commands:
 		CONFIG_PREBOOT
 
@@ -4394,6 +4410,9 @@
 
 		NOTE : currently only supported on AM335x platforms.
 
+- CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC:
+		Enables the RTC32K OSC on AM33xx based plattforms
+
 Freescale QE/FMAN Firmware Support:
 -----------------------------------
 
diff --git a/arch/arm/config.mk b/arch/arm/config.mk
index bdabcf4..fd3e5fb 100644
--- a/arch/arm/config.mk
+++ b/arch/arm/config.mk
@@ -103,3 +103,6 @@
 # such usage by requiring word relocations.
 PLATFORM_CPPFLAGS += $(call cc-option, -mword-relocations)
 endif
+
+# limit ourselves to the sections we want in the .bin.
+OBJCFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rel.dyn
diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile
index fd0da53..b2d30b1 100644
--- a/arch/arm/cpu/Makefile
+++ b/arch/arm/cpu/Makefile
@@ -1,2 +1,3 @@
+obj-$(CONFIG_AT91FAMILY) += at91-common/
 obj-$(CONFIG_TEGRA) += $(SOC)-common/
 obj-$(CONFIG_TEGRA) += tegra-common/
diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c
index 5dd9048..46ed055 100644
--- a/arch/arm/cpu/arm926ejs/at91/led.c
+++ b/arch/arm/cpu/arm926ejs/at91/led.c
@@ -7,43 +7,41 @@
  */
 
 #include <common.h>
-#include <asm/io.h>
-#include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_pio.h>
+#include <asm/gpio.h>
 #include <asm/arch/gpio.h>
 
 #ifdef CONFIG_RED_LED
 void red_led_on(void)
 {
-	at91_set_gpio_value(CONFIG_RED_LED, 1);
+	gpio_set_value(CONFIG_RED_LED, 1);
 }
 
 void red_led_off(void)
 {
-	at91_set_gpio_value(CONFIG_RED_LED, 0);
+	gpio_set_value(CONFIG_RED_LED, 0);
 }
 #endif
 
 #ifdef CONFIG_GREEN_LED
 void green_led_on(void)
 {
-	at91_set_gpio_value(CONFIG_GREEN_LED, 0);
+	gpio_set_value(CONFIG_GREEN_LED, 0);
 }
 
 void green_led_off(void)
 {
-	at91_set_gpio_value(CONFIG_GREEN_LED, 1);
+	gpio_set_value(CONFIG_GREEN_LED, 1);
 }
 #endif
 
 #ifdef CONFIG_YELLOW_LED
 void yellow_led_on(void)
 {
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 0);
+	gpio_set_value(CONFIG_YELLOW_LED, 0);
 }
 
 void yellow_led_off(void)
 {
-	at91_set_gpio_value(CONFIG_YELLOW_LED, 1);
+	gpio_set_value(CONFIG_YELLOW_LED, 1);
 }
 #endif
diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
index 40bcc31..80fb9bd 100644
--- a/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds
@@ -51,11 +51,13 @@
 
 	_end = .;
 
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
index 4927736..76b499d 100644
--- a/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
+++ b/arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds
@@ -51,11 +51,13 @@
 
 	_end = .;
 
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index d3347b3..0467d00 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@
 obj-y	+= cpu.o
 obj-y	+= syslib.o
 
-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY),)
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y	+= lowlevel_init.o
 endif
diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c
index 453effa..803aa9c 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -149,6 +149,7 @@
 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 }
 
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 static void rtc32k_enable(void)
 {
 	struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
@@ -164,6 +165,7 @@
 	/* Enable the RTC 32K OSC by setting bits 3 and 6. */
 	writel((1 << 3) | (1 << 6), &rtc->osc);
 }
+#endif
 
 static void uart_soft_reset(void)
 {
@@ -232,8 +234,10 @@
 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
 	prcm_init();
 	set_mux_conf_regs();
+#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
 	/* Enable RTC32K clock */
 	rtc32k_enable();
+#endif
 	sdram_init();
 #endif
 }
diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c
index fa697c7..5b0454c 100644
--- a/arch/arm/cpu/armv7/am33xx/ddr.c
+++ b/arch/arm/cpu/armv7/am33xx/ddr.c
@@ -89,15 +89,12 @@
 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 {
 	writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
-	writel(cmd->cmd0dldiff, &ddr_cmd_reg[nr]->cm0dldiff);
 	writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 
 	writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
-	writel(cmd->cmd1dldiff, &ddr_cmd_reg[nr]->cm1dldiff);
 	writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 
 	writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
-	writel(cmd->cmd2dldiff, &ddr_cmd_reg[nr]->cm2dldiff);
 	writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 }
 
@@ -121,10 +118,6 @@
 			&(ddr_data_reg[nr]+i)->dt0fwsratio0);
 		writel(data->datawrsratio0,
 			&(ddr_data_reg[nr]+i)->dt0wrsratio0);
-		writel(data->datauserank0delay,
-			&(ddr_data_reg[nr]+i)->dt0rdelays0);
-		writel(data->datadldiff0,
-			&(ddr_data_reg[nr]+i)->dt0dldiff0);
 	}
 }
 
diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
index 51f0a6d..78ecfc8 100644
--- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c
+++ b/arch/arm/cpu/armv7/at91/sama5d3_devices.c
@@ -15,7 +15,7 @@
 
 unsigned int has_emac()
 {
-	return cpu_is_sama5d31() || cpu_is_sama5d35();
+	return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36();
 }
 
 unsigned int has_gmac()
@@ -42,6 +42,8 @@
 			return "SAMA5D34";
 		case ARCH_EXID_SAMA5D35:
 			return "SAMA5D35";
+		case ARCH_EXID_SAMA5D36:
+			return "SAMA5D36";
 		default:
 			return "Unknown CPU type";
 		}
@@ -82,7 +84,7 @@
 	at91_set_a_periph(AT91_PIO_PORTB, 30, 0);	/* DRXD */
 
 	/* Enable clock */
-	at91_periph_clk_enable(ATMEL_ID_SYS);
+	at91_periph_clk_enable(ATMEL_ID_DBGU);
 }
 
 #if defined(CONFIG_ATMEL_SPI)
diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c
index 3808aed..e3ebfe0 100644
--- a/arch/arm/cpu/armv7/at91/timer.c
+++ b/arch/arm/cpu/armv7/at91/timer.c
@@ -60,7 +60,7 @@
 	at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT;
 
 	/* Enable PITC Clock */
-	at91_periph_clk_enable(ATMEL_ID_SYS);
+	at91_periph_clk_enable(ATMEL_ID_PIT);
 
 	/* Enable PITC */
 	writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index 36fedd6..84a5047 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -1410,7 +1410,8 @@
 	else {
 		if (proid_is_exynos4412())
 			exynos4x12_set_mmc_clk(dev_index, div);
-		exynos4_set_mmc_clk(dev_index, div);
+		else
+			exynos4_set_mmc_clk(dev_index, div);
 	}
 }
 
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c
index 8002bce..74cc700 100644
--- a/arch/arm/cpu/armv7/exynos/pinmux.c
+++ b/arch/arm/cpu/armv7/exynos/pinmux.c
@@ -462,7 +462,7 @@
 	case PERIPH_ID_SDMMC1:
 	case PERIPH_ID_SDMMC3:
 	case PERIPH_ID_SDMMC4:
-		printf("SDMMC device %d not implemented\n", peripheral);
+		debug("SDMMC device %d not implemented\n", peripheral);
 		return -1;
 	default:
 		debug("%s: invalid peripheral %d", __func__, peripheral);
diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c
index 3651c00..ade45fd 100644
--- a/arch/arm/cpu/armv7/exynos/spl_boot.c
+++ b/arch/arm/cpu/armv7/exynos/spl_boot.c
@@ -10,8 +10,11 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/dmc.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/pinmux.h>
 #include <asm/arch/power.h>
 #include <asm/arch/spl.h>
+#include <asm/arch/spi.h>
 
 #include "common_setup.h"
 #include "clock_init.h"
@@ -59,6 +62,121 @@
 }
 #endif
 
+#ifdef CONFIG_SPI_BOOTING
+static void spi_rx_tx(struct exynos_spi *regs, int todo,
+			void *dinp, void const *doutp, int i)
+{
+	uint *rxp = (uint *)(dinp + (i * (32 * 1024)));
+	int rx_lvl, tx_lvl;
+	uint out_bytes, in_bytes;
+
+	out_bytes = todo;
+	in_bytes = todo;
+	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	writel(((todo * 8) / 32) | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+
+	while (in_bytes) {
+		uint32_t spi_sts;
+		int temp;
+
+		spi_sts = readl(&regs->spi_sts);
+		rx_lvl = ((spi_sts >> 15) & 0x7f);
+		tx_lvl = ((spi_sts >> 6) & 0x7f);
+		while (tx_lvl < 32 && out_bytes) {
+			temp = 0xffffffff;
+			writel(temp, &regs->tx_data);
+			out_bytes -= 4;
+			tx_lvl += 4;
+		}
+		while (rx_lvl >= 4 && in_bytes) {
+			temp = readl(&regs->rx_data);
+			if (rxp)
+				*rxp++ = temp;
+			in_bytes -= 4;
+			rx_lvl -= 4;
+		}
+	}
+}
+
+/*
+ * Copy uboot from spi flash to RAM
+ *
+ * @parma uboot_size	size of u-boot to copy
+ * @param uboot_addr	address in u-boot to copy
+ */
+static void exynos_spi_copy(unsigned int uboot_size, unsigned int uboot_addr)
+{
+	int upto, todo;
+	int i, timeout = 100;
+	struct exynos_spi *regs = (struct exynos_spi *)CONFIG_ENV_SPI_BASE;
+
+	set_spi_clk(PERIPH_ID_SPI1, 50000000); /* set spi clock to 50Mhz */
+	/* set the spi1 GPIO */
+	exynos_pinmux_config(PERIPH_ID_SPI1, PINMUX_FLAG_NONE);
+
+	/* set pktcnt and enable it */
+	writel(4 | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
+	/* set FB_CLK_SEL */
+	writel(SPI_FB_DELAY_180, &regs->fb_clk);
+	/* set CH_WIDTH and BUS_WIDTH as word */
+	setbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+					SPI_MODE_BUS_WIDTH_WORD);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */
+
+	/* clear rx and tx channel if set priveously */
+	clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON);
+
+	setbits_le32(&regs->swap_cfg, SPI_RX_SWAP_EN |
+			SPI_RX_BYTE_SWAP |
+			SPI_RX_HWORD_SWAP);
+
+	/* do a soft reset */
+	setbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+
+	/* now set rx and tx channel ON */
+	setbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON | SPI_CH_HS_EN);
+	clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */
+
+	/* Send read instruction (0x3h) followed by a 24 bit addr */
+	writel((SF_READ_DATA_CMD << 24) | SPI_FLASH_UBOOT_POS, &regs->tx_data);
+
+	/* waiting for TX done */
+	while (!(readl(&regs->spi_sts) & SPI_ST_TX_DONE)) {
+		if (!timeout) {
+			debug("SPI TIMEOUT\n");
+			break;
+		}
+		timeout--;
+	}
+
+	for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) {
+		todo = min(uboot_size - upto, (1 << 15));
+		spi_rx_tx(regs, todo, (void *)(uboot_addr),
+			  (void *)(SPI_FLASH_UBOOT_POS), i);
+	}
+
+	setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT);/* make the CS high */
+
+	/*
+	 * Let put controller mode to BYTE as
+	 * SPI driver does not support WORD mode yet
+	 */
+	clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD |
+					SPI_MODE_BUS_WIDTH_WORD);
+	writel(0, &regs->swap_cfg);
+
+	/*
+	 * Flush spi tx, rx fifos and reset the SPI controller
+	 * and clear rx/tx channel
+	 */
+	clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
+	clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
+}
+#endif
+
 /*
 * Copy U-boot from mmc to RAM:
 * COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains
@@ -70,6 +188,9 @@
 
 	u32 (*copy_bl2)(u32 offset, u32 nblock, u32 dst) = NULL;
 	u32 offset = 0, size = 0;
+#ifdef CONFIG_SPI_BOOTING
+	struct spl_machine_param *param = spl_get_machine_params();
+#endif
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 	u32 (*copy_bl2_from_emmc)(u32 nblock, u32 dst);
 	void (*end_bootop_from_emmc)(void);
@@ -91,9 +212,8 @@
 	switch (bootmode) {
 #ifdef CONFIG_SPI_BOOTING
 	case BOOT_MODE_SERIAL:
-		offset = SPI_FLASH_UBOOT_POS;
-		size = CONFIG_BL2_SIZE;
-		copy_bl2 = get_irom_func(SPI_INDEX);
+		/* Customised function to copy u-boot from SF */
+		exynos_spi_copy(param->uboot_size, CONFIG_SYS_TEXT_BASE);
 		break;
 #endif
 	case BOOT_MODE_MMC:
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index 24b4c18..6367e09 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -14,6 +14,7 @@
 .arch_extension sec
 .arch_extension virt
 
+	.align	5
 /* the vector table for secure state and HYP mode */
 _monitor_vectors:
 	.word 0	/* reset */
@@ -32,7 +33,6 @@
  * to non-secure state.
  * We use only r0 and r1 here, due to constraints in the caller.
  */
-	.align	5
 _secure_monitor:
 	mrc	p15, 0, r1, c1, c1, 0		@ read SCR
 	bic	r1, r1, #0x4e			@ clear IRQ, FIQ, EA, nET bits
diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile
index 4d3a165..59f5352 100644
--- a/arch/arm/cpu/armv7/omap-common/Makefile
+++ b/arch/arm/cpu/armv7/omap-common/Makefile
@@ -17,6 +17,11 @@
 obj-y	+= abb.o
 endif
 
+ifneq ($(CONFIG_OMAP54XX),)
+obj-y	+= pipe3-phy.o
+obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
+endif
+
 ifeq ($(CONFIG_OMAP34XX),)
 obj-y	+= boot-common.o
 obj-y	+= lowlevel_init.o
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index b0e1caa..5a3f285 100644
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -206,7 +206,7 @@
 	}
 }
 
-static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
@@ -217,47 +217,86 @@
 
 	/*
 	 * Set invert_clkout (if activated)--DDR_PHYCTRL_1
-	 * Invert clock adds an additional half cycle delay on the command
-	 * interface.  The additional half cycle, is usually meant to enable
-	 * leveling in the situation that DQS is later than CK on the board.It
-	 * also helps provide some additional margin for leveling.
+	 * Invert clock adds an additional half cycle delay on the
+	 * command interface.  The additional half cycle, is usually
+	 * meant to enable leveling in the situation that DQS is later
+	 * than CK on the board.It also helps provide some additional
+	 * margin for leveling.
 	 */
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	writel(regs->emif_ddr_phy_ctlr_1,
+	       &emif->emif_ddr_phy_ctrl_1);
+
+	writel(regs->emif_ddr_phy_ctlr_1,
+	       &emif->emif_ddr_phy_ctrl_1_shdw);
 	__udelay(130);
 
 	writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
-		& EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+	       & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 
 	/* Launch Full leveling */
 	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 
 	/* Wait till full leveling is complete */
 	readl(&emif->emif_rd_wr_lvl_ctl);
-	__udelay(130);
+	      __udelay(130);
 
 	/* Read data eye leveling no of samples */
 	config_data_eye_leveling_samples(base);
 
+	/*
+	 * Launch 8 incremental WR_LVL- to compensate for
+	 * PHY limitation.
+	 */
+	writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
+	       &emif->emif_rd_wr_lvl_ctl);
+
-	/* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
-	writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
 	__udelay(130);
 
 	/* Launch Incremental leveling */
 	writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
-	__udelay(130);
+	       __udelay(130);
 }
 
-static void ddr3_sw_leveling(u32 base, const struct emif_regs *regs)
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 {
 	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 
+	u32 fifo_reg;
+
+	fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
+	writel(fifo_reg | 0x00000100,
+	       &emif->emif_ddr_fifo_misaligned_clear_1);
+
+	fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
+	writel(fifo_reg | 0x00000100,
+	       &emif->emif_ddr_fifo_misaligned_clear_2);
+
+	/* Launch Full leveling */
+	writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+	/* Wait till full leveling is complete */
+	readl(&emif->emif_rd_wr_lvl_ctl);
+	      __udelay(130);
+
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
-	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+	/* Read data eye leveling no of samples */
 	config_data_eye_leveling_samples(base);
 
-	writel(regs->emif_rd_wr_lvl_ctl, &emif->emif_rd_wr_lvl_ctl);
-	writel(regs->sdram_config, &emif->emif_sdram_config);
+	/*
+	 * Disable leveling. This is because if leveling is kept
+	 * enabled, then PHY triggers a false leveling during
+	 * EMIF-idle scenario which results in wrong delay
+	 * values getting updated. After this the EMIF becomes
+	 * unaccessible. So disable it after the first time
+	 */
+	writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
+}
+
+static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+	if (is_omap54xx())
+		omap5_ddr3_leveling(base, regs);
+	else
+		dra7_ddr3_leveling(base, regs);
 }
 
 static void ddr3_init(u32 base, const struct emif_regs *regs)
@@ -270,9 +309,6 @@
 	 * defined, contents of mode Registers must be fully initialized.
 	 * H/W takes care of this initialization
 	 */
-	writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
-	writel(regs->sdram_config_init, &emif->emif_sdram_config);
-
 	writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 
 	/* Update timing registers */
@@ -283,15 +319,24 @@
 	writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 	writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 
-	do_ext_phy_settings(base, regs);
+	/*
+	 * The same sequence should work on OMAP5432 as well. But strange that
+	 * it is not working
+	 */
+	if (omap_revision() == DRA752_ES1_0) {
+		do_ext_phy_settings(base, regs);
+		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+		writel(regs->sdram_config_init, &emif->emif_sdram_config);
+	} else {
+		writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+		writel(regs->sdram_config_init, &emif->emif_sdram_config);
+		do_ext_phy_settings(base, regs);
+	}
 
 	/* enable leveling */
 	writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 
-	if (omap_revision() == DRA752_ES1_0)
-		ddr3_sw_leveling(base, regs);
-	else
-		ddr3_leveling(base, regs);
+	ddr3_leveling(base, regs);
 }
 
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
@@ -1079,10 +1124,7 @@
 	if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
 		set_lpmode_selfrefresh(base);
 		emif_reset_phy(base);
-		if (omap_revision() == DRA752_ES1_0)
-			ddr3_sw_leveling(base, regs);
-		else
-			ddr3_leveling(base, regs);
+		ddr3_leveling(base, regs);
 	}
 
 	/* Write to the shadow registers */
@@ -1242,6 +1284,42 @@
 		}
 	}
 
+}
+
+static void do_bug0039_workaround(u32 base)
+{
+	u32 val, i, clkctrl;
+	struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
+	const struct read_write_regs *bug_00339_regs;
+	u32 iterations;
+	u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
+	u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
+
+	if (is_dra7xx())
+		phy_status_base++;
+
+	bug_00339_regs = get_bug_regs(&iterations);
+
+	/* Put EMIF in to idle */
+	clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
+	__raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
+
+	/* Copy the phy status registers in to phy ctrl shadow registers */
+	for (i = 0; i < iterations; i++) {
+		val = __raw_readl(phy_status_base +
+				  bug_00339_regs[i].read_reg - 1);
+
+		__raw_writel(val, phy_ctrl_base +
+			     ((bug_00339_regs[i].write_reg - 1) << 1));
+
+		__raw_writel(val, phy_ctrl_base +
+			     (bug_00339_regs[i].write_reg << 1) - 1);
+	}
+
+	/* Disable leveling */
+	writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
+
+	__raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
 }
 
 /*
@@ -1319,5 +1397,11 @@
 			debug("get_ram_size() successful");
 	}
 
+	if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
+	    (!in_sdram && !warm_reset())) {
+		do_bug0039_workaround(EMIF1_BASE);
+		do_bug0039_workaround(EMIF2_BASE);
+	}
+
 	debug("<<sdram_init()\n");
 }
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.c b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
new file mode 100644
index 0000000..b71d769
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.c
@@ -0,0 +1,231 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <sata.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include "pipe3-phy.h"
+
+/* PLLCTRL Registers */
+#define PLL_STATUS              0x00000004
+#define PLL_GO                  0x00000008
+#define PLL_CONFIGURATION1      0x0000000C
+#define PLL_CONFIGURATION2      0x00000010
+#define PLL_CONFIGURATION3      0x00000014
+#define PLL_CONFIGURATION4      0x00000020
+
+#define PLL_REGM_MASK           0x001FFE00
+#define PLL_REGM_SHIFT          9
+#define PLL_REGM_F_MASK         0x0003FFFF
+#define PLL_REGM_F_SHIFT        0
+#define PLL_REGN_MASK           0x000001FE
+#define PLL_REGN_SHIFT          1
+#define PLL_SELFREQDCO_MASK     0x0000000E
+#define PLL_SELFREQDCO_SHIFT    1
+#define PLL_SD_MASK             0x0003FC00
+#define PLL_SD_SHIFT            10
+#define SET_PLL_GO              0x1
+#define PLL_TICOPWDN            BIT(16)
+#define PLL_LDOPWDN             BIT(15)
+#define PLL_LOCK                0x2
+#define PLL_IDLE                0x1
+
+/* PHY POWER CONTROL Register */
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK         0x003FC000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT        0xE
+
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK        0xFFC00000
+#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT       0x16
+
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON       0x3
+#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF      0x0
+
+
+#define PLL_IDLE_TIME   100     /* in milliseconds */
+#define PLL_LOCK_TIME   100     /* in milliseconds */
+
+static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+	return __raw_readl(addr + offset);
+}
+
+static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset,
+		u32 data)
+{
+	__raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3
+									*pipe3)
+{
+	u32 rate;
+	struct pipe3_dpll_map *dpll_map = pipe3->dpll_map;
+
+	rate = get_sys_clk_freq();
+
+	for (; dpll_map->rate; dpll_map++) {
+		if (rate == dpll_map->rate)
+			return &dpll_map->params;
+	}
+
+	printf("%s: No DPLL configuration for %u Hz SYS CLK\n",
+	       __func__, rate);
+	return NULL;
+}
+
+
+static int omap_pipe3_wait_lock(struct omap_pipe3 *phy)
+{
+	u32 val;
+	int timeout = PLL_LOCK_TIME;
+
+	do {
+		mdelay(1);
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+		if (val & PLL_LOCK)
+			break;
+	} while (--timeout);
+
+	if (!(val & PLL_LOCK)) {
+		printf("%s: DPLL failed to lock\n", __func__);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static int omap_pipe3_dpll_program(struct omap_pipe3 *phy)
+{
+	u32                     val;
+	struct pipe3_dpll_params *dpll_params;
+
+	dpll_params = omap_pipe3_get_dpll_params(phy);
+	if (!dpll_params) {
+		printf("%s: Invalid DPLL parameters\n", __func__);
+		return -EINVAL;
+	}
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+	val &= ~PLL_REGN_MASK;
+	val |= dpll_params->n << PLL_REGN_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+	val &= ~PLL_SELFREQDCO_MASK;
+	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1);
+	val &= ~PLL_REGM_MASK;
+	val |= dpll_params->m << PLL_REGM_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4);
+	val &= ~PLL_REGM_F_MASK;
+	val |= dpll_params->mf << PLL_REGM_F_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val);
+
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3);
+	val &= ~PLL_SD_MASK;
+	val |= dpll_params->sd << PLL_SD_SHIFT;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val);
+
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO);
+
+	return omap_pipe3_wait_lock(phy);
+}
+
+static void omap_control_phy_power(struct omap_pipe3 *phy, int on)
+{
+	u32 val, rate;
+
+	val = readl(phy->power_reg);
+
+	rate = get_sys_clk_freq();
+	rate = rate/1000000;
+
+	if (on) {
+		val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
+				OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
+		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+		val |= rate <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
+	} else {
+		val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
+		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
+			OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
+	}
+
+	writel(val, phy->power_reg);
+}
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy)
+{
+	int ret;
+	u32 val;
+
+	/* Program the DPLL only if not locked */
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+	if (!(val & PLL_LOCK)) {
+		ret = omap_pipe3_dpll_program(phy);
+		if (ret)
+			return ret;
+	} else {
+		/* else just bring it out of IDLE mode */
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+		if (val & PLL_IDLE) {
+			val &= ~PLL_IDLE;
+			omap_pipe3_writel(phy->pll_ctrl_base,
+					  PLL_CONFIGURATION2, val);
+			ret = omap_pipe3_wait_lock(phy);
+			if (ret)
+				return ret;
+		}
+	}
+
+	/* Power up the PHY */
+	omap_control_phy_power(phy, 1);
+
+	return 0;
+}
+
+int phy_pipe3_power_off(struct omap_pipe3 *phy)
+{
+	u32 val;
+	int timeout = PLL_IDLE_TIME;
+
+	/* Power down the PHY */
+	omap_control_phy_power(phy, 0);
+
+	/* Put DPLL in IDLE mode */
+	val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2);
+	val |= PLL_IDLE;
+	omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val);
+
+	/* wait for LDO and Oscillator to power down */
+	do {
+		mdelay(1);
+		val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS);
+		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))
+			break;
+	} while (--timeout);
+
+	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {
+		printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n",
+		       __func__, val);
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
diff --git a/arch/arm/cpu/armv7/omap-common/pipe3-phy.h b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
new file mode 100644
index 0000000..441f49a
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/pipe3-phy.h
@@ -0,0 +1,36 @@
+/*
+ * TI PIPE3 PHY
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __OMAP_PIPE3_PHY_H
+#define __OMAP_PIPE3_PHY_H
+
+struct pipe3_dpll_params {
+	u16     m;
+	u8      n;
+	u8      freq:3;
+	u8      sd;
+	u32     mf;
+};
+
+struct pipe3_dpll_map {
+	unsigned long rate;
+	struct pipe3_dpll_params params;
+};
+
+struct omap_pipe3 {
+	void __iomem            *pll_ctrl_base;
+	void __iomem		*power_reg;
+	struct pipe3_dpll_map   *dpll_map;
+};
+
+
+int phy_pipe3_power_on(struct omap_pipe3 *phy);
+int phy_pipe3_power_off(struct omap_pipe3 *pipe3);
+
+#endif /* __OMAP_PIPE3_PHY_H */
diff --git a/arch/arm/cpu/armv7/omap-common/sata.c b/arch/arm/cpu/armv7/omap-common/sata.c
new file mode 100644
index 0000000..f5468c4
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap-common/sata.c
@@ -0,0 +1,75 @@
+/*
+ * TI SATA platform driver
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <ahci.h>
+#include <scsi.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sata.h>
+#include <asm/io.h>
+#include "pipe3-phy.h"
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+	{12000000, {1000, 7, 4, 6, 0} },        /* 12 MHz */
+	{16800000, {714, 7, 4, 6, 0} },         /* 16.8 MHz */
+	{19200000, {625, 7, 4, 6, 0} },         /* 19.2 MHz */
+	{20000000, {600, 7, 4, 6, 0} },         /* 20 MHz */
+	{26000000, {461, 7, 4, 6, 0} },         /* 26 MHz */
+	{38400000, {312, 7, 4, 6, 0} },         /* 38.4 MHz */
+	{ },                                    /* Terminator */
+};
+
+struct omap_pipe3 sata_phy = {
+	.pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE,
+	/* .power_reg is updated at runtime */
+	.dpll_map = dpll_map_sata,
+};
+
+int omap_sata_init(void)
+{
+	int ret;
+	u32 val;
+
+	u32 const clk_domains_sata[] = {
+		0
+	};
+
+	u32 const clk_modules_hw_auto_sata[] = {
+		(*prcm)->cm_l3init_ocp2scp3_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_sata[] = {
+		(*prcm)->cm_l3init_sata_clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_sata,
+			 clk_modules_hw_auto_sata,
+			 clk_modules_explicit_en_sata,
+			 0);
+
+	/* Enable optional functional clock for SATA */
+	setbits_le32((*prcm)->cm_l3init_sata_clkctrl,
+		     SATA_CLKCTRL_OPTFCLKEN_MASK);
+
+	sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata;
+
+	/* Power up the PHY */
+	phy_pipe3_power_on(&sata_phy);
+
+	/* Enable SATA module, No Idle, No Standby */
+	val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO;
+	writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG);
+
+	ret = ahci_init(DWC_AHSATA_BASE);
+	scsi_scan(1);
+
+	return ret;
+}
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 14fc7e8..1bc27bd 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -730,8 +730,6 @@
 		sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
 		sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
 	}
-	sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
-	sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);
 
 	sdelay(1000);
 }
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c
index 6a225c8..1b2f439 100644
--- a/arch/arm/cpu/armv7/omap4/hw_data.c
+++ b/arch/arm/cpu/armv7/omap4/hw_data.c
@@ -288,17 +288,21 @@
 	.mm.pmic = &twl6030,
 };
 
+/*
+ * Take closest integer part of the mV value corresponding to a TWL6032 SMPS
+ * voltage selection code. Aligned with OMAP4470 ES1.0 OCA V.0.7.
+ */
 struct vcores_data omap4470_volts = {
-	.mpu.value = 1200,
+	.mpu.value = 1202,
 	.mpu.addr = SMPS_REG_ADDR_SMPS1,
 	.mpu.pmic = &twl6030,
 
 	.core.value = 1126,
-	.core.addr = SMPS_REG_ADDR_SMPS1,
+	.core.addr = SMPS_REG_ADDR_SMPS2,
 	.core.pmic = &twl6030,
 
-	.mm.value = 1137,
-	.mm.addr = SMPS_REG_ADDR_SMPS1,
+	.mm.value = 1139,
+	.mm.addr = SMPS_REG_ADDR_SMPS5,
 	.mm.pmic = &twl6030,
 };
 
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
index e4c8316..6903696 100644
--- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c
+++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c
@@ -32,7 +32,7 @@
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 
-static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
+const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
 	.sdram_config_init		= 0x80000eb9,
 	.sdram_config			= 0x80001ab9,
 	.ref_ctrl			= 0x0000030c,
@@ -46,7 +46,7 @@
 	.emif_ddr_phy_ctlr_1		= 0x049ff808
 };
 
-static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
+const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
 	.sdram_config_init		= 0x80000eb1,
 	.sdram_config			= 0x80001ab1,
 	.ref_ctrl			= 0x000005cd,
@@ -321,3 +321,8 @@
 {
 	*regs = &mr_regs;
 }
+
+__weak const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index a1b249e..82910e8 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -600,6 +600,7 @@
 	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE,
 	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE,
 	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 };
 
 const struct ctrl_ioregs ioregs_omap5432_es2 = {
@@ -610,16 +611,18 @@
 	.ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2,
 	.ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2,
 	.ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES,
+	.ctrl_emif_sdram_config_ext_final = SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
 };
 
 const struct ctrl_ioregs ioregs_dra7xx_es1 = {
 	.ctrl_ddrch = 0x40404040,
 	.ctrl_lpddr2ch = 0x40404040,
 	.ctrl_ddr3ch = 0x80808080,
-	.ctrl_ddrio_0 = 0xbae8c631,
-	.ctrl_ddrio_1 = 0xb46318d8,
+	.ctrl_ddrio_0 = 0xA2084210,
+	.ctrl_ddrio_1 = 0x84210840,
 	.ctrl_ddrio_2 = 0x84210000,
-	.ctrl_emif_sdram_config_ext = 0xb2c00000,
+	.ctrl_emif_sdram_config_ext = 0x0001C1A7,
+	.ctrl_emif_sdram_config_ext_final = 0x000101A7,
 	.ctrl_ddr_ctrl_ext_0 = 0xA2000000,
 };
 
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c
index 1065891..5386ae0 100644
--- a/arch/arm/cpu/armv7/omap5/hwinit.c
+++ b/arch/arm/cpu/armv7/omap5/hwinit.c
@@ -168,12 +168,6 @@
 		io_settings_lpddr2();
 	else
 		io_settings_ddr3();
-
-	/* Efuse settings */
-	writel(EFUSE_1, (*ctrl)->control_efuse_1);
-	writel(EFUSE_2, (*ctrl)->control_efuse_2);
-	writel(EFUSE_3, (*ctrl)->control_efuse_3);
-	writel(EFUSE_4, (*ctrl)->control_efuse_4);
 }
 
 static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = {
@@ -297,13 +291,17 @@
 
 void config_data_eye_leveling_samples(u32 emif_base)
 {
+	const struct ctrl_ioregs *ioregs;
+
+	get_ioregs(&ioregs);
+
 	/*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/
 	if (emif_base == EMIF1_BASE)
-		writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-			(*ctrl)->control_emif1_sdram_config_ext);
+		writel(ioregs->ctrl_emif_sdram_config_ext_final,
+		       (*ctrl)->control_emif1_sdram_config_ext);
 	else if (emif_base == EMIF2_BASE)
-		writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES,
-			(*ctrl)->control_emif2_sdram_config_ext);
+		writel(ioregs->ctrl_emif_sdram_config_ext_final,
+		       (*ctrl)->control_emif2_sdram_config_ext);
 }
 
 void init_omap_revision(void)
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index 304ac1c..77c428b 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -203,8 +203,10 @@
 	.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
 	.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
 	.cm_l3init_p1500_clkctrl = 0x4a009378,
+	.cm_l3init_sata_clkctrl = 0x4a009388,
 	.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
+	.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
 
 	/* cm2.l4per */
 	.cm_l4per_clkstctrl = 0x4a009400,
@@ -296,6 +298,7 @@
 	.control_status				= 0x4A002134,
 	.control_std_fuse_opp_vdd_mpu_2		= 0x4A0021B4,
 	.control_phy_power_usb 			= 0x4A002370,
+	.control_phy_power_sata			= 0x4A002374,
 	.control_padconf_core_base		= 0x4A002800,
 	.control_paconf_global			= 0x4A002DA0,
 	.control_paconf_mode			= 0x4A002DA4,
@@ -373,6 +376,7 @@
 
 struct omap_sys_ctrl_regs const dra7xx_ctrl = {
 	.control_status				= 0x4A002134,
+	.control_phy_power_sata			= 0x4A002374,
 	.control_core_mac_id_0_lo		= 0x4A002514,
 	.control_core_mac_id_0_hi		= 0x4A002518,
 	.control_core_mac_id_1_lo		= 0x4A00251C,
@@ -698,6 +702,7 @@
 	.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
 	.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
 	.cm_l3init_p1500_clkctrl = 0x4a009678,
+	.cm_l3init_sata_clkctrl = 0x4a009688,
 	.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
 	.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
 	.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
@@ -891,9 +896,11 @@
 	.cm_l3init_hsusbhost_clkctrl		= 0x4a009340,
 	.cm_l3init_hsusbotg_clkctrl		= 0x4a009348,
 	.cm_l3init_hsusbtll_clkctrl		= 0x4a009350,
+	.cm_l3init_sata_clkctrl			= 0x4a009388,
 	.cm_gmac_clkstctrl			= 0x4a0093c0,
 	.cm_gmac_gmac_clkctrl			= 0x4a0093d0,
 	.cm_l3init_ocp2scp1_clkctrl		= 0x4a0093e0,
+	.cm_l3init_ocp2scp3_clkctrl		= 0x4a0093e8,
 
 	/* cm2.l4per */
 	.cm_l4per_clkstctrl			= 0x4a009700,
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index e65c116..2e18706 100644
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -148,13 +148,13 @@
 	.read_idle_ctrl                 = 0x00050000,
 	.zq_config                      = 0x0007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0E20400A,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
-	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x009E009E,
-	.emif_ddr_ext_phy_ctrl_3        = 0x009E009E,
-	.emif_ddr_ext_phy_ctrl_4        = 0x009E009E,
-	.emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400A,
+	.emif_ddr_phy_ctlr_1            = 0x0024400A,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -172,13 +172,13 @@
 	.read_idle_ctrl                 = 0x00050000,
 	.zq_config                      = 0x0007190B,
 	.temp_alert_config              = 0x00000000,
-	.emif_ddr_phy_ctlr_1_init       = 0x0020400A,
-	.emif_ddr_phy_ctlr_1            = 0x0E24400A,
-	.emif_ddr_ext_phy_ctrl_1        = 0x04040100,
-	.emif_ddr_ext_phy_ctrl_2        = 0x009D009D,
-	.emif_ddr_ext_phy_ctrl_3        = 0x009D009D,
-	.emif_ddr_ext_phy_ctrl_4        = 0x009D009D,
-	.emif_ddr_ext_phy_ctrl_5        = 0x009D009D,
+	.emif_ddr_phy_ctlr_1_init       = 0x0024400A,
+	.emif_ddr_phy_ctlr_1            = 0x0024400A,
+	.emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+	.emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
+	.emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 	.emif_rd_wr_lvl_rmp_win         = 0x00000000,
 	.emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 	.emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -306,7 +306,7 @@
 
 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 
-const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ext_phy_ctrl_const_base[] = {
 	0x01004010,
 	0x00001004,
 	0x04010040,
@@ -329,7 +329,7 @@
 	0x0
 };
 
-const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
 	0x01004010,
 	0x00001004,
 	0x04010040,
@@ -352,7 +352,7 @@
 	0x0
 };
 
-const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
+const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 	0x50D4350D,
 	0x00000D43,
 	0x04010040,
@@ -376,51 +376,61 @@
 };
 
 const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
-	0x009E009E,
-	0x002E002E,
-	0x002E002E,
-	0x002E002E,
-	0x002E002E,
-	0x002E002E,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x004D004D,
-	0x0,
-	0x600020,
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
+	0x00B000B0,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00400040,
+	0x00800080,
+	0x00800080,
+	0x00800080,
+	0x00800080,
+	0x00800080,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00800080,
+	0x00800080,
 	0x40010080,
-	0x8102040
+	0x08102040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
 };
 
 const u32
-dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
-	0x009D009D,
-	0x002D002D,
-	0x002D002D,
-	0x002D002D,
-	0x002D002D,
-	0x002D002D,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
-	0x00570057,
+dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
+	0x00BB00BB,
+	0x00440044,
+	0x00440044,
+	0x00440044,
+	0x00440044,
+	0x00440044,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x007F007F,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
+	0x00600060,
 	0x0,
-	0x600020,
+	0x00600020,
 	0x40010080,
-	0x8102040
+	0x08102040,
+	0x0,
+	0x0,
+	0x0,
+	0x0,
+	0x0
 };
 
 const struct lpddr2_mr_regs mr_regs = {
@@ -431,27 +441,38 @@
 	.mr16	= MR16_REF_FULL_ARRAY
 };
 
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs)
+static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+					     const u32 **regs,
+					     u32 *size)
 {
 	switch (omap_revision()) {
 	case OMAP5430_ES1_0:
 	case OMAP5430_ES2_0:
 		*regs = ext_phy_ctrl_const_base;
+		*size = ARRAY_SIZE(ext_phy_ctrl_const_base);
 		break;
 	case OMAP5432_ES1_0:
 		*regs = ddr3_ext_phy_ctrl_const_base_es1;
+		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
 		break;
 	case OMAP5432_ES2_0:
 		*regs = ddr3_ext_phy_ctrl_const_base_es2;
+		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 		break;
 	case DRA752_ES1_0:
-		if (emif_nr == 1)
+		if (emif_nr == 1) {
 			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
-		else
+			*size =
+			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
+		} else {
 			*regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
+			*size =
+			ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
+		}
 		break;
 	default:
 		*regs = ddr3_ext_phy_ctrl_const_base_es2;
+		*size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 
 	}
 }
@@ -468,6 +489,7 @@
 	u32 emif_nr;
 	const u32 *ext_phy_ctrl_const_regs;
 	u32 i = 0;
+	u32 size;
 
 	emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 
@@ -487,8 +509,10 @@
 	 * external phy 6-24 registers do not change with
 	 * ddr frequency
 	 */
-	emif_get_ext_phy_ctrl_const_regs(emif_nr, &ext_phy_ctrl_const_regs);
-	for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
+	emif_get_ext_phy_ctrl_const_regs(emif_nr,
+					 &ext_phy_ctrl_const_regs, &size);
+
+	for (i = 0; i < size; i++) {
 		writel(ext_phy_ctrl_const_regs[i],
 		       emif_ext_phy_ctrl_base++);
 		/* Update shadow registers */
@@ -545,6 +569,74 @@
 	.min_tck	= &min_tck,
 };
 
+/*
+ * List of status registers to be controlled back to control registers
+ * after initial leveling
+ * readreg, writereg
+ */
+const struct read_write_regs omap5_bug_00339_regs[] = {
+	{ 8,  5 },
+	{ 9,  6 },
+	{ 10, 7 },
+	{ 14, 8 },
+	{ 15, 9 },
+	{ 16, 10 },
+	{ 11, 2 },
+	{ 12, 3 },
+	{ 13, 4 },
+	{ 17, 11 },
+	{ 18, 12 },
+	{ 19, 13 },
+};
+
+const struct read_write_regs dra_bug_00339_regs[] = {
+	{ 7,  7 },
+	{ 8,  8 },
+	{ 9,  9 },
+	{ 10, 10 },
+	{ 11, 11 },
+	{ 12, 2 },
+	{ 13, 3 },
+	{ 14, 4 },
+	{ 15, 5 },
+	{ 16, 6 },
+	{ 17, 12 },
+	{ 18, 13 },
+	{ 19, 14 },
+	{ 20, 15 },
+	{ 21, 16 },
+	{ 22, 17 },
+	{ 23, 18 },
+	{ 24, 19 },
+	{ 25, 20 },
+	{ 26, 21}
+};
+
+const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+	const struct read_write_regs *bug_00339_regs_ptr = NULL;
+
+	switch (omap_revision()) {
+	case OMAP5430_ES1_0:
+	case OMAP5430_ES2_0:
+	case OMAP5432_ES1_0:
+	case OMAP5432_ES2_0:
+		bug_00339_regs_ptr = omap5_bug_00339_regs;
+		*iterations = sizeof(omap5_bug_00339_regs)/
+			     sizeof(omap5_bug_00339_regs[0]);
+		break;
+	case DRA752_ES1_0:
+		bug_00339_regs_ptr = dra_bug_00339_regs;
+		*iterations = sizeof(dra_bug_00339_regs)/
+			     sizeof(dra_bug_00339_regs[0]);
+		break;
+	default:
+		printf("\n Error: UnKnown SOC");
+	}
+
+	return bug_00339_regs_ptr;
+}
+
 void emif_get_device_timings_sdp(u32 emif_nr,
 		const struct lpddr2_device_timings **cs0_device_timings,
 		const struct lpddr2_device_timings **cs1_device_timings)
diff --git a/arch/arm/cpu/armv7/rmobile/Makefile b/arch/arm/cpu/armv7/rmobile/Makefile
index 5e296c4..2221999 100644
--- a/arch/arm/cpu/armv7/rmobile/Makefile
+++ b/arch/arm/cpu/armv7/rmobile/Makefile
@@ -5,14 +5,13 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y = lowlevel_init.o
-obj-y += cpu_info.o
+obj-y = cpu_info.o
 obj-y += emac.o
 
 obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o
 obj-$(CONFIG_GLOBAL_TIMER) += timer.o
-obj-$(CONFIG_R8A7740) += cpu_info-r8a7740.o
-obj-$(CONFIG_R8A7740) += pfc-r8a7740.o
-obj-$(CONFIG_SH73A0) += cpu_info-sh73a0.o
-obj-$(CONFIG_SH73A0) += pfc-sh73a0.o
+obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o
+obj-$(CONFIG_R8A7790) += lowlevel_init_ca15.o cpu_info-r8a7790.o pfc-r8a7790.o
+obj-$(CONFIG_R8A7791) += lowlevel_init_ca15.o cpu_info-r8a7791.o pfc-r8a7791.o
+obj-$(CONFIG_SH73A0) += lowlevel_init.o cpu_info-sh73a0.o pfc-sh73a0.o
 obj-$(CONFIG_TMU_TIMER) += ../../../../sh/lib/time.o
diff --git a/arch/arm/cpu/armv7/rmobile/config.mk b/arch/arm/cpu/armv7/rmobile/config.mk
deleted file mode 100644
index 3a36ab6..0000000
--- a/arch/arm/cpu/armv7/rmobile/config.mk
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-# Make ARMv5 to allow more compilers to work, even though its v7a.
-PLATFORM_CPPFLAGS += -march=armv5
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
new file mode 100644
index 0000000..7232e23
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7790.c
+ *     This file is r8a7790 processor support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#define PRR 0xFF000044
+
+u32 rmobile_get_cpu_type(void)
+{
+	return (readl(PRR) & 0x00007F00) >> 8;
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+	return (readl(PRR) & 0x000000F0) >> 4;
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
new file mode 100644
index 0000000..2de58ed
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/cpu_info-r8a7791.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include <common.h>
+#include <asm/io.h>
+
+#define PRR 0xFF000044
+
+u32 rmobile_get_cpu_type(void)
+{
+	u32 product;
+
+	product = readl(PRR);
+
+	return (u32)((product & 0x00007F00) >> 8);
+}
+
+u32 rmobile_get_cpu_rev_integer(void)
+{
+	u32 product;
+
+	product = readl(PRR);
+
+	return (u32)((product & 0x000000F0) >> 4);
+}
diff --git a/arch/arm/cpu/armv7/rmobile/cpu_info.c b/arch/arm/cpu/armv7/rmobile/cpu_info.c
index 07a33fb..83d5282 100644
--- a/arch/arm/cpu/armv7/rmobile/cpu_info.c
+++ b/arch/arm/cpu/armv7/rmobile/cpu_info.c
@@ -58,6 +58,16 @@
 		       rmobile_get_cpu_rev_fraction());
 		break;
 
+	case 0x45:
+		printf("CPU: Renesas Electronics R8A7790 rev %d\n",
+		       rmobile_get_cpu_rev_integer());
+		break;
+
+	case 0x47:
+		printf("CPU: Renesas Electronics R8A7791 rev %d\n",
+			rmobile_get_cpu_rev_integer());
+		break;
+
 	default:
 		printf("CPU: Renesas Electronics CPU rev %d.%d\n",
 		       rmobile_get_cpu_rev_integer(),
diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
new file mode 100644
index 0000000..e07cc80
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
@@ -0,0 +1,60 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S
+ *     This file is lager low level initialize.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+ENTRY(lowlevel_init)
+	mrc	p15, 0, r4, c0, c0, 5 /* mpidr */
+	orr	r4, r4, r4, lsr #6
+	and	r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
+
+	b do_lowlevel_init
+
+	.pool
+
+/*
+ * CPU ID #1-#3 come here
+ */
+	.align  4
+do_cpu_waiting:
+	ldr	r1, =0xe6180000 /* sysc */
+1:	ldr	r0, [r1, #0x20] /* sbar */
+	tst	r0, r0
+	beq	1b
+	bx	r0
+
+/*
+ * Only CPU ID #0 comes here
+ */
+	.align  4
+do_lowlevel_init:
+	/* surpress wfe if ca15 */
+	tst	r4, #4
+	mrceq p15, 0, r0, c1, c0, 1	/* actlr */
+	orreq r0, r0, #(1<<7)
+	mcreq p15, 0, r0, c1, c0, 1
+	/* and set l2 latency */
+	mrceq p15, 1, r0, c9, c0, 2	/* l2ctlr */
+	orreq r0, r0, #0x00000800
+	orreq r0, r0, #0x00000003
+	mcreq p15, 1, r0, c9, c0, 2
+
+	ldr	r3, =(CONFIG_SYS_INIT_SP_ADDR)
+	sub	sp, r3, #4
+	str	lr, [sp]
+
+	/* initialize system */
+	bl s_init
+
+	ldr	lr, [sp]
+	mov	pc, lr
+	nop
+ENDPROC(lowlevel_init)
+	.ltorg
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
new file mode 100644
index 0000000..1259062
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
@@ -0,0 +1,829 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
+ *     This file is r8a7790 processor support - PFC hardware block.
+ *
+ * Copy from linux-kernel:drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Magnus Damm
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include "pfc-r8a7790.h"
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
+	FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
+	FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
+	FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
+	FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
+	FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
+	FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+	FN_IP3_14_12, FN_IP3_17_15,
+
+	/* GPSR1 */
+	FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
+	FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
+	FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
+	FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
+	FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
+	FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
+	FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
+
+	/* GPSR2 */
+	FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
+	FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
+	FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
+	FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
+	FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
+	FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
+	FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
+
+	/* GPSR3 */
+	FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
+	FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
+	FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
+	FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
+	FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
+	FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
+	FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
+
+	/* GPSR4 */
+	FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
+	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
+	FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
+	FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
+	FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
+	FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
+	FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
+	FN_IP14_15_12, FN_IP14_18_16,
+
+	/* GPSR5 */
+	FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
+	FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
+	FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
+	FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
+	FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
+	FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
+	FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
+
+	/* IPSR0 - IPSR5 */
+	/* IPSR6 */
+	FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+	FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
+	FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+	FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
+	FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+	FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
+	FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+	FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
+	FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+	FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+	FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
+	FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
+	FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
+	FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
+	FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
+	FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+	FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
+	FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+	FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
+	FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+	FN_STP_IVCXO27_1_B, FN_HRX0_F,
+
+	/* IPSR7 */
+	FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+	FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
+	FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+	FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
+	FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
+	FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
+	FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
+	FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+	FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
+	FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+	FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
+	FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
+	FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
+	FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
+	FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
+	FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+	FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+	FN_MII_RXD2,
+
+	/* IPSR8 - IPSR16 */
+
+	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+	FN_SEL_SCIF1_4,
+	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
+	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
+	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+	FN_SEL_SCIFB1_4,
+	FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
+	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
+	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+	FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+	FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+	FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+	FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
+	FN_SEL_VI3_0, FN_SEL_VI3_1,
+	FN_SEL_VI2_0, FN_SEL_VI2_1,
+	FN_SEL_VI1_0, FN_SEL_VI1_1,
+	FN_SEL_VI0_0, FN_SEL_VI0_1,
+	FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
+	FN_SEL_LBS_0, FN_SEL_LBS_1,
+	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+	FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+	FN_SEL_SOF0_0, FN_SEL_SOF0_1,
+
+	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+	FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
+	FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+	FN_SEL_ADI_0, FN_SEL_ADI_1,
+	FN_SEL_SSP_0, FN_SEL_SSP_1,
+	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+	FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
+	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
+	FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
+	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
+	FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+	FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
+	FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
+	FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+
+	FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+	FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+	FN_SEL_IIC2_4,
+	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
+	FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+	FN_SEL_I2C2_4,
+	FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
+
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+	VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
+	DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
+	SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
+	INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+	DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
+	MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+	SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
+	ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
+	TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
+	SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
+	STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
+	SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
+	STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
+	SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
+	RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
+	TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
+	RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
+	STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
+	ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
+	STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
+
+	ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
+	SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
+	RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
+	ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
+	HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
+	SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
+	STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
+	ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
+	TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
+	SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
+	GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
+	STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
+	PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
+	PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
+	AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
+	ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
+	VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
+	MII_RXD2_MARK,
+
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	PINMUX_IPSR_DATA(IP6_2_0, DACK0),
+	PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
+	PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
+	PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
+	PINMUX_IPSR_DATA(IP6_8_6, DACK1),
+	PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
+	PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
+	PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
+	PINMUX_IPSR_DATA(IP6_13_11, DACK2),
+	PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
+	PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
+	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
+	PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
+	PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
+	PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
+	PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
+	PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
+	PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
+	PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
+	PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
+	PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
+	PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
+	PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
+	PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
+	PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
+
+	PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
+	PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
+	PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
+	PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
+	PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
+	PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
+	PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
+	PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
+	PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
+	PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
+	PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
+	PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
+	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_18_16, PWM0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_21_19, PWM1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
+	PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
+	PINMUX_IPSR_DATA(IP7_24_22, PWM2),
+	PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
+	PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
+	PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
+	PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
+	PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
+	PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
+	PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
+	PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
+	PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
+	PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
+	PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
+	PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
+	PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
+
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	/*IPSR0 - IPSR5*/
+	/*IPSR6*/
+	GPIO_FN(DACK0), GPIO_FN(IRQ0), GPIO_FN(INTC_IRQ0_N),
+	GPIO_FN(SSI_SCK6_B), GPIO_FN(VI1_VSYNC_N), GPIO_FN(VI1_VSYNC_N_B),
+	GPIO_FN(SSI_WS78_C), GPIO_FN(DREQ1_N), GPIO_FN(VI1_CLKENB),
+	GPIO_FN(VI1_CLKENB_B), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SSI_SCK78_B),
+	GPIO_FN(DACK1), GPIO_FN(IRQ1), GPIO_FN(INTC_IRQ1_N), GPIO_FN(SSI_WS6_B),
+	GPIO_FN(SSI_SDATA8_C), GPIO_FN(DREQ2_N), GPIO_FN(HSCK1_B),
+	GPIO_FN(HCTS0_N_B), GPIO_FN(MSIOF0_TXD_B), GPIO_FN(DACK2),
+	GPIO_FN(IRQ2), GPIO_FN(INTC_IRQ2_N), GPIO_FN(SSI_SDATA6_B),
+	GPIO_FN(HRTS0_N_B), GPIO_FN(MSIOF0_RXD_B), GPIO_FN(ETH_CRS_DV),
+	GPIO_FN(RMII_CRS_DV), GPIO_FN(STP_ISCLK_0_B), GPIO_FN(TS_SDEN0_D),
+	GPIO_FN(GLO_Q0_C), GPIO_FN(SCL2_E), GPIO_FN(SCL2_CIS_E),
+	GPIO_FN(ETH_RX_ER), GPIO_FN(RMII_RX_ER), GPIO_FN(STP_ISD_0_B),
+	GPIO_FN(TS_SPSYNC0_D), GPIO_FN(GLO_Q1_C), GPIO_FN(SDA2_E),
+	GPIO_FN(SDA2_CIS_E), GPIO_FN(ETH_RXD0), GPIO_FN(RMII_RXD0),
+	GPIO_FN(STP_ISEN_0_B), GPIO_FN(TS_SDAT0_D), GPIO_FN(GLO_I0_C),
+	GPIO_FN(SCIFB1_SCK_G), GPIO_FN(SCK1_E), GPIO_FN(ETH_RXD1),
+	GPIO_FN(RMII_RXD1), GPIO_FN(HRX0_E), GPIO_FN(STP_ISSYNC_0_B),
+	GPIO_FN(TS_SCK0_D), GPIO_FN(GLO_I1_C), GPIO_FN(SCIFB1_RXD_G),
+	GPIO_FN(RX1_E), GPIO_FN(ETH_LINK), GPIO_FN(RMII_LINK), GPIO_FN(HTX0_E),
+	GPIO_FN(STP_IVCXO27_0_B), GPIO_FN(SCIFB1_TXD_G), GPIO_FN(TX1_E),
+	GPIO_FN(ETH_REF_CLK), GPIO_FN(RMII_REF_CLK), GPIO_FN(HCTS0_N_E),
+	GPIO_FN(STP_IVCXO27_1_B), GPIO_FN(HRX0_F),
+
+	/*IPSR7*/
+	GPIO_FN(ETH_MDIO), GPIO_FN(RMII_MDIO), GPIO_FN(HRTS0_N_E),
+	GPIO_FN(SIM0_D_C), GPIO_FN(HCTS0_N_F), GPIO_FN(ETH_TXD1),
+	GPIO_FN(RMII_TXD1), GPIO_FN(HTX0_F), GPIO_FN(BPFCLK_G),
+	GPIO_FN(RDS_CLK_F), GPIO_FN(ETH_TX_EN), GPIO_FN(RMII_TX_EN),
+	GPIO_FN(SIM0_CLK_C), GPIO_FN(HRTS0_N_F), GPIO_FN(ETH_MAGIC),
+	GPIO_FN(RMII_MAGIC), GPIO_FN(SIM0_RST_C), GPIO_FN(ETH_TXD0),
+	GPIO_FN(RMII_TXD0), GPIO_FN(STP_ISCLK_1_B), GPIO_FN(TS_SDEN1_C),
+	GPIO_FN(GLO_SCLK_C), GPIO_FN(ETH_MDC), GPIO_FN(RMII_MDC),
+	GPIO_FN(STP_ISD_1_B), GPIO_FN(TS_SPSYNC1_C), GPIO_FN(GLO_SDATA_C),
+	GPIO_FN(PWM0), GPIO_FN(SCIFA2_SCK_C), GPIO_FN(STP_ISEN_1_B),
+	GPIO_FN(TS_SDAT1_C), GPIO_FN(GLO_SS_C), GPIO_FN(PWM1),
+	GPIO_FN(SCIFA2_TXD_C), GPIO_FN(STP_ISSYNC_1_B), GPIO_FN(TS_SCK1_C),
+	GPIO_FN(GLO_RFON_C), GPIO_FN(PCMOE_N), GPIO_FN(PWM2), GPIO_FN(PWMFSW0),
+	GPIO_FN(SCIFA2_RXD_C), GPIO_FN(PCMWE_N), GPIO_FN(IECLK_C),
+	GPIO_FN(DU1_DOTCLKIN), GPIO_FN(AUDIO_CLKC), GPIO_FN(AUDIO_CLKOUT_C),
+	GPIO_FN(VI0_CLK), GPIO_FN(ATACS00_N), GPIO_FN(AVB_RXD1),
+	GPIO_FN(MII_RXD1), GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(ATACS10_N),
+	GPIO_FN(AVB_RXD2), GPIO_FN(MII_RXD2),
+	/*IPSR8 - IPSR16*/
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		GP_0_31_FN, FN_IP3_17_15,
+		GP_0_30_FN, FN_IP3_14_12,
+		GP_0_29_FN, FN_IP3_11_8,
+		GP_0_28_FN, FN_IP3_7_4,
+		GP_0_27_FN, FN_IP3_3_0,
+		GP_0_26_FN, FN_IP2_28_26,
+		GP_0_25_FN, FN_IP2_25_22,
+		GP_0_24_FN, FN_IP2_21_18,
+		GP_0_23_FN, FN_IP2_17_15,
+		GP_0_22_FN, FN_IP2_14_12,
+		GP_0_21_FN, FN_IP2_11_9,
+		GP_0_20_FN, FN_IP2_8_6,
+		GP_0_19_FN, FN_IP2_5_3,
+		GP_0_18_FN, FN_IP2_2_0,
+		GP_0_17_FN, FN_IP1_29_28,
+		GP_0_16_FN, FN_IP1_27_26,
+		GP_0_15_FN, FN_IP1_25_22,
+		GP_0_14_FN, FN_IP1_21_18,
+		GP_0_13_FN, FN_IP1_17_15,
+		GP_0_12_FN, FN_IP1_14_12,
+		GP_0_11_FN, FN_IP1_11_8,
+		GP_0_10_FN, FN_IP1_7_4,
+		GP_0_9_FN, FN_IP1_3_0,
+		GP_0_8_FN, FN_IP0_30_27,
+		GP_0_7_FN, FN_IP0_26_23,
+		GP_0_6_FN, FN_IP0_22_20,
+		GP_0_5_FN, FN_IP0_19_16,
+		GP_0_4_FN, FN_IP0_15_12,
+		GP_0_3_FN, FN_IP0_11_9,
+		GP_0_2_FN, FN_IP0_8_6,
+		GP_0_1_FN, FN_IP0_5_3,
+		GP_0_0_FN, FN_IP0_2_0 }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_1_29_FN, FN_IP6_13_11,
+		GP_1_28_FN, FN_IP6_10_9,
+		GP_1_27_FN, FN_IP6_8_6,
+		GP_1_26_FN, FN_IP6_5_3,
+		GP_1_25_FN, FN_IP6_2_0,
+		GP_1_24_FN, FN_IP5_29_27,
+		GP_1_23_FN, FN_IP5_26_24,
+		GP_1_22_FN, FN_IP5_23_21,
+		GP_1_21_FN, FN_IP5_20_18,
+		GP_1_20_FN, FN_IP5_17_15,
+		GP_1_19_FN, FN_IP5_14_13,
+		GP_1_18_FN, FN_IP5_12_10,
+		GP_1_17_FN, FN_IP5_9_6,
+		GP_1_16_FN, FN_IP5_5_3,
+		GP_1_15_FN, FN_IP5_2_0,
+		GP_1_14_FN, FN_IP4_29_27,
+		GP_1_13_FN, FN_IP4_26_24,
+		GP_1_12_FN, FN_IP4_23_21,
+		GP_1_11_FN, FN_IP4_20_18,
+		GP_1_10_FN, FN_IP4_17_15,
+		GP_1_9_FN, FN_IP4_14_12,
+		GP_1_8_FN, FN_IP4_11_9,
+		GP_1_7_FN, FN_IP4_8_6,
+		GP_1_6_FN, FN_IP4_5_3,
+		GP_1_5_FN, FN_IP4_2_0,
+		GP_1_4_FN, FN_IP3_31_29,
+		GP_1_3_FN, FN_IP3_28_26,
+		GP_1_2_FN, FN_IP3_25_23,
+		GP_1_1_FN, FN_IP3_22_20,
+		GP_1_0_FN, FN_IP3_19_18, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_2_29_FN, FN_IP7_15_13,
+		GP_2_28_FN, FN_IP7_12_10,
+		GP_2_27_FN, FN_IP7_9_8,
+		GP_2_26_FN, FN_IP7_7_6,
+		GP_2_25_FN, FN_IP7_5_3,
+		GP_2_24_FN, FN_IP7_2_0,
+		GP_2_23_FN, FN_IP6_31_29,
+		GP_2_22_FN, FN_IP6_28_26,
+		GP_2_21_FN, FN_IP6_25_23,
+		GP_2_20_FN, FN_IP6_22_20,
+		GP_2_19_FN, FN_IP6_19_17,
+		GP_2_18_FN, FN_IP6_16_14,
+		GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
+		GP_2_16_FN, FN_IP8_27,
+		GP_2_15_FN, FN_IP8_26,
+		GP_2_14_FN, FN_IP8_25_24,
+		GP_2_13_FN, FN_IP8_23_22,
+		GP_2_12_FN, FN_IP8_21_20,
+		GP_2_11_FN, FN_IP8_19_18,
+		GP_2_10_FN, FN_IP8_17_16,
+		GP_2_9_FN, FN_IP8_15_14,
+		GP_2_8_FN, FN_IP8_13_12,
+		GP_2_7_FN, FN_IP8_11_10,
+		GP_2_6_FN, FN_IP8_9_8,
+		GP_2_5_FN, FN_IP8_7_6,
+		GP_2_4_FN, FN_IP8_5_4,
+		GP_2_3_FN, FN_IP8_3_2,
+		GP_2_2_FN, FN_IP8_1_0,
+		GP_2_1_FN, FN_IP7_30_29,
+		GP_2_0_FN, FN_IP7_28_27 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		GP_3_31_FN, FN_IP11_21_18,
+		GP_3_30_FN, FN_IP11_17_15,
+		GP_3_29_FN, FN_IP11_14_13,
+		GP_3_28_FN, FN_IP11_12_11,
+		GP_3_27_FN, FN_IP11_10_9,
+		GP_3_26_FN, FN_IP11_8_7,
+		GP_3_25_FN, FN_IP11_6_5,
+		GP_3_24_FN, FN_IP11_4,
+		GP_3_23_FN, FN_IP11_3_0,
+		GP_3_22_FN, FN_IP10_29_26,
+		GP_3_21_FN, FN_IP10_25_23,
+		GP_3_20_FN, FN_IP10_22_19,
+		GP_3_19_FN, FN_IP10_18_15,
+		GP_3_18_FN, FN_IP10_14_11,
+		GP_3_17_FN, FN_IP10_10_7,
+		GP_3_16_FN, FN_IP10_6_4,
+		GP_3_15_FN, FN_IP10_3_0,
+		GP_3_14_FN, FN_IP9_31_28,
+		GP_3_13_FN, FN_IP9_27_26,
+		GP_3_12_FN, FN_IP9_25_24,
+		GP_3_11_FN, FN_IP9_23_22,
+		GP_3_10_FN, FN_IP9_21_20,
+		GP_3_9_FN, FN_IP9_19_18,
+		GP_3_8_FN, FN_IP9_17_16,
+		GP_3_7_FN, FN_IP9_15_12,
+		GP_3_6_FN, FN_IP9_11_8,
+		GP_3_5_FN, FN_IP9_7_6,
+		GP_3_4_FN, FN_IP9_5_4,
+		GP_3_3_FN, FN_IP9_3_2,
+		GP_3_2_FN, FN_IP9_1_0,
+		GP_3_1_FN, FN_IP8_30_29,
+		GP_3_0_FN, FN_IP8_28 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		GP_4_31_FN, FN_IP14_18_16,
+		GP_4_30_FN, FN_IP14_15_12,
+		GP_4_29_FN, FN_IP14_11_9,
+		GP_4_28_FN, FN_IP14_8_6,
+		GP_4_27_FN, FN_IP14_5_3,
+		GP_4_26_FN, FN_IP14_2_0,
+		GP_4_25_FN, FN_IP13_30_29,
+		GP_4_24_FN, FN_IP13_28_26,
+		GP_4_23_FN, FN_IP13_25_23,
+		GP_4_22_FN, FN_IP13_22_19,
+		GP_4_21_FN, FN_IP13_18_16,
+		GP_4_20_FN, FN_IP13_15_13,
+		GP_4_19_FN, FN_IP13_12_10,
+		GP_4_18_FN, FN_IP13_9_7,
+		GP_4_17_FN, FN_IP13_6_3,
+		GP_4_16_FN, FN_IP13_2_0,
+		GP_4_15_FN, FN_IP12_30_28,
+		GP_4_14_FN, FN_IP12_27_25,
+		GP_4_13_FN, FN_IP12_24_23,
+		GP_4_12_FN, FN_IP12_22_20,
+		GP_4_11_FN, FN_IP12_19_17,
+		GP_4_10_FN, FN_IP12_16_14,
+		GP_4_9_FN, FN_IP12_13_11,
+		GP_4_8_FN, FN_IP12_10_8,
+		GP_4_7_FN, FN_IP12_7_6,
+		GP_4_6_FN, FN_IP12_5_4,
+		GP_4_5_FN, FN_IP12_3_2,
+		GP_4_4_FN, FN_IP12_1_0,
+		GP_4_3_FN, FN_IP11_31_30,
+		GP_4_2_FN, FN_IP11_29_27,
+		GP_4_1_FN, FN_IP11_26_24,
+		GP_4_0_FN, FN_IP11_23_22 }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		GP_5_31_FN, FN_IP7_24_22,
+		GP_5_30_FN, FN_IP7_21_19,
+		GP_5_29_FN, FN_IP7_18_16,
+		GP_5_28_FN, FN_DU_DOTCLKIN2,
+		GP_5_27_FN, FN_IP7_26_25,
+		GP_5_26_FN, FN_DU_DOTCLKIN0,
+		GP_5_25_FN, FN_AVS2,
+		GP_5_24_FN, FN_AVS1,
+		GP_5_23_FN, FN_USB2_OVC,
+		GP_5_22_FN, FN_USB2_PWEN,
+		GP_5_21_FN, FN_IP16_7,
+		GP_5_20_FN, FN_IP16_6,
+		GP_5_19_FN, FN_USB0_OVC_VBUS,
+		GP_5_18_FN, FN_USB0_PWEN,
+		GP_5_17_FN, FN_IP16_5_3,
+		GP_5_16_FN, FN_IP16_2_0,
+		GP_5_15_FN, FN_IP15_29_28,
+		GP_5_14_FN, FN_IP15_27_26,
+		GP_5_13_FN, FN_IP15_25_23,
+		GP_5_12_FN, FN_IP15_22_20,
+		GP_5_11_FN, FN_IP15_19_18,
+		GP_5_10_FN, FN_IP15_17_16,
+		GP_5_9_FN, FN_IP15_15_14,
+		GP_5_8_FN, FN_IP15_13_12,
+		GP_5_7_FN, FN_IP15_11_9,
+		GP_5_6_FN, FN_IP15_8_6,
+		GP_5_5_FN, FN_IP15_5_3,
+		GP_5_4_FN, FN_IP15_2_0,
+		GP_5_3_FN, FN_IP14_30_28,
+		GP_5_2_FN, FN_IP14_27_25,
+		GP_5_1_FN, FN_IP14_24_22,
+		GP_5_0_FN, FN_IP14_21_19 }
+	},
+
+	/*IPSR0 - IPSR5*/
+	{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+			     3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+		/* IP6_31_29 [3] */
+		FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+		FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
+		/* IP6_28_26 [3] */
+		FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+		FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
+		/* IP6_25_23 [3] */
+		FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+		FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
+		/* IP6_22_20 [3] */
+		FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
+		FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
+		/* IP6_19_17 [3] */
+		FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
+		FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
+		/* IP6_16_14 [3] */
+		FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+		FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+		FN_SCL2_CIS_E, 0,
+		/* IP6_13_11 [3] */
+		FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+		FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+		/* IP6_10_9 [2] */
+		FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
+		/* IP6_8_6 [3] */
+		FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
+		FN_SSI_SDATA8_C, 0, 0, 0,
+		/* IP6_5_3 [3] */
+		FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+		FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
+		/* IP6_2_0 [3] */
+		FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+		FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+			     1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+		/* IP7_31 [1] */
+		0, 0,
+		/* IP7_30_29 [2] */
+		FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+		FN_MII_RXD2,
+		/* IP7_28_27 [2] */
+		FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+		/* IP7_26_25 [2] */
+		FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
+		/* IP7_24_22 [3] */
+		FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
+		0, 0, 0,
+		/* IP7_21_19 [3] */
+		FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
+		FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
+		/* IP7_18_16 [3] */
+		FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+		FN_GLO_SS_C, 0, 0, 0,
+		/* IP7_15_13 [3] */
+		FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+		FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
+		/* IP7_12_10 [3] */
+		FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
+		FN_GLO_SCLK_C, 0, 0, 0,
+		/* IP7_9_8 [2] */
+		FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
+		/* IP7_7_6 [2] */
+		FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
+		/* IP7_5_3 [3] */
+		FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+		0, 0, 0,
+		/* IP7_2_0 [3] */
+		FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+		FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+	},
+	/*IPSR8 - IPSR16*/
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_1_29_IN, GP_1_29_OUT,
+		GP_1_28_IN, GP_1_28_OUT,
+		GP_1_27_IN, GP_1_27_OUT,
+		GP_1_26_IN, GP_1_26_OUT,
+		GP_1_25_IN, GP_1_25_OUT,
+		GP_1_24_IN, GP_1_24_OUT,
+		GP_1_23_IN, GP_1_23_OUT,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_2_29_IN, GP_2_29_OUT,
+		GP_2_28_IN, GP_2_28_OUT,
+		GP_2_27_IN, GP_2_27_OUT,
+		GP_2_26_IN, GP_2_26_OUT,
+		GP_2_25_IN, GP_2_25_OUT,
+		GP_2_24_IN, GP_2_24_OUT,
+		GP_2_23_IN, GP_2_23_OUT,
+		GP_2_22_IN, GP_2_22_OUT,
+		GP_2_21_IN, GP_2_21_OUT,
+		GP_2_20_IN, GP_2_20_OUT,
+		GP_2_19_IN, GP_2_19_OUT,
+		GP_2_18_IN, GP_2_18_OUT,
+		GP_2_17_IN, GP_2_17_OUT,
+		GP_2_16_IN, GP_2_16_OUT,
+		GP_2_15_IN, GP_2_15_OUT,
+		GP_2_14_IN, GP_2_14_OUT,
+		GP_2_13_IN, GP_2_13_OUT,
+		GP_2_12_IN, GP_2_12_OUT,
+		GP_2_11_IN, GP_2_11_OUT,
+		GP_2_10_IN, GP_2_10_OUT,
+		GP_2_9_IN, GP_2_9_OUT,
+		GP_2_8_IN, GP_2_8_OUT,
+		GP_2_7_IN, GP_2_7_OUT,
+		GP_2_6_IN, GP_2_6_OUT,
+		GP_2_5_IN, GP_2_5_OUT,
+		GP_2_4_IN, GP_2_4_OUT,
+		GP_2_3_IN, GP_2_3_OUT,
+		GP_2_2_IN, GP_2_2_OUT,
+		GP_2_1_IN, GP_2_1_OUT,
+		GP_2_0_IN, GP_2_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, GP_1_29_DATA, GP_1_28_DATA,
+		GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA,
+		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) {
+		0, 0, GP_2_29_DATA, GP_2_28_DATA,
+		GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA,
+		GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA,
+		GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA,
+		GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA,
+		GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA,
+		GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA,
+		GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
+	{ },
+};
+
+static struct pinmux_info r8a7790_pinmux_info = {
+	.name = "r8a7790_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_MII_RXD2 /* GPIO_FN_TCLK1_B */,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7790_pinmux_init(void)
+{
+	register_pinmux(&r8a7790_pinmux_info);
+}
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
new file mode 100644
index 0000000..a13317b
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
@@ -0,0 +1,92 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __PFC_R8A7790_H__
+#define __PFC_R8A7790_H__
+
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+
+#define CPU_32_PORT(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx),	\
+	PORT_1(fn, pfx##31, sfx)
+
+#define CPU_32_PORT2(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx)
+
+#if defined(CONFIG_R8A7790)
+#define CPU_32_PORT1(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_10(fn, pfx##2, sfx)				\
+/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */
+#define CPU_ALL_PORT(fn, pfx, sfx)				\
+	CPU_32_PORT(fn, pfx##_0_, sfx),				\
+	CPU_32_PORT1(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT2(fn, pfx##_2_, sfx),			\
+	CPU_32_PORT(fn, pfx##_3_, sfx),				\
+	CPU_32_PORT(fn, pfx##_4_, sfx),				\
+	CPU_32_PORT(fn, pfx##_5_, sfx)
+
+#elif defined(CONFIG_R8A7791)
+#define CPU_32_PORT1(fn, pfx, sfx)				\
+	PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx),	\
+	PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx),	\
+	PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx),	\
+	PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx)
+
+/*
+ * GP_0_0_DATA -> GP_7_25_DATA
+ * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31]
+ *  GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31])
+ */
+#define CPU_ALL_PORT(fn, pfx, sfx)				\
+	CPU_32_PORT(fn, pfx##_0_, sfx),				\
+	CPU_32_PORT1(fn, pfx##_1_, sfx),			\
+	CPU_32_PORT(fn, pfx##_2_, sfx),				\
+	CPU_32_PORT(fn, pfx##_3_, sfx),				\
+	CPU_32_PORT(fn, pfx##_4_, sfx),				\
+	CPU_32_PORT(fn, pfx##_5_, sfx),				\
+	CPU_32_PORT(fn, pfx##_6_, sfx),				\
+	CPU_32_PORT1(fn, pfx##_7_, sfx)
+#else
+#error "NO support"
+#endif
+
+#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN,	\
+				       GP##pfx##_IN, GP##pfx##_OUT)
+
+#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
+#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+
+#define GP_ALL(str)	CPU_ALL_PORT(_PORT_ALL, GP, str)
+#define PINMUX_GPIO_GP_ALL()	CPU_ALL_PORT(_GP_GPIO, , unused)
+#define PINMUX_DATA_GP_ALL()	CPU_ALL_PORT(_GP_DATA, , unused)
+
+#define PORT_10_REV(fn, pfx, sfx)				\
+	PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx),	\
+	PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx),	\
+	PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx),	\
+	PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx),	\
+	PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define CPU_32_PORT_REV(fn, pfx, sfx)					\
+	PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx),		\
+	PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx),	\
+	PORT_10_REV(fn, pfx, sfx)
+
+#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+							  FN_##ipsr, FN_##fn)
+
+#endif /* __PFC_R8A7790_H__ */
diff --git a/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
new file mode 100644
index 0000000..f49f990
--- /dev/null
+++ b/arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
@@ -0,0 +1,1117 @@
+/*
+ * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <sh_pfc.h>
+#include <asm/gpio.h>
+#include "pfc-r8a7790.h"
+
+enum {
+	PINMUX_RESERVED = 0,
+
+	PINMUX_DATA_BEGIN,
+	GP_ALL(DATA),
+	PINMUX_DATA_END,
+
+	PINMUX_INPUT_BEGIN,
+	GP_ALL(IN),
+	PINMUX_INPUT_END,
+
+	PINMUX_OUTPUT_BEGIN,
+	GP_ALL(OUT),
+	PINMUX_OUTPUT_END,
+
+	PINMUX_FUNCTION_BEGIN,
+	GP_ALL(FN),
+
+	/* GPSR0 */
+	FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
+	FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
+	FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
+	FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
+	FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
+	FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
+
+	/* GPSR1 */
+	FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
+	FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
+	FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
+	FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
+	FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
+	FN_IP3_21_20,
+
+	/* GPSR2 */
+	FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
+	FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
+	FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
+	FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
+	FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
+	FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
+	FN_IP6_5_3, FN_IP6_7_6,
+
+	/* GPSR3 */
+	FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
+	FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
+	FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
+	FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
+	FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
+	FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
+	FN_IP9_18_17,
+
+	/* GPSR4 */
+	FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
+	FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2,
+	FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5,
+	FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
+	FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
+	FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
+	FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
+	FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
+
+	/* GPSR5 */
+	FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
+	FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
+	FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
+	FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
+	FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
+	FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
+	FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
+
+	/* GPSR6 */
+	FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
+	FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
+	FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
+	FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
+	FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
+	FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
+
+	/* GPSR7 */
+	FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
+	FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
+	FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
+	FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
+	FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
+	FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
+
+	/* IPSR0 -  IPSR10 */
+
+	/* IPSR11 */
+	FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
+	FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
+	FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+	FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
+	FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
+	FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
+	FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
+	FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
+	FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
+	FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
+	FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
+	FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
+	FN_VI1_DATA7, FN_AVB_MDC,
+	FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
+	FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
+
+	/* IPSR12 */
+	FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
+	FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
+	FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+	FN_SCL2_D, FN_MSIOF1_RXD_E,
+	FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
+	FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+	FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+	FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+	FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+	FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+	FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
+	FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
+	FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
+	FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+	FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+	FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+	FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+
+	/* IPSR13 */
+	/* MOD_SEL */
+	FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+	FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+	FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+	FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+	FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+	FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+	FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+	FN_SEL_QSP_0, FN_SEL_QSP_1,
+	FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+	FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
+	FN_SEL_HSCIF1_4,
+	FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
+	FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+	FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+	FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+	FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
+
+	/* MOD_SEL2 */
+	FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+	FN_SEL_SCIF0_4,
+	FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+	FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+	FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+	FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+	FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+	FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
+	FN_SEL_ADG_0, FN_SEL_ADG_1,
+	FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
+	FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
+	FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+	FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
+	FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
+	FN_SEL_SIM_0, FN_SEL_SIM_1,
+	FN_SEL_SSI8_0, FN_SEL_SSI8_1,
+
+	/* MOD_SEL3 */
+	FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+	FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+	FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
+	FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
+	FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
+	FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
+	FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+	FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+	FN_SEL_MMC_0, FN_SEL_MMC_1,
+	FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+	FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+	FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
+	FN_SEL_IIC1_4,
+	FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
+
+	/* MOD_SEL4 */
+	FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+	FN_SEL_SOF1_4,
+	FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+	FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
+	FN_SEL_RAD_0, FN_SEL_RAD_1,
+	FN_SEL_RCN_0, FN_SEL_RCN_1,
+	FN_SEL_RSP_0, FN_SEL_RSP_1,
+	FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
+	FN_SEL_SCIF2_4,
+	FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
+	FN_SEL_SOF2_4,
+	FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+	FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+	FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
+	PINMUX_FUNCTION_END,
+
+	PINMUX_MARK_BEGIN,
+
+	EX_CS0_N_MARK, RD_N_MARK,
+
+	AUDIO_CLKA_MARK,
+
+	VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK,
+	VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK,
+	VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK,
+
+	USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK,
+
+	/* IPSR0  IPSR10 */
+	/* IPSR11 */
+	VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
+	VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
+	VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
+	SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
+	VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
+	TX4_B_MARK, SCIFA4_TXD_B_MARK,
+	VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
+	RX4_B_MARK, SCIFA4_RXD_B_MARK,
+	VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
+	VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
+	VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
+	VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
+	VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
+	VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
+	VI1_DATA7_MARK, AVB_MDC_MARK,
+	ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
+	ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
+
+	/* IPSR12 */
+	ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
+	ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
+	ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
+	SCL2_D_MARK, MSIOF1_RXD_E_MARK,
+	ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
+	SDA2_D_MARK, MSIOF1_SCK_E_MARK,
+	ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
+	CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
+	ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
+	CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
+	ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
+	ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
+	ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
+	ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
+	STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
+	ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
+	STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
+	ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
+
+	/* IPSR13 */
+	PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+	PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+	/* OTHER IPSR0  - IPSR10 */
+	/* IPSR11 */
+	PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
+	PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
+	PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
+	PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
+	PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
+	PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
+	PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
+	PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
+	PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
+	PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
+	PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
+	PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
+	PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
+	PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
+	PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
+	PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
+	PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
+	PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
+	PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
+	PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
+	PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
+	PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
+	PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
+
+	/* IPSR12 */
+	PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
+	PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
+	PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
+	PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
+	PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
+	PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
+	PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
+	PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
+	PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
+	PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
+	PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
+	PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
+	PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
+	PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
+	PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
+	PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
+	PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
+	PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
+	PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
+	PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
+	PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
+	PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
+	PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
+	PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
+	PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
+
+	/* IPSR13 - IPSR16 */
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+	PINMUX_GPIO_GP_ALL(),
+
+	/* OTHER, IPSR0 - IPSR10 */
+	/* IPSR11 */
+	GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B),
+	GPIO_FN(RX0_C), GPIO_FN(SDA1_D),
+	GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7),
+	GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B),
+	GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B),
+	GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E),
+	GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D),
+	GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B),
+	GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B),
+	GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B),
+	GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B),
+	GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B),
+	GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B),
+	GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4),
+	GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5),
+	GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6),
+	GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7),
+	GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER),
+	GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO),
+	GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV),
+	GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC),
+	GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC),
+	GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C),
+	GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C),
+
+	/* IPSR12 */
+	GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7),
+	GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7),
+	GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C),
+	GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E),
+	GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C),
+	GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E),
+	GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B),
+	GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E),
+	GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B),
+	GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E),
+	GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3),
+	GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B),
+	GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C),
+	GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C),
+	GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C),
+	GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D),
+	GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C),
+	GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D),
+	GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C),
+
+	/* IPSR13 - IPSR16 */
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+	{ PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+		GP_0_31_FN, FN_IP1_22_20,
+		GP_0_30_FN, FN_IP1_19_17,
+		GP_0_29_FN, FN_IP1_16_14,
+		GP_0_28_FN, FN_IP1_13_11,
+		GP_0_27_FN, FN_IP1_10_8,
+		GP_0_26_FN, FN_IP1_7_6,
+		GP_0_25_FN, FN_IP1_5_4,
+		GP_0_24_FN, FN_IP1_3_2,
+		GP_0_23_FN, FN_IP1_1_0,
+		GP_0_22_FN, FN_IP0_30_29,
+		GP_0_21_FN, FN_IP0_28_27,
+		GP_0_20_FN, FN_IP0_26_25,
+		GP_0_19_FN, FN_IP0_24_23,
+		GP_0_18_FN, FN_IP0_22_21,
+		GP_0_17_FN, FN_IP0_20_19,
+		GP_0_16_FN, FN_IP0_18_16,
+		GP_0_15_FN, FN_IP0_15,
+		GP_0_14_FN, FN_IP0_14,
+		GP_0_13_FN, FN_IP0_13,
+		GP_0_12_FN, FN_IP0_12,
+		GP_0_11_FN, FN_IP0_11,
+		GP_0_10_FN, FN_IP0_10,
+		GP_0_9_FN, FN_IP0_9,
+		GP_0_8_FN, FN_IP0_8,
+		GP_0_7_FN, FN_IP0_7,
+		GP_0_6_FN, FN_IP0_6,
+		GP_0_5_FN, FN_IP0_5,
+		GP_0_4_FN, FN_IP0_4,
+		GP_0_3_FN, FN_IP0_3,
+		GP_0_2_FN, FN_IP0_2,
+		GP_0_1_FN, FN_IP0_1,
+		GP_0_0_FN, FN_IP0_0, }
+	},
+	{ PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_FN, FN_IP3_21_20,
+		GP_1_24_FN, FN_IP3_19_18,
+		GP_1_23_FN, FN_IP3_17_16,
+		GP_1_22_FN, FN_IP3_15_14,
+		GP_1_21_FN, FN_IP3_13_12,
+		GP_1_20_FN, FN_IP3_11_9,
+		GP_1_19_FN, FN_RD_N,
+		GP_1_18_FN, FN_IP3_8_6,
+		GP_1_17_FN, FN_IP3_5_3,
+		GP_1_16_FN, FN_IP3_2_0,
+		GP_1_15_FN, FN_IP2_29_27,
+		GP_1_14_FN, FN_IP2_26_25,
+		GP_1_13_FN, FN_IP2_24_23,
+		GP_1_12_FN, FN_EX_CS0_N,
+		GP_1_11_FN, FN_IP2_22_21,
+		GP_1_10_FN, FN_IP2_20_19,
+		GP_1_9_FN, FN_IP2_18_16,
+		GP_1_8_FN, FN_IP2_15_13,
+		GP_1_7_FN, FN_IP2_12_10,
+		GP_1_6_FN, FN_IP2_9_7,
+		GP_1_5_FN, FN_IP2_6_5,
+		GP_1_4_FN, FN_IP2_4_3,
+		GP_1_3_FN, FN_IP2_2_0,
+		GP_1_2_FN, FN_IP1_31_29,
+		GP_1_1_FN, FN_IP1_28_26,
+		GP_1_0_FN, FN_IP1_25_23, }
+	},
+	{ PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+		GP_2_31_FN, FN_IP6_7_6,
+		GP_2_30_FN, FN_IP6_5_3,
+		GP_2_29_FN, FN_IP6_2_0,
+		GP_2_28_FN, FN_AUDIO_CLKA,
+		GP_2_27_FN, FN_IP5_31_29,
+		GP_2_26_FN, FN_IP5_28_26,
+		GP_2_25_FN, FN_IP5_25_24,
+		GP_2_24_FN, FN_IP5_23_22,
+		GP_2_23_FN, FN_IP5_21_20,
+		GP_2_22_FN, FN_IP5_19_17,
+		GP_2_21_FN, FN_IP5_16_15,
+		GP_2_20_FN, FN_IP5_14_12,
+		GP_2_19_FN, FN_IP5_11_9,
+		GP_2_18_FN, FN_IP5_8_6,
+		GP_2_17_FN, FN_IP5_5_3,
+		GP_2_16_FN, FN_IP5_2_0,
+		GP_2_15_FN, FN_IP4_30_28,
+		GP_2_14_FN, FN_IP4_27_26,
+		GP_2_13_FN, FN_IP4_25_24,
+		GP_2_12_FN, FN_IP4_23_22,
+		GP_2_11_FN, FN_IP4_21,
+		GP_2_10_FN, FN_IP4_20,
+		GP_2_9_FN, FN_IP4_19,
+		GP_2_8_FN, FN_IP4_18_16,
+		GP_2_7_FN, FN_IP4_15_13,
+		GP_2_6_FN, FN_IP4_12_10,
+		GP_2_5_FN, FN_IP4_9_8,
+		GP_2_4_FN, FN_IP4_7_5,
+		GP_2_3_FN, FN_IP4_4_2,
+		GP_2_2_FN, FN_IP4_1_0,
+		GP_2_1_FN, FN_IP3_30_28,
+		GP_2_0_FN, FN_IP3_27_25 }
+	},
+	{ PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+		GP_3_31_FN, FN_IP9_18_17,
+		GP_3_30_FN, FN_IP9_16,
+		GP_3_29_FN, FN_IP9_15_13,
+		GP_3_28_FN, FN_IP9_12,
+		GP_3_27_FN, FN_IP9_11,
+		GP_3_26_FN, FN_IP9_10_8,
+		GP_3_25_FN, FN_IP9_7,
+		GP_3_24_FN, FN_IP9_6,
+		GP_3_23_FN, FN_IP9_5_3,
+		GP_3_22_FN, FN_IP9_2_0,
+		GP_3_21_FN, FN_IP8_30_28,
+		GP_3_20_FN, FN_IP8_27_26,
+		GP_3_19_FN, FN_IP8_25_24,
+		GP_3_18_FN, FN_IP8_23_21,
+		GP_3_17_FN, FN_IP8_20_18,
+		GP_3_16_FN, FN_IP8_17_15,
+		GP_3_15_FN, FN_IP8_14_12,
+		GP_3_14_FN, FN_IP8_11_9,
+		GP_3_13_FN, FN_IP8_8_6,
+		GP_3_12_FN, FN_IP8_5_3,
+		GP_3_11_FN, FN_IP8_2_0,
+		GP_3_10_FN, FN_IP7_29_27,
+		GP_3_9_FN, FN_IP7_26_24,
+		GP_3_8_FN, FN_IP7_23_21,
+		GP_3_7_FN, FN_IP7_20_19,
+		GP_3_6_FN, FN_IP7_18_17,
+		GP_3_5_FN, FN_IP7_16_15,
+		GP_3_4_FN, FN_IP7_14_13,
+		GP_3_3_FN, FN_IP7_12_11,
+		GP_3_2_FN, FN_IP7_10_9,
+		GP_3_1_FN, FN_IP7_8_6,
+		GP_3_0_FN, FN_IP7_5_3 }
+	},
+	{ PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+		GP_4_31_FN, FN_IP15_5_4,
+		GP_4_30_FN, FN_IP15_3_2,
+		GP_4_29_FN, FN_IP15_1_0,
+		GP_4_28_FN, FN_IP11_8_6,
+		GP_4_27_FN, FN_IP11_5_3,
+		GP_4_26_FN, FN_IP11_2_0,
+		GP_4_25_FN, FN_IP10_31_29,
+		GP_4_24_FN, FN_IP10_28_27,
+		GP_4_23_FN, FN_IP10_26_25,
+		GP_4_22_FN, FN_IP10_24_22,
+		GP_4_21_FN, FN_IP10_21_19,
+		GP_4_20_FN, FN_IP10_18_17,
+		GP_4_19_FN, FN_IP10_16_15,
+		GP_4_18_FN, FN_IP10_14_12,
+		GP_4_17_FN, FN_IP10_11_9,
+		GP_4_16_FN, FN_IP10_8_6,
+		GP_4_15_FN, FN_IP10_5_3,
+		GP_4_14_FN, FN_IP10_2_0,
+		GP_4_13_FN, FN_IP9_31_29,
+		GP_4_12_FN, FN_VI0_DATA0_VI0_B7,
+		GP_4_11_FN, FN_VI0_DATA0_VI0_B6,
+		GP_4_10_FN, FN_VI0_DATA0_VI0_B5,
+		GP_4_9_FN, FN_VI0_DATA0_VI0_B4,
+		GP_4_8_FN, FN_IP9_28_27,
+		GP_4_7_FN, FN_VI0_DATA0_VI0_B2,
+		GP_4_6_FN, FN_VI0_DATA0_VI0_B1,
+		GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
+		GP_4_4_FN, FN_IP9_26_25,
+		GP_4_3_FN, FN_IP9_24_23,
+		GP_4_2_FN, FN_IP9_22_21,
+		GP_4_1_FN, FN_IP9_20_19,
+		GP_4_0_FN, FN_VI0_CLK }
+	},
+	{ PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+		GP_5_31_FN, FN_IP3_24_22,
+		GP_5_30_FN, FN_IP13_9_7,
+		GP_5_29_FN, FN_IP13_6_5,
+		GP_5_28_FN, FN_IP13_4_3,
+		GP_5_27_FN, FN_IP13_2_0,
+		GP_5_26_FN, FN_IP12_29_27,
+		GP_5_25_FN, FN_IP12_26_24,
+		GP_5_24_FN, FN_IP12_23_22,
+		GP_5_23_FN, FN_IP12_21_20,
+		GP_5_22_FN, FN_IP12_19_18,
+		GP_5_21_FN, FN_IP12_17_16,
+		GP_5_20_FN, FN_IP12_15_13,
+		GP_5_19_FN, FN_IP12_12_10,
+		GP_5_18_FN, FN_IP12_9_7,
+		GP_5_17_FN, FN_IP12_6_4,
+		GP_5_16_FN, FN_IP12_3_2,
+		GP_5_15_FN, FN_IP12_1_0,
+		GP_5_14_FN, FN_IP11_31_30,
+		GP_5_13_FN, FN_IP11_29_28,
+		GP_5_12_FN, FN_IP11_27,
+		GP_5_11_FN, FN_IP11_26,
+		GP_5_10_FN, FN_IP11_25,
+		GP_5_9_FN, FN_IP11_24,
+		GP_5_8_FN, FN_IP11_23,
+		GP_5_7_FN, FN_IP11_22,
+		GP_5_6_FN, FN_IP11_21,
+		GP_5_5_FN, FN_IP11_20,
+		GP_5_4_FN, FN_IP11_19,
+		GP_5_3_FN, FN_IP11_18_17,
+		GP_5_2_FN, FN_IP11_16_15,
+		GP_5_1_FN, FN_IP11_14_12,
+		GP_5_0_FN, FN_IP11_11_9 }
+	},
+	{ PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
+		0, 0,
+		0, 0,
+		GP_6_29_FN, FN_IP14_31_29,
+		GP_6_28_FN, FN_IP14_28_26,
+		GP_6_27_FN, FN_IP14_25_23,
+		GP_6_26_FN, FN_IP14_22_20,
+		GP_6_25_FN, FN_IP14_19_17,
+		GP_6_24_FN, FN_IP14_16_14,
+		GP_6_23_FN, FN_IP14_13_11,
+		GP_6_22_FN, FN_IP14_10_8,
+		GP_6_21_FN, FN_IP14_7,
+		GP_6_20_FN, FN_IP14_6,
+		GP_6_19_FN, FN_IP14_5,
+		GP_6_18_FN, FN_IP14_4,
+		GP_6_17_FN, FN_IP14_3,
+		GP_6_16_FN, FN_IP14_2,
+		GP_6_15_FN, FN_IP14_1_0,
+		GP_6_14_FN, FN_IP13_30_28,
+		GP_6_13_FN, FN_IP13_27,
+		GP_6_12_FN, FN_IP13_26,
+		GP_6_11_FN, FN_IP13_25,
+		GP_6_10_FN, FN_IP13_24_23,
+		GP_6_9_FN, FN_IP13_22,
+		0, 0,
+		GP_6_7_FN, FN_IP13_21_19,
+		GP_6_6_FN, FN_IP13_18_16,
+		GP_6_5_FN, FN_IP13_15,
+		GP_6_4_FN, FN_IP13_14,
+		GP_6_3_FN, FN_IP13_13,
+		GP_6_2_FN, FN_IP13_12,
+		GP_6_1_FN, FN_IP13_11,
+		GP_6_0_FN, FN_IP13_10 }
+	},
+	{ PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_25_FN, FN_USB1_PWEN,
+		GP_7_24_FN, FN_USB0_OVC,
+		GP_7_23_FN, FN_USB0_PWEN,
+		GP_7_22_FN, FN_IP15_14_12,
+		GP_7_21_FN, FN_IP15_11_9,
+		GP_7_20_FN, FN_IP15_8_6,
+		GP_7_19_FN, FN_IP7_2_0,
+		GP_7_18_FN, FN_IP6_29_27,
+		GP_7_17_FN, FN_IP6_26_24,
+		GP_7_16_FN, FN_IP6_23_21,
+		GP_7_15_FN, FN_IP6_20_19,
+		GP_7_14_FN, FN_IP6_18_16,
+		GP_7_13_FN, FN_IP6_15_14,
+		GP_7_12_FN, FN_IP6_13_12,
+		GP_7_11_FN, FN_IP6_11_10,
+		GP_7_10_FN, FN_IP6_9_8,
+		GP_7_9_FN, FN_IP16_11_10,
+		GP_7_8_FN, FN_IP16_9_8,
+		GP_7_7_FN, FN_IP16_7_6,
+		GP_7_6_FN, FN_IP16_5_3,
+		GP_7_5_FN, FN_IP16_2_0,
+		GP_7_4_FN, FN_IP15_29_27,
+		GP_7_3_FN, FN_IP15_26_24,
+		GP_7_2_FN, FN_IP15_23_21,
+		GP_7_1_FN, FN_IP15_20_18,
+		GP_7_0_FN, FN_IP15_17_15 }
+	},
+	/* IPSR0 - IPSR10 */
+	{ PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+			     2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+			     3, 3, 3, 3, 3) {
+		/* IP11_31_30 [2] */
+		FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
+		/* IP11_29_28 [2] */
+		FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
+		/* IP11_27 [1] */
+		FN_VI1_DATA7, FN_AVB_MDC,
+		/* IP11_26 [1] */
+		FN_VI1_DATA6, FN_AVB_MAGIC,
+		/* IP11_25 [1] */
+		FN_VI1_DATA5, FN_AVB_RX_DV,
+		/* IP11_24 [1] */
+		FN_VI1_DATA4, FN_AVB_MDIO,
+		/* IP11_23 [1] */
+		FN_VI1_DATA3, FN_AVB_RX_ER,
+		/* IP11_22 [1] */
+		FN_VI1_DATA2, FN_AVB_RXD7,
+		/* IP11_21 [1] */
+		FN_VI1_DATA1, FN_AVB_RXD6,
+		/* IP11_20 [1] */
+		FN_VI1_DATA0, FN_AVB_RXD5,
+		/* IP11_19 [1] */
+		FN_VI1_CLK, FN_AVB_RXD4,
+		/* IP11_18_17 [2] */
+		FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
+		/* IP11_16_15 [2] */
+		FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
+		/* IP11_14_12 [3] */
+		FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
+		FN_RX4_B, FN_SCIFA4_RXD_B,
+		0, 0, 0,
+		/* IP11_11_9 [3] */
+		FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
+		FN_TX4_B, FN_SCIFA4_TXD_B,
+		0, 0, 0,
+		/* IP11_8_6 [3] */
+		FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
+		FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
+		/* IP11_5_3 [3] */
+		FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
+		0, 0, 0,
+		/* IP11_2_0 [3] */
+		FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
+		0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+			     2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
+		/* IP12_31_30 [2] */
+		0, 0, 0, 0,
+		/* IP12_29_27 [3] */
+		FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
+		FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
+		0, 0, 0,
+		/* IP12_26_24 [3] */
+		FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
+		FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
+		0, 0, 0,
+		/* IP12_23_22 [2] */
+		FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
+		/* IP12_21_20 [2] */
+		FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
+		/* IP12_19_18 [2] */
+		FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
+		/* IP12_17_16 [2] */
+		FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
+		/* IP12_15_13 [3] */
+		FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
+		FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
+		0, 0, 0,
+		/* IP12_12_10 [3] */
+		FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
+		FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
+		0, 0, 0,
+		/* IP12_9_7 [3] */
+		FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
+		FN_SDA2_D, FN_MSIOF1_SCK_E,
+		0, 0, 0,
+		/* IP12_6_4 [3] */
+		FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
+		FN_SCL2_D, FN_MSIOF1_RXD_E,
+		0, 0, 0,
+		/* IP12_3_2 [2] */
+		FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
+		/* IP12_1_0 [2] */
+		FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
+	},
+
+	/* IPSR13 - IPSR16 */
+
+	{ PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+			     1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
+			     3, 2, 2, 2, 1, 2, 2, 2) {
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SCIF1 [2] */
+		FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+		/* SEL_SCIFB [2] */
+		FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
+		/* SEL_SCIFB2 [2] */
+		FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
+		FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
+		/* SEL_SCIFB1 [3] */
+		FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
+		FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+		0, 0, 0, 0,
+		/* SEL_SCIFA1 [2] */
+		FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
+		/* SEL_SSI9 [1] */
+		FN_SEL_SSI9_0, FN_SEL_SSI9_1,
+		/* SEL_SCFA [1] */
+		FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+		/* SEL_QSP [1] */
+		FN_SEL_QSP_0, FN_SEL_QSP_1,
+		/* SEL_SSI7 [1] */
+		FN_SEL_SSI7_0, FN_SEL_SSI7_1,
+		/* SEL_HSCIF1 [3] */
+		FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
+		FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
+		0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_VI1 [2] */
+		FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_TMU [1] */
+		FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+		/* SEL_LBS [2] */
+		FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
+		/* SEL_TSIF0 [2] */
+		FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+		/* SEL_SOF0 [2] */
+		FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+			     3, 1, 1, 3, 2, 1, 1, 2, 2,
+			     1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
+		/* SEL_SCIF0 [3] */
+		FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
+		FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
+		0, 0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SCIF [1] */
+		FN_SEL_SCIF_0, FN_SEL_SCIF_1,
+		/* SEL_CAN0 [3] */
+		FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+		FN_SEL_CAN0_4, FN_SEL_CAN0_5,
+		0, 0,
+		/* SEL_CAN1 [2] */
+		FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SCIFA2 [1] */
+		FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
+		/* SEL_SCIF4 [2] */
+		FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_ADG [1] */
+		FN_SEL_ADG_0, FN_SEL_ADG_1,
+		/* SEL_FM [3] */
+		FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
+		FN_SEL_FM_3, FN_SEL_FM_4,
+		0, 0, 0,
+		/* SEL_SCIFA5 [2] */
+		FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_GPS [2] */
+		FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+		/* SEL_SCIFA4 [2] */
+		FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
+		/* SEL_SCIFA3 [2] */
+		FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
+		/* SEL_SIM [1] */
+		FN_SEL_SIM_0, FN_SEL_SIM_1,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SSI8 [1] */
+		FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+			     2, 2, 2, 2, 2, 2, 2, 2,
+			     1, 1, 2, 2, 3, 2, 2, 2, 1) {
+		/* SEL_HSCIF2 [2] */
+		FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
+		FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
+		/* SEL_CANCLK [2] */
+		FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+		FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
+		/* SEL_IIC8 [2] */
+		FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
+		/* SEL_IIC7 [2] */
+		FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
+		/* SEL_IIC4 [2] */
+		FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
+		/* SEL_IIC3 [2] */
+		FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
+		/* SEL_SCIF3 [2] */
+		FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
+		/* SEL_IEB [2] */
+		FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+		/* SEL_MMC [1] */
+		FN_SEL_MMC_0, FN_SEL_MMC_1,
+		/* SEL_SCIF5 [1] */
+		FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_IIC2 [2] */
+		FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+		/* SEL_IIC1 [3] */
+		FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
+		FN_SEL_IIC1_4,
+		0, 0, 0,
+		/* SEL_IIC0 [2] */
+		FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [1] */
+		0, 0, }
+	},
+	{ PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
+			     3, 2, 2, 1, 1, 1, 1, 3, 2,
+			     2, 3, 1, 1, 1, 2, 2, 2, 2) {
+		/* SEL_SOF1 [3] */
+		FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
+		FN_SEL_SOF1_4,
+		0, 0, 0,
+		/* SEL_HSCIF0 [2] */
+		FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
+		/* SEL_DIS [2] */
+		FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_RAD [1] */
+		FN_SEL_RAD_0, FN_SEL_RAD_1,
+		/* SEL_RCN [1] */
+		FN_SEL_RCN_0, FN_SEL_RCN_1,
+		/* SEL_RSP [1] */
+		FN_SEL_RSP_0, FN_SEL_RSP_1,
+		/* SEL_SCIF2 [3] */
+		FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
+		FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
+		0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* SEL_SOF2 [3] */
+		FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
+		FN_SEL_SOF2_3, FN_SEL_SOF2_4,
+		0, 0, 0,
+		/* RESEVED [1] */
+		0, 0,
+		/* SEL_SSI1 [1] */
+		FN_SEL_SSI1_0, FN_SEL_SSI1_1,
+		/* SEL_SSI0 [1] */
+		FN_SEL_SSI0_0, FN_SEL_SSI0_1,
+		/* SEL_SSP [2] */
+		FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0,
+		/* RESEVED [2] */
+		0, 0, 0, 0, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
+	{ PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_1_25_IN, GP_1_25_OUT,
+		GP_1_24_IN, GP_1_24_OUT,
+		GP_1_23_IN, GP_1_23_OUT,
+		GP_1_22_IN, GP_1_22_OUT,
+		GP_1_21_IN, GP_1_21_OUT,
+		GP_1_20_IN, GP_1_20_OUT,
+		GP_1_19_IN, GP_1_19_OUT,
+		GP_1_18_IN, GP_1_18_OUT,
+		GP_1_17_IN, GP_1_17_OUT,
+		GP_1_16_IN, GP_1_16_OUT,
+		GP_1_15_IN, GP_1_15_OUT,
+		GP_1_14_IN, GP_1_14_OUT,
+		GP_1_13_IN, GP_1_13_OUT,
+		GP_1_12_IN, GP_1_12_OUT,
+		GP_1_11_IN, GP_1_11_OUT,
+		GP_1_10_IN, GP_1_10_OUT,
+		GP_1_9_IN, GP_1_9_OUT,
+		GP_1_8_IN, GP_1_8_OUT,
+		GP_1_7_IN, GP_1_7_OUT,
+		GP_1_6_IN, GP_1_6_OUT,
+		GP_1_5_IN, GP_1_5_OUT,
+		GP_1_4_IN, GP_1_4_OUT,
+		GP_1_3_IN, GP_1_3_OUT,
+		GP_1_2_IN, GP_1_2_OUT,
+		GP_1_1_IN, GP_1_1_OUT,
+		GP_1_0_IN, GP_1_0_OUT, }
+	},
+	{ PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
+	{ PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
+	{ PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
+	{ PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
+	{ PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
+	{ PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		0, 0,
+		GP_7_25_IN, GP_7_25_OUT,
+		GP_7_24_IN, GP_7_24_OUT,
+		GP_7_23_IN, GP_7_23_OUT,
+		GP_7_22_IN, GP_7_22_OUT,
+		GP_7_21_IN, GP_7_21_OUT,
+		GP_7_20_IN, GP_7_20_OUT,
+		GP_7_19_IN, GP_7_19_OUT,
+		GP_7_18_IN, GP_7_18_OUT,
+		GP_7_17_IN, GP_7_17_OUT,
+		GP_7_16_IN, GP_7_16_OUT,
+		GP_7_15_IN, GP_7_15_OUT,
+		GP_7_14_IN, GP_7_14_OUT,
+		GP_7_13_IN, GP_7_13_OUT,
+		GP_7_12_IN, GP_7_12_OUT,
+		GP_7_11_IN, GP_7_11_OUT,
+		GP_7_10_IN, GP_7_10_OUT,
+		GP_7_9_IN, GP_7_9_OUT,
+		GP_7_8_IN, GP_7_8_OUT,
+		GP_7_7_IN, GP_7_7_OUT,
+		GP_7_6_IN, GP_7_6_OUT,
+		GP_7_5_IN, GP_7_5_OUT,
+		GP_7_4_IN, GP_7_4_OUT,
+		GP_7_3_IN, GP_7_3_OUT,
+		GP_7_2_IN, GP_7_2_OUT,
+		GP_7_1_IN, GP_7_1_OUT,
+		GP_7_0_IN, GP_7_0_OUT, }
+	},
+	{ },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+	{ PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
+	{ PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_1_25_DATA, GP_1_24_DATA,
+		GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
+		GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
+		GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
+		GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
+		GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
+		GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
+	},
+	{ PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
+	{ PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
+	{ PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
+	{ PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
+	{ PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
+	{ PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
+		0, 0, 0, 0,
+		0, 0, GP_7_25_DATA, GP_7_24_DATA,
+		GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA,
+		GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA,
+		GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
+		GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
+		GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
+		GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
+	},
+	{ },
+};
+
+static struct pinmux_info r8a7791_pinmux_info = {
+	.name = "r8a7791_pfc",
+
+	.unlock_reg = 0xe6060000, /* PMMR */
+
+	.reserved_id = PINMUX_RESERVED,
+	.data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+	.mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+	.first_gpio = GPIO_GP_0_0,
+	.last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */,
+
+	.gpios = pinmux_gpios,
+	.cfg_regs = pinmux_config_regs,
+	.data_regs = pinmux_data_regs,
+
+	.gpio_data = pinmux_data,
+	.gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7791_pinmux_init(void)
+{
+	register_pinmux(&r8a7791_pinmux_info);
+}
diff --git a/arch/arm/cpu/armv7/rmobile/timer.c b/arch/arm/cpu/armv7/rmobile/timer.c
index 72e0c12..04700e7 100644
--- a/arch/arm/cpu/armv7/rmobile/timer.c
+++ b/arch/arm/cpu/armv7/rmobile/timer.c
@@ -6,6 +6,7 @@
  */
 
 #include <common.h>
+#include <div64.h>
 #include <asm/io.h>
 #include <asm/arch-armv7/globaltimer.h>
 #include <asm/arch/rmobile.h>
@@ -38,13 +39,16 @@
 	u64 timer = get_cpu_global_timer();
 
 	timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1));
-	timer /= (u64)CLK2MHZ(CONFIG_SYS_CPU_CLK);
+	do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK));
 	return timer;
 }
 
 static ulong get_time_ms(void)
 {
-	return (ulong)(get_time_us() / 1000);
+	u64 us = get_time_us();
+
+	do_div(us, 1000);
+	return us;
 }
 
 int timer_init(void)
diff --git a/arch/arm/cpu/armv7/socfpga/Makefile b/arch/arm/cpu/armv7/socfpga/Makefile
index dac2bbd..3e84a0c 100644
--- a/arch/arm/cpu/armv7/socfpga/Makefile
+++ b/arch/arm/cpu/armv7/socfpga/Makefile
@@ -9,4 +9,4 @@
 
 obj-y	:= lowlevel_init.o
 obj-y	+= misc.o timer.o reset_manager.o system_manager.o
-obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/cpu/armv7/socfpga/freeze_controller.c b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
new file mode 100644
index 0000000..b8c9bce
--- /dev/null
+++ b/arch/arm/cpu/armv7/socfpga/freeze_controller.c
@@ -0,0 +1,215 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/freeze_controller.h>
+#include <asm/arch/timer.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_freeze_controller *freeze_controller_base =
+		(void *)(SOCFPGA_SYSMGR_ADDRESS + SYSMGR_FRZCTRL_ADDRESS);
+
+/*
+ * Default state from cold reset is FREEZE_ALL; the global
+ * flag is set to TRUE to indicate the IO banks are frozen
+ */
+static uint32_t frzctrl_channel_freeze[FREEZE_CHANNEL_NUM]
+	= { FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN,
+	FREEZE_CTRL_FROZEN, FREEZE_CTRL_FROZEN};
+
+/* Freeze HPS IOs */
+void sys_mgr_frzctrl_freeze_req(void)
+{
+	u32 ioctrl_reg_offset;
+	u32 reg_value;
+	u32 reg_cfg_mask;
+	u32 channel_id;
+
+	/* select software FSM */
+	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
+
+	/* Freeze channel 0 to 2 */
+	for (channel_id = 0; channel_id <= 2; channel_id++) {
+		ioctrl_reg_offset = (u32)(
+			&freeze_controller_base->vioctrl +
+			(channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+		/*
+		 * Assert active low enrnsl, plniotri
+		 * and niotri signals
+		 */
+		reg_cfg_mask =
+			SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+		clrbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * Assert active low bhniotri signal and de-assert
+		 * active high csrdone
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+		clrbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/* Set global flag to indicate channel is frozen */
+		frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+	}
+
+	/* Freeze channel 3 */
+	/*
+	 * Assert active low enrnsl, plniotri and
+	 * niotri signals
+	 */
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+	clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+	/*
+	 * assert active low bhniotri & nfrzdrv signals,
+	 * de-assert active high csrdone and assert
+	 * active high frzreg and nfrzdrv signals
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK;
+	reg_value
+		= (reg_value & ~reg_cfg_mask)
+		| SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/*
+	 * assert active high reinit signal and de-assert
+	 * active high pllbiasen signals
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_value
+		= (reg_value &
+		~SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK)
+		| SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/* Set global flag to indicate channel is frozen */
+	frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_FROZEN;
+}
+
+/* Unfreeze/Thaw HPS IOs */
+void sys_mgr_frzctrl_thaw_req(void)
+{
+	u32 ioctrl_reg_offset;
+	u32 reg_cfg_mask;
+	u32 reg_value;
+	u32 channel_id;
+
+	/* select software FSM */
+	writel(SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW,	&freeze_controller_base->src);
+
+	/* Thaw channel 0 to 2 */
+	for (channel_id = 0; channel_id <= 2; channel_id++) {
+		ioctrl_reg_offset
+			= (u32)(&freeze_controller_base->vioctrl
+				+ (channel_id << SYSMGR_FRZCTRL_VIOCTRL_SHIFT));
+
+		/*
+		 * Assert active low bhniotri signal and
+		 * de-assert active high csrdone
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK;
+		setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * de-assert active low plniotri and niotri signals
+		 */
+		reg_cfg_mask
+			= SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK
+			| SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK;
+		setbits_le32(ioctrl_reg_offset,	reg_cfg_mask);
+
+		/*
+		 * Note: Delay for 20ns at min
+		 * de-assert active low enrnsl signal
+		 */
+		setbits_le32(ioctrl_reg_offset,
+			SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK);
+
+		/* Set global flag to indicate channel is thawed */
+		frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
+	}
+
+	/* Thaw channel 3 */
+	/* de-assert active high reinit signal */
+	clrbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * assert active high pllbiasen signals
+	 */
+	setbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK);
+
+	/*
+	 * Delay 1000 intosc. intosc is based on eosc1
+	 * Use worst case which is fatest eosc1=50MHz, delay required
+	 * is 1/50MHz * 1000 = 20us
+	 */
+	udelay(20);
+
+	/*
+	 * de-assert active low bhniotri signals,
+	 * assert active high csrdone and nfrzdrv signal
+	 */
+	reg_value = readl(&freeze_controller_base->hioctrl);
+	reg_value = (reg_value
+		| SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK)
+		& ~SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK;
+	writel(reg_value, &freeze_controller_base->hioctrl);
+
+	/*
+	 * Delay 33 intosc
+	 * Use worst case which is fatest eosc1=50MHz, delay required
+	 * is 1/50MHz * 33 = 660ns ~= 1us
+	 */
+	udelay(1);
+
+	/* de-assert active low plniotri and niotri signals */
+	reg_cfg_mask
+		= SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK
+		| SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK;
+
+	setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * de-assert active high frzreg signal
+	 */
+	clrbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK);
+
+	/*
+	 * Note: Delay for 40ns at min
+	 * de-assert active low enrnsl signal
+	 */
+	setbits_le32(&freeze_controller_base->hioctrl,
+		SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK);
+
+	/* Set global flag to indicate channel is thawed */
+	frzctrl_channel_freeze[channel_id] = FREEZE_CTRL_THAWED;
+}
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 74bceab..36a00c3 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -13,6 +13,7 @@
 #include <asm/arch/reset_manager.h>
 #include <spl.h>
 #include <asm/arch/system_manager.h>
+#include <asm/arch/freeze_controller.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -27,6 +28,10 @@
 void spl_board_init(void)
 {
 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
+	debug("Freezing all I/O banks\n");
+	/* freeze all IO banks */
+	sys_mgr_frzctrl_freeze_req();
+
 	/* configure the pin muxing through system manager */
 	sysmgr_pinmux_init();
 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
@@ -34,6 +39,10 @@
 	/* de-assert reset for peripherals and bridges based on handoff */
 	reset_deassert_peripherals_handoff();
 
+	debug("Unfreezing/Thaw all I/O banks\n");
+	/* unfreeze / thaw all IO banks */
+	sys_mgr_frzctrl_thaw_req();
+
 	/* enable console uart printing */
 	preloader_console_init();
 }
diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c
index 2bb3843..9af340e 100644
--- a/arch/arm/cpu/armv7/zynq/cpu.c
+++ b/arch/arm/cpu/armv7/zynq/cpu.c
@@ -16,23 +16,24 @@
 int arch_cpu_init(void)
 {
 	zynq_slcr_unlock();
-	/* remap DDR to zero, FILTERSTART */
-	writel(0, &scu_base->filter_start);
 
 	/* Device config APB, unlock the PCAP */
 	writel(0x757BDF0D, &devcfg_base->unlock);
 	writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
 
+#if (CONFIG_SYS_SDRAM_BASE == 0)
+	/* remap DDR to zero, FILTERSTART */
+	writel(0, &scu_base->filter_start);
+
 	/* OCM_CFG, Mask out the ROM, map ram into upper addresses */
 	writel(0x1F, &slcr_base->ocm_cfg);
 	/* FPGA_RST_CTRL, clear resets on AXI fabric ports */
 	writel(0x0, &slcr_base->fpga_rst_ctrl);
-	/* TZ_DDR_RAM, Set DDR trust zone non-secure */
-	writel(0xFFFFFFFF, &slcr_base->trust_zone);
 	/* Set urgent bits with register */
 	writel(0x0, &slcr_base->ddr_urgent_sel);
 	/* Urgent write, ports S2/S3 */
 	writel(0xC, &slcr_base->ddr_urgent);
+#endif
 
 	zynq_slcr_lock();
 
diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile
new file mode 100644
index 0000000..5b97838
--- /dev/null
+++ b/arch/arm/cpu/at91-common/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2013 Atmel Corporation
+#		     Bo Shen <voice.shen@atmel.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
+obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o
diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c
new file mode 100644
index 0000000..8136396
--- /dev/null
+++ b/arch/arm/cpu/at91-common/mpddrc.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/atmel_mpddrc.h>
+
+static inline void atmel_mpddr_op(int mode, u32 ram_address)
+{
+	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+
+	writel(mode, &mpddr->mr);
+	writel(0, ram_address);
+}
+
+int ddr2_init(const unsigned int ram_address,
+	      const struct atmel_mpddr *mpddr_value)
+{
+	struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
+	u32 ba_off, cr;
+
+	/* Compute bank offset according to NC in configuration register */
+	ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9;
+	if (!(mpddr_value->cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
+		ba_off += ((mpddr->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11;
+
+	ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
+
+	/* Program the memory device type into the memory device register */
+	writel(mpddr_value->md, &mpddr->md);
+
+	/* Program the configuration register */
+	writel(mpddr_value->cr, &mpddr->cr);
+
+	/* Program the timing register */
+	writel(mpddr_value->tpr0, &mpddr->tpr0);
+	writel(mpddr_value->tpr1, &mpddr->tpr1);
+	writel(mpddr_value->tpr2, &mpddr->tpr2);
+
+	/* Issue a NOP command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+	/* A 200 us is provided to precede any signal toggle */
+	udelay(200);
+
+	/* Issue a NOP command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address);
+
+	/* Issue an all banks precharge command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
+
+	/* Issue an extended mode register set(EMRS2) to choose operation */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x2 << ba_off));
+
+	/* Issue an extended mode register set(EMRS3) to set EMSR to 0 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x3 << ba_off));
+
+	/*
+	 * Issue an extended mode register set(EMRS1) to enable DLL and
+	 * program D.I.C (output driver impedance control)
+	 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	/* Enable DLL reset */
+	cr = readl(&mpddr->cr);
+	writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr);
+
+	/* A mode register set(MRS) cycle is issued to reset DLL */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+
+	/* Issue an all banks precharge command */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address);
+
+	/* Two auto-refresh (CBR) cycles are provided */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address);
+
+	/* Disable DLL reset */
+	cr = readl(&mpddr->cr);
+	writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr);
+
+	/* A mode register set (MRS) cycle is issued to disable DLL reset */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address);
+
+	/* Set OCD calibration in default state */
+	cr = readl(&mpddr->cr);
+	writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr);
+
+	/*
+	 * An extended mode register set (EMRS1) cycle is issued
+	 * to OCD default value
+	 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	 /* OCD calibration mode exit */
+	cr = readl(&mpddr->cr);
+	writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr);
+
+	/*
+	 * An extended mode register set (EMRS1) cycle is issued
+	 * to enable OCD exit
+	 */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD,
+		       ram_address + (0x1 << ba_off));
+
+	/* A nornal mode command is provided */
+	atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address);
+
+	/* Perform a write access to any DDR2-SDRAM address */
+	writel(0, ram_address);
+
+	/* Write the refresh rate */
+	writel(mpddr_value->rtr, &mpddr->rtr);
+
+	return 0;
+}
diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c
new file mode 100644
index 0000000..3b6c60c
--- /dev/null
+++ b/arch/arm/cpu/at91-common/phy.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * (C) Copyright 2012
+ * Markus Hubig <mhubig@imko.de>
+ * IMKO GmbH <www.imko.de>
+ *
+ * Copyright (C) 2013 DENX Software Engineering, hs@denx.de
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/sizes.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <watchdog.h>
+
+void at91_phy_reset(void)
+{
+	unsigned long erstl;
+	unsigned long start = get_timer(0);
+	unsigned long const timeout = 1000; /* 1000ms */
+	at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
+
+	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
+
+	/*
+	 * Need to reset PHY -> 500ms reset
+	 * Reset PHY by pulling the NRST line for 500ms to low. To do so
+	 * disable user reset for low level on NRST pin and poll the NRST
+	 * level in reset status register.
+	 */
+	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
+		AT91_RSTC_MR_URSTEN, &rstc->mr);
+
+	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
+
+	/* Wait for end of hardware reset */
+	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
+		/* avoid shutdown by watchdog */
+		WATCHDOG_RESET();
+		mdelay(10);
+
+		/* timeout for not getting stuck in an endless loop */
+		if (get_timer(start) >= timeout) {
+			puts("*** ERROR: Timeout waiting for PHY reset!\n");
+			break;
+		}
+	};
+
+	/* Restore NRST value */
+	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+}
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
new file mode 100644
index 0000000..37c0cc4
--- /dev/null
+++ b/arch/arm/cpu/at91-common/spl.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_wdt.h>
+#include <asm/arch/clk.h>
+#include <spl.h>
+
+static void at91_disable_wdt(void)
+{
+	struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT;
+
+	writel(AT91_WDT_MR_WDDIS, &wdt->mr);
+}
+
+void at91_plla_init(u32 pllar)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(pllar, &pmc->pllar);
+	while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY)))
+		;
+}
+
+void at91_mck_init(u32 mckr)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = readl(&pmc->mckr);
+	tmp &= ~(AT91_PMC_MCKR_PRES_MASK |
+		 AT91_PMC_MCKR_MDIV_MASK |
+		 AT91_PMC_MCKR_PLLADIV_2);
+	tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK |
+		       AT91_PMC_MCKR_MDIV_MASK |
+		       AT91_PMC_MCKR_PLLADIV_2);
+	writel(tmp, &pmc->mckr);
+
+	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))
+		;
+}
+
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	return BOOT_DEVICE_MMC1;
+#endif
+	return BOOT_DEVICE_NONE;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+#ifdef CONFIG_SYS_USE_MMC
+	case BOOT_DEVICE_MMC1:
+		return MMCSD_MODE_FAT;
+		break;
+#endif
+	case BOOT_DEVICE_NONE:
+	default:
+		hang();
+	}
+}
+
+void s_init(void)
+{
+	/* disable watchdog */
+	at91_disable_wdt();
+
+	/* PMC configuration */
+	at91_pmc_init();
+
+	at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+
+	timer_init();
+
+	board_early_init_f();
+
+	preloader_console_init();
+
+	mem_init();
+}
diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/cpu/at91-common/u-boot-spl.lds
new file mode 100644
index 0000000..038335d
--- /dev/null
+++ b/arch/arm/cpu/at91-common/u-boot-spl.lds
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *	Aneesh V <aneesh@ti.com>
+ *
+ * (C) 2013 Atmel Corporation
+ *	    Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		arch/arm/cpu/armv7/start.o	(.text*)
+		*(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+	_end = .;
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}
diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds
index c8d2e12..676ae2c 100644
--- a/arch/arm/cpu/ixp/u-boot.lds
+++ b/arch/arm/cpu/ixp/u-boot.lds
@@ -79,10 +79,13 @@
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds
index 36cc54a..4880d0f 100644
--- a/arch/arm/cpu/u-boot-spl.lds
+++ b/arch/arm/cpu/u-boot-spl.lds
@@ -51,12 +51,15 @@
 		__bss_end = .;
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
 
 #if defined(CONFIG_SPL_MAX_SIZE)
diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds
index 23bf030..9463a33 100644
--- a/arch/arm/cpu/u-boot.lds
+++ b/arch/arm/cpu/u-boot.lds
@@ -91,12 +91,14 @@
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
-	/DISCARD/ : { *(.ARM.exidx*) }
-	/DISCARD/ : { *(.gnu.linkonce.armexidx.*) }
+	.dynsym _end : { *(.dynsym) }
+	.hash : { *(.hash) }
+	.got.plt : { *(.got.plt) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index fe48b5f..2278358 100644
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -18,7 +18,6 @@
 #define VTP_CTRL_READY		(0x1 << 5)
 #define VTP_CTRL_ENABLE		(0x1 << 6)
 #define VTP_CTRL_START_EN	(0x1)
-#define PHY_DLL_LOCK_DIFF	0x0
 #define DDR_CKE_CTRL_NORMAL	0x1
 #define PHY_EN_DYN_PWRDN	(0x1 << 20)
 
@@ -29,7 +28,6 @@
 #define MT47H128M16RT25E_EMIF_TIM3		0x0000033F
 #define MT47H128M16RT25E_EMIF_SDCFG		0x41805332
 #define MT47H128M16RT25E_EMIF_SDREF		0x0000081a
-#define MT47H128M16RT25E_DLL_LOCK_DIFF		0x0
 #define MT47H128M16RT25E_RATIO			0x80
 #define MT47H128M16RT25E_INVERT_CLKOUT		0x00
 #define MT47H128M16RT25E_RD_DQS			0x12
@@ -38,7 +36,6 @@
 #define MT47H128M16RT25E_PHY_GATELVL		0x00
 #define MT47H128M16RT25E_PHY_WR_DATA		0x40
 #define MT47H128M16RT25E_PHY_FIFO_WE		0x80
-#define MT47H128M16RT25E_PHY_RANK0_DELAY		0x1
 #define MT47H128M16RT25E_IOCTRL_VALUE		0x18B
 
 /* Micron MT41J128M16JT-125 */
@@ -49,7 +46,6 @@
 #define MT41J128MJT125_EMIF_SDCFG		0x61C04AB2
 #define MT41J128MJT125_EMIF_SDREF		0x0000093B
 #define MT41J128MJT125_ZQ_CFG			0x50074BE4
-#define MT41J128MJT125_DLL_LOCK_DIFF		0x1
 #define MT41J128MJT125_RATIO			0x40
 #define MT41J128MJT125_INVERT_CLKOUT		0x1
 #define MT41J128MJT125_RD_DQS			0x3B
@@ -58,6 +54,12 @@
 #define MT41J128MJT125_PHY_FIFO_WE		0x100
 #define MT41J128MJT125_IOCTRL_VALUE		0x18B
 
+/* Micron MT41J64M16JT-125 */
+#define MT41J64MJT125_EMIF_SDCFG		0x61C04A32
+
+/* Micron MT41J256M16JT-125 */
+#define MT41J256MJT125_EMIF_SDCFG		0x61C04B32
+
 /* Micron MT41J256M8HX-15E */
 #define MT41J256M8HX15E_EMIF_READ_LATENCY	0x06
 #define MT41J256M8HX15E_EMIF_TIM1		0x0888A39B
@@ -66,7 +68,6 @@
 #define MT41J256M8HX15E_EMIF_SDCFG		0x61C04B32
 #define MT41J256M8HX15E_EMIF_SDREF		0x0000093B
 #define MT41J256M8HX15E_ZQ_CFG			0x50074BE4
-#define MT41J256M8HX15E_DLL_LOCK_DIFF		0x1
 #define MT41J256M8HX15E_RATIO			0x40
 #define MT41J256M8HX15E_INVERT_CLKOUT		0x1
 #define MT41J256M8HX15E_RD_DQS			0x3B
@@ -83,7 +84,6 @@
 #define MT41K256M16HA125E_EMIF_SDCFG		0x61C05332
 #define MT41K256M16HA125E_EMIF_SDREF		0xC30
 #define MT41K256M16HA125E_ZQ_CFG		0x50074BE4
-#define MT41K256M16HA125E_DLL_LOCK_DIFF		0x1
 #define MT41K256M16HA125E_RATIO			0x80
 #define MT41K256M16HA125E_INVERT_CLKOUT		0x0
 #define MT41K256M16HA125E_RD_DQS		0x38
@@ -100,7 +100,6 @@
 #define MT41J512M8RH125_EMIF_SDCFG		0x61C04BB2
 #define MT41J512M8RH125_EMIF_SDREF		0x0000093B
 #define MT41J512M8RH125_ZQ_CFG			0x50074BE4
-#define MT41J512M8RH125_DLL_LOCK_DIFF		0x1
 #define MT41J512M8RH125_RATIO			0x80
 #define MT41J512M8RH125_INVERT_CLKOUT		0x0
 #define MT41J512M8RH125_RD_DQS			0x3B
@@ -117,7 +116,6 @@
 #define K4B2G1646EBIH9_EMIF_SDCFG		0x61C052B2
 #define K4B2G1646EBIH9_EMIF_SDREF		0x00000C30
 #define K4B2G1646EBIH9_ZQ_CFG			0x50074BE4
-#define K4B2G1646EBIH9_DLL_LOCK_DIFF		0x1
 #define K4B2G1646EBIH9_RATIO			0x80
 #define K4B2G1646EBIH9_INVERT_CLKOUT		0x0
 #define K4B2G1646EBIH9_RD_DQS			0x35
@@ -149,18 +147,15 @@
 struct ddr_cmd_regs {
 	unsigned int resv0[7];
 	unsigned int cm0csratio;	/* offset 0x01C */
-	unsigned int resv1[2];
-	unsigned int cm0dldiff;		/* offset 0x028 */
+	unsigned int resv1[3];
 	unsigned int cm0iclkout;	/* offset 0x02C */
 	unsigned int resv2[8];
 	unsigned int cm1csratio;	/* offset 0x050 */
-	unsigned int resv3[2];
-	unsigned int cm1dldiff;		/* offset 0x05C */
+	unsigned int resv3[3];
 	unsigned int cm1iclkout;	/* offset 0x060 */
 	unsigned int resv4[8];
 	unsigned int cm2csratio;	/* offset 0x084 */
-	unsigned int resv5[2];
-	unsigned int cm2dldiff;		/* offset 0x090 */
+	unsigned int resv5[3];
 	unsigned int cm2iclkout;	/* offset 0x094 */
 	unsigned int resv6[3];
 };
@@ -197,24 +192,21 @@
 	unsigned int cm0configclk;	/* offset 0x010 */
 	unsigned int resv1[2];
 	unsigned int cm0csratio;	/* offset 0x01C */
-	unsigned int resv2[2];
-	unsigned int cm0dldiff;		/* offset 0x028 */
+	unsigned int resv2[3];
 	unsigned int cm0iclkout;	/* offset 0x02C */
 	unsigned int resv3[4];
 	unsigned int cm1config;		/* offset 0x040 */
 	unsigned int cm1configclk;	/* offset 0x044 */
 	unsigned int resv4[2];
 	unsigned int cm1csratio;	/* offset 0x050 */
-	unsigned int resv5[2];
-	unsigned int cm1dldiff;		/* offset 0x05C */
+	unsigned int resv5[3];
 	unsigned int cm1iclkout;	/* offset 0x060 */
 	unsigned int resv6[4];
 	unsigned int cm2config;		/* offset 0x074 */
 	unsigned int cm2configclk;	/* offset 0x078 */
 	unsigned int resv7[2];
 	unsigned int cm2csratio;	/* offset 0x084 */
-	unsigned int resv8[2];
-	unsigned int cm2dldiff;		/* offset 0x090 */
+	unsigned int resv8[3];
 	unsigned int cm2iclkout;	/* offset 0x094 */
 	unsigned int resv9[12];
 	unsigned int dt0rdsratio0;	/* offset 0x0C8 */
@@ -243,17 +235,14 @@
 	unsigned long cmd0csratio;
 	unsigned long cmd0csforce;
 	unsigned long cmd0csdelay;
-	unsigned long cmd0dldiff;
 	unsigned long cmd0iclkout;
 	unsigned long cmd1csratio;
 	unsigned long cmd1csforce;
 	unsigned long cmd1csdelay;
-	unsigned long cmd1dldiff;
 	unsigned long cmd1iclkout;
 	unsigned long cmd2csratio;
 	unsigned long cmd2csforce;
 	unsigned long cmd2csdelay;
-	unsigned long cmd2dldiff;
 	unsigned long cmd2iclkout;
 };
 
@@ -267,8 +256,6 @@
 	unsigned long datagiratio0;
 	unsigned long datafwsratio0;
 	unsigned long datawrsratio0;
-	unsigned long datauserank0delay;
-	unsigned long datadldiff0;
 };
 
 /**
diff --git a/arch/arm/include/asm/arch-at91/at91_common.h b/arch/arm/include/asm/arch-at91/at91_common.h
index abcb97d..59e2f43 100644
--- a/arch/arm/include/asm/arch-at91/at91_common.h
+++ b/arch/arm/include/asm/arch-at91/at91_common.h
@@ -22,5 +22,10 @@
 void at91_udp_hw_init(void);
 void at91_uhp_hw_init(void);
 void at91_lcd_hw_init(void);
+void at91_plla_init(u32 pllar);
+void at91_mck_init(u32 mckr);
+void at91_pmc_init(void);
+void mem_init(void);
+void at91_phy_reset(void);
 
 #endif /* AT91_COMMON_H */
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h
index 676f024..50464ff 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -151,37 +151,4 @@
 #define	AT91_PIO_PORTD		0x3
 #define	AT91_PIO_PORTE		0x4
 
-#ifdef CONFIG_AT91_LEGACY
-
-#define PIO_PER		0x00	/* Enable Register */
-#define PIO_PDR		0x04	/* Disable Register */
-#define PIO_PSR		0x08	/* Status Register */
-#define PIO_OER		0x10	/* Output Enable Register */
-#define PIO_ODR		0x14	/* Output Disable Register */
-#define PIO_OSR		0x18	/* Output Status Register */
-#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
-#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
-#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
-#define PIO_SODR	0x30	/* Set Output Data Register */
-#define PIO_CODR	0x34	/* Clear Output Data Register */
-#define PIO_ODSR	0x38	/* Output Data Status Register */
-#define PIO_PDSR	0x3c	/* Pin Data Status Register */
-#define PIO_IER		0x40	/* Interrupt Enable Register */
-#define PIO_IDR		0x44	/* Interrupt Disable Register */
-#define PIO_IMR		0x48	/* Interrupt Mask Register */
-#define PIO_ISR		0x4c	/* Interrupt Status Register */
-#define PIO_MDER	0x50	/* Multi-driver Enable Register */
-#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
-#define PIO_MDSR	0x58	/* Multi-driver Status Register */
-#define PIO_PUDR	0x60	/* Pull-up Disable Register */
-#define PIO_PUER	0x64	/* Pull-up Enable Register */
-#define PIO_PUSR	0x68	/* Pull-up Status Register */
-#define PIO_ASR		0x70	/* Peripheral A Select Register */
-#define PIO_BSR		0x74	/* Peripheral B Select Register */
-#define PIO_ABSR	0x78	/* AB Status Register */
-#define PIO_OWER	0xa0	/* Output Write Enable Register */
-#define PIO_OWDR	0xa4	/* Output Write Disable Register */
-#define PIO_OWSR	0xa8	/* Output Write Status Register */
-#endif
-
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pit.h b/arch/arm/include/asm/arch-at91/at91_pit.h
index d314b06..56724f1 100644
--- a/arch/arm/include/asm/arch-at91/at91_pit.h
+++ b/arch/arm/include/asm/arch-at91/at91_pit.h
@@ -25,20 +25,4 @@
 #define		AT91_PIT_MR_PIV_MASK(x)	(x & 0x000fffff)
 #define		AT91_PIT_MR_PIV(x)	(x & AT91_PIT_MR_PIV_MASK)
 
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
-#define		AT91_PIT_PITIEN		(1 << 25)		/* Timer Interrupt Enable */
-#define		AT91_PIT_PITEN		(1 << 24)		/* Timer Enabled */
-#define		AT91_PIT_PIV		(0xfffff)		/* Periodic Interval Value */
-
-#define AT91_PIT_SR		(AT91_PIT + 0x04)	/* Status Register */
-#define		AT91_PIT_PITS		(1 << 0)		/* Timer Status */
-
-#define AT91_PIT_PIVR		(AT91_PIT + 0x08)	/* Periodic Interval Value Register */
-#define AT91_PIT_PIIR		(AT91_PIT + 0x0c)	/* Periodic Interval Image Register */
-#define		AT91_PIT_PICNT		(0xfff << 20)		/* Interval Counter */
-#define		AT91_PIT_CPIV		(0xfffff)		/* Inverval Value */
-
-#endif /* CONFIG_AT91_LEGACY */
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h
index 7b36f74..4535608 100644
--- a/arch/arm/include/asm/arch-at91/at91_pmc.h
+++ b/arch/arm/include/asm/arch-at91/at91_pmc.h
@@ -14,13 +14,15 @@
 #ifndef AT91_PMC_H
 #define AT91_PMC_H
 
+#ifdef __ASSEMBLY__
+
 #define	AT91_ASM_PMC_MOR	(ATMEL_BASE_PMC + 0x20)
 #define	AT91_ASM_PMC_PLLAR	(ATMEL_BASE_PMC + 0x28)
 #define	AT91_ASM_PMC_PLLBR	(ATMEL_BASE_PMC + 0x2c)
 #define AT91_ASM_PMC_MCKR	(ATMEL_BASE_PMC + 0x30)
 #define AT91_ASM_PMC_SR		(ATMEL_BASE_PMC + 0x68)
 
-#ifndef __ASSEMBLY__
+#else
 
 #include <asm/types.h>
 
@@ -73,7 +75,11 @@
 #define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
 #define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
 #define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
+#ifdef CONFIG_SAMA5D3
+#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7F) << 18)
+#else
 #define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
+#endif
 #define AT91_PMC_PLLAR_29		0x20000000
 #define AT91_PMC_PLLBR_USBDIV_1		0x00000000
 #define AT91_PMC_PLLBR_USBDIV_2		0x10000000
@@ -124,8 +130,8 @@
 #define AT91_PMC_MCKR_MDIV_MASK		0x00000300
 #endif
 
-#define AT91_PMC_MCKR_PLLADIV_1		0x00001000
-#define AT91_PMC_MCKR_PLLADIV_2		0x00002000
+#define AT91_PMC_MCKR_PLLADIV_1		0x00000000
+#define AT91_PMC_MCKR_PLLADIV_2		0x00001000
 
 #define AT91_PMC_IXR_MOSCS		0x00000001
 #define AT91_PMC_IXR_LOCKA		0x00000002
@@ -137,13 +143,6 @@
 #define AT91_PMC_IXR_PCKRDY2		0x00000400
 #define AT91_PMC_IXR_PCKRDY3		0x00000800
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
-#define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
-
-#define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */
-#endif
-
 #define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
 #define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
 #define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
@@ -159,34 +158,18 @@
 #define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
 #define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */
-#define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */
-#define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */
-
-#define	AT91_CKGR_UCKR		(AT91_PMC + 0x1C)	/* UTMI Clock Register [SAM9RL, CAP9] */
-#endif
-
 #define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
 #define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
 #define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
 #define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI PLL Start-up Time */
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
-#endif
 #define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
 #define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
 #define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
-#endif
+
 #define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
 #define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */
-#define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */
-#endif
+
 #define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
 #define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
 #define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
@@ -198,9 +181,6 @@
 #define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
 #define		AT91_PMC_PLLA_WR_ERRATA	(1     << 29)		/* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */
-#endif
 #define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
 #define			AT91_PMC_CSS_SLOW		(0 << 0)
 #define			AT91_PMC_CSS_MAIN		(1 << 0)
@@ -228,9 +208,6 @@
 #define			AT91_PMC_PDIV_1			(0 << 12)
 #define			AT91_PMC_PDIV_2			(1 << 12)
 
-#ifdef CONFIG_AT91_LEGACY
-#define		AT91_PMC_USB			(AT91_PMC + 0x38)	/* USB Clock Register */
-#endif
 #define		AT91_PMC_USBS_USB_PLLA		(0x0)		/* USB Clock Input is PLLA */
 #define		AT91_PMC_USBS_USB_UPLL		(0x1)		/* USB Clock Input is UPLL */
 #define		AT91_PMC_USBS_USB_PLLB		(0x1)		/* USB Clock Input is PLLB, AT91SAM9N12 only */
@@ -238,13 +215,6 @@
 #define		AT91_PMC_USBDIV_8		(0x7 <<  8)	/* USB Clock divided by 8 */
 #define		AT91_PMC_USBDIV_10		(0x9 <<  8)	/* USB Clock divided by 10 */
 
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-3 Registers */
-
-#define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */
-#define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */
-#define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */
-#endif
 #define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
 #define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
 #define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
@@ -255,13 +225,6 @@
 #define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
 #define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
 #define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
-#ifdef CONFIG_AT91_LEGACY
-#define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
 
-#define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
-#endif
 #define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
-#ifdef CONFIG_AT91_LEGACY
-#define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
-#endif /* CONFIG_AT91_LEGACY */
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h
index f44cf67..b18665b 100644
--- a/arch/arm/include/asm/arch-at91/at91_spi.h
+++ b/arch/arm/include/asm/arch-at91/at91_spi.h
@@ -118,6 +118,6 @@
 
 #define AT91_SPI_PTSR		0x0124			/* PDC Transfer Status Register */
 
-#endif /* CONFIG_AT91_LEGACY */
+#endif /* CONFIG_ATMEL_LEGACY */
 
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91_wdt.h b/arch/arm/include/asm/arch-at91/at91_wdt.h
index f0f4ed1..0644bbf 100644
--- a/arch/arm/include/asm/arch-at91/at91_wdt.h
+++ b/arch/arm/include/asm/arch-at91/at91_wdt.h
@@ -40,25 +40,4 @@
 #define AT91_WDT_MR_WDDBGHLT		0x10000000
 #define AT91_WDT_MR_WDIDLEHLT		0x20000000
 
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_WDT_CR		(AT91_WDT + 0x00)	/* Watchdog Control Register */
-#define		AT91_WDT_WDRSTT		(1    << 0)		/* Restart */
-#define		AT91_WDT_KEY		(0xa5 << 24)		/* KEY Password */
-
-#define AT91_WDT_MR		(AT91_WDT + 0x04)	/* Watchdog Mode Register */
-#define		AT91_WDT_WDV		(0xfff << 0)		/* Counter Value */
-#define		AT91_WDT_WDFIEN		(1     << 12)		/* Fault Interrupt Enable */
-#define		AT91_WDT_WDRSTEN	(1     << 13)		/* Reset Processor */
-#define		AT91_WDT_WDRPROC	(1     << 14)		/* Timer Restart */
-#define		AT91_WDT_WDDIS		(1     << 15)		/* Watchdog Disable */
-#define		AT91_WDT_WDD		(0xfff << 16)		/* Delta Value */
-#define		AT91_WDT_WDDBGHLT	(1     << 28)		/* Debug Halt */
-#define		AT91_WDT_WDIDLEHLT	(1     << 29)		/* Idle Halt */
-
-#define AT91_WDT_SR		(AT91_WDT + 0x08)	/* Watchdog Status Register */
-#define		AT91_WDT_WDUNF		(1 << 0)		/* Watchdog Underflow */
-#define		AT91_WDT_WDERR		(1 << 1)		/* Watchdog Error */
-
-#endif /* CONFIG_AT91_LEGACY */
 #endif
diff --git a/arch/arm/include/asm/arch-at91/at91cap9.h b/arch/arm/include/asm/arch-at91/at91cap9.h
index 7ac5bc1..63870bc 100644
--- a/arch/arm/include/asm/arch-at91/at91cap9.h
+++ b/arch/arm/include/asm/arch-at91/at91cap9.h
@@ -55,75 +55,6 @@
 #define AT91_RSTC_BASE	0xfffffd00
 #define AT91_PIT_BASE	0xfffffd30
 
-#ifdef CONFIG_AT91_LEGACY
-
-/*
- * User Peripheral physical base addresses.
- */
-#define AT91CAP9_BASE_UDPHS		0xfff78000
-#define AT91CAP9_BASE_TCB0		0xfff7c000
-#define AT91CAP9_BASE_TC0		0xfff7c000
-#define AT91CAP9_BASE_TC1		0xfff7c040
-#define AT91CAP9_BASE_TC2		0xfff7c080
-#define AT91CAP9_BASE_MCI0		0xfff80000
-#define AT91CAP9_BASE_MCI1		0xfff84000
-#define AT91CAP9_BASE_TWI		0xfff88000
-#define AT91CAP9_BASE_US0		0xfff8c000
-#define AT91CAP9_BASE_US1		0xfff90000
-#define AT91CAP9_BASE_US2		0xfff94000
-#define AT91CAP9_BASE_SSC0		0xfff98000
-#define AT91CAP9_BASE_SSC1		0xfff9c000
-#define AT91CAP9_BASE_AC97C		0xfffa0000
-#define AT91CAP9_BASE_SPI0		0xfffa4000
-#define AT91CAP9_BASE_SPI1		0xfffa8000
-#define AT91CAP9_BASE_CAN		0xfffac000
-#define AT91CAP9_BASE_PWMC		0xfffb8000
-#define AT91CAP9_BASE_EMAC		0xfffbc000
-#define AT91CAP9_BASE_ADC		0xfffc0000
-#define AT91CAP9_BASE_ISI		0xfffc4000
-#define AT91_BASE_SYS			0xffffe200
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC	(0xffffe200 - AT91_BASE_SYS)
-#define AT91_BCRAMC	(0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC	(0xffffe600 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffeb10 - AT91_BASE_SYS)
-#define AT91_DMA	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOD	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_SCKCR	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR_REVB	(0xfffffd50 - AT91_BASE_SYS)
-#define AT91_GPBR_REVC	(0xfffffd60 - AT91_BASE_SYS)
-
-#define AT91_USART0	AT91CAP9_BASE_US0
-#define AT91_USART1	AT91CAP9_BASE_US1
-#define AT91_USART2	AT91CAP9_BASE_US2
-
-/*
- * SCKCR flags
- */
-#define AT91CAP9_SCKCR_RCEN	(1 << 0)	/* RC Oscillator Enable */
-#define AT91CAP9_SCKCR_OSC32EN	(1 << 1)	/* 32kHz Oscillator Enable */
-#define AT91CAP9_SCKCR_OSC32BYP	(1 << 2)	/* 32kHz Oscillator Bypass */
-#define AT91CAP9_SCKCR_OSCSEL	(1 << 3)	/* Slow Clock Selector */
-#define		AT91CAP9_SCKCR_OSCSEL_RC	(0 << 3)
-#define		AT91CAP9_SCKCR_OSCSEL_32	(1 << 3)
-
-#endif /* CONFIG_AT91_LEGACY */
 /*
  * Internal Memory.
  */
diff --git a/arch/arm/include/asm/arch-at91/at91sam9_smc.h b/arch/arm/include/asm/arch-at91/at91sam9_smc.h
index ec5d797..d29e98e 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9_smc.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9_smc.h
@@ -73,64 +73,4 @@
 #define AT91_SMC_MODE_PS_16		0x20000000
 #define AT91_SMC_MODE_PS_32		0x30000000
 
-#ifdef CONFIG_AT91_LEGACY
-
-#define AT91_SMC_SETUP(n)	(AT91_SMC + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
-#define		AT91_SMC_NWESETUP	(0x3f << 0)			/* NWE Setup Length */
-#define			AT91_SMC_NWESETUP_(x)	((x) << 0)
-#define		AT91_SMC_NCS_WRSETUP	(0x3f << 8)			/* NCS Setup Length in Write Access */
-#define			AT91_SMC_NCS_WRSETUP_(x)	((x) << 8)
-#define		AT91_SMC_NRDSETUP	(0x3f << 16)			/* NRD Setup Length */
-#define			AT91_SMC_NRDSETUP_(x)	((x) << 16)
-#define		AT91_SMC_NCS_RDSETUP	(0x3f << 24)			/* NCS Setup Length in Read Access */
-#define			AT91_SMC_NCS_RDSETUP_(x)	((x) << 24)
-
-#define AT91_SMC_PULSE(n)	(AT91_SMC + 0x04 + ((n)*0x10))	/* Pulse Register for CS n */
-#define		AT91_SMC_NWEPULSE	(0x7f <<  0)			/* NWE Pulse Length */
-#define			AT91_SMC_NWEPULSE_(x)	((x) << 0)
-#define		AT91_SMC_NCS_WRPULSE	(0x7f <<  8)			/* NCS Pulse Length in Write Access */
-#define			AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define		AT91_SMC_NRDPULSE	(0x7f << 16)			/* NRD Pulse Length */
-#define			AT91_SMC_NRDPULSE_(x)	((x) << 16)
-#define		AT91_SMC_NCS_RDPULSE	(0x7f << 24)			/* NCS Pulse Length in Read Access */
-#define			AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE(n)	(AT91_SMC + 0x08 + ((n)*0x10))	/* Cycle Register for CS n */
-#define		AT91_SMC_NWECYCLE	(0x1ff << 0 )			/* Total Write Cycle Length */
-#define			AT91_SMC_NWECYCLE_(x)	((x) << 0)
-#define		AT91_SMC_NRDCYCLE	(0x1ff << 16)			/* Total Read Cycle Length */
-#define			AT91_SMC_NRDCYCLE_(x)	((x) << 16)
-
-#define AT91_SMC_MODE(n)	(AT91_SMC + 0x0c + ((n)*0x10))	/* Mode Register for CS n */
-#define		AT91_SMC_READMODE	(1 <<  0)			/* Read Mode */
-#define		AT91_SMC_WRITEMODE	(1 <<  1)			/* Write Mode */
-#define		AT91_SMC_EXNWMODE	(3 <<  4)			/* NWAIT Mode */
-#define			AT91_SMC_EXNWMODE_DISABLE	(0 << 4)
-#define			AT91_SMC_EXNWMODE_FROZEN	(2 << 4)
-#define			AT91_SMC_EXNWMODE_READY		(3 << 4)
-#define		AT91_SMC_BAT		(1 <<  8)			/* Byte Access Type */
-#define			AT91_SMC_BAT_SELECT		(0 << 8)
-#define			AT91_SMC_BAT_WRITE		(1 << 8)
-#define		AT91_SMC_DBW		(3 << 12)			/* Data Bus Width */
-#define			AT91_SMC_DBW_8			(0 << 12)
-#define			AT91_SMC_DBW_16			(1 << 12)
-#define			AT91_SMC_DBW_32			(2 << 12)
-#define		AT91_SMC_TDF		(0xf << 16)			/* Data Float Time. */
-#define			AT91_SMC_TDF_(x)		((x) << 16)
-#define		AT91_SMC_TDFMODE	(1 << 20)			/* TDF Optimization - Enabled */
-#define		AT91_SMC_PMEN		(1 << 24)			/* Page Mode Enabled */
-#define		AT91_SMC_PS		(3 << 28)			/* Page Size */
-#define			AT91_SMC_PS_4			(0 << 28)
-#define			AT91_SMC_PS_8			(1 << 28)
-#define			AT91_SMC_PS_16			(2 << 28)
-#define			AT91_SMC_PS_32			(3 << 28)
-
-#if defined(AT91_SMC1)		/* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)	(AT91_SMC1 + 0x00 + ((n)*0x10))	/* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)	(AT91_SMC1 + 0x04 + ((n)*0x10))	/* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)	(AT91_SMC1 + 0x08 + ((n)*0x10))	/* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)	(AT91_SMC1 + 0x0c + ((n)*0x10))	/* Mode Register for CS n */
-#endif
-
-#endif
 #endif
diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
new file mode 100644
index 0000000..5741f6e
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ATMEL_MPDDRC_H__
+#define __ATMEL_MPDDRC_H__
+
+/*
+ * Only define the needed register in mpddr
+ * If other register needed, will add them later
+ */
+struct atmel_mpddr {
+	u32 mr;
+	u32 rtr;
+	u32 cr;
+	u32 tpr0;
+	u32 tpr1;
+	u32 tpr2;
+	u32 reserved[2];
+	u32 md;
+};
+
+int ddr2_init(const unsigned int ram_address,
+	       const struct atmel_mpddr *mpddr);
+
+/* Bit field in mode register */
+#define ATMEL_MPDDRC_MR_MODE_NORMAL_CMD		0x0
+#define ATMEL_MPDDRC_MR_MODE_NOP_CMD		0x1
+#define ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD	0x2
+#define ATMEL_MPDDRC_MR_MODE_LMR_CMD		0x3
+#define ATMEL_MPDDRC_MR_MODE_RFSH_CMD		0x4
+#define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD	0x5
+#define ATMEL_MPDDRC_MR_MODE_DEEP_CMD		0x6
+#define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD		0x7
+
+/* Bit field in configuration register */
+#define ATMEL_MPDDRC_CR_NC_MASK			0x3
+#define ATMEL_MPDDRC_CR_NC_COL_9		0x0
+#define ATMEL_MPDDRC_CR_NC_COL_10		0x1
+#define ATMEL_MPDDRC_CR_NC_COL_11		0x2
+#define ATMEL_MPDDRC_CR_NC_COL_12		0x3
+#define ATMEL_MPDDRC_CR_NR_MASK			(0x3 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_11		(0x0 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_12		(0x1 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_13		(0x2 << 2)
+#define ATMEL_MPDDRC_CR_NR_ROW_14		(0x3 << 2)
+#define ATMEL_MPDDRC_CR_CAS_MASK		(0x7 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS2		(0x2 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS3		(0x3 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS4		(0x4 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS5		(0x5 << 4)
+#define ATMEL_MPDDRC_CR_CAS_DDR_CAS6		(0x6 << 4)
+#define ATMEL_MPDDRC_CR_DLL_RESET_ENABLED	(0x1 << 7)
+#define ATMEL_MPDDRC_CR_DIC_DS			(0x1 << 8)
+#define ATMEL_MPDDRC_CR_DIS_DLL			(0x1 << 9)
+#define ATMEL_MPDDRC_CR_OCD_DEFAULT		(0x7 << 12)
+#define ATMEL_MPDDRC_CR_ENRDM_ON		(0x1 << 17)
+#define ATMEL_MPDDRC_CR_NB_8BANKS		(0x1 << 20)
+#define ATMEL_MPDDRC_CR_NDQS_DISABLED		(0x1 << 21)
+#define ATMEL_MPDDRC_CR_DECOD_INTERLEAVED	(0x1 << 22)
+#define ATMEL_MPDDRC_CR_UNAL_SUPPORTED		(0x1 << 23)
+
+/* Bit field in timing parameter 0 register */
+#define ATMEL_MPDDRC_TPR0_TRAS_OFFSET		0
+#define ATMEL_MPDDRC_TPR0_TRAS_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRCD_OFFSET		4
+#define ATMEL_MPDDRC_TPR0_TRCD_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TWR_OFFSET		8
+#define ATMEL_MPDDRC_TPR0_TWR_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRC_OFFSET		12
+#define ATMEL_MPDDRC_TPR0_TRC_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRP_OFFSET		16
+#define ATMEL_MPDDRC_TPR0_TRP_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TRRD_OFFSET		20
+#define ATMEL_MPDDRC_TPR0_TRRD_MASK		0xf
+#define ATMEL_MPDDRC_TPR0_TWTR_OFFSET		24
+#define ATMEL_MPDDRC_TPR0_TWTR_MASK		0x7
+#define ATMEL_MPDDRC_TPR0_RDC_WRRD_OFFSET	27
+#define ATMEL_MPDDRC_TPR0_RDC_WRRD_MASK		0x1
+#define ATMEL_MPDDRC_TPR0_TMRD_OFFSET		28
+#define ATMEL_MPDDRC_TPR0_TMRD_MASK		0xf
+
+/* Bit field in timing parameter 1 register */
+#define ATMEL_MPDDRC_TPR1_TRFC_OFFSET		0
+#define ATMEL_MPDDRC_TPR1_TRFC_MASK		0x7f
+#define ATMEL_MPDDRC_TPR1_TXSNR_OFFSET		8
+#define ATMEL_MPDDRC_TPR1_TXSNR_MASK		0xff
+#define ATMEL_MPDDRC_TPR1_TXSRD_OFFSET		16
+#define ATMEL_MPDDRC_TPR1_TXSRD_MASK		0xff
+#define ATMEL_MPDDRC_TPR1_TXP_OFFSET		24
+#define ATMEL_MPDDRC_TPR1_TXP_MASK		0xf
+
+/* Bit field in timing parameter 2 register */
+#define ATMEL_MPDDRC_TPR2_TXARD_OFFSET		0
+#define ATMEL_MPDDRC_TPR2_TXARD_MASK		0xf
+#define ATMEL_MPDDRC_TPR2_TXARDS_OFFSET		4
+#define ATMEL_MPDDRC_TPR2_TXARDS_MASK		0xf
+#define ATMEL_MPDDRC_TPR2_TRPA_OFFSET		8
+#define ATMEL_MPDDRC_TPR2_TRPA_MASK		0xf
+#define ATMEL_MPDDRC_TPR2_TRTP_OFFSET		12
+#define ATMEL_MPDDRC_TPR2_TRTP_MASK		0x7
+#define ATMEL_MPDDRC_TPR2_TFAW_OFFSET		16
+#define ATMEL_MPDDRC_TPR2_TFAW_MASK		0xf
+
+/* Bit field in Memory Device Register */
+#define ATMEL_MPDDRC_MD_LPDDR_SDRAM	0x3
+#define ATMEL_MPDDRC_MD_DDR2_SDRAM	0x6
+#define ATMEL_MPDDRC_MD_DBW_MASK	(0x1 << 4)
+#define ATMEL_MPDDRC_MD_DBW_32_BITS	(0x0 << 4)
+#define ATMEL_MPDDRC_MD_DBW_16_BITS	(0x1 << 4)
+
+#endif
diff --git a/arch/arm/include/asm/arch-at91/gpio.h b/arch/arm/include/asm/arch-at91/gpio.h
index 0700427..ff6142b 100644
--- a/arch/arm/include/asm/arch-at91/gpio.h
+++ b/arch/arm/include/asm/arch-at91/gpio.h
@@ -16,7 +16,7 @@
 
 #ifdef CONFIG_ATMEL_LEGACY
 
-#define PIN_BASE		32
+#define PIN_BASE		0
 
 #define MAX_GPIO_BANKS		5
 
@@ -231,4 +231,26 @@
 #define at91_set_gpio_value(x, y)	at91_set_pio_value(x, y)
 #define at91_get_gpio_value(x)		at91_get_pio_value(x)
 #endif
-#endif
+
+#define GPIO_PIOA_BASE  (0)
+#define GPIO_PIOB_BASE  (GPIO_PIOA_BASE + 32)
+#define GPIO_PIOC_BASE  (GPIO_PIOB_BASE + 32)
+#define GPIO_PIOD_BASE  (GPIO_PIOC_BASE + 32)
+#define GPIO_PIOE_BASE  (GPIO_PIOD_BASE + 32)
+#define GPIO_PIN_PA(x)  (GPIO_PIOA_BASE + (x))
+#define GPIO_PIN_PB(x)  (GPIO_PIOB_BASE + (x))
+#define GPIO_PIN_PC(x)  (GPIO_PIOC_BASE + (x))
+#define GPIO_PIN_PD(x)  (GPIO_PIOD_BASE + (x))
+#define GPIO_PIN_PE(x)  (GPIO_PIOE_BASE + (x))
+
+static inline unsigned at91_gpio_to_port(unsigned gpio)
+{
+	return gpio / 32;
+}
+
+static inline unsigned at91_gpio_to_pin(unsigned gpio)
+{
+	return gpio % 32;
+}
+
+#endif /* __ASM_ARCH_AT91_GPIO_H */
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h b/arch/arm/include/asm/arch-at91/sama5d3.h
index 123a627..6d936f4 100644
--- a/arch/arm/include/asm/arch-at91/sama5d3.h
+++ b/arch/arm/include/asm/arch-at91/sama5d3.h
@@ -79,6 +79,7 @@
 #define ARCH_EXID_SAMA5D33	0x00414300
 #define ARCH_EXID_SAMA5D34	0x00414301
 #define ARCH_EXID_SAMA5D35	0x00584300
+#define ARCH_EXID_SAMA5D36	0x00004301
 
 #define cpu_is_sama5d3()	(get_chip_id() == ARCH_ID_SAMA5D3)
 #define cpu_is_sama5d31()	(cpu_is_sama5d3() && \
@@ -89,6 +90,8 @@
 		(get_extension_chip_id() == ARCH_EXID_SAMA5D34))
 #define cpu_is_sama5d35()	(cpu_is_sama5d3() && \
 		(get_extension_chip_id() == ARCH_EXID_SAMA5D35))
+#define cpu_is_sama5d36()	(cpu_is_sama5d3() && \
+		(get_extension_chip_id() == ARCH_EXID_SAMA5D36))
 
 /*
  * User Peripherals physical base addresses.
diff --git a/arch/arm/include/asm/arch-at91/spl.h b/arch/arm/include/asm/arch-at91/spl.h
new file mode 100644
index 0000000..68c5349
--- /dev/null
+++ b/arch/arm/include/asm/arch-at91/spl.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2013 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_ASM_ARCH_SPL_H_
+#define	_ASM_ARCH_SPL_H_
+
+enum {
+	BOOT_DEVICE_NONE,
+#ifdef CONFIG_SYS_USE_MMC
+	BOOT_DEVICE_MMC1,
+	BOOT_DEVICE_MMC2,
+	BOOT_DEVICE_MMC2_2,
+#endif
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h
index 7aaf4bf..27b1844 100644
--- a/arch/arm/include/asm/arch-davinci/hardware.h
+++ b/arch/arm/include/asm/arch-davinci/hardware.h
@@ -478,8 +478,9 @@
 	dv_reg	rsvd[13];
 	dv_reg	kick0;
 	dv_reg	kick1;
-	dv_reg	rsvd1[53];
+	dv_reg	rsvd1[52];
 	dv_reg	mstpri[3];
+	dv_reg  rsvd2;
 	dv_reg	pinmux[20];
 	dv_reg	suspsrc;
 	dv_reg	chipsig;
diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h
index d1c5d4f..09d739d 100644
--- a/arch/arm/include/asm/arch-exynos/dwmmc.h
+++ b/arch/arm/include/asm/arch-exynos/dwmmc.h
@@ -6,10 +6,6 @@
  */
 
 #define DWMCI_CLKSEL		0x09C
-#define DWMCI_SHIFT_0		0x0
-#define DWMCI_SHIFT_1		0x1
-#define DWMCI_SHIFT_2		0x2
-#define DWMCI_SHIFT_3		0x3
 #define DWMCI_SET_SAMPLE_CLK(x)	(x)
 #define DWMCI_SET_DRV_CLK(x)	((x) << 16)
 #define DWMCI_SET_DIV_RATIO(x)	((x) << 24)
diff --git a/arch/arm/include/asm/arch-exynos/mmc.h b/arch/arm/include/asm/arch-exynos/mmc.h
index 98312d1..98d6530 100644
--- a/arch/arm/include/asm/arch-exynos/mmc.h
+++ b/arch/arm/include/asm/arch-exynos/mmc.h
@@ -55,7 +55,7 @@
 
 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
-static inline unsigned int s5p_mmc_init(int index, int bus_width)
+static inline int s5p_mmc_init(int index, int bus_width)
 {
 	unsigned int base = samsung_get_base_mmc() +
 				(S5P_MMC_DEV_OFFSET * index);
diff --git a/arch/arm/include/asm/arch-exynos/power.h b/arch/arm/include/asm/arch-exynos/power.h
index 8db18c5..2bfee18 100644
--- a/arch/arm/include/asm/arch-exynos/power.h
+++ b/arch/arm/include/asm/arch-exynos/power.h
@@ -16,7 +16,7 @@
 	unsigned int	gnss_rtc_out_ctrl;
 	unsigned char	res2[0x1ec];
 	unsigned int	system_power_down_ctrl;
-	unsigned char	res3[0x1];
+	unsigned int	res3;
 	unsigned int	system_power_down_option;
 	unsigned char	res4[0x1f4];
 	unsigned int	swreset;
diff --git a/arch/arm/include/asm/arch-exynos/spi.h b/arch/arm/include/asm/arch-exynos/spi.h
index 147c1a7..0ba931b 100644
--- a/arch/arm/include/asm/arch-exynos/spi.h
+++ b/arch/arm/include/asm/arch-exynos/spi.h
@@ -30,6 +30,7 @@
 #define EXYNOS_SPI_MAX_FREQ	50000000
 
 #define SPI_TIMEOUT_MS		10
+#define SF_READ_DATA_CMD	0x3
 
 /* SPI_CHCFG */
 #define SPI_CH_HS_EN		(1 << 6)
diff --git a/arch/arm/include/asm/arch-omap3/clock.h b/arch/arm/include/asm/arch-omap3/clock.h
index be669c1..1912cc9 100644
--- a/arch/arm/include/asm/arch-omap3/clock.h
+++ b/arch/arm/include/asm/arch-omap3/clock.h
@@ -27,8 +27,6 @@
 #define ICK_DSS_ON	0x00000001
 #define FCK_CAM_ON	0x00000001
 #define ICK_CAM_ON	0x00000001
-#define FCK_PER_ON	0x0003ffff
-#define ICK_PER_ON	0x0003ffff
 
 /* Used to index into DPLL parameter tables */
 typedef struct {
diff --git a/arch/arm/include/asm/arch-omap3/omap3.h b/arch/arm/include/asm/arch-omap3/omap3.h
index 7fb549a..65a5995 100644
--- a/arch/arm/include/asm/arch-omap3/omap3.h
+++ b/arch/arm/include/asm/arch-omap3/omap3.h
@@ -55,6 +55,7 @@
 #define OMAP34XX_UART1			(OMAP34XX_L4_IO_BASE + 0x6a000)
 #define OMAP34XX_UART2			(OMAP34XX_L4_IO_BASE + 0x6c000)
 #define OMAP34XX_UART3			(OMAP34XX_L4_PER + 0x20000)
+#define OMAP34XX_UART4			(OMAP34XX_L4_PER + 0x42000)
 
 /* General Purpose Timers */
 #define OMAP34XX_GPT1			0x48318000
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 39c5316..ce8217f 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -16,6 +16,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+extern const struct emif_regs emif_regs_elpida_200_mhz_2cs;
+extern const struct emif_regs emif_regs_elpida_380_mhz_1cs;
+extern const struct emif_regs emif_regs_elpida_400_mhz_1cs;
+extern const struct emif_regs emif_regs_elpida_400_mhz_2cs;
 struct omap_sysinfo {
 	char *board_string;
 };
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 8869b50..2dfe4ef 100644
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -137,6 +137,9 @@
 #define HSMMC_CLKCTRL_CLKSEL_MASK		(1 << 24)
 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK		(1 << 25)
 
+/* CM_L3INIT_SATA_CLKCTRL */
+#define SATA_CLKCTRL_OPTFCLKEN_MASK		(1 << 8)
+
 /* CM_WKUP_GPTIMER1_CLKCTRL */
 #define GPTIMER1_CLKCTRL_CLKSEL_MASK		(1 << 24)
 
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 3c2306f..590235b 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -64,6 +64,9 @@
 /* QSPI */
 #define QSPI_BASE		0x4B300000
 
+/* SATA */
+#define DWC_AHSATA_BASE		0x4A140000
+
 /*
  * Hardware Register Details
  */
@@ -239,6 +242,7 @@
 	u32 ctrl_ddrio_1;
 	u32 ctrl_ddrio_2;
 	u32 ctrl_emif_sdram_config_ext;
+	u32 ctrl_emif_sdram_config_ext_final;
 	u32 ctrl_ddr_ctrl_ext_0;
 };
 
diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h
new file mode 100644
index 0000000..2ca8947
--- /dev/null
+++ b/arch/arm/include/asm/arch-omap5/sata.h
@@ -0,0 +1,48 @@
+/*
+ * SATA Wrapper Register map
+ *
+ * (C) Copyright 2013
+ * Texas Instruments, <www.ti.com>
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef _TI_SATA_H
+#define _TI_SATA_H
+
+/* SATA Wrapper module */
+#define TI_SATA_WRAPPER_BASE		(OMAP54XX_L4_CORE_BASE + 0x141100)
+/* SATA PHY Module */
+#define TI_SATA_PLLCTRL_BASE		(OMAP54XX_L4_CORE_BASE + 0x96800)
+
+/* SATA Wrapper register offsets */
+#define TI_SATA_SYSCONFIG			0x00
+#define TI_SATA_CDRLOCK				0x04
+
+/* Register Set */
+#define TI_SATA_SYSCONFIG_OVERRIDE0		(1 << 16)
+#define TI_SATA_SYSCONFIG_STANDBY_MASK		(0x3 << 4)
+#define TI_SATA_SYSCONFIG_IDLE_MASK		(0x3 << 2)
+
+/* Standby modes */
+#define TI_SATA_STANDBY_FORCE			0x0
+#define TI_SATA_STANDBY_NO			(0x1 << 4)
+#define TI_SATA_STANDBY_SMART_WAKE		(0x3 << 4)
+#define TI_SATA_STANDBY_SMART			(0x2 << 4)
+
+/* Idle modes */
+#define TI_SATA_IDLE_FORCE			0x0
+#define TI_SATA_IDLE_NO				(0x1 << 2)
+#define TI_SATA_IDLE_SMART_WAKE			(0x3 << 2)
+#define TI_SATA_IDLE_SMART			(0x2 << 2)
+
+#ifdef CONFIG_SCSI_AHCI_PLAT
+int omap_sata_init(void);
+#else
+static inline int omap_sata_init(void)
+{
+	return 0;
+}
+#endif /* CONFIG_SCSI_AHCI_PLAT */
+
+#endif /* _TI_SATA_H */
diff --git a/arch/arm/include/asm/arch-rmobile/gpio.h b/arch/arm/include/asm/arch-rmobile/gpio.h
index 6b5e4ed..560e9f4 100644
--- a/arch/arm/include/asm/arch-rmobile/gpio.h
+++ b/arch/arm/include/asm/arch-rmobile/gpio.h
@@ -7,6 +7,12 @@
 #elif defined(CONFIG_R8A7740)
 #include "r8a7740-gpio.h"
 void r8a7740_pinmux_init(void);
+#elif defined(CONFIG_R8A7790)
+#include "r8a7790-gpio.h"
+void r8a7790_pinmux_init(void);
+#elif defined(CONFIG_R8A7791)
+#include "r8a7791-gpio.h"
+void r8a7791_pinmux_init(void);
 #endif
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
new file mode 100644
index 0000000..444e361
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790-gpio.h
@@ -0,0 +1,387 @@
+#ifndef __ASM_R8A7790_H__
+#define __ASM_R8A7790_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+	GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
+	GPIO_GP_1_28, GPIO_GP_1_29,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+	GPIO_GP_2_28, GPIO_GP_2_29,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+	GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
+
+	GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC_VBUS,
+	GPIO_FN_USB2_PWEN, GPIO_FN_USB2_OVC, GPIO_FN_AVS1, GPIO_FN_AVS2,
+	GPIO_FN_DU_DOTCLKIN0, GPIO_FN_DU_DOTCLKIN2,
+
+	/* IPSR0 */
+	GPIO_FN_D1, GPIO_FN_MSIOF3_SYNC_B, GPIO_FN_VI3_DATA1, GPIO_FN_VI0_G5,
+	GPIO_FN_VI0_G5_B, GPIO_FN_D2, GPIO_FN_MSIOF3_RXD_B, GPIO_FN_VI3_DATA2,
+	GPIO_FN_VI0_G6, GPIO_FN_VI0_G6_B, GPIO_FN_D3, GPIO_FN_MSIOF3_TXD_B,
+	GPIO_FN_VI3_DATA3, GPIO_FN_VI0_G7, GPIO_FN_VI0_G7_B, GPIO_FN_D4,
+	GPIO_FN_SCIFB1_RXD_F, GPIO_FN_SCIFB0_RXD_C, GPIO_FN_VI3_DATA4,
+	GPIO_FN_VI0_R0, GPIO_FN_VI0_R0_B, GPIO_FN_RX0_B, GPIO_FN_D5,
+	GPIO_FN_SCIFB1_TXD_F, GPIO_FN_SCIFB0_TXD_C, GPIO_FN_VI3_DATA5,
+	GPIO_FN_VI0_R1, GPIO_FN_VI0_R1_B, GPIO_FN_TX0_B, GPIO_FN_D6,
+	GPIO_FN_SCL2_C, GPIO_FN_VI3_DATA6, GPIO_FN_VI0_R2, GPIO_FN_VI0_R2_B,
+	GPIO_FN_SCL2_CIS_C, GPIO_FN_D7, GPIO_FN_AD_DI_B, GPIO_FN_SDA2_C,
+	GPIO_FN_VI3_DATA7, GPIO_FN_VI0_R3, GPIO_FN_VI0_R3_B, GPIO_FN_SDA2_CIS_C,
+	GPIO_FN_D8, GPIO_FN_SCIFA1_SCK_C, GPIO_FN_AVB_TXD0, GPIO_FN_MII_TXD0,
+	GPIO_FN_VI0_G0, GPIO_FN_VI0_G0_B, GPIO_FN_VI2_DATA0_VI2_B0,
+
+	/* IPSR1 */
+	GPIO_FN_D9, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_AVB_TXD1, GPIO_FN_MII_TXD1,
+	GPIO_FN_VI0_G1, GPIO_FN_VI0_G1_B, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_D10,
+	GPIO_FN_SCIFA1_TXD_C, GPIO_FN_AVB_TXD2, GPIO_FN_MII_TXD2,
+	GPIO_FN_VI0_G2, GPIO_FN_VI0_G2_B, GPIO_FN_VI2_DATA2_VI2_B2, GPIO_FN_D11,
+	GPIO_FN_SCIFA1_CTS_N_C, GPIO_FN_AVB_TXD3, GPIO_FN_MII_TXD3,
+	GPIO_FN_VI0_G3, GPIO_FN_VI0_G3_B, GPIO_FN_VI2_DATA3_VI2_B3,
+	GPIO_FN_D12, GPIO_FN_SCIFA1_RTS_N_C, GPIO_FN_AVB_TXD4,
+	GPIO_FN_VI0_HSYNC_N, GPIO_FN_VI0_HSYNC_N_B, GPIO_FN_VI2_DATA4_VI2_B4,
+	GPIO_FN_D13, GPIO_FN_AVB_TXD5, GPIO_FN_VI0_VSYNC_N,
+	GPIO_FN_VI0_VSYNC_N_B, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_D14,
+	GPIO_FN_SCIFB1_RXD_C, GPIO_FN_AVB_TXD6, GPIO_FN_RX1_B,
+	GPIO_FN_VI0_CLKENB, GPIO_FN_VI0_CLKENB_B, GPIO_FN_VI2_DATA6_VI2_B6,
+	GPIO_FN_D15, GPIO_FN_SCIFB1_TXD_C, GPIO_FN_AVB_TXD7, GPIO_FN_TX1_B,
+	GPIO_FN_VI0_FIELD, GPIO_FN_VI0_FIELD_B, GPIO_FN_VI2_DATA7_VI2_B7,
+	GPIO_FN_A0, GPIO_FN_PWM3, GPIO_FN_A1, GPIO_FN_PWM4,
+
+	/* IPSR2 */
+	GPIO_FN_A2, GPIO_FN_PWM5, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_A3,
+	GPIO_FN_PWM6, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF1_TXD_B,
+	GPIO_FN_TPU0TO0, GPIO_FN_A5, GPIO_FN_SCIFA1_TXD_B, GPIO_FN_TPU0TO1,
+	GPIO_FN_A6, GPIO_FN_SCIFA1_RTS_N_B, GPIO_FN_TPU0TO2, GPIO_FN_A7,
+	GPIO_FN_SCIFA1_SCK_B, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_TPU0TO3,
+	GPIO_FN_A8, GPIO_FN_SCIFA1_RXD_B, GPIO_FN_SSI_SCK5_B, GPIO_FN_VI0_R4,
+	GPIO_FN_VI0_R4_B, GPIO_FN_SCIFB2_RXD_C, GPIO_FN_VI2_DATA0_VI2_B0_B,
+	GPIO_FN_A9, GPIO_FN_SCIFA1_CTS_N_B, GPIO_FN_SSI_WS5_B, GPIO_FN_VI0_R5,
+	GPIO_FN_VI0_R5_B, GPIO_FN_SCIFB2_TXD_C, GPIO_FN_VI2_DATA1_VI2_B1_B,
+	GPIO_FN_A10, GPIO_FN_SSI_SDATA5_B, GPIO_FN_MSIOF2_SYNC, GPIO_FN_VI0_R6,
+	GPIO_FN_VI0_R6_B, GPIO_FN_VI2_DATA2_VI2_B2_B,
+
+	/* IPSR3 */
+	GPIO_FN_A11, GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_MSIOF2_SCK, GPIO_FN_VI1_R0,
+	GPIO_FN_VI1_R0_B, GPIO_FN_VI2_G0, GPIO_FN_VI2_DATA3_VI2_B3_B,
+	GPIO_FN_A12, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_MSIOF2_TXD, GPIO_FN_VI1_R1,
+	GPIO_FN_VI1_R1_B, GPIO_FN_VI2_G1, GPIO_FN_VI2_DATA4_VI2_B4_B,
+	GPIO_FN_A13, GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_EX_WAIT2,
+	GPIO_FN_MSIOF2_RXD, GPIO_FN_VI1_R2, GPIO_FN_VI1_R2_B, GPIO_FN_VI2_G2,
+	GPIO_FN_VI2_DATA5_VI2_B5_B, GPIO_FN_A14, GPIO_FN_SCIFB2_TXD_B,
+	GPIO_FN_ATACS11_N, GPIO_FN_MSIOF2_SS1, GPIO_FN_A15,
+	GPIO_FN_SCIFB2_SCK_B, GPIO_FN_ATARD1_N, GPIO_FN_MSIOF2_SS2, GPIO_FN_A16,
+	GPIO_FN_ATAWR1_N, GPIO_FN_A17, GPIO_FN_AD_DO_B, GPIO_FN_ATADIR1_N,
+	GPIO_FN_A18, GPIO_FN_AD_CLK_B, GPIO_FN_ATAG1_N, GPIO_FN_A19,
+	GPIO_FN_AD_NCS_N_B, GPIO_FN_ATACS01_N, GPIO_FN_EX_WAIT0_B, GPIO_FN_A20,
+	GPIO_FN_SPCLK, GPIO_FN_VI1_R3, GPIO_FN_VI1_R3_B, GPIO_FN_VI2_G4,
+
+	/* IPSR4 */
+	GPIO_FN_A21, GPIO_FN_MOSI_IO0, GPIO_FN_VI1_R4, GPIO_FN_VI1_R4_B,
+	GPIO_FN_VI2_G5, GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_VI1_R5,
+	GPIO_FN_VI1_R5_B, GPIO_FN_VI2_G6, GPIO_FN_A23, GPIO_FN_IO2,
+	GPIO_FN_VI1_G7, GPIO_FN_VI1_G7_B, GPIO_FN_VI2_G7, GPIO_FN_A24,
+	GPIO_FN_IO3, GPIO_FN_VI1_R7, GPIO_FN_VI1_R7_B, GPIO_FN_VI2_CLKENB,
+	GPIO_FN_VI2_CLKENB_B, GPIO_FN_A25, GPIO_FN_SSL, GPIO_FN_VI1_G6,
+	GPIO_FN_VI1_G6_B, GPIO_FN_VI2_FIELD, GPIO_FN_VI2_FIELD_B, GPIO_FN_CS0_N,
+	GPIO_FN_VI1_R6, GPIO_FN_VI1_R6_B, GPIO_FN_VI2_G3, GPIO_FN_MSIOF0_SS2_B,
+	GPIO_FN_CS1_N_A26, GPIO_FN_SPEEDIN, GPIO_FN_VI0_R7, GPIO_FN_VI0_R7_B,
+	GPIO_FN_VI2_CLK, GPIO_FN_VI2_CLK_B, GPIO_FN_EX_CS0_N, GPIO_FN_HRX1_B,
+	GPIO_FN_VI1_G5, GPIO_FN_VI1_G5_B, GPIO_FN_VI2_R0, GPIO_FN_HTX0_B,
+	GPIO_FN_MSIOF0_SS1_B, GPIO_FN_EX_CS1_N, GPIO_FN_GPS_CLK,
+	GPIO_FN_HCTS1_N_B, GPIO_FN_VI1_FIELD, GPIO_FN_VI1_FIELD_B,
+	GPIO_FN_VI2_R1, GPIO_FN_EX_CS2_N, GPIO_FN_GPS_SIGN, GPIO_FN_HRTS1_N_B,
+	GPIO_FN_VI3_CLKENB, GPIO_FN_VI1_G0, GPIO_FN_VI1_G0_B, GPIO_FN_VI2_R2,
+
+	/* IPSR5 */
+	GPIO_FN_EX_CS3_N, GPIO_FN_GPS_MAG, GPIO_FN_VI3_FIELD, GPIO_FN_VI1_G1,
+	GPIO_FN_VI1_G1_B, GPIO_FN_VI2_R3, GPIO_FN_EX_CS4_N,
+	GPIO_FN_MSIOF1_SCK_B, GPIO_FN_VI3_HSYNC_N,
+	GPIO_FN_VI2_HSYNC_N, GPIO_FN_SCL1, GPIO_FN_VI2_HSYNC_N_B,
+	GPIO_FN_INTC_EN0_N, GPIO_FN_SCL1_CIS, GPIO_FN_EX_CS5_N, GPIO_FN_CAN0_RX,
+	GPIO_FN_MSIOF1_RXD_B, GPIO_FN_VI3_VSYNC_N, GPIO_FN_VI1_G2,
+	GPIO_FN_VI1_G2_B, GPIO_FN_VI2_R4, GPIO_FN_SDA1, GPIO_FN_INTC_EN1_N,
+	GPIO_FN_SDA1_CIS, GPIO_FN_BS_N, GPIO_FN_IETX, GPIO_FN_HTX1_B,
+	GPIO_FN_CAN1_TX, GPIO_FN_DRACK0, GPIO_FN_IETX_C, GPIO_FN_RD_N,
+	GPIO_FN_CAN0_TX, GPIO_FN_SCIFA0_SCK_B, GPIO_FN_RD_WR_N, GPIO_FN_VI1_G3,
+	GPIO_FN_VI1_G3_B, GPIO_FN_VI2_R5, GPIO_FN_SCIFA0_RXD_B,
+	GPIO_FN_INTC_IRQ4_N, GPIO_FN_WE0_N, GPIO_FN_IECLK, GPIO_FN_CAN_CLK,
+	GPIO_FN_VI2_VSYNC_N, GPIO_FN_SCIFA0_TXD_B, GPIO_FN_VI2_VSYNC_N_B,
+	GPIO_FN_WE1_N, GPIO_FN_IERX, GPIO_FN_CAN1_RX, GPIO_FN_VI1_G4,
+	GPIO_FN_VI1_G4_B, GPIO_FN_VI2_R6, GPIO_FN_SCIFA0_CTS_N_B,
+	GPIO_FN_IERX_C, GPIO_FN_EX_WAIT0, GPIO_FN_IRQ3, GPIO_FN_INTC_IRQ3_N,
+	GPIO_FN_VI3_CLK, GPIO_FN_SCIFA0_RTS_N_B, GPIO_FN_HRX0_B,
+	GPIO_FN_MSIOF0_SCK_B, GPIO_FN_DREQ0_N, GPIO_FN_VI1_HSYNC_N,
+	GPIO_FN_VI1_HSYNC_N_B, GPIO_FN_VI2_R7, GPIO_FN_SSI_SCK78_C,
+	GPIO_FN_SSI_WS78_B,
+
+	/* IPSR6 */
+	GPIO_FN_DACK0, GPIO_FN_IRQ0, GPIO_FN_INTC_IRQ0_N, GPIO_FN_SSI_SCK6_B,
+	GPIO_FN_VI1_VSYNC_N, GPIO_FN_VI1_VSYNC_N_B, GPIO_FN_SSI_WS78_C,
+	GPIO_FN_DREQ1_N, GPIO_FN_VI1_CLKENB, GPIO_FN_VI1_CLKENB_B,
+	GPIO_FN_SSI_SDATA7_C, GPIO_FN_SSI_SCK78_B, GPIO_FN_DACK1, GPIO_FN_IRQ1,
+	GPIO_FN_INTC_IRQ1_N, GPIO_FN_SSI_WS6_B, GPIO_FN_SSI_SDATA8_C,
+	GPIO_FN_DREQ2_N, GPIO_FN_HSCK1_B, GPIO_FN_HCTS0_N_B,
+	GPIO_FN_MSIOF0_TXD_B, GPIO_FN_DACK2, GPIO_FN_IRQ2, GPIO_FN_INTC_IRQ2_N,
+	GPIO_FN_SSI_SDATA6_B, GPIO_FN_HRTS0_N_B, GPIO_FN_MSIOF0_RXD_B,
+	GPIO_FN_ETH_CRS_DV, GPIO_FN_RMII_CRS_DV, GPIO_FN_STP_ISCLK_0_B,
+	GPIO_FN_TS_SDEN0_D, GPIO_FN_GLO_Q0_C, GPIO_FN_SCL2_E,
+	GPIO_FN_SCL2_CIS_E, GPIO_FN_ETH_RX_ER, GPIO_FN_RMII_RX_ER,
+	GPIO_FN_STP_ISD_0_B, GPIO_FN_TS_SPSYNC0_D, GPIO_FN_GLO_Q1_C,
+	GPIO_FN_SDA2_E, GPIO_FN_SDA2_CIS_E, GPIO_FN_ETH_RXD0, GPIO_FN_RMII_RXD0,
+	GPIO_FN_STP_ISEN_0_B, GPIO_FN_TS_SDAT0_D, GPIO_FN_GLO_I0_C,
+	GPIO_FN_SCIFB1_SCK_G, GPIO_FN_SCK1_E, GPIO_FN_ETH_RXD1,
+	GPIO_FN_RMII_RXD1, GPIO_FN_HRX0_E, GPIO_FN_STP_ISSYNC_0_B,
+	GPIO_FN_TS_SCK0_D, GPIO_FN_GLO_I1_C, GPIO_FN_SCIFB1_RXD_G,
+	GPIO_FN_RX1_E, GPIO_FN_ETH_LINK, GPIO_FN_RMII_LINK, GPIO_FN_HTX0_E,
+	GPIO_FN_STP_IVCXO27_0_B, GPIO_FN_SCIFB1_TXD_G, GPIO_FN_TX1_E,
+	GPIO_FN_ETH_REF_CLK, GPIO_FN_RMII_REF_CLK, GPIO_FN_HCTS0_N_E,
+	GPIO_FN_STP_IVCXO27_1_B, GPIO_FN_HRX0_F,
+
+	/* IPSR7 */
+	GPIO_FN_ETH_MDIO, GPIO_FN_RMII_MDIO, GPIO_FN_HRTS0_N_E,
+	GPIO_FN_SIM0_D_C, GPIO_FN_HCTS0_N_F, GPIO_FN_ETH_TXD1,
+	GPIO_FN_RMII_TXD1, GPIO_FN_HTX0_F, GPIO_FN_BPFCLK_G, GPIO_FN_RDS_CLK_F,
+	GPIO_FN_ETH_TX_EN, GPIO_FN_RMII_TX_EN, GPIO_FN_SIM0_CLK_C,
+	GPIO_FN_HRTS0_N_F, GPIO_FN_ETH_MAGIC, GPIO_FN_RMII_MAGIC,
+	GPIO_FN_SIM0_RST_C, GPIO_FN_ETH_TXD0, GPIO_FN_RMII_TXD0,
+	GPIO_FN_STP_ISCLK_1_B, GPIO_FN_TS_SDEN1_C, GPIO_FN_GLO_SCLK_C,
+	GPIO_FN_ETH_MDC, GPIO_FN_RMII_MDC, GPIO_FN_STP_ISD_1_B,
+	GPIO_FN_TS_SPSYNC1_C, GPIO_FN_GLO_SDATA_C, GPIO_FN_PWM0,
+	GPIO_FN_SCIFA2_SCK_C, GPIO_FN_STP_ISEN_1_B, GPIO_FN_TS_SDAT1_C,
+	GPIO_FN_GLO_SS_C, GPIO_FN_PWM1, GPIO_FN_SCIFA2_TXD_C,
+	GPIO_FN_STP_ISSYNC_1_B, GPIO_FN_TS_SCK1_C, GPIO_FN_GLO_RFON_C,
+	GPIO_FN_PCMOE_N, GPIO_FN_PWM2, GPIO_FN_PWMFSW0, GPIO_FN_SCIFA2_RXD_C,
+	GPIO_FN_PCMWE_N, GPIO_FN_IECLK_C, GPIO_FN_DU1_DOTCLKIN,
+	GPIO_FN_AUDIO_CLKC, GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_VI0_CLK,
+	GPIO_FN_ATACS00_N, GPIO_FN_AVB_RXD1, GPIO_FN_MII_RXD1,
+	GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_ATACS10_N, GPIO_FN_AVB_RXD2,
+	GPIO_FN_MII_RXD2,
+
+	/* IPSR8 */
+	GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_ATARD0_N, GPIO_FN_AVB_RXD3,
+	GPIO_FN_MII_RXD3, GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_ATAWR0_N,
+	GPIO_FN_AVB_RXD4, GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_ATADIR0_N,
+	GPIO_FN_AVB_RXD5, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_ATAG0_N,
+	GPIO_FN_AVB_RXD6, GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_EX_WAIT1,
+	GPIO_FN_AVB_RXD7, GPIO_FN_VI0_DATA6_VI0_B6, GPIO_FN_AVB_RX_ER,
+	GPIO_FN_MII_RX_ER, GPIO_FN_VI0_DATA7_VI0_B7, GPIO_FN_AVB_RX_CLK,
+	GPIO_FN_MII_RX_CLK, GPIO_FN_VI1_CLK, GPIO_FN_AVB_RX_DV,
+	GPIO_FN_MII_RX_DV, GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SCIFA1_SCK_D,
+	GPIO_FN_AVB_CRS, GPIO_FN_MII_CRS, GPIO_FN_VI1_DATA1_VI1_B1,
+	GPIO_FN_SCIFA1_RXD_D, GPIO_FN_AVB_MDC, GPIO_FN_MII_MDC,
+	GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SCIFA1_TXD_D, GPIO_FN_AVB_MDIO,
+	GPIO_FN_MII_MDIO, GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SCIFA1_CTS_N_D,
+	GPIO_FN_AVB_GTX_CLK, GPIO_FN_VI1_DATA4_VI1_B4, GPIO_FN_SCIFA1_RTS_N_D,
+	GPIO_FN_AVB_MAGIC, GPIO_FN_MII_MAGIC, GPIO_FN_VI1_DATA5_VI1_B5,
+	GPIO_FN_AVB_PHY_INT, GPIO_FN_VI1_DATA6_VI1_B6, GPIO_FN_AVB_GTXREFCLK,
+	GPIO_FN_SD0_CLK, GPIO_FN_VI1_DATA0_VI1_B0_B, GPIO_FN_SD0_CMD,
+	GPIO_FN_SCIFB1_SCK_B, GPIO_FN_VI1_DATA1_VI1_B1_B,
+
+	/* IPSR9 */
+	GPIO_FN_SD0_DAT0, GPIO_FN_SCIFB1_RXD_B, GPIO_FN_VI1_DATA2_VI1_B2_B,
+	GPIO_FN_SD0_DAT1, GPIO_FN_SCIFB1_TXD_B, GPIO_FN_VI1_DATA3_VI1_B3_B,
+	GPIO_FN_SD0_DAT2, GPIO_FN_SCIFB1_CTS_N_B, GPIO_FN_VI1_DATA4_VI1_B4_B,
+	GPIO_FN_SD0_DAT3, GPIO_FN_SCIFB1_RTS_N_B, GPIO_FN_VI1_DATA5_VI1_B5_B,
+	GPIO_FN_SD0_CD, GPIO_FN_MMC0_D6, GPIO_FN_TS_SDEN0_B, GPIO_FN_USB0_EXTP,
+	GPIO_FN_GLO_SCLK, GPIO_FN_VI1_DATA6_VI1_B6_B, GPIO_FN_SCL1_B,
+	GPIO_FN_SCL1_CIS_B, GPIO_FN_VI2_DATA6_VI2_B6_B, GPIO_FN_SD0_WP,
+	GPIO_FN_MMC0_D7, GPIO_FN_TS_SPSYNC0_B, GPIO_FN_USB0_IDIN,
+	GPIO_FN_GLO_SDATA, GPIO_FN_VI1_DATA7_VI1_B7_B, GPIO_FN_SDA1_B,
+	GPIO_FN_SDA1_CIS_B, GPIO_FN_VI2_DATA7_VI2_B7_B, GPIO_FN_SD1_CLK,
+	GPIO_FN_AVB_TX_EN, GPIO_FN_MII_TX_EN, GPIO_FN_SD1_CMD,
+	GPIO_FN_AVB_TX_ER, GPIO_FN_MII_TX_ER, GPIO_FN_SCIFB0_SCK_B,
+	GPIO_FN_SD1_DAT0, GPIO_FN_AVB_TX_CLK, GPIO_FN_MII_TX_CLK,
+	GPIO_FN_SCIFB0_RXD_B, GPIO_FN_SD1_DAT1, GPIO_FN_AVB_LINK,
+	GPIO_FN_MII_LINK, GPIO_FN_SCIFB0_TXD_B, GPIO_FN_SD1_DAT2,
+	GPIO_FN_AVB_COL, GPIO_FN_MII_COL, GPIO_FN_SCIFB0_CTS_N_B,
+	GPIO_FN_SD1_DAT3, GPIO_FN_AVB_RXD0, GPIO_FN_MII_RXD0,
+	GPIO_FN_SCIFB0_RTS_N_B, GPIO_FN_SD1_CD, GPIO_FN_MMC1_D6,
+	GPIO_FN_TS_SDEN1, GPIO_FN_USB1_EXTP, GPIO_FN_GLO_SS, GPIO_FN_VI0_CLK_B,
+	GPIO_FN_SCL2_D, GPIO_FN_SCL2_CIS_D, GPIO_FN_SIM0_CLK_B,
+	GPIO_FN_VI3_CLK_B,
+
+	/* IPSR10 */
+	GPIO_FN_SD1_WP, GPIO_FN_MMC1_D7, GPIO_FN_TS_SPSYNC1, GPIO_FN_USB1_IDIN,
+	GPIO_FN_GLO_RFON, GPIO_FN_VI1_CLK_B, GPIO_FN_SDA2_D, GPIO_FN_SDA2_CIS_D,
+	GPIO_FN_SIM0_D_B, GPIO_FN_SD2_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_SIM0_CLK,
+	GPIO_FN_VI0_DATA0_VI0_B0_B, GPIO_FN_TS_SDEN0_C, GPIO_FN_GLO_SCLK_B,
+	GPIO_FN_VI3_DATA0_B, GPIO_FN_SD2_CMD, GPIO_FN_MMC0_CMD, GPIO_FN_SIM0_D,
+	GPIO_FN_VI0_DATA1_VI0_B1_B, GPIO_FN_SCIFB1_SCK_E, GPIO_FN_SCK1_D,
+	GPIO_FN_TS_SPSYNC0_C, GPIO_FN_GLO_SDATA_B, GPIO_FN_VI3_DATA1_B,
+	GPIO_FN_SD2_DAT0, GPIO_FN_MMC0_D0, GPIO_FN_FMCLK_B,
+	GPIO_FN_VI0_DATA2_VI0_B2_B, GPIO_FN_SCIFB1_RXD_E, GPIO_FN_RX1_D,
+	GPIO_FN_TS_SDAT0_C, GPIO_FN_GLO_SS_B, GPIO_FN_VI3_DATA2_B,
+	GPIO_FN_SD2_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA,
+	GPIO_FN_VI0_DATA3_VI0_B3_B, GPIO_FN_SCIFB1_TXD_E, GPIO_FN_TX1_D,
+	GPIO_FN_TS_SCK0_C, GPIO_FN_GLO_RFON_B, GPIO_FN_VI3_DATA3_B,
+	GPIO_FN_SD2_DAT2, GPIO_FN_MMC0_D2, GPIO_FN_BPFCLK_B, GPIO_FN_RDS_CLK,
+	GPIO_FN_VI0_DATA4_VI0_B4_B, GPIO_FN_HRX0_D, GPIO_FN_TS_SDEN1_B,
+	GPIO_FN_GLO_Q0_B, GPIO_FN_VI3_DATA4_B, GPIO_FN_SD2_DAT3,
+	GPIO_FN_MMC0_D3, GPIO_FN_SIM0_RST, GPIO_FN_VI0_DATA5_VI0_B5_B,
+	GPIO_FN_HTX0_D, GPIO_FN_TS_SPSYNC1_B, GPIO_FN_GLO_Q1_B,
+	GPIO_FN_VI3_DATA5_B, GPIO_FN_SD2_CD, GPIO_FN_MMC0_D4,
+	GPIO_FN_TS_SDAT0_B, GPIO_FN_USB2_EXTP, GPIO_FN_GLO_I0,
+	GPIO_FN_VI0_DATA6_VI0_B6_B, GPIO_FN_HCTS0_N_D, GPIO_FN_TS_SDAT1_B,
+	GPIO_FN_GLO_I0_B, GPIO_FN_VI3_DATA6_B,
+
+	/* IPSR11 */
+	GPIO_FN_SD2_WP, GPIO_FN_MMC0_D5, GPIO_FN_TS_SCK0_B, GPIO_FN_USB2_IDIN,
+	GPIO_FN_GLO_I1, GPIO_FN_VI0_DATA7_VI0_B7_B, GPIO_FN_HRTS0_N_D,
+	GPIO_FN_TS_SCK1_B, GPIO_FN_GLO_I1_B, GPIO_FN_VI3_DATA7_B,
+	GPIO_FN_SD3_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_SD3_CMD, GPIO_FN_MMC1_CMD,
+	GPIO_FN_MTS_N, GPIO_FN_SD3_DAT0, GPIO_FN_MMC1_D0, GPIO_FN_STM_N,
+	GPIO_FN_SD3_DAT1, GPIO_FN_MMC1_D1, GPIO_FN_MDATA, GPIO_FN_SD3_DAT2,
+	GPIO_FN_MMC1_D2, GPIO_FN_SDATA, GPIO_FN_SD3_DAT3, GPIO_FN_MMC1_D3,
+	GPIO_FN_SCKZ, GPIO_FN_SD3_CD, GPIO_FN_MMC1_D4, GPIO_FN_TS_SDAT1,
+	GPIO_FN_VSP, GPIO_FN_GLO_Q0, GPIO_FN_SIM0_RST_B, GPIO_FN_SD3_WP,
+	GPIO_FN_MMC1_D5, GPIO_FN_TS_SCK1, GPIO_FN_GLO_Q1, GPIO_FN_FMIN_C,
+	GPIO_FN_RDS_DATA_B, GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D, GPIO_FN_FMIN_F,
+	GPIO_FN_RDS_DATA_E, GPIO_FN_MLB_CLK, GPIO_FN_SCL2_B, GPIO_FN_SCL2_CIS_B,
+	GPIO_FN_MLB_SIG, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_RX1_C, GPIO_FN_SDA2_B,
+	GPIO_FN_SDA2_CIS_B, GPIO_FN_MLB_DAT, GPIO_FN_SPV_EVEN,
+	GPIO_FN_SCIFB1_TXD_D, GPIO_FN_TX1_C, GPIO_FN_BPFCLK_C,
+	GPIO_FN_RDS_CLK_B, GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_CLK_B,
+	GPIO_FN_MOUT0,
+
+	/* IPSR12 */
+	GPIO_FN_SSI_WS0129, GPIO_FN_CAN0_TX_B, GPIO_FN_MOUT1,
+	GPIO_FN_SSI_SDATA0, GPIO_FN_CAN0_RX_B, GPIO_FN_MOUT2,
+	GPIO_FN_SSI_SDATA1, GPIO_FN_CAN1_TX_B, GPIO_FN_MOUT5,
+	GPIO_FN_SSI_SDATA2, GPIO_FN_CAN1_RX_B, GPIO_FN_SSI_SCK1, GPIO_FN_MOUT6,
+	GPIO_FN_SSI_SCK34, GPIO_FN_STP_OPWM_0, GPIO_FN_SCIFB0_SCK,
+	GPIO_FN_MSIOF1_SCK, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_SSI_WS34,
+	GPIO_FN_STP_IVCXO27_0, GPIO_FN_SCIFB0_RXD, GPIO_FN_MSIOF1_SYNC,
+	GPIO_FN_CAN_STEP0, GPIO_FN_SSI_SDATA3, GPIO_FN_STP_ISCLK_0,
+	GPIO_FN_SCIFB0_TXD, GPIO_FN_MSIOF1_SS1, GPIO_FN_CAN_TXCLK,
+	GPIO_FN_SSI_SCK4, GPIO_FN_STP_ISD_0, GPIO_FN_SCIFB0_CTS_N,
+	GPIO_FN_MSIOF1_SS2, GPIO_FN_SSI_SCK5_C, GPIO_FN_CAN_DEBUGOUT0,
+	GPIO_FN_SSI_WS4, GPIO_FN_STP_ISEN_0, GPIO_FN_SCIFB0_RTS_N,
+	GPIO_FN_MSIOF1_TXD, GPIO_FN_SSI_WS5_C, GPIO_FN_CAN_DEBUGOUT1,
+	GPIO_FN_SSI_SDATA4, GPIO_FN_STP_ISSYNC_0, GPIO_FN_MSIOF1_RXD,
+	GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_SSI_SCK5, GPIO_FN_SCIFB1_SCK,
+	GPIO_FN_IERX_B, GPIO_FN_DU2_EXHSYNC_DU2_HSYNC, GPIO_FN_QSTH_QHS,
+	GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_SSI_WS5, GPIO_FN_SCIFB1_RXD,
+	GPIO_FN_IECLK_B, GPIO_FN_DU2_EXVSYNC_DU2_VSYNC, GPIO_FN_QSTB_QHE,
+	GPIO_FN_CAN_DEBUGOUT4,
+
+	/* IPSR13 */
+	GPIO_FN_SSI_SDATA5, GPIO_FN_SCIFB1_TXD, GPIO_FN_IETX_B, GPIO_FN_DU2_DR2,
+	GPIO_FN_LCDOUT2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK6,
+	GPIO_FN_SCIFB1_CTS_N, GPIO_FN_BPFCLK_D, GPIO_FN_RDS_CLK_C,
+	GPIO_FN_DU2_DR3, GPIO_FN_LCDOUT3, GPIO_FN_CAN_DEBUGOUT6,
+	GPIO_FN_BPFCLK_F, GPIO_FN_RDS_CLK_E, GPIO_FN_SSI_WS6,
+	GPIO_FN_SCIFB1_RTS_N, GPIO_FN_CAN0_TX_D, GPIO_FN_DU2_DR4,
+	GPIO_FN_LCDOUT4, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_SSI_SDATA6,
+	GPIO_FN_FMIN_D, GPIO_FN_RDS_DATA_C, GPIO_FN_DU2_DR5, GPIO_FN_LCDOUT5,
+	GPIO_FN_CAN_DEBUGOUT8, GPIO_FN_SSI_SCK78, GPIO_FN_STP_IVCXO27_1,
+	GPIO_FN_SCK1, GPIO_FN_SCIFA1_SCK, GPIO_FN_DU2_DR6, GPIO_FN_LCDOUT6,
+	GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_WS78, GPIO_FN_STP_ISCLK_1,
+	GPIO_FN_SCIFB2_SCK, GPIO_FN_SCIFA2_CTS_N, GPIO_FN_DU2_DR7,
+	GPIO_FN_LCDOUT7, GPIO_FN_CAN_DEBUGOUT10, GPIO_FN_SSI_SDATA7,
+	GPIO_FN_STP_ISD_1, GPIO_FN_SCIFB2_RXD, GPIO_FN_SCIFA2_RTS_N,
+	GPIO_FN_TCLK2, GPIO_FN_QSTVA_QVS, GPIO_FN_CAN_DEBUGOUT11,
+	GPIO_FN_BPFCLK_E, GPIO_FN_RDS_CLK_D, GPIO_FN_SSI_SDATA7_B,
+	GPIO_FN_FMIN_G, GPIO_FN_RDS_DATA_F, GPIO_FN_SSI_SDATA8,
+	GPIO_FN_STP_ISEN_1, GPIO_FN_SCIFB2_TXD, GPIO_FN_CAN0_TX_C,
+	GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_SSI_SDATA8_B, GPIO_FN_SSI_SDATA9,
+	GPIO_FN_STP_ISSYNC_1, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_SSI_WS1,
+	GPIO_FN_SSI_SDATA5_C, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_AUDIO_CLKA,
+	GPIO_FN_SCIFB2_RTS_N, GPIO_FN_CAN_DEBUGOUT14,
+
+	/* IPSR14 */
+	GPIO_FN_AUDIO_CLKB, GPIO_FN_SCIF_CLK, GPIO_FN_CAN0_RX_D,
+	GPIO_FN_DVC_MUTE, GPIO_FN_CAN0_RX_C, GPIO_FN_CAN_DEBUGOUT15,
+	GPIO_FN_REMOCON, GPIO_FN_SCIFA0_SCK, GPIO_FN_HSCK1, GPIO_FN_SCK0,
+	GPIO_FN_MSIOF3_SS2, GPIO_FN_DU2_DG2, GPIO_FN_LCDOUT10, GPIO_FN_SDA1_C,
+	GPIO_FN_SDA1_CIS_C, GPIO_FN_SCIFA0_RXD, GPIO_FN_HRX1, GPIO_FN_RX0,
+	GPIO_FN_DU2_DR0, GPIO_FN_LCDOUT0, GPIO_FN_SCIFA0_TXD, GPIO_FN_HTX1,
+	GPIO_FN_TX0, GPIO_FN_DU2_DR1, GPIO_FN_LCDOUT1, GPIO_FN_SCIFA0_CTS_N,
+	GPIO_FN_HCTS1_N, GPIO_FN_CTS0_N, GPIO_FN_MSIOF3_SYNC, GPIO_FN_DU2_DG3,
+	GPIO_FN_LCDOUT11, GPIO_FN_PWM0_B, GPIO_FN_SCL1_C, GPIO_FN_SCL1_CIS_C,
+	GPIO_FN_SCIFA0_RTS_N, GPIO_FN_HRTS1_N, GPIO_FN_RTS0_N_TANS,
+	GPIO_FN_MSIOF3_SS1, GPIO_FN_DU2_DG0, GPIO_FN_LCDOUT8, GPIO_FN_PWM1_B,
+	GPIO_FN_SCIFA1_RXD, GPIO_FN_AD_DI, GPIO_FN_RX1,
+	GPIO_FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+	GPIO_FN_SCIFA1_TXD, GPIO_FN_AD_DO, GPIO_FN_TX1, GPIO_FN_DU2_DG1,
+	GPIO_FN_LCDOUT9, GPIO_FN_SCIFA1_CTS_N, GPIO_FN_AD_CLK,
+	GPIO_FN_CTS1_N, GPIO_FN_MSIOF3_RXD, GPIO_FN_DU0_DOTCLKOUT, GPIO_FN_QCLK,
+	GPIO_FN_SCIFA1_RTS_N, GPIO_FN_AD_NCS_N, GPIO_FN_RTS1_N_TANS,
+	GPIO_FN_MSIOF3_TXD, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_QSTVB_QVE,
+	GPIO_FN_HRTS0_N_C,
+
+	/* IPSR15 */
+	GPIO_FN_SCIFA2_SCK, GPIO_FN_FMCLK, GPIO_FN_MSIOF3_SCK, GPIO_FN_DU2_DG7,
+	GPIO_FN_LCDOUT15, GPIO_FN_SCIF_CLK_B, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN,
+	GPIO_FN_DU2_DB0, GPIO_FN_LCDOUT16, GPIO_FN_SCL2, GPIO_FN_SCL2_CIS,
+	GPIO_FN_SCIFA2_TXD, GPIO_FN_BPFCLK, GPIO_FN_DU2_DB1, GPIO_FN_LCDOUT17,
+	GPIO_FN_SDA2, GPIO_FN_SDA2_CIS, GPIO_FN_HSCK0, GPIO_FN_TS_SDEN0,
+	GPIO_FN_DU2_DG4, GPIO_FN_LCDOUT12, GPIO_FN_HCTS0_N_C, GPIO_FN_HRX0,
+	GPIO_FN_DU2_DB2, GPIO_FN_LCDOUT18, GPIO_FN_HTX0, GPIO_FN_DU2_DB3,
+	GPIO_FN_LCDOUT19, GPIO_FN_HCTS0_N, GPIO_FN_SSI_SCK9, GPIO_FN_DU2_DB4,
+	GPIO_FN_LCDOUT20, GPIO_FN_HRTS0_N, GPIO_FN_SSI_WS9, GPIO_FN_DU2_DB5,
+	GPIO_FN_LCDOUT21, GPIO_FN_MSIOF0_SCK, GPIO_FN_TS_SDAT0, GPIO_FN_ADICLK,
+	GPIO_FN_DU2_DB6, GPIO_FN_LCDOUT22, GPIO_FN_MSIOF0_SYNC, GPIO_FN_TS_SCK0,
+	GPIO_FN_SSI_SCK2, GPIO_FN_ADIDATA, GPIO_FN_DU2_DB7, GPIO_FN_LCDOUT23,
+	GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF0_SS1, GPIO_FN_ADICHS0,
+	GPIO_FN_DU2_DG5, GPIO_FN_LCDOUT13, GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICHS1,
+	GPIO_FN_DU2_DG6, GPIO_FN_LCDOUT14,
+
+	/* IPSR16 */
+	GPIO_FN_MSIOF0_SS2, GPIO_FN_AUDIO_CLKOUT, GPIO_FN_ADICHS2,
+	GPIO_FN_DU2_DISP, GPIO_FN_QPOLA, GPIO_FN_HTX0_C, GPIO_FN_SCIFA2_TXD_B,
+	GPIO_FN_MSIOF0_RXD, GPIO_FN_TS_SPSYNC0, GPIO_FN_SSI_WS2,
+	GPIO_FN_ADICS_SAMP, GPIO_FN_DU2_CDE, GPIO_FN_QPOLB, GPIO_FN_HRX0_C,
+	GPIO_FN_USB1_PWEN, GPIO_FN_AUDIO_CLKOUT_D, GPIO_FN_USB1_OVC,
+	GPIO_FN_TCLK1_B,
+};
+
+#endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7790.h b/arch/arm/include/asm/arch-rmobile/r8a7790.h
new file mode 100644
index 0000000..42d65d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7790.h
@@ -0,0 +1,614 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7790.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_R8A7790_H
+#define __ASM_ARCH_R8A7790_H
+
+/*
+ * R8A7790 I/O Addresses
+ */
+#define	RWDT_BASE		0xE6020000
+#define	SWDT_BASE		0xE6030000
+#define	LBSC_BASE		0xFEC00200
+#define DBSC3_0_BASE		0xE6790000
+#define DBSC3_1_BASE		0xE67A0000
+#define TMU_BASE		0xE61E0000
+#define	GPIO5_BASE		0xE6055000
+
+#define S3C_BASE		0xE6784000
+#define S3C_INT_BASE		0xE6784A00
+#define S3C_MEDIA_BASE		0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE	0xE6784BDC
+#define S3C_QOS_CCI0_BASE	0xE6784C00
+#define S3C_QOS_CCI1_BASE	0xE6784C24
+#define S3C_QOS_MXI_BASE	0xE6784C48
+#define S3C_QOS_AXI_BASE	0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE	0xE6791000
+#define DBSC3_0_QOS_R1_BASE	0xE6791100
+#define DBSC3_0_QOS_R2_BASE	0xE6791200
+#define DBSC3_0_QOS_R3_BASE	0xE6791300
+#define DBSC3_0_QOS_R4_BASE	0xE6791400
+#define DBSC3_0_QOS_R5_BASE	0xE6791500
+#define DBSC3_0_QOS_R6_BASE	0xE6791600
+#define DBSC3_0_QOS_R7_BASE	0xE6791700
+#define DBSC3_0_QOS_R8_BASE	0xE6791800
+#define DBSC3_0_QOS_R9_BASE	0xE6791900
+#define DBSC3_0_QOS_R10_BASE	0xE6791A00
+#define DBSC3_0_QOS_R11_BASE	0xE6791B00
+#define DBSC3_0_QOS_R12_BASE	0xE6791C00
+#define DBSC3_0_QOS_R13_BASE	0xE6791D00
+#define DBSC3_0_QOS_R14_BASE	0xE6791E00
+#define DBSC3_0_QOS_R15_BASE	0xE6791F00
+#define DBSC3_0_QOS_W0_BASE	0xE6792000
+#define DBSC3_0_QOS_W1_BASE	0xE6792100
+#define DBSC3_0_QOS_W2_BASE	0xE6792200
+#define DBSC3_0_QOS_W3_BASE	0xE6792300
+#define DBSC3_0_QOS_W4_BASE	0xE6792400
+#define DBSC3_0_QOS_W5_BASE	0xE6792500
+#define DBSC3_0_QOS_W6_BASE	0xE6792600
+#define DBSC3_0_QOS_W7_BASE	0xE6792700
+#define DBSC3_0_QOS_W8_BASE	0xE6792800
+#define DBSC3_0_QOS_W9_BASE	0xE6792900
+#define DBSC3_0_QOS_W10_BASE	0xE6792A00
+#define DBSC3_0_QOS_W11_BASE	0xE6792B00
+#define DBSC3_0_QOS_W12_BASE	0xE6792C00
+#define DBSC3_0_QOS_W13_BASE	0xE6792D00
+#define DBSC3_0_QOS_W14_BASE	0xE6792E00
+#define DBSC3_0_QOS_W15_BASE	0xE6792F00
+
+#define DBSC3_0_DBADJ2		0xE67900C8
+
+#define CCI_400_MAXOT_1		0xF0091110
+#define CCI_400_MAXOT_2		0xF0092110
+#define CCI_400_QOSCNTL_1	0xF009110C
+#define CCI_400_QOSCNTL_2	0xF009210C
+
+#define	MXI_BASE		0xFE960000
+#define	MXI_QOS_BASE		0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE	0xFF800300
+#define SYS_AXI_AVB_BASE	0xFF800340
+#define SYS_AXI_G2D_BASE	0xFF800540
+#define SYS_AXI_IMP0_BASE	0xFF800580
+#define SYS_AXI_IMP1_BASE	0xFF8005C0
+#define SYS_AXI_IMUX0_BASE	0xFF800600
+#define SYS_AXI_IMUX1_BASE	0xFF800640
+#define SYS_AXI_IMUX2_BASE	0xFF800680
+#define SYS_AXI_LBS_BASE	0xFF8006C0
+#define SYS_AXI_MMUDS_BASE	0xFF800700
+#define SYS_AXI_MMUM_BASE	0xFF800740
+#define SYS_AXI_MMUR_BASE	0xFF800780
+#define SYS_AXI_MMUS0_BASE	0xFF8007C0
+#define SYS_AXI_MMUS1_BASE	0xFF800800
+#define SYS_AXI_MTSB0_BASE	0xFF800880
+#define SYS_AXI_MTSB1_BASE	0xFF8008C0
+#define SYS_AXI_PCI_BASE	0xFF800900
+#define SYS_AXI_RTX_BASE	0xFF800940
+#define SYS_AXI_SDS0_BASE	0xFF800A80
+#define SYS_AXI_SDS1_BASE	0xFF800AC0
+#define SYS_AXI_USB20_BASE	0xFF800C00
+#define SYS_AXI_USB21_BASE	0xFF800C40
+#define SYS_AXI_USB22_BASE	0xFF800C80
+#define SYS_AXI_USB30_BASE	0xFF800CC0
+
+#define RT_AXI_SHX_BASE		0xFF810100
+#define RT_AXI_RDS_BASE		0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE	0xFF810200
+#define RT_AXI_STPRO_BASE	0xFF810240
+
+#define MP_AXI_ADSP_BASE	0xFF820100
+#define MP_AXI_ASDS0_BASE	0xFF8201C0
+#define MP_AXI_ASDS1_BASE	0xFF820200
+#define MP_AXI_MLP_BASE		0xFF820240
+#define MP_AXI_MMUMP_BASE	0xFF820280
+#define MP_AXI_SPU_BASE		0xFF8202C0
+#define MP_AXI_SPUC_BASE	0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
+#define SYS_AXI256_SYX_BASE	0xFF860140
+#define SYS_AXI256_MPX_BASE	0xFF860180
+#define SYS_AXI256_MXI_BASE	0xFF8601C0
+
+#define CCI_AXI_MMUS0_BASE	0xFF880100
+#define CCI_AXI_SYX2_BASE	0xFF880140
+#define CCI_AXI_MMUR_BASE	0xFF880180
+#define CCI_AXI_MMUDS_BASE	0xFF8801C0
+#define CCI_AXI_MMUM_BASE	0xFF880200
+#define CCI_AXI_MXI_BASE	0xFF880240
+#define CCI_AXI_MMUS1_BASE	0xFF880280
+#define CCI_AXI_MMUMP_BASE	0xFF8802C0
+
+#define MEDIA_AXI_JPR_BASE	0xFE964100
+#define MEDIA_AXI_JPW_BASE	0xFE966100
+#define MEDIA_AXI_GCU0R_BASE	0xFE964140
+#define MEDIA_AXI_GCU0W_BASE	0xFE966140
+#define MEDIA_AXI_GCU1R_BASE	0xFE964180
+#define MEDIA_AXI_GCU1W_BASE	0xFE966180
+#define MEDIA_AXI_TDMR_BASE	0xFE964500
+#define MEDIA_AXI_TDMW_BASE	0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE	0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE	0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE	0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE	0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
+#define MEDIA_AXI_VIN0W_BASE	0xFE966900
+#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
+#define MEDIA_AXI_FDP0R_BASE	0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE	0xFE966D40
+#define MEDIA_AXI_IMSR_BASE	0xFE964D80
+#define MEDIA_AXI_IMSW_BASE	0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE	0xFE965100
+#define MEDIA_AXI_VSP1W_BASE	0xFE967100
+#define MEDIA_AXI_FDP1R_BASE	0xFE965140
+#define MEDIA_AXI_FDP1W_BASE	0xFE967140
+#define MEDIA_AXI_IMRR_BASE	0xFE965180
+#define MEDIA_AXI_IMRW_BASE	0xFE967180
+#define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
+#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
+#define MEDIA_AXI_DU0R_BASE	0xFE965580
+#define MEDIA_AXI_DU0W_BASE	0xFE967580
+#define MEDIA_AXI_DU1R_BASE	0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE	0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE	0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE	0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE	0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE	0xFE967940
+#define MEDIA_AXI_VPC0R_BASE	0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE	0xFE965D80
+
+#define SYS_AXI_AVBDMSCR	0xFF802000
+#define SYS_AXI_SYX2DMSCR	0xFF802004
+#define SYS_AXI_CC50DMSCR	0xFF802008
+#define SYS_AXI_CC51DMSCR	0xFF80200C
+#define SYS_AXI_CCIDMSCR	0xFF802010
+#define SYS_AXI_CSDMSCR		0xFF802014
+#define SYS_AXI_DDMDMSCR	0xFF802018
+#define SYS_AXI_ETHDMSCR	0xFF80201C
+#define SYS_AXI_G2DDMSCR	0xFF802020
+#define SYS_AXI_IMP0DMSCR	0xFF802024
+#define SYS_AXI_IMP1DMSCR	0xFF802028
+#define SYS_AXI_LBSDMSCR	0xFF80202C
+#define SYS_AXI_MMUDSDMSCR	0xFF802030
+#define SYS_AXI_MMUMXDMSCR	0xFF802034
+#define SYS_AXI_MMURDDMSCR	0xFF802038
+#define SYS_AXI_MMUS0DMSCR	0xFF80203C
+#define SYS_AXI_MMUS1DMSCR	0xFF802040
+#define SYS_AXI_MPXDMSCR	0xFF802044
+#define SYS_AXI_MTSB0DMSCR	0xFF802048
+#define SYS_AXI_MTSB1DMSCR	0xFF80204C
+#define SYS_AXI_PCIDMSCR	0xFF802050
+#define SYS_AXI_RTXDMSCR	0xFF802054
+#define SYS_AXI_SAT0DMSCR	0xFF802058
+#define SYS_AXI_SAT1DMSCR	0xFF80205C
+#define SYS_AXI_SDM0DMSCR	0xFF802060
+#define SYS_AXI_SDM1DMSCR	0xFF802064
+#define SYS_AXI_SDS0DMSCR	0xFF802068
+#define SYS_AXI_SDS1DMSCR	0xFF80206C
+#define SYS_AXI_ETRABDMSCR	0xFF802070
+#define SYS_AXI_ETRKFDMSCR	0xFF802074
+#define SYS_AXI_UDM0DMSCR	0xFF802078
+#define SYS_AXI_UDM1DMSCR	0xFF80207C
+#define SYS_AXI_USB20DMSCR	0xFF802080
+#define SYS_AXI_USB21DMSCR	0xFF802084
+#define SYS_AXI_USB22DMSCR	0xFF802088
+#define SYS_AXI_USB30DMSCR	0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
+#define SYS_AXI_AVBSLVDMSCR	0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR	0xFF802110
+#define SYS_AXI_GICSLVDMSCR	0xFF802114
+#define SYS_AXI_IMPSLVDMSCR	0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR	0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR	0xFF802124
+#define SYS_AXI_LBSSLVDMSCR	0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR	0xFF802130
+#define SYS_AXI_MPXSLVDMSCR	0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR	0xFF802140
+#define SYS_AXI_PCISLVDMSCR	0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR	0xFF802150
+#define SYS_AXI_SAT0SLVDMSCR	0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR	0xFF802180
+#define SYS_AXI_STBSLVDMSCR	0xFF802188
+#define SYS_AXI_STMSLVDMSCR	0xFF80218C
+#define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
+
+#define RT_AXI_CBMDMSCR		0xFF812000
+#define RT_AXI_DBDMSCR		0xFF812004
+#define RT_AXI_RDMDMSCR		0xFF812008
+#define RT_AXI_RDSDMSCR		0xFF81200C
+#define RT_AXI_STRDMSCR		0xFF812010
+#define RT_AXI_SY2RTDMSCR	0xFF812014
+#define RT_AXI_CBSSLVDMSCR	0xFF812100
+#define RT_AXI_DBSSLVDMSCR	0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR	0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR	0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR	0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR	0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR	0xFF812128
+
+#define MP_AXI_ADSPDMSCR	0xFF822000
+#define MP_AXI_ASDM0DMSCR	0xFF822004
+#define MP_AXI_ASDM1DMSCR	0xFF822008
+#define MP_AXI_ASDS0DMSCR	0xFF82200C
+#define MP_AXI_ASDS1DMSCR	0xFF822010
+#define MP_AXI_MLPDMSCR		0xFF822014
+#define MP_AXI_MMUMPDMSCR	0xFF822018
+#define MP_AXI_SPUDMSCR		0xFF82201C
+#define MP_AXI_SPUCDMSCR	0xFF822020
+#define MP_AXI_SY2MPDMSCR	0xFF822024
+#define MP_AXI_ADSPSLVDMSCR	0xFF822100
+#define MP_AXI_MLMSLVDMSCR	0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR	0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR	0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR	0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR	0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR	0xFF822124
+#define MP_AXI_SPUSLVDMSCR	0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR	0xFF842000
+#define ADM_AXI_ASDM1DMSCR	0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
+
+#define DM_AXI_RDMDMSCR		0xFF852000
+#define DM_AXI_SDM0DMSCR	0xFF852004
+#define DM_AXI_SDM1DMSCR	0xFF852008
+#define DM_AXI_MMAP0SLVDMSCR	0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR	0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR	0xFF852108
+#define DM_AXI_RAP4SLVDMSCR	0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR	0xFF852110
+#define DM_AXI_SAP4SLVDMSCR	0xFF852114
+#define DM_AXI_SAP5SLVDMSCR	0xFF852118
+#define DM_AXI_SAP6SLVDMSCR	0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR	0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR	0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR	0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR	0xFF852130
+
+#define SYS_AXI256_SYXDMSCR	0xFF862000
+#define SYS_AXI256_MPXDMSCR	0xFF862004
+#define SYS_AXI256_MXIDMSCR	0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR	0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR	0xFF862110
+
+#define MXT_SYXDMSCR		0xFF872000
+#define MXT_CMM0SLVDMSCR	0xFF872100
+#define MXT_CMM1SLVDMSCR	0xFF872104
+#define MXT_CMM2SLVDMSCR	0xFF872108
+#define MXT_FDPSLVDMSCR		0xFF87210C
+#define MXT_IMRSLVDMSCR		0xFF872110
+#define MXT_VINSLVDMSCR		0xFF872114
+#define MXT_VPC0SLVDMSCR	0xFF872118
+#define MXT_VPC1SLVDMSCR	0xFF87211C
+#define MXT_VSP0SLVDMSCR	0xFF872120
+#define MXT_VSP1SLVDMSCR	0xFF872124
+#define MXT_VSPD0SLVDMSCR	0xFF872128
+#define MXT_VSPD1SLVDMSCR	0xFF87212C
+#define MXT_MAP1SLVDMSCR	0xFF872130
+#define MXT_MAP2SLVDMSCR	0xFF872134
+
+#define CCI_AXI_MMUS0DMSCR	0xFF882000
+#define CCI_AXI_SYX2DMSCR	0xFF882004
+#define CCI_AXI_MMURDMSCR	0xFF882008
+#define CCI_AXI_MMUDSDMSCR	0xFF88200C
+#define CCI_AXI_MMUMDMSCR	0xFF882010
+#define CCI_AXI_MXIDMSCR	0xFF882014
+#define CCI_AXI_MMUS1DMSCR	0xFF882018
+#define CCI_AXI_MMUMPDMSCR	0xFF88201C
+#define CCI_AXI_DVMDMSCR	0xFF882020
+#define CCI_AXI_CCISLVDMSCR	0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR	0xFF880400
+#define CCI_AXI_IPMMURDVMCR	0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR	0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR	0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR	0xFF880414
+#define CCI_AXI_AX2ADDRMASK	0xFF88041C
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7790_rwdt {
+	u32 rwtcnt;	/* 0x00 */
+	u32 rwtcsra;	/* 0x04 */
+	u16 rwtcsrb;	/* 0x08 */
+};
+
+/* SWDT */
+struct r8a7790_swdt {
+	u32 swtcnt;	/* 0x00 */
+	u32 swtcsra;	/* 0x04 */
+	u16 swtcsrb;	/* 0x08 */
+};
+
+/* LBSC */
+struct r8a7790_lbsc {
+	u32 cs0ctrl;
+	u32 cs1ctrl;
+	u32 ecs0ctrl;
+	u32 ecs1ctrl;
+	u32 ecs2ctrl;
+	u32 ecs3ctrl;
+	u32 ecs4ctrl;
+	u32 ecs5ctrl;
+	u32 dummy0[4];	/* 0x20 .. 0x2C */
+	u32 cswcr0;
+	u32 cswcr1;
+	u32 ecswcr0;
+	u32 ecswcr1;
+	u32 ecswcr2;
+	u32 ecswcr3;
+	u32 ecswcr4;
+	u32 ecswcr5;
+	u32 exdmawcr0;
+	u32 exdmawcr1;
+	u32 exdmawcr2;
+	u32 dummy1[9];	/* 0x5C .. 0x7C */
+	u32 cspwcr0;
+	u32 cspwcr1;
+	u32 ecspwcr0;
+	u32 ecspwcr1;
+	u32 ecspwcr2;
+	u32 ecspwcr3;
+	u32 ecspwcr4;
+	u32 ecspwcr5;
+	u32 exwtsync;
+	u32 dummy2[3];	/* 0xA4 .. 0xAC */
+	u32 cs0bstctl;
+	u32 cs0btph;
+	u32 dummy3[2];	/* 0xB8 .. 0xBC */
+	u32 cs1gdst;
+	u32 ecs0gdst;
+	u32 ecs1gdst;
+	u32 ecs2gdst;
+	u32 ecs3gdst;
+	u32 ecs4gdst;
+	u32 ecs5gdst;
+	u32 dummy4[5];	/* 0xDC .. 0xEC */
+	u32 exdmaset0;
+	u32 exdmaset1;
+	u32 exdmaset2;
+	u32 dummy5[5];	/* 0xFC .. 0x10C */
+	u32 exdmcr0;
+	u32 exdmcr1;
+	u32 exdmcr2;
+	u32 dummy6[5];	/* 0x11C .. 0x12C */
+	u32 bcintsr;
+	u32 bcintcr;
+	u32 bcintmr;
+	u32 dummy7;	/* 0x13C */
+	u32 exbatlv;
+	u32 exwtsts;
+	u32 dummy8[14];	/* 0x148 .. 0x17C */
+	u32 atacsctrl;
+	u32 dummy9[15]; /* 0x184 .. 0x1BC */
+	u32 exbct;
+	u32 extct;
+};
+
+/* DBSC3 */
+struct r8a7790_dbsc3 {
+	u32 dummy0[3];	/* 0x00 .. 0x08 */
+	u32 dbstate1;
+	u32 dbacen;
+	u32 dbrfen;
+	u32 dbcmd;
+	u32 dbwait;
+	u32 dbkind;
+	u32 dbconf0;
+	u32 dummy1[2];	/* 0x28 .. 0x2C */
+	u32 dbphytype;
+	u32 dummy2[3];	/* 0x34 .. 0x3C */
+	u32 dbtr0;
+	u32 dbtr1;
+	u32 dbtr2;
+	u32 dummy3;	/* 0x4C */
+	u32 dbtr3;
+	u32 dbtr4;
+	u32 dbtr5;
+	u32 dbtr6;
+	u32 dbtr7;
+	u32 dbtr8;
+	u32 dbtr9;
+	u32 dbtr10;
+	u32 dbtr11;
+	u32 dbtr12;
+	u32 dbtr13;
+	u32 dbtr14;
+	u32 dbtr15;
+	u32 dbtr16;
+	u32 dbtr17;
+	u32 dbtr18;
+	u32 dbtr19;
+	u32 dummy4[7];	/* 0x94 .. 0xAC */
+	u32 dbbl;
+	u32 dummy5[3];	/* 0xB4 .. 0xBC */
+	u32 dbadj0;
+	u32 dummy6;	/* 0xC4 */
+	u32 dbadj2;
+	u32 dummy7[5];	/* 0xCC .. 0xDC */
+	u32 dbrfcnf0;
+	u32 dbrfcnf1;
+	u32 dbrfcnf2;
+	u32 dummy8[2];	/* 0xEC .. 0xF0 */
+	u32 dbcalcnf;
+	u32 dbcaltr;
+	u32 dummy9;	/* 0xFC */
+	u32 dbrnk0;
+	u32 dummy10[31];	/* 0x104 .. 0x17C */
+	u32 dbpdncnf;
+	u32 dummy11[47];	/* 0x184 ..0x23C */
+	u32 dbdfistat;
+	u32 dbdficnt;
+	u32 dummy12[14];	/* 0x248 .. 0x27C */
+	u32 dbpdlck;
+	u32 dummy13[3];	/* 0x284 .. 0x28C */
+	u32 dbpdrga;
+	u32 dummy14[3];	/* 0x294 .. 0x29C */
+	u32 dbpdrgd;
+	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
+	u32 dbbs0cnt1;
+	u32 dummy16[30];	/* 0x308 .. 0x37C */
+	u32 dbwt0cnf0;
+	u32 dbwt0cnf1;
+	u32 dbwt0cnf2;
+	u32 dbwt0cnf3;
+	u32 dbwt0cnf4;
+};
+
+/* GPIO */
+struct r8a7790_gpio {
+	u32 iointsel;
+	u32 inoutsel;
+	u32 outdt;
+	u32 indt;
+	u32 intdt;
+	u32 intclr;
+	u32 intmsk;
+	u32 posneg;
+	u32 edglevel;
+	u32 filonoff;
+	u32 intmsks;
+	u32 mskclrs;
+	u32 outdtsel;
+	u32 outdth;
+	u32 outdtl;
+	u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct r8a7790_s3c {
+	u32 s3cexcladdmsk;
+	u32 s3cexclidmsk;
+	u32 s3cadsplcr;
+	u32 s3cmaar;
+	u32 s3carcr11;
+	u32 s3crorr;
+	u32 s3cworr;
+	u32 s3carcr22;
+	u32 dummy1[2];	/* 0x20 .. 0x24 */
+	u32 s3cmctr;
+	u32 dummy2;	/* 0x2C */
+	u32 cconf0;
+	u32 cconf1;
+	u32 cconf2;
+	u32 cconf3;
+};
+
+struct r8a7790_s3c_qos {
+	u32 s3cqos0;
+	u32 s3cqos1;
+	u32 s3cqos2;
+	u32 s3cqos3;
+	u32 s3cqos4;
+	u32 s3cqos5;
+	u32 s3cqos6;
+	u32 s3cqos7;
+	u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct r8a7790_dbsc3_qos {
+	u32 dblgcnt;
+	u32 dbtmval0;
+	u32 dbtmval1;
+	u32 dbtmval2;
+	u32 dbtmval3;
+	u32 dbrqctr;
+	u32 dbthres0;
+	u32 dbthres1;
+	u32 dbthres2;
+	u32 dummy0;	/* 0x24 */
+	u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct r8a7790_mxi {
+	u32 mxsaar0;
+	u32 mxsaar1;
+	u32 dummy0[7];	/* 0x08 .. 0x20 */
+	u32 mxaxiracr;
+	u32 mxs3cracr;
+	u32 dummy1[2];	/* 0x2C .. 0x30 */
+	u32 mxaxiwacr;
+	u32 mxs3cwacr;
+	u32 dummy2;	/* 0x3C */
+	u32 mxrtcr;
+	u32 mxwtcr;
+};
+
+struct r8a7790_mxi_qos {
+	u32 vspdu0;
+	u32 vspdu1;
+	u32 du0;
+	u32 du1;
+};
+
+/* AXI(QoS) */
+struct r8a7790_axi_qos {
+	u32 qosconf;
+	u32 qosctset0;
+	u32 qosctset1;
+	u32 qosctset2;
+	u32 qosctset3;
+	u32 qosreqctr;
+	u32 qosthres0;
+	u32 qosthres1;
+	u32 qosthres2;
+	u32 qosqon;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7790_H */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
new file mode 100644
index 0000000..d3cf0c1
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791-gpio.h
@@ -0,0 +1,438 @@
+#ifndef __ASM_R8A7791_H__
+#define __ASM_R8A7791_H__
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+	GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+	GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+	GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+	GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+	GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+	GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+	GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+	GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+
+	GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+	GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+	GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+	GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+	GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+	GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+	GPIO_GP_1_24, GPIO_GP_1_25,
+
+	GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+	GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+	GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+	GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+	GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+	GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+	GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+	GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
+
+	GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+	GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+	GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+	GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+	GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+	GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+	GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+	GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+
+	GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+	GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+	GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+	GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+	GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+	GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+	GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+	GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+
+	GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+	GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+	GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+	GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+	GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+	GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+	GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+	GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
+
+	GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+	GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+	GPIO_GP_6_8, GPIO_GP_6_9, GPIO_GP_6_10, GPIO_GP_6_11,
+	GPIO_GP_6_12, GPIO_GP_6_13, GPIO_GP_6_14, GPIO_GP_6_15,
+	GPIO_GP_6_16, GPIO_GP_6_17, GPIO_GP_6_18, GPIO_GP_6_19,
+	GPIO_GP_6_20, GPIO_GP_6_21, GPIO_GP_6_22, GPIO_GP_6_23,
+	GPIO_GP_6_24, GPIO_GP_6_25, GPIO_GP_6_26, GPIO_GP_6_27,
+	GPIO_GP_6_28, GPIO_GP_6_29, GPIO_GP_6_30, GPIO_GP_6_31,
+
+	GPIO_GP_7_0, GPIO_GP_7_1, GPIO_GP_7_2, GPIO_GP_7_3,
+	GPIO_GP_7_4, GPIO_GP_7_5, GPIO_GP_7_6, GPIO_GP_7_7,
+	GPIO_GP_7_8, GPIO_GP_7_9, GPIO_GP_7_10, GPIO_GP_7_11,
+	GPIO_GP_7_12, GPIO_GP_7_13, GPIO_GP_7_14, GPIO_GP_7_15,
+	GPIO_GP_7_16, GPIO_GP_7_17, GPIO_GP_7_18, GPIO_GP_7_19,
+	GPIO_GP_7_20, GPIO_GP_7_21, GPIO_GP_7_22, GPIO_GP_7_23,
+	GPIO_GP_7_24, GPIO_GP_7_25,
+
+	GPIO_FN_EX_CS0_N, GPIO_FN_RD_N, GPIO_FN_AUDIO_CLKA,
+	GPIO_FN_VI0_CLK, GPIO_FN_VI0_DATA0_VI0_B0,
+	GPIO_FN_VI0_DATA0_VI0_B1, GPIO_FN_VI0_DATA0_VI0_B2,
+	GPIO_FN_VI0_DATA0_VI0_B4, GPIO_FN_VI0_DATA0_VI0_B5,
+	GPIO_FN_VI0_DATA0_VI0_B6, GPIO_FN_VI0_DATA0_VI0_B7,
+	GPIO_FN_USB0_PWEN, GPIO_FN_USB0_OVC, GPIO_FN_USB1_PWEN,
+
+	/* IPSR0 */
+	GPIO_FN_D0, GPIO_FN_D1, GPIO_FN_D2, GPIO_FN_D3, GPIO_FN_D4, GPIO_FN_D5,
+	GPIO_FN_D6, GPIO_FN_D7, GPIO_FN_D8, GPIO_FN_D9, GPIO_FN_D10,
+	GPIO_FN_D11, GPIO_FN_D12, GPIO_FN_D13, GPIO_FN_D14, GPIO_FN_D15,
+	GPIO_FN_A0, GPIO_FN_ATAWR0_N_C, GPIO_FN_MSIOF0_SCK_B,
+	GPIO_FN_SCL0_C, GPIO_FN_PWM2_B,
+	GPIO_FN_A1, GPIO_FN_MSIOF0_SYNC_B, GPIO_FN_A2, GPIO_FN_MSIOF0_SS1_B,
+	GPIO_FN_A3, GPIO_FN_MSIOF0_SS2_B, GPIO_FN_A4, GPIO_FN_MSIOF0_TXD_B,
+	GPIO_FN_A5, GPIO_FN_MSIOF0_RXD_B, GPIO_FN_A6, GPIO_FN_MSIOF1_SCK,
+
+	/* IPSR1 */
+	GPIO_FN_A7, GPIO_FN_MSIOF1_SYNC, GPIO_FN_A8,
+	GPIO_FN_MSIOF1_SS1, GPIO_FN_SCL0,
+	GPIO_FN_A9, GPIO_FN_MSIOF1_SS2, GPIO_FN_SDA0,
+	GPIO_FN_A10, GPIO_FN_MSIOF1_TXD, GPIO_FN_MSIOF1_TXD_D,
+	GPIO_FN_A11, GPIO_FN_MSIOF1_RXD, GPIO_FN_SCL3_D, GPIO_FN_MSIOF1_RXD_D,
+	GPIO_FN_A12, GPIO_FN_FMCLK, GPIO_FN_SDA3_D, GPIO_FN_MSIOF1_SCK_D,
+	GPIO_FN_A13, GPIO_FN_ATAG0_N_C, GPIO_FN_BPFCLK, GPIO_FN_MSIOF1_SS1_D,
+	GPIO_FN_A14, GPIO_FN_ATADIR0_N_C, GPIO_FN_FMIN,
+	GPIO_FN_FMIN_C, GPIO_FN_MSIOF1_SYNC_D,
+	GPIO_FN_A15, GPIO_FN_BPFCLK_C,
+	GPIO_FN_A16, GPIO_FN_DREQ2_B, GPIO_FN_FMCLK_C, GPIO_FN_SCIFA1_SCK_B,
+	GPIO_FN_A17, GPIO_FN_DACK2_B, GPIO_FN_SDA0_C,
+	GPIO_FN_A18, GPIO_FN_DREQ1, GPIO_FN_SCIFA1_RXD_C, GPIO_FN_SCIFB1_RXD_C,
+
+	/* IPSR2 */
+	GPIO_FN_A19, GPIO_FN_DACK1, GPIO_FN_SCIFA1_TXD_C,
+	GPIO_FN_SCIFB1_TXD_C, GPIO_FN_SCIFB1_SCK_B,
+	GPIO_FN_A20, GPIO_FN_SPCLK,
+	GPIO_FN_A21, GPIO_FN_ATAWR0_N_B, GPIO_FN_MOSI_IO0,
+	GPIO_FN_A22, GPIO_FN_MISO_IO1, GPIO_FN_FMCLK_B,
+	GPIO_FN_TX0, GPIO_FN_SCIFA0_TXD,
+	GPIO_FN_A23, GPIO_FN_IO2, GPIO_FN_BPFCLK_B,
+	GPIO_FN_RX0, GPIO_FN_SCIFA0_RXD,
+	GPIO_FN_A24, GPIO_FN_DREQ2, GPIO_FN_IO3,
+	GPIO_FN_TX1, GPIO_FN_SCIFA1_TXD,
+	GPIO_FN_A25, GPIO_FN_DACK2, GPIO_FN_SSL, GPIO_FN_DREQ1_C,
+	GPIO_FN_RX1, GPIO_FN_SCIFA1_RXD,
+	GPIO_FN_CS0_N, GPIO_FN_ATAG0_N_B, GPIO_FN_SCL1,
+	GPIO_FN_CS1_N_A26, GPIO_FN_ATADIR0_N_B, GPIO_FN_SDA1,
+	GPIO_FN_EX_CS1_N, GPIO_FN_MSIOF2_SCK,
+	GPIO_FN_EX_CS2_N, GPIO_FN_ATAWR0_N, GPIO_FN_MSIOF2_SYNC,
+	GPIO_FN_EX_CS3_N, GPIO_FN_ATADIR0_N, GPIO_FN_MSIOF2_TXD,
+	GPIO_FN_ATAG0_N, GPIO_FN_EX_WAIT1,
+
+	/* IPSR3 */
+	GPIO_FN_EX_CS4_N, GPIO_FN_ATARD0_N,
+	GPIO_FN_MSIOF2_RXD, GPIO_FN_EX_WAIT2,
+	GPIO_FN_EX_CS5_N, GPIO_FN_ATACS00_N, GPIO_FN_MSIOF2_SS1,
+	GPIO_FN_HRX1_B, GPIO_FN_SCIFB1_RXD_B,
+	GPIO_FN_PWM1, GPIO_FN_TPU_TO1,
+	GPIO_FN_BS_N, GPIO_FN_ATACS10_N, GPIO_FN_MSIOF2_SS2,
+	GPIO_FN_HTX1_B, GPIO_FN_SCIFB1_TXD_B,
+	GPIO_FN_PWM2, GPIO_FN_TPU_TO2,
+	GPIO_FN_RD_WR_N, GPIO_FN_HRX2_B, GPIO_FN_FMIN_B,
+	GPIO_FN_SCIFB0_RXD_B, GPIO_FN_DREQ1_D,
+	GPIO_FN_WE0_N, GPIO_FN_HCTS2_N_B, GPIO_FN_SCIFB0_TXD_B,
+	GPIO_FN_WE1_N, GPIO_FN_ATARD0_N_B,
+	GPIO_FN_HTX2_B, GPIO_FN_SCIFB0_RTS_N_B,
+	GPIO_FN_EX_WAIT0, GPIO_FN_HRTS2_N_B, GPIO_FN_SCIFB0_CTS_N_B,
+	GPIO_FN_DREQ0, GPIO_FN_PWM3, GPIO_FN_TPU_TO3,
+	GPIO_FN_DACK0, GPIO_FN_DRACK0, GPIO_FN_REMOCON,
+	GPIO_FN_SPEEDIN, GPIO_FN_HSCK0_C, GPIO_FN_HSCK2_C,
+	GPIO_FN_SCIFB0_SCK_B, GPIO_FN_SCIFB2_SCK_B,
+	GPIO_FN_DREQ2_C, GPIO_FN_HTX2_D,
+	GPIO_FN_SSI_SCK0129, GPIO_FN_HRX0_C, GPIO_FN_HRX2_C,
+	GPIO_FN_SCIFB0_RXD_C, GPIO_FN_SCIFB2_RXD_C,
+	GPIO_FN_SSI_WS0129, GPIO_FN_HTX0_C, GPIO_FN_HTX2_C,
+	GPIO_FN_SCIFB0_TXD_C, GPIO_FN_SCIFB2_TXD_C,
+
+	/* IPSR4 */
+	GPIO_FN_SSI_SDATA0, GPIO_FN_SCL0_B,
+	GPIO_FN_SCL7_B, GPIO_FN_MSIOF2_SCK_C,
+	GPIO_FN_SSI_SCK1, GPIO_FN_SDA0_B, GPIO_FN_SDA7_B,
+	GPIO_FN_MSIOF2_SYNC_C, GPIO_FN_GLO_I0_D,
+	GPIO_FN_SSI_WS1, GPIO_FN_SCL1_B, GPIO_FN_SCL8_B,
+	GPIO_FN_MSIOF2_TXD_C, GPIO_FN_GLO_I1_D,
+	GPIO_FN_SSI_SDATA1, GPIO_FN_SDA1_B,
+	GPIO_FN_SDA8_B, GPIO_FN_MSIOF2_RXD_C,
+	GPIO_FN_SSI_SCK2, GPIO_FN_SCL2, GPIO_FN_GPS_CLK_B,
+	GPIO_FN_GLO_Q0_D, GPIO_FN_HSCK1_E,
+	GPIO_FN_SSI_WS2, GPIO_FN_SDA2, GPIO_FN_GPS_SIGN_B,
+	GPIO_FN_RX2_E, GPIO_FN_GLO_Q1_D, GPIO_FN_HCTS1_N_E,
+	GPIO_FN_SSI_SDATA2, GPIO_FN_GPS_MAG_B,
+	GPIO_FN_TX2_E, GPIO_FN_HRTS1_N_E,
+	GPIO_FN_SSI_SCK34, GPIO_FN_SSI_WS34, GPIO_FN_SSI_SDATA3,
+	GPIO_FN_SSI_SCK4, GPIO_FN_GLO_SS_D,
+	GPIO_FN_SSI_WS4, GPIO_FN_GLO_RFON_D,
+	GPIO_FN_SSI_SDATA4, GPIO_FN_MSIOF2_SCK_D,
+	GPIO_FN_SSI_SCK5, GPIO_FN_MSIOF1_SCK_C,
+	GPIO_FN_TS_SDATA0, GPIO_FN_GLO_I0,
+	GPIO_FN_MSIOF2_SYNC_D, GPIO_FN_VI1_R2_B,
+
+	/* IPSR5 */
+	GPIO_FN_SSI_WS5, GPIO_FN_MSIOF1_SYNC_C, GPIO_FN_TS_SCK0,
+	GPIO_FN_GLO_I1, GPIO_FN_MSIOF2_TXD_D, GPIO_FN_VI1_R3_B,
+	GPIO_FN_SSI_SDATA5, GPIO_FN_MSIOF1_TXD_C, GPIO_FN_TS_SDEN0,
+	GPIO_FN_GLO_Q0, GPIO_FN_MSIOF2_SS1_D, GPIO_FN_VI1_R4_B,
+	GPIO_FN_SSI_SCK6, GPIO_FN_MSIOF1_RXD_C, GPIO_FN_TS_SPSYNC0,
+	GPIO_FN_GLO_Q1, GPIO_FN_MSIOF2_RXD_D, GPIO_FN_VI1_R5_B,
+	GPIO_FN_SSI_WS6, GPIO_FN_GLO_SCLK,
+	GPIO_FN_MSIOF2_SS2_D, GPIO_FN_VI1_R6_B,
+	GPIO_FN_SSI_SDATA6, GPIO_FN_STP_IVCXO27_0_B,
+	GPIO_FN_GLO_SDATA, GPIO_FN_VI1_R7_B,
+	GPIO_FN_SSI_SCK78, GPIO_FN_STP_ISCLK_0_B, GPIO_FN_GLO_SS,
+	GPIO_FN_SSI_WS78, GPIO_FN_TX0_D, GPIO_FN_STP_ISD_0_B, GPIO_FN_GLO_RFON,
+	GPIO_FN_SSI_SDATA7, GPIO_FN_RX0_D, GPIO_FN_STP_ISEN_0_B,
+	GPIO_FN_SSI_SDATA8, GPIO_FN_TX1_D, GPIO_FN_STP_ISSYNC_0_B,
+	GPIO_FN_SSI_SCK9, GPIO_FN_RX1_D, GPIO_FN_GLO_SCLK_D,
+	GPIO_FN_SSI_WS9, GPIO_FN_TX3_D, GPIO_FN_CAN0_TX_D, GPIO_FN_GLO_SDATA_D,
+	GPIO_FN_SSI_SDATA9, GPIO_FN_RX3_D, GPIO_FN_CAN0_RX_D,
+
+	/* IPSR6 */
+	GPIO_FN_AUDIO_CLKB, GPIO_FN_STP_OPWM_0_B, GPIO_FN_MSIOF1_SCK_B,
+	GPIO_FN_SCIF_CLK, GPIO_FN_BPFCLK_E,
+	GPIO_FN_AUDIO_CLKC, GPIO_FN_SCIFB0_SCK_C, GPIO_FN_MSIOF1_SYNC_B,
+	GPIO_FN_RX2, GPIO_FN_SCIFA2_RXD, GPIO_FN_FMIN_E,
+	GPIO_FN_AUDIO_CLKOUT, GPIO_FN_MSIOF1_SS1_B,
+	GPIO_FN_TX2, GPIO_FN_SCIFA2_TXD,
+	GPIO_FN_IRQ0, GPIO_FN_SCIFB1_RXD_D, GPIO_FN_INTC_IRQ0_N,
+	GPIO_FN_IRQ1, GPIO_FN_SCIFB1_SCK_C, GPIO_FN_INTC_IRQ1_N,
+	GPIO_FN_IRQ2, GPIO_FN_SCIFB1_TXD_D, GPIO_FN_INTC_IRQ2_N,
+	GPIO_FN_IRQ3, GPIO_FN_SCL4_C,
+	GPIO_FN_MSIOF2_TXD_E, GPIO_FN_INTC_IRQ3_N,
+	GPIO_FN_IRQ4, GPIO_FN_HRX1_C, GPIO_FN_SDA4_C,
+	GPIO_FN_MSIOF2_RXD_E, GPIO_FN_INTC_IRQ4_N,
+	GPIO_FN_IRQ5, GPIO_FN_HTX1_C, GPIO_FN_SCL1_E, GPIO_FN_MSIOF2_SCK_E,
+	GPIO_FN_IRQ6, GPIO_FN_HSCK1_C, GPIO_FN_MSIOF1_SS2_B,
+	GPIO_FN_SDA1_E, GPIO_FN_MSIOF2_SYNC_E,
+	GPIO_FN_IRQ7, GPIO_FN_HCTS1_N_C, GPIO_FN_MSIOF1_TXD_B,
+	GPIO_FN_GPS_CLK_C, GPIO_FN_GPS_CLK_D,
+	GPIO_FN_IRQ8, GPIO_FN_HRTS1_N_C, GPIO_FN_MSIOF1_RXD_B,
+	GPIO_FN_GPS_SIGN_C, GPIO_FN_GPS_SIGN_D,
+
+	/* IPSR7 */
+	GPIO_FN_IRQ9, GPIO_FN_DU1_DOTCLKIN_B, GPIO_FN_CAN_CLK_D,
+	GPIO_FN_GPS_MAG_C, GPIO_FN_SCIF_CLK_B, GPIO_FN_GPS_MAG_D,
+	GPIO_FN_DU1_DR0, GPIO_FN_LCDOUT0, GPIO_FN_VI1_DATA0_B, GPIO_FN_TX0_B,
+	GPIO_FN_SCIFA0_TXD_B, GPIO_FN_MSIOF2_SCK_B,
+	GPIO_FN_DU1_DR1, GPIO_FN_LCDOUT1, GPIO_FN_VI1_DATA1_B, GPIO_FN_RX0_B,
+	GPIO_FN_SCIFA0_RXD_B, GPIO_FN_MSIOF2_SYNC_B,
+	GPIO_FN_DU1_DR2, GPIO_FN_LCDOUT2, GPIO_FN_SSI_SCK0129_B,
+	GPIO_FN_DU1_DR3, GPIO_FN_LCDOUT3, GPIO_FN_SSI_WS0129_B,
+	GPIO_FN_DU1_DR4, GPIO_FN_LCDOUT4, GPIO_FN_SSI_SDATA0_B,
+	GPIO_FN_DU1_DR5, GPIO_FN_LCDOUT5, GPIO_FN_SSI_SCK1_B,
+	GPIO_FN_DU1_DR6, GPIO_FN_LCDOUT6, GPIO_FN_SSI_WS1_B,
+	GPIO_FN_DU1_DR7, GPIO_FN_LCDOUT7, GPIO_FN_SSI_SDATA1_B,
+	GPIO_FN_DU1_DG0, GPIO_FN_LCDOUT8, GPIO_FN_VI1_DATA2_B, GPIO_FN_TX1_B,
+	GPIO_FN_SCIFA1_TXD_B, GPIO_FN_MSIOF2_SS1_B,
+	GPIO_FN_DU1_DG1, GPIO_FN_LCDOUT9, GPIO_FN_VI1_DATA3_B, GPIO_FN_RX1_B,
+	GPIO_FN_SCIFA1_RXD_B, GPIO_FN_MSIOF2_SS2_B,
+	GPIO_FN_DU1_DG2, GPIO_FN_LCDOUT10, GPIO_FN_VI1_DATA4_B,
+	GPIO_FN_SCIF1_SCK_B, GPIO_FN_SCIFA1_SCK, GPIO_FN_SSI_SCK78_B,
+
+	/* IPSR8 */
+	GPIO_FN_DU1_DG3, GPIO_FN_LCDOUT11,
+	GPIO_FN_VI1_DATA5_B, GPIO_FN_SSI_WS78_B,
+	GPIO_FN_DU1_DG4, GPIO_FN_LCDOUT12, GPIO_FN_VI1_DATA6_B,
+	GPIO_FN_HRX0_B, GPIO_FN_SCIFB2_RXD_B, GPIO_FN_SSI_SDATA7_B,
+	GPIO_FN_DU1_DG5, GPIO_FN_LCDOUT13, GPIO_FN_VI1_DATA7_B,
+	GPIO_FN_HCTS0_N_B, GPIO_FN_SCIFB2_TXD_B, GPIO_FN_SSI_SDATA8_B,
+	GPIO_FN_DU1_DG6, GPIO_FN_LCDOUT14, GPIO_FN_HRTS0_N_B,
+	GPIO_FN_SCIFB2_CTS_N_B, GPIO_FN_SSI_SCK9_B,
+	GPIO_FN_DU1_DG7, GPIO_FN_LCDOUT15, GPIO_FN_HTX0_B,
+	GPIO_FN_SCIFB2_RTS_N_B, GPIO_FN_SSI_WS9_B,
+	GPIO_FN_DU1_DB0, GPIO_FN_LCDOUT16, GPIO_FN_VI1_CLK_B, GPIO_FN_TX2_B,
+	GPIO_FN_SCIFA2_TXD_B, GPIO_FN_MSIOF2_TXD_B,
+	GPIO_FN_DU1_DB1, GPIO_FN_LCDOUT17, GPIO_FN_VI1_HSYNC_N_B,
+	GPIO_FN_RX2_B, GPIO_FN_SCIFA2_RXD_B, GPIO_FN_MSIOF2_RXD_B,
+	GPIO_FN_DU1_DB2, GPIO_FN_LCDOUT18, GPIO_FN_VI1_VSYNC_N_B,
+	GPIO_FN_SCIF2_SCK_B, GPIO_FN_SCIFA2_SCK, GPIO_FN_SSI_SDATA9_B,
+	GPIO_FN_DU1_DB3, GPIO_FN_LCDOUT19, GPIO_FN_VI1_CLKENB_B,
+	GPIO_FN_DU1_DB4, GPIO_FN_LCDOUT20,
+	GPIO_FN_VI1_FIELD_B, GPIO_FN_CAN1_RX,
+	GPIO_FN_DU1_DB5, GPIO_FN_LCDOUT21, GPIO_FN_TX3,
+	GPIO_FN_SCIFA3_TXD, GPIO_FN_CAN1_TX,
+
+	/* IPSR9 */
+	GPIO_FN_DU1_DB6, GPIO_FN_LCDOUT22, GPIO_FN_SCL3_C,
+	GPIO_FN_RX3, GPIO_FN_SCIFA3_RXD,
+	GPIO_FN_DU1_DB7, GPIO_FN_LCDOUT23, GPIO_FN_SDA3_C,
+	GPIO_FN_SCIF3_SCK, GPIO_FN_SCIFA3_SCK,
+	GPIO_FN_DU1_DOTCLKIN, GPIO_FN_QSTVA_QVS,
+	GPIO_FN_DU1_DOTCLKOUT0, GPIO_FN_QCLK,
+	GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_QSTVB_QVE, GPIO_FN_CAN0_TX,
+	GPIO_FN_TX3_B, GPIO_FN_SCL2_B, GPIO_FN_PWM4,
+	GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_QSTH_QHS,
+	GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_QSTB_QHE,
+	GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+	GPIO_FN_CAN0_RX, GPIO_FN_RX3_B, GPIO_FN_SDA2_B,
+	GPIO_FN_DU1_DISP, GPIO_FN_QPOLA,
+	GPIO_FN_DU1_CDE, GPIO_FN_QPOLB, GPIO_FN_PWM4_B,
+	GPIO_FN_VI0_CLKENB, GPIO_FN_TX4,
+	GPIO_FN_SCIFA4_TXD, GPIO_FN_TS_SDATA0_D,
+	GPIO_FN_VI0_FIELD, GPIO_FN_RX4, GPIO_FN_SCIFA4_RXD, GPIO_FN_TS_SCK0_D,
+	GPIO_FN_VI0_HSYNC_N, GPIO_FN_TX5,
+	GPIO_FN_SCIFA5_TXD, GPIO_FN_TS_SDEN0_D,
+	GPIO_FN_VI0_VSYNC_N, GPIO_FN_RX5,
+	GPIO_FN_SCIFA5_RXD, GPIO_FN_TS_SPSYNC0_D,
+	GPIO_FN_VI0_DATA3_VI0_B3, GPIO_FN_SCIF3_SCK_B, GPIO_FN_SCIFA3_SCK_B,
+	GPIO_FN_VI0_G0, GPIO_FN_SCL8, GPIO_FN_STP_IVCXO27_0_C, GPIO_FN_SCL4,
+	GPIO_FN_HCTS2_N, GPIO_FN_SCIFB2_CTS_N, GPIO_FN_ATAWR1_N,
+
+	/* IPSR10 */
+	GPIO_FN_VI0_G1, GPIO_FN_SDA8, GPIO_FN_STP_ISCLK_0_C, GPIO_FN_SDA4,
+	GPIO_FN_HRTS2_N, GPIO_FN_SCIFB2_RTS_N, GPIO_FN_ATADIR1_N,
+	GPIO_FN_VI0_G2, GPIO_FN_VI2_HSYNC_N, GPIO_FN_STP_ISD_0_C,
+	GPIO_FN_SCL3_B, GPIO_FN_HSCK2, GPIO_FN_SCIFB2_SCK, GPIO_FN_ATARD1_N,
+	GPIO_FN_VI0_G3, GPIO_FN_VI2_VSYNC_N, GPIO_FN_STP_ISEN_0_C,
+	GPIO_FN_SDA3_B, GPIO_FN_HRX2, GPIO_FN_SCIFB2_RXD, GPIO_FN_ATACS01_N,
+	GPIO_FN_VI0_G4, GPIO_FN_VI2_CLKENB, GPIO_FN_STP_ISSYNC_0_C,
+	GPIO_FN_HTX2, GPIO_FN_SCIFB2_TXD, GPIO_FN_SCIFB0_SCK_D,
+	GPIO_FN_VI0_G5, GPIO_FN_VI2_FIELD, GPIO_FN_STP_OPWM_0_C,
+	GPIO_FN_FMCLK_D, GPIO_FN_CAN0_TX_E,
+	GPIO_FN_HTX1_D, GPIO_FN_SCIFB0_TXD_D,
+	GPIO_FN_VI0_G6, GPIO_FN_VI2_CLK, GPIO_FN_BPFCLK_D,
+	GPIO_FN_VI0_G7, GPIO_FN_VI2_DATA0, GPIO_FN_FMIN_D,
+	GPIO_FN_VI0_R0, GPIO_FN_VI2_DATA1, GPIO_FN_GLO_I0_B,
+	GPIO_FN_TS_SDATA0_C, GPIO_FN_ATACS11_N,
+	GPIO_FN_VI0_R1, GPIO_FN_VI2_DATA2, GPIO_FN_GLO_I1_B,
+	GPIO_FN_TS_SCK0_C, GPIO_FN_ATAG1_N,
+	GPIO_FN_VI0_R2, GPIO_FN_VI2_DATA3,
+	GPIO_FN_GLO_Q0_B, GPIO_FN_TS_SDEN0_C,
+	GPIO_FN_VI0_R3, GPIO_FN_VI2_DATA4,
+	GPIO_FN_GLO_Q1_B, GPIO_FN_TS_SPSYNC0_C,
+	GPIO_FN_VI0_R4, GPIO_FN_VI2_DATA5, GPIO_FN_GLO_SCLK_B,
+	GPIO_FN_TX0_C, GPIO_FN_SCL1_D,
+
+	/* IPSR11 */
+	GPIO_FN_VI0_R5, GPIO_FN_VI2_DATA6, GPIO_FN_GLO_SDATA_B,
+	GPIO_FN_RX0_C, GPIO_FN_SDA1_D,
+	GPIO_FN_VI0_R6, GPIO_FN_VI2_DATA7, GPIO_FN_GLO_SS_B,
+	GPIO_FN_TX1_C, GPIO_FN_SCL4_B,
+	GPIO_FN_VI0_R7, GPIO_FN_GLO_RFON_B, GPIO_FN_RX1_C, GPIO_FN_CAN0_RX_E,
+	GPIO_FN_SDA4_B, GPIO_FN_HRX1_D, GPIO_FN_SCIFB0_RXD_D,
+	GPIO_FN_VI1_HSYNC_N, GPIO_FN_AVB_RXD0, GPIO_FN_TS_SDATA0_B,
+	GPIO_FN_TX4_B, GPIO_FN_SCIFA4_TXD_B,
+	GPIO_FN_VI1_VSYNC_N, GPIO_FN_AVB_RXD1, GPIO_FN_TS_SCK0_B,
+	GPIO_FN_RX4_B, GPIO_FN_SCIFA4_RXD_B,
+	GPIO_FN_VI1_CLKENB, GPIO_FN_AVB_RXD2, GPIO_FN_TS_SDEN0_B,
+	GPIO_FN_VI1_FIELD, GPIO_FN_AVB_RXD3, GPIO_FN_TS_SPSYNC0_B,
+	GPIO_FN_VI1_CLK, GPIO_FN_AVB_RXD4, GPIO_FN_VI1_DATA0, GPIO_FN_AVB_RXD5,
+	GPIO_FN_VI1_DATA1, GPIO_FN_AVB_RXD6,
+	GPIO_FN_VI1_DATA2, GPIO_FN_AVB_RXD7,
+	GPIO_FN_VI1_DATA3, GPIO_FN_AVB_RX_ER,
+	GPIO_FN_VI1_DATA4, GPIO_FN_AVB_MDIO,
+	GPIO_FN_VI1_DATA5, GPIO_FN_AVB_RX_DV,
+	GPIO_FN_VI1_DATA6, GPIO_FN_AVB_MAGIC,
+	GPIO_FN_VI1_DATA7, GPIO_FN_AVB_MDC,
+	GPIO_FN_ETH_MDIO, GPIO_FN_AVB_RX_CLK, GPIO_FN_SCL2_C,
+	GPIO_FN_ETH_CRS_DV, GPIO_FN_AVB_LINK, GPIO_FN_SDA2_C,
+
+	/* IPSR12 */
+	GPIO_FN_ETH_RX_ER, GPIO_FN_AVB_CRS, GPIO_FN_SCL3, GPIO_FN_SCL7,
+	GPIO_FN_ETH_RXD0, GPIO_FN_AVB_PHY_INT, GPIO_FN_SDA3, GPIO_FN_SDA7,
+	GPIO_FN_ETH_RXD1, GPIO_FN_AVB_GTXREFCLK, GPIO_FN_CAN0_TX_C,
+	GPIO_FN_SCL2_D, GPIO_FN_MSIOF1_RXD_E,
+	GPIO_FN_ETH_LINK, GPIO_FN_AVB_TXD0, GPIO_FN_CAN0_RX_C,
+	GPIO_FN_SDA2_D, GPIO_FN_MSIOF1_SCK_E,
+	GPIO_FN_ETH_REFCLK, GPIO_FN_AVB_TXD1, GPIO_FN_SCIFA3_RXD_B,
+	GPIO_FN_CAN1_RX_C, GPIO_FN_MSIOF1_SYNC_E,
+	GPIO_FN_ETH_TXD1, GPIO_FN_AVB_TXD2, GPIO_FN_SCIFA3_TXD_B,
+	GPIO_FN_CAN1_TX_C, GPIO_FN_MSIOF1_TXD_E,
+	GPIO_FN_ETH_TX_EN, GPIO_FN_AVB_TXD3,
+	GPIO_FN_TCLK1_B, GPIO_FN_CAN_CLK_B,
+	GPIO_FN_ETH_MAGIC, GPIO_FN_AVB_TXD4, GPIO_FN_IETX_C,
+	GPIO_FN_ETH_TXD0, GPIO_FN_AVB_TXD5, GPIO_FN_IECLK_C,
+	GPIO_FN_ETH_MDC, GPIO_FN_AVB_TXD6, GPIO_FN_IERX_C,
+	GPIO_FN_STP_IVCXO27_0, GPIO_FN_AVB_TXD7, GPIO_FN_SCIFB2_TXD_D,
+	GPIO_FN_ADIDATA_B, GPIO_FN_MSIOF0_SYNC_C,
+	GPIO_FN_STP_ISCLK_0, GPIO_FN_AVB_TX_EN, GPIO_FN_SCIFB2_RXD_D,
+	GPIO_FN_ADICS_SAMP_B, GPIO_FN_MSIOF0_SCK_C,
+
+	/* IPSR13 */
+	GPIO_FN_STP_ISD_0, GPIO_FN_AVB_TX_ER, GPIO_FN_SCIFB2_SCK_C,
+	GPIO_FN_ADICLK_B, GPIO_FN_MSIOF0_SS1_C,
+	GPIO_FN_STP_ISEN_0, GPIO_FN_AVB_TX_CLK,
+	GPIO_FN_ADICHS0_B, GPIO_FN_MSIOF0_SS2_C,
+	GPIO_FN_STP_ISSYNC_0, GPIO_FN_AVB_COL,
+	GPIO_FN_ADICHS1_B, GPIO_FN_MSIOF0_RXD_C,
+	GPIO_FN_STP_OPWM_0, GPIO_FN_AVB_GTX_CLK, GPIO_FN_PWM0_B,
+	GPIO_FN_ADICHS2_B, GPIO_FN_MSIOF0_TXD_C,
+	GPIO_FN_SD0_CLK, GPIO_FN_SPCLK_B, GPIO_FN_SD0_CMD, GPIO_FN_MOSI_IO0_B,
+	GPIO_FN_SD0_DATA0, GPIO_FN_MISO_IO1_B,
+	GPIO_FN_SD0_DATA1, GPIO_FN_IO2_B,
+	GPIO_FN_SD0_DATA2, GPIO_FN_IO3_B, GPIO_FN_SD0_DATA3, GPIO_FN_SSL_B,
+	GPIO_FN_SD0_CD, GPIO_FN_MMC_D6_B,
+	GPIO_FN_SIM0_RST_B, GPIO_FN_CAN0_RX_F,
+	GPIO_FN_SCIFA5_TXD_B, GPIO_FN_TX3_C,
+	GPIO_FN_SD0_WP, GPIO_FN_MMC_D7_B, GPIO_FN_SIM0_D_B, GPIO_FN_CAN0_TX_F,
+	GPIO_FN_SCIFA5_RXD_B, GPIO_FN_RX3_C,
+	GPIO_FN_SD1_CMD, GPIO_FN_REMOCON_B,
+	GPIO_FN_SD1_DATA0, GPIO_FN_SPEEDIN_B,
+	GPIO_FN_SD1_DATA1, GPIO_FN_IETX_B, GPIO_FN_SD1_DATA2, GPIO_FN_IECLK_B,
+	GPIO_FN_SD1_DATA3, GPIO_FN_IERX_B,
+	GPIO_FN_SD1_CD, GPIO_FN_PWM0, GPIO_FN_TPU_TO0, GPIO_FN_SCL1_C,
+
+	/* IPSR14 */
+	GPIO_FN_SD1_WP, GPIO_FN_PWM1_B, GPIO_FN_SDA1_C,
+	GPIO_FN_SD2_CLK, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CMD, GPIO_FN_MMC_CMD,
+	GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D1,
+	GPIO_FN_SD2_DATA2, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D3,
+	GPIO_FN_SD2_CD, GPIO_FN_MMC_D4, GPIO_FN_SCL8_C,
+	GPIO_FN_TX5_B, GPIO_FN_SCIFA5_TXD_C,
+	GPIO_FN_SD2_WP, GPIO_FN_MMC_D5, GPIO_FN_SDA8_C,
+	GPIO_FN_RX5_B, GPIO_FN_SCIFA5_RXD_C,
+	GPIO_FN_MSIOF0_SCK, GPIO_FN_RX2_C, GPIO_FN_ADIDATA,
+	GPIO_FN_VI1_CLK_C, GPIO_FN_VI1_G0_B,
+	GPIO_FN_MSIOF0_SYNC, GPIO_FN_TX2_C, GPIO_FN_ADICS_SAMP,
+	GPIO_FN_VI1_CLKENB_C, GPIO_FN_VI1_G1_B,
+	GPIO_FN_MSIOF0_TXD, GPIO_FN_ADICLK,
+	GPIO_FN_VI1_FIELD_C, GPIO_FN_VI1_G2_B,
+	GPIO_FN_MSIOF0_RXD, GPIO_FN_ADICHS0,
+	GPIO_FN_VI1_DATA0_C, GPIO_FN_VI1_G3_B,
+	GPIO_FN_MSIOF0_SS1, GPIO_FN_MMC_D6, GPIO_FN_ADICHS1, GPIO_FN_TX0_E,
+	GPIO_FN_VI1_HSYNC_N_C, GPIO_FN_SCL7_C, GPIO_FN_VI1_G4_B,
+	GPIO_FN_MSIOF0_SS2, GPIO_FN_MMC_D7, GPIO_FN_ADICHS2, GPIO_FN_RX0_E,
+	GPIO_FN_VI1_VSYNC_N_C, GPIO_FN_SDA7_C, GPIO_FN_VI1_G5_B,
+
+	/* IPSR15 */
+	GPIO_FN_SIM0_RST, GPIO_FN_IETX, GPIO_FN_CAN1_TX_D,
+	GPIO_FN_SIM0_CLK, GPIO_FN_IECLK, GPIO_FN_CAN_CLK_C,
+	GPIO_FN_SIM0_D, GPIO_FN_IERX, GPIO_FN_CAN1_RX_D,
+	GPIO_FN_GPS_CLK, GPIO_FN_DU1_DOTCLKIN_C, GPIO_FN_AUDIO_CLKB_B,
+	GPIO_FN_PWM5_B, GPIO_FN_SCIFA3_TXD_C,
+	GPIO_FN_GPS_SIGN, GPIO_FN_TX4_C, GPIO_FN_SCIFA4_TXD_C, GPIO_FN_PWM5,
+	GPIO_FN_VI1_G6_B, GPIO_FN_SCIFA3_RXD_C,
+	GPIO_FN_GPS_MAG, GPIO_FN_RX4_C, GPIO_FN_SCIFA4_RXD_C, GPIO_FN_PWM6,
+	GPIO_FN_VI1_G7_B, GPIO_FN_SCIFA3_SCK_C,
+	GPIO_FN_HCTS0_N, GPIO_FN_SCIFB0_CTS_N, GPIO_FN_GLO_I0_C,
+	GPIO_FN_TCLK1, GPIO_FN_VI1_DATA1_C,
+	GPIO_FN_HRTS0_N, GPIO_FN_SCIFB0_RTS_N,
+	GPIO_FN_GLO_I1_C, GPIO_FN_VI1_DATA2_C,
+	GPIO_FN_HSCK0, GPIO_FN_SCIFB0_SCK, GPIO_FN_GLO_Q0_C, GPIO_FN_CAN_CLK,
+	GPIO_FN_TCLK2, GPIO_FN_VI1_DATA3_C,
+	GPIO_FN_HRX0, GPIO_FN_SCIFB0_RXD, GPIO_FN_GLO_Q1_C,
+	GPIO_FN_CAN0_RX_B, GPIO_FN_VI1_DATA4_C,
+	GPIO_FN_HTX0, GPIO_FN_SCIFB0_TXD, GPIO_FN_GLO_SCLK_C,
+	GPIO_FN_CAN0_TX_B, GPIO_FN_VI1_DATA5_C,
+
+	/* IPSR16 */
+	GPIO_FN_HRX1, GPIO_FN_SCIFB1_RXD, GPIO_FN_VI1_R0_B,
+	GPIO_FN_GLO_SDATA_C, GPIO_FN_VI1_DATA6_C,
+	GPIO_FN_HTX1, GPIO_FN_SCIFB1_TXD, GPIO_FN_VI1_R1_B,
+	GPIO_FN_GLO_SS_C, GPIO_FN_VI1_DATA7_C,
+	GPIO_FN_HSCK1, GPIO_FN_SCIFB1_SCK, GPIO_FN_MLB_CK, GPIO_FN_GLO_RFON_C,
+	GPIO_FN_HCTS1_N, GPIO_FN_SCIFB1_CTS_N,
+	GPIO_FN_MLB_SIG, GPIO_FN_CAN1_TX_B,
+	GPIO_FN_HRTS1_N, GPIO_FN_SCIFB1_RTS_N,
+	GPIO_FN_MLB_DAT, GPIO_FN_CAN1_RX_B,
+};
+
+#endif /* __ASM_R8A7791_H__ */
diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
new file mode 100644
index 0000000..2afda0a
--- /dev/null
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -0,0 +1,664 @@
+/*
+ * arch/arm/include/asm/arch-rmobile/r8a7791.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __ASM_ARCH_R8A7791_H
+#define __ASM_ARCH_R8A7791_H
+
+/*
+ * R8A7791 I/O Addresses
+ */
+#define	RWDT_BASE	0xE6020000
+#define	SWDT_BASE	0xE6030000
+#define	LBSC_BASE	0xFEC00200
+#define DBSC3_0_BASE	0xE6790000
+#define DBSC3_1_BASE	0xE67A0000
+#define TMU_BASE	0xE61E0000
+#define	GPIO5_BASE	0xE6055000
+
+#define S3C_BASE	0xE6784000
+#define S3C_INT_BASE	0xE6784A00
+#define S3C_MEDIA_BASE	0xE6784B00
+
+#define S3C_QOS_DCACHE_BASE	0xE6784BDC
+#define S3C_QOS_CCI0_BASE	0xE6784C00
+#define S3C_QOS_CCI1_BASE	0xE6784C24
+#define S3C_QOS_MXI_BASE	0xE6784C48
+#define S3C_QOS_AXI_BASE	0xE6784C6C
+
+#define DBSC3_0_QOS_R0_BASE	0xE6791000
+#define DBSC3_0_QOS_R1_BASE	0xE6791100
+#define DBSC3_0_QOS_R2_BASE	0xE6791200
+#define DBSC3_0_QOS_R3_BASE	0xE6791300
+#define DBSC3_0_QOS_R4_BASE	0xE6791400
+#define DBSC3_0_QOS_R5_BASE	0xE6791500
+#define DBSC3_0_QOS_R6_BASE	0xE6791600
+#define DBSC3_0_QOS_R7_BASE	0xE6791700
+#define DBSC3_0_QOS_R8_BASE	0xE6791800
+#define DBSC3_0_QOS_R9_BASE	0xE6791900
+#define DBSC3_0_QOS_R10_BASE	0xE6791A00
+#define DBSC3_0_QOS_R11_BASE	0xE6791B00
+#define DBSC3_0_QOS_R12_BASE	0xE6791C00
+#define DBSC3_0_QOS_R13_BASE	0xE6791D00
+#define DBSC3_0_QOS_R14_BASE	0xE6791E00
+#define DBSC3_0_QOS_R15_BASE	0xE6791F00
+#define DBSC3_0_QOS_W0_BASE	0xE6792000
+#define DBSC3_0_QOS_W1_BASE	0xE6792100
+#define DBSC3_0_QOS_W2_BASE	0xE6792200
+#define DBSC3_0_QOS_W3_BASE	0xE6792300
+#define DBSC3_0_QOS_W4_BASE	0xE6792400
+#define DBSC3_0_QOS_W5_BASE	0xE6792500
+#define DBSC3_0_QOS_W6_BASE	0xE6792600
+#define DBSC3_0_QOS_W7_BASE	0xE6792700
+#define DBSC3_0_QOS_W8_BASE	0xE6792800
+#define DBSC3_0_QOS_W9_BASE	0xE6792900
+#define DBSC3_0_QOS_W10_BASE	0xE6792A00
+#define DBSC3_0_QOS_W11_BASE	0xE6792B00
+#define DBSC3_0_QOS_W12_BASE	0xE6792C00
+#define DBSC3_0_QOS_W13_BASE	0xE6792D00
+#define DBSC3_0_QOS_W14_BASE	0xE6792E00
+#define DBSC3_0_QOS_W15_BASE	0xE6792F00
+
+#define DBSC3_1_QOS_R0_BASE	0xE67A1000
+#define DBSC3_1_QOS_R1_BASE	0xE67A1100
+#define DBSC3_1_QOS_R2_BASE	0xE67A1200
+#define DBSC3_1_QOS_R3_BASE	0xE67A1300
+#define DBSC3_1_QOS_R4_BASE	0xE67A1400
+#define DBSC3_1_QOS_R5_BASE	0xE67A1500
+#define DBSC3_1_QOS_R6_BASE	0xE67A1600
+#define DBSC3_1_QOS_R7_BASE	0xE67A1700
+#define DBSC3_1_QOS_R8_BASE	0xE67A1800
+#define DBSC3_1_QOS_R9_BASE	0xE67A1900
+#define DBSC3_1_QOS_R10_BASE	0xE67A1A00
+#define DBSC3_1_QOS_R11_BASE	0xE67A1B00
+#define DBSC3_1_QOS_R12_BASE	0xE67A1C00
+#define DBSC3_1_QOS_R13_BASE	0xE67A1D00
+#define DBSC3_1_QOS_R14_BASE	0xE67A1E00
+#define DBSC3_1_QOS_R15_BASE	0xE67A1F00
+#define DBSC3_1_QOS_W0_BASE	0xE67A2000
+#define DBSC3_1_QOS_W1_BASE	0xE67A2100
+#define DBSC3_1_QOS_W2_BASE	0xE67A2200
+#define DBSC3_1_QOS_W3_BASE	0xE67A2300
+#define DBSC3_1_QOS_W4_BASE	0xE67A2400
+#define DBSC3_1_QOS_W5_BASE	0xE67A2500
+#define DBSC3_1_QOS_W6_BASE	0xE67A2600
+#define DBSC3_1_QOS_W7_BASE	0xE67A2700
+#define DBSC3_1_QOS_W8_BASE	0xE67A2800
+#define DBSC3_1_QOS_W9_BASE	0xE67A2900
+#define DBSC3_1_QOS_W10_BASE	0xE67A2A00
+#define DBSC3_1_QOS_W11_BASE	0xE67A2B00
+#define DBSC3_1_QOS_W12_BASE	0xE67A2C00
+#define DBSC3_1_QOS_W13_BASE	0xE67A2D00
+#define DBSC3_1_QOS_W14_BASE	0xE67A2E00
+#define DBSC3_1_QOS_W15_BASE	0xE67A2F00
+
+#define DBSC3_0_DBADJ2		0xE67900C8
+
+#define CCI_400_MAXOT_1		0xF0091110
+#define CCI_400_MAXOT_2		0xF0092110
+#define CCI_400_QOSCNTL_1	0xF009110C
+#define CCI_400_QOSCNTL_2	0xF009210C
+
+#define	MXI_BASE		0xFE960000
+#define	MXI_QOS_BASE		0xFE960300
+
+#define SYS_AXI_SYX64TO128_BASE	0xFF800300
+#define SYS_AXI_AVB_BASE	0xFF800340
+#define SYS_AXI_G2D_BASE	0xFF800540
+#define SYS_AXI_IMP0_BASE	0xFF800580
+#define SYS_AXI_IMP1_BASE	0xFF8005C0
+#define SYS_AXI_IMUX0_BASE	0xFF800600
+#define SYS_AXI_IMUX1_BASE	0xFF800640
+#define SYS_AXI_IMUX2_BASE	0xFF800680
+#define SYS_AXI_LBS_BASE	0xFF8006C0
+#define SYS_AXI_MMUDS_BASE	0xFF800700
+#define SYS_AXI_MMUM_BASE	0xFF800740
+#define SYS_AXI_MMUR_BASE	0xFF800780
+#define SYS_AXI_MMUS0_BASE	0xFF8007C0
+#define SYS_AXI_MMUS1_BASE	0xFF800800
+#define SYS_AXI_MTSB0_BASE	0xFF800880
+#define SYS_AXI_MTSB1_BASE	0xFF8008C0
+#define SYS_AXI_PCI_BASE	0xFF800900
+#define SYS_AXI_RTX_BASE	0xFF800940
+#define SYS_AXI_SDS0_BASE	0xFF800A80
+#define SYS_AXI_SDS1_BASE	0xFF800AC0
+#define SYS_AXI_USB20_BASE	0xFF800C00
+#define SYS_AXI_USB21_BASE	0xFF800C40
+#define SYS_AXI_USB22_BASE	0xFF800C80
+#define SYS_AXI_USB30_BASE	0xFF800CC0
+#define SYS_AXI_AX2M_BASE	0xFF800380
+#define SYS_AXI_CC50_BASE	0xFF8003C0
+#define SYS_AXI_CCI_BASE	0xFF800440
+#define SYS_AXI_CS_BASE		0xFF800480
+#define SYS_AXI_DDM_BASE	0xFF8004C0
+#define SYS_AXI_ETH_BASE	0xFF800500
+#define SYS_AXI_MPXM_BASE	0xFF800840
+#define SYS_AXI_SAT0_BASE	0xFF800980
+#define SYS_AXI_SAT1_BASE	0xFF8009C0
+#define SYS_AXI_SDM0_BASE	0xFF800A00
+#define SYS_AXI_SDM1_BASE	0xFF800A40
+#define SYS_AXI_TRAB_BASE	0xFF800B00
+#define SYS_AXI_UDM0_BASE	0xFF800B80
+#define SYS_AXI_UDM1_BASE	0xFF800BC0
+
+#define RT_AXI_SHX_BASE		0xFF810100
+#define RT_AXI_DBG_BASE		0xFF810140
+#define RT_AXI_RDM_BASE		0xFF810180
+#define RT_AXI_RDS_BASE		0xFF8101C0
+#define RT_AXI_RTX64TO128_BASE	0xFF810200
+#define RT_AXI_STPRO_BASE	0xFF810240
+#define RT_AXI_SY2RT_BASE	0xFF810280
+
+#define MP_AXI_ADSP_BASE	0xFF820100
+#define MP_AXI_ASDS0_BASE	0xFF8201C0
+#define MP_AXI_ASDS1_BASE	0xFF820200
+#define MP_AXI_MLP_BASE		0xFF820240
+#define MP_AXI_MMUMP_BASE	0xFF820280
+#define MP_AXI_SPU_BASE		0xFF8202C0
+#define MP_AXI_SPUC_BASE	0xFF820300
+
+#define SYS_AXI256_AXI128TO256_BASE	0xFF860100
+#define SYS_AXI256_SYX_BASE	0xFF860140
+#define SYS_AXI256_MPX_BASE	0xFF860180
+#define SYS_AXI256_MXI_BASE	0xFF8601C0
+
+#define CCI_AXI_MMUS0_BASE	0xFF880100
+#define CCI_AXI_SYX2_BASE	0xFF880140
+#define CCI_AXI_MMUR_BASE	0xFF880180
+#define CCI_AXI_MMUDS_BASE	0xFF8801C0
+#define CCI_AXI_MMUM_BASE	0xFF880200
+#define CCI_AXI_MXI_BASE	0xFF880240
+#define CCI_AXI_MMUS1_BASE	0xFF880280
+#define CCI_AXI_MMUMP_BASE	0xFF8802C0
+
+#define MEDIA_AXI_MXR_BASE	0xFE960080
+#define MEDIA_AXI_MXW_BASE	0xFE9600C0
+#define MEDIA_AXI_JPR_BASE	0xFE964100
+#define MEDIA_AXI_JPW_BASE	0xFE966100
+#define MEDIA_AXI_GCU0R_BASE	0xFE964140
+#define MEDIA_AXI_GCU0W_BASE	0xFE966140
+#define MEDIA_AXI_GCU1R_BASE	0xFE964180
+#define MEDIA_AXI_GCU1W_BASE	0xFE966180
+#define MEDIA_AXI_TDMR_BASE	0xFE964500
+#define MEDIA_AXI_TDMW_BASE	0xFE966500
+#define MEDIA_AXI_VSP0CR_BASE	0xFE964540
+#define MEDIA_AXI_VSP0CW_BASE	0xFE966540
+#define MEDIA_AXI_VSP1CR_BASE	0xFE964580
+#define MEDIA_AXI_VSP1CW_BASE	0xFE966580
+#define MEDIA_AXI_VSPDU0CR_BASE	0xFE9645C0
+#define MEDIA_AXI_VSPDU0CW_BASE	0xFE9665C0
+#define MEDIA_AXI_VSPDU1CR_BASE	0xFE964600
+#define MEDIA_AXI_VSPDU1CW_BASE	0xFE966600
+#define MEDIA_AXI_VIN0W_BASE	0xFE966900
+#define MEDIA_AXI_VSP0R_BASE	0xFE964D00
+#define MEDIA_AXI_VSP0W_BASE	0xFE966D00
+#define MEDIA_AXI_FDP0R_BASE	0xFE964D40
+#define MEDIA_AXI_FDP0W_BASE	0xFE966D40
+#define MEDIA_AXI_IMSR_BASE	0xFE964D80
+#define MEDIA_AXI_IMSW_BASE	0xFE966D80
+#define MEDIA_AXI_VSP1R_BASE	0xFE965100
+#define MEDIA_AXI_VSP1W_BASE	0xFE967100
+#define MEDIA_AXI_FDP1R_BASE	0xFE965140
+#define MEDIA_AXI_FDP1W_BASE	0xFE967140
+#define MEDIA_AXI_IMRR_BASE	0xFE965180
+#define MEDIA_AXI_IMRW_BASE	0xFE967180
+#define MEDIA_AXI_FDP2R_BASE	0xFE9651C0
+#define MEDIA_AXI_FDP2W_BASE	0xFE966DC0
+#define MEDIA_AXI_VSPD0R_BASE	0xFE965500
+#define MEDIA_AXI_VSPD0W_BASE	0xFE967500
+#define MEDIA_AXI_VSPD1R_BASE	0xFE965540
+#define MEDIA_AXI_VSPD1W_BASE	0xFE967540
+#define MEDIA_AXI_DU0R_BASE	0xFE965580
+#define MEDIA_AXI_DU0W_BASE	0xFE967580
+#define MEDIA_AXI_DU1R_BASE	0xFE9655C0
+#define MEDIA_AXI_DU1W_BASE	0xFE9675C0
+#define MEDIA_AXI_VCP0CR_BASE	0xFE965900
+#define MEDIA_AXI_VCP0CW_BASE	0xFE967900
+#define MEDIA_AXI_VCP0VR_BASE	0xFE965940
+#define MEDIA_AXI_VCP0VW_BASE	0xFE967940
+#define MEDIA_AXI_VPC0R_BASE	0xFE965980
+#define MEDIA_AXI_VCP1CR_BASE	0xFE965D00
+#define MEDIA_AXI_VCP1CW_BASE	0xFE967D00
+#define MEDIA_AXI_VCP1VR_BASE	0xFE965D40
+#define MEDIA_AXI_VCP1VW_BASE	0xFE967D40
+#define MEDIA_AXI_VPC1R_BASE	0xFE965D80
+
+#define SYS_AXI_AVBDMSCR	0xFF802000
+#define SYS_AXI_SYX2DMSCR	0xFF802004
+#define SYS_AXI_CC50DMSCR	0xFF802008
+#define SYS_AXI_CC51DMSCR	0xFF80200C
+#define SYS_AXI_CCIDMSCR	0xFF802010
+#define SYS_AXI_CSDMSCR		0xFF802014
+#define SYS_AXI_DDMDMSCR	0xFF802018
+#define SYS_AXI_ETHDMSCR	0xFF80201C
+#define SYS_AXI_G2DDMSCR	0xFF802020
+#define SYS_AXI_IMP0DMSCR	0xFF802024
+#define SYS_AXI_IMP1DMSCR	0xFF802028
+#define SYS_AXI_LBSDMSCR	0xFF80202C
+#define SYS_AXI_MMUDSDMSCR	0xFF802030
+#define SYS_AXI_MMUMXDMSCR	0xFF802034
+#define SYS_AXI_MMURDDMSCR	0xFF802038
+#define SYS_AXI_MMUS0DMSCR	0xFF80203C
+#define SYS_AXI_MMUS1DMSCR	0xFF802040
+#define SYS_AXI_MPXDMSCR	0xFF802044
+#define SYS_AXI_MTSB0DMSCR	0xFF802048
+#define SYS_AXI_MTSB1DMSCR	0xFF80204C
+#define SYS_AXI_PCIDMSCR	0xFF802050
+#define SYS_AXI_RTXDMSCR	0xFF802054
+#define SYS_AXI_SAT0DMSCR	0xFF802058
+#define SYS_AXI_SAT1DMSCR	0xFF80205C
+#define SYS_AXI_SDM0DMSCR	0xFF802060
+#define SYS_AXI_SDM1DMSCR	0xFF802064
+#define SYS_AXI_SDS0DMSCR	0xFF802068
+#define SYS_AXI_SDS1DMSCR	0xFF80206C
+#define SYS_AXI_ETRABDMSCR	0xFF802070
+#define SYS_AXI_ETRKFDMSCR	0xFF802074
+#define SYS_AXI_UDM0DMSCR	0xFF802078
+#define SYS_AXI_UDM1DMSCR	0xFF80207C
+#define SYS_AXI_USB20DMSCR	0xFF802080
+#define SYS_AXI_USB21DMSCR	0xFF802084
+#define SYS_AXI_USB22DMSCR	0xFF802088
+#define SYS_AXI_USB30DMSCR	0xFF80208C
+#define SYS_AXI_X128TO64SLVDMSCR	0xFF802100
+#define SYS_AXI_X64TO128SLVDMSCR	0xFF802104
+#define SYS_AXI_AVBSLVDMSCR	0xFF802108
+#define SYS_AXI_SYX2SLVDMSCR	0xFF80210C
+#define SYS_AXI_ETHSLVDMSCR	0xFF802110
+#define SYS_AXI_GICSLVDMSCR	0xFF802114
+#define SYS_AXI_IMPSLVDMSCR	0xFF802118
+#define SYS_AXI_IMX0SLVDMSCR	0xFF80211C
+#define SYS_AXI_IMX1SLVDMSCR	0xFF802120
+#define SYS_AXI_IMX2SLVDMSCR	0xFF802124
+#define SYS_AXI_LBSSLVDMSCR	0xFF802128
+#define SYS_AXI_MMC0SLVDMSCR	0xFF80212C
+#define SYS_AXI_MMC1SLVDMSCR	0xFF802130
+#define SYS_AXI_MPXSLVDMSCR	0xFF802134
+#define SYS_AXI_MTSB0SLVDMSCR	0xFF802138
+#define SYS_AXI_MTSB1SLVDMSCR	0xFF80213C
+#define SYS_AXI_MXTSLVDMSCR	0xFF802140
+#define SYS_AXI_PCISLVDMSCR	0xFF802144
+#define SYS_AXI_SYAPBSLVDMSCR	0xFF802148
+#define SYS_AXI_QSAPBSLVDMSCR	0xFF80214C
+#define SYS_AXI_RTXSLVDMSCR	0xFF802150
+#define SYS_AXI_SAT0SLVDMSCR	0xFF802168
+#define SYS_AXI_SAT1SLVDMSCR	0xFF80216C
+#define SYS_AXI_SDAP0SLVDMSCR	0xFF802170
+#define SYS_AXI_SDAP1SLVDMSCR	0xFF802174
+#define SYS_AXI_SDAP2SLVDMSCR	0xFF802178
+#define SYS_AXI_SDAP3SLVDMSCR	0xFF80217C
+#define SYS_AXI_SGXSLVDMSCR	0xFF802180
+#define SYS_AXI_STBSLVDMSCR	0xFF802188
+#define SYS_AXI_STMSLVDMSCR	0xFF80218C
+#define SYS_AXI_TSPL0SLVDMSCR	0xFF802194
+#define SYS_AXI_TSPL1SLVDMSCR	0xFF802198
+#define SYS_AXI_TSPL2SLVDMSCR	0xFF80219C
+#define SYS_AXI_USB20SLVDMSCR	0xFF8021A0
+#define SYS_AXI_USB21SLVDMSCR	0xFF8021A4
+#define SYS_AXI_USB22SLVDMSCR	0xFF8021A8
+#define SYS_AXI_USB30SLVDMSCR	0xFF8021AC
+
+#define RT_AXI_CBMDMSCR		0xFF812000
+#define RT_AXI_DBDMSCR		0xFF812004
+#define RT_AXI_RDMDMSCR		0xFF812008
+#define RT_AXI_RDSDMSCR		0xFF81200C
+#define RT_AXI_STRDMSCR		0xFF812010
+#define RT_AXI_SY2RTDMSCR	0xFF812014
+#define RT_AXI_CBSSLVDMSCR	0xFF812100
+#define RT_AXI_DBSSLVDMSCR	0xFF812104
+#define RT_AXI_RTAP1SLVDMSCR	0xFF812108
+#define RT_AXI_RTAP2SLVDMSCR	0xFF81210C
+#define RT_AXI_RTAP3SLVDMSCR	0xFF812110
+#define RT_AXI_RT2SYSLVDMSCR	0xFF812114
+#define RT_AXI_A128TO64SLVDMSCR	0xFF812118
+#define RT_AXI_A64TO128SLVDMSCR	0xFF81211C
+#define RT_AXI_A64TO128CSLVDMSCR	0xFF812120
+#define RT_AXI_UTLBRSLVDMSCR	0xFF812128
+
+#define MP_AXI_ADSPDMSCR	0xFF822000
+#define MP_AXI_ASDM0DMSCR	0xFF822004
+#define MP_AXI_ASDM1DMSCR	0xFF822008
+#define MP_AXI_ASDS0DMSCR	0xFF82200C
+#define MP_AXI_ASDS1DMSCR	0xFF822010
+#define MP_AXI_MLPDMSCR		0xFF822014
+#define MP_AXI_MMUMPDMSCR	0xFF822018
+#define MP_AXI_SPUDMSCR		0xFF82201C
+#define MP_AXI_SPUCDMSCR	0xFF822020
+#define MP_AXI_SY2MPDMSCR	0xFF822024
+#define MP_AXI_ADSPSLVDMSCR	0xFF822100
+#define MP_AXI_MLMSLVDMSCR	0xFF822104
+#define MP_AXI_MPAP4SLVDMSCR	0xFF822108
+#define MP_AXI_MPAP5SLVDMSCR	0xFF82210C
+#define MP_AXI_MPAP6SLVDMSCR	0xFF822110
+#define MP_AXI_MPAP7SLVDMSCR	0xFF822114
+#define MP_AXI_MP2SYSLVDMSCR	0xFF822118
+#define MP_AXI_MP2SY2SLVDMSCR	0xFF82211C
+#define MP_AXI_MPXAPSLVDMSCR	0xFF822124
+#define MP_AXI_SPUSLVDMSCR	0xFF822128
+#define MP_AXI_UTLBMPSLVDMSCR	0xFF82212C
+
+#define ADM_AXI_ASDM0DMSCR	0xFF842000
+#define ADM_AXI_ASDM1DMSCR	0xFF842004
+#define ADM_AXI_MPAP1SLVDMSCR	0xFF842104
+#define ADM_AXI_MPAP2SLVDMSCR	0xFF842108
+#define ADM_AXI_MPAP3SLVDMSCR	0xFF84210C
+
+#define DM_AXI_RDMDMSCR		0xFF852000
+#define DM_AXI_SDM0DMSCR	0xFF852004
+#define DM_AXI_SDM1DMSCR	0xFF852008
+#define DM_AXI_MMAP0SLVDMSCR	0xFF852100
+#define DM_AXI_MMAP1SLVDMSCR	0xFF852104
+#define DM_AXI_QSPAPSLVDMSCR	0xFF852108
+#define DM_AXI_RAP4SLVDMSCR	0xFF85210C
+#define DM_AXI_RAP5SLVDMSCR	0xFF852110
+#define DM_AXI_SAP4SLVDMSCR	0xFF852114
+#define DM_AXI_SAP5SLVDMSCR	0xFF852118
+#define DM_AXI_SAP6SLVDMSCR	0xFF85211C
+#define DM_AXI_SAP65SLVDMSCR	0xFF852120
+#define DM_AXI_SDAP0SLVDMSCR	0xFF852124
+#define DM_AXI_SDAP1SLVDMSCR	0xFF852128
+#define DM_AXI_SDAP2SLVDMSCR	0xFF85212C
+#define DM_AXI_SDAP3SLVDMSCR	0xFF852130
+
+#define SYS_AXI256_SYXDMSCR	0xFF862000
+#define SYS_AXI256_MPXDMSCR	0xFF862004
+#define SYS_AXI256_MXIDMSCR	0xFF862008
+#define SYS_AXI256_X128TO256SLVDMSCR	0xFF862100
+#define SYS_AXI256_X256TO128SLVDMSCR	0xFF862104
+#define SYS_AXI256_SYXSLVDMSCR	0xFF862108
+#define SYS_AXI256_CCXSLVDMSCR	0xFF86210C
+#define SYS_AXI256_S3CSLVDMSCR	0xFF862110
+
+#define MXT_SYXDMSCR		0xFF872000
+#define MXT_CMM0SLVDMSCR	0xFF872100
+#define MXT_CMM1SLVDMSCR	0xFF872104
+#define MXT_CMM2SLVDMSCR	0xFF872108
+#define MXT_FDPSLVDMSCR		0xFF87210C
+#define MXT_IMRSLVDMSCR		0xFF872110
+#define MXT_VINSLVDMSCR		0xFF872114
+#define MXT_VPC0SLVDMSCR	0xFF872118
+#define MXT_VPC1SLVDMSCR	0xFF87211C
+#define MXT_VSP0SLVDMSCR	0xFF872120
+#define MXT_VSP1SLVDMSCR	0xFF872124
+#define MXT_VSPD0SLVDMSCR	0xFF872128
+#define MXT_VSPD1SLVDMSCR	0xFF87212C
+#define MXT_MAP1SLVDMSCR	0xFF872130
+#define MXT_MAP2SLVDMSCR	0xFF872134
+
+#define CCI_AXI_MMUS0DMSCR	0xFF882000
+#define CCI_AXI_SYX2DMSCR	0xFF882004
+#define CCI_AXI_MMURDMSCR	0xFF882008
+#define CCI_AXI_MMUDSDMSCR	0xFF88200C
+#define CCI_AXI_MMUMDMSCR	0xFF882010
+#define CCI_AXI_MXIDMSCR	0xFF882014
+#define CCI_AXI_MMUS1DMSCR	0xFF882018
+#define CCI_AXI_MMUMPDMSCR	0xFF88201C
+#define CCI_AXI_DVMDMSCR	0xFF882020
+#define CCI_AXI_CCISLVDMSCR	0xFF882100
+
+#define CCI_AXI_IPMMUIDVMCR	0xFF880400
+#define CCI_AXI_IPMMURDVMCR	0xFF880404
+#define CCI_AXI_IPMMUS0DVMCR	0xFF880408
+#define CCI_AXI_IPMMUS1DVMCR	0xFF88040C
+#define CCI_AXI_IPMMUMPDVMCR	0xFF880410
+#define CCI_AXI_IPMMUDSDVMCR	0xFF880414
+#define CCI_AXI_AX2ADDRMASK	0xFF88041C
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+/* RWDT */
+struct r8a7791_rwdt {
+	u32 rwtcnt;	/* 0x00 */
+	u32 rwtcsra;	/* 0x04 */
+	u16 rwtcsrb;	/* 0x08 */
+};
+
+/* SWDT */
+struct r8a7791_swdt {
+	u32 swtcnt;	/* 0x00 */
+	u32 swtcsra;	/* 0x04 */
+	u16 swtcsrb;	/* 0x08 */
+};
+
+/* LBSC */
+struct r8a7791_lbsc {
+	u32 cs0ctrl;
+	u32 cs1ctrl;
+	u32 ecs0ctrl;
+	u32 ecs1ctrl;
+	u32 ecs2ctrl;
+	u32 ecs3ctrl;
+	u32 ecs4ctrl;
+	u32 ecs5ctrl;
+	u32 dummy0[4];	/* 0x20 .. 0x2C */
+	u32 cswcr0;
+	u32 cswcr1;
+	u32 ecswcr0;
+	u32 ecswcr1;
+	u32 ecswcr2;
+	u32 ecswcr3;
+	u32 ecswcr4;
+	u32 ecswcr5;
+	u32 exdmawcr0;
+	u32 exdmawcr1;
+	u32 exdmawcr2;
+	u32 dummy1[9];	/* 0x5C .. 0x7C */
+	u32 cspwcr0;
+	u32 cspwcr1;
+	u32 ecspwcr0;
+	u32 ecspwcr1;
+	u32 ecspwcr2;
+	u32 ecspwcr3;
+	u32 ecspwcr4;
+	u32 ecspwcr5;
+	u32 exwtsync;
+	u32 dummy2[3];	/* 0xA4 .. 0xAC */
+	u32 cs0bstctl;
+	u32 cs0btph;
+	u32 dummy3[2];	/* 0xB8 .. 0xBC */
+	u32 cs1gdst;
+	u32 ecs0gdst;
+	u32 ecs1gdst;
+	u32 ecs2gdst;
+	u32 ecs3gdst;
+	u32 ecs4gdst;
+	u32 ecs5gdst;
+	u32 dummy4[5];	/* 0xDC .. 0xEC */
+	u32 exdmaset0;
+	u32 exdmaset1;
+	u32 exdmaset2;
+	u32 dummy5[5];	/* 0xFC .. 0x10C */
+	u32 exdmcr0;
+	u32 exdmcr1;
+	u32 exdmcr2;
+	u32 dummy6[5];	/* 0x11C .. 0x12C */
+	u32 bcintsr;
+	u32 bcintcr;
+	u32 bcintmr;
+	u32 dummy7;	/* 0x13C */
+	u32 exbatlv;
+	u32 exwtsts;
+	u32 dummy8[14];	/* 0x148 .. 0x17C */
+	u32 atacsctrl;
+	u32 dummy9[15]; /* 0x184 .. 0x1BC */
+	u32 exbct;
+	u32 extct;
+};
+
+/* DBSC3 */
+struct r8a7791_dbsc3 {
+	u32 dummy0[3];	/* 0x00 .. 0x08 */
+	u32 dbstate1;
+	u32 dbacen;
+	u32 dbrfen;
+	u32 dbcmd;
+	u32 dbwait;
+	u32 dbkind;
+	u32 dbconf0;
+	u32 dummy1[2];	/* 0x28 .. 0x2C */
+	u32 dbphytype;
+	u32 dummy2[3];	/* 0x34 .. 0x3C */
+	u32 dbtr0;
+	u32 dbtr1;
+	u32 dbtr2;
+	u32 dummy3;	/* 0x4C */
+	u32 dbtr3;
+	u32 dbtr4;
+	u32 dbtr5;
+	u32 dbtr6;
+	u32 dbtr7;
+	u32 dbtr8;
+	u32 dbtr9;
+	u32 dbtr10;
+	u32 dbtr11;
+	u32 dbtr12;
+	u32 dbtr13;
+	u32 dbtr14;
+	u32 dbtr15;
+	u32 dbtr16;
+	u32 dbtr17;
+	u32 dbtr18;
+	u32 dbtr19;
+	u32 dummy4[7];	/* 0x94 .. 0xAC */
+	u32 dbbl;
+	u32 dummy5[3];	/* 0xB4 .. 0xBC */
+	u32 dbadj0;
+	u32 dummy6;	/* 0xC4 */
+	u32 dbadj2;
+	u32 dummy7[5];	/* 0xCC .. 0xDC */
+	u32 dbrfcnf0;
+	u32 dbrfcnf1;
+	u32 dbrfcnf2;
+	u32 dummy8[2];	/* 0xEC .. 0xF0 */
+	u32 dbcalcnf;
+	u32 dbcaltr;
+	u32 dummy9;	/* 0xFC */
+	u32 dbrnk0;
+	u32 dummy10[31];	/* 0x104 .. 0x17C */
+	u32 dbpdncnf;
+	u32 dummy11[47];	/* 0x184 ..0x23C */
+	u32 dbdfistat;
+	u32 dbdficnt;
+	u32 dummy12[14];	/* 0x248 .. 0x27C */
+	u32 dbpdlck;
+	u32 dummy13[3];	/* 0x284 .. 0x28C */
+	u32 dbpdrga;
+	u32 dummy14[3];	/* 0x294 .. 0x29C */
+	u32 dbpdrgd;
+	u32 dummy15[24];	/* 0x2A4 .. 0x300 */
+	u32 dbbs0cnt1;
+	u32 dummy16[30];	/* 0x308 .. 0x37C */
+	u32 dbwt0cnf0;
+	u32 dbwt0cnf1;
+	u32 dbwt0cnf2;
+	u32 dbwt0cnf3;
+	u32 dbwt0cnf4;
+};
+
+/* GPIO */
+struct r8a7791_gpio {
+	u32 iointsel;
+	u32 inoutsel;
+	u32 outdt;
+	u32 indt;
+	u32 intdt;
+	u32 intclr;
+	u32 intmsk;
+	u32 posneg;
+	u32 edglevel;
+	u32 filonoff;
+	u32 intmsks;
+	u32 mskclrs;
+	u32 outdtsel;
+	u32 outdth;
+	u32 outdtl;
+	u32 bothedge;
+};
+
+/* S3C(QoS) */
+struct r8a7791_s3c {
+	u32 s3cexcladdmsk;
+	u32 s3cexclidmsk;
+	u32 s3cadsplcr;
+	u32 s3cmaar;
+	u32 dummy0;	/* 0x10 */
+	u32 s3crorr;
+	u32 s3cworr;
+	u32 s3carcr22;
+	u32 dummy1[2];	/* 0x20 .. 0x24 */
+	u32 s3cmctr;
+	u32 dummy2;	/* 0x2C */
+	u32 cconf0;
+	u32 cconf1;
+	u32 cconf2;
+	u32 cconf3;
+};
+
+struct r8a7791_s3c_qos {
+	u32 s3cqos0;
+	u32 s3cqos1;
+	u32 s3cqos2;
+	u32 s3cqos3;
+	u32 s3cqos4;
+	u32 s3cqos5;
+	u32 s3cqos6;
+	u32 s3cqos7;
+	u32 s3cqos8;
+};
+
+/* DBSC(QoS) */
+struct r8a7791_dbsc3_qos {
+	u32 dblgcnt;
+	u32 dbtmval0;
+	u32 dbtmval1;
+	u32 dbtmval2;
+	u32 dbtmval3;
+	u32 dbrqctr;
+	u32 dbthres0;
+	u32 dbthres1;
+	u32 dbthres2;
+	u32 dummy0;	/* 0x24 */
+	u32 dblgqon;
+};
+
+/* MXI(QoS) */
+struct r8a7791_mxi {
+	u32 mxsaar0;
+	u32 mxsaar1;
+	u32 dummy0[8];	/* 0x08 .. 0x24 */
+	u32 mxs3cracr;
+	u32 dummy1[3];	/* 0x2C .. 0x34 */
+	u32 mxs3cwacr;
+	u32 dummy2;	/* 0x3C */
+	u32 mxrtcr;
+	u32 mxwtcr;
+};
+
+struct r8a7791_mxi_qos {
+	u32 vspdu0;
+	u32 vspdu1;
+	u32 du0;
+	u32 du1;
+};
+
+/* AXI(QoS) */
+struct r8a7791_axi_qos {
+	u32 qosconf;
+	u32 qosctset0;
+	u32 qosctset1;
+	u32 qosctset2;
+	u32 qosctset3;
+	u32 qosreqctr;
+	u32 qosthres0;
+	u32 qosthres1;
+	u32 qosthres2;
+	u32 qosqon;
+};
+
+#endif
+
+#endif /* __ASM_ARCH_R8A7791_H */
diff --git a/arch/arm/include/asm/arch-rmobile/rmobile.h b/arch/arm/include/asm/arch-rmobile/rmobile.h
index ac17561..2382565 100644
--- a/arch/arm/include/asm/arch-rmobile/rmobile.h
+++ b/arch/arm/include/asm/arch-rmobile/rmobile.h
@@ -6,6 +6,10 @@
 #include <asm/arch/sh73a0.h>
 #elif defined(CONFIG_R8A7740)
 #include <asm/arch/r8a7740.h>
+#elif defined(CONFIG_R8A7790)
+#include <asm/arch/r8a7790.h>
+#elif defined(CONFIG_R8A7791)
+#include <asm/arch/r8a7791.h>
 #else
 #error "SOC Name not defined"
 #endif
diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
index 55ff10b..dd473c8 100644
--- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h
+++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h
@@ -55,7 +55,7 @@
 
 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
 
-static inline unsigned int s5p_mmc_init(int index, int bus_width)
+static inline int s5p_mmc_init(int index, int bus_width)
 {
 	unsigned int base = samsung_get_base_mmc() +
 				 (S5P_MMC_DEV_OFFSET * index);
diff --git a/arch/arm/include/asm/arch-socfpga/freeze_controller.h b/arch/arm/include/asm/arch-socfpga/freeze_controller.h
new file mode 100644
index 0000000..120f20e
--- /dev/null
+++ b/arch/arm/include/asm/arch-socfpga/freeze_controller.h
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2013 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_FREEZE_CONTROLLER_H_
+#define	_FREEZE_CONTROLLER_H_
+
+struct socfpga_freeze_controller {
+	u32	vioctrl;
+	u32	padding[3];
+	u32	hioctrl;
+	u32	src;
+	u32	hwctrl;
+};
+
+#define FREEZE_CHANNEL_NUM		(4)
+
+typedef enum {
+	FREEZE_CTRL_FROZEN = 0,
+	FREEZE_CTRL_THAWED = 1
+} FREEZE_CTRL_CHAN_STATE;
+
+#define SYSMGR_FRZCTRL_ADDRESS 0x40
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
+#define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
+#define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
+#define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
+#define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
+#define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
+#define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
+#define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
+#define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
+#define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
+#define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
+#define SYSMGR_FRZCTRL_VIOCTRL_SHIFT 0x2
+
+void sys_mgr_frzctrl_freeze_req(void);
+void sys_mgr_frzctrl_thaw_req(void);
+
+#endif /* _FREEZE_CONTROLLER_H_ */
diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 1b94a99..d9d521a 100644
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -581,7 +581,6 @@
 	(0xFF << EMIF_SYS_ADDR_SHIFT))
 
 #define EMIF_EXT_PHY_CTRL_TIMING_REG	0x5
-#define EMIF_EXT_PHY_CTRL_CONST_REG	0x14
 
 /* Reg mapping structure */
 struct emif_reg_struct {
@@ -641,7 +640,9 @@
 	u32 emif_ddr_phy_ctrl_2;
 	u32 padding7[12];
 	u32 emif_rd_wr_exec_thresh;
-	u32 padding8[55];
+	u32 padding8[7];
+	u32 emif_ddr_phy_status[21];
+	u32 padding9[27];
 	u32 emif_ddr_ext_phy_ctrl_1;
 	u32 emif_ddr_ext_phy_ctrl_1_shdw;
 	u32 emif_ddr_ext_phy_ctrl_2;
@@ -690,6 +691,9 @@
 	u32 emif_ddr_ext_phy_ctrl_23_shdw;
 	u32 emif_ddr_ext_phy_ctrl_24;
 	u32 emif_ddr_ext_phy_ctrl_24_shdw;
+	u32 padding[22];
+	u32 emif_ddr_fifo_misaligned_clear_1;
+	u32 emif_ddr_fifo_misaligned_clear_2;
 };
 
 struct dmm_lisa_map_regs {
@@ -1139,6 +1143,11 @@
 	s8 mr16;
 };
 
+struct read_write_regs {
+	u32 read_reg;
+	u32 write_reg;
+};
+
 /* assert macros */
 #if defined(DEBUG)
 #define emif_assert(c)	({ if (!(c)) for (;;); })
@@ -1167,4 +1176,5 @@
 
 void config_data_eye_leveling_samples(u32 emif_base);
 u32 emif_sdram_type(void);
+const struct read_write_regs *get_bug_regs(u32 *iterations);
 #endif
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 8a395e8..a78f990 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -226,6 +226,7 @@
 	u32 cm_l3init_hsusbotg_clkctrl;
 	u32 cm_l3init_hsusbtll_clkctrl;
 	u32 cm_l3init_p1500_clkctrl;
+	u32 cm_l3init_sata_clkctrl;
 	u32 cm_l3init_fsusb_clkctrl;
 	u32 cm_l3init_ocp2scp1_clkctrl;
 	u32 cm_l3init_ocp2scp3_clkctrl;
@@ -366,6 +367,7 @@
 	u32 control_ldosram_mpu_voltage_ctrl;
 	u32 control_ldosram_core_voltage_ctrl;
 	u32 control_usbotghs_ctrl;
+	u32 control_phy_power_sata;
 	u32 control_padconf_core_base;
 	u32 control_paconf_global;
 	u32 control_paconf_mode;
@@ -605,6 +607,14 @@
 	extern u32 *const omap_si_rev;
 	return ((*omap_si_rev & 0xFF000000) == OMAP54xx);
 }
+
+#define DRA7XX		0x07000000
+
+static inline u8 is_dra7xx(void)
+{
+	extern u32 *const omap_si_rev;
+	return ((*omap_si_rev & 0xFF000000) == DRA7XX);
+}
 #endif
 
 /*
diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c
index e2ae6fd..63f7ad9 100644
--- a/board/BuS/vl_ma2sc/vl_ma2sc.c
+++ b/board/BuS/vl_ma2sc/vl_ma2sc.c
@@ -10,13 +10,13 @@
 #include <common.h>
 #include <asm/sizes.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pio.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91sam9263.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/at91_common.h>
@@ -66,35 +66,22 @@
 
 	/* Configure RDY/BSY */
 #ifdef CONFIG_SYS_NAND_READY_PIN
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 #endif
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void vl_ma2sc_macb_hw_init(void)
 {
-	unsigned long	erstl;
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
-	at91_rstc_t	*rstc	= (at91_rstc_t *) ATMEL_BASE_RSTC;
+
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+	at91_phy_reset();
 
 	at91_macb_hw_init();
 }
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
index b0f09f5..4716e4f 100644
--- a/board/actux1/u-boot.lds
+++ b/board/actux1/u-boot.lds
@@ -87,10 +87,13 @@
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
index d84934e..f00d7c7 100644
--- a/board/actux2/u-boot.lds
+++ b/board/actux2/u-boot.lds
@@ -87,10 +87,13 @@
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
index 30c204b..2de3ca6 100644
--- a/board/actux3/u-boot.lds
+++ b/board/actux3/u-boot.lds
@@ -87,10 +87,13 @@
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c
index e1b1c10..ea9575d 100644
--- a/board/afeb9260/afeb9260.c
+++ b/board/afeb9260/afeb9260.c
@@ -13,7 +13,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
@@ -67,8 +66,6 @@
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 
 	/* Enable EMAC clock */
@@ -94,20 +91,7 @@
 	       pin_to_mask(AT91_PIN_PA28),
 	       &pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
-
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 263de49..7f14af1 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <atmel_mci.h>
 
@@ -73,8 +72,6 @@
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable EMAC clock */
 	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@@ -98,21 +95,7 @@
 		pin_to_mask(AT91_PIN_PA28),
 		&pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index 2e9246f..d42a173 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
@@ -82,10 +81,9 @@
 #ifdef CONFIG_MACB
 static void at91sam9263ek_macb_hw_init(void)
 {
-	unsigned long 	erstl;
 	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 	at91_pio_t	*pio	= (at91_pio_t *) ATMEL_BASE_PIO;
-	at91_rstc_t	*rstc	= (at91_rstc_t *) ATMEL_BASE_RSTC;
+
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
 
@@ -97,23 +95,10 @@
 	 *
 	 * PHY has internal pull-down
 	 */
-
 	writel(1 << 25, &pio->pioc.pudr);
 	writel((1 << 25) | (1 <<26), &pio->pioe.pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(1 << 25, &pio->pioc.puer);
diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index 6a071f6..b7e2efd 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -12,7 +12,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <lcd.h>
@@ -88,8 +87,6 @@
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
@@ -107,21 +104,7 @@
 	       pin_to_mask(AT91_PIN_PA13),
 	       &pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA15) |
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index 83fd63f..eff94a4 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -20,6 +20,9 @@
 #include <micrel.h>
 #include <net.h>
 #include <netdev.h>
+#include <spl.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/at91_wdt.h>
 
 #ifdef CONFIG_USB_GADGET_ATMEL_USBA
 #include <asm/arch/atmel_usba_udc.h>
@@ -159,6 +162,12 @@
 
 int board_early_init_f(void)
 {
+	at91_periph_clk_enable(ATMEL_ID_PIOA);
+	at91_periph_clk_enable(ATMEL_ID_PIOB);
+	at91_periph_clk_enable(ATMEL_ID_PIOC);
+	at91_periph_clk_enable(ATMEL_ID_PIOD);
+	at91_periph_clk_enable(ATMEL_ID_PIOE);
+
 	at91_seriald_hw_init();
 
 	return 0;
@@ -291,3 +300,85 @@
 	}
 }
 #endif /* CONFIG_ATMEL_SPI */
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+	sama5d3xek_mci_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+		    ATMEL_MPDDRC_CR_ENRDM_ON |
+		    ATMEL_MPDDRC_CR_NB_8BANKS |
+		    ATMEL_MPDDRC_CR_NDQS_DISABLED |
+		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+	/*
+	 * As the DDR2-SDRAm device requires a refresh time is 7.8125us
+	 * when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
+	 */
+	ddr2->rtr = 0x411;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct atmel_mpddr ddr2;
+
+	ddr2_conf(&ddr2);
+
+	/* enable MPDDR clock */
+	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+	writel(0x4, &pmc->scer);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	u32 tmp;
+
+	tmp = AT91_PMC_PLLAR_29 |
+	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+	      AT91_PMC_PLLXR_MUL(43) |
+	      AT91_PMC_PLLXR_DIV(1);
+	at91_plla_init(tmp);
+
+	writel(0x3 << 8, &pmc->pllicpr);
+
+	tmp = AT91_PMC_MCKR_MDIV_4 |
+	      AT91_PMC_MCKR_CSS_PLLA;
+	at91_mck_init(tmp);
+}
+#endif
diff --git a/board/bluewater/snapper9260/snapper9260.c b/board/bluewater/snapper9260/snapper9260.c
index 8a6919d..bfde129 100644
--- a/board/bluewater/snapper9260/snapper9260.c
+++ b/board/bluewater/snapper9260/snapper9260.c
@@ -14,7 +14,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <net.h>
 #include <netdev.h>
@@ -31,8 +30,6 @@
 {
 	struct at91_pmc *pmc   = (struct at91_pmc  *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@@ -54,18 +51,7 @@
 	/* Enable ethernet power */
 	pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
 
-	/* Need to reset PHY -> 500ms reset */
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-	       AT91_RSTC_MR_URSTEN, &rstc->mr);
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr);
+	at91_phy_reset();
 
 	/* Bring the ethernet out of reset */
 	pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c
index ecf261c..2074a93 100644
--- a/board/calao/sbc35_a9g20/sbc35_a9g20.c
+++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c
@@ -15,7 +15,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -77,8 +76,6 @@
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable EMAC clock */
 	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
@@ -102,21 +99,7 @@
 	       pin_to_mask(AT91_PIN_PA28),
 	       &pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
-		AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
diff --git a/board/calao/usb_a9263/Makefile b/board/calao/usb_a9263/Makefile
new file mode 100644
index 0000000..8a22b3e
--- /dev/null
+++ b/board/calao/usb_a9263/Makefile
@@ -0,0 +1,14 @@
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# (C) Copyright 2013
+# Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+
+obj-y	+= usb_a9263.o
diff --git a/board/calao/usb_a9263/usb_a9263.c b/board/calao/usb_a9263/usb_a9263.c
new file mode 100644
index 0000000..266e950
--- /dev/null
+++ b/board/calao/usb_a9263/usb_a9263.c
@@ -0,0 +1,148 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
+ * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm-generic/gpio.h>
+#include <asm/io.h>
+#include <net.h>
+#include <netdev.h>
+#include <dataflash.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_HAS_DATAFLASH
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/*define the area offsets*/
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x00001FFF, FLAG_PROTECT_SET, 0, "Bootstrap"},
+	{0x00002000, 0x00003FFF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00004000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "U-Boot"},
+};
+#endif
+
+#ifdef CONFIG_CMD_NAND
+static void usb_a9263_nand_hw_init(void)
+{
+	unsigned long csa;
+	at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
+	at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
+	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+	writel(csa, &matrix->csa[0]);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+
+	writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+
+	writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+	       &smc->cs[3].cycle);
+
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
+
+	writel(1 << ATMEL_ID_PIOA | 1 << ATMEL_ID_PIOCDE, &pmc->pcer);
+
+	/* Configure RDY/BSY */
+	gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
+
+	/* Enable NandFlash */
+	gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void usb_a9263_macb_hw_init(void)
+{
+	at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *  RXDV (PC25) => PHY normal mode (not Test mode)
+	 *  ERX0 (PE25) => PHY ADDR0
+	 *  ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal weak pull-up/pull-down
+	 */
+	gpio_request(GPIO_PIN_PC(25), "PHY mode");
+	gpio_direction_input(GPIO_PIN_PC(25));
+
+	gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
+	gpio_direction_input(GPIO_PIN_PE(25));
+
+	gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
+	gpio_direction_input(GPIO_PIN_PE(26));
+
+	at91_phy_reset();
+
+	/* It will set proper pinmux for ports PC25, PE25-26 */
+	at91_macb_hw_init();
+}
+#endif
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	usb_a9263_nand_hw_init();
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	usb_a9263_macb_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001);
+#endif
+	return rc;
+}
diff --git a/board/compulab/cm_t335/Makefile b/board/compulab/cm_t335/Makefile
new file mode 100644
index 0000000..0e6e96e
--- /dev/null
+++ b/board/compulab/cm_t335/Makefile
@@ -0,0 +1,10 @@
+#
+# Copyright (C) 2013 Compulab Ltd - http://compulab.co.il/
+#
+# Author: Ilya Ledvich <ilya@compulab.co.il>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= $(BOARD).o
+obj-$(CONFIG_SPL_BUILD) += mux.o spl.o
diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c
new file mode 100644
index 0000000..01019e8
--- /dev/null
+++ b/board/compulab/cm_t335/cm_t335.c
@@ -0,0 +1,162 @@
+/*
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <miiphy.h>
+#include <cpsw.h>
+
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Basic board specific setup.  Pinmux has been handled already.
+ */
+int board_init(void)
+{
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	gpmc_init();
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+	status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+#endif
+	return 0;
+}
+
+#if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
+static void cpsw_control(int enabled)
+{
+	/* VTP can be added here */
+	return;
+}
+
+static struct cpsw_slave_data cpsw_slave = {
+	.slave_reg_ofs	= 0x208,
+	.sliver_reg_ofs	= 0xd80,
+	.phy_id		= 0,
+	.phy_if		= PHY_INTERFACE_MODE_RGMII,
+};
+
+static struct cpsw_platform_data cpsw_data = {
+	.mdio_base		= CPSW_MDIO_BASE,
+	.cpsw_base		= CPSW_BASE,
+	.mdio_div		= 0xff,
+	.channels		= 8,
+	.cpdma_reg_ofs		= 0x800,
+	.slaves			= 1,
+	.slave_data		= &cpsw_slave,
+	.ale_reg_ofs		= 0xd00,
+	.ale_entries		= 1024,
+	.host_port_reg_ofs	= 0x108,
+	.hw_stats_reg_ofs	= 0x900,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= (1 << 5),
+	.control		= cpsw_control,
+	.host_port_num		= 0,
+	.version		= CPSW_CTRL_VERSION_2,
+};
+
+/* PHY reset GPIO */
+#define GPIO_PHY_RST		GPIO_PIN(3, 7)
+
+static void board_phy_init(void)
+{
+	gpio_request(GPIO_PHY_RST, "phy_rst");
+	gpio_direction_output(GPIO_PHY_RST, 0);
+	mdelay(2);
+	gpio_set_value(GPIO_PHY_RST, 1);
+	mdelay(2);
+}
+
+static void get_efuse_mac_addr(uchar *enetaddr)
+{
+	uint32_t mac_hi, mac_lo;
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	mac_lo = readl(&cdev->macid0l);
+	mac_hi = readl(&cdev->macid0h);
+	enetaddr[0] = mac_hi & 0xFF;
+	enetaddr[1] = (mac_hi & 0xFF00) >> 8;
+	enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
+	enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
+	enetaddr[4] = mac_lo & 0xFF;
+	enetaddr[5] = (mac_lo & 0xFF00) >> 8;
+}
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int handle_mac_address(void)
+{
+	uchar enetaddr[6];
+	int rv;
+
+	rv = eth_getenv_enetaddr("ethaddr", enetaddr);
+	if (rv)
+		return 0;
+
+	rv = cl_eeprom_read_mac_addr(enetaddr);
+	if (rv)
+		get_efuse_mac_addr(enetaddr);
+
+	if (!is_valid_ether_addr(enetaddr))
+		return -1;
+
+	return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define AR8051_PHY_DEBUG_ADDR_REG	0x1d
+#define AR8051_PHY_DEBUG_DATA_REG	0x1e
+#define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
+#define AR8051_RGMII_TX_CLK_DLY		0x100
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, n = 0;
+	const char *devname;
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	rv = handle_mac_address();
+	if (rv)
+		printf("No MAC address found!\n");
+
+	writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
+
+	board_phy_init();
+
+	rv = cpsw_register(&cpsw_data);
+	if (rv < 0)
+		printf("Error %d registering CPSW switch\n", rv);
+	else
+		n += rv;
+
+	/*
+	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
+	 * operating points.  So we must set the TX clock delay feature
+	 * in the AR8051 PHY.  Since we only support a single ethernet
+	 * device, we only do this for the first instance.
+	 */
+	devname = miiphy_get_current_dev();
+
+	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
+		     AR8051_DEBUG_RGMII_CLK_DLY_REG);
+	miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
+		     AR8051_RGMII_TX_CLK_DLY);
+	return n;
+}
+#endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */
diff --git a/board/compulab/cm_t335/mux.c b/board/compulab/cm_t335/mux.c
new file mode 100644
index 0000000..7d2beb0
--- /dev/null
+++ b/board/compulab/cm_t335/mux.c
@@ -0,0 +1,117 @@
+/*
+ * Pinmux configuration for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
+	{OFFSET(uart1_ctsn), (MODE(0) | PULLUP_EN | RXACTIVE)},
+	{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN)},
+	{-1},
+};
+
+static struct module_pin_mux mmc0_pin_mux[] = {
+	{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)},
+	{-1},
+};
+
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux i2c1_pin_mux[] = {
+	/* I2C_DATA */
+	{OFFSET(uart0_ctsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	/* I2C_SCLK */
+	{OFFSET(uart0_rtsn), (MODE(3) | RXACTIVE | PULLUDDIS | SLEWCTRL)},
+	{-1},
+};
+
+static struct module_pin_mux rgmii1_pin_mux[] = {
+	{OFFSET(mii1_txen), MODE(2)},			/* RGMII1_TCTL */
+	{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE},	/* RGMII1_RCTL */
+	{OFFSET(mii1_txd3), MODE(2)},			/* RGMII1_TD3 */
+	{OFFSET(mii1_txd2), MODE(2)},			/* RGMII1_TD2 */
+	{OFFSET(mii1_txd1), MODE(2)},			/* RGMII1_TD1 */
+	{OFFSET(mii1_txd0), MODE(2)},			/* RGMII1_TD0 */
+	{OFFSET(mii1_txclk), MODE(2)},			/* RGMII1_TCLK */
+	{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE},	/* RGMII1_RCLK */
+	{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE},	/* RGMII1_RD3 */
+	{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE},	/* RGMII1_RD2 */
+	{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE},	/* RGMII1_RD1 */
+	{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE},	/* RGMII1_RD0 */
+	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
+	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
+	{-1},
+};
+
+static struct module_pin_mux nand_pin_mux[] = {
+	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
+	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
+	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
+	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
+	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
+	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
+	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
+	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
+	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
+	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
+	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},		/* NAND_CS0 */
+	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
+	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
+	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
+	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
+	{-1},
+};
+
+static struct module_pin_mux eth_phy_rst_pin_mux[] = {
+	{OFFSET(emu0), (MODE(7) | PULLUDDIS)},	/* GPIO3_7 */
+	{-1},
+};
+
+static struct module_pin_mux status_led_pin_mux[] = {
+	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN)},	/* GPIO2_0 */
+	{-1},
+};
+
+void set_uart_mux_conf(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void set_mux_conf_regs(void)
+{
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(i2c1_pin_mux);
+	configure_module_pin_mux(rgmii1_pin_mux);
+	configure_module_pin_mux(eth_phy_rst_pin_mux);
+	configure_module_pin_mux(mmc0_pin_mux);
+	configure_module_pin_mux(nand_pin_mux);
+	configure_module_pin_mux(status_led_pin_mux);
+}
diff --git a/board/compulab/cm_t335/spl.c b/board/compulab/cm_t335/spl.c
new file mode 100644
index 0000000..99f3a86
--- /dev/null
+++ b/board/compulab/cm_t335/spl.c
@@ -0,0 +1,106 @@
+/*
+ * SPL specific code for Compulab CM-T335 board
+ *
+ * Board functions for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+
+#include <asm/arch/ddr_defs.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clocks_am33xx.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware_am33xx.h>
+#include <asm/sizes.h>
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0		= MT41J128MJT125_RD_DQS,
+	.datawdsratio0		= MT41J128MJT125_WR_DQS,
+	.datafwsratio0		= MT41J128MJT125_PHY_FIFO_WE,
+	.datawrsratio0		= MT41J128MJT125_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio		= MT41J128MJT125_RATIO,
+	.cmd0iclkout		= MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd1csratio		= MT41J128MJT125_RATIO,
+	.cmd1iclkout		= MT41J128MJT125_INVERT_CLKOUT,
+
+	.cmd2csratio		= MT41J128MJT125_RATIO,
+	.cmd2iclkout		= MT41J128MJT125_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config		= MT41J128MJT125_EMIF_SDCFG,
+	.ref_ctrl		= MT41J128MJT125_EMIF_SDREF,
+	.sdram_tim1		= MT41J128MJT125_EMIF_TIM1,
+	.sdram_tim2		= MT41J128MJT125_EMIF_TIM2,
+	.sdram_tim3		= MT41J128MJT125_EMIF_TIM3,
+	.zq_config		= MT41J128MJT125_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1	= MT41J128MJT125_EMIF_READ_LATENCY |
+					PHY_EN_DYN_PWRDN,
+};
+
+const struct dpll_params dpll_ddr = {
+/*       M           N            M2  M3  M4  M5  M6 */
+	303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
+
+void am33xx_spl_board_init(void)
+{
+	struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
+
+	/* Get the frequency */
+	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
+
+	/* Set CORE Frequencies to OPP100 */
+	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
+
+	/* Set MPU Frequency to what we detected now that voltages are set */
+	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	return &dpll_ddr;
+}
+
+static void probe_sdram_size(long size)
+{
+	switch (size) {
+	case SZ_512M:
+		ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
+		break;
+	case SZ_256M:
+		ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
+		break;
+	case SZ_128M:
+		ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
+		break;
+	default:
+		puts("Failed configuring DRAM, resetting...\n\n");
+		reset_cpu(0);
+	}
+	debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
+	config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+
+void sdram_init(void)
+{
+	long size = SZ_1G;
+
+	do {
+		size = size / 2;
+		probe_sdram_size(size);
+	} while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
+
+	return;
+}
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
new file mode 100644
index 0000000..1b609a2
--- /dev/null
+++ b/board/compulab/cm_t335/u-boot.lds
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		CPUDIR/start.o (.text*)
+		board/compulab/cm_t335/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	/DISCARD/ : { *(.dynsym) }
+	/DISCARD/ : { *(.dynstr*) }
+	/DISCARD/ : { *(.dynamic*) }
+	/DISCARD/ : { *(.plt*) }
+	/DISCARD/ : { *(.interp*) }
+	/DISCARD/ : { *(.gnu*) }
+}
diff --git a/board/compulab/cm_t35/Makefile b/board/compulab/cm_t35/Makefile
index 6e2e1cb..ede250b 100644
--- a/board/compulab/cm_t35/Makefile
+++ b/board/compulab/cm_t35/Makefile
@@ -7,4 +7,4 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y	+= cm_t35.o leds.o
+obj-y	+= cm_t35.o
diff --git a/board/compulab/cm_t35/leds.c b/board/compulab/cm_t35/leds.c
deleted file mode 100644
index 7e2803e..0000000
--- a/board/compulab/cm_t35/leds.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
- *
- * Author: Igor Grinberg <grinberg@compulab.co.il>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <status_led.h>
-#include <asm/gpio.h>
-
-static unsigned int leds[] = { GREEN_LED_GPIO };
-
-void __led_init(led_id_t mask, int state)
-{
-	if (gpio_request(leds[mask], "") != 0) {
-		printf("%s: failed requesting GPIO%u\n", __func__, leds[mask]);
-		return;
-	}
-
-	gpio_direction_output(leds[mask], 0);
-}
-
-void __led_set(led_id_t mask, int state)
-{
-	gpio_set_value(leds[mask], state == STATUS_LED_ON);
-}
-
-void __led_toggle(led_id_t mask)
-{
-	gpio_set_value(leds[mask], !gpio_get_value(leds[mask]));
-}
diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
index 0035a0b..ebcaf44 100644
--- a/board/dvlhost/u-boot.lds
+++ b/board/dvlhost/u-boot.lds
@@ -87,10 +87,13 @@
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c
index 1f5eea5..b45213c 100644
--- a/board/egnite/ethernut5/ethernut5.c
+++ b/board/egnite/ethernut5/ethernut5.c
@@ -71,6 +71,7 @@
 #include <asm/arch/at91_spi.h>
 #include <asm/arch/gpio.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 
 #include "ethernut5_pwrman.h"
 
@@ -141,7 +142,7 @@
 	/* Ready pin is optional. */
 	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
 #endif
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c
index 9bf6739..c5994e0 100644
--- a/board/esd/meesc/meesc.c
+++ b/board/esd/meesc/meesc.c
@@ -12,6 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -74,10 +75,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif /* CONFIG_CMD_NAND */
 
diff --git a/board/esd/otc570/otc570.c b/board/esd/otc570/otc570.c
index acc1b31..4751d0a 100644
--- a/board/esd/otc570/otc570.c
+++ b/board/esd/otc570/otc570.c
@@ -12,6 +12,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -82,10 +83,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif /* CONFIG_CMD_NAND */
 
diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c
index 5e1524e..01ecccb 100644
--- a/board/eukrea/cpu9260/cpu9260.c
+++ b/board/eukrea/cpu9260/cpu9260.c
@@ -12,12 +12,12 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9260.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_matrix.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/at91_pio.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/hardware.h>
@@ -79,39 +79,24 @@
 	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
 #ifdef CONFIG_MACB
 static void cpu9260_macb_hw_init(void)
 {
-	unsigned long rstcmr;
 	at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
-	at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
 
 	/* Enable clock */
 	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
 
 	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
 
-	rstcmr = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0xD) |
-				AT91_RSTC_MR_URSTEN, &rstc->mr);
-
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end hardware reset */
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
-		;
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | rstcmr | AT91_RSTC_MR_URSTEN, &rstc->mr);
+	at91_phy_reset();
 
 	at91_macb_hw_init();
 }
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 8d5cc91..1cca176 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -90,13 +90,13 @@
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.bss*) }
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/isee/igep0033/board.c b/board/isee/igep0033/board.c
index 0b8356d..6a8ca2b 100644
--- a/board/isee/igep0033/board.c
+++ b/board/isee/igep0033/board.c
@@ -35,20 +35,16 @@
 	.datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
 	.datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
 	.datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = K4B2G1646EBIH9_RATIO,
-	.cmd0dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
 	.cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 
 	.cmd1csratio = K4B2G1646EBIH9_RATIO,
-	.cmd1dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
 	.cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 
 	.cmd2csratio = K4B2G1646EBIH9_RATIO,
-	.cmd2dldiff = K4B2G1646EBIH9_DLL_LOCK_DIFF,
 	.cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
 };
 
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 034886a..68463e7 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -49,25 +49,22 @@
 	return &dpll_ddr;
 }
 
+#ifdef CONFIG_REV1
 static const struct ddr_data ddr3_data = {
 	.datardsratio0 = MT41J256M8HX15E_RD_DQS,
 	.datawdsratio0 = MT41J256M8HX15E_WR_DQS,
 	.datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J256M8HX15E_RATIO,
-	.cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41J256M8HX15E_RATIO,
-	.cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41J256M8HX15E_RATIO,
-	.cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
 };
 
@@ -82,6 +79,48 @@
 				PHY_EN_DYN_PWRDN,
 };
 
+void sdram_init(void)
+{
+	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#else
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY |
+				PHY_EN_DYN_PWRDN,
+};
+
+void sdram_init(void)
+{
+	config_ddr(DDR_CLK_MHZ, MT41K256M16HA125E_IOCTRL_VALUE, &ddr3_data,
+		   &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+}
+#endif
+
 void set_uart_mux_conf(void)
 {
 	enable_uart0_pin_mux();
@@ -95,12 +134,6 @@
 
 	enable_board_pin_mux();
 }
-
-void sdram_init(void)
-{
-	config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
-			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
-}
 #endif
 
 /*
diff --git a/board/renesas/koelsch/Makefile b/board/renesas/koelsch/Makefile
new file mode 100644
index 0000000..b4d0183
--- /dev/null
+++ b/board/renesas/koelsch/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/koelsch/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= koelsch.o qos.o
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
new file mode 100644
index 0000000..7153f65
--- /dev/null
+++ b/board/renesas/koelsch/koelsch.c
@@ -0,0 +1,283 @@
+/*
+ * board/renesas/koelsch/koelsch.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include <i2c.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define s_init_wait(cnt) \
+	({	\
+		u32 i = 0x10000 * cnt;	\
+		while (i > 0)	\
+			i--;	\
+	})
+
+
+#define dbpdrgd_check(bsc) \
+	({	\
+		while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1)	\
+			;	\
+	})
+
+#if defined(CONFIG_NORFLASH)
+static void bsc_init(void)
+{
+	struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
+	struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
+
+	/* LBSC */
+	writel(0x00000020, &lbsc->cs0ctrl);
+	writel(0x00000020, &lbsc->cs1ctrl);
+	writel(0x00002020, &lbsc->ecs0ctrl);
+	writel(0x00002020, &lbsc->ecs1ctrl);
+
+	writel(0x077F077F, &lbsc->cswcr0);
+	writel(0x077F077F, &lbsc->cswcr1);
+	writel(0x077F077F, &lbsc->ecswcr0);
+	writel(0x077F077F, &lbsc->ecswcr1);
+
+	/* DBSC3 */
+	s_init_wait(10);
+
+	writel(0x0000A55A, &dbsc3_0->dbpdlck);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x80000000, &dbsc3_0->dbpdrgd);
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000006, &dbsc3_0->dbpdrga);
+	writel(0x0001C000, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FD2480, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000010, &dbsc3_0->dbpdrga);
+	writel(0xF004649B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000F, &dbsc3_0->dbpdrga);
+	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000E, &dbsc3_0->dbpdrga);
+	writel(0x33C03812, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000003, &dbsc3_0->dbpdrga);
+	writel(0x0300C481, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000007, &dbsc3_0->dbkind);
+	writel(0x10030A02, &dbsc3_0->dbconf0);
+	writel(0x00000001, &dbsc3_0->dbphytype);
+	writel(0x00000000, &dbsc3_0->dbbl);
+	writel(0x0000000B, &dbsc3_0->dbtr0);
+	writel(0x00000008, &dbsc3_0->dbtr1);
+	writel(0x00000000, &dbsc3_0->dbtr2);
+	writel(0x0000000B, &dbsc3_0->dbtr3);
+	writel(0x000C000B, &dbsc3_0->dbtr4);
+	writel(0x00000027, &dbsc3_0->dbtr5);
+	writel(0x0000001C, &dbsc3_0->dbtr6);
+	writel(0x00000005, &dbsc3_0->dbtr7);
+	writel(0x00000018, &dbsc3_0->dbtr8);
+	writel(0x00000008, &dbsc3_0->dbtr9);
+	writel(0x0000000C, &dbsc3_0->dbtr10);
+	writel(0x00000009, &dbsc3_0->dbtr11);
+	writel(0x00000012, &dbsc3_0->dbtr12);
+	writel(0x000000D0, &dbsc3_0->dbtr13);
+	writel(0x00140005, &dbsc3_0->dbtr14);
+	writel(0x00050004, &dbsc3_0->dbtr15);
+	writel(0x70233005, &dbsc3_0->dbtr16);
+	writel(0x000C0000, &dbsc3_0->dbtr17);
+	writel(0x00000300, &dbsc3_0->dbtr18);
+	writel(0x00000040, &dbsc3_0->dbtr19);
+	writel(0x00000001, &dbsc3_0->dbrnk0);
+	writel(0x00020001, &dbsc3_0->dbadj0);
+	writel(0x20082008, &dbsc3_0->dbadj2);
+	writel(0x00020002, &dbsc3_0->dbwt0cnf0);
+	writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
+
+	writel(0x00000015, &dbsc3_0->dbpdrga);
+	writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000016, &dbsc3_0->dbpdrga);
+	writel(0x00000006, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000017, &dbsc3_0->dbpdrga);
+	writel(0x00000018, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000012, &dbsc3_0->dbpdrga);
+	writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000013, &dbsc3_0->dbpdrga);
+	writel(0x1A868300, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000014, &dbsc3_0->dbpdrga);
+	writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000001A, &dbsc3_0->dbpdrga);
+	writel(0x930035C7, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000060, &dbsc3_0->dbpdrga);
+	writel(0x330657B2, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000011, &dbsc3_0->dbpdrga);
+	writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000071, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x2100FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+
+	writel(0x110000DB, &dbsc3_0->dbcmd);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+	writel(0x01004C20, &dbsc3_0->dbcalcnf);
+	writel(0x014000AA, &dbsc3_0->dbcaltr);
+	writel(0x00000140, &dbsc3_0->dbrfcnf0);
+	writel(0x00081860, &dbsc3_0->dbrfcnf1);
+	writel(0x00010000, &dbsc3_0->dbrfcnf2);
+	writel(0x00000001, &dbsc3_0->dbrfen);
+	writel(0x00000001, &dbsc3_0->dbacen);
+}
+#else
+#define bsc_init() do {} while (0)
+#endif /* CONFIG_NORFLASH */
+
+void s_init(void)
+{
+	struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
+	struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS */
+	qos_init();
+
+	/* BSC */
+	bsc_init();
+}
+
+#define MSTPSR1		0xE6150038
+#define SMSTPCR1	0xE6150134
+#define TMU0_MSTP125	(1 << 25)
+
+#define MSTPSR7		0xE61501C4
+#define SMSTPCR7	0xE615014C
+#define SCIF0_MSTP721	(1 << 21)
+
+#define PMMR	0xE6060000
+#define GPSR4	0xE6060014
+#define IPSR14	0xE6060058
+
+#define set_guard_reg(addr, mask, value)	\
+{ \
+	u32 val; \
+	val = (readl(addr) & ~(mask)) | (value); \
+	writel(~val, PMMR); \
+	writel(val, addr); \
+}
+
+#define mstp_setbits(type, addr, saddr, set) \
+	out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+	out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set) \
+	mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear)   \
+	mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+#if defined(CONFIG_NORFLASH)
+	/* SCIF0 */
+	set_guard_reg(GPSR4, 0x34000000, 0x00000000);
+	set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
+	set_guard_reg(GPSR4, 0x00000000, 0x34000000);
+#endif
+
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7791_pinmux_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c
new file mode 100644
index 0000000..7f88f7d
--- /dev/null
+++ b/board/renesas/koelsch/qos.c
@@ -0,0 +1,1220 @@
+/*
+ * board/renesas/koelsch/qos.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ *
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.23 */
+
+enum {
+	DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
+	DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
+	DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
+	DBSC3_15,
+	DBSC3_NR,
+};
+
+static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
+};
+
+static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
+};
+
+static u32 dbsc3_1_r_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_R0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_R1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_R2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_R3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_R4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_R5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_R6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_R7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_R8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_R9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_R10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_R11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_R12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_R13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_R14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_R15_BASE,
+};
+
+static u32 dbsc3_1_w_qos_addr[DBSC3_NR] = {
+	[DBSC3_00] = DBSC3_1_QOS_W0_BASE,
+	[DBSC3_01] = DBSC3_1_QOS_W1_BASE,
+	[DBSC3_02] = DBSC3_1_QOS_W2_BASE,
+	[DBSC3_03] = DBSC3_1_QOS_W3_BASE,
+	[DBSC3_04] = DBSC3_1_QOS_W4_BASE,
+	[DBSC3_05] = DBSC3_1_QOS_W5_BASE,
+	[DBSC3_06] = DBSC3_1_QOS_W6_BASE,
+	[DBSC3_07] = DBSC3_1_QOS_W7_BASE,
+	[DBSC3_08] = DBSC3_1_QOS_W8_BASE,
+	[DBSC3_09] = DBSC3_1_QOS_W9_BASE,
+	[DBSC3_10] = DBSC3_1_QOS_W10_BASE,
+	[DBSC3_11] = DBSC3_1_QOS_W11_BASE,
+	[DBSC3_12] = DBSC3_1_QOS_W12_BASE,
+	[DBSC3_13] = DBSC3_1_QOS_W13_BASE,
+	[DBSC3_14] = DBSC3_1_QOS_W14_BASE,
+	[DBSC3_15] = DBSC3_1_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct r8a7791_s3c *s3c;
+	struct r8a7791_s3c_qos *s3c_qos;
+	struct r8a7791_dbsc3_qos *qos_addr;
+	struct r8a7791_mxi *mxi;
+	struct r8a7791_mxi_qos *mxi_qos;
+	struct r8a7791_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct r8a7791_s3c *)S3C_BASE;
+	writel(0x00FF1B1D, &s3c->s3cadsplcr);
+	writel(0x1F0D0C0C, &s3c->s3crorr);
+	writel(0x1F0D0C0A, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00890089, &s3c_qos->s3cqos0);
+	writel(0x20960010, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA2200, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960010, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA2200, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20DC, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20DC, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7791_s3c_qos *)S3C_QOS_AXI_BASE;
+	writel(0x00820082, &s3c_qos->s3cqos0);
+	writel(0x20960020, &s3c_qos->s3cqos1);
+	writel(0x20302030, &s3c_qos->s3cqos2);
+	writel(0x20AA20FA, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20960020, &s3c_qos->s3cqos5);
+	writel(0x20302030, &s3c_qos->s3cqos6);
+	writel(0x20AA20FA, &s3c_qos->s3cqos7);
+	writel(0x00002032, &s3c_qos->s3cqos8);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FE7, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC0 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x000020EB, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Read */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_r_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x00002096, &qos_addr->dbtmval0);
+		writel(0x00002064, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00001FB0, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000204B, &qos_addr->dbthres1);
+		writel(0x00001FE7, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* DBSC1 - Write */
+	for (i = DBSC3_00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7791_dbsc3_qos *)dbsc3_1_w_qos_addr[i];
+		writel(0x00000002, &qos_addr->dblgcnt);
+		writel(0x000020EB, &qos_addr->dbtmval0);
+		writel(0x0000206E, &qos_addr->dbtmval1);
+		writel(0x00002050, &qos_addr->dbtmval2);
+		writel(0x0000203A, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002078, &qos_addr->dbthres0);
+		writel(0x0000205A, &qos_addr->dbthres1);
+		writel(0x0000203C, &qos_addr->dbthres2);
+		writel(0x00000001, &qos_addr->dblgqon);
+	}
+
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct r8a7791_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00780080, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct r8a7791_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000D, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002021, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_AX2M_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CC50_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CCI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_CS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_DDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_ETH_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_MPXM_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SAT1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_SDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000214C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_TRAB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020A6, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI_UDM1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_DBG_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDM_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002299, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002029, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)RT_AXI_SY2RT_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002037, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002053, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000206E, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x00002245, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXR_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_MXW_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x000020DC, &axi_qos->qosctset0);
+	writel(0x00002096, &axi_qos->qosctset1);
+	writel(0x00002030, &axi_qos->qosctset2);
+	writel(0x00002030, &axi_qos->qosctset3);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x000020AA, &axi_qos->qosthres0);
+	writel(0x00002032, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002190, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x000020C8, &axi_qos->qosctset0);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002063, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7791_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002073, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002064, &axi_qos->qosthres0);
+	writel(0x00002004, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+}
diff --git a/board/renesas/koelsch/qos.h b/board/renesas/koelsch/qos.h
new file mode 100644
index 0000000..9a6c046
--- /dev/null
+++ b/board/renesas/koelsch/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile
new file mode 100644
index 0000000..034c6f8
--- /dev/null
+++ b/board/renesas/lager/Makefile
@@ -0,0 +1,9 @@
+#
+# board/renesas/lager/Makefile
+#
+# Copyright (C) 2013 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-y	:= lager.o qos.o
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
new file mode 100644
index 0000000..5c99fc9
--- /dev/null
+++ b/board/renesas/lager/lager.c
@@ -0,0 +1,287 @@
+/*
+ * board/renesas/lager/lager.c
+ *     This file is lager board support.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <netdev.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <asm/arch/rmobile.h>
+#include "qos.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define s_init_wait(cnt) \
+	({	\
+		u32 i = 0x10000 * cnt;	\
+		while (i > 0)	\
+			i--;	\
+	})
+
+#define dbpdrgd_check(bsc) \
+	({	\
+		while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1)	\
+			;	\
+	})
+
+#if defined(CONFIG_NORFLASH)
+static void bsc_init(void)
+{
+	struct r8a7790_lbsc *lbsc = (struct r8a7790_lbsc *)LBSC_BASE;
+	struct r8a7790_dbsc3 *dbsc3_0 = (struct r8a7790_dbsc3 *)DBSC3_0_BASE;
+
+	/* LBSC */
+	writel(0x00000020, &lbsc->cs0ctrl);
+	writel(0x00000020, &lbsc->cs1ctrl);
+	writel(0x00002020, &lbsc->ecs0ctrl);
+	writel(0x00002020, &lbsc->ecs1ctrl);
+
+	writel(0x077F077F, &lbsc->cswcr0);
+	writel(0x077F077F, &lbsc->cswcr1);
+	writel(0x077F077F, &lbsc->ecswcr0);
+	writel(0x077F077F, &lbsc->ecswcr1);
+
+	/* DBSC3 */
+	s_init_wait(10);
+
+	writel(0x0000A55A, &dbsc3_0->dbpdlck);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x80000000, &dbsc3_0->dbpdrgd);
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000006, &dbsc3_0->dbpdrga);
+	writel(0x0001C000, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FD2480, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000010, &dbsc3_0->dbpdrga);
+	writel(0xF004649B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000F, &dbsc3_0->dbpdrga);
+	writel(0x00181EE4, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000000E, &dbsc3_0->dbpdrga);
+	writel(0x33C03812, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000003, &dbsc3_0->dbpdrga);
+	writel(0x0300C481, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000007, &dbsc3_0->dbkind);
+	writel(0x10030A02, &dbsc3_0->dbconf0);
+	writel(0x00000001, &dbsc3_0->dbphytype);
+	writel(0x00000000, &dbsc3_0->dbbl);
+	writel(0x0000000B, &dbsc3_0->dbtr0);
+	writel(0x00000008, &dbsc3_0->dbtr1);
+	writel(0x00000000, &dbsc3_0->dbtr2);
+	writel(0x0000000B, &dbsc3_0->dbtr3);
+	writel(0x000C000B, &dbsc3_0->dbtr4);
+	writel(0x00000027, &dbsc3_0->dbtr5);
+	writel(0x0000001C, &dbsc3_0->dbtr6);
+	writel(0x00000005, &dbsc3_0->dbtr7);
+	writel(0x00000018, &dbsc3_0->dbtr8);
+	writel(0x00000008, &dbsc3_0->dbtr9);
+	writel(0x0000000C, &dbsc3_0->dbtr10);
+	writel(0x00000009, &dbsc3_0->dbtr11);
+	writel(0x00000012, &dbsc3_0->dbtr12);
+	writel(0x000000D0, &dbsc3_0->dbtr13);
+	writel(0x00140005, &dbsc3_0->dbtr14);
+	writel(0x00050004, &dbsc3_0->dbtr15);
+	writel(0x70233005, &dbsc3_0->dbtr16);
+	writel(0x000C0000, &dbsc3_0->dbtr17);
+	writel(0x00000300, &dbsc3_0->dbtr18);
+	writel(0x00000040, &dbsc3_0->dbtr19);
+	writel(0x00000001, &dbsc3_0->dbrnk0);
+	writel(0x00020001, &dbsc3_0->dbadj0);
+	writel(0x20082008, &dbsc3_0->dbadj2);
+	writel(0x00020002, &dbsc3_0->dbwt0cnf0);
+	writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
+
+	writel(0x00000015, &dbsc3_0->dbpdrga);
+	writel(0x00000D70, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000016, &dbsc3_0->dbpdrga);
+	writel(0x00000006, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000017, &dbsc3_0->dbpdrga);
+	writel(0x00000018, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000012, &dbsc3_0->dbpdrga);
+	writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000013, &dbsc3_0->dbpdrga);
+	writel(0x1A868300, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000023, &dbsc3_0->dbpdrga);
+	writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000014, &dbsc3_0->dbpdrga);
+	writel(0x300214D8, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000001A, &dbsc3_0->dbpdrga);
+	writel(0x930035C7, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000060, &dbsc3_0->dbpdrga);
+	writel(0x330657B2, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000011, &dbsc3_0->dbpdrga);
+	writel(0x1000040B, &dbsc3_0->dbpdrgd);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000071, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x2100FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+	writel(0x0000FA00, &dbsc3_0->dbcmd);
+
+	writel(0x110000DB, &dbsc3_0->dbcmd);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x00000181, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000001, &dbsc3_0->dbpdrga);
+	writel(0x0000FE01, &dbsc3_0->dbpdrgd);
+
+	writel(0x00000004, &dbsc3_0->dbpdrga);
+	dbpdrgd_check(dbsc3_0);
+
+	writel(0x00000000, &dbsc3_0->dbbs0cnt1);
+	writel(0x01004C20, &dbsc3_0->dbcalcnf);
+	writel(0x014000AA, &dbsc3_0->dbcaltr);
+	writel(0x00000140, &dbsc3_0->dbrfcnf0);
+	writel(0x00081860, &dbsc3_0->dbrfcnf1);
+	writel(0x00010000, &dbsc3_0->dbrfcnf2);
+	writel(0x00000001, &dbsc3_0->dbrfen);
+	writel(0x00000001, &dbsc3_0->dbacen);
+}
+#else
+#define bsc_init() do {} while (0)
+#endif /* CONFIG_NORFLASH */
+
+void s_init(void)
+{
+	struct r8a7790_rwdt *rwdt = (struct r8a7790_rwdt *)RWDT_BASE;
+	struct r8a7790_swdt *swdt = (struct r8a7790_swdt *)SWDT_BASE;
+
+	/* Watchdog init */
+	writel(0xA5A5A500, &rwdt->rwtcsra);
+	writel(0xA5A5A500, &swdt->swtcsra);
+
+	/* QoS(Quality-of-Service) Init */
+	qos_init();
+
+	/* BSC init */
+	bsc_init();
+}
+
+#define MSTPSR1	0xE6150038
+#define SMSTPCR1	0xE6150134
+#define TMU0_MSTP125	(1 << 25)
+
+#define MSTPSR7	0xE61501C4
+#define SMSTPCR7	0xE615014C
+#define SCIF0_MSTP721	(1 << 21)
+
+#define PMMR	0xE6060000
+#define GPSR4	0xE6060014
+#define IPSR14	0xE6060058
+
+#define	set_guard_reg(addr, mask, value)	\
+{ \
+	u32	val; \
+	val = (readl(addr) & ~(mask)) | (value);	\
+	writel(~val, PMMR);	\
+	writel(val, addr);	\
+}
+
+#define mstp_setbits(type, addr, saddr, set) \
+	out_##type((saddr), in_##type(addr) | (set))
+#define mstp_clrbits(type, addr, saddr, clear) \
+	out_##type((saddr), in_##type(addr) & ~(clear))
+#define mstp_setbits_le32(addr, saddr, set)	\
+		mstp_setbits(le32, addr, saddr, set)
+#define mstp_clrbits_le32(addr, saddr, clear)	\
+		mstp_clrbits(le32, addr, saddr, clear)
+
+int board_early_init_f(void)
+{
+	/* TMU0 */
+	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
+
+#if defined(CONFIG_NORFLASH)
+	/* SCIF0 */
+	set_guard_reg(GPSR4, 0x34000000, 0x00000000);
+	set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
+	set_guard_reg(GPSR4,  0x00000000, 0x34000000);
+#endif
+
+	mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
+
+	return 0;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int board_init(void)
+{
+	/* board id for linux */
+	gd->bd->bi_arch_number = MACH_TYPE_LAGER;
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LAGER_SDRAM_BASE + 0x100;
+
+	/* Init PFC controller */
+	r8a7790_pinmux_init();
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+const struct rmobile_sysinfo sysinfo = {
+	CONFIG_RMOBILE_BOARD_STRING
+};
+
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = LAGER_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = LAGER_SDRAM_SIZE;
+}
+
+int board_late_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+}
diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c
new file mode 100644
index 0000000..b88511a
--- /dev/null
+++ b/board/renesas/lager/qos.c
@@ -0,0 +1,1119 @@
+/*
+ * board/renesas/lager/qos.c
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/processor.h>
+#include <asm/mach-types.h>
+#include <asm/io.h>
+#include <asm/arch/rmobile.h>
+
+/* QoS version 0.954 */
+
+enum {
+	DBSC3_R00, DBSC3_R01, DBSC3_R02, DBSC3_R03, DBSC3_R04,
+	DBSC3_R05, DBSC3_R06, DBSC3_R07, DBSC3_R08, DBSC3_R09,
+	DBSC3_R10, DBSC3_R11, DBSC3_R12, DBSC3_R13, DBSC3_R14,
+	DBSC3_R15,
+	DBSC3_W00, DBSC3_W01, DBSC3_W02, DBSC3_W03, DBSC3_W04,
+	DBSC3_W05, DBSC3_W06, DBSC3_W07, DBSC3_W08, DBSC3_W09,
+	DBSC3_W10, DBSC3_W11, DBSC3_W12, DBSC3_W13, DBSC3_W14,
+	DBSC3_W15,
+	DBSC3_NR,
+};
+
+static const u32 dbsc3_qos_addr[DBSC3_NR] = {
+	[DBSC3_R00] = DBSC3_0_QOS_R0_BASE,
+	[DBSC3_R01] = DBSC3_0_QOS_R1_BASE,
+	[DBSC3_R02] = DBSC3_0_QOS_R2_BASE,
+	[DBSC3_R03] = DBSC3_0_QOS_R3_BASE,
+	[DBSC3_R04] = DBSC3_0_QOS_R4_BASE,
+	[DBSC3_R05] = DBSC3_0_QOS_R5_BASE,
+	[DBSC3_R06] = DBSC3_0_QOS_R6_BASE,
+	[DBSC3_R07] = DBSC3_0_QOS_R7_BASE,
+	[DBSC3_R08] = DBSC3_0_QOS_R8_BASE,
+	[DBSC3_R09] = DBSC3_0_QOS_R9_BASE,
+	[DBSC3_R10] = DBSC3_0_QOS_R10_BASE,
+	[DBSC3_R11] = DBSC3_0_QOS_R11_BASE,
+	[DBSC3_R12] = DBSC3_0_QOS_R12_BASE,
+	[DBSC3_R13] = DBSC3_0_QOS_R13_BASE,
+	[DBSC3_R14] = DBSC3_0_QOS_R14_BASE,
+	[DBSC3_R15] = DBSC3_0_QOS_R15_BASE,
+	[DBSC3_W00] = DBSC3_0_QOS_W0_BASE,
+	[DBSC3_W01] = DBSC3_0_QOS_W1_BASE,
+	[DBSC3_W02] = DBSC3_0_QOS_W2_BASE,
+	[DBSC3_W03] = DBSC3_0_QOS_W3_BASE,
+	[DBSC3_W04] = DBSC3_0_QOS_W4_BASE,
+	[DBSC3_W05] = DBSC3_0_QOS_W5_BASE,
+	[DBSC3_W06] = DBSC3_0_QOS_W6_BASE,
+	[DBSC3_W07] = DBSC3_0_QOS_W7_BASE,
+	[DBSC3_W08] = DBSC3_0_QOS_W8_BASE,
+	[DBSC3_W09] = DBSC3_0_QOS_W9_BASE,
+	[DBSC3_W10] = DBSC3_0_QOS_W10_BASE,
+	[DBSC3_W11] = DBSC3_0_QOS_W11_BASE,
+	[DBSC3_W12] = DBSC3_0_QOS_W12_BASE,
+	[DBSC3_W13] = DBSC3_0_QOS_W13_BASE,
+	[DBSC3_W14] = DBSC3_0_QOS_W14_BASE,
+	[DBSC3_W15] = DBSC3_0_QOS_W15_BASE,
+};
+
+void qos_init(void)
+{
+	int i;
+	struct r8a7790_s3c *s3c;
+	struct r8a7790_s3c_qos *s3c_qos;
+	struct r8a7790_dbsc3_qos *qos_addr;
+	struct r8a7790_mxi *mxi;
+	struct r8a7790_mxi_qos *mxi_qos;
+	struct r8a7790_axi_qos *axi_qos;
+
+	/* DBSC DBADJ2 */
+	writel(0x20042004, DBSC3_0_DBADJ2);
+
+	/* S3C -QoS */
+	s3c = (struct r8a7790_s3c *)S3C_BASE;
+	writel(0x80FF1C1E, &s3c->s3cadsplcr);
+	writel(0x1F060505, &s3c->s3crorr);
+	writel(0x1F020100, &s3c->s3cworr);
+
+	/* QoS Control Registers */
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI0_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_CCI1_BASE;
+	writel(0x00800080, &s3c_qos->s3cqos0);
+	writel(0x22000010, &s3c_qos->s3cqos1);
+	writel(0x22002200, &s3c_qos->s3cqos2);
+	writel(0x2F002200, &s3c_qos->s3cqos3);
+	writel(0x2F002F00, &s3c_qos->s3cqos4);
+	writel(0x22000010, &s3c_qos->s3cqos5);
+	writel(0x22002200, &s3c_qos->s3cqos6);
+	writel(0x2F002200, &s3c_qos->s3cqos7);
+	writel(0x2F002F00, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_MXI_BASE;
+	writel(0x80918099, &s3c_qos->s3cqos0);
+	writel(0x20410010, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	s3c_qos = (struct r8a7790_s3c_qos *)S3C_QOS_AXI_BASE;
+
+	writel(0x00810089, &s3c_qos->s3cqos0);
+	writel(0x20410001, &s3c_qos->s3cqos1);
+	writel(0x200A2023, &s3c_qos->s3cqos2);
+	writel(0x20502001, &s3c_qos->s3cqos3);
+	writel(0x00002032, &s3c_qos->s3cqos4);
+	writel(0x20410FFF, &s3c_qos->s3cqos5);
+	writel(0x200A2023, &s3c_qos->s3cqos6);
+	writel(0x20502001, &s3c_qos->s3cqos7);
+	writel(0x20142032, &s3c_qos->s3cqos8);
+
+	writel(0x00200808, &s3c->s3carcr11);
+
+	/* DBSC -QoS */
+	/* DBSC0 - Read/Write */
+	for (i = DBSC3_R00; i < DBSC3_NR; i++) {
+		qos_addr = (struct r8a7790_dbsc3_qos *)dbsc3_qos_addr[i];
+		writel(0x00000203, &qos_addr->dblgcnt);
+		writel(0x00002064, &qos_addr->dbtmval0);
+		writel(0x00002048, &qos_addr->dbtmval1);
+		writel(0x00002032, &qos_addr->dbtmval2);
+		writel(0x00002019, &qos_addr->dbtmval3);
+		writel(0x00000001, &qos_addr->dbrqctr);
+		writel(0x00002019, &qos_addr->dbthres0);
+		writel(0x00002019, &qos_addr->dbthres1);
+		writel(0x00002019, &qos_addr->dbthres2);
+		writel(0x00000000, &qos_addr->dblgqon);
+	}
+	/* CCI-400 -QoS */
+	writel(0x20001000, CCI_400_MAXOT_1);
+	writel(0x20001000, CCI_400_MAXOT_2);
+	writel(0x0000000C, CCI_400_QOSCNTL_1);
+	writel(0x0000000C, CCI_400_QOSCNTL_2);
+
+	/* MXI -QoS */
+	/* Transaction Control (MXI) */
+	mxi = (struct r8a7790_mxi *)MXI_BASE;
+	writel(0x00000013, &mxi->mxrtcr);
+	writel(0x00000013, &mxi->mxwtcr);
+	writel(0x00B800C0, &mxi->mxsaar0);
+	writel(0x02000800, &mxi->mxsaar1);
+	writel(0x00200000, &mxi->mxs3cracr);
+	writel(0x00200000, &mxi->mxs3cwacr);
+	writel(0x00200000, &mxi->mxaxiracr);
+	writel(0x00200000, &mxi->mxaxiwacr);
+
+	/* QoS Control (MXI) */
+	mxi_qos = (struct r8a7790_mxi_qos *)MXI_QOS_BASE;
+	writel(0x0000000C, &mxi_qos->vspdu0);
+	writel(0x0000000C, &mxi_qos->vspdu1);
+	writel(0x0000000D, &mxi_qos->du0);
+	writel(0x0000000D, &mxi_qos->du1);
+
+	/* AXI -QoS */
+	/* Transaction Control (MXI) */
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SYX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_AVB_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_G2D_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMP1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002004, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX0_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX1_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_IMUX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_LBS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_MTSB1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_PCI_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_RTX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS0_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_SDS1_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200A, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB20_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB21_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB22_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI_USB30_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (RT-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_SHX_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002005, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RDS_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_RTX64TO128_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)RT_AXI_STPRO_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002003, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (MP-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ADSP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_ASDS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002014, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MLP_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002002, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPU_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MP_AXI_SPUC_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200D, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (SYS-AXI256) */
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_SYX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MPX_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)SYS_AXI256_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (CCI-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS0_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_SYX2_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUDS_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUM_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MXI_BASE;
+	writel(0x00000002, &axi_qos->qosconf);
+	writel(0x0000200F, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUS1_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)CCI_AXI_MMUMP_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002001, &axi_qos->qosctset0);
+	writel(0x00002009, &axi_qos->qosctset1);
+	writel(0x00002003, &axi_qos->qosctset2);
+	writel(0x00002003, &axi_qos->qosctset3);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000000, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	/* QoS Register (Media-AXI) */
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_JPW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_GCU1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_TDMW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPDU1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002018, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VIN0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP0W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMSW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP1W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_IMRW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_FDP2W_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VSPD1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU0W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1R_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_DU1W_BASE;
+	writel(0x00000000, &axi_qos->qosconf);
+	writel(0x0000200C, &axi_qos->qosctset0);
+	writel(0x00000001, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC0R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1CW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VR_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VCP1VW_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000001, &axi_qos->qosqon);
+
+	axi_qos = (struct r8a7790_axi_qos *)MEDIA_AXI_VPC1R_BASE;
+	writel(0x00000001, &axi_qos->qosconf);
+	writel(0x00002007, &axi_qos->qosctset0);
+	writel(0x00000020, &axi_qos->qosreqctr);
+	writel(0x00002006, &axi_qos->qosthres0);
+	writel(0x00002001, &axi_qos->qosthres1);
+	writel(0x00000001, &axi_qos->qosthres2);
+	writel(0x00000000, &axi_qos->qosqon);
+}
diff --git a/board/renesas/lager/qos.h b/board/renesas/lager/qos.h
new file mode 100644
index 0000000..9a6c046
--- /dev/null
+++ b/board/renesas/lager/qos.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __QOS_H__
+#define __QOS_H__
+
+void qos_init(void);
+
+#endif
diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c
index 223a516..cc4c2a0 100644
--- a/board/ronetix/pm9261/led.c
+++ b/board/ronetix/pm9261/led.c
@@ -8,9 +8,9 @@
  */
 
 #include <common.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/io.h>
 
 void coloured_LED_init(void)
 {
@@ -19,11 +19,11 @@
 	/* Enable clock */
 	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
 
-	at91_set_pio_output(CONFIG_RED_LED, 1);
-	at91_set_pio_output(CONFIG_GREEN_LED, 1);
-	at91_set_pio_output(CONFIG_YELLOW_LED, 1);
+	gpio_direction_output(CONFIG_RED_LED, 1);
+	gpio_direction_output(CONFIG_GREEN_LED, 1);
+	gpio_direction_output(CONFIG_YELLOW_LED, 1);
 
-	at91_set_pio_value(CONFIG_RED_LED, 0);
-	at91_set_pio_value(CONFIG_GREEN_LED, 1);
-	at91_set_pio_value(CONFIG_YELLOW_LED, 1);
+	gpio_set_value(CONFIG_RED_LED, 0);
+	gpio_set_value(CONFIG_GREEN_LED, 1);
+	gpio_set_value(CONFIG_YELLOW_LED, 1);
 }
diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c
index a2a569b..a634383 100644
--- a/board/ronetix/pm9261/pm9261.c
+++ b/board/ronetix/pm9261/pm9261.c
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <asm/sizes.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -73,10 +74,10 @@
 		&pmc->pcer);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 
 	at91_set_a_periph(AT91_PIO_PORTC, 0, 0);	/* NANDOE */
 	at91_set_a_periph(AT91_PIO_PORTC, 1, 0);	/* NANDWE */
diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c
index 44e3430..bfc2310 100644
--- a/board/ronetix/pm9263/led.c
+++ b/board/ronetix/pm9263/led.c
@@ -8,9 +8,9 @@
  */
 
 #include <common.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/io.h>
 
 void coloured_LED_init(void)
 {
@@ -19,9 +19,9 @@
 	/* Enable clock */
 	writel(1 << ATMEL_ID_PIOB, &pmc->pcer);
 
-	at91_set_pio_output(CONFIG_RED_LED, 1);
-	at91_set_pio_output(CONFIG_GREEN_LED, 1);
+	gpio_direction_output(CONFIG_RED_LED, 1);
+	gpio_direction_output(CONFIG_GREEN_LED, 1);
 
-	at91_set_pio_value(CONFIG_RED_LED, 0);
-	at91_set_pio_value(CONFIG_GREEN_LED, 1);
+	gpio_set_value(CONFIG_RED_LED, 0);
+	gpio_set_value(CONFIG_GREEN_LED, 1);
 }
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 48eba99..3cedeef 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -11,6 +11,7 @@
 #include <common.h>
 #include <asm/sizes.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -67,10 +68,10 @@
 		&smc->cs[3].mode);
 
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c
index 5bb5a3c..c9f2747 100644
--- a/board/ronetix/pm9g45/pm9g45.c
+++ b/board/ronetix/pm9g45/pm9g45.c
@@ -14,6 +14,7 @@
 #include <common.h>
 #include <asm/sizes.h>
 #include <asm/io.h>
+#include <asm/gpio.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
@@ -66,11 +67,11 @@
 
 #ifdef CONFIG_SYS_NAND_READY_PIN
 	/* Configure RDY/BSY */
-	at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+	gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
 #endif
 
 	/* Enable NandFlash */
-	at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+	gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 }
 #endif
 
diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c
index 44be5fc..8aba51c 100644
--- a/board/samsung/trats/trats.c
+++ b/board/samsung/trats/trats.c
@@ -504,6 +504,17 @@
 	debug("USB_udc_probe\n");
 	return s3c_udc_probe(&s5pc210_otg_data);
 }
+
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
+{
+	struct pmic *muic = pmic_get("MAX8997_MUIC");
+	if (!muic)
+		return 0;
+
+	return !!muic->chrg->chrg_type(muic);
+}
+#endif
 #endif
 
 static void pmic_reset(void)
diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c
index 8df85ee..147de17 100644
--- a/board/samsung/trats2/trats2.c
+++ b/board/samsung/trats2/trats2.c
@@ -25,6 +25,9 @@
 #include <power/max77693_fg.h>
 #include <libtizen.h>
 #include <errno.h>
+#include <usb.h>
+#include <usb/s3c_udc.h>
+#include <usb_mass_storage.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,7 +43,7 @@
 	int modelrev = 0;
 	int i;
 
-	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+	gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
 
 	/*
 	 * GPM1[1:0]: MODEL_REV[1:0]
@@ -90,7 +93,7 @@
 
 static void board_external_gpio_init(void)
 {
-	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+	gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
 
 	/*
 	 * some pins which in alive block are connected with external pull-up
@@ -117,8 +120,8 @@
 {
 	int err;
 
-	gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
-	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+	gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
+	gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
 
 	/* I2C_7 */
 	err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
@@ -170,7 +173,7 @@
 int board_init(void)
 {
 	struct exynos4_power *pwr =
-		(struct exynos4_power *)EXYNOS4X12_POWER_BASE;
+		(struct exynos4_power *)samsung_get_base_power();
 
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
@@ -277,7 +280,7 @@
 {
 	int err0, err2 = 0;
 
-	gpio2 = (struct exynos4x12_gpio_part2 *)EXYNOS4X12_GPIO_PART2_BASE;
+	gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
 
 	/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
 	s5p_gpio_direction_output(&gpio2->k0, 2, 1);
@@ -331,6 +334,95 @@
 	return err0 & err2;
 }
 
+#ifdef CONFIG_USB_GADGET
+static int s5pc210_phy_control(int on)
+{
+	int ret = 0;
+	unsigned int val;
+	struct pmic *p, *p_pmic, *p_muic;
+
+	p_pmic = pmic_get("MAX77686_PMIC");
+	if (!p_pmic)
+		return -ENODEV;
+
+	if (pmic_probe(p_pmic))
+		return -1;
+
+	p_muic = pmic_get("MAX77693_MUIC");
+	if (!p_muic)
+		return -ENODEV;
+
+	if (pmic_probe(p_muic))
+		return -1;
+
+	if (on) {
+		ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
+		if (ret)
+			return -1;
+
+		p = pmic_get("MAX77693_PMIC");
+		if (!p)
+			return -ENODEV;
+
+		if (pmic_probe(p))
+			return -1;
+
+		/* SAFEOUT */
+		ret = pmic_reg_read(p, MAX77693_SAFEOUT, &val);
+		if (ret)
+			return -1;
+
+		val |= MAX77693_ENSAFEOUT1;
+		ret = pmic_reg_write(p, MAX77693_SAFEOUT, val);
+		if (ret)
+			return -1;
+
+		/* PATH: USB */
+		ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
+			MAX77693_MUIC_CTRL1_DN1DP2);
+
+	} else {
+		ret = max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
+		if (ret)
+			return -1;
+
+		/* PATH: UART */
+		ret = pmic_reg_write(p_muic, MAX77693_MUIC_CONTROL1,
+			MAX77693_MUIC_CTRL1_UT1UR2);
+	}
+
+	if (ret)
+		return -1;
+
+	return 0;
+}
+
+struct s3c_plat_otg_data s5pc210_otg_data = {
+	.phy_control	= s5pc210_phy_control,
+	.regs_phy	= EXYNOS4X12_USBPHY_BASE,
+	.regs_otg	= EXYNOS4X12_USBOTG_BASE,
+	.usb_phy_ctrl	= EXYNOS4X12_USBPHY_CONTROL,
+	.usb_flags	= PHY0_SLEEP,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("USB_udc_probe\n");
+	return s3c_udc_probe(&s5pc210_otg_data);
+}
+
+#ifdef CONFIG_USB_CABLE_CHECK
+int usb_cable_connected(void)
+{
+	struct pmic *muic = pmic_get("MAX77693_MUIC");
+	if (!muic)
+		return 0;
+
+	return !!muic->chrg->chrg_type(muic);
+}
+#endif
+#endif
+
 static int pmic_init_max77686(void)
 {
 	struct pmic *p = pmic_get("MAX77686_PMIC");
@@ -444,7 +536,7 @@
 {
 	struct pmic *p = pmic_get("MAX77686_PMIC");
 
-	gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
+	gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
 
 	/* LCD_2.2V_EN: GPC0[1] */
 	s5p_gpio_set_pull(&gpio1->c0, 1, GPIO_PULL_UP);
@@ -458,7 +550,7 @@
 
 void exynos_reset_lcd(void)
 {
-	gpio1 = (struct exynos4x12_gpio_part1 *)EXYNOS4X12_GPIO_PART1_BASE;
+	gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
 
 	/* reset lcd */
 	s5p_gpio_direction_output(&gpio1->f2, 1, 0);
diff --git a/board/siemens/common/factoryset.c b/board/siemens/common/factoryset.c
index fbe7997..266dbbb 100644
--- a/board/siemens/common/factoryset.c
+++ b/board/siemens/common/factoryset.c
@@ -15,7 +15,8 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/unaligned.h>
 #include <net.h>
-#include <usbdescriptors.h>
+#include <errno.h>
+#include <g_dnl.h>
 #include "factoryset.h"
 
 #define EEPR_PG_SZ		0x80
@@ -224,8 +225,20 @@
 					MAX_STRING_LENGTH)) {
 		debug("display name: %s\n", factory_dat.disp_name);
 	}
-
 #endif
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+					(uchar *)"num", factory_dat.serial,
+					MAX_STRING_LENGTH)) {
+		debug("serial number: %s\n", factory_dat.serial);
+	}
+	if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
+					(uchar *)"ver", buf,
+					MAX_STRING_LENGTH)) {
+		factory_dat.version = simple_strtoul((char *)buf,
+							    NULL, 16);
+		debug("version number: %d\n", factory_dat.version);
+	}
+
 	return 0;
 
 err:
@@ -279,6 +292,13 @@
 {
 	put_unaligned(factory_dat.usb_vendor_id, &dev->idVendor);
 	put_unaligned(factory_dat.usb_product_id, &dev->idProduct);
+	g_dnl_set_serialnumber((char *)factory_dat.serial);
+
 	return 0;
 }
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+	return factory_dat.version;
+}
 #endif /* defined(CONFIG_SPL_BUILD) */
diff --git a/board/siemens/common/factoryset.h b/board/siemens/common/factoryset.h
index 445f384..4d6de10 100644
--- a/board/siemens/common/factoryset.h
+++ b/board/siemens/common/factoryset.h
@@ -18,6 +18,8 @@
 #if defined(CONFIG_VIDEO)
 	unsigned char disp_name[MAX_STRING_LENGTH];
 #endif
+	unsigned char serial[MAX_STRING_LENGTH];
+	int version;
 };
 
 int factoryset_read_eeprom(int i2c_addr);
diff --git a/board/siemens/corvus/Makefile b/board/siemens/corvus/Makefile
new file mode 100644
index 0000000..f3ebf77
--- /dev/null
+++ b/board/siemens/corvus/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for siemens CORVUS (AT91SAM9G45) based board
+# (C) Copyright 2013 Siemens AG
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += board.o
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
new file mode 100644
index 0000000..f1e93ef
--- /dev/null
+++ b/board/siemens/corvus/board.c
@@ -0,0 +1,195 @@
+/*
+ * Board functions for Siemens CORVUS (AT91SAM9G45) based board
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9g45_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/clk.h>
+#include <lcd.h>
+#include <atmel_lcdc.h>
+#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
+#include <net.h>
+#endif
+#include <netdev.h>
+#include <spi.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void corvus_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+	       AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+	       AT91_SMC_MODE_DBW_8 |
+#endif
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_CMD_USB
+static void taurus_usb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
+
+	at91_set_gpio_output(AT91_PIN_PD1, 0);
+	at91_set_gpio_output(AT91_PIN_PD3, 0);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void corvus_macb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clock */
+	writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *      RXDV (PA15) => PHY normal mode (not Test mode)
+	 *      ERX0 (PA12) => PHY ADDR0
+	 *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 0);
+
+	at91_phy_reset();
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+
+	/* And the pins. */
+	at91_macb_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+	at91_seriald_hw_init();
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+#ifdef CONFIG_CMD_NAND
+	corvus_nand_hw_init();
+#endif
+#ifdef CONFIG_ATMEL_SPI
+	at91_spi0_hw_init(1 << 4);
+#endif
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	corvus_macb_hw_init();
+#endif
+#ifdef CONFIG_CMD_USB
+	taurus_usb_hw_init();
+#endif
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+/* SPI chip select control */
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+	return bus == 0 && cs < 2;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 0);
+			break;
+	case 0:
+	default:
+			at91_set_gpio_output(AT91_PIN_PB3, 0);
+			break;
+	}
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+	switch (slave->cs) {
+	case 1:
+			at91_set_gpio_output(AT91_PIN_PB18, 1);
+			break;
+	case 0:
+	default:
+			at91_set_gpio_output(AT91_PIN_PB3, 1);
+			break;
+	}
+}
diff --git a/board/siemens/dxr2/board.c b/board/siemens/dxr2/board.c
index af9d84f..3a5e11d 100644
--- a/board/siemens/dxr2/board.c
+++ b/board/siemens/dxr2/board.c
@@ -38,11 +38,11 @@
 
 #ifdef CONFIG_SPL_BUILD
 static struct dxr2_baseboard_id __attribute__((section(".data"))) settings;
-
+/* @303MHz-i0 */
 const struct ddr3_data ddr3_default = {
-	0x33524444, 0x56312e33, 0x0100, 0x0001, 0x003A, 0x008A, 0x010B,
-	0x00C4, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x0006, 0x61C04AB2,
-	0x00000618,
+	0x33524444, 0x56312e34, 0x0080, 0x0000, 0x0038, 0x003E, 0x00A4,
+	0x0075, 0x0888A39B, 0x26247FDA, 0x501F821F, 0x00100206, 0x61A44A32,
+	0x00000618, 0x0000014A,
 };
 
 static void set_default_ddr3_timings(void)
@@ -73,6 +73,7 @@
 
 	PRINTARGS(sdram_config);
 	PRINTARGS(ref_ctrl);
+	PRINTARGS(ioctr_val);
 }
 
 static void print_chip_data(void)
@@ -139,13 +140,9 @@
 };
 
 struct ddr_data dxr2_ddr3_data = {
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 struct cmd_control dxr2_ddr3_cmd_ctrl_data = {
-	.cmd0dldiff = 0,
-	.cmd1dldiff = 0,
-	.cmd2dldiff = 0,
 };
 	/* pass values from eeprom */
 	dxr2_ddr3_emif_reg_data.sdram_tim1 = settings.ddr3.sdram_tim1;
@@ -168,7 +165,7 @@
 	dxr2_ddr3_cmd_ctrl_data.cmd2csratio = settings.ddr3.ddr3_sratio;
 	dxr2_ddr3_cmd_ctrl_data.cmd2iclkout = settings.ddr3.iclkout;
 
-	config_ddr(DDR_PLL_FREQ, DXR2_IOCTRL_VAL, &dxr2_ddr3_data,
+	config_ddr(DDR_PLL_FREQ, settings.ddr3.ioctr_val, &dxr2_ddr3_data,
 		   &dxr2_ddr3_cmd_ctrl_data, &dxr2_ddr3_emif_reg_data, 0);
 }
 
diff --git a/board/siemens/dxr2/board.h b/board/siemens/dxr2/board.h
index 2be78fb..abf5432 100644
--- a/board/siemens/dxr2/board.h
+++ b/board/siemens/dxr2/board.h
@@ -22,11 +22,11 @@
 #define MAGIC_CHIP	0x50494843
 
 /* Automatic generated definition */
-/* Wed, 19 Jun 2013 10:57:48 +0200 */
-/* From file: draco/ddr3-data-micron.txt */
+/* Wed, 18 Sep 2013 18:58:27 +0200 */
+/* From file: draco/ddr3-data-micron-v2.txt */
 struct ddr3_data {
 	unsigned int magic;			/* 0x33524444 */
-	unsigned int version;			/* 0x56312e33 */
+	unsigned int version;			/* 0x56312e34 */
 	unsigned short int ddr3_sratio;		/* 0x0100 */
 	unsigned short int iclkout;		/* 0x0001 */
 	unsigned short int dt0rdsratio0;	/* 0x003A */
@@ -36,9 +36,10 @@
 	unsigned int sdram_tim1;		/* 0x0888A39B */
 	unsigned int sdram_tim2;		/* 0x26247FDA */
 	unsigned int sdram_tim3;		/* 0x501F821F */
-	unsigned short int emif_ddr_phy_ctlr_1;	/* 0x0006 */
+	unsigned int emif_ddr_phy_ctlr_1;	/* 0x00100206 */
 	unsigned int sdram_config;		/* 0x61C04AB2 */
 	unsigned int ref_ctrl;			/* 0x00000618 */
+	unsigned int ioctr_val;			/* 0x0000018B */
 };
 
 struct chip_data {
diff --git a/board/siemens/dxr2/mux.c b/board/siemens/dxr2/mux.c
index bc80b79..5c22999 100644
--- a/board/siemens/dxr2/mux.c
+++ b/board/siemens/dxr2/mux.c
@@ -63,6 +63,164 @@
 	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDEN | RXACTIVE)},
 	{OFFSET(gpmc_csn3), MODE(7) },			/* LED0 GPIO2_0 */
 	{OFFSET(emu0), MODE(7)},			/* LED1 GPIO3_7 */
+	/* Triacs in HW Rev 2 */
+	{OFFSET(uart1_ctsn), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y5 GPIO0_12*/
+	{OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y3 GPIO2_28*/
+	{OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE},	/* Y7 GPIO2_27*/
+	/* Triacs initial HW Rev */
+	{OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_30 Y0 */
+	{OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_28 Y1 */
+	{OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_31 Y2 */
+	{OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS},	/* 0_11 Y3 */
+	{OFFSET(lcd_data14), MODE(7) | RXACTIVE | PULLUDDIS},	/* 0_10 Y4 */
+	{OFFSET(gpmc_clk), MODE(7) | RXACTIVE | PULLUDDIS},	/* 2_1  Y5 */
+	{OFFSET(emu1), MODE(7) | RXACTIVE | PULLUDDIS},		/* 3_8  Y6 */
+	{OFFSET(gpmc_ad15), MODE(7) | RXACTIVE | PULLUDDIS},	/* 1_15 Y7 */
+	/* Remaining pins that were not used in this file */
+	{OFFSET(gpmc_ad8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_ad9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(gpmc_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_data9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_vsync), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_hsync), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_pclk), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(lcd_ac_bias_en), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_dat3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_dat0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_clk), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mmc0_cmd), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_sclk), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(spi0_cs0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart0_ctsn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart0_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart1_rtsn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart1_rxd), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(uart1_txd), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_aclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_fsx), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_axr0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_ahclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_aclkr), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_fsr), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_axr1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(mcasp0_ahclkx), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(xdma_event_intr0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(xdma_event_intr1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(nresetin_out), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(porz), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(nnmi), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc0_in), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc0_out), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(rsvd1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tms), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tdi), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tdo), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(tck), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ntrst), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc1_in), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(osc1_out), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(pmic_power_en), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(rtc_porz), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(rsvd2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ext_wakeup), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(enz_kaldo_1p8v), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_id), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb0_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_dm), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_dp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_ce), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_id), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_vbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(usb1_drvvbus), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_resetn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_csn0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_cke), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ck), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_nck), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_casn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_rasn), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_wen), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ba0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ba1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_ba2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a10), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a11), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a12), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a13), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a14), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_a15), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_odt), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d8), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d9), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d10), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d11), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d12), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d13), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d14), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_d15), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqm0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqm1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqs0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqsn0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqs1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_dqsn1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_vref), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_vtp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_strben0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ddr_strben1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain7), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain6), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain5), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain4), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain3), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain2), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain1), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(ain0), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(vrefp), MODE(7) | RXACTIVE | PULLUDDIS},
+	{OFFSET(vrefn), MODE(7) | RXACTIVE | PULLUDDIS},
 	{-1},
 };
 
diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c
index 2c1841f..0a25b4b 100644
--- a/board/siemens/pxm2/board.c
+++ b/board/siemens/pxm2/board.c
@@ -58,19 +58,14 @@
 	.datawdsratio0 = 0,
 	.datafwsratio0 = 0x8020080,
 	.datawrsratio0 = 0x4010040,
-	.datauserank0delay = 1,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 struct cmd_control pxm2_ddr3_cmd_ctrl_data = {
 	.cmd0csratio = 0x80,
-	.cmd0dldiff = 0,
 	.cmd0iclkout = 0,
 	.cmd1csratio = 0x80,
-	.cmd1dldiff = 0,
 	.cmd1iclkout = 0,
 	.cmd2csratio = 0x80,
-	.cmd2dldiff = 0,
 	.cmd2iclkout = 0,
 };
 
@@ -413,8 +408,7 @@
 
 static int board_video_init(void)
 {
-	/* set 300 MHz */
-	conf_disp_pll(25, 2);
+	conf_disp_pll(24, 1);
 	if (factory_dat.pxm50)
 		da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
 	else
diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c
index 5de8fc6..77592db 100644
--- a/board/siemens/rut/board.c
+++ b/board/siemens/rut/board.c
@@ -63,19 +63,14 @@
 	.datawdsratio0 = 0x85,
 	.datafwsratio0 = 0x100,
 	.datawrsratio0 = 0xc1,
-	.datauserank0delay = 1,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 struct cmd_control rut_ddr3_cmd_ctrl_data = {
 	.cmd0csratio = 0x40,
-	.cmd0dldiff = 0,
 	.cmd0iclkout = 1,
 	.cmd1csratio = 0x40,
-	.cmd1dldiff = 0,
 	.cmd1iclkout = 1,
 	.cmd2csratio = 0x40,
-	.cmd2dldiff = 0,
 	.cmd2iclkout = 1,
 };
 
@@ -83,9 +78,48 @@
 		   &rut_ddr3_cmd_ctrl_data, &rut_ddr3_emif_reg_data, 0);
 }
 
+static int request_and_pulse_reset(int gpio, const char *name)
+{
+	int ret;
+	const int delay_us = 2000; /* 2ms */
+
+	ret = gpio_request(gpio, name);
+	if (ret < 0) {
+		printf("%s: Unable to request %s\n", __func__, name);
+		goto err;
+	}
+
+	ret = gpio_direction_output(gpio, 0);
+	if (ret < 0) {
+		printf("%s: Unable to set %s  as output\n", __func__, name);
+		goto err_free_gpio;
+	}
+
+	udelay(delay_us);
+
+	gpio_set_value(gpio, 1);
+
+	return 0;
+
+err_free_gpio:
+	gpio_free(gpio);
+err:
+	return ret;
+}
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#define ETH_PHY_RESET_GPIO		GPIO_TO_PIN(2, 18)
+#define MAXTOUCH_RESET_GPIO		GPIO_TO_PIN(3, 18)
+#define DISPLAY_RESET_GPIO		GPIO_TO_PIN(3, 19)
+
+#define REQUEST_AND_PULSE_RESET(N) \
+		request_and_pulse_reset(N, #N);
+
 static void spl_siemens_board_init(void)
 {
-	return;
+	REQUEST_AND_PULSE_RESET(ETH_PHY_RESET_GPIO);
+	REQUEST_AND_PULSE_RESET(MAXTOUCH_RESET_GPIO);
+	REQUEST_AND_PULSE_RESET(DISPLAY_RESET_GPIO);
 }
 #endif /* if def CONFIG_SPL_BUILD */
 
@@ -336,7 +370,6 @@
 static int conf_disp_pll(int m, int n)
 {
 	struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
-	struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
 	struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
 #if defined(DISPL_PLL_SPREAD_SPECTRUM)
 	struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
@@ -353,8 +386,6 @@
 		0
 	};
 	do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
-	/* 0x44e0_0500 write lcdc pixel clock mux Linux hat hier 0 */
-	writel(0x0, &cmdpll->clklcdcpixelclk);
 
 	do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
 
@@ -380,10 +411,13 @@
 {
 	unsigned char buf[1];
 
+	set_gpio(BOARD_LCD_RESET, 0);
+	mdelay(1);
 	set_gpio(BOARD_LCD_RESET, 1);
+	mdelay(1);
 
 	/* spi lcd init */
-	kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_3);
+	kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
 
 	/* backlight on */
 	buf[0] = 0xf;
@@ -418,7 +452,7 @@
 		printf("%s: %s not found, using default %s\n", __func__,
 		       factory_dat.disp_name, lcd_panels[i].name);
 	}
-	conf_disp_pll(25, 2);
+	conf_disp_pll(24, 1);
 	da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
 			 lcd_cfgs[display].bpp);
 
diff --git a/board/siemens/taurus/Makefile b/board/siemens/taurus/Makefile
new file mode 100644
index 0000000..a26fb92
--- /dev/null
+++ b/board/siemens/taurus/Makefile
@@ -0,0 +1,18 @@
+#
+# Makefile for Siemens TAURUS (AT91SAM9G20) based board
+# (C) Copyright 2013 Siemens AG
+#
+# Based on:
+# U-Boot file: board/atmel/at91sam9260ek/Makefile
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian@popies.net>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= taurus.o
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
new file mode 100644
index 0000000..673b302
--- /dev/null
+++ b/board/siemens/taurus/taurus.c
@@ -0,0 +1,160 @@
+/*
+ * Board functions for Siemens TAURUS (AT91SAM9G20) based boards
+ * (C) Copyright Siemens AG
+ *
+ * Based on:
+ * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/at91sam9260_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/at91sam9_sdramc.h>
+#include <atmel_mci.h>
+
+#include <net.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static void taurus_nand_hw_init(void)
+{
+	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+	struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	unsigned long csa;
+
+	/* Assign CS3 to NAND/SmartMedia Interface */
+	csa = readl(&matrix->ebicsa);
+	csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
+	writel(csa, &matrix->ebicsa);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
+	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
+	       &smc->cs[3].setup);
+	writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
+	       AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3),
+	       &smc->cs[3].pulse);
+	writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
+	       &smc->cs[3].cycle);
+	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+	       AT91_SMC_MODE_EXNW_DISABLE |
+	       AT91_SMC_MODE_DBW_8 |
+	       AT91_SMC_MODE_TDF_CYCLE(3),
+	       &smc->cs[3].mode);
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#ifdef CONFIG_MACB
+static void taurus_macb_hw_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable EMAC clock */
+	writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
+
+	/*
+	 * Disable pull-up on:
+	 *	RXDV (PA17) => PHY normal mode (not Test mode)
+	 *	ERX0 (PA14) => PHY ADDR0
+	 *	ERX1 (PA15) => PHY ADDR1
+	 *	ERX2 (PA25) => PHY ADDR2
+	 *	ERX3 (PA26) => PHY ADDR3
+	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
+	 *
+	 * PHY has internal pull-down
+	 */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);
+
+	at91_phy_reset();
+
+	at91_set_gpio_input(AT91_PIN_PA25, 1);   /* ERST tri-state */
+
+	/* Re-enable pull-up */
+	at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);
+
+	/* Initialize EMAC=MACB hardware */
+	at91_macb_hw_init();
+}
+#endif
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+int board_mmc_init(bd_t *bd)
+{
+	at91_mci_hw_init();
+
+	return atmel_mci_init((void *)ATMEL_BASE_MCI);
+}
+#endif
+
+int board_early_init_f(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+	/* Enable clocks for all PIOs */
+	writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
+		(1 << ATMEL_ID_PIOC),
+		&pmc->pcer);
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	at91_seriald_hw_init();
+#ifdef CONFIG_CMD_NAND
+	taurus_nand_hw_init();
+#endif
+#ifdef CONFIG_MACB
+	taurus_macb_hw_init();
+#endif
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
+#endif
+	return rc;
+}
diff --git a/board/taskit/stamp9g20/stamp9g20.c b/board/taskit/stamp9g20/stamp9g20.c
index 704a63b..27cdf77 100644
--- a/board/taskit/stamp9g20/stamp9g20.c
+++ b/board/taskit/stamp9g20/stamp9g20.c
@@ -19,7 +19,6 @@
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
-#include <asm/arch/at91_rstc.h>
 #include <asm/arch/gpio.h>
 #include <watchdog.h>
 
@@ -67,8 +66,6 @@
 static void stamp9G20_macb_hw_init(void)
 {
 	struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
-	struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
-	unsigned long erstl;
 
 	/* Enable the PHY Chip via PA26 on the Stamp 2 Adaptor */
 	at91_set_gpio_output(AT91_PIN_PA26, 0);
@@ -91,33 +88,7 @@
 		pin_to_mask(AT91_PIN_PA28),
 		&pioa->pudr);
 
-	erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
-
-	/* Need to reset PHY -> 500ms reset */
-	writel(AT91_RSTC_KEY | (AT91_RSTC_MR_ERSTL(13) &
-				~AT91_RSTC_MR_URSTEN), &rstc->mr);
-	writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
-
-	/* Wait for end of hardware reset */
-	unsigned long start = get_timer(0);
-	unsigned long timeout = 1000; /* 1000ms */
-
-	while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
-
-		/* avoid shutdown by watchdog */
-		WATCHDOG_RESET();
-		mdelay(10);
-
-		/* timeout for not getting stuck in an endless loop */
-		if (get_timer(start) >= timeout) {
-			puts("*** ERROR: Timeout waiting for PHY reset!\n");
-			break;
-		};
-	};
-
-	/* Restore NRST value */
-	writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
-		&rstc->mr);
+	at91_phy_reset();
 
 	/* Re-enable pull-up */
 	writel(pin_to_mask(AT91_PIN_PA14) |
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index db225ce..33693e4 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -107,21 +107,16 @@
 			  (MT47H128M16RT25E_PHY_WR_DATA<<20) |
 			  (MT47H128M16RT25E_PHY_WR_DATA<<10) |
 			  (MT47H128M16RT25E_PHY_WR_DATA<<0)),
-	.datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr2_cmd_ctrl_data = {
 	.cmd0csratio = MT47H128M16RT25E_RATIO,
-	.cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd1csratio = MT47H128M16RT25E_RATIO,
-	.cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 
 	.cmd2csratio = MT47H128M16RT25E_RATIO,
-	.cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
 };
 
@@ -139,7 +134,6 @@
 	.datawdsratio0 = MT41J128MJT125_WR_DQS,
 	.datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct ddr_data ddr3_beagleblack_data = {
@@ -147,7 +141,6 @@
 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
 	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
 	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct ddr_data ddr3_evm_data = {
@@ -155,48 +148,38 @@
 	.datawdsratio0 = MT41J512M8RH125_WR_DQS,
 	.datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
 	.datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
-	.datadldiff0 = PHY_DLL_LOCK_DIFF,
 };
 
 static const struct cmd_control ddr3_cmd_ctrl_data = {
 	.cmd0csratio = MT41J128MJT125_RATIO,
-	.cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41J128MJT125_RATIO,
-	.cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41J128MJT125_RATIO,
-	.cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
 };
 
 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
 	.cmd0csratio = MT41K256M16HA125E_RATIO,
-	.cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41K256M16HA125E_RATIO,
-	.cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41K256M16HA125E_RATIO,
-	.cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
 };
 
 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
 	.cmd0csratio = MT41J512M8RH125_RATIO,
-	.cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 	.cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 
 	.cmd1csratio = MT41J512M8RH125_RATIO,
-	.cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 	.cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 
 	.cmd2csratio = MT41J512M8RH125_RATIO,
-	.cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
 	.cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
 };
 
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
index e77a501..6a734b3 100644
--- a/board/ti/am335x/u-boot.lds
+++ b/board/ti/am335x/u-boot.lds
@@ -108,10 +108,13 @@
 		KEEP(*(.__bss_end));
 	}
 
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c
index 9657c75..9ae88c5 100644
--- a/board/ti/dra7xx/evm.c
+++ b/board/ti/dra7xx/evm.c
@@ -14,6 +14,7 @@
 #include <palmas.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sata.h>
 
 #include "mux_data.h"
 
@@ -77,6 +78,12 @@
 	return 0;
 }
 
+int board_late_init(void)
+{
+	omap_sata_init();
+	return 0;
+}
+
 /**
  * @brief misc_init_r - Configure EVM board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index bb3a699..af854da 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -20,6 +20,7 @@
 #include <asm/arch/clock.h>
 #include <asm/arch/ehci.h>
 #include <asm/ehci-omap.h>
+#include <asm/arch/sata.h>
 
 #define DIE_ID_REG_BASE     (OMAP54XX_L4_CORE_BASE + 0x2000)
 #define DIE_ID_REG_OFFSET	0x200
@@ -67,6 +68,12 @@
 	return 0;
 }
 
+int board_late_init(void)
+{
+	omap_sata_init();
+	return 0;
+}
+
 int board_eth_init(bd_t *bis)
 {
 	return 0;
diff --git a/board/ti/omap730p2/Makefile b/board/ti/omap730p2/Makefile
deleted file mode 100644
index 8242f3d..0000000
--- a/board/ti/omap730p2/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= omap730p2.o flash.o
-obj-y	+= lowlevel_init.o
diff --git a/board/ti/omap730p2/README.omap730p2 b/board/ti/omap730p2/README.omap730p2
deleted file mode 100644
index 7c70916..0000000
--- a/board/ti/omap730p2/README.omap730p2
+++ /dev/null
@@ -1,91 +0,0 @@
-
-		     u-boot for the TI OMAP730 Perseus2
-
-		      Dave Peverley, MPC-Data Limited
-			 http://www.mpc-data.co.uk
-
-
-Overview :
-
- As the OMAP730 is similar to the OMAP1610 in many ways, this port was based
-on the u-boot port to the OMAP1610 Innovator. Supported features are :
-
-  - Serial terminal support
-  - Onboard NOR Flash
-  - Ethernet via the seperate debug board
-  - Tested on Rev4 and Rev5 boards
-
- It has also been tested to work correctly when built with a 'standard' GCC
-3.2.1 cross-compiler as well as Montavista Linux CEE 3.1's toolchain.
-
-
-Hardware Configuration :
-
- The main dips on the P2 board should be set to 2,3,7 and 9 on with all
-others off. On the debug board, dips 1 and 7 should be on with the rest off.
-The serial console has been set up to run from the DB9 connector on the
-P2 board at 115200 baud, 8 data bits, no stop bits, 1 parity bit.
-
- It should be noted that the P2 board has NOR flash that is addressable via
-either CS0 or CS3. This mode can be changed via DIP9 on the P2 board.
-
-
-Installing u-boot for the P2 :
-
- You can simply build u-boot for the Perseus by following the instructions
-in the main readme file. The target configuration is "omap730p2_config".
-Once u-boot has been built, you should strip the executable so it can be
-loaded via CCS (which cant cope with the symbols in the ELF binary) :
-  $ cp u-boot u-boot.out
-  $ arm-linux-strip u-boot.out
-
- The method we've used for installing u-boot the first time on a P2 is
-as follows :
-
-1) Configure TI Code Composer Studio to connect to the P2 board via JTAG
-   as described in the Users Guide.
-
-2) Set up the P2 to boot from CS3, and connect with CCS. Reset the CPU
-   and run the "init_mmu" GEL script.
-
-3) Use the "Load Program" option to send the u-boot.out file to the P2 and
-   run.
-
- At this point, u-boot should run and you will see the boot menu on your
-serial terminal. You can then load the u-boot image to memory :
-
-  # loadb 0x10000000
-
- Send the "u-boot.bin" binary via the serial using Kermit. Once loaded
-you can self-flash u-boot :
-
-  # protect off 1:0
-  # erase 1:0
-  # cp.b 0x10000000 0x0 0x20000
-
- You should now be able to reset the board and run u-boot from flash.
-
-
-Alternative flash option :
-
- Sometimes, if you've been silly, you can get the board into a state where
-whats in flash has upset the board so much that you can no longer connect
-to the P2 via JTAG. However, you can set DIP9 to off to swap the boot mode
-of the P2 so that you boot from RAM instead of NOR flash. This moves NOR
-flash up to 0x0C000000. You can build a special version of u-boot to
-utilise this by the following config :
-
-  $ make omap730p2_cs0boot_config
-
- If you load this up via CCS it will detect flash at its alternate location
-and allow you to programme your u-boot image (which, remember must be built
-for CS3 boot!) Once you do this, you can revert to CS3 boot and it will work
-fine again.
-
-
-Errata :
-
-1) It's been observed that sometimes the tftp transfer of kernels to the
-   board can have checksum errors or stall. This appears to be an issue
-   with the lan91c96.c driver, and can normally be worked around by
-   resetting the board and trying again.
diff --git a/board/ti/omap730p2/config.mk b/board/ti/omap730p2/config.mk
deleted file mode 100644
index 8618820..0000000
--- a/board/ti/omap730p2/config.mk
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
-#
-# (C) Copyright 2003
-# Texas Instruments, <www.ti.com>
-# Kshitij Gupta <Kshitij@ti.com>
-#
-# TI Perseus 2 board with OMAP720 (ARM925EJS) cpu
-# see http://www.ti.com/ for more information on Texas Instruments
-#
-# Innovator has 1 bank of 256 MB SDRAM
-# Physical Address:
-# 1000'0000 to 2000'0000
-#
-#
-# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000
-# (mem base + reserved)
-#
-# we load ourself to 1108'0000
-#
-#
-
-CONFIG_SYS_TEXT_BASE = 0x11080000
diff --git a/board/ti/omap730p2/flash.c b/board/ti/omap730p2/flash.c
deleted file mode 100644
index 56f981c..0000000
--- a/board/ti/omap730p2/flash.c
+++ /dev/null
@@ -1,463 +0,0 @@
-/*
- * (C) Copyright 2001
- * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
- *
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <linux/byteorder/swab.h>
-
-#define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
-
-/* Board support for 1 or 2 flash devices */
-#undef FLASH_PORT_WIDTH32
-#define FLASH_PORT_WIDTH16
-
-#ifdef FLASH_PORT_WIDTH16
-#define FLASH_PORT_WIDTH		ushort
-#define FLASH_PORT_WIDTHV		vu_short
-#define SWAP(x)			__swab16(x)
-#else
-#define FLASH_PORT_WIDTH		ulong
-#define FLASH_PORT_WIDTHV		vu_long
-#define SWAP(x)			__swab32(x)
-#endif
-
-#define FPW	FLASH_PORT_WIDTH
-#define FPWV	FLASH_PORT_WIDTHV
-
-#define mb() __asm__ __volatile__ ("" : : : "memory")
-
-
-/* Flash Organization Structure */
-typedef struct OrgDef {
-	unsigned int sector_number;
-	unsigned int sector_size;
-} OrgDef;
-
-
-/* Flash Organizations */
-OrgDef OrgIntel_28F256L18T[] = {
-	{4, 32 * 1024},				/* 4 * 32kBytes sectors */
-	{255, 128 * 1024},			/* 255 * 128kBytes sectors */
-};
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-unsigned long flash_init (void);
-static ulong flash_get_size (FPW * addr, flash_info_t * info);
-static int write_data (flash_info_t * info, ulong dest, FPW data);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-void inline spin_wheel (void);
-void flash_print_info (flash_info_t * info);
-void flash_unprotect_sectors (FPWV * addr);
-int flash_erase (flash_info_t * info, int s_first, int s_last);
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	int i;
-	ulong size = 0;
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
-		switch (i) {
-		case 0:
-			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
-			flash_get_offsets (PHYS_FLASH_1, &flash_info[i]);
-			break;
-		default:
-			panic ("configured too many flash banks!\n");
-			break;
-		}
-		size += flash_info[i].size;
-	}
-
-	/* Protect monitor and environment sectors
-	 */
-	flash_protect (FLAG_PROTECT_SET,
-			CONFIG_SYS_FLASH_BASE,
-			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
-
-	flash_protect (FLAG_PROTECT_SET,
-			CONFIG_ENV_ADDR,
-			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]);
-
-	return size;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return;
-	}
-
-	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-		for (i = 0; i < info->sector_count; i++) {
-			if (i > 255) {
-				info->start[i] = base + (i * 0x8000);
-				info->protect[i] = 0;
-			} else {
-				info->start[i] = base +
-						(i * PHYS_FLASH_SECT_SIZE);
-				info->protect[i] = 0;
-			}
-		}
-	}
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
-	int i;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_INTEL:
-		printf ("INTEL ");
-		break;
-	default:
-		printf ("Unknown Vendor ");
-		break;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_28F256L18T:
-		printf ("FLASH 28F256L18T\n");
-		break;
-	default:
-		printf ("Unknown Chip Type\n");
-		break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-			info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i = 0; i < info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i], info->protect[i] ? " (RO)" : "     ");
-	}
-	printf ("\n");
-	return;
-}
-
-/*
- * The following code cannot be run from FLASH!
- */
-static ulong flash_get_size (FPW * addr, flash_info_t * info)
-{
-	volatile FPW value;
-
-	/* Write auto select command: read Manufacturer ID */
-	addr[0x5555] = (FPW) 0x00AA00AA;
-	addr[0x2AAA] = (FPW) 0x00550055;
-	addr[0x5555] = (FPW) 0x00900090;
-
-	mb ();
-	value = addr[0];
-
-	switch (value) {
-
-	case (FPW) INTEL_MANUFACT:
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-		return (0);		/* no or unknown flash  */
-	}
-
-	mb ();
-	value = addr[1];	/* device ID        */
-	switch (value) {
-
-	case (FPW) (INTEL_ID_28F256L18T):
-		info->flash_id += FLASH_28F256L18T;
-		info->sector_count = 259;
-		info->size = 0x02000000;
-		break;			/* => 32 MB     */
-
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		break;
-	}
-
-	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
-		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
-		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
-	}
-
-	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
-
-	return (info->size);
-}
-
-
-/* unprotects a sector for write and erase
- * on some intel parts, this unprotects the entire chip, but it
- * wont hurt to call this additional times per sector...
- */
-void flash_unprotect_sectors (FPWV * addr)
-{
-#define PD_FINTEL_WSMS_READY_MASK    0x0080
-
-	*addr = (FPW) 0x00500050;	/* clear status register */
-
-	/* this sends the clear lock bit command */
-	*addr = (FPW) 0x00600060;
-	*addr = (FPW) 0x00D000D0;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
-	int flag, prot, sect;
-	ulong type, start;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	type = (info->flash_id & FLASH_VENDMASK);
-	if ((type != FLASH_MAN_INTEL)) {
-		printf ("Can't erase unknown flash type %08lx - aborted\n",
-				info->flash_id);
-		return 1;
-	}
-
-	prot = 0;
-	for (sect = s_first; sect <= s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-				prot);
-	} else {
-		printf ("\n");
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect <= s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			FPWV *addr = (FPWV *) (info->start[sect]);
-			FPW status;
-
-			printf ("Erasing sector %2d ... ", sect);
-
-			flash_unprotect_sectors (addr);
-
-			/* arm simple, non interrupt dependent timer */
-			start = get_timer(0);
-
-			*addr = (FPW) 0x00500050;/* clear status register */
-			*addr = (FPW) 0x00200020;/* erase setup */
-			*addr = (FPW) 0x00D000D0;/* erase confirm */
-
-			while (((status =
-				*addr) & (FPW) 0x00800080) !=
-				(FPW) 0x00800080) {
-					if (get_timer(start) >
-					CONFIG_SYS_FLASH_ERASE_TOUT) {
-					printf ("Timeout\n");
-					/* suspend erase     */
-					*addr = (FPW) 0x00B000B0;
-					/* reset to read mode */
-					*addr = (FPW) 0x00FF00FF;
-					rcode = 1;
-					break;
-				}
-			}
-
-			/* clear status register cmd.   */
-			*addr = (FPW) 0x00500050;
-			*addr = (FPW) 0x00FF00FF;/* resest to read mode */
-			printf (" done\n");
-		}
-	}
-
-	if (flag)
-		enable_interrupts();
-
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - Flash not identified
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
-	ulong cp, wp;
-	FPW data;
-	int count, i, l, rc, port_width;
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		return 4;
-	}
-/* get lower word aligned address */
-#ifdef FLASH_PORT_WIDTH16
-	wp = (addr & ~1);
-	port_width = 2;
-#else
-	wp = (addr & ~3);
-	port_width = 4;
-#endif
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i = 0, cp = wp; i < l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-		for (; i < port_width && cnt > 0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt == 0 && i < port_width; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *) cp);
-		}
-
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	count = 0;
-	while (cnt >= port_width) {
-		data = 0;
-		for (i = 0; i < port_width; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_data (info, wp, SWAP (data))) != 0) {
-			return (rc);
-		}
-		wp += port_width;
-		cnt -= port_width;
-		if (count++ > 0x800) {
-			spin_wheel ();
-			count = 0;
-		}
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i < port_width; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *) cp);
-	}
-
-	return (write_data (info, wp, SWAP (data)));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word or halfword to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_data (flash_info_t * info, ulong dest, FPW data)
-{
-	FPWV *addr = (FPWV *) dest;
-	ulong status;
-	int flag, rc = 0;
-	ulong start;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*addr & data) != data) {
-		printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr);
-		return (2);
-	}
-	flash_unprotect_sectors (addr);
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-	*addr = (FPW) 0x00400040;	/* write setup */
-	*addr = data;
-
-	/* arm simple, non interrupt dependent timer */
-	start = get_timer(0);
-
-	/* wait while polling the status register */
-	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-			rc = 1;
-			goto done;
-		}
-	}
-done:
-	*addr = (FPW)0x00FF00FF;	/* restore read mode */
-	if (flag)
-		enable_interrupts();
-	return rc;
-}
-
-void inline spin_wheel (void)
-{
-	static int p = 0;
-	static char w[] = "\\/-";
-
-	printf ("\010%c", w[p]);
-	(++p == 3) ? (p = 0) : 0;
-}
diff --git a/board/ti/omap730p2/lowlevel_init.S b/board/ti/omap730p2/lowlevel_init.S
deleted file mode 100644
index 795c495..0000000
--- a/board/ti/omap730p2/lowlevel_init.S
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * Board specific setup info
- *
- * (C) Copyright 2003-2004
- *
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
- *
- * Modified for OMAP730 P2 Board by Dave Peverley, MPC-Data Limited
- * (http://www.mpc-data.co.uk)
- *
- * TODO : Tidy up and change to use system register defines
- *        from omap730.h where possible.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <version.h>
-
-#if defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
-_TEXT_BASE:
-	.word	CONFIG_SYS_TEXT_BASE	/* sdram load addr from config.mk */
-
-.globl lowlevel_init
-lowlevel_init:
-	/* Save callers address in r11 - r11 must never be modified */
-	mov r11, lr
-
-	/*------------------------------------------------------*
-	 *mask all IRQs by setting all bits in the INTMR default*
-	 *------------------------------------------------------*/
-	mov	r1,	#0xffffffff
-	ldr	r0,	=REG_IHL1_MIR
-	str	r1,	[r0]
-	ldr	r0,	=REG_IHL2_MIR
-	str	r1,	[r0]
-
-	/*------------------------------------------------------*
-	 * Set up ARM CLM registers (IDLECT1)                   *
-	 *------------------------------------------------------*/
-	ldr	r0,	REG_ARM_IDLECT1
-	ldr	r1,	VAL_ARM_IDLECT1
-	str	r1,	[r0]
-
-	/*------------------------------------------------------*
-	 * Set up ARM CLM registers (IDLECT2)		        *
-	 *------------------------------------------------------*/
-	ldr	r0,	REG_ARM_IDLECT2
-	ldr	r1,	VAL_ARM_IDLECT2
-	str	r1,	[r0]
-
-	/*------------------------------------------------------*
-	 * Set up ARM CLM registers (IDLECT3)		        *
-	 *------------------------------------------------------*/
-	ldr	r0,	REG_ARM_IDLECT3
-	ldr	r1,	VAL_ARM_IDLECT3
-	str	r1,	[r0]
-
-
-	mov	r1,	#0x01		/* PER_EN bit */
-	ldr	r0,	REG_ARM_RSTCT2
-	strh	r1,	[r0]		/* CLKM; Peripheral reset. */
-
-	/* Set CLKM to Sync-Scalable	*/
-	/* I supposedly need to enable the dsp clock before switching */
-	mov	r1,	#0x1000
-	ldr	r0,	REG_ARM_SYSST
-	strh	r1,	[r0]
-	mov	r0,	#0x400
-1:
-	subs	r0,	r0,	#0x1	/* wait for any bubbles to finish */
-	bne	1b
-	ldr	r1,	VAL_ARM_CKCTL
-	ldr	r0,	REG_ARM_CKCTL
-	strh	r1,	[r0]
-
-	/* a few nops to let settle */
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	/* setup DPLL 1 */
-	/* Ramp up the clock to 96Mhz */
-	ldr	r1,	VAL_DPLL1_CTL
-	ldr	r0,	REG_DPLL1_CTL
-	strh	r1,	[r0]
-	ands	r1,	r1,	#0x10	/* Check if PLL is enabled. */
-	beq	lock_end	/* Do not look for lock if BYPASS selected */
-2:
-	ldrh	r1,	[r0]
-	ands	r1,	r1,	#0x01	/*	Check the LOCK bit.*/
-	beq 2b			/*	loop until bit goes hi. */
-lock_end:
-
-	/*------------------------------------------------------*
-	 * Turn off the watchdog during init...			*
-	 *------------------------------------------------------*/
-	ldr	r0,	REG_WATCHDOG
-	ldr	r1,	WATCHDOG_VAL1
-	str	r1,	[r0]
-	ldr	r1,	WATCHDOG_VAL2
-	str	r1,	[r0]
-	ldr	r0,	REG_WSPRDOG
-	ldr	r1,	WSPRDOG_VAL1
-	str	r1,	[r0]
-	ldr	r0,	REG_WWPSDOG
-
-watch1Wait:
-	ldr	r1,	[r0]
-	tst	r1,	#0x10
-	bne	watch1Wait
-
-	ldr	r0,	REG_WSPRDOG
-	ldr	r1,	WSPRDOG_VAL2
-	str	r1,	[r0]
-	ldr	r0,	REG_WWPSDOG
-watch2Wait:
-	ldr	r1,	[r0]
-	tst	r1,	#0x10
-	bne	watch2Wait
-
-	/* Set memory timings corresponding to the new clock speed */
-
-	/* Check execution location to determine current execution location
-	 * and branch to appropriate initialization code.
-	 */
-	/* Compare physical SDRAM base & current execution location. */
-	and     r0, pc, #0xF0000000
-	/* Compare. */
-	cmp     r0, #0
-	/* Skip over EMIF-fast initialization if running from SDRAM. */
-	bne	skip_sdram
-
-	/*
-	* Delay for SDRAM initialization.
-	*/
-	mov	r3,	#0x1800		/* value should be checked */
-3:
-	subs	r3,	r3,	#0x1	/* Decrement count */
-	bne	3b
-
-	ldr	r0,	REG_SDRAM_CONFIG
-	ldr	r1,	SDRAM_CONFIG_VAL
-	str	r1,	[r0]
-
-	ldr	r0,	REG_SDRAM_MRS_LEGACY
-	ldr	r1,	SDRAM_MRS_VAL
-	str	r1,	[r0]
-
-skip_sdram:
-
-common_tc:
-	/* slow interface */
-	ldr	r1,	VAL_TC_EMIFS_CS0_CONFIG
-	ldr	r0,	REG_TC_EMIFS_CS0_CONFIG
-	str	r1,	[r0] /* Chip Select 0 */
-
-	ldr	r1,	VAL_TC_EMIFS_CS1_CONFIG
-	ldr	r0,	REG_TC_EMIFS_CS1_CONFIG
-	str	r1,	[r0] /* Chip Select 1 */
-	ldr	r1,	VAL_TC_EMIFS_CS2_CONFIG
-	ldr	r0,	REG_TC_EMIFS_CS2_CONFIG
-	str	r1,	[r0] /* Chip Select 2 */
-	ldr	r1,	VAL_TC_EMIFS_CS3_CONFIG
-	ldr	r0,	REG_TC_EMIFS_CS3_CONFIG
-	str	r1,	[r0] /* Chip Select 3 */
-
-	/* 48MHz clock request for UART1 */
-	ldr	r1,	PERSEUS2_CONFIG_BASE
-	ldrh	r0,	[r1, #CONFIG_PCC_CONF]
-	orr	r0,	r0, #CONF_MOD_UART1_CLK_MODE_R
-	strh	r0,	[r1, #CONFIG_PCC_CONF]
-
-	/* Initialize public and private rheas
-	 *  - set access factor 2 on both rhea / strobe
-	 *  - disable write buffer on strb0, enable write buffer on strb1
-	 */
-
-	ldr	R0,	REG_RHEA_PUB_CTL
-	ldr	R1,	REG_RHEA_PRIV_CTL
-	ldr	R2,	VAL_RHEA_CTL
-	strh	R2,	[R0]
-	strh	R2,	[R1]
-	mov	R3,	#2          /* disable write buffer on strb0, enable write buffer on strb1 */
-	strh	R3,	[R0, #0x08]	/* arm rhea control reg */
-	strh	R3,	[R1, #0x08]
-
-	/* enable IRQ and FIQ */
-
-	mrs	r4,	CPSR
-	bic	r4,	r4, #IRQ_MASK
-	bic	r4,	r4, #FIQ_MASK
-	msr	CPSR,	r4
-
-	/* set TAP CONF to TRI EMULATION */
-
-	ldr	r1,	[r0, #CONFIG_MODE2]
-	bic	r1,	r1, #0x18
-	orr	r1,	r1, #0x10
-	str	r1,	[r0, #CONFIG_MODE2]
-
-	/* set tdbgen to 1 */
-
-	ldr	r0,	PERSEUS2_CONFIG_BASE
-	ldr	r1,	[r0, #CONFIG_MODE1]
-	mov	r2,	#0x10000
-	orr	r1,	r1, r2
-	str	r1,	[r0, #CONFIG_MODE1]
-
-#ifdef CONFIG_P2_OMAP1610
-	/* inserting additional 2 clock cycle hold time for LAN */
-	ldr     r0,     REG_TC_EMIFS_CS1_ADVANCED
-	ldr	r1,     VAL_TC_EMIFS_CS1_ADVANCED
-	str     r1,     [r0]
-#endif
-	/* Start MPU Timer 1 */
-	ldr	r0,	REG_MPU_LOAD_TIMER
-	ldr	r1,	VAL_MPU_LOAD_TIMER
-	str	r1,	[r0]
-
-	ldr	r0,	REG_MPU_CNTL_TIMER
-	ldr	r1,	VAL_MPU_CNTL_TIMER
-	str	r1,	[r0]
-
-	/* back to arch calling code */
-	mov	pc,	r11
-
-	/* the literal pools origin */
-	.ltorg
-
-REG_TC_EMIFS_CONFIG:		/* 32 bits */
-	.word 0xfffecc0c
-REG_TC_EMIFS_CS0_CONFIG:	/* 32 bits */
-	.word 0xfffecc10
-REG_TC_EMIFS_CS1_CONFIG:	/* 32 bits */
-	.word 0xfffecc14
-REG_TC_EMIFS_CS2_CONFIG:	/* 32 bits */
-	.word 0xfffecc18
-REG_TC_EMIFS_CS3_CONFIG:	/* 32 bits */
-	.word 0xfffecc1c
-
-#ifdef CONFIG_P2_OMAP730
-REG_TC_EMIFS_CS1_ADVANCED:	/* 32 bits */
-	.word 0xfffecc54
-#endif
-
-/* MPU clock/reset/power mode control registers */
-REG_ARM_CKCTL:			/* 16 bits */
-	.word 0xfffece00
-
-REG_ARM_IDLECT3:		/* 16 bits */
-	.word 0xfffece24
-REG_ARM_IDLECT2:		/* 16 bits */
-	.word 0xfffece08
-REG_ARM_IDLECT1:		/* 16 bits */
-	.word 0xfffece04
-
-REG_ARM_RSTCT2:			/* 16 bits */
-	.word 0xfffece14
-REG_ARM_SYSST:			/* 16 bits */
-	.word 0xfffece18
-/* DPLL control registers */
-REG_DPLL1_CTL:			/* 16 bits */
-	.word 0xfffecf00
-
-/* Watch Dog register */
-/* secure watchdog stop */
-REG_WSPRDOG:
-	.word 0xfffeb048
-/* watchdog write pending */
-REG_WWPSDOG:
-	.word 0xfffeb034
-
-WSPRDOG_VAL1:
-	.word 0x0000aaaa
-WSPRDOG_VAL2:
-	.word 0x00005555
-
-/* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
- counter @8192 rows, 10 ns, 8 burst */
-REG_SDRAM_CONFIG:
-	.word 0xfffecc20
-
-REG_SDRAM_MRS_LEGACY:
-	.word 0xfffecc24
-
-REG_WATCHDOG:
-	.word 0xfffec808
-
-REG_MPU_LOAD_TIMER:
-	.word 0xfffec504
-REG_MPU_CNTL_TIMER:
-	.word 0xfffec500
-
-/* Public and private rhea bridge registers definition */
-
-REG_RHEA_PUB_CTL:
-	.word 0xFFFECA00
-
-REG_RHEA_PRIV_CTL:
-	.word 0xFFFED300
-
-/* EMIFF SDRAM Configuration register
-   - self refresh disable
-   - auto refresh enabled
-   - SDRAM type 64 Mb, 16 bits bus 4 banks
-   - power down enabled
-   - SDRAM clock disabled
- */
-SDRAM_CONFIG_VAL:
-	.word 0x0C017DF4
-
-/* Burst full page length ; cas latency = 3 */
-SDRAM_MRS_VAL:
-	.word 0x00000037
-
-VAL_ARM_CKCTL:
-	.word 0x6505
-VAL_DPLL1_CTL:
-	.word 0x3412
-
-#ifdef CONFIG_P2_OMAP730
-VAL_TC_EMIFS_CS0_CONFIG:
-	.word 0x0000FFF3
-VAL_TC_EMIFS_CS1_CONFIG:
-	.word 0x00004278
-VAL_TC_EMIFS_CS2_CONFIG:
-	.word 0x00004278
-VAL_TC_EMIFS_CS3_CONFIG:
-	.word 0x00004278
-VAL_TC_EMIFS_CS1_ADVANCED:
-	.word 0x00000022
-#endif
-
-VAL_ARM_IDLECT1:
-	.word 0x00000400
-VAL_ARM_IDLECT2:
-	.word 0x00000886
-VAL_ARM_IDLECT3:
-	.word 0x00000015
-
-WATCHDOG_VAL1:
-	.word 0x000000f5
-WATCHDOG_VAL2:
-	.word 0x000000a0
-
-VAL_MPU_LOAD_TIMER:
-	.word 0xffffffff
-VAL_MPU_CNTL_TIMER:
-	.word 0xffffffa1
-
-VAL_RHEA_CTL:
-	.word			0xFF22
-
-/* Config Register vals */
-PERSEUS2_CONFIG_BASE:
-	.word			0xFFFE1000
-
-.equ	CONFIG_PCC_CONF,	0xB4
-.equ	CONFIG_MODE1,		0x10
-.equ	CONFIG_MODE2,		0x14
-.equ	CONF_MOD_UART1_CLK_MODE_R,	0x0A
-
-/* misc values */
-.equ	IRQ_MASK,		0x80           /* IRQ mask value */
-.equ	FIQ_MASK,		0x40           /* FIQ mask value */
diff --git a/board/ti/omap730p2/omap730p2.c b/board/ti/omap730p2/omap730p2.c
deleted file mode 100644
index 554019c..0000000
--- a/board/ti/omap730p2/omap730p2.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- * Kshitij Gupta <Kshitij@ti.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#if defined(CONFIG_OMAP730)
-#include <./configs/omap730.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int test_boot_mode(void);
-void spin_up_leds(void);
-void flash__init (void);
-void ether__init (void);
-void set_muxconf_regs (void);
-void peripheral_power_enable (void);
-
-#define FLASH_ON_CS0	1
-#define FLASH_ON_CS3	0
-
-static inline void delay (unsigned long loops)
-{
-	__asm__ volatile ("1:\n"
-			  "subs %0, %1, #1\n"
-			  "bne 1b":"=r" (loops):"0" (loops));
-}
-
-int test_boot_mode(void)
-{
-	/* Check for CS0 and CS3 address decode swapping */
-	if (*((volatile int *)EMIFS_CONFIG) & 0x00000002)
-		return(FLASH_ON_CS3);
-	else
-		return(FLASH_ON_CS0);
-}
-
-/* Toggle backup LED indication */
-void toggle_backup_led(void)
-{
-	static int  backupLEDState = 0;	 /* Init variable so that the LED will be ON the first time */
-	volatile unsigned int *IOConfReg;
-
-
-	IOConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT);
-
-	if (backupLEDState != 0) {
-		*IOConfReg &= (0xFFFFEFFF);
-		backupLEDState = 0;
-	} else {
-		*IOConfReg |= (0x00001000);
-		backupLEDState = 1;
-	}
-}
-
-/*
- * Miscellaneous platform dependent initialisations
- */
-
-int board_init (void)
-{
-	/* arch number of OMAP 730 P2 Board - Same as the Innovator! */
-	gd->bd->bi_arch_number = MACH_TYPE_OMAP_PERSEUS2;
-
-	/* adress of boot parameters */
-	gd->bd->bi_boot_params = 0x10000100;
-
-	/* Configure MUX settings */
-	set_muxconf_regs ();
-
-	peripheral_power_enable ();
-
-	/* Backup LED indication via GPIO_140 -> Red led if MUX correctly setup */
-	toggle_backup_led();
-
-	/* Hold GSM in reset until needed */
-	*((volatile unsigned short *)M_CTL) &= ~1;
-
-	/*
-	 *  CSx timings, GPIO Mux ... setup
-	 */
-
-	/* Flash: CS0 timings setup */
-	*((volatile unsigned int *) FLASH_CFG_0) = 0x0000fff3;
-	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000088;
-
-	/* Ethernet support trough the debug board */
-	/* CS1 timings setup */
-	*((volatile unsigned int *) FLASH_CFG_1) = 0x0000fff3;
-	*((volatile unsigned int *) FLASH_ACFG_0_1) = 0x00000000;
-
-	/* this speeds up your boot a quite a bit.  However to make it
-	 *  work, you need make sure your kernel startup flush bug is fixed.
-	 *  ... rkw ...
-	 */
-	icache_enable ();
-
-	flash__init ();
-	ether__init ();
-
-	return 0;
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-void flash__init (void)
-{
-	unsigned int regval;
-
-	regval = *((volatile unsigned int *) EMIFS_CONFIG);
-	/* Turn off write protection for flash devices. */
-	regval = regval | 0x0001;
-	*((volatile unsigned int *) EMIFS_CONFIG) = regval;
-}
-
-/*************************************************************
- Routine:ether__init
- Description: take the Ethernet controller out of reset and wait
-			   for the EEPROM load to complete.
-*************************************************************/
-void ether__init (void)
-{
-#define LAN_RESET_REGISTER 0x0400001c
-
-	*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
-	do {
-		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001;
-		udelay (100);
-	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001);
-
-	do {
-		*((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000;
-		udelay (100);
-	} while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000);
-
-#define ETH_CONTROL_REG 0x0400030b
-
-	*((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
-	udelay (100);
-}
-
-/******************************
- Routine:
- Description:
-******************************/
-int dram_init (void)
-{
-	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
-
-	return 0;
-}
-
-/******************************************************
- Routine: set_muxconf_regs
- Description: Setting up the configuration Mux registers
-			  specific to the hardware
-*******************************************************/
-void set_muxconf_regs (void)
-{
-	volatile unsigned int *MuxConfReg;
-	/* set each registers to its reset value; */
-
-	/*
-	 *  Backup LED Indication
-	 */
-
-	/* Configure MUXed pin. Mode 6: GPIO_140 */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF10);
-	*MuxConfReg &= (0xFFFFFF1F);	     /* Clear D_MPU_LPG1 */
-	*MuxConfReg |= 0x000000C0;	     /* Set D_MPU_LPG1 to 0x6 */
-
-	/* Configure GPIO_140 as output */
-	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL);
-	*MuxConfReg &= (0xFFFFEFFF);	     /* Clear direction (output) for GPIO 140 */
-
-	/*
-	 * Configure GPIOs for battery charge & feedback
-	 */
-
-	/* Configure MUXed pin. Mode 6: GPIO_35 */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
-	*MuxConfReg &= 0xFFFFFFF1;	     /* Clear M_CLK_OUT */
-	*MuxConfReg |= 0x0000000C;	     /* Set M_CLK_OUT = 0x6 (GPIOs) */
-
-	/* Configure MUXed pin. Mode 6: GPIO_72,73,74 */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF5);
-	*MuxConfReg &= 0xFFFF1FFF;	     /* Clear D_DDR */
-	*MuxConfReg |= 0x0000C000;	     /* Set D_DDR = 0x6 (GPIOs) */
-
-	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL);
-	*MuxConfReg |= 0x00000100;	     /* Configure GPIO_72 as input */
-	*MuxConfReg &= 0xFFFFFDFF;	     /* Configure GPIO_73 as output	*/
-
-	/*
-	 * Allow battery charge
-	 */
-
-	MuxConfReg = (volatile unsigned int *) ((unsigned int) OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT);
-	*MuxConfReg &= (0xFFFFFDFF);	     /* Clear GPIO_73 pin */
-
-	/*
-	 * Configure MPU_EXT_NIRQ IO in IO_CONF9 register,
-	 * It is used as the Ethernet controller interrupt
-	 */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF9);
-	*MuxConfReg &= 0x1FFFFFFF;
-}
-
-/******************************************************
- Routine: peripheral_power_enable
- Description: Enable the power for UART1
-*******************************************************/
-void peripheral_power_enable (void)
-{
-	volatile unsigned int *MuxConfReg;
-
-
-	/* Set up pins used by UART */
-
-	/* Start UART clock (48MHz) */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS_PCC_CONF_REG);
-	*MuxConfReg &= (0xFFFFFFF7);
-	*MuxConfReg |= (0x00000008);
-
-	/* Get the UART pin in mode0  */
-	MuxConfReg = (volatile unsigned int *) (PERSEUS2_IO_CONF3);
-	*MuxConfReg &= (0xFF1FFFFF);
-	*MuxConfReg &= (0xF1FFFFFF);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_LAN91C96
-	rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index c104024..cda09a9 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -123,6 +123,66 @@
 }
 
 /**
+ * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
+ *
+ *
+ * Detect if we are running on B3 version of ES panda board,
+ * This can be done by reading the level of GPIO 171 and checking the
+ * processor revisions.
+ * GPIO171: 1 => Panda ES Rev B3
+ *
+ * Return : return 1 if Panda ES Rev B3 , else return 0
+ */
+u8 is_panda_es_rev_b3(void)
+{
+        int processor_rev = omap_revision();
+        int ret = 0;
+
+        if ((processor_rev >= OMAP4460_ES1_0 &&
+             processor_rev <= OMAP4460_ES1_1)) {
+
+                /* Setup the mux for the common board ID pins (gpio 171) */
+                writew((IEN | M3),
+			(*ctrl)->control_padconf_core_base + UNIPRO_TX0);
+
+                /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
+                ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
+        }
+        return ret;
+}
+
+#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+/*
+ * emif_get_reg_dump() - emif_get_reg_dump strong function
+ *
+ * @emif_nr - emif base
+ * @regs - reg dump of timing values
+ *
+ * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
+ */
+void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
+{
+	u32 omap4_rev = omap_revision();
+
+	/* Same devices and geometry on both EMIFs */
+	if (omap4_rev == OMAP4430_ES1_0)
+		*regs = &emif_regs_elpida_380_mhz_1cs;
+	else if (omap4_rev == OMAP4430_ES2_0)
+		*regs = &emif_regs_elpida_200_mhz_2cs;
+	else if (omap4_rev == OMAP4430_ES2_3)
+		*regs = &emif_regs_elpida_400_mhz_1cs;
+	else if (omap4_rev < OMAP4470_ES1_0) {
+		if(is_panda_es_rev_b3())
+			*regs = &emif_regs_elpida_400_mhz_1cs;
+		else
+			*regs = &emif_regs_elpida_400_mhz_2cs;
+	}
+	else
+		*regs = &emif_regs_elpida_400_mhz_1cs;
+}
+#endif
+
+/**
  * @brief misc_init_r - Configure Panda board specific configurations
  * such as power configurations, ethernet initialization as phase2 of
  * boot sequence
diff --git a/board/ti/ti814x/evm.c b/board/ti/ti814x/evm.c
index e406326..0b76a77 100644
--- a/board/ti/ti814x/evm.c
+++ b/board/ti/ti814x/evm.c
@@ -33,15 +33,12 @@
 #ifdef CONFIG_SPL_BUILD
 static const struct cmd_control evm_ddr2_cctrl_data = {
 	.cmd0csratio	= 0x80,
-	.cmd0dldiff	= 0x04,
 	.cmd0iclkout	= 0x00,
 
 	.cmd1csratio	= 0x80,
-	.cmd1dldiff	= 0x04,
 	.cmd1iclkout	= 0x00,
 
 	.cmd2csratio	= 0x80,
-	.cmd2dldiff	= 0x04,
 	.cmd2iclkout	= 0x00,
 };
 
@@ -77,8 +74,6 @@
 	.datagiratio0		= ((0<<10) | (0<<0)),
 	.datafwsratio0		= ((0x90<<10) | (0x90<<0)),
 	.datawrsratio0		= ((0x50<<10) | (0x50<<0)),
-	.datauserank0delay	= 1,
-	.datadldiff0		= 0x4,
 };
 
 void set_uart_mux_conf(void)
diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c
index 74d35e9..a53859e 100644
--- a/board/ti/ti816x/evm.c
+++ b/board/ti/ti816x/evm.c
@@ -59,21 +59,16 @@
 	.datagiratio0		= ((0x0<<10) | (0x0<<0)),
 	.datafwsratio0		= ((0x13A<<10) | (0x13A<<0)),
 	.datawrsratio0		= ((0x8A<<10) | (0x8A<<0)),
-	.datauserank0delay	= 0x1,
-	.datadldiff0		= 0x0, /* depend on cpu rev, set later */
 };
 
 static struct cmd_control ddr2_ctrl = {
 	.cmd0csratio	= 0x80,
-	.cmd0dldiff	= 0x04, /* reset value is 0x4 */
 	.cmd0iclkout	= 0x00,
 
 	.cmd1csratio	= 0x80,
-	.cmd1dldiff	= 0x04, /* reset value is 0x4 */
 	.cmd1iclkout	= 0x00,
 
 	.cmd2csratio	= 0x80,
-	.cmd2dldiff	= 0x04, /* reset value is 0x4 */
 	.cmd2iclkout	= 0x00,
 
 };
@@ -150,21 +145,16 @@
 	.datagiratio0		= ((0x20<<10) | 0x20<<0),
 	.datafwsratio0		= ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
 	.datawrsratio0		= (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
-	.datauserank0delay	= 0x1,
-	.datadldiff0		= 0x0, /* depend on cpu rev, set later */
 };
 
 static const struct cmd_control ddr3_ctrl = {
 	.cmd0csratio	= 0x100,
-	.cmd0dldiff	= 0x004, /* reset value is 0x4 */
 	.cmd0iclkout	= 0x001,
 
 	.cmd1csratio	= 0x100,
-	.cmd1dldiff	= 0x004, /* reset value is 0x4 */
 	.cmd1iclkout	= 0x001,
 
 	.cmd2csratio	= 0x100,
-	.cmd2dldiff	= 0x004, /* reset value is 0x4 */
 	.cmd2iclkout	= 0x001,
 };
 
@@ -198,11 +188,6 @@
 	config_dmm(&evm_lisa_map_regs);
 
 #ifdef CONFIG_TI816X_EVM_DDR2
-	ddr2_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-	ddr2_ctrl.cmd0dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-	ddr2_ctrl.cmd1dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-	ddr2_ctrl.cmd2dldiff = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-
 	if (CONFIG_TI816X_USE_EMIF0) {
 		ddr2_emif0_regs.emif_ddr_phy_ctlr_1 =
 			(get_cpu_rev() == 0x1 ? 0x0000010B : 0x0000030B);
@@ -217,8 +202,6 @@
 #endif
 
 #ifdef CONFIG_TI816X_EVM_DDR3
-	ddr3_data.datadldiff0 = (get_cpu_rev() == 0x1 ? 0x0 : 0xF);
-
 	if (CONFIG_TI816X_USE_EMIF0)
 		config_ddr(0, 0, &ddr3_data, &ddr3_ctrl, &ddr3_emif0_regs, 0);
 
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index c9b50e9..02d107c 100644
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -62,13 +62,13 @@
 		__bss_end = .;
 	}
 
-	/DISCARD/ : { *(.bss*) }
-	/DISCARD/ : { *(.dynsym) }
-	/DISCARD/ : { *(.dynstr*) }
-	/DISCARD/ : { *(.dynsym*) }
-	/DISCARD/ : { *(.dynamic*) }
-	/DISCARD/ : { *(.hash*) }
-	/DISCARD/ : { *(.plt*) }
-	/DISCARD/ : { *(.interp*) }
-	/DISCARD/ : { *(.gnu*) }
+	.dynsym _end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.hash : { *(.hash*) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
 }
diff --git a/boards.cfg b/boards.cfg
index 114cc86..2128996 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -119,6 +119,7 @@
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9260_nandflash                  tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH                                                                                           Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9g20_eeprom                     tny_a9260:AT91SAM9G20,SYS_USE_EEPROM                                                                                              Albin Tonnerre <albin.tonnerre@free-electrons.com>
 Active  arm         arm926ejs      at91        calao           tny_a9260           tny_a9g20_nandflash                  tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH                                                                                           Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Active  arm         arm926ejs      at91        calao           usb_a9263           usb_a9263_dataflash                  usb_a9263:AT91SAM9263,SYS_USE_DATAFLASH                                                                                           Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
 Active  arm         arm926ejs      at91        egnite          ethernut5           ethernut5                            ethernut5:AT91SAM9XE                                                                                                              egnite GmbH <info@egnite.de>
 Active  arm         arm926ejs      at91        emk             top9000             top9000eval_xe                       top9000:EVAL9000                                                                                                                  Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
 Active  arm         arm926ejs      at91        emk             top9000             top9000su_xe                         top9000:SU9000                                                                                                                    Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
@@ -139,6 +140,9 @@
 Active  arm         arm926ejs      at91        ronetix         pm9g45              pm9g45                               pm9g45:AT91SAM9G45                                                                                                                Ilko Iliev <iliev@ronetix.at>
 Active  arm         arm926ejs      at91        taskit          stamp9g20           portuxg20                            stamp9g20:AT91SAM9G20,PORTUXG20                                                                                                   Markus Hubig <mhubig@imko.de>
 Active  arm         arm926ejs      at91        taskit          stamp9g20           stamp9g20                            stamp9g20:AT91SAM9G20                                                                                                             Markus Hubig <mhubig@imko.de>
+Active  arm         arm926ejs      at91        siemens         taurus              axm                                  taurus:AT91SAM9G20,MACH_TYPE=2068,BOARD_AXM                                                                                       Heiko Schocher <hs@denx.de>
+Active  arm         arm926ejs      at91        siemens         corvus              corvus                               corvus:AT91SAM9M10G45,SYS_USE_NANDFLASH                                                                                           Heiko Schocher <hs@denx.de>
+Active  arm         arm926ejs      at91        siemens         taurus              taurus                               taurus:AT91SAM9G20,MACH_TYPE=2067,BOARD_TAURUS                                                                                    Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      davinci     ait             cam_enc_4xx         cam_enc_4xx                          cam_enc_4xx                                                                                                                       Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      davinci     Barix           ipam390             ipam390                              -                                                                                                                                 Heiko Schocher <hs@denx.de>
 Active  arm         arm926ejs      davinci     davinci         da8xxevm            da830evm                             -                                                                                                                                 Nick Thompson <nick.thompson@gefanuc.com>
@@ -213,9 +217,6 @@
 Active  arm         arm926ejs      nomadik     st              nhk8815             nhk8815                              -                                                                                                                                 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
 Active  arm         arm926ejs      nomadik     st              nhk8815             nhk8815_onenand                      nhk8815:BOOT_ONENAND                                                                                                              Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it>
 Active  arm         arm926ejs      omap        ti              -                   omap5912osk                          -                                                                                                                                 Rishi Bhattacharya <rishi@ti.com>
-Active  arm         arm926ejs      omap        ti              omap730p2           omap730p2                            omap730p2:CS3_BOOT                                                                                                                Dave Peverley <dpeverley@mpc-data.co.uk>
-Active  arm         arm926ejs      omap        ti              omap730p2           omap730p2_cs0boot                    omap730p2:CS0_BOOT                                                                                                                Dave Peverley <dpeverley@mpc-data.co.uk>
-Active  arm         arm926ejs      omap        ti              omap730p2           omap730p2_cs3boot                    omap730p2:CS3_BOOT                                                                                                                Dave Peverley <dpeverley@mpc-data.co.uk>
 Active  arm         arm926ejs      orion5x     LaCie           -                   edminiv2                             -                                                                                                                                 Albert ARIBAUD <albert.u.boot@aribaud.net>
 Active  arm         arm926ejs      pantheon    Marvell         -                   dkb                                  -                                                                                                                                 Lei Wen <leiwen@marvell.com>
 Active  arm         arm926ejs      spear       spear           -                   x600                                 x600                                                                                                                              Stefan Roese <sr@denx.de>
@@ -247,8 +248,10 @@
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca15_tc2                    -                                                                                                                                 -
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca5x2                       -                                                                                                                                 Matt Waddel <matt.waddel@linaro.org>
 Active  arm         armv7          -           armltd          vexpress            vexpress_ca9x4                       -                                                                                                                                 Matt Waddel <matt.waddel@linaro.org>
+Active  arm         armv7          am33xx      compulab        cm_t335             cm_t335                              cm_t335                                                                                                                           Igor Grinberg <grinberg@compulab.co.il>
 Active  arm         armv7          am33xx      isee            igep0033            am335x_igep0033                      -                                                                                                                                 Enric Balletbo i Serra <eballetbo@iseebcn.com>
-Active  arm         armv7          am33xx      phytec          pcm051              pcm051                               pcm051                                                                                                                            Lars Poeschel <poeschel@lemonage.de>
+Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev1                          pcm051:REV1                                                                                                                       Lars Poeschel <poeschel@lemonage.de>
+Active  arm         armv7          am33xx      phytec          pcm051              pcm051_rev3                          pcm051:REV3                                                                                                                       Lars Poeschel <poeschel@lemonage.de>
 Active  arm         armv7          am33xx      siemens         dxr2                dxr2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         pxm2                pxm2                                 -                                                                                                                                 Roger Meier <r.meier@siemens.com>
 Active  arm         armv7          am33xx      siemens         rut                 rut                                  -                                                                                                                                 Roger Meier <r.meier@siemens.com>
@@ -257,14 +260,14 @@
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_nor                       am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR                                                                                          Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_norboot                   am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT                                                                                      Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_spiboot                   am335x_evm:SERIAL1,CONS_INDEX=1,SPI_BOOT                                                                                          Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart1                     am335x_evm:SERIAL2,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart2                     am335x_evm:SERIAL3,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart3                     am335x_evm:SERIAL4,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart4                     am335x_evm:SERIAL5,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
-Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart5                     am335x_evm:SERIAL6,CONS_INDEX=1,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart1                     am335x_evm:SERIAL2,CONS_INDEX=2,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart2                     am335x_evm:SERIAL3,CONS_INDEX=3,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart3                     am335x_evm:SERIAL4,CONS_INDEX=4,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart4                     am335x_evm:SERIAL5,CONS_INDEX=5,NAND                                                                                              Tom Rini <trini@ti.com>
+Active  arm         armv7          am33xx      ti              am335x              am335x_evm_uart5                     am335x_evm:SERIAL6,CONS_INDEX=6,NAND                                                                                              Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am335x              am335x_evm_usbspl                    am335x_evm:SERIAL1,CONS_INDEX=1,NAND,SPL_USBETH_SUPPORT                                                                           Tom Rini <trini@ti.com>
 Active  arm         armv7          am33xx      ti              am43xx              am43xx_evm                           am43xx_evm:SERIAL1,CONS_INDEX=1                                                                                                   -
-Active  arm         armv7          am33xx      ti              ti814x              ti814x_evm                           -                                                                                                                                 Matt Porter <mporter@ti.com>
+Active  arm         armv7          am33xx      ti              ti814x              ti814x_evm                           -                                                                                                                                 Matt Porter <matt.porter@linaro.org>
 Active  arm         armv7          am33xx      ti              ti816x              ti816x_evm                           -                                                                                                                                 -
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_mmc                       sama5d3xek:SAMA5D3,SYS_USE_MMC                                                                                                    Bo Shen <voice.shen@atmel.com>
 Active  arm         armv7          at91        atmel           sama5d3xek          sama5d3xek_nandflash                 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH                                                                                              Bo Shen <voice.shen@atmel.com>
@@ -341,6 +344,10 @@
 Active  arm         armv7          omap5       ti              omap5_uevm          omap5_uevm                           -                                                                                                                                 -
 Active  arm         armv7          rmobile     atmark-techno   armadillo-800eva    armadillo-800eva                     -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          rmobile     kmc             kzm9g               kzm9g                                -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
+Active  arm         armv7          rmobile     renesas         lager               lager                                -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active  arm         armv7          rmobile     renesas         lager               lager_nor                            lager:NORFLASH                                                                                                                    Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active  arm         armv7          rmobile     renesas         koelsch             koelsch                              -                                                                                                                                 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
+Active  arm         armv7          rmobile     renesas         koelsch             koelsch_nor                          koelsch:NORFLASH                                                                                                                  Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
 Active  arm         armv7          s5pc1xx     samsung         goni                s5p_goni                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
 Active  arm         armv7          s5pc1xx     samsung         smdkc100            smdkc100                             -                                                                                                                                 Minkyu Kang <mk7.kang@samsung.com>
 Active  arm         armv7          socfpga     altera          socfpga             socfpga_cyclone5                     -                                                                                                                                 -
diff --git a/doc/README.at91-soc b/doc/README.at91-soc
index bed035c..ab3f713 100644
--- a/doc/README.at91-soc
+++ b/doc/README.at91-soc
@@ -39,3 +39,10 @@
 3. add new structures for SoC access
 4. Convert arch, driver and boards file to new SoC
 5. remove legacy code, if all boards and drives are ready
+
+2013-10-30 Andreas Bießmann <andreas.devel@googlemail.com>:
+
+The goal is almost reached, we could remove the CONFIG_AT91_LEGACY switch but
+remain the CONFIG_ATMEL_LEGACY switch until the GPIO disaster is fixed. The
+AT91 spi driver has also some CONFIG_ATMEL_LEGACY stuff left, so another point
+to fix until this README can be removed.
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index f045f43..604de0c 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,9 +11,10 @@
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+omap730p2        arm         arm926ejs      -           2013-11-11
 pn62             powerpc     mpc824x        -           2013-11-11  Wolfgang Grandegger <wg@grandegger.com>
-pdnb3            arm         ixp            -           2013-09-24  Stefan Roese <sr@denx.de>
-scpu             arm         ixp            -           2013-09-24  Stefan Roese <sr@denx.de>
+pdnb3            arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
+scpu             arm         ixp            304db0b     2013-09-24  Stefan Roese <sr@denx.de>
 omap1510inn      arm         arm925t        0610a16     2013-09-23  Kshitij Gupta <kshitij@ti.com>
 CANBT            powerpc     405CR          fb8f4fd     2013-08-07  Matthias Fuchs <matthias.fuchs@esd.eu>
 Alaska8220       powerpc     mpc8220        d6ed322     2013-05-11
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index 0daad36..e64df4f 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -379,6 +379,11 @@
 	int rc;
 
 	probe_ent = malloc(sizeof(struct ahci_probe_ent));
+	if (!probe_ent) {
+		printf("%s: No memory for probe_ent\n", __func__);
+		return -ENOMEM;
+	}
+
 	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
 	probe_ent->dev = pdev;
 
@@ -503,7 +508,7 @@
 	mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
 	if (!mem) {
 		free(pp);
-		printf("No mem for table!\n");
+		printf("%s: No mem for table!\n", __func__);
 		return -ENOMEM;
 	}
 
@@ -618,7 +623,7 @@
 		95 - 4,
 	};
 	u8 fis[20];
-	u16 *tmpid;
+	ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
 	u8 port;
 
 	/* Clean ccb data buffer */
@@ -637,14 +642,10 @@
 
 	/* Read id from sata */
 	port = pccb->target;
-	tmpid = malloc(ATA_ID_WORDS * 2);
-	if (!tmpid)
-		return -ENOMEM;
 
 	if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), (u8 *)tmpid,
 				ATA_ID_WORDS * 2, 0)) {
 		debug("scsi_ahci: SCSI inquiry command failure.\n");
-		free(tmpid);
 		return -EIO;
 	}
 
@@ -889,6 +890,11 @@
 	u32 linkmap;
 
 	probe_ent = malloc(sizeof(struct ahci_probe_ent));
+	if (!probe_ent) {
+		printf("%s: No memory for probe_ent\n", __func__);
+		return -ENOMEM;
+	}
+
 	memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
 
 	probe_ent->host_flags = ATA_FLAG_SATA
diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile
index 8256ed0..bed6971 100644
--- a/drivers/bootcount/Makefile
+++ b/drivers/bootcount/Makefile
@@ -6,5 +6,6 @@
 obj-$(CONFIG_AT91SAM9XE)	+= bootcount_at91.o
 obj-$(CONFIG_BLACKFIN)		+= bootcount_blackfin.o
 obj-$(CONFIG_SOC_DA8XX)		+= bootcount_davinci.o
-obj-$(CONFIG_AM33XX)		+= bootcount_davinci.o
+obj-$(CONFIG_BOOTCOUNT_AM33XX)	+= bootcount_davinci.o
 obj-$(CONFIG_BOOTCOUNT_RAM)	+= bootcount_ram.o
+obj-$(CONFIG_BOOTCOUNT_ENV)	+= bootcount_env.o
diff --git a/drivers/bootcount/bootcount_davinci.c b/drivers/bootcount/bootcount_davinci.c
index f0acfad..fa87b5e 100644
--- a/drivers/bootcount/bootcount_davinci.c
+++ b/drivers/bootcount/bootcount_davinci.c
@@ -2,6 +2,10 @@
  * (C) Copyright 2011
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
+ * A bootcount driver for the RTC IP block found on many TI platforms.
+ * This requires the RTC clocks, etc, to be enabled prior to use and
+ * not all boards with this IP block on it will have the RTC in use.
+ *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
diff --git a/drivers/bootcount/bootcount_env.c b/drivers/bootcount/bootcount_env.c
new file mode 100644
index 0000000..2d6e8db
--- /dev/null
+++ b/drivers/bootcount/bootcount_env.c
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2013
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+
+void bootcount_store(ulong a)
+{
+	int upgrade_available = getenv_ulong("upgrade_available", 10, 0);
+
+	if (upgrade_available) {
+		setenv_ulong("bootcount", a);
+		saveenv();
+	}
+}
+
+ulong bootcount_load(void)
+{
+	int upgrade_available = getenv_ulong("upgrade_available", 10, 0);
+	ulong val = 0;
+
+	if (upgrade_available)
+		val = getenv_ulong("bootcount", 10, 0);
+
+	return val;
+}
diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c
index af09786..8b76666 100644
--- a/drivers/gpio/at91_gpio.c
+++ b/drivers/gpio/at91_gpio.c
@@ -14,6 +14,7 @@
 #include <asm/sizes.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pio.h>
+#include <asm/arch/gpio.h>
 
 static struct at91_port *at91_pio_get_port(unsigned port)
 {
@@ -356,9 +357,6 @@
 
 /* Common GPIO API */
 
-#define at91_gpio_to_port(gpio)		(gpio / 32)
-#define at91_gpio_to_pin(gpio)		(gpio % 32)
-
 int gpio_request(unsigned gpio, const char *label)
 {
 	return 0;
diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c
index 396fea8..dfea54a 100644
--- a/drivers/i2c/soft_i2c.c
+++ b/drivers/i2c/soft_i2c.c
@@ -25,7 +25,7 @@
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pio.h>
-#ifdef CONFIG_AT91_LEGACY
+#ifdef CONFIG_ATMEL_LEGACY
 #include <asm/arch/gpio.h>
 #endif
 #endif
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 16b7df0..05ddfbb 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -12,9 +12,8 @@
  */
 
 #include <common.h>
-#include <asm/arch/hardware.h>
+#include <asm/gpio.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/at91_pio.h>
 
 #include <malloc.h>
 #include <nand.h>
@@ -1154,8 +1153,7 @@
 			IO_ADDR_W |= CONFIG_SYS_NAND_MASK_ALE;
 
 #ifdef CONFIG_SYS_NAND_ENABLE_PIN
-		at91_set_gpio_value(CONFIG_SYS_NAND_ENABLE_PIN,
-				    !(ctrl & NAND_NCE));
+		gpio_set_value(CONFIG_SYS_NAND_ENABLE_PIN, !(ctrl & NAND_NCE));
 #endif
 		this->IO_ADDR_W = (void *) IO_ADDR_W;
 	}
@@ -1167,7 +1165,7 @@
 #ifdef CONFIG_SYS_NAND_READY_PIN
 static int at91_nand_ready(struct mtd_info *mtd)
 {
-	return at91_get_gpio_value(CONFIG_SYS_NAND_READY_PIN);
+	return gpio_get_value(CONFIG_SYS_NAND_READY_PIN);
 }
 #endif
 
diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index 73612ea..64d4c56 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -10,19 +10,10 @@
 
 #include <common.h>
 #include <asm/io.h>
-#ifndef CONFIG_AT91_LEGACY
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_emac.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_pio.h>
-#else
-/* remove next 5 lines, if all RM9200 boards convert to at91 arch */
-#include <asm/arch-at91/at91rm9200.h>
-#include <asm/arch-at91/hardware.h>
-#include <asm/arch-at91/at91_emac.h>
-#include <asm/arch-at91/at91_pmc.h>
-#include <asm/arch-at91/at91_pio.h>
-#endif
 #include <net.h>
 #include <netdev.h>
 #include <malloc.h>
diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c
index 39240d9..50167aa 100644
--- a/drivers/net/cpsw.c
+++ b/drivers/net/cpsw.c
@@ -914,7 +914,7 @@
 	void *buffer;
 	int len;
 
-	cpsw_update_link(priv);
+	cpsw_check_link(priv);
 
 	while (cpdma_process(priv, &priv->rx_chan, &buffer, &len) >= 0) {
 		invalidate_dcache_range((unsigned long)buffer,
diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c
index 0858b60..a1c6663 100644
--- a/drivers/power/twl6030.c
+++ b/drivers/power/twl6030.c
@@ -9,6 +9,26 @@
 
 #include <twl6030.h>
 
+static struct twl6030_data *twl;
+
+static struct twl6030_data twl6030_info = {
+	.chip_type	= chip_TWL6030,
+	.adc_rbase	= GPCH0_LSB,
+	.adc_ctrl	= CTRL_P2,
+	.adc_enable	= CTRL_P2_SP2,
+	.vbat_mult	= TWL6030_VBAT_MULT,
+	.vbat_shift	= TWL6030_VBAT_SHIFT,
+};
+
+static struct twl6030_data twl6032_info = {
+	.chip_type	= chip_TWL6032,
+	.adc_rbase	= TWL6032_GPCH0_LSB,
+	.adc_ctrl	= TWL6032_CTRL_P1,
+	.adc_enable	= CTRL_P1_SP1,
+	.vbat_mult	= TWL6032_VBAT_MULT,
+	.vbat_shift	= TWL6032_VBAT_SHIFT,
+};
+
 static int twl6030_gpadc_read_channel(u8 channel_no)
 {
 	u8 lsb = 0;
@@ -16,12 +36,12 @@
 	int ret = 0;
 
 	ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
-				  GPCH0_LSB + channel_no * 2, &lsb);
+				  twl->adc_rbase + channel_no * 2, &lsb);
 	if (ret)
 		return ret;
 
 	ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
-				  GPCH0_MSB + channel_no * 2, &msb);
+				  twl->adc_rbase + 1 + channel_no * 2, &msb);
 	if (ret)
 		return ret;
 
@@ -33,7 +53,8 @@
 	u8 val;
 	int ret = 0;
 
-	ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC, CTRL_P2, CTRL_P2_SP2);
+	ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
+				   twl->adc_ctrl, twl->adc_enable);
 	if (ret)
 		return ret;
 
@@ -41,7 +62,8 @@
 	val =  CTRL_P2_BUSY;
 
 	while (!((val & CTRL_P2_EOCP2) && (!(val & CTRL_P2_BUSY)))) {
-		ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC, CTRL_P2, &val);
+		ret = twl6030_i2c_read_u8(TWL6030_CHIP_ADC,
+					  twl->adc_ctrl, &val);
 		if (ret)
 			return ret;
 		udelay(1000);
@@ -102,6 +124,18 @@
 {
 	int battery_volt = 0;
 	int ret = 0;
+	u8 vbatch;
+
+	if (twl->chip_type == chip_TWL6030) {
+		vbatch = TWL6030_GPADC_VBAT_CHNL;
+	} else {
+		ret = twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
+					   TWL6032_GPSELECT_ISB,
+					   TWL6032_GPADC_VBAT_CHNL);
+		if (ret)
+			return ret;
+		vbatch = 0;
+	}
 
 	/* Start GPADC SW conversion */
 	ret = twl6030_gpadc_sw2_trigger();
@@ -111,12 +145,12 @@
 	}
 
 	/* measure Vbat voltage */
-	battery_volt = twl6030_gpadc_read_channel(7);
+	battery_volt = twl6030_gpadc_read_channel(vbatch);
 	if (battery_volt < 0) {
 		printf("Failed to read battery voltage\n");
 		return ret;
 	}
-	battery_volt = (battery_volt * 25 * 1000) >> (10 + 2);
+	battery_volt = (battery_volt * twl->vbat_mult) >> twl->vbat_shift;
 	printf("Battery Voltage: %d mV\n", battery_volt);
 
 	return battery_volt;
@@ -124,12 +158,35 @@
 
 void twl6030_init_battery_charging(void)
 {
-	u8 stat1 = 0;
+	u8 val = 0;
 	int battery_volt = 0;
 	int ret = 0;
 
+	ret = twl6030_i2c_read_u8(TWL6030_CHIP_USB, USB_PRODUCT_ID_LSB, &val);
+	if (ret) {
+		puts("twl6030_init_battery_charging(): could not determine chip!\n");
+		return;
+	}
+	if (val == 0x30) {
+		twl = &twl6030_info;
+	} else if (val == 0x32) {
+		twl = &twl6032_info;
+	} else {
+		puts("twl6030_init_battery_charging(): unsupported chip type\n");
+		return;
+	}
+
 	/* Enable VBAT measurement */
-	twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS);
+	if (twl->chip_type == chip_TWL6030) {
+		twl6030_i2c_write_u8(TWL6030_CHIP_PM, MISC1, VBAT_MEAS);
+		twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
+				     TWL6030_GPADC_CTRL,
+				     GPADC_CTRL_SCALER_DIV4);
+	} else {
+		twl6030_i2c_write_u8(TWL6030_CHIP_ADC,
+				     TWL6032_GPADC_CTRL2,
+				     GPADC_CTRL2_CH18_SCALER_EN);
+	}
 
 	/* Enable GPADC module */
 	ret = twl6030_i2c_write_u8(TWL6030_CHIP_CHARGER, TOGGLE1, FGS | GPADCS);
@@ -146,10 +203,10 @@
 		printf("Main battery voltage too low!\n");
 
 	/* Check for the presence of USB charger */
-	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &stat1);
+	twl6030_i2c_read_u8(TWL6030_CHIP_CHARGER, CONTROLLER_STAT1, &val);
 
 	/* check for battery presence indirectly via Fuel gauge */
-	if ((stat1 & VBUS_DET) && (battery_volt < 3300))
+	if ((val & VBUS_DET) && (battery_volt < 3300))
 		twl6030_start_usb_charging();
 
 	return;
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index 8dc3d9f..dd95afe 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -147,6 +147,23 @@
 	return 0;
 }
 
+__weak int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+	return gcnum;
+}
+
+static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev)
+{
+	struct usb_gadget *gadget = cdev->gadget;
+	int gcnum;
+
+	gcnum = usb_gadget_controller_number(gadget);
+	if (gcnum > 0)
+		gcnum += 0x200;
+
+	return g_dnl_get_board_bcd_device_number(gcnum);
+}
+
 static int g_dnl_bind(struct usb_composite_dev *cdev)
 {
 	struct usb_gadget *gadget = cdev->gadget;
@@ -181,11 +198,9 @@
 	if (ret)
 		goto error;
 
-	gcnum = usb_gadget_controller_number(gadget);
-
-	debug("gcnum: %d\n", gcnum);
+	gcnum = g_dnl_get_bcd_device_number(cdev);
 	if (gcnum >= 0)
-		device_desc.bcdDevice = cpu_to_le16(0x0200 + gcnum);
+		device_desc.bcdDevice = cpu_to_le16(gcnum);
 	else {
 		debug("%s: controller '%s' not recognized\n",
 			shortname, gadget->name);
diff --git a/drivers/usb/gadget/regs-otg.h b/drivers/usb/gadget/regs-otg.h
index 84bfcc5..ac5d112 100644
--- a/drivers/usb/gadget/regs-otg.h
+++ b/drivers/usb/gadget/regs-otg.h
@@ -226,6 +226,11 @@
 #define CLK_SEL_12MHZ                   (0x2 << 0)
 #define CLK_SEL_48MHZ                   (0x0 << 0)
 
+#define EXYNOS4X12_ID_PULLUP0		(0x01 << 3)
+#define EXYNOS4X12_COMMON_ON_N0	(0x01 << 4)
+#define EXYNOS4X12_CLK_SEL_12MHZ	(0x02 << 0)
+#define EXYNOS4X12_CLK_SEL_24MHZ	(0x05 << 0)
+
 /* Device Configuration Register DCFG */
 #define DEV_SPEED_HIGH_SPEED_20         (0x0 << 0)
 #define DEV_SPEED_FULL_SPEED_20         (0x1 << 0)
diff --git a/drivers/usb/gadget/s3c_udc_otg.c b/drivers/usb/gadget/s3c_udc_otg.c
index 7e20209..ba17a04 100644
--- a/drivers/usb/gadget/s3c_udc_otg.c
+++ b/drivers/usb/gadget/s3c_udc_otg.c
@@ -167,8 +167,13 @@
 		writel((readl(&phy->phypwr) &~(OTG_DISABLE_0 | ANALOG_PWRDOWN)
 			&~FORCE_SUSPEND_0), &phy->phypwr);
 
-	writel((readl(&phy->phyclk) &~(ID_PULLUP0 | COMMON_ON_N0)) |
-	       CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
+	if (s5p_cpu_id == 0x4412)
+		writel((readl(&phy->phyclk) & ~(EXYNOS4X12_ID_PULLUP0 |
+			EXYNOS4X12_COMMON_ON_N0)) | EXYNOS4X12_CLK_SEL_24MHZ,
+		       &phy->phyclk); /* PLL 24Mhz */
+	else
+		writel((readl(&phy->phyclk) & ~(ID_PULLUP0 | COMMON_ON_N0)) |
+		       CLK_SEL_24MHZ, &phy->phyclk); /* PLL 24Mhz */
 
 	writel((readl(&phy->rstcon) &~(LINK_SW_RST | PHYLNK_SW_RST))
 	       | PHY_SW_RST0, &phy->rstcon);
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index c4ce487..1b215c2 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -28,21 +28,48 @@
 
 static int omap_uhh_reset(void)
 {
-/*
- * Soft resetting the UHH module causes instability issues on
- * all OMAPs so we just avoid it.
- *
- * See OMAP36xx Errata
- *  i571: USB host EHCI may stall when entering smart-standby mode
- *  i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
- *
- * On OMAP4/5, soft-resetting the UHH module will put it into
- * Smart-Idle mode and lead to a deadlock.
- *
- * On OMAP3, this doesn't seem to be the case but still instabilities
- * are observed on beagle (3530 ES1.0) if soft-reset is used.
- * e.g. NFS root failures with Linux kernel.
- */
+	int timeout = 0;
+	u32 rev;
+
+	rev = readl(&uhh->rev);
+
+	/* Soft RESET */
+	writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
+
+	switch (rev) {
+	case OMAP_USBHS_REV1:
+		/* Wait for soft RESET to complete */
+		while (!(readl(&uhh->syss) & 0x1)) {
+			if (timeout > 100) {
+				printf("%s: RESET timeout\n", __func__);
+				return -1;
+			}
+			udelay(10);
+			timeout++;
+		}
+
+		/* Set No-Idle, No-Standby */
+		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
+		break;
+
+	default:	/* Rev. 2 onwards */
+
+		udelay(2); /* Need to wait before accessing SYSCONFIG back */
+
+		/* Wait for soft RESET to complete */
+		while ((readl(&uhh->sysc) & 0x1)) {
+			if (timeout > 100) {
+				printf("%s: RESET timeout\n", __func__);
+				return -1;
+			}
+			udelay(10);
+			timeout++;
+		}
+
+		writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
+		break;
+	}
+
 	return 0;
 }
 
diff --git a/drivers/video/bus_vcxk.c b/drivers/video/bus_vcxk.c
index 0138bca..60a5cc5 100644
--- a/drivers/video/bus_vcxk.c
+++ b/drivers/video/bus_vcxk.c
@@ -20,7 +20,6 @@
 	#ifndef VCBITMASK
 		#define VCBITMASK(bitno)	(0x0001 << (bitno % 16))
 	#endif
-#ifndef CONFIG_AT91_LEGACY
 at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
 #define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
 	do { \
@@ -37,20 +36,6 @@
 #define VCXK_ACKNOWLEDGE	\
 	(!(readl(&pio->CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT.pdsr) & \
 			CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
-#else
-	#define VCXK_INIT_PIN(PORT, PIN, DDR, I0O1) \
-		((AT91PS_PIO) PORT)->PIO_PER = PIN; \
-		((AT91PS_PIO) PORT)->DDR = PIN; \
-		((AT91PS_PIO) PORT)->PIO_MDDR = PIN; \
-		if (!I0O1) ((AT91PS_PIO) PORT)->PIO_PPUER = PIN;
-
-	#define VCXK_SET_PIN(PORT, PIN)	((AT91PS_PIO) PORT)->PIO_SODR  = PIN;
-	#define VCXK_CLR_PIN(PORT, PIN)	((AT91PS_PIO) PORT)->PIO_CODR  = PIN;
-
-	#define VCXK_ACKNOWLEDGE	\
-		(!(((AT91PS_PIO) CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT)->\
-			PIO_PDSR & CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN))
-#endif
 #elif defined(CONFIG_MCF52x2)
 	#include <asm/m5282.h>
 	#ifndef VCBITMASK
diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h
index 5e71898..14bac15 100644
--- a/include/configs/afeb9260.h
+++ b/include/configs/afeb9260.h
@@ -106,7 +106,7 @@
 /* Ethernet */
 #define CONFIG_MACB
 #define CONFIG_RESET_PHY_R
-
+#define CONFIG_AT91_WANTS_COMMON_PHY
 #define CONFIG_NET_RETRY_COUNT		20
 
 /* USB */
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index d75df92..8af4d6a 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -42,12 +42,11 @@
 	"dfu_alt_info_nand=" DFU_ALT_INFO_NAND "\0" \
 	"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
 	"nandrootfstype=ubifs rootwait=1\0" \
-	"nandsrcaddr=0x280000\0" \
-		"nandboot=echo Booting from nand ...; " \
+	"nandboot=echo Booting from nand ...; " \
 		"run nandargs; " \
-		"nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; " \
-		"bootz ${loadaddr}\0" \
-	"nandimgsize=0x500000\0"
+		"nand read ${fdtaddr} u-boot-spl-os; " \
+		"nand read ${loadaddr} kernel; " \
+		"bootz ${loadaddr} - ${fdtaddr}\0"
 #else
 #define NANDARGS ""
 #endif
@@ -198,6 +197,10 @@
 #define CONFIG_SPL_POWER_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 
+/* Bootcount using the RTC block */
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_AM33XX
+
 /* CPSW support */
 #define CONFIG_SPL_ETH_SUPPORT
 
diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h
index a3473b5..1fa477a 100644
--- a/include/configs/am3517_evm.h
+++ b/include/configs/am3517_evm.h
@@ -141,8 +141,18 @@
 #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
 #define CONFIG_SYS_I2C_OMAP34XX
 
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
+/*
+ * Ethernet
+ */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT		10
+
 /*
  * Board NAND Info.
  */
diff --git a/include/configs/arndale.h b/include/configs/arndale.h
index ea8753b..a3cb56b 100644
--- a/include/configs/arndale.h
+++ b/include/configs/arndale.h
@@ -198,10 +198,6 @@
 #define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
 #define BL2_SIZE_BLOC_COUNT	(CONFIG_BL2_SIZE/512)
 
-#define CONFIG_SPI_BOOTING
-#define EXYNOS_COPY_SPI_FNPTR_ADDR	0x02020058
-#define SPI_FLASH_UBOOT_POS		(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
-
 #define CONFIG_DOS_PARTITION
 #define CONFIG_EFI_PARTITION
 #define CONFIG_CMD_PART
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index 1c4bb81..73917b0 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -181,6 +181,7 @@
 #define CONFIG_RMII			1
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R		1
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index 0a1969d..b9aa036 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -275,6 +275,7 @@
 #define CONFIG_RMII			1
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R		1
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index 2095fe6..ccfda71 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -15,7 +15,6 @@
 
 #define CONFIG_SYS_TEXT_BASE		0x73f00000
 
-#define CONFIG_AT91_LEGACY
 #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
 
 /* ARM asynchronous clock */
@@ -77,6 +76,10 @@
 /*
  * Command line configuration.
  */
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_FPGA
@@ -97,9 +100,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
 
-/* No NOR flash */
-#define CONFIG_SYS_NO_FLASH
-
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_NAND_ATMEL
@@ -120,6 +120,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_EHCI
diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h
index 4ec1799..e23549d 100644
--- a/include/configs/at91sam9n12ek.h
+++ b/include/configs/at91sam9n12ek.h
@@ -113,8 +113,8 @@
 #define CONFIG_SYS_NAND_BASE		0x40000000
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 4
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTD, 5
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(4)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(5)
 
 /* PMECC & PMERRLOC */
 #define CONFIG_ATMEL_NAND_HWECC
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
new file mode 100644
index 0000000..56e9a8e
--- /dev/null
+++ b/include/configs/cm_t335.h
@@ -0,0 +1,182 @@
+/*
+ * Config file for Compulab CM-T335 board
+ *
+ * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
+ *
+ * Author: Ilya Ledvich <ilya@compulab.co.il>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_CM_T335_H
+#define __CONFIG_CM_T335_H
+
+#define CONFIG_CM_T335
+#define CONFIG_NAND
+
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_BOARD_LATE_INIT
+#undef CONFIG_SPI
+#undef CONFIG_OMAP3_SPI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_SPL_OS_BOOT
+#undef CONFIG_BOOTCOUNT_LIMIT
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#undef CONFIG_MAX_RAM_BANK_SIZE
+#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 512MB */
+
+#undef CONFIG_SYS_PROMPT
+#define CONFIG_SYS_PROMPT		"CM-T335 # "
+
+#define CONFIG_OMAP_COMMON
+
+#define MACH_TYPE_CM_T335		4586	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_CM_T335
+
+/* Clock Defines */
+#define V_OSCK				25000000  /* Clock output from T2 */
+#define V_SCLK				(V_OSCK)
+
+#define CONFIG_ENV_SIZE			(16 << 10)	/* 16 KiB */
+
+#ifndef CONFIG_SPL_BUILD
+#define MMCARGS \
+	"mmcdev=0\0" \
+	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
+	"mmcrootfstype=ext4\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=${mmcroot} " \
+		"rootfstype=${mmcrootfstype}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0"
+
+#define NANDARGS \
+	"mtdids=" MTDIDS_DEFAULT "\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"nandroot=ubi0:rootfs rw\0" \
+	"nandrootfstype=ubifs\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=${nandroot} " \
+		"rootfstype=${nandrootfstype} " \
+		"ubi.mtd=${rootfs_name}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nboot ${loadaddr} nand0 900000; " \
+		"bootm ${loadaddr}\0"
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=82000000\0" \
+	"console=ttyO0,115200n8\0" \
+	"rootfs_name=rootfs\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
+	MMCARGS \
+	NANDARGS
+
+#define CONFIG_BOOTCOMMAND \
+	"mmc dev ${mmcdev}; if mmc rescan; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_TIMESTAMP
+#define CONFIG_SYS_AUTOLOAD		"no"
+
+/* Serial console configuration */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SERIAL1			1	/* UART0 */
+
+/* NS16550 Configuration */
+#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
+#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
+#define CONFIG_BAUDRATE			115200
+
+/* I2C Configuration */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+
+/* SPL */
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ADDR			0
+#define CONFIG_PHY_ATHEROS
+
+/* NAND support */
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
+					 10, 11, 12, 13, 14, 15, 16, 17, \
+					 18, 19, 20, 21, 22, 23, 24, 25, \
+					 26, 27, 28, 29, 30, 31, 32, 33, \
+					 34, 35, 36, 37, 38, 39, 40, 41, \
+					 42, 43, 44, 45, 46, 47, 48, 49, \
+					 50, 51, 52, 53, 54, 55, 56, 57, }
+
+#define CONFIG_SYS_NAND_ECCSIZE		512
+#define CONFIG_SYS_NAND_ECCBYTES	14
+
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+
+#undef CONFIG_SYS_NAND_U_BOOT_OFFS
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x200000
+
+#define CONFIG_CMD_NAND
+#define GPMC_NAND_ECC_LP_x8_LAYOUT
+#define MTDIDS_DEFAULT			"nand0=nand"
+#define MTDPARTS_DEFAULT		"mtdparts=nand:2m(spl)," \
+					"1m(u-boot),1m(u-boot-env)," \
+					"1m(dtb),4m(splash)," \
+					"6m(kernel),-(rootfs)"
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x300000 /* environment starts here */
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* GPIO pin + bank to pin ID mapping */
+#define GPIO_PIN(_bank, _pin)		((_bank << 5) + _pin)
+
+/* Status LED */
+#define CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
+#define CONFIG_BOARD_SPECIFIC_LED
+#define STATUS_LED_BIT			GPIO_PIN(2, 0)
+/* Status LED polarity is inversed, so init it in the "off" state */
+#define STATUS_LED_STATE		STATUS_LED_OFF
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+#define STATUS_LED_BOOT			0
+
+#ifndef CONFIG_SPL_BUILD
+/*
+ * Enable PCA9555 at I2C0-0x26.
+ * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
+ */
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#define CONFIG_SYS_I2C_PCA953X_ADDR	0x26
+#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x26, 16} }
+#endif /* CONFIG_SPL_BUILD */
+
+#endif	/* __CONFIG_CM_T335_H */
+
diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h
index f4ecd0d..e72187e 100644
--- a/include/configs/cm_t35.h
+++ b/include/configs/cm_t35.h
@@ -302,12 +302,13 @@
 /* Status LED */
 #define CONFIG_STATUS_LED		/* Status LED enabled */
 #define CONFIG_BOARD_SPECIFIC_LED
-#define STATUS_LED_GREEN		0
-#define STATUS_LED_BIT			STATUS_LED_GREEN
+#define CONFIG_GPIO_LED
+#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
+#define GREEN_LED_DEV			0
+#define STATUS_LED_BIT			GREEN_LED_GPIO
 #define STATUS_LED_STATE		STATUS_LED_ON
 #define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
-#define STATUS_LED_BOOT			STATUS_LED_BIT
-#define GREEN_LED_GPIO			186 /* CM-T35 Green LED is GPIO186 */
+#define STATUS_LED_BOOT			GREEN_LED_DEV
 
 #define CONFIG_SPLASHIMAGE_GUARD
 
diff --git a/include/configs/corvus.h b/include/configs/corvus.h
new file mode 100644
index 0000000..11ba4cf
--- /dev/null
+++ b/include/configs/corvus.h
@@ -0,0 +1,165 @@
+/*
+ * Common board functions for siemens AT91SAM9G45 based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9m10g45ek.h
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/hardware.h>
+
+#define MACH_TYPE_CORVUS               2066
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+#define CONFIG_SYS_TEXT_BASE  0x73f00000
+
+#define CONFIG_AT91_LEGACY
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_HZ		        1000
+
+#define CONFIG_AT91FAMILY
+
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+
+/* LED */
+#define CONFIG_AT91_LED
+#define CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
+#define CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
+#define CONFIG_SYS_SDRAM_SIZE		0x08000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+
+/* No NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT		20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_ATMEL
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS	2
+#define CONFIG_DOS_PARTITION
+#define CONFIG_USB_STORAGE
+
+#define CONFIG_SYS_LOAD_ADDR		0x72000000	/* load address */
+
+/* bootstrap + u-boot + env in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+#define CONFIG_ENV_SIZE			0x20000
+
+#define CONFIG_BOOTCOMMAND						\
+	"nand read 0x70000000 0x200000 0x300000;"			\
+	"bootm 0x70000000"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE +	\
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + \
+				128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h
index ccf36a5..39f7062 100644
--- a/include/configs/cpu9260.h
+++ b/include/configs/cpu9260.h
@@ -280,8 +280,8 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE		1
 #define CONFIG_SYS_NAND_BASE			0x40000000
 #define CONFIG_SYS_NAND_DBW_8			1
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTC, 13
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PC(13)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
 
@@ -310,6 +310,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT			20
 #define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* LEDS */
 /* Status LED */
diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h
index 8a69c7d..48b47cb 100644
--- a/include/configs/dra7xx_evm.h
+++ b/include/configs/dra7xx_evm.h
@@ -83,4 +83,15 @@
 #define CONFIG_OMAP_USB_PHY
 #define CONFIG_OMAP_USB2PHY2_HOST
 
+/* SATA */
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 #endif /* __CONFIG_DRA7XX_EVM_H */
diff --git a/include/configs/dxr2.h b/include/configs/dxr2.h
index cd553ec..1e42f5c 100644
--- a/include/configs/dxr2.h
+++ b/include/configs/dxr2.h
@@ -21,8 +21,8 @@
 
 #define CONFIG_SYS_MPUCLK	275
 #define DXR2_IOCTRL_VAL	0x18b
-#define DDR_PLL_FREQ	266
-#define CONFIG_SPL_AM33XX_DO_NOT_ENABLE_RTC32K
+#define DDR_PLL_FREQ	303
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #define BOARD_DFU_BUTTON_GPIO	27
 #define BOARD_DFU_BUTTON_LED	64
@@ -62,7 +62,7 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=dxr2\0" \
-	"nand_img_size=0x300000\0" \
+	"nand_img_size=0x400000\0" \
 	"optargs=\0" \
 	CONFIG_COMMON_ENV_SETTINGS
 
@@ -75,10 +75,9 @@
 	"run dfu_start; " \
 	"reset; " \
 "fi;" \
-"if ping ${serverip}; then " \
-	"run net_nfs; " \
-"fi;" \
-"run nand_boot;"
+"run nand_boot;" \
+"reset;"
+
 
 #else
 #define CONFIG_BOOTDELAY		0
diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index 2d8c42c..f7e70aa 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -41,10 +41,6 @@
 #define CONFIG_SYS_LOAD_ADDR		0x21000000  /* default load address */
 #define CONFIG_STANDALONE_LOAD_ADDR	0x21000000
 
-#define CONFIG_SYS_BOOT_SIZE		0x00 /* 0 KBytes */
-#define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
-#define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
-
 #define CONFIG_BOOT_RETRY_TIME		30
 #define CONFIG_CMDLINE_EDITING
 
diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h
index 252df54..480d867 100644
--- a/include/configs/ethernut5.h
+++ b/include/configs/ethernut5.h
@@ -149,7 +149,7 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTC, 14
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
 #endif
 
 /* JFFS2 */
diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-dt.h
index 1e9c1e3..8fb904c 100644
--- a/include/configs/exynos5250-dt.h
+++ b/include/configs/exynos5250-dt.h
@@ -157,6 +157,7 @@
 #define COPY_BL2_FNPTR_ADDR	0x02020030
 
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
 
 /* specific .lds file */
 #define CONFIG_SPL_LDSCRIPT	"board/samsung/common/exynos-uboot-spl.lds"
@@ -266,6 +267,7 @@
 /* SPI */
 #define CONFIG_ENV_IS_IN_SPI_FLASH
 #define CONFIG_SPI_FLASH
+#define CONFIG_ENV_SPI_BASE	0x12D30000
 
 #ifdef CONFIG_SPI_FLASH
 #define CONFIG_EXYNOS_SPI
@@ -291,27 +293,6 @@
 #define CONFIG_POWER_I2C
 #define CONFIG_POWER_MAX77686
 
-/* SPI */
-#define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_SPI_FLASH
-
-#ifdef CONFIG_SPI_FLASH
-#define CONFIG_EXYNOS_SPI
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
-#define CONFIG_SF_DEFAULT_SPEED		50000000
-#define EXYNOS5_SPI_NUM_CONTROLLERS	5
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
-#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
-#define CONFIG_ENV_SPI_BUS	1
-#define CONFIG_ENV_SPI_MAX_HZ	50000000
-#endif
-
 /* Ethernet Controllor Driver */
 #ifdef CONFIG_CMD_NET
 #define CONFIG_SMC911X
diff --git a/include/configs/h2_p2_dbg_board.h b/include/configs/h2_p2_dbg_board.h
deleted file mode 100644
index 4ba2c55..0000000
--- a/include/configs/h2_p2_dbg_board.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   TI H2 and P2 Debug Board hardware map
- *
- * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
- * Author: MPC-Data Limited
- *	   Dave Peverley
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __INCLUDED_H2_P2_DBH_BOARD_H
-#define __INCLUDED_H2_P2_DBH_BOARD_H
-
-#include <asm/sizes.h>
-
-/*
- * The Debug board is designed to function with the P2 Sample, H2
- * Sample and 1610 Innovator boards. The main difference AFAICT is
- * the chip selects used with each system ;
- *
- *   P2 Sample : CS1 of OMAP730 is used to select the CPLD & LAN regs
- *   H2 Sample : CS1a is used to select the CPLD registers.
- *
- */
-
-/***************************************************************************
- * CPLD Registers
- **************************************************************************/
-
-#define H2DBG_CPLD_REVISION        0x04000010
-#define H2DBG_BOARD_REVISION       0x04000012
-#define H2DBG_GPIO_REGISTER        0x04000014
-#define H2DBG_LED_CONTROL          0x04000016
-#define H2DBG_MISC_INPUT           0x04000018
-#define H2DBG_LAN_STATUS           0x0400001A
-#define H2DBG_LAN_RESET            0x0400001C
-#define H2DBG_ETH_REG_BASE         0x04000300
-
-/***************************************************************************
- * Ethernet Control Registers
- * These are for the LAN91C96 on the debug board
- **************************************************************************/
-
-/* Bank 0 in IO space */
-
-#define ETH_TCR            (H2DBG_ETH_REG_BASE + 0x00)   /* Transmit Control Register */
-#define ETH_EPH_STATUS     (H2DBG_ETH_REG_BASE + 0x02)   /* EPH Status Register */
-#define ETH_RCR            (H2DBG_ETH_REG_BASE + 0x04)   /* Receive Control Register */
-#define ETH_COUNTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Counter Register */
-#define ETH_MIR            (H2DBG_ETH_REG_BASE + 0x08)   /* Memory Information Register */
-#define ETH_MCR            (H2DBG_ETH_REG_BASE + 0x0A)   /* Memory Configuration Register */
-
-/* Bank 1 in IO space */
-
-#define ETH_CONFIG         (H2DBG_ETH_REG_BASE + 0x00)   /* Configuration Register */
-#define ETH_BASE           (H2DBG_ETH_REG_BASE + 0x02)   /* Base Address Register */
-#define ETH_IA0            (H2DBG_ETH_REG_BASE + 0x04)   /* Individual Address Register - 0 */
-#define ETH_IA1            (H2DBG_ETH_REG_BASE + 0x05)   /* Individual Address Register - 1 */
-#define ETH_IA2            (H2DBG_ETH_REG_BASE + 0x06)   /* Individual Address Register - 2 */
-#define ETH_IA3            (H2DBG_ETH_REG_BASE + 0x07)   /* Individual Address Register - 3 */
-#define ETH_IA4            (H2DBG_ETH_REG_BASE + 0x08)   /* Individual Address Register - 4 */
-#define ETH_IA5            (H2DBG_ETH_REG_BASE + 0x09)   /* Individual Address Register - 5 */
-#define ETH_GEN_PURPOSE    (H2DBG_ETH_REG_BASE + 0x0A)   /* General Address Registers */
-#define ETH_CONTROL        (H2DBG_ETH_REG_BASE + 0x0B)   /* Control Register */
-
-/* Bank 2 in IO space */
-
-#define ETH_MMU            (H2DBG_ETH_REG_BASE + 0x00)   /* MMU Command Register */
-#define ETH_AUTO_TX_START  (H2DBG_ETH_REG_BASE + 0x01)   /* Auto Tx Start Register */
-#define ETH_PNR            (H2DBG_ETH_REG_BASE + 0x02)   /* Packet Number Register */
-#define ETH_ARR            (H2DBG_ETH_REG_BASE + 0x03)   /* Allocation Result Register */
-#define ETH_FIFO           (H2DBG_ETH_REG_BASE + 0x04)   /* FIFO Ports Register */
-#define ETH_POINTER        (H2DBG_ETH_REG_BASE + 0x06)   /* Pointer Register */
-#define ETH_DATA_HIGH      (H2DBG_ETH_REG_BASE + 0x08)   /* Data High Register */
-#define ETH_DATA_LOW       (H2DBG_ETH_REG_BASE + 0x0A)   /* Data Low Register */
-#define ETH_INT_STATS      (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Status Register - RO */
-#define ETH_INT_ACK        (H2DBG_ETH_REG_BASE + 0x0C)   /* Interrupt Acknowledge Register -WO */
-#define ETH_INT_MASK       (H2DBG_ETH_REG_BASE + 0x0D)   /* Interrupt Mask Register */
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * A couple of utility inlines to aid debugging using the LED's on the
- * debug board.
- */
-
-static inline void set_led_state(int state)
-{
-	static unsigned long hw_led_state = 0;
-	volatile unsigned short *led_address = (volatile unsigned short *)0x04000016;
-
-	hw_led_state = ((unsigned long)state);
-	*((unsigned short *) (led_address)) = (unsigned short) (~hw_led_state & 0xFFFF);
-}
-
-
-static inline void spin_up_leds(void)
-{
-	volatile int i, j, k;
-
-	for (k = 0; k < 2; k++) {
-		for (i = 0; i < 16; i++) {
-			for (j = 0; j < 5000; j++) {
-				set_led_state(1 << i);
-			}
-		}
-		for (i = 15; i >= 0; i--) {
-			for (j = 0; j < 5000; j++) {
-				set_led_state(1 << i);
-			}
-		}
-	}
-}
-
-#endif    /* !  __ASSEMBLY__ */
-
-#endif    /* !  __INCLUDED_H2_P2_DBH_BOARD_H */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
new file mode 100644
index 0000000..59c4948
--- /dev/null
+++ b/include/configs/koelsch.h
@@ -0,0 +1,133 @@
+/*
+ * include/configs/koelsch.h
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __KOELSCH_H
+#define __KOELSCH_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7791
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Koelsch"
+#define CONFIG_SH_GPIO_PFC
+
+#include <asm/arch/rmobile.h>
+
+#define	CONFIG_CMD_EDITENV
+#define	CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_BOOTZ
+#define	CONFIG_CMD_FLASH
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_INITRD_TAG
+#define	CONFIG_CMDLINE_EDITING
+
+#define CONFIG_OF_LIBFDT
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE633fffc
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define KOELSCH_SDRAM_BASE	0x40000000
+#define KOELSCH_SDRAM_SIZE	(2048u * 1024 * 1024)
+#define KOELSCH_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define SCIF0_BASE		0xe6e60000
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(KOELSCH_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(KOELSCH_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(KOELSCH_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define	CONFIG_FLASH_CFI_DRIVER
+#define	CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define	CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define	CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define	CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+
+/* Board Clock */
+#define	CONFIG_SYS_CLK_FREQ	10000000
+#define CONFIG_SH_TMU_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+#define CONFIG_SH_SCIF_CLK_FREQ	14745600
+#define CONFIG_SYS_TMU_CLK_DIV	4
+#define CONFIG_SYS_HZ		1000
+
+#endif	/* __KOELSCH_H */
diff --git a/include/configs/lager.h b/include/configs/lager.h
new file mode 100644
index 0000000..7819edd
--- /dev/null
+++ b/include/configs/lager.h
@@ -0,0 +1,141 @@
+/*
+ * include/configs/lager.h
+ *     This file is lager board configuration.
+ *
+ * Copyright (C) 2013 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __LAGER_H
+#define __LAGER_H
+
+#undef DEBUG
+#define CONFIG_ARMV7
+#define CONFIG_R8A7790
+#define CONFIG_RMOBILE
+#define CONFIG_RMOBILE_BOARD_STRING "Lager"
+#define CONFIG_SH_GPIO_PFC
+#define MACH_TYPE_LAGER		4538
+#define CONFIG_MACH_TYPE	MACH_TYPE_LAGER
+
+#include <asm/arch/rmobile.h>
+
+#define	CONFIG_CMD_EDITENV
+#define	CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_BOOTZ
+#define	CONFIG_CMD_FLASH
+
+#define	CONFIG_CMDLINE_TAG
+#define	CONFIG_SETUP_MEMORY_TAGS
+#define	CONFIG_INITRD_TAG
+#define	CONFIG_CMDLINE_EDITING
+#define	CONFIG_OF_LIBFDT
+
+/* #define CONFIG_OF_LIBFDT */
+#define BOARD_LATE_INIT
+
+#define CONFIG_BAUDRATE		38400
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTARGS		""
+
+#define CONFIG_VERSION_VARIABLE
+#undef	CONFIG_SHOW_BOOT_PROGRESS
+
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_USE_ARCH_MEMSET
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_TMU_TIMER
+
+/* STACK */
+#define CONFIG_SYS_INIT_SP_ADDR		0xE827fffc
+#define STACK_AREA_SIZE				0xC000
+#define LOW_LEVEL_MERAM_STACK	\
+		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
+
+/* MEMORY */
+#define LAGER_SDRAM_BASE	0x40000000
+#define LAGER_SDRAM_SIZE	(2048u * 1024 * 1024)
+#define LAGER_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		512
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE
+#define CONFIG_CONS_SCIF0
+#define SCIF0_BASE		0xe6e60000
+#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START	(LAGER_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
+					 504 * 1024 * 1024)
+#undef	CONFIG_SYS_ALT_MEMTEST
+#undef	CONFIG_SYS_MEMTEST_SCRATCH
+#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE		(LAGER_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE		(LAGER_UBOOT_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
+#define CONFIG_SYS_GBL_DATA_SIZE	(256)
+#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
+
+/* USE NOR FLASH */
+#define CONFIG_SYS_TEXT_BASE	0x00000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#define	CONFIG_FLASH_CFI_DRIVER
+#define	CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define	CONFIG_FLASH_SHOW_PROGRESS	45
+#define CONFIG_SYS_FLASH_BASE		0x00000000
+#define	CONFIG_SYS_FLASH_SIZE		0x04000000	/* 64 MB */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
+#define	CONFIG_SYS_FLASH_BANKS_SIZES	{ (CONFIG_SYS_FLASH_SIZE) }
+#define CONFIG_SYS_FLASH_ERASE_TOUT	3000
+#define CONFIG_SYS_FLASH_WRITE_TOUT	3000
+#define CONFIG_SYS_FLASH_LOCK_TOUT	3000
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT	3000
+
+/* ENV setting */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OVERWRITE	1
+#define CONFIG_ENV_SECT_SIZE	(256 * 1024)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_SYS_MONITOR_LEN)
+
+/* Board Clock */
+#define CONFIG_BASE_CLK_FREQ	20000000u
+#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
+#define CONFIG_PLL1_CLK_FREQ	(CONFIG_BASE_CLK_FREQ * 156 / 2)
+#define CONFIG_PLL1_DIV2_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 2)
+#define CONFIG_MP_CLK_FREQ	(CONFIG_PLL1_DIV2_CLK_FREQ / 15)
+#define CONFIG_SH_SCIF_CLK_FREQ	CONFIG_MP_CLK_FREQ
+
+#define CONFIG_SYS_TMU_CLK_DIV	4
+#define CONFIG_SYS_HZ		1000
+
+#endif	/* __LAGER_H */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h
index 91f6e2f..86ce5f2 100644
--- a/include/configs/meesc.h
+++ b/include/configs/meesc.h
@@ -143,8 +143,8 @@
 # define CONFIG_SYS_NAND_DBW_8
 # define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 # define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
-# define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
+# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* Ethernet */
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 9eab190..3acb854 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -118,9 +118,6 @@
 #define CONFIG_USB_EHCI_OMAP
 #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	147
 
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-
 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_SMSC95XX
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 6820e42..73dc088 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -36,9 +36,6 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
 
-#define CONFIG_USB_ULPI
-#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-
 #include <configs/omap4_common.h>
 #define CONFIG_CMD_NET
 
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 4d3a800..2f128b8 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -69,4 +69,14 @@
 /* Max time to hold reset on this board, see doc/README.omap-reset-time */
 #define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC	16296
 
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_CMD_SCSI
+#define CONFIG_LIBATA
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
+#define CONFIG_SYS_SCSI_MAX_LUN		1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+
 #endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/omap730.h b/include/configs/omap730.h
deleted file mode 100644
index b54e0fb..0000000
--- a/include/configs/omap730.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   OMAP730 hardware map
- *
- * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
- * Author: MPC-Data Limited
- *	   Dave Peverley
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __INCLUDED_OMAP730_H
-#define __INCLUDED_OMAP730_H
-
-#include <asm/sizes.h>
-
-/***************************************************************************
- * OMAP730 Configuration Registers
- **************************************************************************/
-
-#define PERSEUS2_MPU_DEV_ID               ((unsigned int)(0xFFFE1000))
-#define PERSEUS2_GSM_DEV_ID0              ((unsigned int)(0xFFFE1000))
-#define PERSEUS2_GDM_DEV_ID1              ((unsigned int)(0xFFFE1002))
-#define DSP_CONF                          ((unsigned int)(0xFFFE1004))
-#define PERSEUS2_MPU_DIE_ID0              ((unsigned int)(0xFFFE1008))
-#define GSM_ASIC_CONF                     ((unsigned int)(0xFFFE1008))
-#define PERSEUS2_MPU_DIE_ID1              ((unsigned int)(0xFFFE100C))
-#define PERSEUS2_MODE1                    ((unsigned int)(0xFFFE1010))
-#define PERSEUS2_GSM_DIE_ID0              ((unsigned int)(0xFFFE1010))
-#define PERSEUS2_GSM_DIE_ID1              ((unsigned int)(0xFFFE1012))
-#define PERSEUS2_MODE2                    ((unsigned int)(0xFFFE1014))
-#define PERSEUS2_GSM_DIE_ID2              ((unsigned int)(0xFFFE1014))
-#define PERSEUS2_GSM_DIE_ID3              ((unsigned int)(0xFFFE1016))
-#define PERSEUS2_ANALOG_CELLS_CONF        ((unsigned int)(0xFFFE1018))
-#define SPECCTL                           ((unsigned int)(0xFFFE101C))
-#define SPARE1                            ((unsigned int)(0xFFFE1020))
-#define SPARE2                            ((unsigned int)(0xFFFE1024))
-#define GSM_PBG_IRQ                       ((unsigned int)(0xFFFE1028))
-#define DMA_REQ_CONF                      ((unsigned int)(0xFFFE1030))
-#define PE_CONF_NO_DUAL                   ((unsigned int)(0xFFFE1060))
-#define PERSEUS2_IO_CONF0                 ((unsigned int)(0xFFFE1070))
-#define PERSEUS2_IO_CONF1                 ((unsigned int)(0xFFFE1074))
-#define PERSEUS2_IO_CONF2                 ((unsigned int)(0xFFFE1078))
-#define PERSEUS2_IO_CONF3                 ((unsigned int)(0xFFFE107C))
-#define PERSEUS2_IO_CONF4                 ((unsigned int)(0xFFFE1080))
-#define PERSEUS2_IO_CONF5                 ((unsigned int)(0xFFFE1084))
-#define PERSEUS2_IO_CONF6                 ((unsigned int)(0xFFFE1088))
-#define PERSEUS2_IO_CONF7                 ((unsigned int)(0xFFFE108C))
-#define PERSEUS2_IO_CONF8                 ((unsigned int)(0xFFFE1090))
-#define PERSEUS2_IO_CONF9                 ((unsigned int)(0xFFFE1094))
-#define PERSEUS2_IO_CONF10                ((unsigned int)(0xFFFE1098))
-#define PERSEUS2_IO_CONF11                ((unsigned int)(0xFFFE109C))
-#define PERSEUS2_IO_CONF12                ((unsigned int)(0xFFFE10A0))
-#define PERSEUS2_IO_CONF13                ((unsigned int)(0xFFFE10A4))
-#define PERSEUS_PCC_CONF_REG              ((unsigned int)(0xFFFE10B4))
-#define BIST_STATUS_INTERNAL              ((unsigned int)(0xFFFE10B8))
-#define BIST_CONTROL                      ((unsigned int)(0xFFFE10C0))
-#define BOOT_ROM_REG                      ((unsigned int)(0xFFFE10C4))
-#define PRODUCTION_ID_REG                 ((unsigned int)(0xFFFE10C8))
-#define BIST_SECROM_SIGNATURE1_INTERNAL   ((unsigned int)(0xFFFE10D0))
-#define BIST_SECROM_SIGNATURE2_INTERNAL   ((unsigned int)(0xFFFE10D4))
-#define BIST_CONTROL_2                    ((unsigned int)(0xFFFE10D8))
-#define DEBUG1                            ((unsigned int)(0xFFFE10E0))
-#define DEBUG2                            ((unsigned int)(0xFFFE10E4))
-#define DEBUG_DMA_IRQ                     ((unsigned int)(0xFFFE10E8))
-
-/***************************************************************************
- * OMAP730 EMIFS Registers                                       (TRM 2.5.7)
- **************************************************************************/
-
-#define TCMIF_BASE                 0xFFFECC00
-
-#define EMIFS_LRUREG               (TCMIF_BASE + 0x04)
-#define EMIFS_CONFIG               (TCMIF_BASE + 0x0C)
-#define FLASH_CFG_0                (TCMIF_BASE + 0x10)
-#define FLASH_CFG_1                (TCMIF_BASE + 0x14)
-#define FLASH_CFG_2                (TCMIF_BASE + 0x18)
-#define FLASH_CFG_3                (TCMIF_BASE + 0x1C)
-#define FL_CFG_DYN_WAIT            (TCMIF_BASE + 0x40)
-#define EMIFS_TIMEOUT1_REG         (TCMIF_BASE + 0x28)
-#define EMIFS_TIMEOUT2_REG         (TCMIF_BASE + 0x2C)
-#define EMIFS_TIMEOUT3_REG         (TCMIF_BASE + 0x30)
-#define EMIFS_ABORT_ADDR           (TCMIF_BASE + 0x44)
-#define EMIFS_ABORT_TYPE           (TCMIF_BASE + 0x48)
-#define EMIFS_ABORT_TOUT           (TCMIF_BASE + 0x4C)
-#define FLASH_ACFG_0_1             (TCMIF_BASE + 0x50)
-#define FLASH_ACFG_1_1             (TCMIF_BASE + 0x54)
-#define FLASH_ACFG_2_1             (TCMIF_BASE + 0x58)
-#define FLASH_ACFG_3_1             (TCMIF_BASE + 0x5C)
-
-/***************************************************************************
- * OMAP730 Interrupt handlers
- **************************************************************************/
-
-#define OMAP_IH1_BASE		0xFFFECB00     /* MPU Level 1 IRQ handler */
-#define OMAP_IH2_BASE           0xfffe0000
-
-/***************************************************************************
- * OMAP730 Timers
- *
- * There are three general purpose OS timers in the 730 that can be
- * configured in autoreload or one-shot modes.
- **************************************************************************/
-
-#define OMAP730_32kHz_TIMER_BASE  0xFFFB9000
-
-/* 32k Timer Registers */
-#define TIMER32k_CR               0x08
-#define TIMER32k_TVR              0x00
-#define TIMER32k_TCR              0x04
-
-/* 32k Timer Control Register definition */
-#define TIMER32k_TSS              (1<<0)
-#define TIMER32k_TRB              (1<<1)
-#define TIMER32k_INT              (1<<2)
-#define TIMER32k_ARL              (1<<3)
-
-/* MPU Timer base addresses  */
-#define OMAP730_MPUTIMER_BASE	0xfffec500
-#define OMAP730_MPUTIMER_OFF	0x00000100
-
-#define OMAP730_TIMER1_BASE	0xFFFEC500
-#define OMAP730_TIMER2_BASE	0xFFFEC600
-#define OMAP730_TIMER3_BASE	0xFFFEC700
-
-/* MPU Timer Register offsets */
-#define CNTL_TIMER	           0x00   /* MPU_CNTL_TIMER */
-#define LOAD_TIM	           0x04   /* MPU_LOAD_TIMER */
-#define READ_TIM	           0x08   /* MPU_READ_TIMER */
-
-/* MPU_CNTL_TIMER register bits */
-#define MPUTIM_FREE               (1<<6)
-#define MPUTIM_CLOCK_ENABLE       (1<<5)
-#define MPUTIM_PTV_MASK           (0x7<<MPUTIM_PTV_BIT)
-#define MPUTIM_PTV_BIT            2
-#define MPUTIM_AR                 (1<<1)
-#define MPUTIM_ST                 (1<<0)
-
-/***************************************************************************
- * OMAP730 GPIO
- *
- * The GPIO control is split over 6 register bases in the OMAP730 to allow
- * access to all the (6 x 32) GPIO pins!
- **************************************************************************/
-
-#define OMAP730_GPIO_BASE_1        0xFFFBC000
-#define OMAP730_GPIO_BASE_2        0xFFFBC800
-#define OMAP730_GPIO_BASE_3        0xFFFBD000
-#define OMAP730_GPIO_BASE_4        0xFFFBD800
-#define OMAP730_GPIO_BASE_5        0xFFFBE000
-#define OMAP730_GPIO_BASE_6        0xFFFBE800
-
-#define GPIO_DATA_INPUT            0x00
-#define GPIO_DATA_OUTPUT           0x04
-#define GPIO_DIRECTION_CONTROL     0x08
-#define GPIO_INTERRUPT_CONTROL     0x0C
-#define GPIO_INTERRUPT_MASK        0x10
-#define GPIO_INTERRUPT_STATUS      0x14
-
-#define GPIO_DATA_INPUT_1            ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_1           ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_1        ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_1      ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_2            ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_2           ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_2        ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_2      ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_3            ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_3           ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_3        ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_3      ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_4            ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_4           ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_4        ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_4      ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_5            ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_5           ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_5        ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_5      ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
-
-#define GPIO_DATA_INPUT_6            ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
-#define GPIO_DATA_OUTPUT_6           ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
-#define GPIO_DIRECTION_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
-#define GPIO_INTERRUPT_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
-#define GPIO_INTERRUPT_MASK_6        ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
-#define GPIO_INTERRUPT_STATUS_6      ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
-
-/***************************************************************************
- * OMAP730 Watchdog timers
- **************************************************************************/
-
-#define WDTIM_BASE                 0xFFFEC800
-#define WDTIM_CONTROL              (WDTIM_BASE + 0x00)    /* MPU_CNTL_TIMER */
-#define WDTIM_LOAD                 (WDTIM_BASE + 0x04)    /* MPU_LOAD_TIMER */
-#define WDTIM_READ                 (WDTIM_BASE + 0x04)    /* MPU_READ_TIMER */
-#define WDTIM_MODE                 (WDTIM_BASE + 0x08)    /* MPU_TIMER_MODE */
-
-/***************************************************************************
- * OMAP730 Interrupt Registers
- **************************************************************************/
-
-/* Interrupt Register offsets */
-
-#define IRQ_ITR                               0x00
-#define IRQ_MIR                               0x04
-#define IRQ_SIR_IRQ                           0x10
-#define IRQ_SIR_FIQ                           0x14
-#define IRQ_CONTROL_REG                       0x18
-#define IRQ_ILR0                              0x1C  /* ILRx == ILR0 + (0x4 * x) */
-#define IRQ_SIR                               0x9C  /* a.k.a.IRQ_ISR */
-#define IRQ_GMIR                              0xA0
-
-#define REG_IHL1_MIR  (OMAP_IH1_BASE + IRQ_MIR)
-#define REG_IHL2_MIR  (OMAP_IH2_BASE + IRQ_MIR)
-
-/***************************************************************************
- * OMAP730 Intersystem Communication Register                      (TRM 4.5)
- **************************************************************************/
-
-#define ICR_BASE                   0xFFFBB800
-
-#define M_ICR                      (ICR_BASE + 0x00)
-#define G_ICR                      (ICR_BASE + 0x02)
-#define M_CTL                      (ICR_BASE + 0x04)
-#define G_CTL                      (ICR_BASE + 0x06)
-#define PM_BA                      (ICR_BASE + 0x0A)
-#define DM_BA                      (ICR_BASE + 0x0C)
-#define RM_BA                      (ICR_BASE + 0x0E)
-#define SSPI_TAS                   (ICR_BASE + 0x12)
-
-#endif /* ! __INCLUDED_OMAP730_H */
diff --git a/include/configs/omap730p2.h b/include/configs/omap730p2.h
deleted file mode 100644
index 947f27b..0000000
--- a/include/configs/omap730p2.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * MPC Data Limited (http://www.mpc-data.co.uk)
- * Dave Peverley <dpeverley at mpc-data.co.uk>
- *
- * Configuation settings for the TI OMAP Perseus 2 board.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_ARM926EJS	   1	     /* This is an arm926ejs CPU core  */
-#define CONFIG_OMAP		   1	     /* in a TI OMAP core    */
-#define CONFIG_OMAP730		   1	     /* which is in a 730  */
-#define CONFIG_P2_OMAP730	   1	     /*	 a Perseus 2 Board  */
-
-/*
- * Input clock of PLL
- * The OMAP730 Perseus 2 has 13MHz input clock
- */
-
-#define CONFIG_SYS_CLK_FREQ	   13000000
-
-#define CONFIG_CMDLINE_TAG	   1	     /* enable passing of ATAGs	 */
-#define CONFIG_SETUP_MEMORY_TAGS   1
-
-/*
- * Size of malloc() pool
- */
-
-#define CONFIG_SYS_MALLOC_LEN		   (CONFIG_ENV_SIZE + 128*1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_LAN91C96
-#define CONFIG_LAN91C96_BASE	   0x04000300
-#define CONFIG_LAN91C96_EXT_PHY
-
-/*
- * NS16550 Configuration
- */
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	   (1)
-#define CONFIG_SYS_NS16550_CLK		   (48000000)	  /* can be 12M/32Khz or 48Mhz */
-#define CONFIG_SYS_NS16550_COM1	   0xfffb0000	  /* uart1, bluetooth uart
-						   * on perseus */
-
-/*
- * select serial console configuration
- */
-
-#define CONFIG_SERIAL1		   1	     /* we use SERIAL 1 on OMAP730 Perseus 2 */
-
-#define CONFIG_CONS_INDEX	   1
-#define CONFIG_BAUDRATE		   115200
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-
-
-#include <configs/omap730.h>
-#include <configs/h2_p2_dbg_board.h>
-
-#define CONFIG_BOOTDELAY	   3
-#define CONFIG_BOOTARGS		   "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
-
-#define CONFIG_LOADADDR		   0x10000000
-
-#define CONFIG_ETHADDR
-#define CONFIG_NETMASK		   255.255.255.0
-#define CONFIG_IPADDR		   192.168.0.23
-#define CONFIG_SERVERIP		   192.150.0.100
-#define CONFIG_BOOTFILE		   "uImage"  /* File to load */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	   115200    /* Speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	   1	     /* Which serial port to use */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_LONGHELP				       /* undef to save memory	   */
-#define CONFIG_SYS_PROMPT		   "OMAP730 P2 # "     /* Monitor Command Prompt   */
-#define CONFIG_SYS_CBSIZE		   256		       /* Console I/O Buffer Size  */
-/* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE		   (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		   16		       /* max number of command args   */
-#define CONFIG_SYS_BARGSIZE		   CONFIG_SYS_CBSIZE	       /* Boot Argument Buffer Size    */
-
-#define CONFIG_SYS_MEMTEST_START	   0x10000000	       /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END		   0x12000000	       /* 32 MB in DRAM	   */
-
-#define CONFIG_SYS_LOAD_ADDR		   0x10000000	       /* default load address */
-
-/* The OMAP730 has 3 general purpose MPU timers, they can be driven by
- * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
- * local divisor.
- */
-#define CONFIG_SYS_TIMERBASE		0xFFFEC500	/* use timer 1 */
-#define CONFIG_SYS_PTV			7	/* 2^(PTV+1), divide by 256 */
-#define CONFIG_SYS_HZ			((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-
-#define CONFIG_NR_DRAM_BANKS	   1		  /* we have 1 bank of DRAM */
-#define PHYS_SDRAM_1		   0x10000000	  /* SDRAM Bank #1 */
-#define PHYS_SDRAM_1_SIZE	   0x02000000	  /* 32 MB */
-
-#if defined(CONFIG_CS0_BOOT)
-#define PHYS_FLASH_1		   0x0C000000
-#elif defined(CONFIG_CS3_BOOT)
-#define PHYS_FLASH_1		   0x00000000
-#else
-#error Unknown Boot Chip-Select number
-#endif
-
-#define PHYS_SRAM		0x20000000
-
-#define CONFIG_SYS_FLASH_BASE		   PHYS_FLASH_1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	   1		  /* max number of memory banks */
-#define PHYS_FLASH_SIZE		   0x02000000	  /* 32MB */
-#define CONFIG_SYS_MAX_FLASH_SECT	   (259)	  /* max number of sectors on one chip */
-/* addr of environment */
-#define CONFIG_ENV_ADDR		   (CONFIG_SYS_FLASH_BASE + 0x020000)
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	    (20*CONFIG_SYS_HZ)	  /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	    (20*CONFIG_SYS_HZ)	  /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_IN_FLASH	   1
-#define CONFIG_ENV_SIZE		   0x20000	  /* Total Size of Environment Sector */
-#define CONFIG_ENV_OFFSET		   0x20000	  /* environment starts here  */
-
-#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR 	PHYS_SRAM
-
-#endif	  /* ! __CONFIG_H */
diff --git a/include/configs/otc570.h b/include/configs/otc570.h
index 3f4e073..629967d 100644
--- a/include/configs/otc570.h
+++ b/include/configs/otc570.h
@@ -193,8 +193,8 @@
 # define CONFIG_SYS_NAND_DBW_8
 # define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
 # define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-# define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTD, 15
-# define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 22
+# define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+# define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
 #endif
 
 /* Ethernet */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index fc95cf0..4a71927 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -50,15 +50,13 @@
 #define	CONFIG_SYS_MCKR1_VAL		\
 		(AT91_PMC_MCKR_CSS_SLOW |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
-		 AT91_PMC_MCKR_MDIV_2 |	\
-		 AT91_PMC_MCKR_PLLADIV_1)
+		 AT91_PMC_MCKR_MDIV_2)
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR2_VAL		\
 		(AT91_PMC_MCKR_CSS_PLLA |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
-		 AT91_PMC_MCKR_MDIV_2 |	\
-		 AT91_PMC_MCKR_PLLADIV_1)
+		 AT91_PMC_MCKR_MDIV_2)
 
 /* define PDC[31:16] as DATA[31:16] */
 #define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
@@ -166,9 +164,9 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTC, 12
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTC, 13
-#define	CONFIG_YELLOW_LED	AT91_PIO_PORTC, 15
+#define CONFIG_RED_LED		GPIO_PIN_PC(12)
+#define CONFIG_GREEN_LED	GPIO_PIN_PC(13)
+#define CONFIG_YELLOW_LED	GPIO_PIN_PC(15)
 
 #define CONFIG_BOOTDELAY	3
 
@@ -221,8 +219,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 16
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
 
 /* NOR flash */
 #define CONFIG_SYS_FLASH_CFI			1
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 533e249..d9c04d1 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -179,8 +179,8 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTB, 7	/* this is the power led */
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTB, 8	/* this is the user1 led */
+#define CONFIG_RED_LED		GPIO_PIN_PB(7) /* this is the power led */
+#define CONFIG_GREEN_LED	GPIO_PIN_PB(8) /* this is the user1 led */
 
 #define CONFIG_BOOTDELAY	3
 
@@ -241,8 +241,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTB, 30
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(30)
 
 #endif
 
diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index e0c388e..f78e0ec 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -54,8 +54,8 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTD, 31 /* this is the user1 led */
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTD, 0 /* this is the user2 led */
+#define CONFIG_RED_LED		GPIO_PIN_PD(31) /* this is the user1 led */
+#define CONFIG_GREEN_LED	GPIO_PIN_PD(0)  /* this is the user2 led */
 
 #define CONFIG_BOOTDELAY	3
 
@@ -106,8 +106,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
 /* our CLE is AD22 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTC, 14
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTD, 3
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PD(3)
 
 #endif
 
diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h
index 20b0f9a..7722f7b 100644
--- a/include/configs/pxm2.h
+++ b/include/configs/pxm2.h
@@ -70,6 +70,7 @@
 	"hostname=pxm2\0" \
 	"nand_img_size=0x500000\0" \
 	"optargs=\0" \
+	"splashpos=m,m\0"	\
 	CONFIG_COMMON_ENV_SETTINGS \
 	"mmc_dev=0\0" \
 	"mmc_root=/dev/mmcblk0p2 rw\0" \
@@ -118,9 +119,7 @@
 		"fi;" \
 	"fi;" \
 	"run nand_boot;" \
-	"if ping ${serverip}; then " \
-		"run net_nfs; " \
-	"fi; "
+	"reset;"
 
 #else
 #define CONFIG_BOOTDELAY		0
@@ -148,6 +147,8 @@
 #define DA8XX_LCD_CNTL_BASE	LCD_CNTL_BASE
 #define PWM_TICKS	0x1388
 #define PWM_DUTY	0x200
+#define CONFIG_SYS_CONSOLE_BG_COL	0xff
+#define CONFIG_SYS_CONSOLE_FG_COL	0x00
 #endif
 
 #endif	/* ! __CONFIG_PXM2_H */
diff --git a/include/configs/rut.h b/include/configs/rut.h
index 7c94644..d4519f9 100644
--- a/include/configs/rut.h
+++ b/include/configs/rut.h
@@ -65,7 +65,8 @@
 /* Default env settings */
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"hostname=rut\0" \
-	"splashpos=488,352\0" \
+	"nand_img_size=0x500000\0" \
+	"splashpos=m,m\0" \
 	"optargs=fixrtc --no-log consoleblank=0 \0" \
 	CONFIG_COMMON_ENV_SETTINGS \
 	"mmc_dev=0\0" \
@@ -111,9 +112,7 @@
 		"fi;" \
 	"fi;" \
 	"run nand_boot;" \
-	"if ping ${serverip}; then " \
-		"run net_nfs; " \
-	"fi; "
+	"reset;"
 
 #else
 #define CONFIG_BOOTDELAY		0
@@ -151,6 +150,9 @@
 #define BOARD_LCD_RESET		115	/* Bank 3 pin 19 */
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_FORMIKE
+#define DISPL_PLL_SPREAD_SPECTRUM
+#define CONFIG_SYS_CONSOLE_BG_COL	0xff
+#define CONFIG_SYS_CONSOLE_FG_COL	0x00
 #endif
 
 #endif	/* ! __CONFIG_RUT_H */
diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h
index 5a6f0fc..c34feb5 100644
--- a/include/configs/sama5d3xek.h
+++ b/include/configs/sama5d3xek.h
@@ -24,7 +24,10 @@
 #define CONFIG_AT91FAMILY
 #define CONFIG_ARCH_CPU_INIT
 
+#ifndef CONFIG_SPL_BUILD
 #define CONFIG_SKIP_LOWLEVEL_INIT
+#endif
+
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_DISPLAY_CPUINFO
 
@@ -93,8 +96,12 @@
 #define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_DDRCS
 #define CONFIG_SYS_SDRAM_SIZE		0x20000000
 
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_INIT_SP_ADDR		0x310000
+#else
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
+#endif
 
 /* SerialFlash */
 #define CONFIG_CMD_SF
@@ -235,4 +242,31 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
 
+/* SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x10000
+#define CONFIG_SPL_BSS_START_ADDR	0x20000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_SPL_MALLOC_START	0x20080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#ifdef CONFIG_SYS_USE_MMC
+#define CONFIG_SPL_LDSCRIPT		arch/arm/cpu/at91-common/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#endif
+
 #endif
diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h
index cbcd4e1..7e16c45 100644
--- a/include/configs/sbc35_a9g20.h
+++ b/include/configs/sbc35_a9g20.h
@@ -115,6 +115,7 @@
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R
 #define CONFIG_MACB_SEARCH_PHY
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* USB */
 #define CONFIG_USB_ATMEL
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h
index f37653f..4569fd4 100644
--- a/include/configs/siemens-am33x-common.h
+++ b/include/configs/siemens-am33x-common.h
@@ -254,11 +254,11 @@
 #define CONFIG_USB_GADGET
 #define CONFIG_USBDOWNLOAD_GADGET
 
-/* USB TI's IDs */
+/* USB DRACO ID as default */
 #define CONFIG_USBD_HS
-#define CONFIG_G_DNL_VENDOR_NUM 0x0525
-#define CONFIG_G_DNL_PRODUCT_NUM 0x4a47
-#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
+#define CONFIG_G_DNL_VENDOR_NUM 0x0908
+#define CONFIG_G_DNL_PRODUCT_NUM 0x02d2
+#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
 
 /* USB Device Firmware Update support */
 #define CONFIG_DFU_FUNCTION
@@ -358,31 +358,38 @@
 #define CONFIG_COMMON_ENV_SETTINGS \
 	"verify=no \0" \
 	"project_dir=systemone\0" \
+	"upgrade_available=0\0" \
+	"altbootcmd=run bootcmd\0" \
+	"bootlimit=3\0" \
+	"partitionset_active=A\0" \
 	"loadaddr=0x82000000\0" \
 	"kloadaddr=0x81000000\0" \
 	"script_addr=0x81900000\0" \
-	"console=console=ttyMTD,mtdoops console=ttyO0,115200n8\0" \
-	"active_set=a\0" \
+	"console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \
 	"nand_active_ubi_vol=rootfs_a\0" \
+	"nand_active_ubi_vol_A=rootfs_a\0" \
+	"nand_active_ubi_vol_B=rootfs_b\0" \
 	"nand_root_fs_type=ubifs rootwait=1\0" \
 	"nand_src_addr=0x280000\0" \
-	"nand_src_addr_a=0x280000\0" \
-	"nand_src_addr_b=0x780000\0" \
+	"nand_src_addr_A=0x280000\0" \
+	"nand_src_addr_B=0x780000\0" \
 	"nfsopts=nolock rw mem=128M\0" \
 	"ip_method=none\0" \
 	"bootenv=uEnv.txt\0" \
 	"bootargs_defaults=setenv bootargs " \
 		"console=${console} " \
+		"${testargs} " \
 		"${optargs}\0" \
 	"nand_args=run bootargs_defaults;" \
 		"mtdparts default;" \
-		"setenv nand_active_ubi_vol rootfs_${active_set};" \
-		"setenv ${active_set} true;" \
-		"if test -n ${a}; then " \
-			"setenv nand_src_addr ${nand_src_addr_a};" \
+		"setenv ${partitionset_active} true;" \
+		"if test -n ${A}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \
+			"setenv nand_src_addr ${nand_src_addr_A};" \
 		"fi;" \
-		"if test -n ${b}; then " \
-			"setenv nand_src_addr ${nand_src_addr_b};" \
+		"if test -n ${B}; then " \
+			"setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \
+			"setenv nand_src_addr ${nand_src_addr_B};" \
 		"fi;" \
 		"setenv nand_root ubi0:${nand_active_ubi_vol} rw " \
 		"ubi.mtd=9,2048;" \
@@ -403,9 +410,26 @@
 		"setenv bootargs ${bootargs} " \
 		"root=/dev/nfs ${mtdparts} " \
 		"nfsroot=${serverip}:${rootpath},${nfsopts} " \
-		"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \
+		"ip=${ipaddr}:${serverip}:" \
 		"${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
-	"nand_boot=echo Booting from nand, active set ${active_set} ...; " \
+	"nand_boot=echo Booting from nand; " \
+		"if test ${upgrade_available} -eq 1; then " \
+			"if test ${bootcount} -gt ${bootlimit}; " \
+				"then " \
+				"setenv upgrade_available 0;" \
+				"setenv ${partitionset_active} true;" \
+				"if test -n ${A}; then " \
+					"setenv partitionset_active B; " \
+					"env delete A; " \
+				"fi;" \
+				"if test -n ${B}; then " \
+					"setenv partitionset_active A; " \
+					"env delete B; " \
+				"fi;" \
+				"saveenv; " \
+			"fi;" \
+		"fi;" \
+		"echo set ${partitionset_active}...;" \
 		"run nand_args; " \
 		"nand read.i ${kloadaddr} ${nand_src_addr} " \
 		"${nand_img_size}; bootm ${kloadaddr}\0" \
@@ -414,7 +438,7 @@
 		"tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \
 		"bootm ${kloadaddr}\0" \
 	"flash_self=run nand_boot\0" \
-	"flash_self_test=setenv bootargs_defaults ${bootargs_defaults} test; " \
+	"flash_self_test=setenv testargs test; " \
 		"run nand_boot\0" \
 	"dfu_start=echo Preparing for dfu mode ...; " \
 		"run dfu_args; \0" \
@@ -425,8 +449,9 @@
 		"mode; echo Not ready yet: 'run flash_nfs' to use kernel " \
 		"from memory and root filesystem over NFS; echo Type " \
 		"'run net_nfs' to get Kernel over TFTP and mount root " \
-		"filesystem over NFS; echo Set active_set variable to 'a' " \
-		"or 'b' to select kernel and rootfs partition; " \
+		"filesystem over NFS; " \
+		"echo Set partitionset_active variable to 'A' " \
+		"or 'B' to select kernel and rootfs partition; " \
 		"echo" \
 		"\0"
 
@@ -457,4 +482,15 @@
 #define CONFIG_AUTOBOOT_PROMPT	"Autobooting in %d seconds, "		\
 				"press \"<Esc><Esc>\" to stop\n", bootdelay
 
+/* Reboot after 60 sec if bootcmd fails */
+#define CONFIG_RESET_TO_RETRY
+#define CONFIG_BOOT_RETRY_TIME 60
+
+#define CONFIG_BOOTCOUNT_LIMIT
+#define CONFIG_BOOTCOUNT_ENV
+
+/* Enable Device-Tree (FDT) support */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_CMD_FDT
+
 #endif	/* ! __CONFIG_SIEMENS_AM33X_COMMON_H */
diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h
index 5436bae..94a65c4 100644
--- a/include/configs/snapper9260.h
+++ b/include/configs/snapper9260.h
@@ -59,6 +59,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R
+#define CONFIG_AT91_WANTS_COMMON_PHY
 #define CONFIG_TFTP_PORT
 #define CONFIG_TFTP_TSIZE
 
@@ -74,7 +75,6 @@
 #define CONFIG_USB_STORAGE
 
 /* GPIOs and IO expander */
-#define CONFIG_AT91_LEGACY
 #define CONFIG_ATMEL_LEGACY
 #define CONFIG_AT91_GPIO
 #define CONFIG_AT91_GPIO_PULLUP		1
diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h
index 248e657..51339b1 100644
--- a/include/configs/stamp9g20.h
+++ b/include/configs/stamp9g20.h
@@ -145,6 +145,7 @@
 #ifdef CONFIG_MACB
 # define CONFIG_RMII			/* use reduced MII inteface */
 # define CONFIG_NET_RETRY_COUNT	20      /* # of DHCP/BOOTP retries */
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 /* BOOTP and DHCP options */
 # define CONFIG_BOOTP_BOOTFILESIZE
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
new file mode 100644
index 0000000..c980023
--- /dev/null
+++ b/include/configs/taurus.h
@@ -0,0 +1,160 @@
+/*
+ * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
+ * (C) Copyright 2013 Siemens AG
+ *
+ * Based on:
+ * U-Boot file: include/configs/at91sam9260ek.h
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian@popies.net>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
+#define MACH_TYPE_TAURUS		2067
+#define MACH_TYPE_AXM			2068
+
+/*
+ * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * adapting the initial boot program.
+ * Since the linker has to swallow that define, we must use a pure
+ * hex number here!
+ */
+
+
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000	/* main clock xtal */
+#define CONFIG_SYS_HZ			1000
+
+/* Misc CPU related */
+#define CONFIG_ARCH_CPU_INIT
+#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+/* general purpose I/O */
+#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
+#define CONFIG_AT91_GPIO
+#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY	3
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_SOURCE
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+
+/*
+ * SDRAM: 1 bank, min 32, max 128 MB
+ * Initialized before u-boot gets started.
+ */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		(128 * 1024 * 1024)
+
+/*
+ * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
+ * leaving the correct space for initial global data structure above
+ * that address while providing maximum stack area below.
+ */
+# define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
+#define CONFIG_SYS_NAND_DBW_8
+#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
+#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
+#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13
+#endif
+
+/* NOR flash - no real flash on this board */
+#define CONFIG_SYS_NO_FLASH			1
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#if defined(CONFIG_BOARD_TAURUS)
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#endif
+
+/* load address */
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+/* bootstrap in spi flash , u-boot + env + linux in nandflash */
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x100000
+#define CONFIG_ENV_OFFSET_REDUND	0x180000
+#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
+#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0x200000 0x300000; bootm"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 earlyprintk "				\
+	"mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro,"		\
+	"256k(env),256k(env_redundant),256k(spare),"			\
+	"512k(dtb),6M(kernel)ro,-(rootfs) "				\
+	"root=/dev/mtdblock7 rw rootfstype=jffs2"
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE \
+	(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN \
+	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h
index 10fe47f..4364eef 100644
--- a/include/configs/ti_am335x_common.h
+++ b/include/configs/ti_am335x_common.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CACHELINE_SIZE       64
 #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
 #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
+#define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
 
 #include <asm/arch/omap.h>
 
@@ -42,9 +43,9 @@
 
 /*
  * RTC related defines. To use bootcount you must set bootlimit in the
- * environment to a non-zero value.
+ * environment to a non-zero value and enable CONFIG_BOOTCOUNT_LIMIT
+ * in the board config.
  */
-#define CONFIG_BOOTCOUNT_LIMIT
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x44E3E000
 
 /* Enable the HW watchdog, since we can use this with bootcount */
diff --git a/include/configs/trats.h b/include/configs/trats.h
index f163303..0877142 100644
--- a/include/configs/trats.h
+++ b/include/configs/trats.h
@@ -299,6 +299,7 @@
 #define CONFIG_USB_GADGET_S3C_UDC_OTG
 #define CONFIG_USB_GADGET_DUALSPEED
 #define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_USB_CABLE_CHECK
 
 /* LCD */
 #define CONFIG_EXYNOS_FB
diff --git a/include/configs/trats2.h b/include/configs/trats2.h
index 3bcdfb1..5d86a3d 100644
--- a/include/configs/trats2.h
+++ b/include/configs/trats2.h
@@ -20,8 +20,6 @@
 #define CONFIG_EXYNOS4		/* which is in a EXYNOS4XXX */
 #define CONFIG_TIZEN		/* TIZEN lib */
 
-#define PLATFORM_NO_UNALIGNED
-
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 
 #define CONFIG_ARCH_CPU_INIT
@@ -65,10 +63,9 @@
 
 #define CONFIG_DISPLAY_CPUINFO
 
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (2 << 20))
+#include <asm/sizes.h>
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 * SZ_1M))
 
 /* select serial console configuration */
 #define CONFIG_SERIAL2
@@ -100,6 +97,7 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MMC
+#define CONFIG_CMD_DFU
 #define CONFIG_CMD_GPT
 #define CONFIG_CMD_PMIC
 
@@ -113,6 +111,23 @@
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
 
+/* USB Composite download gadget - g_dnl */
+#define CONFIG_USBDOWNLOAD_GADGET
+#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
+#define CONFIG_DFU_FUNCTION
+#define CONFIG_DFU_MMC
+
+/* TIZEN THOR downloader support */
+#define CONFIG_CMD_THOR_DOWNLOAD
+#define CONFIG_THOR_FUNCTION
+
+/* USB Samsung's IDs */
+#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
+#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
+#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
+#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
+#define CONFIG_G_DNL_MANUFACTURER "Samsung"
+
 /* To use the TFTPBOOT over USB, Please enable the CONFIG_CMD_NET */
 #undef CONFIG_CMD_NET
 
@@ -136,25 +151,29 @@
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 
 /* Tizen - partitions definitions */
-#define PARTS_CSA		"csa-mmc"
-#define PARTS_BOOTLOADER	"u-boot"
+#define PARTS_CSA		"csa"
 #define PARTS_BOOT		"boot"
+#define PARTS_MODEM		"modem"
+#define PARTS_CSC		"csc"
 #define PARTS_ROOT		"platform"
 #define PARTS_DATA		"data"
-#define PARTS_CSC		"csc"
 #define PARTS_UMS		"ums"
 
 #define PARTS_DEFAULT \
-	"uuid_disk=${uuid_gpt_disk};" \
-	"name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
-	"name="PARTS_BOOTLOADER",size=60MiB," \
-		"uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \
-	"name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
-	"name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
-	"name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
+	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
+	"name="PARTS_BOOT",size=64MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
+	"name="PARTS_MODEM",size=100MiB,uuid=${uuid_gpt_"PARTS_MODEM"};" \
 	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
+	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
+	"name="PARTS_DATA",size=512MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
 	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
 
+#define CONFIG_DFU_ALT \
+	"u-boot mmc 80 800;" \
+	"uImage ext4 0 2;" \
+	"exynos4412-trats2.dtb ext4 0 2;" \
+	""PARTS_ROOT" part 0 5\0"
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootk=" \
 		"run loaddtb; run loaduimage; bootm 0x40007FC0 - ${fdtaddr}\0" \
@@ -178,15 +197,16 @@
 	"rootfstype=ext4\0" \
 	"console=" CONFIG_DEFAULT_CONSOLE \
 	"kernelname=uImage\0" \
-	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
-		"0x40007FC0 ${kernelname}\0" \
+	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
+		"${kernelname}\0" \
 	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
 		"${fdtfile}\0" \
-	"mmcdev=0\0" \
+	"mmcdev=CONFIG_MMC_DEFAULT_DEV\0" \
 	"mmcbootpart=2\0" \
 	"mmcrootpart=5\0" \
 	"opts=always_resume=1\0" \
 	"partitions=" PARTS_DEFAULT \
+	"dfu_alt_info=" CONFIG_DFU_ALT \
 	"uartpath=ap\0" \
 	"usbpath=ap\0" \
 	"consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
@@ -233,8 +253,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_LOAD_ADDR \
 					- GENERATED_GBL_DATA_SIZE)
 
-#define CONFIG_SYS_HZ			1000
-
 /* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
@@ -288,6 +306,11 @@
 #define CONFIG_POWER_MUIC_MAX77693
 #define CONFIG_POWER_FG_MAX77693
 #define CONFIG_POWER_BATTERY_TRATS2
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_S3C_UDC_OTG
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_VBUS_DRAW	2
+#define CONFIG_USB_CABLE_CHECK
 
 /* LCD */
 #define CONFIG_EXYNOS_FB
@@ -300,6 +323,9 @@
 #define CONFIG_VIDEO_BMP_GZIP
 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 250 * 4) + (1 << 12))
 
+#define CONFIG_CMD_USB_MASS_STORAGE
+#define CONFIG_USB_GADGET_MASS_STORAGE
+
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT    1
 
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h
new file mode 100644
index 0000000..c4d04de
--- /dev/null
+++ b/include/configs/usb_a9263.h
@@ -0,0 +1,169 @@
+/*
+ * (C) Copyright 2007-2013
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
+ * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
+ *
+ * Settings for Calao USB-A9263 board
+ *
+ * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap
+ * installed on board will not be able to load it properly.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/hardware.h>
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_MACH_TYPE		MACH_TYPE_USB_A9263
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_CMDLINE_TAG	/* enable passing of ATAGs      */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_SYS_TEXT_BASE		0x23f00000
+
+/*
+ * Hardware drivers
+ */
+#define CONFIG_AT91_GPIO
+
+/* serial console */
+#define CONFIG_ATMEL_USART
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define CONFIG_USART_ID			ATMEL_ID_SYS
+#define CONFIG_BAUDRATE			115200
+
+#define CONFIG_BOOTDELAY 3
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMI
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
+#define CONFIG_SYS_SDRAM_SIZE		0x04000000
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
+#define AT91_SPI_CLK				8000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* no NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(22)
+#endif
+
+#define MTDPARTS_DEFAULT \
+	"mtdparts=atmel_nand:16m(kernel)ro,120m(root1),-(root2)"
+
+/* Ethernet */
+#define CONFIG_MACB
+#define CONFIG_RMII
+#define CONFIG_NET_RETRY_COUNT			20
+#define CONFIG_AT91_WANTS_COMMON_PHY
+
+/* USB */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SYS_USB_OHCI_CPU_INIT
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_FAT
+#endif
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000
+
+#define CONFIG_SYS_MEMTEST_START		CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH
+#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x4000)
+#define CONFIG_ENV_OFFSET	0x2000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+				 CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_BOOTCOMMAND	"nboot 21000000 0"
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
+	"root=/dev/mtdblock1 " \
+	"mtdparts=" MTDPARTS_DEFAULT " " \
+	"rw rootfstype=jffs2"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_LONGHELP
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
+
+#endif
diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h
index 6da5e8f..7e78f8a 100644
--- a/include/configs/vexpress_common.h
+++ b/include/configs/vexpress_common.h
@@ -132,7 +132,7 @@
 #define VEXPRESS_FLASHPROG_FLVPPEN	(1 << 0)
 
 #define CONFIG_SYS_TIMER_RATE		1000000
-#define CONFIG_SYS_TIMER_COUNTER	(0x10011000 + 0x4)
+#define CONFIG_SYS_TIMER_COUNTER	(V2M_TIMER01 + 0x4)
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 
 /* SMSC9115 Ethernet from SMSC9118 family */
diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h
index 1489080..88aaa95 100644
--- a/include/configs/vl_ma2sc.h
+++ b/include/configs/vl_ma2sc.h
@@ -320,8 +320,8 @@
 #define CONFIG_SYS_NAND_DBW_8		1
 #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)	/* our ALE is AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)	/* our CLE is AD22 */
-#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIO_PORTD, 15
-#define CONFIG_SYS_NAND_READY_PIN	AT91_PIO_PORTB, 0
+#define CONFIG_SYS_NAND_ENABLE_PIN	GPIO_PIN_PD(15)
+#define CONFIG_SYS_NAND_READY_PIN	GPIO_PIN_PB(0)
 #define CONFIG_SYS_64BIT_VSPRINTF	/* needed for nand_util.c */
 #endif
 
@@ -330,6 +330,7 @@
 #define CONFIG_RMII
 #define CONFIG_NET_MULTI
 #define CONFIG_NET_RETRY_COUNT		5
+#define CONFIG_AT91_WANTS_COMMON_PHY
 
 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 
diff --git a/include/i2c.h b/include/i2c.h
index c1be533..f93a183 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -147,7 +147,7 @@
 
 # elif (defined(CONFIG_AT91RM9200) || \
 	defined(CONFIG_AT91SAM9260) ||  defined(CONFIG_AT91SAM9261) || \
-	defined(CONFIG_AT91SAM9263)) && !defined(CONFIG_AT91_LEGACY)
+	defined(CONFIG_AT91SAM9263))
 #  define I2C_SOFT_DECLARATIONS	at91_pio_t *pio	= (at91_pio_t *) ATMEL_BASE_PIOA;
 # else
 #  define I2C_SOFT_DECLARATIONS
diff --git a/include/twl6030.h b/include/twl6030.h
index b4035ba..7898699 100644
--- a/include/twl6030.h
+++ b/include/twl6030.h
@@ -110,9 +110,47 @@
 #define CTRL_P2_EOCP2	(1 << 1)
 #define CTRL_P2_BUSY	(1 << 0)
 
+#define TWL6032_CTRL_P1	0x36
+#define CTRL_P1_SP1	(1 << 3)
+
 #define GPCH0_LSB	0x57
 #define GPCH0_MSB	0x58
 
+#define TWL6032_GPCH0_LSB	0x3b
+
+#define TWL6032_GPSELECT_ISB	0x35
+
+#define USB_PRODUCT_ID_LSB	0x02
+
+#define TWL6030_GPADC_VBAT_CHNL	0x07
+#define TWL6032_GPADC_VBAT_CHNL	0x12
+
+#define TWL6030_GPADC_CTRL	0x2e
+#define TWL6032_GPADC_CTRL2	0x2f
+#define GPADC_CTRL2_CH18_SCALER_EN	(1 << 2)
+#define GPADC_CTRL_SCALER_DIV4		(1 << 3)
+
+#define TWL6030_VBAT_MULT	40 * 1000
+#define TWL6032_VBAT_MULT	25 * 1000
+
+#define TWL6030_VBAT_SHIFT	(10 + 3)
+#define TWL6032_VBAT_SHIFT	(12 + 2)
+
+enum twl603x_chip_type{
+	chip_TWL6030,
+	chip_TWL6032,
+	chip_TWL603X_cnt
+};
+
+struct twl6030_data{
+	u8 chip_type;
+	u8 adc_rbase;
+	u8 adc_ctrl;
+	u8 adc_enable;
+	int vbat_mult;
+	int vbat_shift;
+};
+
 /* Functions to read and write from TWL6030 */
 static inline int twl6030_i2c_write_u8(u8 chip_no, u8 reg, u8 val)
 {