| commit | 45bc119d425884c4601e8c6af07071477959b512 | [log] [tgz] |
|---|---|---|
| author | Stephen George <stephen.george@freescale.com> | Mon Mar 25 07:40:12 2013 +0000 |
| committer | Andy Fleming <afleming@freescale.com> | Fri May 24 16:54:12 2013 -0500 |
| tree | 07118135410c7b399c8ac780b6fa803ceebdfaea | |
| parent | 171d0d22e7dc482e17a207ffa318c7ff78cc7f32 [diff] |
board/t4240qds, b4860qds: LAW/TLB for DCSR set to size 32M Debug trace buffers are memory mapped in DCSR space beyond 4M. Signed-off-by: Stephen George <stephen.george@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>