commit 43ec7e0bf5a6483fb69cd9895340a6a44f667847
author Trevor Woerner <trevor@toganlabs.com> Fri May 03 09:41:00 2019 -0400
committer Tom Rini <trini@konsulko.com> Sat May 18 08:15:35 2019 -0400
tree 6513e23c1df21e1a4bc55eb98a73a58f269ccf46
parent ba64b8b30bebfda159aff96ce41534e09b25bc3a

CONFIG_SPL_SYS_[DI]CACHE_OFF: add

While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Trevor Woerner <trevor@toganlabs.com>
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini <trini@konsulko.com>

arch/arm/cpu/armv8/cache_v8.c

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index 9ca397e..e500e72 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -13,7 +13,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 /*
  *  With 4k page granule, a virtual address is split into 4 lookup parts
@@ -657,7 +657,7 @@
 	__asm_invalidate_tlb_all();
 }
 
-#else	/* CONFIG_SYS_DCACHE_OFF */
+#else	/* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 /*
  * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
@@ -694,9 +694,9 @@
 {
 }
 
-#endif	/* CONFIG_SYS_DCACHE_OFF */
+#endif	/* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 
 void icache_enable(void)
 {
@@ -720,7 +720,7 @@
 	__asm_invalidate_l3_icache();
 }
 
-#else	/* CONFIG_SYS_ICACHE_OFF */
+#else	/* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 
 void icache_enable(void)
 {
@@ -739,7 +739,7 @@
 {
 }
 
-#endif	/* CONFIG_SYS_ICACHE_OFF */
+#endif	/* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 
 /*
  * Enable dCache & iCache, whether cache is actually enabled

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 978d46b..12d709e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -388,7 +388,7 @@
 		strcpy(name, "unknown");
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
@@ -611,7 +611,7 @@
 	icache_enable();
 	dcache_enable();
 }
-#endif	/* CONFIG_SYS_DCACHE_OFF */
+#endif	/* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 #ifdef CONFIG_TFABOOT
 enum boot_src __get_boot_src(u32 porsr1)

arch/arm/cpu/armv8/s32v234/cpu.c

diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c
index 1fa6841..b4cb67a 100644
--- a/arch/arm/cpu/armv8/s32v234/cpu.c
+++ b/arch/arm/cpu/armv8/s32v234/cpu.c
@@ -16,7 +16,7 @@
 	return readl(MC_ME_CS);
 }
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 #define S32V234_IRAM_BASE        0x3e800000UL
 #define S32V234_IRAM_SIZE        0x800000UL