tree 1bcb035b90add59f032b9e6843e7a3a112d234b3
parent e0098b37e8ef439be12d3ae96bd5afea09077ba9
author Marek Vasut <marex@denx.de> 1410890072 +0200
committer Marek Vasut <marex@denx.de> 1412610409 +0200

arm: socfpga: clock: Sync with reference code

Add the missing pieces from the reference clock code from Altera. This
puts the code on par with the Altera U-Boot fork for all but the SDRAM
self-refresh bits, which are not part of this patch.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>