sunxi: armv8: FEL: save and restore GICv3 registers
To be able to return to the BootROM FEL USB debug code, we must restore
the core's state as accurately as possible after the SPL has been run.
Since the BootROM runs in AArch32, but the SPL uses AArch64, this requires
a core reset, which clears the core's state.
So far we were saving and restoring the required registers like SCTLR
and VBAR, but could ignore the interrupt controller's state (GICC), since
that lives in MMIO registers, unaffected by a core reset.
Newer Allwinner SoCs now feature a GICv3 interrupt controller, which keeps
some GIC state in architected system registers, and those are cleared
when we switch back to AArch32.
To enable FEL operation on the Allwinner A523 SoC,
Add AArch32 assembly code to save and restore the ICC_PMR and ICC_IGRPEN1
system registers. The other GICv3 sysregs are either not relevant for the
BROM operation, or haven't been changed from their reset defaults by the
BROM anyway.
This enables FEL operation on the Allwinner A523 family of SoCs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index f7707ac..f9d0c9e 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -79,5 +79,12 @@
.word 0xe590100c // ldr r1, [r0, #12]
.word 0xee011f10 // mcr 15, 0, r1, cr1, cr0, {0} ; SCTLR
.word 0xf57ff06f // isb
+#ifdef CONFIG_MACH_SUN55I_A523
+ .word 0xe5901014 // ldr r1, [r0, #20]
+ .word 0xee041f16 // mcr 15, 0, r1, cr4, cr6, {0}; ICC_PMR
+ .word 0xe5901018 // ldr r1, [r0, #24]
+ .word 0xee0c1ffc // mcr 15, 0, r1, cr12, cr12, {7}; ICC_IGRPEN1
+#endif
+
.word 0xe12fff1e // bx lr ; return to FEL
ENDPROC(return_to_fel)