arm: socfpga: agilex5: Add SMMU initialization
Allow non-secure accesses only with SMMU peripherals. This would protect
the content in DDR secure region from accidentally modified by SMMU
peripherals.
Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com>
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
index 08f568f..af3f5d3 100644
--- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -388,6 +388,40 @@
bootph-all;
};
};
+
+ socfpga_smmu_secure_config: socfpga-smmu-secure-config {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bootph-all;
+
+ /* System manager */
+ i_sys_mgt_sysmgr_csr@10d12000 {
+ reg = <0x10d12000 0x00000500>;
+ intel,offset-settings =
+ /* dma_tbu_stream_ctrl_reg_0_dma0 */
+ <0x0000017c 0x00000000 0x0000003f>,
+ /* dma_tbu_stream_ctrl_reg_0_dma1 */
+ <0x00000180 0x00000000 0x0000003f>,
+ /* sdm_tbu_stream_ctrl_reg_1_sdm */
+ <0x00000184 0x00000000 0x0000003f>,
+ /* io_tbu_stream_ctrl_reg_2_usb2 */
+ <0x00000188 0x00000000 0x0000003f>,
+ /* io_tbu_stream_ctrl_reg_2_sdmmc */
+ <0x00000190 0x00000000 0x0000003f>,
+ /* io_tbu_stream_ctrl_reg_2_nand */
+ <0x00000194 0x00000000 0x0000003f>,
+ /* io_tbu_stream_ctrl_reg_2_etr */
+ <0x00000198 0x00000000 0x0000003f>,
+ /* tsn_tbu_stream_ctrl_reg_3_tsn0 */
+ <0x0000019c 0x00000000 0x0000003f>,
+ /* tsn_tbu_stream_ctrl_reg_3_tsn1 */
+ <0x000001a0 0x00000000 0x0000003f>,
+ /* tsn_tbu_stream_ctrl_reg_3_tsn2 */
+ <0x000001a4 0x00000000 0x0000003f>;
+ bootph-all;
+ };
+ };
};
};