diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0e8dc01..53d0831 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1021,7 +1021,6 @@
 config ARCH_UNIPHIER
 	bool "Socionext UniPhier SoCs"
 	select BOARD_LATE_INIT
-	select CLK_UNIPHIER
 	select DM
 	select DM_GPIO
 	select DM_I2C
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index d07715f..762429c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -119,8 +119,6 @@
 	uniphier-pxs2-vodka.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \
 	uniphier-pxs3-ref.dtb
-dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \
-	uniphier-sld3-ref.dtb
 dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \
 	uniphier-sld8-ref.dtb
 
diff --git a/arch/arm/dts/uniphier-ld20.dtsi b/arch/arm/dts/uniphier-ld20.dtsi
index 927340f..44257af 100644
--- a/arch/arm/dts/uniphier-ld20.dtsi
+++ b/arch/arm/dts/uniphier-ld20.dtsi
@@ -426,6 +426,7 @@
 				compatible = "snps,dwc3";
 				reg = <0x65a00000 0x10000>;
 				interrupts = <0 134 4>;
+				dr_mode = "host";
 				tx-fifo-resize;
 			};
 		};
diff --git a/arch/arm/dts/uniphier-pro4.dtsi b/arch/arm/dts/uniphier-pro4.dtsi
index 60287c4..cbb8482 100644
--- a/arch/arm/dts/uniphier-pro4.dtsi
+++ b/arch/arm/dts/uniphier-pro4.dtsi
@@ -587,6 +587,7 @@
 				compatible = "snps,dwc3";
 				reg = <0x65a00000 0x10000>;
 				interrupts = <0 134 4>;
+				dr_mode = "host";
 				tx-fifo-resize;
 			};
 		};
@@ -604,6 +605,7 @@
 				compatible = "snps,dwc3";
 				reg = <0x65c00000 0x10000>;
 				interrupts = <0 137 4>;
+				dr_mode = "host";
 				tx-fifo-resize;
 			};
 		};
diff --git a/arch/arm/dts/uniphier-pro5.dtsi b/arch/arm/dts/uniphier-pro5.dtsi
index a29597a..498354c 100644
--- a/arch/arm/dts/uniphier-pro5.dtsi
+++ b/arch/arm/dts/uniphier-pro5.dtsi
@@ -598,6 +598,7 @@
 				compatible = "snps,dwc3";
 				reg = <0x65a00000 0x10000>;
 				interrupts = <0 134 4>;
+				dr_mode = "host";
 				tx-fifo-resize;
 			};
 		};
@@ -615,6 +616,7 @@
 				compatible = "snps,dwc3";
 				reg = <0x65c00000 0x10000>;
 				interrupts = <0 137 4>;
+				dr_mode = "host";
 				tx-fifo-resize;
 			};
 		};
diff --git a/arch/arm/dts/uniphier-pxs2.dtsi b/arch/arm/dts/uniphier-pxs2.dtsi
index 2962cb5..32844f7 100644
--- a/arch/arm/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/dts/uniphier-pxs2.dtsi
@@ -610,6 +610,7 @@
 				compatible = "snps,dwc3";
 				reg = <0x65a00000 0x10000>;
 				interrupts = <0 134 4>;
+				dr_mode = "host";
 				tx-fifo-resize;
 			};
 		};
@@ -627,6 +628,7 @@
 				compatible = "snps,dwc3";
 				reg = <0x65c00000 0x10000>;
 				interrupts = <0 137 4>;
+				dr_mode = "host";
 				tx-fifo-resize;
 			};
 		};
diff --git a/arch/arm/dts/uniphier-sld3-ref.dts b/arch/arm/dts/uniphier-sld3-ref.dts
deleted file mode 100644
index baf7069..0000000
--- a/arch/arm/dts/uniphier-sld3-ref.dts
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Device Tree Source for UniPhier sLD3 Reference Board
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-/dts-v1/;
-/include/ "uniphier-sld3.dtsi"
-/include/ "uniphier-ref-daughter.dtsi"
-/include/ "uniphier-support-card.dtsi"
-
-/ {
-	model = "UniPhier sLD3 Reference Board";
-	compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3";
-
-	chosen {
-		stdout-path = "serial0:115200n8";
-	};
-
-	aliases {
-		serial0 = &serial0;
-		serial1 = &serial1;
-		serial2 = &serial2;
-		i2c0 = &i2c0;
-		i2c1 = &i2c1;
-		i2c2 = &i2c2;
-		i2c3 = &i2c3;
-		i2c4 = &i2c4;
-	};
-
-	memory@8000000 {
-		device_type = "memory";
-		reg = <0x80000000 0x20000000
-		       0xc0000000 0x20000000>;
-	};
-};
-
-&ethsc {
-	interrupts = <0 49 4>;
-};
-
-&serial0 {
-	status = "okay";
-};
-
-&serial1 {
-	status = "okay";
-};
-
-&serial2 {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-};
-
-&emmc {
-	status = "okay";
-};
-
-&sd {
-	status = "okay";
-};
-
-&usb0 {
-	status = "okay";
-};
-
-&usb1 {
-	status = "okay";
-};
-
-&usb2 {
-	status = "okay";
-};
-
-&usb3 {
-	status = "okay";
-};
-
-/* for U-Boot only */
-&serial0 {
-       u-boot,dm-pre-reloc;
-};
-
-&emmc {
-       u-boot,dm-pre-reloc;
-};
-
-&pinctrl_uart0 {
-	u-boot,dm-pre-reloc;
-};
-
-&pinctrl_emmc {
-	u-boot,dm-pre-reloc;
-};
diff --git a/arch/arm/dts/uniphier-sld3.dtsi b/arch/arm/dts/uniphier-sld3.dtsi
deleted file mode 100644
index 2bb2e02..0000000
--- a/arch/arm/dts/uniphier-sld3.dtsi
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
- * Device Tree Source for UniPhier sLD3 SoC
- *
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
- */
-
-/ {
-	compatible = "socionext,uniphier-sld3";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a9";
-			reg = <0>;
-			enable-method = "psci";
-			next-level-cache = <&l2>;
-		};
-
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a9";
-			reg = <1>;
-			enable-method = "psci";
-			next-level-cache = <&l2>;
-		};
-	};
-
-	psci {
-		compatible = "arm,psci-0.2";
-		method = "smc";
-	};
-
-	clocks {
-		refclk: ref {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <24576000>;
-		};
-
-		arm_timer_clk: arm_timer_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <50000000>;
-		};
-	};
-
-	soc {
-		compatible = "simple-bus";
-		#address-cells = <1>;
-		#size-cells = <1>;
-		ranges;
-		interrupt-parent = <&intc>;
-		u-boot,dm-pre-reloc;
-
-		timer@20000200 {
-			compatible = "arm,cortex-a9-global-timer";
-			reg = <0x20000200 0x20>;
-			interrupts = <1 11 0x304>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		timer@20000600 {
-			compatible = "arm,cortex-a9-twd-timer";
-			reg = <0x20000600 0x20>;
-			interrupts = <1 13 0x304>;
-			clocks = <&arm_timer_clk>;
-		};
-
-		intc: interrupt-controller@20001000 {
-			compatible = "arm,cortex-a9-gic";
-			#interrupt-cells = <3>;
-			interrupt-controller;
-			reg = <0x20001000 0x1000>,
-			      <0x20000100 0x100>;
-		};
-
-		l2: l2-cache@500c0000 {
-			compatible = "socionext,uniphier-system-cache";
-			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
-			      <0x506c0000 0x400>;
-			interrupts = <0 174 4>, <0 175 4>;
-			cache-unified;
-			cache-size = <(512 * 1024)>;
-			cache-sets = <256>;
-			cache-line-size = <128>;
-			cache-level = <2>;
-		};
-
-		serial0: serial@54006800 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006800 0x40>;
-			interrupts = <0 33 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart0>;
-			clocks = <&sys_clk 0>;
-			clock-frequency = <36864000>;
-		};
-
-		serial1: serial@54006900 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006900 0x40>;
-			interrupts = <0 35 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart1>;
-			clocks = <&sys_clk 0>;
-			clock-frequency = <36864000>;
-		};
-
-		serial2: serial@54006a00 {
-			compatible = "socionext,uniphier-uart";
-			status = "disabled";
-			reg = <0x54006a00 0x40>;
-			interrupts = <0 37 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_uart2>;
-			clocks = <&sys_clk 0>;
-			clock-frequency = <36864000>;
-		};
-
-		port0x: gpio@55000008 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000008 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port1x: gpio@55000010 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000010 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port2x: gpio@55000018 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000018 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port3x: gpio@55000020 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000020 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port4: gpio@55000028 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000028 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port5x: gpio@55000030 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000030 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port6x: gpio@55000038 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000038 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port7x: gpio@55000040 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000040 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port8x: gpio@55000048 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000048 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port9x: gpio@55000050 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000050 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port10x: gpio@55000058 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000058 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port11x: gpio@55000060 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000060 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port12x: gpio@55000068 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000068 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port13x: gpio@55000070 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000070 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port14x: gpio@55000078 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000078 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		port16x: gpio@55000088 {
-			compatible = "socionext,uniphier-gpio";
-			reg = <0x55000088 0x8>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		i2c0: i2c@58400000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58400000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 41 1>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_i2c0>;
-			clocks = <&sys_clk 1>;
-			clock-frequency = <100000>;
-		};
-
-		i2c1: i2c@58480000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58480000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 42 1>;
-			clocks = <&sys_clk 1>;
-			clock-frequency = <100000>;
-		};
-
-		i2c2: i2c@58500000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58500000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 43 1>;
-			clocks = <&sys_clk 1>;
-			clock-frequency = <100000>;
-		};
-
-		i2c3: i2c@58580000 {
-			compatible = "socionext,uniphier-i2c";
-			status = "disabled";
-			reg = <0x58580000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 44 1>;
-			clocks = <&sys_clk 1>;
-			clock-frequency = <100000>;
-		};
-
-		/* chip-internal connection for DMD */
-		i2c4: i2c@58600000 {
-			compatible = "socionext,uniphier-i2c";
-			reg = <0x58600000 0x40>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <0 45 1>;
-			clocks = <&sys_clk 1>;
-			clock-frequency = <400000>;
-		};
-
-		system_bus: system-bus@58c00000 {
-			compatible = "socionext,uniphier-system-bus";
-			status = "disabled";
-			reg = <0x58c00000 0x400>;
-			#address-cells = <2>;
-			#size-cells = <1>;
-		};
-
-		smpctrl@59801000 {
-			compatible = "socionext,uniphier-smpctrl";
-			reg = <0x59801000 0x400>;
-		};
-
-		mioctrl@59810000 {
-			compatible = "socionext,uniphier-sld3-mioctrl",
-				     "simple-mfd", "syscon";
-			reg = <0x59810000 0x800>;
-			u-boot,dm-pre-reloc;
-
-			mio_clk: clock {
-				compatible = "socionext,uniphier-sld3-mio-clock";
-				#clock-cells = <1>;
-				u-boot,dm-pre-reloc;
-			};
-
-			mio_rst: reset {
-				compatible = "socionext,uniphier-sld3-mio-reset";
-				#reset-cells = <1>;
-			};
-		};
-
-		emmc: sdhc@5a400000 {
-			compatible = "socionext,uniphier-sdhc";
-			status = "disabled";
-			reg = <0x5a400000 0x200>;
-			interrupts = <0 78 4>;
-			pinctrl-names = "default", "1.8v";
-			pinctrl-0 = <&pinctrl_emmc>;
-			pinctrl-1 = <&pinctrl_emmc_1v8>;
-			clocks = <&mio_clk 1>;
-			reset-names = "host", "bridge";
-			resets = <&mio_rst 1>, <&mio_rst 4>;
-			bus-width = <8>;
-			non-removable;
-			cap-mmc-highspeed;
-			cap-mmc-hw-reset;
-		};
-
-		sd: sdhc@5a500000 {
-			compatible = "socionext,uniphier-sdhc";
-			status = "disabled";
-			reg = <0x5a500000 0x200>;
-			interrupts = <0 76 4>;
-			pinctrl-names = "default", "1.8v";
-			pinctrl-0 = <&pinctrl_sd>;
-			pinctrl-1 = <&pinctrl_sd_1v8>;
-			clocks = <&mio_clk 0>;
-			reset-names = "host", "bridge";
-			resets = <&mio_rst 0>, <&mio_rst 3>;
-			bus-width = <4>;
-			cap-sd-highspeed;
-			sd-uhs-sdr12;
-			sd-uhs-sdr25;
-			sd-uhs-sdr50;
-		};
-
-		usb0: usb@5a800100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a800100 0x100>;
-			interrupts = <0 80 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb0>;
-			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
-			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
-				 <&mio_rst 12>;
-		};
-
-		usb1: usb@5a810100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a810100 0x100>;
-			interrupts = <0 81 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb1>;
-			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
-			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
-				 <&mio_rst 13>;
-		};
-
-		usb2: usb@5a820100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a820100 0x100>;
-			interrupts = <0 82 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb2>;
-			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
-			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
-				 <&mio_rst 14>;
-		};
-
-		usb3: usb@5a830100 {
-			compatible = "socionext,uniphier-ehci", "generic-ehci";
-			status = "disabled";
-			reg = <0x5a830100 0x100>;
-			interrupts = <0 83 4>;
-			pinctrl-names = "default";
-			pinctrl-0 = <&pinctrl_usb3>;
-			clocks = <&mio_clk 7>, <&mio_clk 11>, <&mio_clk 15>;
-			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 11>,
-				 <&mio_rst 15>;
-		};
-
-		soc-glue@5f800000 {
-			compatible = "socionext,uniphier-sld3-soc-glue",
-				     "simple-mfd", "syscon";
-			reg = <0x5f800000 0x2000>;
-			u-boot,dm-pre-reloc;
-
-			pinctrl: pinctrl {
-				compatible = "socionext,uniphier-sld3-pinctrl";
-				u-boot,dm-pre-reloc;
-			};
-		};
-
-		aidet@f1830000 {
-			compatible = "simple-mfd", "syscon";
-			reg = <0xf1830000 0x200>;
-		};
-
-		sysctrl@f1840000 {
-			compatible = "socionext,uniphier-sld3-sysctrl",
-				     "simple-mfd", "syscon";
-			reg = <0xf1840000 0x10000>;
-
-			sys_clk: clock {
-				compatible = "socionext,uniphier-sld3-clock";
-				#clock-cells = <1>;
-			};
-
-			sys_rst: reset {
-				compatible = "socionext,uniphier-sld3-reset";
-				#reset-cells = <1>;
-			};
-		};
-
-		nand: nand@f8000000 {
-			compatible = "socionext,uniphier-denali-nand-v5a";
-			status = "disabled";
-			reg-names = "nand_data", "denali_reg";
-			reg = <0xf8000000 0x20>, <0xf8100000 0x1000>;
-			interrupts = <0 65 4>;
-			clocks = <&sys_clk 2>;
-			nand-ecc-strength = <8>;
-		};
-	};
-};
-
-/include/ "uniphier-pinctrl.dtsi"
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 3147db7..6a7e239 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -15,10 +15,6 @@
         prompt "UniPhier SoC select"
         default ARCH_UNIPHIER_PRO4
 
-config ARCH_UNIPHIER_SLD3
-	bool "UniPhier sLD3 SoC"
-	select ARCH_UNIPHIER_32BIT
-
 config ARCH_UNIPHIER_LD4_SLD8
 	bool "UniPhier LD4/sLD8 SoCs"
 	select ARCH_UNIPHIER_32BIT
diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.c b/arch/arm/mach-uniphier/arm32/cache-uniphier.c
index 658969b..3df82bf 100644
--- a/arch/arm/mach-uniphier/arm32/cache-uniphier.c
+++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.c
@@ -197,9 +197,6 @@
 	void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00;
 
 	switch (readl(UNIPHIER_SSCID)) { /* revision */
-	case 0x11:	/* sLD3 */
-		base = (void __iomem *)UNIPHIER_SSCC + 0x870;
-		break;
 	case 0x12:	/* LD4 */
 	case 0x16:	/* sld8 */
 		base = (void __iomem *)UNIPHIER_SSCC + 0x840;
diff --git a/arch/arm/mach-uniphier/arm32/debug_ll.S b/arch/arm/mach-uniphier/arm32/debug_ll.S
index 76631f2..b39899e 100644
--- a/arch/arm/mach-uniphier/arm32/debug_ll.S
+++ b/arch/arm/mach-uniphier/arm32/debug_ll.S
@@ -26,27 +26,6 @@
 	and		r1, r1, #SG_REVISION_TYPE_MASK
 	mov		r1, r1, lsr #SG_REVISION_TYPE_SHIFT
 
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-#define UNIPHIER_SLD3_UART_CLK		36864000
-	cmp		r1, #0x25
-	bne		sld3_end
-
-	sg_set_pinsel	64, 1, 4, 4, r0, r1	@ TXD0 -> TXD0
-
-	ldr		r0, =BCSCR5
-	ldr		r1, =0x24440000
-	str		r1, [r0]
-
-	ldr		r0, =SC_CLKCTRL
-	ldr		r1, [r0]
-	orr		r1, r1, #SC_CLKCTRL_CEN_PERI
-	str		r1, [r0]
-
-	ldr		r3, =DIV_ROUND(UNIPHIER_SLD3_UART_CLK, 16 * BAUDRATE)
-
-	b		init_uart
-sld3_end:
-#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 #define UNIPHIER_LD4_UART_CLK		36864000
 	cmp		r1, #0x26
diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
index af5ed1c..a399a16 100644
--- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S
+++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S
@@ -25,13 +25,16 @@
 	orr	r0, r0, #(CR_C | CR_M)	@ enable MMU and Dcache
 	mcr	p15, 0, r0, c1, c0, 0
 
+#ifdef CONFIG_DEBUG_LL
+	bl	debug_ll_init
+#endif
+
 	bl	setup_init_ram		@ RAM area for stack and page table
 
 	/*
 	 * Now we are using the page table embedded in the Boot ROM.
-	 * It is not handy since it is not a straight mapped table for sLD3.
-	 * Also, the access to the external bus is prohibited.  What we need
-	 * to do next is to create a page table and switch over to it.
+	 * What we need to do next is to create a page table and switch
+	 * over to it.
 	 */
 	bl	create_page_table
 	bl	__v7_flush_dcache_all
@@ -43,10 +46,6 @@
 
 	bl	enable_mmu
 
-#ifdef CONFIG_DEBUG_LL
-	bl	debug_ll_init
-#endif
-
 	mov	lr, r8			@ restore link
 	mov	pc, lr			@ back to my caller
 ENDPROC(lowlevel_init)
@@ -99,11 +98,6 @@
 
 ENTRY(setup_init_ram)
 	ldr	r1, = SSCO_BASE
-	mrc	p15, 0, r0, c2, c0, 0	@ TTBR0
-	ldr	r0, [r0, #0x400]	@ entry for virtual address 0x100*****
-	bfc	r0, #0, #20
-	cmp	r0, #0x50000000		@ is sLD3 page table?
-	biceq	r1, r1, #0xc0000000	@ sLD3 ROM maps 0x5******* to 0x1*******
 
 	/* Touch to zero for the boot way */
 0:	ldr	r0, = 0x00408006	@ touch to zero with address range
diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c
index 65a468d..3ab101a 100644
--- a/arch/arm/mach-uniphier/arm32/psci.c
+++ b/arch/arm/mach-uniphier/arm32/psci.c
@@ -29,7 +29,6 @@
 static int uniphier_get_nr_cpus(void)
 {
 	switch (uniphier_get_soc_id()) {
-	case UNIPHIER_SLD3_ID:
 	case UNIPHIER_PRO4_ID:
 	case UNIPHIER_PRO5_ID:
 		return 2;
diff --git a/arch/arm/mach-uniphier/bcu/Makefile b/arch/arm/mach-uniphier/bcu/Makefile
index 02107b3..5a9d8d7 100644
--- a/arch/arm/mach-uniphier/bcu/Makefile
+++ b/arch/arm/mach-uniphier/bcu/Makefile
@@ -2,6 +2,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= bcu-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= bcu-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= bcu-ld4.o
diff --git a/arch/arm/mach-uniphier/bcu/bcu-sld3.c b/arch/arm/mach-uniphier/bcu/bcu-sld3.c
deleted file mode 100644
index 99b318f..0000000
--- a/arch/arm/mach-uniphier/bcu/bcu-sld3.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (C) 2011-2014 Panasonic Corporation
- * Copyright (C) 2015-2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <linux/io.h>
-
-#include "../init.h"
-#include "bcu-regs.h"
-
-#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
-
-void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd)
-{
-	int shift;
-
-	writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
-	writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
-	writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
-	/*
-	 * 0xe0000000-0xefffffff: Ex-bus
-	 * 0xf0000000-0xfbffffff: ASM bus
-	 * 0xfc000000-0xffffffff: OCM bus
-	 */
-	writel(0x24440000, BCSCR5);
-
-	/* Specify DDR channel */
-	shift = bd->dram_ch[0].size / 0x04000000 * 4;
-	writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
-
-	shift -= 32;
-	writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
-
-	shift -= 32;
-	writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
-}
diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c
index 884bc67..ed58d07 100644
--- a/arch/arm/mach-uniphier/board_init.c
+++ b/arch/arm/mach-uniphier/board_init.c
@@ -86,15 +86,6 @@
 };
 
 static const struct uniphier_initdata uniphier_initdata[] = {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-	{
-		.soc_id = UNIPHIER_SLD3_ID,
-		.nand_2cs = true,
-		.sbc_init = uniphier_sbc_init_admulti,
-		.pll_init = uniphier_sld3_pll_init,
-		.clk_init = uniphier_ld4_clk_init,
-	},
-#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 	{
 		.soc_id = UNIPHIER_LD4_ID,
diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c
index 78de256..9bfc4c2 100644
--- a/arch/arm/mach-uniphier/boards.c
+++ b/arch/arm/mach-uniphier/boards.c
@@ -13,25 +13,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-static const struct uniphier_board_data uniphier_sld3_data = {
-	.dram_freq = 1600,
-	.dram_ch[0] = {
-		.size = 0x20000000,
-		.width = 32,
-	},
-	.dram_ch[1] = {
-		.size = 0x20000000,
-		.width = 16,
-	},
-	.dram_ch[2] = {
-		.size = 0x10000000,
-		.width = 16,
-	},
-	.flags = UNIPHIER_BD_DRAM_SPARSE,
-};
-#endif
-
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 static const struct uniphier_board_data uniphier_ld4_data = {
 	.dram_freq = 1600,
@@ -146,9 +127,6 @@
 };
 
 static const struct uniphier_board_id uniphier_boards[] = {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-	{ "socionext,uniphier-sld3", &uniphier_sld3_data, },
-#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 	{ "socionext,uniphier-ld4", &uniphier_ld4_data, },
 #endif
diff --git a/arch/arm/mach-uniphier/boot-device/Makefile b/arch/arm/mach-uniphier/boot-device/Makefile
index b357292..6c8580c 100644
--- a/arch/arm/mach-uniphier/boot-device/Makefile
+++ b/arch/arm/mach-uniphier/boot-device/Makefile
@@ -4,7 +4,6 @@
 
 obj-y					+= boot-device.o
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= boot-device-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= boot-device-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= boot-device-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= boot-device-ld4.o
diff --git a/arch/arm/mach-uniphier/boot-device/boot-device-sld3.c b/arch/arm/mach-uniphier/boot-device/boot-device-sld3.c
deleted file mode 100644
index 2b36494..0000000
--- a/arch/arm/mach-uniphier/boot-device/boot-device-sld3.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (C) 2014      Panasonic Corporation
- * Copyright (C) 2015-2017 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <spl.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-
-#include "boot-device.h"
-
-const struct uniphier_boot_device uniphier_sld3_boot_device_table[] = {
-	{BOOT_DEVICE_NOR,  "NOR  (XECS0)"},
-	{BOOT_DEVICE_NONE, "External Master"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_MMC1, "eMMC (3.3V, Boot Oparation)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_MMC1, "eMMC (1.8V, Boot Oparation)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_MMC1, "eMMC (3.3V, Normal)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_MMC1, "eMMC (1.8V, Normal)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 128KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 256KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, EraseSize 512KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 128KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 256KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, EraseSize 512KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, EraseSize   1MB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 128KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 256KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, EraseSize 512KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 128KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 256KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, EraseSize 512KB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, EraseSize   1MB, Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC  8, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 1, ECC 16, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 4, ECC 24, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC  8, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 16, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 24, ONFI,            Addr 5)"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-	{BOOT_DEVICE_NONE, "Reserved"},
-};
-
-const unsigned uniphier_sld3_boot_device_count =
-				ARRAY_SIZE(uniphier_sld3_boot_device_table);
diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.c b/arch/arm/mach-uniphier/boot-device/boot-device.c
index 094f77b..0f93926 100644
--- a/arch/arm/mach-uniphier/boot-device/boot-device.c
+++ b/arch/arm/mach-uniphier/boot-device/boot-device.c
@@ -26,15 +26,6 @@
 };
 
 static const struct uniphier_boot_device_info uniphier_boot_device_info[] = {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-	{
-		.soc_id = UNIPHIER_SLD3_ID,
-		.boot_device_sel_shift = 0,
-		.boot_device_table = uniphier_sld3_boot_device_table,
-		.boot_device_count = &uniphier_sld3_boot_device_count,
-		.have_internal_stm = 0,
-	},
-#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 	{
 		.soc_id = UNIPHIER_LD4_ID,
diff --git a/arch/arm/mach-uniphier/boot-device/boot-device.h b/arch/arm/mach-uniphier/boot-device/boot-device.h
index c4ce3e5..f9631d6 100644
--- a/arch/arm/mach-uniphier/boot-device/boot-device.h
+++ b/arch/arm/mach-uniphier/boot-device/boot-device.h
@@ -13,14 +13,12 @@
 	const char *desc;
 };
 
-extern const struct uniphier_boot_device uniphier_sld3_boot_device_table[];
 extern const struct uniphier_boot_device uniphier_ld4_boot_device_table[];
 extern const struct uniphier_boot_device uniphier_pro5_boot_device_table[];
 extern const struct uniphier_boot_device uniphier_pxs2_boot_device_table[];
 extern const struct uniphier_boot_device uniphier_ld11_boot_device_table[];
 extern const struct uniphier_boot_device uniphier_pxs3_boot_device_table[];
 
-extern const unsigned int uniphier_sld3_boot_device_count;
 extern const unsigned int uniphier_ld4_boot_device_count;
 extern const unsigned int uniphier_pro5_boot_device_count;
 extern const unsigned int uniphier_pxs2_boot_device_count;
diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile
index 1680ddd..76633bc 100644
--- a/arch/arm/mach-uniphier/clk/Makefile
+++ b/arch/arm/mach-uniphier/clk/Makefile
@@ -4,17 +4,15 @@
 
 ifdef CONFIG_SPL_BUILD
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= clk-early-sld3.o clk-dram-sld3.o dpll-sld3.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= clk-early-sld3.o clk-dram-sld3.o dpll-ld4.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= clk-early-sld3.o clk-dram-sld3.o dpll-pro4.o
-obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-early-sld3.o clk-dram-sld3.o dpll-sld8.o
-obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-early-sld3.o clk-dram-pro5.o dpll-pro5.o
-obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
-obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-early-sld3.o clk-dram-pxs2.o dpll-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
+obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
+obj-$(CONFIG_ARCH_UNIPHIER_PRO5)	+= clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
+obj-$(CONFIG_ARCH_UNIPHIER_PXS2)	+= clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
+obj-$(CONFIG_ARCH_UNIPHIER_LD6B)	+= clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
 
 else
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= clk-ld4.o pll-sld3.o dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= clk-ld4.o pll-ld4.o dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= clk-pro4.o pll-pro4.o dpll-tail.o
 obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= clk-ld4.o pll-ld4.o dpll-tail.o
diff --git a/arch/arm/mach-uniphier/clk/clk-dram-sld3.c b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
similarity index 93%
rename from arch/arm/mach-uniphier/clk/clk-dram-sld3.c
rename to arch/arm/mach-uniphier/clk/clk-dram-ld4.c
index 3430303..407daf0 100644
--- a/arch/arm/mach-uniphier/clk/clk-dram-sld3.c
+++ b/arch/arm/mach-uniphier/clk/clk-dram-ld4.c
@@ -12,7 +12,7 @@
 #include "../init.h"
 #include "../sc-regs.h"
 
-void uniphier_sld3_dram_clk_init(void)
+void uniphier_ld4_dram_clk_init(void)
 {
 	u32 tmp;
 
diff --git a/arch/arm/mach-uniphier/clk/clk-early-sld3.c b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
similarity index 93%
rename from arch/arm/mach-uniphier/clk/clk-early-sld3.c
rename to arch/arm/mach-uniphier/clk/clk-early-ld4.c
index 3235da2..07b916d 100644
--- a/arch/arm/mach-uniphier/clk/clk-early-sld3.c
+++ b/arch/arm/mach-uniphier/clk/clk-early-ld4.c
@@ -12,7 +12,7 @@
 #include "../init.h"
 #include "../sc-regs.h"
 
-void uniphier_sld3_early_clk_init(void)
+void uniphier_ld4_early_clk_init(void)
 {
 	u32 tmp;
 
diff --git a/arch/arm/mach-uniphier/clk/dpll-sld3.c b/arch/arm/mach-uniphier/clk/dpll-sld3.c
deleted file mode 100644
index 0eb310c..0000000
--- a/arch/arm/mach-uniphier/clk/dpll-sld3.c
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include "../init.h"
-
-int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd)
-{
-	/* add pll init code here */
-	return 0;
-}
diff --git a/arch/arm/mach-uniphier/clk/pll-sld3.c b/arch/arm/mach-uniphier/clk/pll-sld3.c
deleted file mode 100644
index 37a7c12..0000000
--- a/arch/arm/mach-uniphier/clk/pll-sld3.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include "../init.h"
-#include "pll.h"
-
-void uniphier_sld3_pll_init(void)
-{
-	uniphier_ld4_dpll_ssc_en();
-}
diff --git a/arch/arm/mach-uniphier/cpu-info.c b/arch/arm/mach-uniphier/cpu-info.c
index 2ce73c5..90ef411 100644
--- a/arch/arm/mach-uniphier/cpu-info.c
+++ b/arch/arm/mach-uniphier/cpu-info.c
@@ -23,10 +23,6 @@
 	puts("SoC:   ");
 
 	switch (id) {
-	case UNIPHIER_SLD3_ID:
-		puts("sLD3");
-		required_model = 2;
-		break;
 	case UNIPHIER_LD4_ID:
 		puts("LD4");
 		required_rev = 2;
diff --git a/arch/arm/mach-uniphier/debug-uart/Makefile b/arch/arm/mach-uniphier/debug-uart/Makefile
index 0bad718..3837ee7 100644
--- a/arch/arm/mach-uniphier/debug-uart/Makefile
+++ b/arch/arm/mach-uniphier/debug-uart/Makefile
@@ -3,7 +3,6 @@
 #
 
 ifdef CONFIG_SPL_BUILD
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= debug-uart-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= debug-uart-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= debug-uart-pro4.o
 obj-$(CONFIG_ARCH_UNIPHIER_SLD8)	+= debug-uart-sld8.o
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c b/arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c
deleted file mode 100644
index 508318a..0000000
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart-sld3.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include "../bcu/bcu-regs.h"
-#include "../sc-regs.h"
-#include "../sg-regs.h"
-#include "debug-uart.h"
-
-#define UNIPHIER_SLD3_UART_CLK		36864000
-
-unsigned int uniphier_sld3_debug_uart_init(void)
-{
-	u32 tmp;
-
-	sg_set_pinsel(64, 1, 4, 4);	/* TXD0 -> TXD0 */
-
-	writel(0x24440000, BCSCR5);
-
-	tmp = readl(SC_CLKCTRL);
-	tmp |= SC_CLKCTRL_CEN_PERI;
-	writel(tmp, SC_CLKCTRL);
-
-	return DIV_ROUND_CLOSEST(UNIPHIER_SLD3_UART_CLK, 16 * CONFIG_BAUDRATE);
-}
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.c b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
index 72a514d..94d05a8 100644
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.c
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.c
@@ -33,11 +33,6 @@
 	unsigned int divisor;
 
 	switch (uniphier_get_soc_id()) {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-	case UNIPHIER_SLD3_ID:
-		divisor = uniphier_sld3_debug_uart_init();
-		break;
-#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 	case UNIPHIER_LD4_ID:
 		divisor = uniphier_ld4_debug_uart_init();
diff --git a/arch/arm/mach-uniphier/debug-uart/debug-uart.h b/arch/arm/mach-uniphier/debug-uart/debug-uart.h
index 8de9124..d57e5df 100644
--- a/arch/arm/mach-uniphier/debug-uart/debug-uart.h
+++ b/arch/arm/mach-uniphier/debug-uart/debug-uart.h
@@ -7,7 +7,6 @@
 #ifndef _MACH_DEBUG_UART_H
 #define _MACH_DEBUG_UART_H
 
-unsigned int uniphier_sld3_debug_uart_init(void);
 unsigned int uniphier_ld4_debug_uart_init(void);
 unsigned int uniphier_pro4_debug_uart_init(void);
 unsigned int uniphier_sld8_debug_uart_init(void);
diff --git a/arch/arm/mach-uniphier/dram/Makefile b/arch/arm/mach-uniphier/dram/Makefile
index 1da33f6..baf2a7b 100644
--- a/arch/arm/mach-uniphier/dram/Makefile
+++ b/arch/arm/mach-uniphier/dram/Makefile
@@ -4,7 +4,6 @@
 
 ifdef CONFIG_SPL_BUILD
 
-obj-$(CONFIG_ARCH_UNIPHIER_SLD3)	+= umc-sld3.o
 obj-$(CONFIG_ARCH_UNIPHIER_LD4)		+= umc-ld4.o \
 					   ddrphy-training.o ddrphy-ld4.o
 obj-$(CONFIG_ARCH_UNIPHIER_PRO4)	+= umc-pro4.o \
diff --git a/arch/arm/mach-uniphier/dram/umc-sld3.c b/arch/arm/mach-uniphier/dram/umc-sld3.c
deleted file mode 100644
index 99249eb..0000000
--- a/arch/arm/mach-uniphier/dram/umc-sld3.c
+++ /dev/null
@@ -1,6 +0,0 @@
-#include "../init.h"
-
-int uniphier_sld3_umc_init(const struct uniphier_board_data *bd)
-{
-	return 0;
-}
diff --git a/arch/arm/mach-uniphier/dram_init.c b/arch/arm/mach-uniphier/dram_init.c
index 6eb8d26..32d3593 100644
--- a/arch/arm/mach-uniphier/dram_init.c
+++ b/arch/arm/mach-uniphier/dram_init.c
@@ -28,15 +28,6 @@
 
 static const struct uniphier_memif_data uniphier_memif_data[] = {
 	{
-		.soc_id = UNIPHIER_SLD3_ID,
-		.sparse_ch1_base = 0xc0000000,
-		/*
-		 * In fact, SLD3 has DRAM ch2, but the memory regions for ch1
-		 * and ch2 overlap, and host cannot get access to them at the
-		 * same time.  Hide the ch2 from U-Boot.
-		 */
-	},
-	{
 		.soc_id = UNIPHIER_LD4_ID,
 		.sparse_ch1_base = 0xc0000000,
 	},
diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h
index b322628..29f638d 100644
--- a/arch/arm/mach-uniphier/init.h
+++ b/arch/arm/mach-uniphier/init.h
@@ -28,7 +28,6 @@
 
 const struct uniphier_board_data *uniphier_get_board_param(void);
 
-int uniphier_sld3_init(const struct uniphier_board_data *bd);
 int uniphier_ld4_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_init(const struct uniphier_board_data *bd);
@@ -63,34 +62,29 @@
 }
 #endif
 
-void uniphier_sld3_bcu_init(const struct uniphier_board_data *bd);
 void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd);
 
 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd);
-int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd);
 int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd);
 
-int uniphier_sld3_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_ld4_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_dpll_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_dpll_init(const struct uniphier_board_data *bd);
 
-void uniphier_sld3_early_clk_init(void);
+void uniphier_ld4_early_clk_init(void);
 
-void uniphier_sld3_dram_clk_init(void);
+void uniphier_ld4_dram_clk_init(void);
 void uniphier_pro5_dram_clk_init(void);
 void uniphier_pxs2_dram_clk_init(void);
 
-int uniphier_sld3_umc_init(const struct uniphier_board_data *bd);
 int uniphier_ld4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pro4_umc_init(const struct uniphier_board_data *bd);
 int uniphier_sld8_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pro5_umc_init(const struct uniphier_board_data *bd);
 int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd);
 
-void uniphier_sld3_pll_init(void);
 void uniphier_ld4_pll_init(void);
 void uniphier_pro4_pll_init(void);
 void uniphier_ld11_pll_init(void);
diff --git a/arch/arm/mach-uniphier/memconf.c b/arch/arm/mach-uniphier/memconf.c
index 4ced2cb..3b34e4d 100644
--- a/arch/arm/mach-uniphier/memconf.c
+++ b/arch/arm/mach-uniphier/memconf.c
@@ -15,7 +15,7 @@
 #include "init.h"
 
 static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
-				   int have_ch2, int have_ch2_disable_bit)
+				   int have_ch2)
 {
 	u32 val = 0;
 	unsigned long size_per_word;
@@ -100,8 +100,7 @@
 		goto out;
 
 	if (!bd->dram_ch[2].size) {
-		if (have_ch2_disable_bit)
-			val |= SG_MEMCONF_CH2_DISABLE;
+		val |= SG_MEMCONF_CH2_DISABLE;
 		goto out;
 	}
 
@@ -149,15 +148,10 @@
 
 int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd)
 {
-	return __uniphier_memconf_init(bd, 0, 0);
+	return __uniphier_memconf_init(bd, 0);
 }
 
-int uniphier_memconf_3ch_no_disbit_init(const struct uniphier_board_data *bd)
-{
-	return __uniphier_memconf_init(bd, 1, 0);
-}
-
 int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd)
 {
-	return __uniphier_memconf_init(bd, 1, 1);
+	return __uniphier_memconf_init(bd, 1);
 }
diff --git a/arch/arm/mach-uniphier/mmc-boot-mode.c b/arch/arm/mach-uniphier/mmc-boot-mode.c
index d60c578..f40534e 100644
--- a/arch/arm/mach-uniphier/mmc-boot-mode.c
+++ b/arch/arm/mach-uniphier/mmc-boot-mode.c
@@ -14,7 +14,7 @@
 	struct mmc *mmc;
 
 	/*
-	 * work around a bug in the Boot ROM of PH1-sLD3, LD4, Pro4, and sLD8:
+	 * work around a bug in the Boot ROM of LD4, Pro4, and sLD8:
 	 *
 	 * The boot ROM in these SoCs breaks the PARTITION_CONFIG [179] of
 	 * Extended CSD register; when switching to the Boot Partition 1, the
diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h
index ad58e10..54bbe43 100644
--- a/arch/arm/mach-uniphier/sc-regs.h
+++ b/arch/arm/mach-uniphier/sc-regs.h
@@ -11,11 +11,7 @@
 #ifndef ARCH_SC_REGS_H
 #define ARCH_SC_REGS_H
 
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-#define SC_BASE_ADDR			0xf1840000
-#else
 #define SC_BASE_ADDR			0x61840000
-#endif
 
 #define SC_DPLLOSCCTRL			(SC_BASE_ADDR | 0x1110)
 #define SC_DPLLOSCCTRL_DPLLST		(0x1 << 1)
diff --git a/arch/arm/mach-uniphier/soc-info.h b/arch/arm/mach-uniphier/soc-info.h
index 0473252..9ba6a7e 100644
--- a/arch/arm/mach-uniphier/soc-info.h
+++ b/arch/arm/mach-uniphier/soc-info.h
@@ -11,7 +11,6 @@
 #include <linux/kernel.h>
 #include <linux/stddef.h>
 
-#define UNIPHIER_SLD3_ID	0x25
 #define UNIPHIER_LD4_ID		0x26
 #define UNIPHIER_PRO4_ID	0x28
 #define UNIPHIER_SLD8_ID	0x29
diff --git a/arch/arm/mach-uniphier/spl_board_init.c b/arch/arm/mach-uniphier/spl_board_init.c
index 6da5631..1272b4e 100644
--- a/arch/arm/mach-uniphier/spl_board_init.c
+++ b/arch/arm/mach-uniphier/spl_board_init.c
@@ -24,35 +24,24 @@
 };
 
 static const struct uniphier_spl_initdata uniphier_spl_initdata[] = {
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3)
-	{
-		.soc_id = UNIPHIER_SLD3_ID,
-		.bcu_init = uniphier_sld3_bcu_init,
-		.early_clk_init = uniphier_sld3_early_clk_init,
-		.dpll_init = uniphier_sld3_dpll_init,
-		.memconf_init = uniphier_memconf_3ch_no_disbit_init,
-		.dram_clk_init = uniphier_sld3_dram_clk_init,
-		.umc_init = uniphier_sld3_umc_init,
-	},
-#endif
 #if defined(CONFIG_ARCH_UNIPHIER_LD4)
 	{
 		.soc_id = UNIPHIER_LD4_ID,
 		.bcu_init = uniphier_ld4_bcu_init,
-		.early_clk_init = uniphier_sld3_early_clk_init,
+		.early_clk_init = uniphier_ld4_early_clk_init,
 		.dpll_init = uniphier_ld4_dpll_init,
 		.memconf_init = uniphier_memconf_2ch_init,
-		.dram_clk_init = uniphier_sld3_dram_clk_init,
+		.dram_clk_init = uniphier_ld4_dram_clk_init,
 		.umc_init = uniphier_ld4_umc_init,
 	},
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_PRO4)
 	{
 		.soc_id = UNIPHIER_PRO4_ID,
-		.early_clk_init = uniphier_sld3_early_clk_init,
+		.early_clk_init = uniphier_ld4_early_clk_init,
 		.dpll_init = uniphier_pro4_dpll_init,
 		.memconf_init = uniphier_memconf_2ch_init,
-		.dram_clk_init = uniphier_sld3_dram_clk_init,
+		.dram_clk_init = uniphier_ld4_dram_clk_init,
 		.umc_init = uniphier_pro4_umc_init,
 	},
 #endif
@@ -60,17 +49,17 @@
 	{
 		.soc_id = UNIPHIER_SLD8_ID,
 		.bcu_init = uniphier_ld4_bcu_init,
-		.early_clk_init = uniphier_sld3_early_clk_init,
+		.early_clk_init = uniphier_ld4_early_clk_init,
 		.dpll_init = uniphier_sld8_dpll_init,
 		.memconf_init = uniphier_memconf_2ch_init,
-		.dram_clk_init = uniphier_sld3_dram_clk_init,
+		.dram_clk_init = uniphier_ld4_dram_clk_init,
 		.umc_init = uniphier_sld8_umc_init,
 	},
 #endif
 #if defined(CONFIG_ARCH_UNIPHIER_PRO5)
 	{
 		.soc_id = UNIPHIER_PRO5_ID,
-		.early_clk_init = uniphier_sld3_early_clk_init,
+		.early_clk_init = uniphier_ld4_early_clk_init,
 		.dpll_init = uniphier_pro5_dpll_init,
 		.memconf_init = uniphier_memconf_2ch_init,
 		.dram_clk_init = uniphier_pro5_dram_clk_init,
@@ -80,7 +69,7 @@
 #if defined(CONFIG_ARCH_UNIPHIER_PXS2)
 	{
 		.soc_id = UNIPHIER_PXS2_ID,
-		.early_clk_init = uniphier_sld3_early_clk_init,
+		.early_clk_init = uniphier_ld4_early_clk_init,
 		.dpll_init = uniphier_pxs2_dpll_init,
 		.memconf_init = uniphier_memconf_3ch_init,
 		.dram_clk_init = uniphier_pxs2_dram_clk_init,
@@ -90,7 +79,7 @@
 #if defined(CONFIG_ARCH_UNIPHIER_LD6B)
 	{
 		.soc_id = UNIPHIER_LD6B_ID,
-		.early_clk_init = uniphier_sld3_early_clk_init,
+		.early_clk_init = uniphier_ld4_early_clk_init,
 		.dpll_init = uniphier_pxs2_dpll_init,
 		.memconf_init = uniphier_memconf_3ch_init,
 		.dram_clk_init = uniphier_pxs2_dram_clk_init,
diff --git a/configs/uniphier_sld3_defconfig b/configs/uniphier_sld3_defconfig
deleted file mode 100644
index 35f8421..0000000
--- a/configs/uniphier_sld3_defconfig
+++ /dev/null
@@ -1,46 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_UNIPHIER=y
-CONFIG_SYS_TEXT_BASE=0x84000000
-CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_SPL_MMC_SUPPORT=y
-CONFIG_SPL_SERIAL_SUPPORT=y
-CONFIG_SPL_NAND_SUPPORT=y
-CONFIG_ARCH_UNIPHIER_SLD3=y
-CONFIG_MICRO_SUPPORT_CARD=y
-CONFIG_DEFAULT_DEVICE_TREE="uniphier-sld3-ref"
-# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
-CONFIG_SPL=y
-CONFIG_SPL_NOR_SUPPORT=y
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_CONFIG=y
-CONFIG_CMD_BOOTZ=y
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_FPGA is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_TFTPPUT=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_FAT=y
-CONFIG_CMD_FS_GENERIC=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_GPIO_UNIPHIER=y
-CONFIG_MISC=y
-CONFIG_I2C_EEPROM=y
-CONFIG_MMC_UNIPHIER=y
-CONFIG_NAND_DENALI=y
-CONFIG_SYS_NAND_DENALI_64BIT=y
-CONFIG_NAND_DENALI_SPARE_AREA_SKIP_BYTES=8
-CONFIG_SPL_NAND_DENALI=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_STORAGE=y
diff --git a/doc/README.uniphier b/doc/README.uniphier
index f21c9d0..fa1f9bc 100644
--- a/doc/README.uniphier
+++ b/doc/README.uniphier
@@ -29,7 +29,6 @@
 
  Board         | <defconfig>                  | <device-tree>
 ---------------|------------------------------|------------------------------
-sLD3 reference | uniphier_sld3_defconfig      | uniphier-sld3-ref (default)
 LD4 reference  | uniphier_ld4_sld8_defconfig  | uniphier-ld4-ref (default)
 sld8 reference | uniphier_ld4_sld8_defconfig  | uniphier-sld8-def
 Pro4 reference | uniphier_pro4_defconfig      | uniphier-pro4-ref (default)
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index da3e355..3666d84 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -1,9 +1,8 @@
 config CLK_UNIPHIER
-	bool "Clock driver for UniPhier SoCs"
+	def_bool y
 	depends on ARCH_UNIPHIER
 	select CLK
-	select SPL_CLK
-	default y
+	select SPL_CLK if SPL
 	help
 	  Support for clock controllers on UniPhier SoCs.
 	  Say Y if you want to control clocks provided by System Control
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 0fb4854..eed21b9 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -147,10 +147,6 @@
 
 static const struct udevice_id uniphier_clk_match[] = {
 	{
-		.compatible = "socionext,uniphier-sld3-mio-clock",
-		.data = (ulong)&uniphier_mio_clk_data,
-	},
-	{
 		.compatible = "socionext,uniphier-ld4-mio-clock",
 		.data = (ulong)&uniphier_mio_clk_data,
 	},
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index 18e6856..9c13dcd 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -64,11 +64,9 @@
 	UNIPHIER_MIO_CLK_USB2(8, 0),
 	UNIPHIER_MIO_CLK_USB2(9, 1),
 	UNIPHIER_MIO_CLK_USB2(10, 2),
-	UNIPHIER_MIO_CLK_USB2(11, 3),		/* for PH1-sLD3 only */
 	UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
 	UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
 	UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
-	UNIPHIER_MIO_CLK_USB2_PHY(15, 3),	/* for PH1-sLD3 only */
 	UNIPHIER_CLK_END
 };
 
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index a6e51ca..b6abcd1 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -3,12 +3,6 @@
 config PINCTRL_UNIPHIER
 	bool
 
-config PINCTRL_UNIPHIER_SLD3
-	bool "UniPhier sLD3 SoC pinctrl driver"
-	depends on ARCH_UNIPHIER_SLD3
-	default y
-	select PINCTRL_UNIPHIER
-
 config PINCTRL_UNIPHIER_LD4
 	bool "UniPhier LD4 SoC pinctrl driver"
 	depends on ARCH_UNIPHIER_LD4
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index b805765..215104b 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -4,7 +4,6 @@
 
 obj-y					+= pinctrl-uniphier-core.o
 
-obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3)	+= pinctrl-uniphier-sld3.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_LD4)	+= pinctrl-uniphier-ld4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4)	+= pinctrl-uniphier-pro4.o
 obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8)	+= pinctrl-uniphier-sld8.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
deleted file mode 100644
index e9cc9d2..0000000
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright (C) 2016 Socionext Inc.
- *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <dm/pinctrl.h>
-
-#include "pinctrl-uniphier.h"
-
-static const unsigned emmc_pins[] = {55, 56, 60};
-static const int emmc_muxvals[] = {1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {57};
-static const int emmc_dat8_muxvals[] = {1};
-static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112,
-					  113};
-static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2};
-static const unsigned ether_rmii_pins[] = {35};
-static const int ether_rmii_muxvals[] = {1};
-static const unsigned i2c0_pins[] = {36};
-static const int i2c0_muxvals[] = {0};
-static const unsigned nand_pins[] = {38, 39, 40, 58, 59};
-static const int nand_muxvals[] = {1, 1, 1, 1, 1};
-static const unsigned nand_cs1_pins[] = {41};
-static const int nand_cs1_muxvals[] = {1};
-static const unsigned sd_pins[] = {42, 43, 44, 45};
-static const int sd_muxvals[] = {1, 1, 1, 1};
-static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76,
-					   77, 78, 79, 80, 88, 89, 91, 92, 99};
-static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
-					 1, 1, 1, 1, 1};
-static const unsigned system_bus_cs0_pins[] = {93};
-static const int system_bus_cs0_muxvals[] = {1};
-static const unsigned system_bus_cs1_pins[] = {94};
-static const int system_bus_cs1_muxvals[] = {1};
-static const unsigned system_bus_cs2_pins[] = {95};
-static const int system_bus_cs2_muxvals[] = {1};
-static const unsigned system_bus_cs3_pins[] = {96};
-static const int system_bus_cs3_muxvals[] = {1};
-static const unsigned system_bus_cs4_pins[] = {81};
-static const int system_bus_cs4_muxvals[] = {1};
-static const unsigned system_bus_cs5_pins[] = {82};
-static const int system_bus_cs5_muxvals[] = {1};
-static const unsigned uart0_pins[] = {63, 64};
-static const int uart0_muxvals[] = {0, 1};
-static const unsigned uart1_pins[] = {65, 66};
-static const int uart1_muxvals[] = {0, 1};
-static const unsigned uart2_pins[] = {96, 102};
-static const int uart2_muxvals[] = {2, 2};
-static const unsigned usb0_pins[] = {13, 14};
-static const int usb0_muxvals[] = {0, 1};
-static const unsigned usb1_pins[] = {15, 16};
-static const int usb1_muxvals[] = {0, 1};
-static const unsigned usb2_pins[] = {17, 18};
-static const int usb2_muxvals[] = {0, 1};
-static const unsigned usb3_pins[] = {19, 20};
-static const int usb3_muxvals[] = {0, 1};
-
-static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = {
-	UNIPHIER_PINCTRL_GROUP_SPL(emmc),
-	UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
-	UNIPHIER_PINCTRL_GROUP(ether_mii),
-	UNIPHIER_PINCTRL_GROUP(ether_rmii),
-	UNIPHIER_PINCTRL_GROUP(i2c0),
-	UNIPHIER_PINCTRL_GROUP(nand),
-	UNIPHIER_PINCTRL_GROUP(nand_cs1),
-	UNIPHIER_PINCTRL_GROUP(sd),
-	UNIPHIER_PINCTRL_GROUP(system_bus),
-	UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
-	UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
-	UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
-	UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
-	UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
-	UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
-	UNIPHIER_PINCTRL_GROUP_SPL(uart0),
-	UNIPHIER_PINCTRL_GROUP_SPL(uart1),
-	UNIPHIER_PINCTRL_GROUP_SPL(uart2),
-	UNIPHIER_PINCTRL_GROUP(usb0),
-	UNIPHIER_PINCTRL_GROUP(usb1),
-	UNIPHIER_PINCTRL_GROUP(usb2),
-	UNIPHIER_PINCTRL_GROUP(usb3)
-};
-
-static const char * const uniphier_sld3_functions[] = {
-	UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
-	UNIPHIER_PINMUX_FUNCTION(ether_mii),
-	UNIPHIER_PINMUX_FUNCTION(ether_rmii),
-	UNIPHIER_PINMUX_FUNCTION(i2c0),
-	UNIPHIER_PINMUX_FUNCTION(nand),
-	UNIPHIER_PINMUX_FUNCTION(sd),
-	UNIPHIER_PINMUX_FUNCTION(system_bus),
-	UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
-	UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
-	UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
-	UNIPHIER_PINMUX_FUNCTION(usb0),
-	UNIPHIER_PINMUX_FUNCTION(usb1),
-	UNIPHIER_PINMUX_FUNCTION(usb2),
-	UNIPHIER_PINMUX_FUNCTION(usb3),
-};
-
-static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = {
-	.groups = uniphier_sld3_groups,
-	.groups_count = ARRAY_SIZE(uniphier_sld3_groups),
-	.functions = uniphier_sld3_functions,
-	.functions_count = ARRAY_SIZE(uniphier_sld3_functions),
-	.caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT,
-};
-
-static int uniphier_sld3_pinctrl_probe(struct udevice *dev)
-{
-	return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata);
-}
-
-static const struct udevice_id uniphier_sld3_pinctrl_match[] = {
-	{ .compatible = "socionext,uniphier-sld3-pinctrl" },
-	{ /* sentinel */ }
-};
-
-U_BOOT_DRIVER(uniphier_sld3_pinctrl) = {
-	.name = "uniphier-sld3-pinctrl",
-	.id = UCLASS_PINCTRL,
-	.of_match = of_match_ptr(uniphier_sld3_pinctrl_match),
-	.probe = uniphier_sld3_pinctrl_probe,
-	.priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
-	.ops = &uniphier_pinctrl_ops,
-};
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index 17e971a..ebb2cae 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -41,46 +41,20 @@
 	}
 
 /* System reset data */
-#define UNIPHIER_SLD3_SYS_RESET_STDMAC(id)		\
-	UNIPHIER_RESETX((id), 0x2000, 10)
-
-#define UNIPHIER_LD11_SYS_RESET_STDMAC(id)		\
-	UNIPHIER_RESETX((id), 0x200c, 8)
-
-#define UNIPHIER_PRO4_SYS_RESET_GIO(id)			\
-	UNIPHIER_RESETX((id), 0x2000, 6)
-
-#define UNIPHIER_LD20_SYS_RESET_GIO(id)			\
-	UNIPHIER_RESETX((id), 0x200c, 5)
-
-#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch)		\
-	UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
-
-static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
-	UNIPHIER_SLD3_SYS_RESET_STDMAC(8),	/* Ether, HSC, MIO */
-	UNIPHIER_RESET_END,
-};
-
 static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
-	UNIPHIER_SLD3_SYS_RESET_STDMAC(8),	/* HSC, MIO, RLE */
-	UNIPHIER_PRO4_SYS_RESET_GIO(12),	/* Ether, SATA, USB3 */
-	UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
-	UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
-	UNIPHIER_RESET_END,
-};
-
-static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
-	UNIPHIER_SLD3_SYS_RESET_STDMAC(8),	/* HSC */
-	UNIPHIER_PRO4_SYS_RESET_GIO(12),	/* PCIe, USB3 */
-	UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
-	UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+	UNIPHIER_RESETX(2, 0x2000, 2),		/* NAND */
+	UNIPHIER_RESETX(8, 0x2000, 10),		/* STDMAC */
+	UNIPHIER_RESETX(12, 0x2000, 6),		/* GIO */
+	UNIPHIER_RESETX(14, 0x2000, 17),	/* USB30 */
+	UNIPHIER_RESETX(15, 0x2004, 17),	/* USB31 */
 	UNIPHIER_RESET_END,
 };
 
 static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
-	UNIPHIER_SLD3_SYS_RESET_STDMAC(8),	/* HSC, RLE */
-	UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
-	UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+	UNIPHIER_RESETX(2, 0x2000, 2),		/* NAND */
+	UNIPHIER_RESETX(8, 0x2000, 10),		/* STDMAC */
+	UNIPHIER_RESETX(14, 0x2000, 17),	/* USB30 */
+	UNIPHIER_RESETX(15, 0x2004, 17),	/* USB31 */
 	UNIPHIER_RESETX(16, 0x2014, 4),		/* USB30-PHY0 */
 	UNIPHIER_RESETX(17, 0x2014, 0),		/* USB30-PHY1 */
 	UNIPHIER_RESETX(18, 0x2014, 2),		/* USB30-PHY2 */
@@ -91,14 +65,11 @@
 	UNIPHIER_RESET_END,
 };
 
-static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
-	UNIPHIER_LD11_SYS_RESET_STDMAC(8),	/* HSC, MIO */
-	UNIPHIER_RESET_END,
-};
-
 static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
-	UNIPHIER_LD11_SYS_RESET_STDMAC(8),	/* HSC */
-	UNIPHIER_LD20_SYS_RESET_GIO(12),	/* PCIe, USB3 */
+	UNIPHIER_RESETX(2, 0x200c, 0),		/* NAND */
+	UNIPHIER_RESETX(4, 0x200c, 2),		/* eMMC */
+	UNIPHIER_RESETX(8, 0x200c, 8),		/* STDMAC */
+	UNIPHIER_RESETX(12, 0x200c, 5),		/* GIO */
 	UNIPHIER_RESETX(16, 0x200c, 12),	/* USB30-PHY0 */
 	UNIPHIER_RESETX(17, 0x200c, 13),	/* USB30-PHY1 */
 	UNIPHIER_RESETX(18, 0x200c, 14),	/* USB30-PHY2 */
@@ -270,12 +241,8 @@
 static const struct udevice_id uniphier_reset_match[] = {
 	/* System reset */
 	{
-		.compatible = "socionext,uniphier-sld3-reset",
-		.data = (ulong)uniphier_sld3_sys_reset_data,
-	},
-	{
 		.compatible = "socionext,uniphier-ld4-reset",
-		.data = (ulong)uniphier_sld3_sys_reset_data,
+		.data = (ulong)uniphier_pro4_sys_reset_data,
 	},
 	{
 		.compatible = "socionext,uniphier-pro4-reset",
@@ -283,11 +250,11 @@
 	},
 	{
 		.compatible = "socionext,uniphier-sld8-reset",
-		.data = (ulong)uniphier_sld3_sys_reset_data,
+		.data = (ulong)uniphier_pro4_sys_reset_data,
 	},
 	{
 		.compatible = "socionext,uniphier-pro5-reset",
-		.data = (ulong)uniphier_pro5_sys_reset_data,
+		.data = (ulong)uniphier_pro4_sys_reset_data,
 	},
 	{
 		.compatible = "socionext,uniphier-pxs2-reset",
@@ -295,7 +262,7 @@
 	},
 	{
 		.compatible = "socionext,uniphier-ld11-reset",
-		.data = (ulong)uniphier_ld11_sys_reset_data,
+		.data = (ulong)uniphier_ld20_sys_reset_data,
 	},
 	{
 		.compatible = "socionext,uniphier-ld20-reset",
@@ -303,10 +270,6 @@
 	},
 	/* Media I/O reset */
 	{
-		.compatible = "socionext,uniphier-sld3-mio-clock",
-		.data = (ulong)uniphier_mio_reset_data,
-	},
-	{
 		.compatible = "socionext,uniphier-ld4-mio-reset",
 		.data = (ulong)uniphier_mio_reset_data,
 	},
diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h
index 6f53139..9a64063 100644
--- a/include/configs/uniphier.h
+++ b/include/configs/uniphier.h
@@ -88,13 +88,8 @@
 
 #define CONFIG_NAND_DENALI_ECC_SIZE			1024
 
-#ifdef CONFIG_ARCH_UNIPHIER_SLD3
-#define CONFIG_SYS_NAND_REGS_BASE			0xf8100000
-#define CONFIG_SYS_NAND_DATA_BASE			0xf8000000
-#else
 #define CONFIG_SYS_NAND_REGS_BASE			0x68100000
 #define CONFIG_SYS_NAND_DATA_BASE			0x68000000
-#endif
 
 #define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_NAND_DATA_BASE + 0x10)
 
@@ -249,8 +244,7 @@
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE)
 
 /* only for SPL */
-#if defined(CONFIG_ARCH_UNIPHIER_SLD3) || \
-	defined(CONFIG_ARCH_UNIPHIER_LD4) || \
+#if defined(CONFIG_ARCH_UNIPHIER_LD4) || \
 	defined(CONFIG_ARCH_UNIPHIER_SLD8)
 #define CONFIG_SPL_TEXT_BASE		0x00040000
 #else