clk: qcom: Use setbits_le32() for qcom_gate_clk_en()
The other clock enable functions in clock-qcom.c use setbits_le32() to
read/modify/write the enable registers. Use the same for qcom_gate_clk_en()
to simplify the code a bit.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Casey Connolly <casey.connolly@linaro.org>
Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-3-fcc371c9e45f@linaro.org
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
diff --git a/drivers/clk/qcom/clock-qcom.c b/drivers/clk/qcom/clock-qcom.c
index 5018851..7a259db 100644
--- a/drivers/clk/qcom/clock-qcom.c
+++ b/drivers/clk/qcom/clock-qcom.c
@@ -76,16 +76,13 @@
int qcom_gate_clk_en(const struct msm_clk_priv *priv, unsigned long id)
{
- u32 val;
if (id >= priv->data->num_clks || priv->data->clks[id].reg == 0) {
log_err("gcc@%#08llx: unknown clock ID %lu!\n",
priv->base, id);
return -ENOENT;
}
- val = readl(priv->base + priv->data->clks[id].reg);
- writel(val | priv->data->clks[id].en_val, priv->base + priv->data->clks[id].reg);
-
+ setbits_le32(priv->base + priv->data->clks[id].reg, priv->data->clks[id].en_val);
return 0;
}