drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue
Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/drivers/ddr/imx/imx8m/ddrphy_train.c b/drivers/ddr/imx/imx8m/ddrphy_train.c
index f2a997b..08fed61 100644
--- a/drivers/ddr/imx/imx8m/ddrphy_train.c
+++ b/drivers/ddr/imx/imx8m/ddrphy_train.c
@@ -8,6 +8,7 @@
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
#include <asm/arch/lpddr4_define.h>
+#include <asm/arch/sys_proto.h>
int ddr_cfg_phy(struct dram_timing_info *dram_timing)
{
@@ -71,9 +72,15 @@
/* Read the Message Block results */
dwc_ddrphy_apb_wr(0xd0000, 0x0);
+
ddrphy_init_read_msg_block(fsp_msg->fw_type);
+
+ if(fsp_msg->fw_type != FW_2D_IMAGE)
+ get_trained_CDD(i);
+
dwc_ddrphy_apb_wr(0xd0000, 0x1);
+
fsp_msg++;
}