tree 81f90fbf651d0892767e820aae05c5dbd719161e
parent 59b6247d9f9cd0054dd6ace2983994b8533eaa60
author Eric Nelson <eric@nelint.com> 1477870427 -0700
committer Stefano Babic <sbabic@denx.de> 1480433998 +0100

mx6: ddr: allow 32 cycles for DQS gating calibration

The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
cycle) for the first PHY.

Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
output value isn't polluted with calibration artifacts.

Signed-off-by: Eric Nelson <eric@nelint.com>
Reviewed-by: Marek Vasut <marex@denx.de>