diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 8c37bbe..e108a0d 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -71,5 +71,16 @@
   # bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
   setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
 
-  The above memory controller interleaving and bank interleaving can be mixed. The syntax is
-  setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"
+Memory controller address hashing
+==================================
+If the DDR controller supports address hashing, it can be enabled by hwconfig.
+
+Syntax is:
+hwconfig=fsl_ddr:addr_hash=true
+
+Combination of hwconfig
+=======================
+Hwconfig can be combined with multiple parameters, for example, on a supported
+platform
+
+hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3