xtensa: add support for the xtensa processor architecture [1/2]
The Xtensa processor architecture is a configurable, extensible,
and synthesizable 32-bit RISC processor core provided by Cadence.
This is the first part of the basic architecture port with changes to
common files. The 'arch/xtensa' directory, and boards and additional
drivers will be in separate commits.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
diff --git a/MAINTAINERS b/MAINTAINERS
index 8905f88..e0bf679 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -454,6 +454,11 @@
T: git git://git.denx.de/u-boot-x86.git
F: arch/x86/
+XTENSA
+M: Max Filippov <jcmvbkbc@gmail.com>
+S: Maintained
+F: arch/xtensa/
+
THE REST
M: Tom Rini <trini@konsulko.com>
L: u-boot@lists.denx.de