| commit | 568edfd7547dd715fb7bb611736b8659d198dbc1 | [log] [tgz] |
|---|---|---|
| author | Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> | Fri Oct 23 04:59:02 2020 -0600 |
| committer | Michal Simek <michal.simek@xilinx.com> | Tue Oct 27 08:13:34 2020 +0100 |
| tree | e56147df0a26e3b93a32e7e5b4ccbd275b5ba320 | |
| parent | 8f62986d7ccb091fe4482adce39e19211373b2ab [diff] |
mmc: zynq_sdhci: Add clock phase delays for Versal Define default values for input and output clock phase delays for Versal. Also define functions for setting tapdelays based on these clock phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>