S5PC2XX: Rename S5pc2XX to exynos
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.
In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
index 58b737b..7a1ea98 100644
--- a/board/samsung/smdkv310/lowlevel_init.S
+++ b/board/samsung/smdkv310/lowlevel_init.S
@@ -1,5 +1,5 @@
/*
- * Lowlevel setup for SMDKV310 board based on S5PC210
+ * Lowlevel setup for SMDKV310 board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
@@ -45,11 +45,11 @@
/* r5 has always zero */
mov r5, #0
- ldr r7, =S5PC210_GPIO_PART1_BASE
- ldr r6, =S5PC210_GPIO_PART2_BASE
+ ldr r7, =EXYNOS4_GPIO_PART1_BASE
+ ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* check reset status */
- ldr r0, =(S5PC210_POWER_BASE + 0x81C) @ INFORM7
+ ldr r0, =(EXYNOS4_POWER_BASE + 0x81C) @ INFORM7
ldr r1, [r0]
/* AFTR wakeup reset */
@@ -95,9 +95,9 @@
exit_wakeup:
/* Load return address and jump to kernel */
- ldr r0, =(S5PC210_POWER_BASE + 0x800) @ INFORM0
+ ldr r0, =(EXYNOS4_POWER_BASE + 0x800) @ INFORM0
- /* r1 = physical address of s5pc210_cpu_resume function */
+ /* r1 = physical address of exynos4210_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel*/
@@ -111,7 +111,7 @@
*/
system_clock_init:
push {lr}
- ldr r0, =S5PC210_CLOCK_BASE
+ ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =0x0101
@@ -388,12 +388,12 @@
/* setup UART0-UART3 GPIOs (part1) */
mov r0, r7
ldr r1, =0x22222222
- str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
+ str r1, [r0, #0x00] @ EXYNOS4_GPIO_A0_OFFSET
ldr r1, =0x00222222
- str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
+ str r1, [r0, #0x20] @ EXYNOS4_GPIO_A1_OFFSET
- ldr r0, =S5PC210_UART_BASE
- add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
+ ldr r0, =EXYNOS4_UART_BASE
+ add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
ldr r1, =0x3C5
str r1, [r0, #0x4]
diff --git a/board/samsung/smdkv310/mem_setup.S b/board/samsung/smdkv310/mem_setup.S
index 73aebe3..d3b6265 100644
--- a/board/samsung/smdkv310/mem_setup.S
+++ b/board/samsung/smdkv310/mem_setup.S
@@ -1,5 +1,5 @@
/*
- * Memory setup for SMDKV310 board based on S5PC210
+ * Memory setup for SMDKV310 board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
@@ -54,7 +54,7 @@
str r1, [r0]
#ifdef SET_MIU
- ldr r0, =S5PC210_MIU_BASE @0x10600000
+ ldr r0, =EXYNOS4_MIU_BASE @0x10600000
#ifdef CONFIG_MIU_1BIT_INTERLEAVED
ldr r1, =0x0000000c
str r1, [r0, #0x400] @MIU_INTLV_CONFIG
@@ -89,7 +89,7 @@
#endif
#endif
/* DREX0 */
- ldr r0, =S5PC210_DMC0_BASE @0x10400000
+ ldr r0, =EXYNOS4_DMC0_BASE @0x10400000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
@@ -221,7 +221,7 @@
bne 8b
/* DREX1 */
- ldr r0, =S5PC210_DMC1_BASE @0x10410000
+ ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
ldr r1, =0xe0000086
str r1, [r0, #0x1C] @DMC_PHYCONTROL1
diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c
index d9caca7..81ac8f6 100644
--- a/board/samsung/smdkv310/smdkv310.c
+++ b/board/samsung/smdkv310/smdkv310.c
@@ -29,8 +29,8 @@
#include <asm/arch/sromc.h>
DECLARE_GLOBAL_DATA_PTR;
-struct s5pc210_gpio_part1 *gpio1;
-struct s5pc210_gpio_part2 *gpio2;
+struct exynos4_gpio_part1 *gpio1;
+struct exynos4_gpio_part2 *gpio2;
static void smc9115_pre_init(void)
{
@@ -52,8 +52,8 @@
int board_init(void)
{
- gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
- gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+ gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
smc9115_pre_init();