S5PC2XX: Rename S5pc2XX to exynos
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15
based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15
based SoC's will be sub-classified as Exynos4 and Exynos5 respectively.
In order to better adapt and reuse code across various upcoming Samsung Exynos
based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in
this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix
are renamed as exynos4/EXYNOS4.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S
index ddca1e2..0eebbfc 100644
--- a/board/samsung/origen/lowlevel_init.S
+++ b/board/samsung/origen/lowlevel_init.S
@@ -1,5 +1,5 @@
/*
- * Lowlevel setup for ORIGEN board based on S5PV310
+ * Lowlevel setup for ORIGEN board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
@@ -43,11 +43,11 @@
/* r5 has always zero */
mov r5, #0
- ldr r7, =S5PC210_GPIO_PART1_BASE
- ldr r6, =S5PC210_GPIO_PART2_BASE
+ ldr r7, =EXYNOS4_GPIO_PART1_BASE
+ ldr r6, =EXYNOS4_GPIO_PART2_BASE
/* check reset status */
- ldr r0, =(S5PC210_POWER_BASE + INFORM1_OFFSET)
+ ldr r0, =(EXYNOS4_POWER_BASE + INFORM1_OFFSET)
ldr r1, [r0]
/* AFTR wakeup reset */
@@ -97,9 +97,9 @@
exit_wakeup:
/* Load return address and jump to kernel */
- ldr r0, =(S5PC210_POWER_BASE + INFORM0_OFFSET)
+ ldr r0, =(EXYNOS4_POWER_BASE + INFORM0_OFFSET)
- /* r1 = physical address of s5pc210_cpu_resume function */
+ /* r1 = physical address of exynos4210_cpu_resume function */
ldr r1, [r0]
/* Jump to kernel*/
@@ -113,7 +113,7 @@
*/
system_clock_init:
push {lr}
- ldr r0, =S5PC210_CLOCK_BASE
+ ldr r0, =EXYNOS4_CLOCK_BASE
/* APLL(1), MPLL(1), CORE(0), HPM(0) */
ldr r1, =CLK_SRC_CPU_VAL
@@ -290,13 +290,13 @@
/* setup UART0-UART3 GPIOs (part1) */
mov r0, r7
- ldr r1, =S5PC210_GPIO_A0_CON_VAL
- str r1, [r0, #S5PC210_GPIO_A0_CON_OFFSET]
- ldr r1, =S5PC210_GPIO_A1_CON_VAL
- str r1, [r0, #S5PC210_GPIO_A1_CON_OFFSET]
+ ldr r1, =EXYNOS4_GPIO_A0_CON_VAL
+ str r1, [r0, #EXYNOS4_GPIO_A0_CON_OFFSET]
+ ldr r1, =EXYNOS4_GPIO_A1_CON_VAL
+ str r1, [r0, #EXYNOS4_GPIO_A1_CON_OFFSET]
- ldr r0, =S5PC210_UART_BASE
- add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
+ ldr r0, =EXYNOS4_UART_BASE
+ add r0, r0, #EXYNOS4_DEFAULT_UART_OFFSET
ldr r1, =ULCON_VAL
str r1, [r0, #ULCON_OFFSET]
diff --git a/board/samsung/origen/mem_setup.S b/board/samsung/origen/mem_setup.S
index a798848..b49b193 100644
--- a/board/samsung/origen/mem_setup.S
+++ b/board/samsung/origen/mem_setup.S
@@ -1,5 +1,5 @@
/*
- * Memory setup for ORIGEN board based on S5PV310
+ * Memory setup for ORIGEN board based on EXYNOS4210
*
* Copyright (C) 2011 Samsung Electronics
*
@@ -38,7 +38,7 @@
str r1, [r0]
#ifdef SET_MIU
- ldr r0, =S5PC210_MIU_BASE
+ ldr r0, =EXYNOS4_MIU_BASE
/* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */
ldr r1, =0x20001507
str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET]
@@ -48,7 +48,7 @@
str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET]
#endif
/* DREX0 */
- ldr r0, =S5PC210_DMC0_BASE
+ ldr r0, =EXYNOS4_DMC0_BASE
/*
* DLL Parameter Setting:
@@ -229,7 +229,7 @@
bne 8b
/* DREX1 */
- ldr r0, =S5PC210_DMC1_BASE @0x10410000
+ ldr r0, =EXYNOS4_DMC1_BASE @0x10410000
/*
* DLL Parameter Setting:
@@ -410,11 +410,11 @@
bne 8b
/* turn on DREX0, DREX1 */
- ldr r0, =S5PC210_DMC0_BASE
+ ldr r0, =EXYNOS4_DMC0_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #DMC_CONCONTROL]
- ldr r0, =S5PC210_DMC1_BASE
+ ldr r0, =EXYNOS4_DMC1_BASE
ldr r1, =0x0FFF303a
str r1, [r0, #DMC_CONCONTROL]
diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c
index 8882646..638e7b1 100644
--- a/board/samsung/origen/origen.c
+++ b/board/samsung/origen/origen.c
@@ -27,13 +27,13 @@
#include <asm/arch/mmc.h>
DECLARE_GLOBAL_DATA_PTR;
-struct s5pc210_gpio_part1 *gpio1;
-struct s5pc210_gpio_part2 *gpio2;
+struct exynos4_gpio_part1 *gpio1;
+struct exynos4_gpio_part2 *gpio2;
int board_init(void)
{
- gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE;
- gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE;
+ gpio1 = (struct exynos4_gpio_part1 *) EXYNOS4_GPIO_PART1_BASE;
+ gpio2 = (struct exynos4_gpio_part2 *) EXYNOS4_GPIO_PART2_BASE;
gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
return 0;
diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h
index 63d85d8..d949ad2 100644
--- a/board/samsung/origen/origen_setup.h
+++ b/board/samsung/origen/origen_setup.h
@@ -98,8 +98,8 @@
#define INFORM1_OFFSET 0x804
/* GPIO Offsets for UART: GPIO Contol Register */
-#define S5PC210_GPIO_A0_CON_OFFSET 0x00
-#define S5PC210_GPIO_A1_CON_OFFSET 0x20
+#define EXYNOS4_GPIO_A0_CON_OFFSET 0x00
+#define EXYNOS4_GPIO_A1_CON_OFFSET 0x20
/* UART Register offsets */
#define ULCON_OFFSET 0x00
@@ -416,8 +416,8 @@
* UART GPIO_A0/GPIO_A1 Control Register Value
* 0x2: UART Function
*/
-#define S5PC210_GPIO_A0_CON_VAL 0x22222222
-#define S5PC210_GPIO_A1_CON_VAL 0x222222
+#define EXYNOS4_GPIO_A0_CON_VAL 0x22222222
+#define EXYNOS4_GPIO_A1_CON_VAL 0x222222
/* ULCON: UART Line Control Value 8N1 */
#define WORD_LEN_5_BIT 0x00