arm: socfpga: agilex5: Add MMU mapping region
MMU mapping regions were added for the second and third DDR memory banks.
Signed-off-by: Tingting Meng <tingting.meng@altera.com>
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
index b8e40d9a..1dc44ab 100644
--- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -58,6 +58,20 @@
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_INNER_SHARE,
}, {
+ /* MEM 30GB */
+ .virt = 0x880000000UL,
+ .phys = 0x880000000UL,
+ .size = 0x780000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
+ /* MEM 480GB */
+ .virt = 0x8800000000UL,
+ .phys = 0x8800000000UL,
+ .size = 0x7800000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
/* List terminator */
},
};