commit 40a8c35719fea54f5ea1cf1e6faf3df83fa655fb
author Simon Glass <sjg@chromium.org> Wed Nov 12 22:42:04 2014 -0700
committer Simon Glass <sjg@chromium.org> Fri Nov 21 07:24:12 2014 +0100
tree e4a3f61e5571d16f283863f6ca29e30f5a819a53
parent 588751a1ca7cc821d3604b67222f75b7f42aeecf

x86: Allow timer calibration to work on ivybridge

Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.

For this CPU we know the frequency, so add another special case for now.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

arch/x86/lib/tsc_timer.c

diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c
index f091c91..fb9afed 100644
--- a/arch/x86/lib/tsc_timer.c
+++ b/arch/x86/lib/tsc_timer.c
@@ -36,7 +36,8 @@
 struct freq_desc {
 	u8 x86_family;	/* CPU family */
 	u8 x86_model;	/* model */
-	u8 msr_plat;	/* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
+	/* 2: use 100MHz, 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
+	u8 msr_plat;
 	u32 freqs[MAX_NUM_FREQS];
 };
 
@@ -49,6 +50,8 @@
 	{ 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
 	/* VLV2 */
 	{ 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
+	/* Ivybridge */
+	{ 6, 0x3a, 2, { 0, 0, 0, 0, 0, 0, 0, 0 } },
 	/* ANN */
 	{ 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
 };
@@ -97,11 +100,18 @@
 	if (!ratio)
 		goto fail;
 
-	/* Get FSB FREQ ID */
-	rdmsr(MSR_FSB_FREQ, lo, hi);
-	freq_id = lo & 0x7;
-	freq = id_to_freq(cpu_index, freq_id);
-	debug("Resolved frequency ID: %u, frequency: %u KHz\n", freq_id, freq);
+	if (freq_desc_tables[cpu_index].msr_plat == 2) {
+		/* TODO: Figure out how best to deal with this */
+		freq = FREQ_100;
+		debug("Using frequency: %u KHz\n", freq);
+	} else {
+		/* Get FSB FREQ ID */
+		rdmsr(MSR_FSB_FREQ, lo, hi);
+		freq_id = lo & 0x7;
+		freq = id_to_freq(cpu_index, freq_id);
+		debug("Resolved frequency ID: %u, frequency: %u KHz\n",
+		      freq_id, freq);
+	}
 	if (!freq)
 		goto fail;
 
@@ -297,12 +307,12 @@
 		return gd->arch.tsc_mhz;
 
 	fast_calibrate = try_msr_calibrate_tsc();
-	if (fast_calibrate)
-		return fast_calibrate;
+	if (!fast_calibrate) {
 
-	fast_calibrate = quick_pit_calibrate();
-	if (!fast_calibrate)
-		panic("TSC frequency is ZERO");
+		fast_calibrate = quick_pit_calibrate();
+		if (!fast_calibrate)
+			panic("TSC frequency is ZERO");
+	}
 
 	gd->arch.tsc_mhz = fast_calibrate;
 	return fast_calibrate;