diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3368.c b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
index c1f692a..40cc846 100644
--- a/drivers/pinctrl/rockchip/pinctrl-rk3368.c
+++ b/drivers/pinctrl/rockchip/pinctrl-rk3368.c
@@ -79,10 +79,6 @@
 	if (bank->bank_num == 0) {
 		*regmap = priv->regmap_pmu;
 		*reg = RK3368_DRV_PMU_OFFSET;
-
-		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
-		*bit = pin_num % ROCKCHIP_DRV_PINS_PER_REG;
-		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
 	} else {
 		*regmap = priv->regmap_base;
 		*reg = RK3368_DRV_GRF_OFFSET;
@@ -90,11 +86,35 @@
 		/* correct the offset, as we're starting with the 2nd bank */
 		*reg -= 0x10;
 		*reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
-		*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+	}
 
-		*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
-		*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+	*reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
+	*bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
+	*bit *= ROCKCHIP_DRV_BITS_PER_PIN;
+}
+
+static int rk3368_set_drive(struct rockchip_pin_bank *bank,
+			    int pin_num, int strength)
+{
+	struct regmap *regmap;
+	int reg, ret;
+	u32 data;
+	u8 bit;
+	int type = bank->drv[pin_num / 8].drv_type;
+
+	rk3368_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ret = rockchip_translate_drive_value(type, strength);
+	if (ret < 0) {
+		debug("unsupported driver strength %d\n", strength);
+		return ret;
 	}
+
+	/* enable the write to the equivalent lower bits */
+	data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+	data |= (ret << bit);
+	ret = regmap_write(regmap, reg, data);
+
+	return ret;
 }
 
 static struct rockchip_pin_bank rk3368_pin_banks[] = {
@@ -117,7 +137,7 @@
 	.pmu_mux_offset		= 0x0,
 	.set_mux		= rk3368_set_mux,
 	.pull_calc_reg		= rk3368_calc_pull_reg_and_bit,
-	.drv_calc_reg		= rk3368_calc_drv_reg_and_bit,
+	.set_drive		= rk3368_set_drive,
 };
 
 static const struct udevice_id rk3368_pinctrl_ids[] = {