Merge branch '2022-10-31-broadcom-updates'
- Update / add a large number of Broadcom BCA SoCs.
diff --git a/MAINTAINERS b/MAINTAINERS
index 048db37..1cf99c1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -213,11 +213,26 @@
M: William Zhang <william.zhang@broadcom.com>
M: Kursad Oney <kursad.oney@broadcom.com>
M: Joel Peshkin <joel.peshkin@broadcom.com>
+M: Philippe Reynes <philippe.reynes@softathome.com>
S: Maintained
F: arch/arm/mach-bcmbca/
F: board/broadcom/bcmbca/
-F: configs/bcm947622_defconfig
-F: include/configs/bcm947622.h
+N: bcmbca
+N: bcm[9]?47622
+N: bcm[9]?4908
+N: bcm[9]?4912
+N: bcm[9]?63138
+N: bcm[9]?63146
+N: bcm[9]?63148
+N: bcm[9]?63158
+N: bcm[9]?63178
+N: bcm[9]?6756
+N: bcm[9]?6813
+N: bcm[9]?6846
+N: bcm[9]?6855
+N: bcm[9]?6856
+N: bcm[9]?6858
+N: bcm[9]?6878
ARM BROADCOM BCMSTB
M: Thomas Fitzsimmons <fitzsim@fitzsim.org>
@@ -495,7 +510,7 @@
F: drivers/reset/sti-reset.c
F: drivers/serial/serial_sti_asc.c
F: drivers/sysreset/sysreset_sti.c
-F: drivers/timer/sti-timer.c
+F: drivers/timer/arm_global_timer.c
F: drivers/usb/host/dwc3-sti-glue.c
F: include/dwc3-sti-glue.h
F: include/dt-bindings/clock/stih407-clks.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6fb39e1..8bc9aaf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -678,31 +678,6 @@
imply CMD_DM
imply FAT_WRITE
-config ARCH_BCM63158
- bool "Broadcom BCM63158 family"
- select DM
- select OF_CONTROL
- imply CMD_DM
-
-config ARCH_BCM6753
- bool "Broadcom BCM6753 family"
- select CPU_V7A
- select DM
- select OF_CONTROL
- imply CMD_DM
-
-config ARCH_BCM68360
- bool "Broadcom BCM68360 family"
- select DM
- select OF_CONTROL
- imply CMD_DM
-
-config ARCH_BCM6858
- bool "Broadcom BCM6858 family"
- select DM
- select OF_CONTROL
- imply CMD_DM
-
config ARCH_BCMSTB
bool "Broadcom BCM7XXX family"
select CPU_V7A
@@ -719,6 +694,7 @@
bool "Broadcom broadband chip family"
select DM
select OF_CONTROL
+ imply CMD_DM
config TARGET_VEXPRESS_CA9X4
bool "Support vexpress_ca9x4"
@@ -2335,10 +2311,6 @@
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
-source "board/broadcom/bcm963158/Kconfig"
-source "board/broadcom/bcm96753ref/Kconfig"
-source "board/broadcom/bcm968360bg/Kconfig"
-source "board/broadcom/bcm968580xref/Kconfig"
source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/eets/pdu001/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5c7cdc9..7918387 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1164,24 +1164,43 @@
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-4-b.dtb
-dtb-$(CONFIG_ARCH_BCM63158) += \
- bcm963158.dtb
-
-dtb-$(CONFIG_ARCH_BCM68360) += \
- bcm968360bg.dtb
-
-dtb-$(CONFIG_ARCH_BCM6753) += \
- bcm96753ref.dtb
-
-dtb-$(CONFIG_ARCH_BCM6858) += \
- bcm968580xref.dtb
-
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
dtb-$(CONFIG_BCM47622) += \
bcm947622.dtb
+dtb-$(CONFIG_BCM4908) += \
+ bcm94908.dtb
+dtb-$(CONFIG_BCM4912) += \
+ bcm94912.dtb
+dtb-$(CONFIG_BCM63138) += \
+ bcm963138.dtb
+dtb-$(CONFIG_BCM63146) += \
+ bcm963146.dtb
+dtb-$(CONFIG_BCM63148) += \
+ bcm963148.dtb
+dtb-$(CONFIG_BCM63158) += \
+ bcm963158.dtb
+dtb-$(CONFIG_BCM63178) += \
+ bcm963178.dtb
+dtb-$(CONFIG_BCM6756) += \
+ bcm96756.dtb
+dtb-$(CONFIG_BCM6813) += \
+ bcm96813.dtb
+dtb-$(CONFIG_BCM6846) += \
+ bcm96846.dtb
+dtb-$(CONFIG_BCM6855) += \
+ bcm96855.dtb \
+ bcm96753ref.dtb
+dtb-$(CONFIG_BCM6856) += \
+ bcm96856.dtb \
+ bcm968360bg.dtb
+dtb-$(CONFIG_BCM6858) += \
+ bcm96858.dtb \
+ bcm968580xref.dtb
+dtb-$(CONFIG_BCM6878) += \
+ bcm96878.dtb
dtb-$(CONFIG_ASPEED_AST2500) += ast2500-evb.dtb
dtb-$(CONFIG_ASPEED_AST2600) += ast2600-evb.dtb
diff --git a/arch/arm/dts/bcm4908.dtsi b/arch/arm/dts/bcm4908.dtsi
new file mode 100644
index 0000000..0be5cfe
--- /dev/null
+++ b/arch/arm/dts/bcm4908.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ compatible = "brcm,bcm4908", "brcm,bcmbca";
+
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b53";
+ reg = <0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b53";
+ reg = <0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b53";
+ reg = <0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b53";
+ reg = <0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x81000000 0x4000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ clocks {
+ periph_clk: periph_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "periph";
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0xff800000 0x3000>;
+
+ uart0: serial@640 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x640 0x18>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+
+ };
+};
diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi
new file mode 100644
index 0000000..3d016c2
--- /dev/null
+++ b/arch/arm/dts/bcm4912.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "brcm,bcm4912", "brcm,bcmbca";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ B53_0: cpu@0 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B53_1: cpu@1 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B53_2: cpu@2 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B53_3: cpu@3 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&B53_0>, <&B53_1>,
+ <&B53_2>, <&B53_3>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi
new file mode 100644
index 0000000..42b442a
--- /dev/null
+++ b/arch/arm/dts/bcm63138.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom BCM63138 DSL SoCs Device Tree
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm63138", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <0>;
+ enable-method = "brcm,bcm63138";
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <&L2>;
+ reg = <1>;
+ enable-method = "brcm,bcm63138";
+ };
+ };
+
+ clocks {
+ /* UBUS peripheral clock */
+ periph_clk: periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <50000000>;
+ clock-output-names = "periph";
+ };
+
+ /* peripheral clock for system timer */
+ axi_clk: axi_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /* APB bus clock */
+ apb_clk: apb_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&armpll>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ /* ARM bus */
+ axi@80000000 {
+ compatible = "simple-bus";
+ ranges = <0 0x80000000 0x784000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ L2: cache-controller@1d000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1d000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <524288>;
+ cache-sets = <1024>;
+ cache-line-size = <32>;
+ interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ scu: scu@1e000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x1e000 0x100>;
+ };
+
+ gic: interrupt-controller@1f000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x1f000 0x1000
+ 0x1e100 0x100>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ };
+
+ global_timer: timer@1e200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x1e200 0x20>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&axi_clk>;
+ };
+
+ local_timer: local-timer@1e600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x1e600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&axi_clk>;
+ };
+
+ twd_watchdog: watchdog@1e620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x1e620 0x20>;
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ armpll: armpll@20000 {
+ #clock-cells = <0>;
+ compatible = "brcm,bcm63138-armpll";
+ clocks = <&periph_clk>;
+ reg = <0x20000 0xf00>;
+ };
+ };
+
+ /* Legacy UBUS base */
+ bus@fffe8000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xfffe8000 0x8000>;
+
+ timer0: timer@80 {
+ compatible = "brcm,bcmbca-periph-timer";
+ reg = <0x80 0x28>;
+ clocks = <&periph_clk>;
+ };
+
+ uart0: serial@600 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x600 0x20>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi
new file mode 100644
index 0000000..04de96b
--- /dev/null
+++ b/arch/arm/dts/bcm63146.dtsi
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "brcm,bcm63146", "brcm,bcmbca";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ B53_0: cpu@0 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B53_1: cpu@1 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&B53_0>, <&B53_1>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm63148.dtsi b/arch/arm/dts/bcm63148.dtsi
new file mode 100644
index 0000000..df5307b
--- /dev/null
+++ b/arch/arm/dts/bcm63148.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm63148", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ B15_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b15";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B15_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b15";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a15-pmu";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&B15_0>, <&B15_1>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@80030000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x80030000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xfffe8000 0x8000>;
+
+ uart0: serial@600 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x600 0x20>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm63158.dtsi b/arch/arm/dts/bcm63158.dtsi
index 7dd2858..8b179ba 100644
--- a/arch/arm/dts/bcm63158.dtsi
+++ b/arch/arm/dts/bcm63158.dtsi
@@ -1,122 +1,167 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ * Copyright 2022 Broadcom Ltd.
*/
-#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
- compatible = "brcm,bcm63158";
+ compatible = "brcm,bcm63158", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- spi0 = &hsspi;
- };
+ interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_0: cpu@0 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_1: cpu@1 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu2: cpu@2 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_2: cpu@2 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu3: cpu@3 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_3: cpu@3 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- l2: l2-cache0 {
+ L2_0: l2-cache0 {
compatible = "cache";
- u-boot,dm-pre-reloc;
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&B53_0>, <&B53_1>,
+ <&B53_2>, <&B53_3>;
+ };
+
clocks {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
u-boot,dm-pre-reloc;
-
- periph_osc: periph-osc {
+ periph_clk: periph-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
- clock-frequency = <0xbebc200>;
- u-boot,dm-pre-reloc;
+ clock-frequency = <200000000>;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
- clocks = <&periph_osc>;
+ clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
- refclk50mhz: refclk50mhz {
- compatible = "fixed-clock";
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ wdt_clk: wdt-clk {
+ compatible = "fixed-factor-clock";
#clock-cells = <0>;
- clock-frequency = <50000000>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
};
- ubus {
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
u-boot,dm-pre-reloc;
- uart0: serial@ff812000 {
+ uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
- reg = <0x0 0xff812000 0x0 0x1000>;
- clock = <50000000>;
-
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
- leds: led-controller@ff800800 {
+ leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
- reg = <0x0 0xff800800 0x0 0xe4>;
+ reg = <0x800 0xe4>;
status = "disabled";
};
- wdt1: watchdog@ff800480 {
+ wdt1: watchdog@480 {
compatible = "brcm,bcm6345-wdt";
- reg = <0x0 0xff800480 0x0 0x14>;
- clocks = <&refclk50mhz>;
+ reg = <0x480 0x14>;
+ clocks = <&wdt_clk>;
};
- wdt2: watchdog@ff8004c0 {
+ wdt2: watchdog@4c0 {
compatible = "brcm,bcm6345-wdt";
- reg = <0x0 0xff8004c0 0x0 0x14>;
- clocks = <&refclk50mhz>;
+ reg = <0x4c0 0x14>;
+ clocks = <&wdt_clk>;
};
wdt-reboot {
@@ -124,91 +169,91 @@
wdt = <&wdt1>;
};
- gpio0: gpio-controller@0xff800500 {
+ gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800500 0x0 0x4>,
- <0x0 0xff800520 0x0 0x4>;
+ reg = <0x500 0x4>,
+ <0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio1: gpio-controller@0xff800504 {
+ gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800504 0x0 0x4>,
- <0x0 0xff800524 0x0 0x4>;
+ reg = <0x504 0x4>,
+ <0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio2: gpio-controller@0xff800508 {
+ gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800508 0x0 0x4>,
- <0x0 0xff800528 0x0 0x4>;
+ reg = <0x508 0x4>,
+ <0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio3: gpio-controller@0xff80050c {
+ gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff80050c 0x0 0x4>,
- <0x0 0xff80052c 0x0 0x4>;
+ reg = <0x50c 0x4>,
+ <0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio4: gpio-controller@0xff800510 {
+ gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800510 0x0 0x4>,
- <0x0 0xff800530 0x0 0x4>;
+ reg = <0x510 0x4>,
+ <0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio5: gpio-controller@0xff800514 {
+ gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800514 0x0 0x4>,
- <0x0 0xff800534 0x0 0x4>;
+ reg = <0x514 0x4>,
+ <0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio6: gpio-controller@0xff800518 {
+ gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800518 0x0 0x4>,
- <0x0 0xff800538 0x0 0x4>;
+ reg = <0x518 0x4>,
+ <0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio7: gpio-controller@0xff80051c {
+ gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff80051c 0x0 0x4>,
- <0x0 0xff80053c 0x0 0x4>;
+ reg = <0x51c 0x4>,
+ <0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- hsspi: spi-controller@ff801000 {
+ hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x0 0xff801000 0x0 0x600>;
+ reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
@@ -217,14 +262,14 @@
status = "disabled";
};
- nand: nand-controller@ff801800 {
+ nand: nand-controller@1800 {
compatible = "brcm,nand-bcm63158",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
- reg = <0x0 0xff801800 0x0 0x180>,
- <0x0 0xff802000 0x0 0x10>,
- <0x0 0xff801c00 0x0 0x200>;
+ reg = <0x1800 0x180>,
+ <0x2000 0x10>,
+ <0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
diff --git a/arch/arm/dts/bcm63178.dtsi b/arch/arm/dts/bcm63178.dtsi
new file mode 100644
index 0000000..cbd094d
--- /dev/null
+++ b/arch/arm/dts/bcm63178.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm63178", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>,
+ <&CA7_2>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm6753.dtsi b/arch/arm/dts/bcm6753.dtsi
deleted file mode 100644
index e88ab09..0000000
--- a/arch/arm/dts/bcm6753.dtsi
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include "skeleton.dtsi"
-
-/ {
- compatible = "brcm,bcm6753";
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- u-boot,dm-pre-reloc;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0x0>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0x1>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- cpu2: cpu@2 {
- compatible = "arm,cortex-a7";
- device_type = "cpu";
- reg = <0x2>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- u-boot,dm-pre-reloc;
- };
- };
-
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- u-boot,dm-pre-reloc;
-
- periph_osc: periph-osc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- u-boot,dm-pre-reloc;
- };
-
- hsspi_pll: hsspi-pll {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clocks = <&periph_osc>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- refclk50mhz: refclk50mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- };
- };
-
- ubus {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- u-boot,dm-pre-reloc;
-
- uart0: serial@ff812000 {
- compatible = "arm,pl011", "arm,primecell";
- reg = <0xff812000 0x1000>;
- clock = <50000000>;
-
- status = "disabled";
- };
-
- wdt1: watchdog@ff800480 {
- compatible = "brcm,bcm6345-wdt";
- reg = <0xff800480 0x14>;
- clocks = <&refclk50mhz>;
- };
-
- wdt2: watchdog@ff8004c0 {
- compatible = "brcm,bcm6345-wdt";
- reg = <0xff8004c0 0x14>;
- clocks = <&refclk50mhz>;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <&wdt1>;
- };
-
- gpio0: gpio-controller@0xff800500 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0xff800500 0x4>,
- <0xff800520 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio1: gpio-controller@0xff800504 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0xff800504 0x4>,
- <0xff800524 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio2: gpio-controller@0xff800508 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0xff800508 0x4>,
- <0xff800528 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio3: gpio-controller@0xff80050c {
- compatible = "brcm,bcm6345-gpio";
- reg = <0xff80050c 0x4>,
- <0xff80052c 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio4: gpio-controller@0xff800510 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0xff800510 0x4>,
- <0xff800530 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio5: gpio-controller@0xff800514 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0xff800514 0x4>,
- <0xff800534 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio6: gpio-controller@0xff800518 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0xff800518 0x4>,
- <0xff800538 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio7: gpio-controller@0xff80051c {
- compatible = "brcm,bcm6345-gpio";
- reg = <0xff80051c 0x4>,
- <0xff80053c 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- nand: nand-controller@ff801800 {
- compatible = "brcm,nand-bcm6753",
- "brcm,brcmnand-v5.0",
- "brcm,brcmnand";
- reg-names = "nand", "nand-int-base", "nand-cache";
- reg = <0xff801800 0x180>,
- <0xff802000 0x10>,
- <0xff801c00 0x200>;
- parameter-page-big-endian = <0>;
-
- status = "disabled";
- };
-
- leds: led-controller@ff803000 {
- compatible = "brcm,bcm6753-leds";
- reg = <0xff803000 0x3480>;
-
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/bcm6756.dtsi b/arch/arm/dts/bcm6756.dtsi
new file mode 100644
index 0000000..ce1b59f
--- /dev/null
+++ b/arch/arm/dts/bcm6756.dtsi
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm6756", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>,
+ <&CA7_2>, <&CA7_3>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm6813.dtsi b/arch/arm/dts/bcm6813.dtsi
new file mode 100644
index 0000000..c3e6197
--- /dev/null
+++ b/arch/arm/dts/bcm6813.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "brcm,bcm6813", "brcm,bcmbca";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ B53_0: cpu@0 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B53_1: cpu@1 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B53_2: cpu@2 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B53_3: cpu@3 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&B53_0>, <&B53_1>,
+ <&B53_2>, <&B53_3>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm68360.dtsi b/arch/arm/dts/bcm68360.dtsi
deleted file mode 100644
index 7bbe207..0000000
--- a/arch/arm/dts/bcm68360.dtsi
+++ /dev/null
@@ -1,217 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include "skeleton64.dtsi"
-
-/ {
- compatible = "brcm,bcm68360";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- spi0 = &hsspi;
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
- u-boot,dm-pre-reloc;
-
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
- device_type = "cpu";
- reg = <0x0 0x0>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
- device_type = "cpu";
- reg = <0x0 0x1>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
- };
-
- l2: l2-cache0 {
- compatible = "cache";
- u-boot,dm-pre-reloc;
- };
- };
-
- clocks {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- u-boot,dm-pre-reloc;
-
- periph_osc: periph-osc {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <200000000>;
- u-boot,dm-pre-reloc;
- };
-
- hsspi_pll: hsspi-pll {
- compatible = "fixed-factor-clock";
- #clock-cells = <0>;
- clocks = <&periph_osc>;
- clock-mult = <2>;
- clock-div = <1>;
- };
-
- refclk50mhz: refclk50mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <50000000>;
- };
- };
-
- ubus {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- u-boot,dm-pre-reloc;
-
- wdt1: watchdog@ff800480 {
- compatible = "brcm,bcm6345-wdt";
- reg = <0x0 0xff800480 0x0 0x14>;
- clocks = <&refclk50mhz>;
- };
-
- wdt2: watchdog@ff8004c0 {
- compatible = "brcm,bcm6345-wdt";
- reg = <0x0 0xff8004c0 0x0 0x14>;
- clocks = <&refclk50mhz>;
- };
-
- wdt-reboot {
- compatible = "wdt-reboot";
- wdt = <&wdt1>;
- };
-
- uart0: serial@ff800640 {
- compatible = "brcm,bcm6345-uart";
- reg = <0x0 0xff800640 0x0 0x18>;
- clocks = <&periph_osc>;
-
- status = "disabled";
- };
-
- leds: led-controller@ff800800 {
- compatible = "brcm,bcm6858-leds";
- reg = <0x0 0xff800800 0x0 0xe4>;
-
- status = "disabled";
- };
-
- gpio0: gpio-controller@0xff800500 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800500 0x0 0x4>,
- <0x0 0xff800520 0x0 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio1: gpio-controller@0xff800504 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800504 0x0 0x4>,
- <0x0 0xff800524 0x0 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio2: gpio-controller@0xff800508 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800508 0x0 0x4>,
- <0x0 0xff800528 0x0 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio3: gpio-controller@0xff80050c {
- compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff80050c 0x0 0x4>,
- <0x0 0xff80052c 0x0 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio4: gpio-controller@0xff800510 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800510 0x0 0x4>,
- <0x0 0xff800530 0x0 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio5: gpio-controller@0xff800514 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800514 0x0 0x4>,
- <0x0 0xff800534 0x0 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio6: gpio-controller@0xff800518 {
- compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800518 0x0 0x4>,
- <0x0 0xff800538 0x0 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- gpio7: gpio-controller@0xff80051c {
- compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff80051c 0x0 0x4>,
- <0x0 0xff80053c 0x0 0x4>;
- gpio-controller;
- #gpio-cells = <2>;
-
- status = "disabled";
- };
-
- hsspi: spi-controller@ff801000 {
- compatible = "brcm,bcm6328-hsspi";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0xff801000 0x0 0x600>;
- clocks = <&hsspi_pll>, <&hsspi_pll>;
- clock-names = "hsspi", "pll";
- spi-max-frequency = <100000000>;
- num-cs = <8>;
-
- status = "disabled";
- };
-
- nand: nand-controller@ff801800 {
- compatible = "brcm,nand-bcm68360",
- "brcm,brcmnand-v5.0",
- "brcm,brcmnand";
- reg-names = "nand", "nand-int-base", "nand-cache";
- reg = <0x0 0xff801800 0x0 0x180>,
- <0x0 0xff802000 0x0 0x10>,
- <0x0 0xff801c00 0x0 0x200>;
- parameter-page-big-endian = <0>;
-
- status = "disabled";
- };
- };
-};
diff --git a/arch/arm/dts/bcm6846.dtsi b/arch/arm/dts/bcm6846.dtsi
new file mode 100644
index 0000000..8aa47a2
--- /dev/null
+++ b/arch/arm/dts/bcm6846.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm6846", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ uart0: serial@640 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x640 0x1b>;
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm6855.dtsi b/arch/arm/dts/bcm6855.dtsi
new file mode 100644
index 0000000..05e0a4e
--- /dev/null
+++ b/arch/arm/dts/bcm6855.dtsi
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm6855", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>, <&CA7_2>;
+ };
+
+ clocks: clocks {
+ u-boot,dm-pre-reloc;
+
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ wdt_clk: wdt-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(3) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+ u-boot,dm-pre-reloc;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+
+ wdt1: watchdog@480 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x480 0x14>;
+ clocks = <&wdt_clk>;
+ };
+
+ wdt2: watchdog@4c0 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x4c0 0x14>;
+ clocks = <&wdt_clk>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt1>;
+ };
+
+ gpio0: gpio-controller@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x500 0x4>,
+ <0x520 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@504 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x504 0x4>,
+ <0x524 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio2: gpio-controller@508 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x508 0x4>,
+ <0x528 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio3: gpio-controller@50c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x50c 0x4>,
+ <0x52c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio4: gpio-controller@510 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x510 0x4>,
+ <0x530 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio5: gpio-controller@514 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x514 0x4>,
+ <0x534 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio6: gpio-controller@518 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x518 0x4>,
+ <0x538 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio7: gpio-controller@51c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x51c 0x4>,
+ <0x53c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ nand: nand-controller@1800 {
+ compatible = "brcm,nand-bcm6753",
+ "brcm,brcmnand-v5.0",
+ "brcm,brcmnand";
+ reg-names = "nand", "nand-int-base", "nand-cache";
+ reg = <0x1800 0x180>,
+ <0x2000 0x10>,
+ <0x1c00 0x200>;
+ parameter-page-big-endian = <0>;
+
+ status = "disabled";
+ };
+
+ leds: led-controller@3000 {
+ compatible = "brcm,bcm6753-leds";
+ reg = <0x3000 0x3480>;
+
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm6856.dtsi b/arch/arm/dts/bcm6856.dtsi
new file mode 100644
index 0000000..99185ab
--- /dev/null
+++ b/arch/arm/dts/bcm6856.dtsi
@@ -0,0 +1,253 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "brcm,bcm6856", "brcm,bcmbca";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ B53_0: cpu@0 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ B53_1: cpu@1 {
+ compatible = "brcm,brahma-b53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&B53_0>, <&B53_1>;
+ };
+
+ clocks: clocks {
+ u-boot,dm-pre-reloc;
+
+ periph_clk:periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-mult = <2>;
+ clock-div = <1>;
+ };
+
+ wdt_clk: wdt-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>, /* GICD */
+ <0x2000 0x2000>, /* GICC */
+ <0x4000 0x2000>, /* GICH */
+ <0x6000 0x2000>; /* GICV */
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
+ u-boot,dm-pre-reloc;
+
+ uart0: serial@640 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x640 0x18>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+
+ wdt1: watchdog@480 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x480 0x14>;
+ clocks = <&wdt_clk>;
+ };
+
+ wdt2: watchdog@4c0 {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0x4c0 0x14>;
+ clocks = <&wdt_clk>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt1>;
+ };
+
+ leds: led-controller@800 {
+ compatible = "brcm,bcm6858-leds";
+ reg = <0x800 0xe4>;
+
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller@500 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x500 0x4>,
+ <0x520 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller@504 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x504 0x4>,
+ <0x524 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio2: gpio-controller@508 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x508 0x4>,
+ <0x528 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio3: gpio-controller@50c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x50c 0x4>,
+ <0x52c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio4: gpio-controller@510 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x510 0x4>,
+ <0x530 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio5: gpio-controller@514 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x514 0x4>,
+ <0x534 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio6: gpio-controller@518 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x518 0x4>,
+ <0x538 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpio7: gpio-controller@51c {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0x51c 0x4>,
+ <0x53c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ hsspi: spi-controller@1000 {
+ compatible = "brcm,bcm6328-hsspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1000 0x600>;
+ clocks = <&hsspi_pll>, <&hsspi_pll>;
+ clock-names = "hsspi", "pll";
+ spi-max-frequency = <100000000>;
+ num-cs = <8>;
+
+ status = "disabled";
+ };
+
+ nand: nand-controller@1800 {
+ compatible = "brcm,nand-bcm68360",
+ "brcm,brcmnand-v5.0",
+ "brcm,brcmnand";
+ reg-names = "nand", "nand-int-base", "nand-cache";
+ reg = <0x1800 0x180>,
+ <0x2000 0x10>,
+ <0x1c00 0x200>;
+ parameter-page-big-endian = <0>;
+
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm6858.dtsi b/arch/arm/dts/bcm6858.dtsi
index 0222562..19c4dd6 100644
--- a/arch/arm/dts/bcm6858.dtsi
+++ b/arch/arm/dts/bcm6858.dtsi
@@ -1,122 +1,161 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
+ * Copyright 2022 Broadcom Ltd.
*/
-#include "skeleton64.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
- compatible = "brcm,bcm6858";
+ compatible = "brcm,bcm6858", "brcm,bcmbca";
#address-cells = <2>;
#size-cells = <2>;
- aliases {
- spi0 = &hsspi;
- };
+ interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
- cpu0: cpu@0 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_0: cpu@0 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x0>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu1: cpu@1 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_1: cpu@1 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x1>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu2: cpu@2 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_2: cpu@2 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x2>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- cpu3: cpu@3 {
- compatible = "arm,cortex-a53", "arm,armv8";
+ B53_3: cpu@3 {
+ compatible = "brcm,brahma-b53";
device_type = "cpu";
reg = <0x0 0x3>;
- next-level-cache = <&l2>;
- u-boot,dm-pre-reloc;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
};
- l2: l2-cache0 {
+ L2_0: l2-cache0 {
compatible = "cache";
- u-boot,dm-pre-reloc;
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu: pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&B53_0>, <&B53_1>,
+ <&B53_2>, <&B53_3>;
+ };
+
clocks {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
u-boot,dm-pre-reloc;
- periph_osc: periph-osc {
+ periph_clk: periph_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
- u-boot,dm-pre-reloc;
};
hsspi_pll: hsspi-pll {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
- clocks = <&periph_osc>;
+ clocks = <&periph_clk>;
clock-mult = <2>;
clock-div = <1>;
};
- refclk50mhz: refclk50mhz {
- compatible = "fixed-clock";
+ wdt_clk: wdt-clk {
+ compatible = "fixed-factor-clock";
#clock-cells = <0>;
- clock-frequency = <50000000>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
};
};
- ubus {
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>, /* GICD */
+ <0x2000 0x2000>, /* GICC */
+ <0x4000 0x2000>, /* GICH */
+ <0x6000 0x2000>; /* GICV */
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xff800000 0x800000>;
u-boot,dm-pre-reloc;
- uart0: serial@ff800640 {
+ uart0: serial@640 {
compatible = "brcm,bcm6345-uart";
- reg = <0x0 0xff800640 0x0 0x18>;
- clocks = <&periph_osc>;
-
+ reg = <0x640 0x18>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
status = "disabled";
};
- leds: led-controller@ff800800 {
+ leds: led-controller@800 {
compatible = "brcm,bcm6858-leds";
- reg = <0x0 0xff800800 0x0 0xe4>;
+ reg = <0x800 0xe4>;
status = "disabled";
};
- wdt1: watchdog@ff802780 {
+ wdt1: watchdog@2780 {
compatible = "brcm,bcm6345-wdt";
- reg = <0x0 0xff802780 0x0 0x14>;
- clocks = <&refclk50mhz>;
+ reg = <0x2780 0x14>;
+ clocks = <&wdt_clk>;
};
- wdt2: watchdog@ff8027c0 {
+ wdt2: watchdog@27c0 {
compatible = "brcm,bcm6345-wdt";
- reg = <0x0 0xff8027c0 0x0 0x14>;
- clocks = <&refclk50mhz>;
+ reg = <0x27c0 0x14>;
+ clocks = <&wdt_clk>;
};
wdt-reboot {
@@ -124,91 +163,91 @@
wdt = <&wdt1>;
};
- gpio0: gpio-controller@0xff800500 {
+ gpio0: gpio-controller@500 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800500 0x0 0x4>,
- <0x0 0xff800520 0x0 0x4>;
+ reg = <0x500 0x4>,
+ <0x520 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio1: gpio-controller@0xff800504 {
+ gpio1: gpio-controller@504 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800504 0x0 0x4>,
- <0x0 0xff800524 0x0 0x4>;
+ reg = <0x504 0x4>,
+ <0x524 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio2: gpio-controller@0xff800508 {
+ gpio2: gpio-controller@508 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800508 0x0 0x4>,
- <0x0 0xff800528 0x0 0x4>;
+ reg = <0x508 0x4>,
+ <0x528 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio3: gpio-controller@0xff80050c {
+ gpio3: gpio-controller@50c {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff80050c 0x0 0x4>,
- <0x0 0xff80052c 0x0 0x4>;
+ reg = <0x50c 0x4>,
+ <0x52c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio4: gpio-controller@0xff800510 {
+ gpio4: gpio-controller@510 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800510 0x0 0x4>,
- <0x0 0xff800530 0x0 0x4>;
+ reg = <0x510 0x4>,
+ <0x530 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio5: gpio-controller@0xff800514 {
+ gpio5: gpio-controller@514 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800514 0x0 0x4>,
- <0x0 0xff800534 0x0 0x4>;
+ reg = <0x514 0x4>,
+ <0x534 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio6: gpio-controller@0xff800518 {
+ gpio6: gpio-controller@518 {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff800518 0x0 0x4>,
- <0x0 0xff800538 0x0 0x4>;
+ reg = <0x518 0x4>,
+ <0x538 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- gpio7: gpio-controller@0xff80051c {
+ gpio7: gpio-controller@51c {
compatible = "brcm,bcm6345-gpio";
- reg = <0x0 0xff80051c 0x0 0x4>,
- <0x0 0xff80053c 0x0 0x4>;
+ reg = <0x51c 0x4>,
+ <0x53c 0x4>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
- hsspi: spi-controller@ff801000 {
+ hsspi: spi-controller@1000 {
compatible = "brcm,bcm6328-hsspi";
#address-cells = <1>;
#size-cells = <0>;
- reg = <0x0 0xff801000 0x0 0x600>;
+ reg = <0x1000 0x600>;
clocks = <&hsspi_pll>, <&hsspi_pll>;
clock-names = "hsspi", "pll";
spi-max-frequency = <100000000>;
@@ -217,14 +256,14 @@
status = "disabled";
};
- nand: nand-controller@ff801800 {
+ nand: nand-controller@1800 {
compatible = "brcm,nand-bcm6858",
"brcm,brcmnand-v5.0",
"brcm,brcmnand";
reg-names = "nand", "nand-int-base", "nand-cache";
- reg = <0x0 0xff801800 0x0 0x180>,
- <0x0 0xff802000 0x0 0x10>,
- <0x0 0xff801c00 0x0 0x200>;
+ reg = <0x1800 0x180>,
+ <0x2000 0x10>,
+ <0x1c00 0x200>;
parameter-page-big-endian = <0>;
status = "disabled";
diff --git a/arch/arm/dts/bcm6878.dtsi b/arch/arm/dts/bcm6878.dtsi
new file mode 100644
index 0000000..1e8b5fa
--- /dev/null
+++ b/arch/arm/dts/bcm6878.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "brcm,bcm6878", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <&gic>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CA7_0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ CA7_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ next-level-cache = <&L2_0>;
+ enable-method = "psci";
+ };
+
+ L2_0: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ pmu: pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&CA7_0>, <&CA7_1>;
+ };
+
+ clocks: clocks {
+ periph_clk: periph-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>;
+ };
+ uart_clk: uart-clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&periph_clk>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ axi@81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x81000000 0x8000>;
+
+ gic: interrupt-controller@1000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>,
+ <0x4000 0x2000>,
+ <0x6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ bus@ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff800000 0x800000>;
+
+ uart0: serial@12000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x12000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&uart_clk>, <&uart_clk>;
+ clock-names = "uartclk", "apb_pclk";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/bcm94908.dts b/arch/arm/dts/bcm94908.dts
new file mode 100644
index 0000000..fcbd3c4
--- /dev/null
+++ b/arch/arm/dts/bcm94908.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm4908.dtsi"
+
+/ {
+ model = "Broadcom BCM94908 Reference Board";
+ compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm94912.dts b/arch/arm/dts/bcm94912.dts
new file mode 100644
index 0000000..a3623e6
--- /dev/null
+++ b/arch/arm/dts/bcm94912.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm4912.dtsi"
+
+/ {
+ model = "Broadcom BCM94912 Reference Board";
+ compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm963138.dts b/arch/arm/dts/bcm963138.dts
new file mode 100644
index 0000000..6158a87
--- /dev/null
+++ b/arch/arm/dts/bcm963138.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63138.dtsi"
+
+/ {
+ model = "Broadcom BCM963138 Reference Board";
+ compatible = "brcm,bcm963138", "brcm,bcm63138", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm963146.dts b/arch/arm/dts/bcm963146.dts
new file mode 100644
index 0000000..e39f1e6
--- /dev/null
+++ b/arch/arm/dts/bcm963146.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63146.dtsi"
+
+/ {
+ model = "Broadcom BCM963146 Reference Board";
+ compatible = "brcm,bcm963146", "brcm,bcm63146", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm963148.dts b/arch/arm/dts/bcm963148.dts
new file mode 100644
index 0000000..98f6a6d
--- /dev/null
+++ b/arch/arm/dts/bcm963148.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63148.dtsi"
+
+/ {
+ model = "Broadcom BCM963148 Reference Board";
+ compatible = "brcm,bcm963148", "brcm,bcm63148", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm963158.dts b/arch/arm/dts/bcm963158.dts
index c2bdd33..eba07e0 100644
--- a/arch/arm/dts/bcm963158.dts
+++ b/arch/arm/dts/bcm963158.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
+ * Copyright 2022 Broadcom Ltd.
*/
/dts-v1/;
@@ -8,8 +8,8 @@
#include "bcm63158.dtsi"
/ {
- model = "Broadcom bcm963158";
- compatible = "broadcom,bcm963158", "brcm,bcm63158";
+ model = "Broadcom BCM963158 Reference Board";
+ compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
aliases {
serial0 = &uart0;
@@ -19,121 +19,12 @@
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
- reg = <0x0 0x0 0x0 0x40000000>;
+ reg = <0x0 0x0 0x0 0x08000000>;
};
};
&uart0 {
- u-boot,dm-pre-reloc;
status = "okay";
};
-
-&gpio0 {
- status = "okay";
-};
-
-&gpio1 {
- status = "okay";
-};
-
-&gpio2 {
- status = "okay";
-};
-
-&gpio3 {
- status = "okay";
-};
-
-&gpio4 {
- status = "okay";
-};
-
-&gpio5 {
- status = "okay";
-};
-
-&gpio6 {
- status = "okay";
-};
-
-&gpio7 {
- status = "okay";
-};
-
-&nand {
- status = "okay";
- write-protect = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- nandcs@0 {
- compatible = "brcm,nandcs";
- reg = <0>;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- brcm,nand-oob-sector-size = <16>;
- };
-};
-
-&leds {
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
- brcm,serial-led-en-pol;
- brcm,serial-led-data-ppol;
-
- led@16 {
- reg = <16>;
- label = "red:dsl2";
- };
-
- led@17 {
- reg = <17>;
- label = "green:dsl1";
- };
-
- led@18 {
- reg = <18>;
- label = "green:fxs2";
- };
-
- led@19 {
- reg = <19>;
- label = "green:fxs1";
- };
-
- led@26 {
- reg = <26>;
- label = "green:wan1_act";
- };
-
- led@27 {
- reg = <27>;
- label = "green:wps";
- };
-
- led@28 {
- reg = <28>;
- active-low;
- label = "green:aggregate_act";
- };
-
- led@29 {
- reg = <29>;
- label = "green:aggregate_link";
- };
-};
-
-&hsspi {
- status = "okay";
-
- flash: mt25@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <25000000>;
- };
-};
diff --git a/arch/arm/dts/bcm963178.dts b/arch/arm/dts/bcm963178.dts
new file mode 100644
index 0000000..fa096e9
--- /dev/null
+++ b/arch/arm/dts/bcm963178.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm63178.dtsi"
+
+/ {
+ model = "Broadcom BCM963178 Reference Board";
+ compatible = "brcm,bcm963178", "brcm,bcm63178", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm96753ref.dts b/arch/arm/dts/bcm96753ref.dts
index ca15ca5f..f74137f 100644
--- a/arch/arm/dts/bcm96753ref.dts
+++ b/arch/arm/dts/bcm96753ref.dts
@@ -5,13 +5,13 @@
/dts-v1/;
-#include "bcm6753.dtsi"
+#include "bcm6855.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
- model = "Broadcom bcm6753ref";
- compatible = "broadcom,bcm6753ref", "brcm,bcm6753";
+ model = "Broadcom BCM96753REF Reference Board";
+ compatible = "brcm,bcm96753ref", "brcm,bcm6855", "brcm,bcmbca";
aliases {
serial0 = &uart0;
diff --git a/arch/arm/dts/bcm96756.dts b/arch/arm/dts/bcm96756.dts
new file mode 100644
index 0000000..9a4a87b
--- /dev/null
+++ b/arch/arm/dts/bcm96756.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6756.dtsi"
+
+/ {
+ model = "Broadcom BCM96756 Reference Board";
+ compatible = "brcm,bcm96756", "brcm,bcm6756", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm96813.dts b/arch/arm/dts/bcm96813.dts
new file mode 100644
index 0000000..af17091
--- /dev/null
+++ b/arch/arm/dts/bcm96813.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6813.dtsi"
+
+/ {
+ model = "Broadcom BCM96813 Reference Board";
+ compatible = "brcm,bcm96813", "brcm,bcm6813", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm968360bg.dts b/arch/arm/dts/bcm968360bg.dts
index c060294..6f1090a 100644
--- a/arch/arm/dts/bcm968360bg.dts
+++ b/arch/arm/dts/bcm968360bg.dts
@@ -5,11 +5,11 @@
/dts-v1/;
-#include "bcm68360.dtsi"
+#include "bcm6856.dtsi"
/ {
- model = "Broadcom bcm68360bg";
- compatible = "broadcom,bcm68360bg", "brcm,bcm68360";
+ model = "Broadcom BCM968360BG Reference Board";
+ compatible = "brcm,bcm968360bg", "brcm,bcm6856", "brcm,bcmbca";
aliases {
serial0 = &uart0;
diff --git a/arch/arm/dts/bcm96846.dts b/arch/arm/dts/bcm96846.dts
new file mode 100644
index 0000000..c70ebcc
--- /dev/null
+++ b/arch/arm/dts/bcm96846.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6846.dtsi"
+
+/ {
+ model = "Broadcom BCM96846 Reference Board";
+ compatible = "brcm,bcm96846", "brcm,bcm6846", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm96855.dts b/arch/arm/dts/bcm96855.dts
new file mode 100644
index 0000000..e4e740c
--- /dev/null
+++ b/arch/arm/dts/bcm96855.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6855.dtsi"
+
+/ {
+ model = "Broadcom BCM96855 Reference Board";
+ compatible = "brcm,bcm96855", "brcm,bcm6855", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm96856.dts b/arch/arm/dts/bcm96856.dts
new file mode 100644
index 0000000..032aeb7
--- /dev/null
+++ b/arch/arm/dts/bcm96856.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6856.dtsi"
+
+/ {
+ model = "Broadcom BCM96856 Reference Board";
+ compatible = "brcm,bcm96856", "brcm,bcm6856", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm96858.dts b/arch/arm/dts/bcm96858.dts
new file mode 100644
index 0000000..0cbf582
--- /dev/null
+++ b/arch/arm/dts/bcm96858.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6858.dtsi"
+
+/ {
+ model = "Broadcom BCM96858 Reference Board";
+ compatible = "brcm,bcm96858", "brcm,bcm6858", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/bcm968580xref.dts b/arch/arm/dts/bcm968580xref.dts
index a034e38..6d787bd 100644
--- a/arch/arm/dts/bcm968580xref.dts
+++ b/arch/arm/dts/bcm968580xref.dts
@@ -8,8 +8,8 @@
#include "bcm6858.dtsi"
/ {
- model = "Broadcom bcm68580xref";
- compatible = "broadcom,bcm68580xref", "brcm,bcm6858";
+ model = "Broadcom BCM968580xref Reference Board";
+ compatible = "brcm,bcm968580xref", "brcm,bcm6858", "brcm,bcmbca";
aliases {
serial0 = &uart0;
diff --git a/arch/arm/dts/bcm96878.dts b/arch/arm/dts/bcm96878.dts
new file mode 100644
index 0000000..8fbc175
--- /dev/null
+++ b/arch/arm/dts/bcm96878.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm6878.dtsi"
+
+/ {
+ model = "Broadcom BCM96878 Reference Board";
+ compatible = "brcm,bcm96878", "brcm,bcm6878", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig
index 2d49380..62b3716 100644
--- a/arch/arm/mach-bcmbca/Kconfig
+++ b/arch/arm/mach-bcmbca/Kconfig
@@ -12,6 +12,128 @@
select DM_SERIAL
select PL01X_SERIAL
-endif
+config BCM4908
+ bool "Support for Broadcom 4908 Family"
+ select ARM64
+ select SYS_ARCH_TIMER
+ select DM_SERIAL
+ select BCM6345_SERIAL
+
+config BCM4912
+ bool "Support for Broadcom 4912 Family"
+ select ARM64
+ select SYS_ARCH_TIMER
+ select DM_SERIAL
+ select PL01X_SERIAL
+
+config BCM63138
+ bool "Support for Broadcom 63138 Family"
+ select TIMER
+ select ARM_GLOBAL_TIMER
+ select CPU_V7A
+ select DM_SERIAL
+ select BCM6345_SERIAL
+
+config BCM63146
+ bool "Support for Broadcom 63146 Family"
+ select ARM64
+ select SYS_ARCH_TIMER
+ select DM_SERIAL
+ select PL01X_SERIAL
+
+config BCM63148
+ bool "Support for Broadcom 63148 Family"
+ select SYS_ARCH_TIMER
+ select CPU_V7A
+ select DM_SERIAL
+ select BCM6345_SERIAL
+
+config BCM63158
+ bool "Support for Broadcom 63158 Family"
+ select ARM64
+ select SYS_ARCH_TIMER
+ select DM_SERIAL
+ select PL01X_SERIAL
+
+config BCM63178
+ bool "Support for Broadcom 63178 Family"
+ select SYS_ARCH_TIMER
+ select CPU_V7A
+ select DM_SERIAL
+ select PL01X_SERIAL
+
+config BCM6756
+ bool "Support for Broadcom 6756 Family"
+ select SYS_ARCH_TIMER
+ select CPU_V7A
+ select DM_SERIAL
+ select PL01X_SERIAL
+
+config BCM6813
+ bool "Support for Broadcom 6813 Family"
+ select ARM64
+ select SYS_ARCH_TIMER
+ select DM_SERIAL
+ select PL01X_SERIAL
+
+config BCM6846
+ bool "Support for Broadcom 6846 Family"
+ select SYS_ARCH_TIMER
+ select CPU_V7A
+ select DM_SERIAL
+ select BCM6345_SERIAL
+
+config BCM6855
+ bool "Support for Broadcom 6855 Family"
+ select SYS_ARCH_TIMER
+ select CPU_V7A
+ select DM_SERIAL
+ select PL01X_SERIAL
+ help
+ Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway
+ SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753.
+
+config BCM6856
+ bool "Support for Broadcom 6856 Family"
+ select ARM64
+ select SYS_ARCH_TIMER
+ select DM_SERIAL
+ select BCM6345_SERIAL
+ help
+ Broadcom BCM6856 is a dual core Brahma-B53 ARMv8 based xPON Gateway
+ SoC. This SoC family includes BCM6856, BCM6836 and BCM4910.
+
+config BCM6858
+ bool "Support for Broadcom 6858 Family"
+ select ARM64
+ select SYS_ARCH_TIMER
+ select DM_SERIAL
+ select BCM6345_SERIAL
+ help
+ Broadcom BCM6858 is a quad core Brahma-B53 ARMv8 based xPON Gateway
+ SoC. This SoC family includes BCM6858, BCM49508, BCM5504X and BCM6545.
+
+config BCM6878
+ bool "Support for Broadcom 6878 Family"
+ select SYS_ARCH_TIMER
+ select CPU_V7A
+ select DM_SERIAL
+ select PL01X_SERIAL
source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
+source "arch/arm/mach-bcmbca/bcm4908/Kconfig"
+source "arch/arm/mach-bcmbca/bcm4912/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63138/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63146/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63148/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63158/Kconfig"
+source "arch/arm/mach-bcmbca/bcm63178/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6756/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6813/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6846/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6855/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6856/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6858/Kconfig"
+source "arch/arm/mach-bcmbca/bcm6878/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile
index 072d4ea..7de9450 100644
--- a/arch/arm/mach-bcmbca/Makefile
+++ b/arch/arm/mach-bcmbca/Makefile
@@ -4,3 +4,17 @@
#
obj-$(CONFIG_BCM47622) += bcm47622/
+obj-$(CONFIG_BCM4908) += bcm4908/
+obj-$(CONFIG_BCM4912) += bcm4912/
+obj-$(CONFIG_BCM63138) += bcm63138/
+obj-$(CONFIG_BCM63146) += bcm63146/
+obj-$(CONFIG_BCM63148) += bcm63148/
+obj-$(CONFIG_BCM63158) += bcm63158/
+obj-$(CONFIG_BCM63178) += bcm63178/
+obj-$(CONFIG_BCM6756) += bcm6756/
+obj-$(CONFIG_BCM6813) += bcm6813/
+obj-$(CONFIG_BCM6846) += bcm6846/
+obj-$(CONFIG_BCM6855) += bcm6855/
+obj-$(CONFIG_BCM6856) += bcm6856/
+obj-$(CONFIG_BCM6858) += bcm6858/
+obj-$(CONFIG_BCM6878) += bcm6878/
diff --git a/arch/arm/mach-bcmbca/bcm4908/Kconfig b/arch/arm/mach-bcmbca/bcm4908/Kconfig
new file mode 100644
index 0000000..564bc8d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM4908
+
+config TARGET_BCM94908
+ bool "Broadcom 4908 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm4908"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm4908/Makefile b/arch/arm/mach-bcmbca/bcm4908/Makefile
new file mode 100644
index 0000000..6262497
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj-y += mmu_table.o
diff --git a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c
new file mode 100644
index 0000000..5ab0408
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+static struct mm_region bcm94908_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 1UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SoC peripheral */
+ .virt = 0xff800000UL,
+ .phys = 0xff800000UL,
+ .size = 0x100000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm94908_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm4912/Kconfig b/arch/arm/mach-bcmbca/bcm4912/Kconfig
new file mode 100644
index 0000000..b8c14d1
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4912/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM4912
+
+config TARGET_BCM94912
+ bool "Broadcom 4912 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm4912"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm4912/Makefile b/arch/arm/mach-bcmbca/bcm4912/Makefile
new file mode 100644
index 0000000..6262497
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4912/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj-y += mmu_table.o
diff --git a/arch/arm/mach-bcmbca/bcm4912/mmu_table.c b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c
new file mode 100644
index 0000000..52a53a2
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4912/mmu_table.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+static struct mm_region bcm94912_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 1UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SoC peripheral */
+ .virt = 0xff800000UL,
+ .phys = 0xff800000UL,
+ .size = 0x100000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm94912_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm63138/Kconfig b/arch/arm/mach-bcmbca/bcm63138/Kconfig
new file mode 100644
index 0000000..a34888d
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM63138
+
+config TARGET_BCM963138
+ bool "Broadcom 63138 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm63138"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63138/Makefile b/arch/arm/mach-bcmbca/bcm63138/Makefile
new file mode 100644
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63138/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o
diff --git a/arch/arm/mach-bcmbca/bcm63146/Kconfig b/arch/arm/mach-bcmbca/bcm63146/Kconfig
new file mode 100644
index 0000000..690cbf1
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63146/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM63146
+
+config TARGET_BCM963146
+ bool "Broadcom 63146 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm63146"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63146/Makefile b/arch/arm/mach-bcmbca/bcm63146/Makefile
new file mode 100644
index 0000000..6262497
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63146/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj-y += mmu_table.o
diff --git a/arch/arm/mach-bcmbca/bcm63146/mmu_table.c b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c
new file mode 100644
index 0000000..c6b7a54
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63146/mmu_table.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+static struct mm_region bcm963146_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 1UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SoC peripheral */
+ .virt = 0xff800000UL,
+ .phys = 0xff800000UL,
+ .size = 0x100000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm963146_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm63148/Kconfig b/arch/arm/mach-bcmbca/bcm63148/Kconfig
new file mode 100644
index 0000000..f81504c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM63148
+
+config TARGET_BCM963148
+ bool "Broadcom 63148 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm63148"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63148/Makefile b/arch/arm/mach-bcmbca/bcm63148/Makefile
new file mode 100644
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63148/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o
diff --git a/arch/arm/mach-bcmbca/bcm63158/Kconfig b/arch/arm/mach-bcmbca/bcm63158/Kconfig
new file mode 100644
index 0000000..b774443
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63158/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM63158
+
+config TARGET_BCM963158
+ bool "Broadcom 63158 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm63158"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63158/Makefile b/arch/arm/mach-bcmbca/bcm63158/Makefile
new file mode 100644
index 0000000..6262497
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63158/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj-y += mmu_table.o
diff --git a/arch/arm/mach-bcmbca/bcm63158/mmu_table.c b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c
new file mode 100644
index 0000000..fe7efb3
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63158/mmu_table.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+static struct mm_region bcm963158_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 1UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SoC peripheral */
+ .virt = 0xff800000UL,
+ .phys = 0xff800000UL,
+ .size = 0x100000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm963158_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm63178/Kconfig b/arch/arm/mach-bcmbca/bcm63178/Kconfig
new file mode 100644
index 0000000..73ac462
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63178/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM63178
+
+config TARGET_BCM963178
+ bool "Broadcom 63178 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm63178"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm63178/Makefile b/arch/arm/mach-bcmbca/bcm63178/Makefile
new file mode 100644
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm63178/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o
diff --git a/arch/arm/mach-bcmbca/bcm6756/Kconfig b/arch/arm/mach-bcmbca/bcm6756/Kconfig
new file mode 100644
index 0000000..c83dcd0
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6756/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM6756
+
+config TARGET_BCM96756
+ bool "Broadcom 6756 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm6756"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6756/Makefile b/arch/arm/mach-bcmbca/bcm6756/Makefile
new file mode 100644
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6756/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o
diff --git a/arch/arm/mach-bcmbca/bcm6813/Kconfig b/arch/arm/mach-bcmbca/bcm6813/Kconfig
new file mode 100644
index 0000000..25a4221
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6813/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM6813
+
+config TARGET_BCM96813
+ bool "Broadcom 6813 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm6813"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6813/Makefile b/arch/arm/mach-bcmbca/bcm6813/Makefile
new file mode 100644
index 0000000..6262497
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6813/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj-y += mmu_table.o
diff --git a/arch/arm/mach-bcmbca/bcm6813/mmu_table.c b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c
new file mode 100644
index 0000000..eb736bf
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6813/mmu_table.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+static struct mm_region bcm96813_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 1UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SoC peripheral */
+ .virt = 0xff800000UL,
+ .phys = 0xff800000UL,
+ .size = 0x100000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm96813_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm6846/Kconfig b/arch/arm/mach-bcmbca/bcm6846/Kconfig
new file mode 100644
index 0000000..229ab88
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6846/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM6846
+
+config TARGET_BCM96846
+ bool "Broadcom 6846 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm6846"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6846/Makefile b/arch/arm/mach-bcmbca/bcm6846/Makefile
new file mode 100644
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6846/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o
diff --git a/arch/arm/mach-bcmbca/bcm6855/Kconfig b/arch/arm/mach-bcmbca/bcm6855/Kconfig
new file mode 100644
index 0000000..78087c7
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6855/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM6855
+
+config TARGET_BCM96855
+ bool "Broadcom 6855 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm6855"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6855/Makefile b/arch/arm/mach-bcmbca/bcm6855/Makefile
new file mode 100644
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6855/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o
diff --git a/arch/arm/mach-bcmbca/bcm6856/Kconfig b/arch/arm/mach-bcmbca/bcm6856/Kconfig
new file mode 100644
index 0000000..6ac75cb
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6856/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM6856
+
+config TARGET_BCM96856
+ bool "Broadcom 6856 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm6856"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6856/Makefile b/arch/arm/mach-bcmbca/bcm6856/Makefile
new file mode 100644
index 0000000..6262497
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6856/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj-y += mmu_table.o
diff --git a/arch/arm/mach-bcmbca/bcm6856/mmu_table.c b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c
new file mode 100644
index 0000000..8e53b49
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6856/mmu_table.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+static struct mm_region bcm96856_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 1UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SoC peripheral */
+ .virt = 0xff800000UL,
+ .phys = 0xff800000UL,
+ .size = 0x100000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm96856_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm6858/Kconfig b/arch/arm/mach-bcmbca/bcm6858/Kconfig
new file mode 100644
index 0000000..a6504ba
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6858/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM6858
+
+config TARGET_BCM96858
+ bool "Broadcom 6858 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm6858"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6858/Makefile b/arch/arm/mach-bcmbca/bcm6858/Makefile
new file mode 100644
index 0000000..6262497
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6858/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj-y += mmu_table.o
diff --git a/arch/arm/mach-bcmbca/bcm6858/mmu_table.c b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c
new file mode 100644
index 0000000..8982910
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6858/mmu_table.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+static struct mm_region bcm96858_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 1UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SoC peripheral */
+ .virt = 0xff800000UL,
+ .phys = 0xff800000UL,
+ .size = 0x100000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm96858_mem_map;
diff --git a/arch/arm/mach-bcmbca/bcm6878/Kconfig b/arch/arm/mach-bcmbca/bcm6878/Kconfig
new file mode 100644
index 0000000..43f8942
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6878/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM6878
+
+config TARGET_BCM96878
+ bool "Broadcom 6878 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm6878"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm6878/Makefile b/arch/arm/mach-bcmbca/bcm6878/Makefile
new file mode 100644
index 0000000..beb979a
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm6878/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj- += dummy.o
diff --git a/board/broadcom/bcm963158/Kconfig b/board/broadcom/bcm963158/Kconfig
deleted file mode 100644
index 08a8bc1..0000000
--- a/board/broadcom/bcm963158/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if TARGET_BCM963158
-
-config SYS_VENDOR
- default "broadcom"
-
-config SYS_BOARD
- default "bcm963158"
-
-config SYS_CONFIG_NAME
- default "broadcom_bcm963158"
-
-endif
-
-config TARGET_BCM963158
- bool "Support Broadcom bcm963158"
- depends on ARCH_BCM63158
- select ARM64
diff --git a/board/broadcom/bcm963158/MAINTAINERS b/board/broadcom/bcm963158/MAINTAINERS
deleted file mode 100644
index d28d971..0000000
--- a/board/broadcom/bcm963158/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BROADCOM BCM963158
-M: Philippe Reynes <philippe.reynes@softathome.com>
-S: Maintained
-F: board/broadcom/bcm963158/
-F: include/configs/broadcom_bcm963158.h
-F: configs/bcm963158_ram_defconfig
diff --git a/board/broadcom/bcm963158/Makefile b/board/broadcom/bcm963158/Makefile
deleted file mode 100644
index 0a902c9..0000000
--- a/board/broadcom/bcm963158/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += bcm963158.o
diff --git a/board/broadcom/bcm963158/bcm963158.c b/board/broadcom/bcm963158/bcm963158.c
deleted file mode 100644
index 9feaee3..0000000
--- a/board/broadcom/bcm963158/bcm963158.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <init.h>
-#include <linux/io.h>
-
-#ifdef CONFIG_ARM64
-#include <asm/armv8/mmu.h>
-
-static struct mm_region broadcom_bcm963158_mem_map[] = {
- {
- /* RAM */
- .virt = 0x00000000UL,
- .phys = 0x00000000UL,
- .size = 8UL * SZ_1G,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- /* SoC */
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0xff80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = broadcom_bcm963158_mem_map;
-#endif
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- printf("fdtdec_setup_mem_size_base() has failed\n");
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- return 0;
-}
diff --git a/board/broadcom/bcm96753ref/Kconfig b/board/broadcom/bcm96753ref/Kconfig
deleted file mode 100644
index 479e790..0000000
--- a/board/broadcom/bcm96753ref/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if TARGET_BCM96753REF
-
-config SYS_VENDOR
- default "broadcom"
-
-config SYS_BOARD
- default "bcm96753ref"
-
-config SYS_CONFIG_NAME
- default "broadcom_bcm96753ref"
-
-endif
-
-config TARGET_BCM96753REF
- bool "Support Broadcom bcm96753ref"
- depends on ARCH_BCM6753
diff --git a/board/broadcom/bcm96753ref/MAINTAINERS b/board/broadcom/bcm96753ref/MAINTAINERS
deleted file mode 100644
index be060f5..0000000
--- a/board/broadcom/bcm96753ref/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BROADCOM BCM96753REF
-M: Philippe Reynes <philippe.reynes@softathome.com>
-S: Maintained
-F: board/broadcom/bcm96753ref
-F: include/configs/broadcom_bcm96753ref.h
-F: configs/bcm96753ref_ram_defconfig
diff --git a/board/broadcom/bcm96753ref/Makefile b/board/broadcom/bcm96753ref/Makefile
deleted file mode 100644
index a1fa2bf..0000000
--- a/board/broadcom/bcm96753ref/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += bcm96753ref.o
diff --git a/board/broadcom/bcm96753ref/bcm96753ref.c b/board/broadcom/bcm96753ref/bcm96753ref.c
deleted file mode 100644
index bf78d84..0000000
--- a/board/broadcom/bcm96753ref/bcm96753ref.c
+++ /dev/null
@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <linux/io.h>
-#include <cpu_func.h>
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- printf("fdtdec_setup_mem_size_base() has failed\n");
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- return 0;
-}
-
-void enable_caches(void)
-{
- icache_enable();
- dcache_enable();
-}
diff --git a/board/broadcom/bcm968360bg/Kconfig b/board/broadcom/bcm968360bg/Kconfig
deleted file mode 100644
index dd372f1..0000000
--- a/board/broadcom/bcm968360bg/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if ARCH_BCM68360
-
-config SYS_VENDOR
- default "broadcom"
-
-config SYS_BOARD
- default "bcm968360bg"
-
-config SYS_CONFIG_NAME
- default "broadcom_bcm968360bg"
-
-endif
-
-config TARGET_BCM968360BG
- bool "Support Broadcom bcm968360bg"
- depends on ARCH_BCM68360
- select ARM64
diff --git a/board/broadcom/bcm968360bg/MAINTAINERS b/board/broadcom/bcm968360bg/MAINTAINERS
deleted file mode 100644
index cfcbbc5..0000000
--- a/board/broadcom/bcm968360bg/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BCM968360BG BOARD
-M: Philippe Reynes <philippe.reynes@softathome.com>
-S: Maintained
-F: board/broadcom/bcm968360bg
-F: include/configs/broadcom_bcm968360bg.h
-F: configs/bcm968360bg_ram_defconfig
diff --git a/board/broadcom/bcm968360bg/Makefile b/board/broadcom/bcm968360bg/Makefile
deleted file mode 100644
index d099c1c..0000000
--- a/board/broadcom/bcm968360bg/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += bcm968360bg.o
diff --git a/board/broadcom/bcm968360bg/bcm968360bg.c b/board/broadcom/bcm968360bg/bcm968360bg.c
deleted file mode 100644
index 90af6b8..0000000
--- a/board/broadcom/bcm968360bg/bcm968360bg.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <init.h>
-#include <linux/io.h>
-
-#ifdef CONFIG_ARM64
-#include <asm/armv8/mmu.h>
-
-static struct mm_region broadcom_bcm968360bg_mem_map[] = {
- {
- /* RAM */
- .virt = 0x00000000UL,
- .phys = 0x00000000UL,
- .size = 8UL * SZ_1G,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- /* SoC */
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0xff80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = broadcom_bcm968360bg_mem_map;
-#endif
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- printf("fdtdec_setup_mem_size_base() has failed\n");
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- return 0;
-}
diff --git a/board/broadcom/bcm968580xref/Kconfig b/board/broadcom/bcm968580xref/Kconfig
deleted file mode 100644
index b573036..0000000
--- a/board/broadcom/bcm968580xref/Kconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-if ARCH_BCM6858
-
-config SYS_VENDOR
- default "broadcom"
-
-config SYS_BOARD
- default "bcm968580xref"
-
-config SYS_CONFIG_NAME
- default "broadcom_bcm968580xref"
-
-endif
-
-config TARGET_BCM968580XREF
- bool "Support Broadcom bcm968580xref"
- depends on ARCH_BCM6858
- select ARM64
diff --git a/board/broadcom/bcm968580xref/MAINTAINERS b/board/broadcom/bcm968580xref/MAINTAINERS
deleted file mode 100644
index 5ee0c4d..0000000
--- a/board/broadcom/bcm968580xref/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-BCM968580XREF BOARD
-M: Philippe Reynes <philippe.reynes@softathome.com>
-S: Maintained
-F: board/broadcom/bcm968580xref/
-F: include/configs/broadcom_bcm968580xref.h
-F: configs/bcm968580xref_ram_defconfig
diff --git a/board/broadcom/bcm968580xref/Makefile b/board/broadcom/bcm968580xref/Makefile
deleted file mode 100644
index 5cd393b..0000000
--- a/board/broadcom/bcm968580xref/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-
-obj-y += bcm968580xref.o
diff --git a/board/broadcom/bcm968580xref/bcm968580xref.c b/board/broadcom/bcm968580xref/bcm968580xref.c
deleted file mode 100644
index 1bd723d..0000000
--- a/board/broadcom/bcm968580xref/bcm968580xref.c
+++ /dev/null
@@ -1,62 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <common.h>
-#include <fdtdec.h>
-#include <init.h>
-#include <linux/io.h>
-
-#ifdef CONFIG_ARM64
-#include <asm/armv8/mmu.h>
-
-static struct mm_region broadcom_bcm968580xref_mem_map[] = {
- {
- /* RAM */
- .virt = 0x00000000UL,
- .phys = 0x00000000UL,
- .size = 8UL * SZ_1G,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- /* SoC */
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0xff80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = broadcom_bcm968580xref_mem_map;
-#endif
-
-int board_init(void)
-{
- return 0;
-}
-
-int dram_init(void)
-{
- if (fdtdec_setup_mem_size_base() != 0)
- printf("fdtdec_setup_mem_size_base() has failed\n");
-
- return 0;
-}
-
-int dram_init_banksize(void)
-{
- fdtdec_setup_memory_banksize();
-
- return 0;
-}
-
-int print_cpuinfo(void)
-{
- return 0;
-}
diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig
index 63d4252..5903a6a 100644
--- a/board/broadcom/bcmbca/Kconfig
+++ b/board/broadcom/bcmbca/Kconfig
@@ -15,3 +15,101 @@
default "bcm947622"
endif
+
+if TARGET_BCM94908
+
+config SYS_CONFIG_NAME
+ default "bcm94908"
+
+endif
+
+if TARGET_BCM94912
+
+config SYS_CONFIG_NAME
+ default "bcm94912"
+
+endif
+
+if TARGET_BCM963138
+
+config SYS_CONFIG_NAME
+ default "bcm963138"
+
+endif
+
+if TARGET_BCM963146
+
+config SYS_CONFIG_NAME
+ default "bcm963146"
+
+endif
+
+if TARGET_BCM963148
+
+config SYS_CONFIG_NAME
+ default "bcm963148"
+
+endif
+
+if TARGET_BCM963158
+
+config SYS_CONFIG_NAME
+ default "bcm963158"
+
+endif
+
+if TARGET_BCM963178
+
+config SYS_CONFIG_NAME
+ default "bcm963178"
+
+endif
+
+if TARGET_BCM96756
+
+config SYS_CONFIG_NAME
+ default "bcm96756"
+
+endif
+
+if TARGET_BCM96813
+
+config SYS_CONFIG_NAME
+ default "bcm96813"
+
+endif
+
+if TARGET_BCM96846
+
+config SYS_CONFIG_NAME
+ default "bcm96846"
+
+endif
+
+if TARGET_BCM96855
+
+config SYS_CONFIG_NAME
+ default "bcm96855"
+
+endif
+
+if TARGET_BCM96856
+
+config SYS_CONFIG_NAME
+ default "bcm96856"
+
+endif
+
+if TARGET_BCM96858
+
+config SYS_CONFIG_NAME
+ default "bcm96858"
+
+endif
+
+if TARGET_BCM96878
+
+config SYS_CONFIG_NAME
+ default "bcm96878"
+
+endif
diff --git a/board/broadcom/bcmbca/board.c b/board/broadcom/bcmbca/board.c
index 4aa1d65..bcecb4d 100644
--- a/board/broadcom/bcmbca/board.c
+++ b/board/broadcom/bcmbca/board.c
@@ -30,6 +30,6 @@
return 0;
}
-void reset_cpu(ulong addr)
+__weak void reset_cpu(void)
{
}
diff --git a/configs/bcm94908_defconfig b/configs/bcm94908_defconfig
new file mode 100644
index 0000000..6dfb882
--- /dev/null
+++ b/configs/bcm94908_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM4908=y
+CONFIG_TARGET_BCM94908=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="bcm94908"
+CONFIG_IDENT_STRING=" Broadcom BCM4908"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm94912_defconfig b/configs/bcm94912_defconfig
new file mode 100644
index 0000000..355f10a
--- /dev/null
+++ b/configs/bcm94912_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM4912=y
+CONFIG_TARGET_BCM94912=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="bcm94912"
+CONFIG_IDENT_STRING=" Broadcom BCM4912"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm963138_defconfig b/configs/bcm963138_defconfig
new file mode 100644
index 0000000..5aec7b8
--- /dev/null
+++ b/configs/bcm963138_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM63138=y
+CONFIG_TARGET_BCM963138=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm963138"
+CONFIG_IDENT_STRING=" Broadcom BCM63138"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm963146_defconfig b/configs/bcm963146_defconfig
new file mode 100644
index 0000000..4dcc0fd
--- /dev/null
+++ b/configs/bcm963146_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM63146=y
+CONFIG_TARGET_BCM963146=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="bcm963146"
+CONFIG_IDENT_STRING=" Broadcom BCM63146"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm963148_defconfig b/configs/bcm963148_defconfig
new file mode 100644
index 0000000..6ddb45c
--- /dev/null
+++ b/configs/bcm963148_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM63148=y
+CONFIG_TARGET_BCM963148=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm963148"
+CONFIG_IDENT_STRING=" Broadcom BCM63148"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm963158_defconfig b/configs/bcm963158_defconfig
new file mode 100644
index 0000000..b585adb
--- /dev/null
+++ b/configs/bcm963158_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM63158=y
+CONFIG_TARGET_BCM963158=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
+CONFIG_IDENT_STRING=" Broadcom BCM63158"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm963158_ram_defconfig b/configs/bcm963158_ram_defconfig
deleted file mode 100644
index c0fda57..0000000
--- a/configs/bcm963158_ram_defconfig
+++ /dev/null
@@ -1,65 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-# CONFIG_ARM64_SUPPORT_AARCH32 is not set
-CONFIG_ARCH_BCM63158=y
-CONFIG_SYS_TEXT_BASE=0x10000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="bcm963158"
-CONFIG_SYS_LOAD_ADDR=0x10000000
-CONFIG_TARGET_BCM963158=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x11000000
-CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_RSASSA_PSS=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x1000000
-# CONFIG_CMD_LZMADEC is not set
-# CONFIG_CMD_UNZIP is not set
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_CACHE=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
-CONFIG_CLK=y
-CONFIG_BCM6345_GPIO=y
-CONFIG_LED=y
-CONFIG_LED_BCM6858=y
-CONFIG_LED_BLINK=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_BRCMNAND=y
-CONFIG_NAND_BRCMNAND_63158=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_CONS_INDEX=0
-CONFIG_DM_SERIAL=y
-CONFIG_SERIAL_SEARCH_ALL=y
-CONFIG_PL01X_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_BCM63XX_HSSPI=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_WDT_BCM6345=y
diff --git a/configs/bcm963178_defconfig b/configs/bcm963178_defconfig
new file mode 100644
index 0000000..d9e62cf
--- /dev/null
+++ b/configs/bcm963178_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM63178=y
+CONFIG_TARGET_BCM963178=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm963178"
+CONFIG_IDENT_STRING=" Broadcom BCM63178"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm96753ref_ram_defconfig b/configs/bcm96753ref_ram_defconfig
deleted file mode 100644
index 59ac1cd..0000000
--- a/configs/bcm96753ref_ram_defconfig
+++ /dev/null
@@ -1,87 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
-CONFIG_SYS_ARCH_TIMER=y
-CONFIG_ARCH_BCM6753=y
-CONFIG_SYS_TEXT_BASE=0x1000000
-CONFIG_SYS_MALLOC_F_LEN=0x1000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x20000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="bcm96753ref"
-CONFIG_ARMV7_LPAE=y
-CONFIG_SYS_LOAD_ADDR=0x1000000
-CONFIG_TARGET_BCM96753REF=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
-CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_CIPHER=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-# CONFIG_AUTOBOOT is not set
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_BOOTM_NETBSD is not set
-# CONFIG_BOOTM_PLAN9 is not set
-# CONFIG_BOOTM_RTEMS is not set
-# CONFIG_BOOTM_VXWORKS is not set
-# CONFIG_CMD_ELF is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EXPORTENV is not set
-# CONFIG_CMD_IMPORTENV is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_SAVEENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-# CONFIG_CMD_CRC32 is not set
-CONFIG_CMD_MEMINFO=y
-CONFIG_CMD_CLK=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_MTD=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_WDT=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_MTDPARTS=y
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-# CONFIG_NET is not set
-CONFIG_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_BUTTON=y
-CONFIG_BUTTON_GPIO=y
-CONFIG_CLK=y
-CONFIG_BCM6345_GPIO=y
-# CONFIG_INPUT is not set
-CONFIG_LED=y
-CONFIG_LED_BCM6753=y
-CONFIG_LED_BLINK=y
-CONFIG_LED_GPIO=y
-CONFIG_MISC=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_BRCMNAND=y
-CONFIG_NAND_BRCMNAND_6753=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_DM_SERIAL=y
-CONFIG_PL01X_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_SPI_MEM=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_WDT_BCM6345=y
-CONFIG_REGEX=y
diff --git a/configs/bcm96756_defconfig b/configs/bcm96756_defconfig
new file mode 100644
index 0000000..8152673
--- /dev/null
+++ b/configs/bcm96756_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM6756=y
+CONFIG_TARGET_BCM96756=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm96756"
+CONFIG_IDENT_STRING=" Broadcom BCM6756"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm96813_defconfig b/configs/bcm96813_defconfig
new file mode 100644
index 0000000..5d03624
--- /dev/null
+++ b/configs/bcm96813_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM6813=y
+CONFIG_TARGET_BCM96813=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="bcm96813"
+CONFIG_IDENT_STRING=" Broadcom BCM6813"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm968360bg_ram_defconfig b/configs/bcm968360bg_ram_defconfig
deleted file mode 100644
index a83d4ef..0000000
--- a/configs/bcm968360bg_ram_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_BCM68360=y
-CONFIG_SYS_TEXT_BASE=0x10000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="bcm968360bg"
-CONFIG_SYS_LOAD_ADDR=0x10000000
-CONFIG_TARGET_BCM968360BG=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x11000000
-CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x800000
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
-CONFIG_CLK=y
-CONFIG_BCM6345_GPIO=y
-CONFIG_LED=y
-CONFIG_LED_BCM6858=y
-CONFIG_LED_BLINK=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_BRCMNAND=y
-CONFIG_NAND_BRCMNAND_68360=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_CONS_INDEX=0
-CONFIG_DM_SERIAL=y
-CONFIG_SERIAL_SEARCH_ALL=y
-CONFIG_BCM6345_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_BCM63XX_HSSPI=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_WDT_BCM6345=y
diff --git a/configs/bcm96846_defconfig b/configs/bcm96846_defconfig
new file mode 100644
index 0000000..27cfb45
--- /dev/null
+++ b/configs/bcm96846_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM6846=y
+CONFIG_TARGET_BCM96846=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm96846"
+CONFIG_IDENT_STRING=" Broadcom BCM6846"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm96855_defconfig b/configs/bcm96855_defconfig
new file mode 100644
index 0000000..223c0a1
--- /dev/null
+++ b/configs/bcm96855_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM6855=y
+CONFIG_TARGET_BCM96855=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm96855"
+CONFIG_IDENT_STRING=" Broadcom BCM6855"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm96856_defconfig b/configs/bcm96856_defconfig
new file mode 100644
index 0000000..7e1c097
--- /dev/null
+++ b/configs/bcm96856_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM6856=y
+CONFIG_TARGET_BCM96856=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="bcm96856"
+CONFIG_IDENT_STRING=" Broadcom BCM6856"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm968580xref_ram_defconfig b/configs/bcm968580xref_ram_defconfig
deleted file mode 100644
index 4320739..0000000
--- a/configs/bcm968580xref_ram_defconfig
+++ /dev/null
@@ -1,62 +0,0 @@
-CONFIG_ARM=y
-CONFIG_SKIP_LOWLEVEL_INIT=y
-CONFIG_ARCH_BCM6858=y
-CONFIG_SYS_TEXT_BASE=0x10000000
-CONFIG_SYS_MALLOC_LEN=0x100000
-CONFIG_SYS_MALLOC_F_LEN=0x8000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x2000
-CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="bcm968580xref"
-CONFIG_SYS_LOAD_ADDR=0x10000000
-CONFIG_TARGET_BCM968580XREF=y
-CONFIG_ENV_VARS_UBOOT_CONFIG=y
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x11000000
-CONFIG_FIT=y
-CONFIG_FIT_SIGNATURE=y
-CONFIG_FIT_VERBOSE=y
-CONFIG_LEGACY_IMAGE_FORMAT=y
-CONFIG_SUPPORT_RAW_INITRD=y
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_HUSH_PARSER=y
-CONFIG_SYS_MAXARGS=24
-CONFIG_SYS_CBSIZE=256
-CONFIG_SYS_PBSIZE=276
-CONFIG_SYS_BOOTM_LEN=0x800000
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_MTD=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_PART=y
-CONFIG_CMD_SPI=y
-CONFIG_DOS_PARTITION=y
-CONFIG_ISO_PARTITION=y
-CONFIG_EFI_PARTITION=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-# CONFIG_NET is not set
-CONFIG_CLK=y
-CONFIG_BCM6345_GPIO=y
-CONFIG_LED=y
-CONFIG_LED_BCM6858=y
-CONFIG_LED_BLINK=y
-# CONFIG_MMC is not set
-CONFIG_MTD=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_BRCMNAND=y
-CONFIG_NAND_BRCMNAND_6858=y
-CONFIG_SYS_NAND_ONFI_DETECTION=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_SPI_FLASH_SFDP_SUPPORT=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPECIFY_CONSOLE_INDEX=y
-CONFIG_CONS_INDEX=0
-CONFIG_DM_SERIAL=y
-CONFIG_SERIAL_SEARCH_ALL=y
-CONFIG_BCM6345_SERIAL=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_BCM63XX_HSSPI=y
-CONFIG_SYSRESET=y
-CONFIG_SYSRESET_WATCHDOG=y
-CONFIG_WDT_BCM6345=y
diff --git a/configs/bcm96858_defconfig b/configs/bcm96858_defconfig
new file mode 100644
index 0000000..5f7be11
--- /dev/null
+++ b/configs/bcm96858_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM6858=y
+CONFIG_TARGET_BCM96858=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="bcm96858"
+CONFIG_IDENT_STRING=" Broadcom BCM6858"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/configs/bcm96878_defconfig b/configs/bcm96878_defconfig
new file mode 100644
index 0000000..8476462
--- /dev/null
+++ b/configs/bcm96878_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM6878=y
+CONFIG_TARGET_BCM96878=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_DEFAULT_DEVICE_TREE="bcm96878"
+CONFIG_IDENT_STRING=" Broadcom BCM6878"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 220e2cb..ff87fbf 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -110,9 +110,8 @@
config BCM6345_GPIO
bool "BCM6345 GPIO driver"
- depends on DM_GPIO && (ARCH_BMIPS || ARCH_BCM68360 || \
- ARCH_BCM6858 || ARCH_BCM63158 || \
- ARCH_BCM6753)
+ depends on DM_GPIO && (ARCH_BMIPS || BCM6856 || \
+ BCM6858 || BCM63158 || BCM6855)
help
This driver supports the GPIO banks on BCM6345 SoCs.
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index ccdd7d7..996b757 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -30,14 +30,14 @@
config LED_BCM6753
bool "LED Support for BCM6753"
- depends on LED && ARCH_BCM6753
+ depends on LED && BCM6855
help
This option enables support for LEDs connected to the BCM6753
HW has blinking and fading capabilities and up to 32 LEDs can be controlled.
config LED_BCM6858
bool "LED Support for BCM6858"
- depends on LED && (ARCH_BCM68360 || ARCH_BCM6858 || ARCH_BCM63158)
+ depends on LED && (BCM6856 || BCM6858 || BCM63158)
help
This option enables support for LEDs connected to the BCM6858
HW has blinking capabilities and up to 32 LEDs can be controlled.
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index ce67d1a..d6e3eeb 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -97,13 +97,13 @@
config NAND_BRCMNAND_6753
bool "Support Broadcom NAND controller on bcm6753"
- depends on NAND_BRCMNAND && ARCH_BCM6753
+ depends on NAND_BRCMNAND && BCM6855
help
Enable support for broadcom nand driver on bcm6753.
config NAND_BRCMNAND_68360
bool "Support Broadcom NAND controller on bcm68360"
- depends on NAND_BRCMNAND && ARCH_BCM68360
+ depends on NAND_BRCMNAND && BCM6856
help
Enable support for broadcom nand driver on bcm68360.
@@ -115,13 +115,13 @@
config NAND_BRCMNAND_6858
bool "Support Broadcom NAND controller on bcm6858"
- depends on NAND_BRCMNAND && ARCH_BCM6858
+ depends on NAND_BRCMNAND && BCM6858
help
Enable support for broadcom nand driver on bcm6858.
config NAND_BRCMNAND_63158
bool "Support Broadcom NAND controller on bcm63158"
- depends on NAND_BRCMNAND && ARCH_BCM63158
+ depends on NAND_BRCMNAND && BCM63158
help
Enable support for broadcom nand driver on bcm63158.
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 2f12081..34b92ce 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -101,8 +101,7 @@
config BCM63XX_HSSPI
bool "BCM63XX HSSPI driver"
- depends on (ARCH_BMIPS || ARCH_BCM68360 || \
- ARCH_BCM6858 || ARCH_BCM63158)
+ depends on (ARCH_BMIPS || BCM6856 || BCM6858 || BCM63158)
help
Enable the BCM6328 HSSPI driver. This driver can be used to
access the SPI NOR flash on platforms embedding this Broadcom
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index fd8745f..3b2fa24 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -230,12 +230,14 @@
Select this to enable an emulated timer for sandbox. It gets
time from host os.
-config STI_TIMER
- bool "STi timer support"
+config ARM_GLOBAL_TIMER
+ bool "ARM Cortex A9 global timer support"
depends on TIMER
+ depends on ARM
default y if ARCH_STI
help
- Select this to enable a timer for STi devices.
+ Select this to enable global timer found on ARM Cortex A9
+ based devices.
config STM32_TIMER
bool "STM32 timer support"
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index 7bfb774..bc8b2c0 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -24,7 +24,7 @@
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
-obj-$(CONFIG_STI_TIMER) += sti-timer.o
+obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o
obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
obj-$(CONFIG_MTK_TIMER) += mtk_timer.o
diff --git a/drivers/timer/sti-timer.c b/drivers/timer/arm_global_timer.c
similarity index 66%
rename from drivers/timer/sti-timer.c
rename to drivers/timer/arm_global_timer.c
index 87444a0..065f10b 100644
--- a/drivers/timer/sti-timer.c
+++ b/drivers/timer/arm_global_timer.c
@@ -2,6 +2,8 @@
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
+ *
+ * ARM Cortext A9 global timer driver
*/
#include <common.h>
@@ -13,13 +15,13 @@
#include <asm/io.h>
#include <asm/arch-armv7/globaltimer.h>
-struct sti_timer_priv {
+struct arm_global_timer_priv {
struct globaltimer *global_timer;
};
-static u64 sti_timer_get_count(struct udevice *dev)
+static u64 arm_global_timer_get_count(struct udevice *dev)
{
- struct sti_timer_priv *priv = dev_get_priv(dev);
+ struct arm_global_timer_priv *priv = dev_get_priv(dev);
struct globaltimer *global_timer = priv->global_timer;
u32 low, high;
u64 timer;
@@ -37,10 +39,10 @@
return (u64)((timer << 32) | low);
}
-static int sti_timer_probe(struct udevice *dev)
+static int arm_global_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
- struct sti_timer_priv *priv = dev_get_priv(dev);
+ struct arm_global_timer_priv *priv = dev_get_priv(dev);
struct clk clk;
int err;
ulong ret;
@@ -66,20 +68,20 @@
return 0;
}
-static const struct timer_ops sti_timer_ops = {
- .get_count = sti_timer_get_count,
+static const struct timer_ops arm_global_timer_ops = {
+ .get_count = arm_global_timer_get_count,
};
-static const struct udevice_id sti_timer_ids[] = {
+static const struct udevice_id arm_global_timer_ids[] = {
{ .compatible = "arm,cortex-a9-global-timer" },
{}
};
-U_BOOT_DRIVER(sti_timer) = {
- .name = "sti_timer",
+U_BOOT_DRIVER(arm_global_timer) = {
+ .name = "arm_global_timer",
.id = UCLASS_TIMER,
- .of_match = sti_timer_ids,
- .priv_auto = sizeof(struct sti_timer_priv),
- .probe = sti_timer_probe,
- .ops = &sti_timer_ops,
+ .of_match = arm_global_timer_ids,
+ .priv_auto = sizeof(struct arm_global_timer_priv),
+ .probe = arm_global_timer_probe,
+ .ops = &arm_global_timer_ops,
};
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 29e375e..f1b1cf6 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -130,9 +130,8 @@
config WDT_BCM6345
bool "BCM6345 watchdog timer support"
- depends on WDT && (ARCH_BMIPS || ARCH_BCM68360 || \
- ARCH_BCM6858 || ARCH_BCM63158 || \
- ARCH_BCM6753)
+ depends on WDT && (ARCH_BMIPS || BCM6856 || \
+ BCM6858 || BCM63158 || BCM6855)
help
Select this to enable watchdog timer for BCM6345 SoCs.
The watchdog timer is stopped when initialized.
diff --git a/include/configs/bcm94908.h b/include/configs/bcm94908.h
new file mode 100644
index 0000000..1346ace
--- /dev/null
+++ b/include/configs/bcm94908.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM94908_H
+#define __BCM94908_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/configs/bcm94912.h b/include/configs/bcm94912.h
new file mode 100644
index 0000000..f3d17dd
--- /dev/null
+++ b/include/configs/bcm94912.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM94912_H
+#define __BCM94912_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/configs/bcm963138.h b/include/configs/bcm963138.h
new file mode 100644
index 0000000..361569a
--- /dev/null
+++ b/include/configs/bcm963138.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM963138_H
+#define __BCM963138_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_HZ_CLOCK 500000000
+
+#endif
diff --git a/include/configs/bcm963146.h b/include/configs/bcm963146.h
new file mode 100644
index 0000000..edbdfc3
--- /dev/null
+++ b/include/configs/bcm963146.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM963146_H
+#define __BCM963146_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/configs/bcm963148.h b/include/configs/bcm963148.h
new file mode 100644
index 0000000..5a24ccc
--- /dev/null
+++ b/include/configs/bcm963148.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM963148_H
+#define __BCM963148_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/configs/bcm963158.h b/include/configs/bcm963158.h
new file mode 100644
index 0000000..f473963
--- /dev/null
+++ b/include/configs/bcm963158.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM963158_H
+#define __BCM963158_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#ifdef CONFIG_MTD_RAW_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#endif /* CONFIG_MTD_RAW_NAND */
+
+#endif
diff --git a/include/configs/bcm963178.h b/include/configs/bcm963178.h
new file mode 100644
index 0000000..b25f6a1
--- /dev/null
+++ b/include/configs/bcm963178.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM963178_H
+#define __BCM963178_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/configs/bcm96756.h b/include/configs/bcm96756.h
new file mode 100644
index 0000000..c8f3267
--- /dev/null
+++ b/include/configs/bcm96756.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM96756_H
+#define __BCM96756_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/configs/bcm96813.h b/include/configs/bcm96813.h
new file mode 100644
index 0000000..5d9e87b
--- /dev/null
+++ b/include/configs/bcm96813.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM96813_H
+#define __BCM96813_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/configs/bcm96846.h b/include/configs/bcm96846.h
new file mode 100644
index 0000000..1d6d5d6
--- /dev/null
+++ b/include/configs/bcm96846.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM96846_H
+#define __BCM96846_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/configs/bcm96855.h b/include/configs/bcm96855.h
new file mode 100644
index 0000000..ba2d8a3
--- /dev/null
+++ b/include/configs/bcm96855.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM96855_H
+#define __BCM96855_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#ifdef CONFIG_MTD_RAW_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#endif /* CONFIG_MTD_RAW_NAND */
+
+#endif
diff --git a/include/configs/bcm96856.h b/include/configs/bcm96856.h
new file mode 100644
index 0000000..3050cf3
--- /dev/null
+++ b/include/configs/bcm96856.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM96856_H
+#define __BCM96856_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#ifdef CONFIG_MTD_RAW_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#endif /* CONFIG_MTD_RAW_NAND */
+
+#endif
diff --git a/include/configs/bcm96858.h b/include/configs/bcm96858.h
new file mode 100644
index 0000000..8bd1169
--- /dev/null
+++ b/include/configs/bcm96858.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM96858_H
+#define __BCM96858_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#ifdef CONFIG_MTD_RAW_NAND
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#endif /* CONFIG_MTD_RAW_NAND */
+
+#endif
diff --git a/include/configs/bcm96878.h b/include/configs/bcm96878.h
new file mode 100644
index 0000000..3e23e94
--- /dev/null
+++ b/include/configs/bcm96878.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM96878_H
+#define __BCM96878_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h
deleted file mode 100644
index 0c8d352..0000000
--- a/include/configs/broadcom_bcm963158.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2019 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <linux/sizes.h>
-
-/*
- * common
- */
-
-/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
- 230400, 500000, 1500000 }
-/* Memory usage */
-
-/*
- * 63158
- */
-
-/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* U-Boot */
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
-
-/*
- * bcm963158
- */
diff --git a/include/configs/broadcom_bcm96753ref.h b/include/configs/broadcom_bcm96753ref.h
deleted file mode 100644
index 33c70c7..0000000
--- a/include/configs/broadcom_bcm96753ref.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2022 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <linux/sizes.h>
-
-/*
- * common
- */
-
-/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
- 230400, 500000, 1500000 }
-/* Memory usage */
-
-/*
- * 6853
- */
-
-/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* U-Boot */
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
-
-/*
- * 96753ref
- */
diff --git a/include/configs/broadcom_bcm968360bg.h b/include/configs/broadcom_bcm968360bg.h
deleted file mode 100644
index 8a80235..0000000
--- a/include/configs/broadcom_bcm968360bg.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2020 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <linux/sizes.h>
-
-/*
- * common
- */
-
-/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
- 230400, 500000, 1500000 }
-/* Memory usage */
-
-/*
- * 6858
- */
-
-/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* U-Boot */
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
-
-/*
- * 968360bg
- */
diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h
deleted file mode 100644
index abc2da3..0000000
--- a/include/configs/broadcom_bcm968580xref.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
- */
-
-#include <linux/sizes.h>
-
-/*
- * common
- */
-
-/* UART */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \
- 230400, 500000, 1500000 }
-/* Memory usage */
-
-/*
- * 6858
- */
-
-/* RAM */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-/* U-Boot */
-
-#ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#endif /* CONFIG_MTD_RAW_NAND */
-
-/*
- * 968580xref
- */
diff --git a/tools/buildman/boards.py b/tools/buildman/boards.py
index cdc4d9f..0bb0723 100644
--- a/tools/buildman/boards.py
+++ b/tools/buildman/boards.py
@@ -368,6 +368,17 @@
targets.append(front)
elif tag == 'S:':
status = rest
+ elif tag == 'N:':
+ # Just scan the configs directory since that's all we care
+ # about
+ for dirpath, _, fnames in os.walk('configs'):
+ for fname in fnames:
+ path = os.path.join(dirpath, fname)
+ front, match, rear = path.partition('configs/')
+ if not front and match:
+ front, match, rear = rear.rpartition('_defconfig')
+ if match and not rear:
+ targets.append(front)
elif line == '\n':
for target in targets:
self.database[target] = (status, maintainers)