commit 405ff74b8422f18c94b010309775c99b2f61da06
author Tom Rini <trini@konsulko.com> Mon Apr 19 11:34:17 2021 -0400
committer Tom Rini <trini@konsulko.com> Mon Apr 19 11:34:17 2021 -0400
tree f417181c6497517985895c9d40d674f8911fc43a
parent 7861f8b092aca9878d7d58288713815d396dce1e
parent 8e04f4ee643c709d9ddce5d6fcb77a6568bbf8df

Merge tag 'u-boot-atmel-2021.07-b' of https://source.denx.de/u-boot/custodians/u-boot-atmel

Second set of u-boot-atmel features for 2021.07 cycle:

This small feature set include support for 5th PIO bank on pio4 pinctrl
driver and a fix for the SPL on sama5d3.

arch/arm/dts/sama5d3.dtsi

diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi
index 6ed218e..42c30e9 100644
--- a/arch/arm/dts/sama5d3.dtsi
+++ b/arch/arm/dts/sama5d3.dtsi
@@ -1320,6 +1320,7 @@
 				reg = <0xfffffe30 0xf>;
 				interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
 				clocks = <&mck>;
+				u-boot,dm-pre-reloc;
 			};
 
 			watchdog@fffffe40 {

arch/arm/dts/sama7g5.dtsi

diff --git a/arch/arm/dts/sama7g5.dtsi b/arch/arm/dts/sama7g5.dtsi
index 0cb6eaf..b951aff 100644
--- a/arch/arm/dts/sama7g5.dtsi
+++ b/arch/arm/dts/sama7g5.dtsi
@@ -63,7 +63,7 @@
 			#size-cells = <1>;
 
 			pioA: pinctrl@e0014000 {
-				compatible = "atmel,sama5d2-gpio";
+				compatible = "microchip,sama7g5-gpio";
 				reg = <0xe0014000 0x800>;
 				gpio-controller;
 				#gpio-cells = <2>;

drivers/gpio/atmel_pio4.c

diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c
index f615fce..bea609d 100644
--- a/drivers/gpio/atmel_pio4.c
+++ b/drivers/gpio/atmel_pio4.c
@@ -173,8 +173,15 @@
 
 #if CONFIG_IS_ENABLED(DM_GPIO)
 
+/**
+ * struct atmel_pioctrl_data - Atmel PIO controller (pinmux + gpio) data struct
+ * @nbanks: number of PIO banks
+ * @last_bank_count: number of lines in the last bank (can be less than
+ *     the rest of the banks).
+ */
 struct atmel_pioctrl_data {
 	u32 nbanks;
+	u32 last_bank_count;
 };
 
 struct atmel_pio4_plat {
@@ -313,6 +320,12 @@
 					  NULL);
 	uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK;
 
+	/* if last bank has limited number of pins, adjust accordingly */
+	if (pioctrl_data->last_bank_count != ATMEL_PIO_NPINS_PER_BANK) {
+		uc_priv->gpio_count -= ATMEL_PIO_NPINS_PER_BANK;
+		uc_priv->gpio_count += pioctrl_data->last_bank_count;
+	}
+
 	return 0;
 }
 
@@ -322,12 +335,21 @@
  */
 static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = {
 	.nbanks	= 4,
+	.last_bank_count = ATMEL_PIO_NPINS_PER_BANK,
 };
 
+static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
+	.nbanks	= 5,
+	.last_bank_count = 8, /* 5th bank has only 8 lines on sama7g5 */
+};
+
 static const struct udevice_id atmel_pio4_ids[] = {
 	{
 		.compatible = "atmel,sama5d2-gpio",
 		.data = (ulong)&atmel_sama5d2_pioctrl_data,
+	}, {
+		.compatible = "microchip,sama7g5-gpio",
+		.data = (ulong)&microchip_sama7g5_pioctrl_data,
 	},
 	{}
 };